1 /*
2 * Copyright (c) 2016 - 2020, Broadcom
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdlib.h>
8 #include <string.h>
9 #include <stddef.h>
10
11 #include <arch_helpers.h>
12 #include <lib/mmio.h>
13
14 #include "bcm_emmc.h"
15 #include "emmc_chal_types.h"
16 #include "emmc_csl_sdprot.h"
17 #include "emmc_chal_sd.h"
18 #include "emmc_csl_sdcmd.h"
19 #include "emmc_csl_sd.h"
20 #include "emmc_pboot_hal_memory_drv.h"
21
22 #define SD_CARD_BUSY 0x80000000
23 #define SD_CARD_RETRY_LIMIT 1000
24 #define SD_CARD_HIGH_SPEED_PS 13
25 #define SD_CHK_HIGH_SPEED_MODE 0x00FFFFF1
26 #define SD_SET_HIGH_SPEED_MODE 0x80FFFFF1
27 #define SD_MMC_ENABLE_HIGH_SPEED 0x03b90100 //0x03b90103
28 #define SD_MMC_8BIT_MODE 0x03b70200
29 #define SD_MMC_4BIT_MODE 0x03b70100
30 #define SD_MMC_1BIT_MODE 0x03b70000
31
32 #define SD_MMC_BOOT_8BIT_MODE 0x03b10200
33 #define SD_MMC_BOOT_4BIT_MODE 0x03b10100
34 #define SD_MMC_BOOT_1BIT_MODE 0x03b10000
35 #define SDIO_HW_EMMC_EXT_CSD_BOOT_CNF 0X03B30000
36
37 #ifdef USE_EMMC_FIP_TOC_CACHE
38 /*
39 * Cache size mirrors the size of the global eMMC temp buffer
40 * which is used for non-image body reads such as headers, ToC etc.
41 */
42 #define CACHE_SIZE ((EMMC_BLOCK_SIZE) * 2)
43 #define PARTITION_BLOCK_ADDR ((PLAT_FIP_ATTEMPT_OFFSET)/(EMMC_BLOCK_SIZE))
44
45 static uint32_t cached_partition_block;
46 static uint8_t cached_block[CACHE_SIZE];
47 #endif
48
49 static int set_card_data_width(struct sd_handle *handle, int width);
50 static int abort_err(struct sd_handle *handle);
51 static int err_recovery(struct sd_handle *handle, uint32_t errors);
52 static int xfer_data(struct sd_handle *handle, uint32_t mode, uint32_t addr,
53 uint32_t length, uint8_t *base);
54
set_boot_config(struct sd_handle * handle,uint32_t config)55 int set_boot_config(struct sd_handle *handle, uint32_t config)
56 {
57 return mmc_cmd6(handle, SDIO_HW_EMMC_EXT_CSD_BOOT_CNF | config);
58 }
59
process_csd_mmc_speed(struct sd_handle * handle,uint32_t csd_mmc_speed)60 void process_csd_mmc_speed(struct sd_handle *handle, uint32_t csd_mmc_speed)
61 {
62 uint32_t div_ctrl_setting;
63
64 /* CSD field TRAN_SPEED:
65 * Bits [2:0] 0 = 100 KHz
66 * 1 = 1 MHz
67 * 2 = 10 MHz
68 * 3 = 100 MHz
69 * 4...7 Reserved.
70 * Bits [6:3] 0 = Reserved
71 * 1 = 1.0
72 * 2 = 1.2
73 * 3 = 1.3
74 * 4 = 1.5
75 * 5 = 2.0
76 * 6 = 2.6
77 * 7 = 3.0
78 * 8 = 3.5
79 * 9 = 4.0
80 * A = 4.5
81 * B = 5.2
82 * C = 5.5
83 * D = 6.0
84 * E = 7.0
85 * F = 8.0
86 * For cards supporting version 4.0, 4.1, and 4.2 of the standard,
87 * the value shall be 20 MHz (0x2A).
88 * For cards supporting version 4.3 , the value shall be 26 MHz (0x32)
89 */
90
91 switch (csd_mmc_speed & 0x7F) {
92 case 0x2A:
93 EMMC_TRACE("Speeding up eMMC clock to 20MHz\n");
94 div_ctrl_setting =
95 chal_sd_freq_2_div_ctrl_setting(20 * 1000 * 1000);
96 break;
97 case 0x32:
98 EMMC_TRACE("Speeding up eMMC clock to 26MHz\n");
99 div_ctrl_setting =
100 chal_sd_freq_2_div_ctrl_setting(26 * 1000 * 1000);
101 break;
102 default:
103 /* Unknown */
104 return;
105 }
106
107 chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 0);
108
109 chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 1);
110
111 SD_US_DELAY(1000);
112 }
113
114
115 /*
116 * The function changes SD/SDIO/MMC card data width if
117 * the card support configurable data width. The host controller
118 * and the card has to be in the same bus data width.
119 */
set_card_data_width(struct sd_handle * handle,int width)120 int set_card_data_width(struct sd_handle *handle, int width)
121 {
122 uint32_t data_width = 0;
123 int is_valid_arg = 1;
124 int rc = SD_FAIL;
125 char *bitwidth_str = " ";
126 char *result_str = "failed";
127
128 switch (width) {
129 #ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
130 case SD_BUS_DATA_WIDTH_8BIT:
131 data_width = SD_MMC_8BIT_MODE;
132 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
133 bitwidth_str = "8_BIT";
134 #endif
135 break;
136 #endif
137 case SD_BUS_DATA_WIDTH_4BIT:
138 data_width = SD_MMC_4BIT_MODE;
139 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
140 bitwidth_str = "4_BIT";
141 #endif
142 break;
143
144 case SD_BUS_DATA_WIDTH_1BIT:
145 data_width = SD_MMC_1BIT_MODE;
146 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
147 bitwidth_str = "1_BIT";
148 #endif
149 break;
150
151 default:
152 is_valid_arg = 0;
153 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
154 bitwidth_str = "unknown";
155 #endif
156 break;
157 }
158
159 if (is_valid_arg) {
160 rc = mmc_cmd6(handle, data_width);
161 if (rc == SD_OK) {
162 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
163 result_str = "succeeded";
164 #endif
165 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
166 width);
167 } else {
168 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
169 result_str = "failed";
170 #endif
171 }
172 } else {
173 rc = SD_FAIL;
174 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
175 result_str = "ignored";
176 #endif
177 }
178
179 VERBOSE("SDIO Data Width(%s) %s.\n", bitwidth_str, result_str);
180
181 return rc;
182 }
183
184
185 /*
186 * Error handling routine. Does abort data
187 * transmission if error is found.
188 */
abort_err(struct sd_handle * handle)189 static int abort_err(struct sd_handle *handle)
190 {
191 uint32_t present, options, event, rel = 0;
192 struct sd_resp cmdRsp;
193
194 handle->device->ctrl.argReg = 0;
195 handle->device->ctrl.cmdIndex = SD_CMD_STOP_TRANSMISSION;
196
197 options = (SD_CMD_STOP_TRANSMISSION << 24) |
198 (SD_CMDR_RSP_TYPE_R1b_5b << SD_CMDR_RSP_TYPE_S) |
199 SD4_EMMC_TOP_CMD_CRC_EN_MASK |
200 SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
201
202 chal_sd_send_cmd((CHAL_HANDLE *) handle->device,
203 handle->device->ctrl.cmdIndex,
204 handle->device->ctrl.argReg, options);
205
206 event = wait_for_event(handle,
207 SD4_EMMC_TOP_INTR_CMDDONE_MASK |
208 SD_ERR_INTERRUPTS,
209 handle->device->cfg.wfe_retry);
210
211 if (event & SD_CMD_ERROR_INT) {
212 rel = SD_ERROR_NON_RECOVERABLE;
213 } else {
214 if (event & SD_DAT_TIMEOUT) {
215 return SD_ERROR_NON_RECOVERABLE;
216 }
217
218 chal_sd_get_response((CHAL_HANDLE *) handle->device,
219 (uint32_t *)&cmdRsp);
220
221 process_cmd_response(handle, handle->device->ctrl.cmdIndex,
222 cmdRsp.data.r2.rsp1, cmdRsp.data.r2.rsp2,
223 cmdRsp.data.r2.rsp3, cmdRsp.data.r2.rsp4,
224 &cmdRsp);
225
226 SD_US_DELAY(2000);
227
228 present =
229 chal_sd_get_present_status((CHAL_HANDLE *) handle->device);
230
231 if ((present & 0x00F00000) == 0x00F00000)
232 rel = SD_ERROR_RECOVERABLE;
233 else
234 rel = SD_ERROR_NON_RECOVERABLE;
235 }
236
237 return rel;
238 }
239
240
241 /*
242 * The function handles real data transmission on both DMA and
243 * none DMA mode, In None DMA mode the data transfer starts
244 * when the command is sent to the card, data has to be written
245 * into the host contollers buffer at this time one block
246 * at a time.
247 * In DMA mode, the real data transfer is done by the DMA engine
248 * and this functions just waits for the data transfer to complete.
249 *
250 */
process_data_xfer(struct sd_handle * handle,uint8_t * buffer,uint32_t addr,uint32_t length,int dir)251 int process_data_xfer(struct sd_handle *handle, uint8_t *buffer, uint32_t addr,
252 uint32_t length, int dir)
253 {
254 if (dir == SD_XFER_HOST_TO_CARD) {
255 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
256 if (handle->device->cfg.dma == SD_DMA_OFF) {
257 /*
258 * In NON DMA mode, the real data xfer starts from here
259 */
260 if (write_buffer(handle, length, buffer))
261 return SD_WRITE_ERROR;
262 } else {
263 wait_for_event(handle,
264 SD4_EMMC_TOP_INTR_TXDONE_MASK |
265 SD_ERR_INTERRUPTS,
266 handle->device->cfg.wfe_retry);
267
268 if (handle->device->ctrl.cmdStatus == SD_OK)
269 return SD_OK;
270
271 check_error(handle, handle->device->ctrl.cmdStatus);
272 return SD_WRITE_ERROR;
273 }
274 #else
275 return SD_WRITE_ERROR;
276 #endif
277 } else { /* SD_XFER_CARD_TO_HOST */
278
279 if (handle->device->cfg.dma == SD_DMA_OFF) {
280 /* In NON DMA mode, the real data
281 * transfer starts from here
282 */
283 if (read_buffer(handle, length, buffer))
284 return SD_READ_ERROR;
285
286 } else { /* for DMA mode */
287
288 /*
289 * once the data transmission is done
290 * copy data to the host buffer.
291 */
292 wait_for_event(handle,
293 SD4_EMMC_TOP_INTR_TXDONE_MASK |
294 SD_ERR_INTERRUPTS,
295 handle->device->cfg.wfe_retry);
296
297 if (handle->device->ctrl.cmdStatus == SD_OK)
298 return SD_OK;
299
300 check_error(handle, handle->device->ctrl.cmdStatus);
301 return SD_READ_ERROR;
302 }
303 }
304 return SD_OK;
305 }
306
307
308 /*
309 * The function sets block size for the next SD/SDIO/MMC
310 * card read/write command.
311 */
select_blk_sz(struct sd_handle * handle,uint16_t size)312 int select_blk_sz(struct sd_handle *handle, uint16_t size)
313 {
314 return sd_cmd16(handle, size);
315 }
316
317
318 /*
319 * The function initalizes the SD/SDIO/MMC/CEATA and detects
320 * the card according to the flag of detection.
321 * Once this function is called, the card is put into ready state
322 * so application can do data transfer to and from the card.
323 */
init_card(struct sd_handle * handle,int detection)324 int init_card(struct sd_handle *handle, int detection)
325 {
326 /*
327 * After Reset, eMMC comes up in 1 Bit Data Width by default.
328 * Set host side to match.
329 */
330 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
331 SD_BUS_DATA_WIDTH_1BIT);
332
333 #ifdef USE_EMMC_FIP_TOC_CACHE
334 cached_partition_block = 0;
335 #endif
336 handle->device->ctrl.present = 0; /* init card present to be no card */
337
338 init_mmc_card(handle);
339
340 handle->device->ctrl.present = 1; /* card is detected */
341
342 /* switch the data width back */
343 if (handle->card->type != SD_CARD_MMC)
344 return SD_FAIL;
345
346 /*
347 * Dynamically set Data Width to highest supported value.
348 * Try different data width settings (highest to lowest).
349 * Verify each setting by reading EXT_CSD and comparing
350 * against the EXT_CSD contents previously read in call to
351 * init_mmc_card() earlier. Stop at first verified data width
352 * setting.
353 */
354 {
355 #define EXT_CSD_PROPERTIES_SECTION_START_INDEX 192
356 #define EXT_CSD_PROPERTIES_SECTION_END_INDEX 511
357 uint8_t buffer[EXT_CSD_SIZE];
358 #ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
359 /* Try 8 Bit Data Width */
360 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
361 SD_BUS_DATA_WIDTH_8BIT);
362 if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_8BIT)) &&
363 (!mmc_cmd8(handle, buffer)) &&
364 (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
365 &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
366 EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
367
368 return SD_OK;
369 #endif
370 /* Fall back to 4 Bit Data Width */
371 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
372 SD_BUS_DATA_WIDTH_4BIT);
373 if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_4BIT)) &&
374 (!mmc_cmd8(handle, buffer)) &&
375 (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
376 &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
377 EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
378
379 return SD_OK;
380
381 /* Fall back to 1 Bit Data Width */
382 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
383 SD_BUS_DATA_WIDTH_1BIT);
384 /* Just use 1 Bit Data Width then. */
385 if (!set_card_data_width(handle, SD_BUS_DATA_WIDTH_1BIT))
386 return SD_OK;
387
388 }
389 return SD_CARD_INIT_ERROR;
390 }
391
392
393 /*
394 * The function handles MMC/CEATA card initalization.
395 */
init_mmc_card(struct sd_handle * handle)396 int init_mmc_card(struct sd_handle *handle)
397 {
398 uint32_t ocr = 0, newOcr, rc, limit = 0;
399 uint32_t cmd1_option = 0x40300000;
400 uint32_t sec_count;
401
402 handle->card->type = SD_CARD_MMC;
403
404 do {
405 SD_US_DELAY(1000);
406 newOcr = 0;
407 ocr = 0;
408 rc = sd_cmd1(handle, cmd1_option, &newOcr);
409 limit++;
410
411 if (rc == SD_OK)
412 ocr = newOcr;
413
414 } while (((ocr & SD_CARD_BUSY) == 0) && (limit < SD_CARD_RETRY_LIMIT));
415
416 if (limit >= SD_CARD_RETRY_LIMIT) {
417 handle->card->type = SD_CARD_UNKNOWN;
418 EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
419 return SD_CARD_UNKNOWN;
420 }
421
422 /* Save the ocr register */
423 handle->device->ctrl.ocr = ocr;
424
425 /* Ready State */
426 rc = sd_cmd2(handle);
427 if (rc != SD_OK) {
428 handle->card->type = SD_CARD_UNKNOWN;
429 return SD_CARD_UNKNOWN;
430 }
431
432 rc = sd_cmd3(handle);
433 if (rc != SD_OK) {
434 handle->card->type = SD_CARD_UNKNOWN;
435 return SD_CARD_UNKNOWN;
436 }
437 /* read CSD */
438 rc = sd_cmd9(handle, &emmc_global_vars_ptr->cardData);
439 if (rc != SD_OK) {
440 handle->card->type = SD_CARD_UNKNOWN;
441 return SD_CARD_UNKNOWN;
442 }
443
444 /* Increase clock frequency according to what the card advertises */
445 EMMC_TRACE("From CSD... cardData.csd.mmc.speed = 0x%X\n",
446 emmc_global_vars_ptr->cardData.csd.mmc.speed);
447 process_csd_mmc_speed(handle,
448 emmc_global_vars_ptr->cardData.csd.mmc.speed);
449
450 /* goto transfer mode */
451 rc = sd_cmd7(handle, handle->device->ctrl.rca);
452 if (rc != SD_OK) {
453 handle->card->type = SD_CARD_UNKNOWN;
454 return SD_CARD_UNKNOWN;
455 }
456
457 rc = mmc_cmd8(handle, emmc_global_buf_ptr->u.Ext_CSD_storage);
458 if (rc == SD_OK) {
459 /* calcul real capacity */
460 sec_count = emmc_global_buf_ptr->u.Ext_CSD_storage[212] |
461 emmc_global_buf_ptr->u.Ext_CSD_storage[213] << 8 |
462 emmc_global_buf_ptr->u.Ext_CSD_storage[214] << 16 |
463 emmc_global_buf_ptr->u.Ext_CSD_storage[215] << 24;
464
465 EMMC_TRACE("Device density = %ldMBytes\n",
466 handle->card->size / (1024 * 1024));
467
468 if (sec_count > 0) {
469 handle->card->size = (uint64_t)sec_count * 512;
470
471 EMMC_TRACE("Updated Device density = %ldMBytes\n",
472 handle->card->size / (1024 * 1024));
473 }
474
475 if (sec_count > (2u * 1024 * 1024 * 1024) / 512) {
476 handle->device->ctrl.ocr |= SD_CARD_HIGH_CAPACITY;
477 handle->device->cfg.blockSize = 512;
478 }
479
480 if (handle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
481 EMMC_TRACE("Sector addressing\n");
482 else
483 EMMC_TRACE("Byte addressing\n");
484
485 EMMC_TRACE("Ext_CSD_storage[162]: 0x%02X Ext_CSD_storage[179]: 0x%02X\n",
486 emmc_global_buf_ptr->u.Ext_CSD_storage[162],
487 emmc_global_buf_ptr->u.Ext_CSD_storage[179]);
488 }
489
490 return handle->card->type;
491 }
492
493
494 /*
495 * The function send reset command to the card.
496 * The card will be in ready status after the reset.
497 */
reset_card(struct sd_handle * handle)498 int reset_card(struct sd_handle *handle)
499 {
500 int res = SD_OK;
501
502 /* on reset, card's RCA should return to 0 */
503 handle->device->ctrl.rca = 0;
504
505 res = sd_cmd0(handle);
506
507 if (res != SD_OK)
508 return SD_RESET_ERROR;
509
510 return res;
511 }
512
513
514 /*
515 * The function sends command to the card and starts
516 * data transmission.
517 */
xfer_data(struct sd_handle * handle,uint32_t mode,uint32_t addr,uint32_t length,uint8_t * base)518 static int xfer_data(struct sd_handle *handle,
519 uint32_t mode,
520 uint32_t addr, uint32_t length, uint8_t *base)
521 {
522 int rc = SD_OK;
523
524 VERBOSE("XFER: dest: 0x%llx, addr: 0x%x, size: 0x%x bytes\n",
525 (uint64_t)base, addr, length);
526
527 if ((length / handle->device->cfg.blockSize) > 1) {
528 if (mode == SD_OP_READ) {
529 inv_dcache_range((uintptr_t)base, (uint64_t)length);
530 rc = sd_cmd18(handle, addr, length, base);
531 } else {
532 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
533 flush_dcache_range((uintptr_t)base, (uint64_t)length);
534 rc = sd_cmd25(handle, addr, length, base);
535 #else
536 rc = SD_DATA_XFER_ERROR;
537 #endif
538 }
539 } else {
540 if (mode == SD_OP_READ) {
541 inv_dcache_range((uintptr_t)base, (uint64_t)length);
542 rc = sd_cmd17(handle, addr,
543 handle->device->cfg.blockSize, base);
544 } else {
545 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
546 flush_dcache_range((uintptr_t)base, (uint64_t)length);
547 rc = sd_cmd24(handle, addr,
548 handle->device->cfg.blockSize, base);
549 #else
550 rc = SD_DATA_XFER_ERROR;
551 #endif
552 }
553 }
554
555 if (rc != SD_OK)
556 return SD_DATA_XFER_ERROR;
557
558 return SD_OK;
559 }
560
561 #ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
erase_card(struct sd_handle * handle,uint32_t addr,uint32_t blocks)562 int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks)
563 {
564 uint32_t end_addr;
565
566 INFO("ERASE: addr: 0x%x, num of sectors: 0x%x\n", addr, blocks);
567
568 if (sd_cmd35(handle, addr) != SD_OK)
569 return SD_FAIL;
570
571 end_addr = addr + blocks - 1;
572 if (sd_cmd36(handle, end_addr) != SD_OK)
573 return SD_FAIL;
574
575 if (sd_cmd38(handle) != SD_OK)
576 return SD_FAIL;
577
578 return SD_OK;
579 }
580 #endif
581
582 /*
583 * The function reads block data from a card.
584 */
585 #ifdef USE_EMMC_FIP_TOC_CACHE
read_block(struct sd_handle * handle,uint8_t * dst,uint32_t addr,uint32_t len)586 int read_block(struct sd_handle *handle,
587 uint8_t *dst, uint32_t addr, uint32_t len)
588 {
589 int rel = SD_OK;
590
591 /*
592 * Avoid doing repeated reads of the partition block
593 * by caching.
594 */
595 if (cached_partition_block &&
596 addr == PARTITION_BLOCK_ADDR &&
597 len == CACHE_SIZE) {
598 memcpy(dst, cached_block, len);
599 } else {
600 rel = xfer_data(handle, SD_OP_READ, addr, len, dst);
601
602 if (len == CACHE_SIZE && addr == PARTITION_BLOCK_ADDR) {
603 cached_partition_block = 1;
604 memcpy(cached_block, dst, len);
605 }
606 }
607
608 return rel;
609 }
610 #else
read_block(struct sd_handle * handle,uint8_t * dst,uint32_t addr,uint32_t len)611 int read_block(struct sd_handle *handle,
612 uint8_t *dst, uint32_t addr, uint32_t len)
613 {
614 return xfer_data(handle, SD_OP_READ, addr, len, dst);
615 }
616 #endif
617
618 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
619
620 /*
621 * The function writes block data to a card.
622 */
write_block(struct sd_handle * handle,uint8_t * src,uint32_t addr,uint32_t len)623 int write_block(struct sd_handle *handle,
624 uint8_t *src, uint32_t addr, uint32_t len)
625 {
626 int rel = SD_OK;
627
628 /*
629 * Current HC has problem to get response of cmd16 after cmd12,
630 * the delay is necessary to sure the next cmd16 will not be timed out.
631 * The delay has to be at least 4 ms.
632 * The code removed cmd16 and use cmd13 to get card status before
633 * sending cmd18 or cmd25 to make sure the card is ready and thus
634 * no need to have delay here.
635 */
636
637 rel = xfer_data(handle, SD_OP_WRITE, addr, len, src);
638
639 EMMC_TRACE("wr_blk addr:0x%08X src:0x%08X len:0x%08X result:%d\n",
640 addr, src, len, rel);
641
642 return rel;
643 }
644
645
646 /*
647 * The function is called to write one block data directly to
648 * a card's data buffer.
649 * it is used in Non-DMA mode for card data transmission.
650 */
write_buffer(struct sd_handle * handle,uint32_t length,uint8_t * data)651 int write_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
652 {
653 uint32_t rem, blockSize, event;
654 uint8_t *pData = data;
655
656 blockSize = handle->device->cfg.blockSize;
657 rem = length;
658
659 if (rem == 0)
660 return SD_OK;
661
662 while (rem > 0) {
663
664 event = wait_for_event(handle,
665 SD4_EMMC_TOP_INTR_BWRDY_MASK |
666 SD_ERR_INTERRUPTS,
667 handle->device->cfg.wfe_retry);
668
669 if (handle->device->ctrl.cmdStatus) {
670 check_error(handle, handle->device->ctrl.cmdStatus);
671 return SD_WRITE_ERROR;
672 }
673
674 if (rem >= blockSize)
675 chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
676 blockSize, pData);
677 else
678 chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
679 rem, pData);
680
681 if (rem > blockSize) {
682 rem -= blockSize;
683 pData += blockSize;
684 } else {
685 pData += rem;
686 rem = 0;
687 }
688 }
689
690 if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
691 SD4_EMMC_TOP_INTR_TXDONE_MASK) {
692 event = wait_for_event(handle,
693 SD4_EMMC_TOP_INTR_TXDONE_MASK |
694 SD_ERR_INTERRUPTS,
695 handle->device->cfg.wfe_retry);
696
697 if (handle->device->ctrl.cmdStatus != SD_OK) {
698 check_error(handle, handle->device->ctrl.cmdStatus);
699 return SD_WRITE_ERROR;
700 }
701 } else {
702 handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
703 }
704
705 return SD_OK;
706 }
707 #endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */
708
709
710 /*
711 * The function is called to read maximal one block data
712 * directly from a card
713 * It is used in Non-DMA mode for card data transmission.
714 */
read_buffer(struct sd_handle * handle,uint32_t length,uint8_t * data)715 int read_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
716 {
717 uint32_t rem, blockSize, event = 0;
718 uint8_t *pData = data;
719
720 blockSize = handle->device->cfg.blockSize;
721 rem = length;
722
723 if (rem == 0)
724 return SD_OK;
725
726 while (rem > 0) {
727 event = wait_for_event(handle,
728 SD4_EMMC_TOP_INTR_BRRDY_MASK |
729 SD_ERR_INTERRUPTS,
730 handle->device->cfg.wfe_retry);
731
732 if (handle->device->ctrl.cmdStatus) {
733 check_error(handle, handle->device->ctrl.cmdStatus);
734 return SD_READ_ERROR;
735 }
736
737 if (rem >= blockSize)
738 chal_sd_read_buffer((CHAL_HANDLE *) handle->device,
739 blockSize, pData);
740 else
741 chal_sd_read_buffer((CHAL_HANDLE *) handle->device, rem,
742 pData);
743
744 if (rem > blockSize) {
745 rem -= blockSize;
746 pData += blockSize;
747 } else {
748 pData += rem;
749 rem = 0;
750 }
751 }
752
753 /* In case, there are extra data in the SD FIFO, just dump them. */
754 chal_sd_dump_fifo((CHAL_HANDLE *) handle->device);
755
756 if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
757 SD4_EMMC_TOP_INTR_TXDONE_MASK) {
758 event = wait_for_event(handle, SD4_EMMC_TOP_INTR_TXDONE_MASK,
759 handle->device->cfg.wfe_retry);
760
761 if (handle->device->ctrl.cmdStatus) {
762 check_error(handle, handle->device->ctrl.cmdStatus);
763 return SD_READ_ERROR;
764 }
765 } else {
766 handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
767 }
768
769 return SD_OK;
770 }
771
772
773 /*
774 * Error handling routine.
775 * The function just reset the DAT
776 * and CMD line if an error occures during data transmission.
777 */
check_error(struct sd_handle * handle,uint32_t ints)778 int check_error(struct sd_handle *handle, uint32_t ints)
779 {
780 uint32_t rel;
781
782 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
783 SD_ERR_INTERRUPTS, 0);
784
785 if (ints & SD4_EMMC_TOP_INTR_CMDERROR_MASK) {
786
787 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
788 SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
789 rel = abort_err(handle);
790
791 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
792 SD4_EMMC_TOP_CTRL1_DATRST_MASK);
793 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
794 SD_ERR_INTERRUPTS, 1);
795
796 return (rel == SD_ERROR_NON_RECOVERABLE) ?
797 SD_ERROR_NON_RECOVERABLE : SD_ERROR_RECOVERABLE;
798 } else {
799 rel = err_recovery(handle, ints);
800 }
801
802 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
803 SD_ERR_INTERRUPTS, 1);
804
805 return rel;
806 }
807
808
809 /*
810 * Error recovery routine.
811 * Try to recover from the error.
812 */
err_recovery(struct sd_handle * handle,uint32_t errors)813 static int err_recovery(struct sd_handle *handle, uint32_t errors)
814 {
815 uint32_t rel = 0;
816
817 /*
818 * In case of timeout error, the cmd line and data line maybe
819 * still active or stuck at atcitve so it is needed to reset
820 * either data line or cmd line to make sure a new cmd can be sent.
821 */
822
823 if (errors & SD_CMD_ERROR_INT)
824 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
825 SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
826
827 if (errors & SD_DAT_ERROR_INT)
828 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
829 SD4_EMMC_TOP_CTRL1_DATRST_MASK);
830
831 /* Abort transaction by sending out stop command */
832 if ((handle->device->ctrl.cmdIndex == 18) ||
833 (handle->device->ctrl.cmdIndex == 25))
834 rel = abort_err(handle);
835
836 return rel;
837 }
838
839
840 /*
841 * The function is called to read one block data directly from a card.
842 * It is used in Non-DMA mode for card data transmission.
843 */
process_cmd_response(struct sd_handle * handle,uint32_t cmdIndex,uint32_t rsp0,uint32_t rsp1,uint32_t rsp2,uint32_t rsp3,struct sd_resp * resp)844 int process_cmd_response(struct sd_handle *handle,
845 uint32_t cmdIndex,
846 uint32_t rsp0,
847 uint32_t rsp1,
848 uint32_t rsp2, uint32_t rsp3, struct sd_resp *resp)
849 {
850 int result = SD_OK;
851
852 /* R6 */
853 uint32_t rca = (rsp0 >> 16) & 0xffff;
854 uint32_t cardStatus = rsp0;
855
856 /* R4 */
857 uint32_t cBit = (rsp0 >> 31) & 0x1;
858 uint32_t funcs = (rsp0 >> 28) & 0x7;
859 uint32_t memPresent = (rsp0 >> 27) & 0x1;
860
861 resp->r1 = 0x3f;
862 resp->cardStatus = cardStatus;
863
864 if (cmdIndex == SD_CMD_IO_SEND_OP_COND) {
865 resp->data.r4.cardReady = cBit;
866 resp->data.r4.funcs = funcs;
867 resp->data.r4.memPresent = memPresent;
868 resp->data.r4.ocr = cardStatus;
869 }
870
871 if (cmdIndex == SD_CMD_MMC_SET_RCA) {
872 resp->data.r6.rca = rca;
873 resp->data.r6.cardStatus = cardStatus & 0xFFFF;
874 }
875
876 if (cmdIndex == SD_CMD_SELECT_DESELECT_CARD) {
877 resp->data.r7.rca = rca;
878 }
879
880 if (cmdIndex == SD_CMD_IO_RW_DIRECT) {
881 if (((rsp0 >> 16) & 0xffff) != 0)
882 result = SD_CMD_ERR_INVALID_RESPONSE;
883
884 resp->data.r5.data = rsp0 & 0xff;
885 }
886
887 if (cmdIndex == SD_CMD_IO_RW_EXTENDED) {
888 if (((rsp0 >> 16) & 0xffff) != 0)
889 result = SD_CMD_ERR_INVALID_RESPONSE;
890
891 resp->data.r5.data = rsp0 & 0xff;
892 }
893
894 if (cmdIndex == SD_ACMD_SD_SEND_OP_COND ||
895 cmdIndex == SD_CMD_SEND_OPCOND)
896 resp->data.r3.ocr = cardStatus;
897
898 if (cmdIndex == SD_CMD_SEND_CSD ||
899 cmdIndex == SD_CMD_SEND_CID ||
900 cmdIndex == SD_CMD_ALL_SEND_CID) {
901 resp->data.r2.rsp4 = rsp3;
902 resp->data.r2.rsp3 = rsp2;
903 resp->data.r2.rsp2 = rsp1;
904 resp->data.r2.rsp1 = rsp0;
905 }
906
907 if ((cmdIndex == SD_CMD_READ_EXT_CSD) &&
908 (handle->card->type == SD_CARD_SD)) {
909 if ((resp->cardStatus & 0xAA) != 0xAA) {
910 result = SD_CMD_ERR_INVALID_RESPONSE;
911 }
912 }
913
914 return result;
915 }
916
917
918 /*
919 * The function sets DMA buffer and data length, process
920 * block size and the number of blocks to be transferred.
921 * It returns the DMA buffer address.
922 * It copies dma data from user buffer to the DMA buffer
923 * if the operation is to write data to the SD card.
924 */
data_xfer_setup(struct sd_handle * handle,uint8_t * data,uint32_t length,int dir)925 void data_xfer_setup(struct sd_handle *handle, uint8_t *data, uint32_t length,
926 int dir)
927 {
928 chal_sd_setup_xfer((CHAL_HANDLE *)handle->device, data, length, dir);
929 }
930
931
932 /*
933 * The function does soft reset the host SD controller. After
934 * the function call all host controller's register are reset
935 * to default vallue;
936 *
937 * Note This function only resets the host controller it does not
938 * reset the controller's handler.
939 */
reset_host_ctrl(struct sd_handle * handle)940 int reset_host_ctrl(struct sd_handle *handle)
941 {
942 chal_sd_stop();
943
944 return SD_OK;
945 }
946
pstate_log(struct sd_handle * handle)947 static void pstate_log(struct sd_handle *handle)
948 {
949 ERROR("PSTATE: 0x%x\n", mmio_read_32
950 (handle->device->ctrl.sdRegBaseAddr +
951 SD4_EMMC_TOP_PSTATE_SD4_OFFSET));
952 ERROR("ERRSTAT: 0x%x\n", mmio_read_32
953 (handle->device->ctrl.sdRegBaseAddr +
954 SD4_EMMC_TOP_ERRSTAT_OFFSET));
955 }
956
957 /*
958 * The function waits for one or a group of interrupts specified
959 * by mask. The function returns if any one the interrupt status
960 * is set. If interrupt mode is not enabled then it will poll
961 * the interrupt status register until a interrupt status is set
962 * an error interrupt happens. If interrupt mode is enabled then
963 * this function should be called after the interrupt
964 * is received by ISR routine.
965 */
wait_for_event(struct sd_handle * handle,uint32_t mask,uint32_t retry)966 uint32_t wait_for_event(struct sd_handle *handle,
967 uint32_t mask, uint32_t retry)
968 {
969 uint32_t regval, cmd12, time = 0;
970
971 handle->device->ctrl.cmdStatus = 0; /* no error */
972 EMMC_TRACE("%s %d mask:0x%x timeout:%d irq_status:0x%x\n",
973 __func__, __LINE__, mask, retry,
974 chal_sd_get_irq_status((CHAL_HANDLE *)handle->device));
975
976 /* Polling mode */
977 do {
978 regval = chal_sd_get_irq_status((CHAL_HANDLE *)handle->device);
979
980 if (regval & SD4_EMMC_TOP_INTR_DMAIRQ_MASK) {
981 chal_sd_set_dma_addr((CHAL_HANDLE *)handle->device,
982 (uintptr_t)
983 chal_sd_get_dma_addr((CHAL_HANDLE *)
984 handle->device));
985 chal_sd_clear_irq((CHAL_HANDLE *)handle->device,
986 SD4_EMMC_TOP_INTR_DMAIRQ_MASK);
987 }
988
989 if (time++ > retry) {
990 ERROR("EMMC: No response (cmd%d) after %dus.\n",
991 handle->device->ctrl.cmdIndex,
992 time * EMMC_WFE_RETRY_DELAY_US);
993 handle->device->ctrl.cmdStatus = SD_CMD_MISSING;
994 pstate_log(handle);
995 ERROR("EMMC: INT[0x%x]\n", regval);
996 break;
997 }
998
999 if (regval & SD4_EMMC_TOP_INTR_CTOERR_MASK) {
1000 ERROR("EMMC: Cmd%d timeout INT[0x%x]\n",
1001 handle->device->ctrl.cmdIndex, regval);
1002 handle->device->ctrl.cmdStatus =
1003 SD4_EMMC_TOP_INTR_CTOERR_MASK;
1004 pstate_log(handle);
1005 break;
1006 }
1007 if (regval & SD_CMD_ERROR_FLAGS) {
1008 ERROR("EMMC: Cmd%d error INT[0x%x]\n",
1009 handle->device->ctrl.cmdIndex, regval);
1010 handle->device->ctrl.cmdStatus = SD_CMD_ERROR_FLAGS;
1011 pstate_log(handle);
1012 break;
1013 }
1014
1015 cmd12 = chal_sd_get_atuo12_error((CHAL_HANDLE *)handle->device);
1016 if (cmd12) {
1017 ERROR("EMMC: Cmd%d auto cmd12 err:0x%x\n",
1018 handle->device->ctrl.cmdIndex, cmd12);
1019 handle->device->ctrl.cmdStatus = cmd12;
1020 pstate_log(handle);
1021 break;
1022 }
1023
1024 if (SD_DATA_ERROR_FLAGS & regval) {
1025 ERROR("EMMC: Data for cmd%d error, INT[0x%x]\n",
1026 handle->device->ctrl.cmdIndex, regval);
1027 handle->device->ctrl.cmdStatus =
1028 (SD_DATA_ERROR_FLAGS & regval);
1029 pstate_log(handle);
1030 break;
1031 }
1032
1033 if ((regval & mask) == 0)
1034 udelay(EMMC_WFE_RETRY_DELAY_US);
1035
1036 } while ((regval & mask) == 0);
1037
1038 /* clear the interrupt since it is processed */
1039 chal_sd_clear_irq((CHAL_HANDLE *)handle->device, (regval & mask));
1040
1041 return (regval & mask);
1042 }
1043
set_config(struct sd_handle * handle,uint32_t speed,uint32_t retry,uint32_t dma,uint32_t dmaBound,uint32_t blkSize,uint32_t wfe_retry)1044 int32_t set_config(struct sd_handle *handle, uint32_t speed, uint32_t retry,
1045 uint32_t dma, uint32_t dmaBound, uint32_t blkSize,
1046 uint32_t wfe_retry)
1047 {
1048 int32_t rel = 0;
1049
1050 if (handle == NULL)
1051 return SD_FAIL;
1052
1053 handle->device->cfg.wfe_retry = wfe_retry;
1054
1055 rel = chal_sd_config((CHAL_HANDLE *)handle->device, speed, retry,
1056 dmaBound, blkSize, dma);
1057 return rel;
1058
1059 }
1060
mmc_cmd1(struct sd_handle * handle)1061 int mmc_cmd1(struct sd_handle *handle)
1062 {
1063 uint32_t newOcr, res;
1064 uint32_t cmd1_option = MMC_OCR_OP_VOLT | MMC_OCR_SECTOR_ACCESS_MODE;
1065
1066 /*
1067 * After Reset, eMMC comes up in 1 Bit Data Width by default.
1068 * Set host side to match.
1069 */
1070 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
1071 SD_BUS_DATA_WIDTH_1BIT);
1072
1073 #ifdef USE_EMMC_FIP_TOC_CACHE
1074 cached_partition_block = 0;
1075 #endif
1076 handle->device->ctrl.present = 0; /* init card present to be no card */
1077
1078 handle->card->type = SD_CARD_MMC;
1079
1080 res = sd_cmd1(handle, cmd1_option, &newOcr);
1081
1082 if (res != SD_OK) {
1083 EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
1084 res = SD_CARD_UNKNOWN;
1085 }
1086 return res;
1087 }
1088