1 /*
2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "util/u_dump.h"
29 #include "util/half_float.h"
30
31 #include "freedreno_blitter.h"
32 #include "freedreno_fence.h"
33 #include "freedreno_log.h"
34 #include "freedreno_resource.h"
35
36 #include "fd6_blitter.h"
37 #include "fd6_format.h"
38 #include "fd6_emit.h"
39 #include "fd6_resource.h"
40
41 static inline enum a6xx_2d_ifmt
fd6_ifmt(enum a6xx_format fmt)42 fd6_ifmt(enum a6xx_format fmt)
43 {
44 switch (fmt) {
45 case FMT6_A8_UNORM:
46 case FMT6_8_UNORM:
47 case FMT6_8_SNORM:
48 case FMT6_8_8_UNORM:
49 case FMT6_8_8_SNORM:
50 case FMT6_8_8_8_8_UNORM:
51 case FMT6_8_8_8_X8_UNORM:
52 case FMT6_8_8_8_8_SNORM:
53 case FMT6_4_4_4_4_UNORM:
54 case FMT6_5_5_5_1_UNORM:
55 case FMT6_5_6_5_UNORM:
56 return R2D_UNORM8;
57
58 case FMT6_32_UINT:
59 case FMT6_32_SINT:
60 case FMT6_32_32_UINT:
61 case FMT6_32_32_SINT:
62 case FMT6_32_32_32_32_UINT:
63 case FMT6_32_32_32_32_SINT:
64 return R2D_INT32;
65
66 case FMT6_16_UINT:
67 case FMT6_16_SINT:
68 case FMT6_16_16_UINT:
69 case FMT6_16_16_SINT:
70 case FMT6_16_16_16_16_UINT:
71 case FMT6_16_16_16_16_SINT:
72 case FMT6_10_10_10_2_UINT:
73 return R2D_INT16;
74
75 case FMT6_8_UINT:
76 case FMT6_8_SINT:
77 case FMT6_8_8_UINT:
78 case FMT6_8_8_SINT:
79 case FMT6_8_8_8_8_UINT:
80 case FMT6_8_8_8_8_SINT:
81 case FMT6_Z24_UNORM_S8_UINT:
82 case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
83 return R2D_INT8;
84
85 case FMT6_16_UNORM:
86 case FMT6_16_SNORM:
87 case FMT6_16_16_UNORM:
88 case FMT6_16_16_SNORM:
89 case FMT6_16_16_16_16_UNORM:
90 case FMT6_16_16_16_16_SNORM:
91 case FMT6_32_FLOAT:
92 case FMT6_32_32_FLOAT:
93 case FMT6_32_32_32_32_FLOAT:
94 return R2D_FLOAT32;
95
96 case FMT6_16_FLOAT:
97 case FMT6_16_16_FLOAT:
98 case FMT6_16_16_16_16_FLOAT:
99 case FMT6_11_11_10_FLOAT:
100 case FMT6_10_10_10_2_UNORM_DEST:
101 return R2D_FLOAT16;
102
103 default:
104 unreachable("bad format");
105 return 0;
106 }
107 }
108
109 /* Make sure none of the requested dimensions extend beyond the size of the
110 * resource. Not entirely sure why this happens, but sometimes it does, and
111 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
112 * back to u_blitter
113 */
114 static bool
ok_dims(const struct pipe_resource * r,const struct pipe_box * b,int lvl)115 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
116 {
117 int last_layer =
118 r->target == PIPE_TEXTURE_3D ? u_minify(r->depth0, lvl)
119 : r->array_size;
120
121 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
122 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
123 (b->z >= 0) && (b->z + b->depth <= last_layer);
124 }
125
126 static bool
ok_format(enum pipe_format pfmt)127 ok_format(enum pipe_format pfmt)
128 {
129 enum a6xx_format fmt = fd6_pipe2color(pfmt);
130
131 if (util_format_is_compressed(pfmt))
132 return true;
133
134 switch (pfmt) {
135 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
136 case PIPE_FORMAT_Z24X8_UNORM:
137 case PIPE_FORMAT_Z16_UNORM:
138 case PIPE_FORMAT_Z32_UNORM:
139 case PIPE_FORMAT_Z32_FLOAT:
140 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
141 case PIPE_FORMAT_S8_UINT:
142 return true;
143 default:
144 break;
145 }
146
147 if (fmt == FMT6_NONE)
148 return false;
149
150 return true;
151 }
152
153 #define DEBUG_BLIT 0
154 #define DEBUG_BLIT_FALLBACK 0
155
156 #define fail_if(cond) \
157 do { \
158 if (cond) { \
159 if (DEBUG_BLIT_FALLBACK) { \
160 fprintf(stderr, "falling back: %s for blit:\n", #cond); \
161 dump_blit_info(info); \
162 } \
163 return false; \
164 } \
165 } while (0)
166
167 static bool
is_ubwc(struct pipe_resource * prsc,unsigned level)168 is_ubwc(struct pipe_resource *prsc, unsigned level)
169 {
170 return fd_resource_ubwc_enabled(fd_resource(prsc), level);
171 }
172
173 static void
dump_blit_info(const struct pipe_blit_info * info)174 dump_blit_info(const struct pipe_blit_info *info)
175 {
176 util_dump_blit_info(stderr, info);
177 fprintf(stderr, "\ndst resource: ");
178 util_dump_resource(stderr, info->dst.resource);
179 if (is_ubwc(info->dst.resource, info->dst.level))
180 fprintf(stderr, " (ubwc)");
181 fprintf(stderr, "\nsrc resource: ");
182 util_dump_resource(stderr, info->src.resource);
183 if (is_ubwc(info->src.resource, info->src.level))
184 fprintf(stderr, " (ubwc)");
185 fprintf(stderr, "\n");
186 }
187
188 static bool
can_do_blit(const struct pipe_blit_info * info)189 can_do_blit(const struct pipe_blit_info *info)
190 {
191 /* I think we can do scaling, but not in z dimension since that would
192 * require blending..
193 */
194 fail_if(info->dst.box.depth != info->src.box.depth);
195
196 /* Fail if unsupported format: */
197 fail_if(!ok_format(info->src.format));
198 fail_if(!ok_format(info->dst.format));
199
200 debug_assert(!util_format_is_compressed(info->src.format));
201 debug_assert(!util_format_is_compressed(info->dst.format));
202
203 fail_if(!ok_dims(info->src.resource, &info->src.box, info->src.level));
204
205 fail_if(!ok_dims(info->dst.resource, &info->dst.box, info->dst.level));
206
207 debug_assert(info->dst.box.width >= 0);
208 debug_assert(info->dst.box.height >= 0);
209 debug_assert(info->dst.box.depth >= 0);
210
211 fail_if(info->dst.resource->nr_samples > 1);
212
213 fail_if(info->window_rectangle_include);
214
215 const struct util_format_description *src_desc =
216 util_format_description(info->src.format);
217 const struct util_format_description *dst_desc =
218 util_format_description(info->dst.format);
219 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels);
220
221 if (info->mask & PIPE_MASK_RGBA) {
222 for (int i = 0; i < common_channels; i++) {
223 fail_if(memcmp(&src_desc->channel[i],
224 &dst_desc->channel[i],
225 sizeof(src_desc->channel[0])));
226 }
227 }
228
229 fail_if(info->alpha_blend);
230
231 return true;
232 }
233
234 static void
emit_setup(struct fd_batch * batch)235 emit_setup(struct fd_batch *batch)
236 {
237 struct fd_ringbuffer *ring = batch->draw;
238 struct fd_screen *screen = batch->ctx->screen;
239
240 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
241 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
242 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
243 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
244
245 /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
246 OUT_WFI5(ring);
247 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
248 OUT_RING(ring, A6XX_RB_CCU_CNTL_OFFSET(screen->info.a6xx.ccu_offset_bypass));
249 }
250
251 static void
emit_blit_setup(struct fd_ringbuffer * ring,enum pipe_format pfmt,bool scissor_enable,union pipe_color_union * color)252 emit_blit_setup(struct fd_ringbuffer *ring,
253 enum pipe_format pfmt, bool scissor_enable, union pipe_color_union *color)
254 {
255 enum a6xx_format fmt = fd6_pipe2color(pfmt);
256 bool is_srgb = util_format_is_srgb(pfmt);
257 enum a6xx_2d_ifmt ifmt = fd6_ifmt(fmt);
258
259 OUT_PKT7(ring, CP_SET_MARKER, 1);
260 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
261
262 if (is_srgb) {
263 assert(ifmt == R2D_UNORM8);
264 ifmt = R2D_UNORM8_SRGB;
265 }
266
267 uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
268 A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
269 A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt) |
270 COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) |
271 COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR);
272
273 OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
274 OUT_RING(ring, blit_cntl);
275
276 OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
277 OUT_RING(ring, blit_cntl);
278
279 if (fmt == FMT6_10_10_10_2_UNORM_DEST)
280 fmt = FMT6_16_16_16_16_FLOAT;
281
282 /* This register is probably badly named... it seems that it's
283 * controlling the internal/accumulator format or something like
284 * that. It's certainly not tied to only the src format.
285 */
286 OUT_PKT4(ring, REG_A6XX_SP_2D_DST_FORMAT, 1);
287 OUT_RING(ring, A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(fmt) |
288 COND(util_format_is_pure_sint(pfmt),
289 A6XX_SP_2D_DST_FORMAT_SINT) |
290 COND(util_format_is_pure_uint(pfmt),
291 A6XX_SP_2D_DST_FORMAT_UINT) |
292 COND(util_format_is_snorm(pfmt),
293 A6XX_SP_2D_DST_FORMAT_SINT |
294 A6XX_SP_2D_DST_FORMAT_NORM) |
295 COND(util_format_is_unorm(pfmt),
296 // TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
297 // A6XX_SP_2D_DST_FORMAT_UINT |
298 A6XX_SP_2D_DST_FORMAT_NORM) |
299 COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) |
300 A6XX_SP_2D_DST_FORMAT_MASK(0xf));
301
302 OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
303 OUT_RING(ring, 0);
304 }
305
306 /* buffers need to be handled specially since x/width can exceed the bounds
307 * supported by hw.. if necessary decompose into (potentially) two 2D blits
308 */
309 static void
emit_blit_buffer(struct fd_context * ctx,struct fd_ringbuffer * ring,const struct pipe_blit_info * info)310 emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
311 const struct pipe_blit_info *info)
312 {
313 const struct pipe_box *sbox = &info->src.box;
314 const struct pipe_box *dbox = &info->dst.box;
315 struct fd_resource *src, *dst;
316 unsigned sshift, dshift;
317
318 if (DEBUG_BLIT) {
319 fprintf(stderr, "buffer blit: ");
320 dump_blit_info(info);
321 }
322
323 src = fd_resource(info->src.resource);
324 dst = fd_resource(info->dst.resource);
325
326 debug_assert(src->layout.cpp == 1);
327 debug_assert(dst->layout.cpp == 1);
328 debug_assert(info->src.resource->format == info->dst.resource->format);
329 debug_assert((sbox->y == 0) && (sbox->height == 1));
330 debug_assert((dbox->y == 0) && (dbox->height == 1));
331 debug_assert((sbox->z == 0) && (sbox->depth == 1));
332 debug_assert((dbox->z == 0) && (dbox->depth == 1));
333 debug_assert(sbox->width == dbox->width);
334 debug_assert(info->src.level == 0);
335 debug_assert(info->dst.level == 0);
336
337 /*
338 * Buffers can have dimensions bigger than max width, remap into
339 * multiple 1d blits to fit within max dimension
340 *
341 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
342 * seems to prevent overfetch related faults. Not quite sure what
343 * the deal is there.
344 *
345 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
346 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
347 * difference. On top of already splitting up the blit so width
348 * isn't > 16k.
349 *
350 * We perhaps could do a bit better, if src and dst are aligned but
351 * in the worst case this means we have to split the copy up into
352 * 16k (0x4000) minus 64 (0x40).
353 */
354
355 sshift = sbox->x & 0x3f;
356 dshift = dbox->x & 0x3f;
357
358 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, NULL);
359
360 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
361 unsigned soff, doff, w, p;
362
363 soff = (sbox->x + off) & ~0x3f;
364 doff = (dbox->x + off) & ~0x3f;
365
366 w = MIN2(sbox->width - off, (0x4000 - 0x40));
367 p = align(w, 64);
368
369 debug_assert((soff + w) <= fd_bo_size(src->bo));
370 debug_assert((doff + w) <= fd_bo_size(dst->bo));
371
372 /*
373 * Emit source:
374 */
375 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
376 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
377 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(TILE6_LINEAR) |
378 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(WZYX) |
379 0x500000);
380 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(sshift + w) |
381 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(1)); /* SP_PS_2D_SRC_SIZE */
382 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
383 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(p));
384
385 OUT_RING(ring, 0x00000000);
386 OUT_RING(ring, 0x00000000);
387 OUT_RING(ring, 0x00000000);
388 OUT_RING(ring, 0x00000000);
389 OUT_RING(ring, 0x00000000);
390
391 /*
392 * Emit destination:
393 */
394 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
395 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
396 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
397 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
398 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
399 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p));
400 OUT_RING(ring, 0x00000000);
401 OUT_RING(ring, 0x00000000);
402 OUT_RING(ring, 0x00000000);
403 OUT_RING(ring, 0x00000000);
404 OUT_RING(ring, 0x00000000);
405
406 /*
407 * Blit command:
408 */
409 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
410 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sshift));
411 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sshift + w - 1));
412 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(0));
413 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(0));
414
415 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
416 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
417 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) | A6XX_GRAS_2D_DST_BR_Y(0));
418
419 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
420 OUT_RING(ring, 0x3f);
421 OUT_WFI5(ring);
422
423 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
424 OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
425
426 OUT_PKT7(ring, CP_BLIT, 1);
427 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
428
429 OUT_WFI5(ring);
430
431 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
432 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
433 }
434 }
435
436 static void
fd6_clear_ubwc(struct fd_batch * batch,struct fd_resource * rsc)437 fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc)
438 {
439 struct fd_ringbuffer *ring = fd_batch_get_prologue(batch);
440 union pipe_color_union color = {};
441
442 emit_blit_setup(ring, PIPE_FORMAT_R8_UNORM, false, &color);
443
444 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
445 OUT_RING(ring, 0x00000000);
446 OUT_RING(ring, 0x00000000);
447 OUT_RING(ring, 0x00000000);
448 OUT_RING(ring, 0x00000000);
449 OUT_RING(ring, 0x00000000);
450 OUT_RING(ring, 0x00000000);
451 OUT_RING(ring, 0x00000000);
452 OUT_RING(ring, 0x00000000);
453 OUT_RING(ring, 0x00000000);
454 OUT_RING(ring, 0x00000000);
455 OUT_RING(ring, 0x00000000);
456 OUT_RING(ring, 0x00000000);
457 OUT_RING(ring, 0x00000000);
458
459 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
460 OUT_RING(ring, 0x00000000);
461 OUT_RING(ring, 0x00000000);
462 OUT_RING(ring, 0x00000000);
463 OUT_RING(ring, 0x00000000);
464
465 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
466 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(0));
467 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(0));
468 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(0));
469 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(0));
470
471 unsigned size = rsc->layout.slices[0].offset;
472 unsigned offset = 0;
473
474 /* We could be more clever here and realize that we could use a
475 * larger width if the size is aligned to something more than a
476 * single page.. or even use a format larger than r8 in those
477 * cases. But for normal sized textures and even up to 16k x 16k
478 * at <= 4byte/pixel, we'll only go thru the loop once
479 */
480 const unsigned w = 0x1000;
481
482 /* ubwc size should always be page aligned: */
483 assert((size % w) == 0);
484
485 while (size > 0) {
486 const unsigned h = MIN2(0x4000, size / w);
487 /* width is already aligned to a suitable pitch: */
488 const unsigned p = w;
489
490 /*
491 * Emit destination:
492 */
493 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
494 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(FMT6_8_UNORM) |
495 A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
496 A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
497 OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_2D_DST_LO/HI */
498 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p));
499 OUT_RING(ring, 0x00000000);
500 OUT_RING(ring, 0x00000000);
501 OUT_RING(ring, 0x00000000);
502 OUT_RING(ring, 0x00000000);
503 OUT_RING(ring, 0x00000000);
504
505 /*
506 * Blit command:
507 */
508
509 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
510 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
511 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(w - 1) | A6XX_GRAS_2D_DST_BR_Y(h - 1));
512
513 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
514 OUT_RING(ring, 0x3f);
515 OUT_WFI5(ring);
516
517 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
518 OUT_RING(ring, batch->ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
519
520 OUT_PKT7(ring, CP_BLIT, 1);
521 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
522
523 OUT_WFI5(ring);
524
525 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
526 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
527
528 offset += w * h;
529 size -= w * h;
530 }
531
532 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
533 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
534 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
535 fd6_cache_inv(batch, ring);
536 }
537
538 static void
emit_blit_dst(struct fd_ringbuffer * ring,struct pipe_resource * prsc,enum pipe_format pfmt,unsigned level,unsigned layer)539 emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_format pfmt, unsigned level, unsigned layer)
540 {
541 struct fd_resource *dst = fd_resource(prsc);
542 enum a6xx_format fmt = fd6_pipe2color(pfmt);
543 enum a6xx_tile_mode tile = fd_resource_tile_mode(prsc, level);
544 enum a3xx_color_swap swap = fd6_resource_swap(dst, pfmt);
545 uint32_t pitch = fd_resource_pitch(dst, level);
546 bool ubwc_enabled = fd_resource_ubwc_enabled(dst, level);
547 unsigned off = fd_resource_offset(dst, level, layer);
548
549 if (fmt == FMT6_Z24_UNORM_S8_UINT)
550 fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
551
552 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
553 OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(fmt) |
554 A6XX_RB_2D_DST_INFO_TILE_MODE(tile) |
555 A6XX_RB_2D_DST_INFO_COLOR_SWAP(swap) |
556 COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) |
557 COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS));
558 OUT_RELOC(ring, dst->bo, off, 0, 0); /* RB_2D_DST_LO/HI */
559 OUT_RING(ring, A6XX_RB_2D_DST_PITCH(pitch));
560 OUT_RING(ring, 0x00000000);
561 OUT_RING(ring, 0x00000000);
562 OUT_RING(ring, 0x00000000);
563 OUT_RING(ring, 0x00000000);
564 OUT_RING(ring, 0x00000000);
565
566 if (ubwc_enabled) {
567 OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
568 fd6_emit_flag_reference(ring, dst, level, layer);
569 OUT_RING(ring, 0x00000000);
570 OUT_RING(ring, 0x00000000);
571 OUT_RING(ring, 0x00000000);
572 }
573 }
574
575 static void
emit_blit_src(struct fd_ringbuffer * ring,const struct pipe_blit_info * info,unsigned layer,unsigned nr_samples)576 emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info, unsigned layer, unsigned nr_samples)
577 {
578 struct fd_resource *src = fd_resource(info->src.resource);
579 enum a6xx_format sfmt = fd6_pipe2color(info->src.format);
580 enum a6xx_tile_mode stile = fd_resource_tile_mode(info->src.resource, info->src.level);
581 enum a3xx_color_swap sswap = fd6_resource_swap(src, info->src.format);
582 uint32_t pitch = fd_resource_pitch(src, info->src.level);
583 bool subwc_enabled = fd_resource_ubwc_enabled(src, info->src.level);
584 unsigned soff = fd_resource_offset(src, info->src.level, layer);
585 uint32_t width = u_minify(src->base.width0, info->src.level) * nr_samples;
586 uint32_t height = u_minify(src->base.height0, info->src.level);
587 uint32_t filter = 0;
588
589 if (info->filter == PIPE_TEX_FILTER_LINEAR)
590 filter = A6XX_SP_PS_2D_SRC_INFO_FILTER;
591
592 enum a3xx_msaa_samples samples = fd_msaa_samples(src->base.nr_samples);
593
594 if (sfmt == FMT6_10_10_10_2_UNORM_DEST)
595 sfmt = FMT6_10_10_10_2_UNORM;
596
597 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 10);
598 OUT_RING(ring, A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
599 A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(stile) |
600 A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(sswap) |
601 A6XX_SP_PS_2D_SRC_INFO_SAMPLES(samples) |
602 COND(samples > MSAA_ONE && (info->mask & PIPE_MASK_RGBA),
603 A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
604 COND(subwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
605 COND(util_format_is_srgb(info->src.format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
606 0x500000 | filter);
607 OUT_RING(ring, A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
608 A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height)); /* SP_PS_2D_SRC_SIZE */
609 OUT_RELOC(ring, src->bo, soff, 0, 0); /* SP_PS_2D_SRC_LO/HI */
610 OUT_RING(ring, A6XX_SP_PS_2D_SRC_PITCH_PITCH(pitch));
611
612 OUT_RING(ring, 0x00000000);
613 OUT_RING(ring, 0x00000000);
614 OUT_RING(ring, 0x00000000);
615 OUT_RING(ring, 0x00000000);
616 OUT_RING(ring, 0x00000000);
617
618 if (subwc_enabled) {
619 OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
620 fd6_emit_flag_reference(ring, src, info->src.level, layer);
621 OUT_RING(ring, 0x00000000);
622 OUT_RING(ring, 0x00000000);
623 OUT_RING(ring, 0x00000000);
624 }
625 }
626
627 static void
emit_blit_texture(struct fd_context * ctx,struct fd_ringbuffer * ring,const struct pipe_blit_info * info)628 emit_blit_texture(struct fd_context *ctx,
629 struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
630 {
631 const struct pipe_box *sbox = &info->src.box;
632 const struct pipe_box *dbox = &info->dst.box;
633 struct fd_resource *dst;
634 int sx1, sy1, sx2, sy2;
635 int dx1, dy1, dx2, dy2;
636
637 if (DEBUG_BLIT) {
638 fprintf(stderr, "texture blit: ");
639 dump_blit_info(info);
640 }
641
642 dst = fd_resource(info->dst.resource);
643
644 uint32_t nr_samples = fd_resource_nr_samples(&dst->base);
645
646 sx1 = sbox->x * nr_samples;
647 sy1 = sbox->y;
648 sx2 = (sbox->x + sbox->width) * nr_samples - 1;
649 sy2 = sbox->y + sbox->height - 1;
650
651 OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
652 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X(sx1));
653 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X(sx2));
654 OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y(sy1));
655 OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y(sy2));
656
657 dx1 = dbox->x * nr_samples;
658 dy1 = dbox->y;
659 dx2 = (dbox->x + dbox->width) * nr_samples - 1;
660 dy2 = dbox->y + dbox->height - 1;
661
662 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
663 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dx1) | A6XX_GRAS_2D_DST_TL_Y(dy1));
664 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dx2) | A6XX_GRAS_2D_DST_BR_Y(dy2));
665
666 if (info->scissor_enable) {
667 OUT_PKT4(ring, REG_A6XX_GRAS_2D_RESOLVE_CNTL_1, 2);
668 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.minx) |
669 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.miny));
670 OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
671 A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
672 }
673
674 emit_blit_setup(ring, info->dst.format, info->scissor_enable, NULL);
675
676 for (unsigned i = 0; i < info->dst.box.depth; i++) {
677
678 emit_blit_src(ring, info, sbox->z + i, nr_samples);
679 emit_blit_dst(ring, info->dst.resource, info->dst.format, info->dst.level, dbox->z + i);
680
681 /*
682 * Blit command:
683 */
684 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
685 OUT_RING(ring, 0x3f);
686 OUT_WFI5(ring);
687
688 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
689 OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
690
691 OUT_PKT7(ring, CP_BLIT, 1);
692 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
693
694 OUT_WFI5(ring);
695
696 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
697 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
698 }
699 }
700
701 static void
emit_clear_color(struct fd_ringbuffer * ring,enum pipe_format pfmt,union pipe_color_union * color)702 emit_clear_color(struct fd_ringbuffer *ring,
703 enum pipe_format pfmt, union pipe_color_union *color)
704 {
705 switch (pfmt) {
706 case PIPE_FORMAT_Z24X8_UNORM:
707 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
708 case PIPE_FORMAT_X24S8_UINT: {
709 uint32_t depth_unorm24 = color->f[0] * ((1u << 24) - 1);
710 uint8_t stencil = color->ui[1];
711 color->ui[0] = depth_unorm24 & 0xff;
712 color->ui[1] = (depth_unorm24 >> 8) & 0xff;
713 color->ui[2] = (depth_unorm24 >> 16) & 0xff;
714 color->ui[3] = stencil;
715 break;
716 }
717 default:
718 break;
719 }
720
721 OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
722 switch (fd6_ifmt(fd6_pipe2color(pfmt))) {
723 case R2D_UNORM8:
724 case R2D_UNORM8_SRGB:
725 OUT_RING(ring, float_to_ubyte(color->f[0]));
726 OUT_RING(ring, float_to_ubyte(color->f[1]));
727 OUT_RING(ring, float_to_ubyte(color->f[2]));
728 OUT_RING(ring, float_to_ubyte(color->f[3]));
729 break;
730 case R2D_FLOAT16:
731 OUT_RING(ring, _mesa_float_to_half(color->f[0]));
732 OUT_RING(ring, _mesa_float_to_half(color->f[1]));
733 OUT_RING(ring, _mesa_float_to_half(color->f[2]));
734 OUT_RING(ring, _mesa_float_to_half(color->f[3]));
735 break;
736 case R2D_FLOAT32:
737 case R2D_INT32:
738 case R2D_INT16:
739 case R2D_INT8:
740 default:
741 OUT_RING(ring, color->ui[0]);
742 OUT_RING(ring, color->ui[1]);
743 OUT_RING(ring, color->ui[2]);
744 OUT_RING(ring, color->ui[3]);
745 break;
746 }
747 }
748
749 void
fd6_clear_surface(struct fd_context * ctx,struct fd_ringbuffer * ring,struct pipe_surface * psurf,uint32_t width,uint32_t height,union pipe_color_union * color)750 fd6_clear_surface(struct fd_context *ctx,
751 struct fd_ringbuffer *ring, struct pipe_surface *psurf,
752 uint32_t width, uint32_t height, union pipe_color_union *color)
753 {
754 if (DEBUG_BLIT) {
755 fprintf(stderr, "surface clear:\ndst resource: ");
756 util_dump_resource(stderr, psurf->texture);
757 fprintf(stderr, "\n");
758 }
759
760 uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
761 OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
762 OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
763 OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width * nr_samples - 1) |
764 A6XX_GRAS_2D_DST_BR_Y(height - 1));
765
766 emit_clear_color(ring, psurf->format, color);
767 emit_blit_setup(ring, psurf->format, false, color);
768
769 for (unsigned i = psurf->u.tex.first_layer; i <= psurf->u.tex.last_layer; i++) {
770 emit_blit_dst(ring, psurf->texture, psurf->format, psurf->u.tex.level, i);
771
772 /*
773 * Blit command:
774 */
775 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
776 OUT_RING(ring, 0x3f);
777 OUT_WFI5(ring);
778
779 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
780 OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
781
782 OUT_PKT7(ring, CP_BLIT, 1);
783 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
784
785 OUT_WFI5(ring);
786
787 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
788 OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
789 }
790 }
791
792 static bool
handle_rgba_blit(struct fd_context * ctx,const struct pipe_blit_info * info)793 handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
794 {
795 struct fd_batch *batch;
796
797 debug_assert(!(info->mask & PIPE_MASK_ZS));
798
799 if (!can_do_blit(info))
800 return false;
801
802 batch = fd_bc_alloc_batch(&ctx->screen->batch_cache, ctx, true);
803
804 fd_screen_lock(ctx->screen);
805
806 fd_batch_resource_read(batch, fd_resource(info->src.resource));
807 fd_batch_resource_write(batch, fd_resource(info->dst.resource));
808
809 fd_screen_unlock(ctx->screen);
810
811 /* Clearing last_fence must come after the batch dependency tracking
812 * (resource_read()/resource_write()), as that can trigger a flush,
813 * re-populating last_fence
814 */
815 fd_fence_ref(&ctx->last_fence, NULL);
816
817 fd_batch_set_stage(batch, FD_STAGE_BLIT);
818
819 fd_log_stream(batch, stream, util_dump_blit_info(stream, info));
820
821 emit_setup(batch);
822
823 if ((info->src.resource->target == PIPE_BUFFER) &&
824 (info->dst.resource->target == PIPE_BUFFER)) {
825 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
826 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
827 fd_log(batch, "START BLIT (BUFFER)");
828 emit_blit_buffer(ctx, batch->draw, info);
829 fd_log(batch, "END BLIT (BUFFER)");
830 } else {
831 /* I don't *think* we need to handle blits between buffer <-> !buffer */
832 debug_assert(info->src.resource->target != PIPE_BUFFER);
833 debug_assert(info->dst.resource->target != PIPE_BUFFER);
834 fd_log(batch, "START BLIT (TEXTURE)");
835 emit_blit_texture(ctx, batch->draw, info);
836 fd_log(batch, "END BLIT (TEXTURE)");
837 }
838
839 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
840 fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
841 fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
842 fd6_cache_inv(batch, batch->draw);
843
844 fd_resource(info->dst.resource)->valid = true;
845 batch->needs_flush = true;
846
847 fd_batch_flush(batch);
848 fd_batch_reference(&batch, NULL);
849
850 return true;
851 }
852
853 /**
854 * Re-written z/s blits can still fail for various reasons (for example MSAA).
855 * But we want to do the fallback blit with the re-written pipe_blit_info,
856 * in particular as u_blitter cannot blit stencil. So handle the fallback
857 * ourself and never "fail".
858 */
859 static bool
do_rewritten_blit(struct fd_context * ctx,const struct pipe_blit_info * info)860 do_rewritten_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
861 {
862 bool success = handle_rgba_blit(ctx, info);
863 if (!success)
864 success = fd_blitter_blit(ctx, info);
865 debug_assert(success); /* fallback should never fail! */
866 return success;
867 }
868
869 /**
870 * Handle depth/stencil blits either via u_blitter and/or re-writing the
871 * blit into an equivilant format that we can handle
872 */
873 static bool
handle_zs_blit(struct fd_context * ctx,const struct pipe_blit_info * info)874 handle_zs_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
875 {
876 struct pipe_blit_info blit = *info;
877
878 if (DEBUG_BLIT) {
879 fprintf(stderr, "---- handle_zs_blit: ");
880 dump_blit_info(info);
881 }
882
883 switch (info->dst.format) {
884 case PIPE_FORMAT_S8_UINT:
885 debug_assert(info->mask == PIPE_MASK_S);
886 blit.mask = PIPE_MASK_R;
887 blit.src.format = PIPE_FORMAT_R8_UINT;
888 blit.dst.format = PIPE_FORMAT_R8_UINT;
889 return do_rewritten_blit(ctx, &blit);
890
891 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
892 if (info->mask & PIPE_MASK_Z) {
893 blit.mask = PIPE_MASK_R;
894 blit.src.format = PIPE_FORMAT_R32_FLOAT;
895 blit.dst.format = PIPE_FORMAT_R32_FLOAT;
896 do_rewritten_blit(ctx, &blit);
897 }
898
899 if (info->mask & PIPE_MASK_S) {
900 blit.mask = PIPE_MASK_R;
901 blit.src.format = PIPE_FORMAT_R8_UINT;
902 blit.dst.format = PIPE_FORMAT_R8_UINT;
903 blit.src.resource = &fd_resource(info->src.resource)->stencil->base;
904 blit.dst.resource = &fd_resource(info->dst.resource)->stencil->base;
905 do_rewritten_blit(ctx, &blit);
906 }
907
908 return true;
909
910 case PIPE_FORMAT_Z16_UNORM:
911 blit.mask = PIPE_MASK_R;
912 blit.src.format = PIPE_FORMAT_R16_UNORM;
913 blit.dst.format = PIPE_FORMAT_R16_UNORM;
914 return do_rewritten_blit(ctx, &blit);
915
916 case PIPE_FORMAT_Z32_UNORM:
917 case PIPE_FORMAT_Z32_FLOAT:
918 debug_assert(info->mask == PIPE_MASK_Z);
919 blit.mask = PIPE_MASK_R;
920 blit.src.format = PIPE_FORMAT_R32_UINT;
921 blit.dst.format = PIPE_FORMAT_R32_UINT;
922 return do_rewritten_blit(ctx, &blit);
923
924 case PIPE_FORMAT_Z24X8_UNORM:
925 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
926 blit.mask = 0;
927 if (info->mask & PIPE_MASK_Z)
928 blit.mask |= PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B;
929 if (info->mask & PIPE_MASK_S)
930 blit.mask |= PIPE_MASK_A;
931 blit.src.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
932 blit.dst.format = PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
933 return fd_blitter_blit(ctx, &blit);
934
935 default:
936 return false;
937 }
938 }
939
940 static bool
handle_compressed_blit(struct fd_context * ctx,const struct pipe_blit_info * info)941 handle_compressed_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
942 {
943 struct pipe_blit_info blit = *info;
944
945 if (DEBUG_BLIT) {
946 fprintf(stderr, "---- handle_compressed_blit: ");
947 dump_blit_info(info);
948 }
949
950 if (info->src.format != info->dst.format)
951 return fd_blitter_blit(ctx, info);
952
953 if (util_format_get_blocksize(info->src.format) == 8) {
954 blit.src.format = blit.dst.format = PIPE_FORMAT_R16G16B16A16_UINT;
955 } else {
956 debug_assert(util_format_get_blocksize(info->src.format) == 16);
957 blit.src.format = blit.dst.format = PIPE_FORMAT_R32G32B32A32_UINT;
958 }
959
960 int bw = util_format_get_blockwidth(info->src.format);
961 int bh = util_format_get_blockheight(info->src.format);
962
963 /* NOTE: x/y *must* be aligned to block boundary (ie. in
964 * glCompressedTexSubImage2D()) but width/height may not
965 * be:
966 */
967
968 debug_assert((blit.src.box.x % bw) == 0);
969 debug_assert((blit.src.box.y % bh) == 0);
970
971 blit.src.box.x /= bw;
972 blit.src.box.y /= bh;
973 blit.src.box.width = DIV_ROUND_UP(blit.src.box.width, bw);
974 blit.src.box.height = DIV_ROUND_UP(blit.src.box.height, bh);
975
976 debug_assert((blit.dst.box.x % bw) == 0);
977 debug_assert((blit.dst.box.y % bh) == 0);
978
979 blit.dst.box.x /= bw;
980 blit.dst.box.y /= bh;
981 blit.dst.box.width = DIV_ROUND_UP(blit.dst.box.width, bw);
982 blit.dst.box.height = DIV_ROUND_UP(blit.dst.box.height, bh);
983
984 return do_rewritten_blit(ctx, &blit);
985 }
986
987 static bool
fd6_blit(struct fd_context * ctx,const struct pipe_blit_info * info)988 fd6_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
989 {
990 if (info->mask & PIPE_MASK_ZS)
991 return handle_zs_blit(ctx, info);
992 if (util_format_is_compressed(info->src.format) ||
993 util_format_is_compressed(info->dst.format))
994 return handle_compressed_blit(ctx, info);
995
996 return handle_rgba_blit(ctx, info);
997 }
998
999 void
fd6_blitter_init(struct pipe_context * pctx)1000 fd6_blitter_init(struct pipe_context *pctx)
1001 {
1002 fd_context(pctx)->clear_ubwc = fd6_clear_ubwc;
1003
1004 if (fd_mesa_debug & FD_DBG_NOBLIT)
1005 return;
1006
1007 fd_context(pctx)->blit = fd6_blit;
1008 }
1009
1010 unsigned
fd6_tile_mode(const struct pipe_resource * tmpl)1011 fd6_tile_mode(const struct pipe_resource *tmpl)
1012 {
1013 /* if the mipmap level 0 is still too small to be tiled, then don't
1014 * bother pretending:
1015 */
1016 if (fd_resource_level_linear(tmpl, 0))
1017 return TILE6_LINEAR;
1018
1019 /* basically just has to be a format we can blit, so uploads/downloads
1020 * via linear staging buffer works:
1021 */
1022 if (ok_format(tmpl->format))
1023 return TILE6_3;
1024
1025 return TILE6_LINEAR;
1026 }
1027