1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_const.h"
39 #include "fd6_emit.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
42 #include "fd6_pack.h"
43
44 void
fd6_emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)45 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
46 {
47 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
48
49 uint32_t obj_start;
50 uint32_t instrlen;
51
52 switch (so->type) {
53 case MESA_SHADER_VERTEX:
54 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
55 instrlen = REG_A6XX_SP_VS_INSTRLEN;
56 break;
57 case MESA_SHADER_TESS_CTRL:
58 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
59 instrlen = REG_A6XX_SP_HS_INSTRLEN;
60 break;
61 case MESA_SHADER_TESS_EVAL:
62 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
63 instrlen = REG_A6XX_SP_DS_INSTRLEN;
64 break;
65 case MESA_SHADER_GEOMETRY:
66 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
67 instrlen = REG_A6XX_SP_GS_INSTRLEN;
68 break;
69 case MESA_SHADER_FRAGMENT:
70 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
71 instrlen = REG_A6XX_SP_FS_INSTRLEN;
72 break;
73 case MESA_SHADER_COMPUTE:
74 case MESA_SHADER_KERNEL:
75 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
76 instrlen = REG_A6XX_SP_CS_INSTRLEN;
77 break;
78 case MESA_SHADER_TASK:
79 case MESA_SHADER_MESH:
80 case MESA_SHADER_RAYGEN:
81 case MESA_SHADER_ANY_HIT:
82 case MESA_SHADER_CLOSEST_HIT:
83 case MESA_SHADER_MISS:
84 case MESA_SHADER_INTERSECTION:
85 case MESA_SHADER_CALLABLE:
86 unreachable("Unsupported shader stage");
87 case MESA_SHADER_NONE:
88 unreachable("");
89 }
90
91 #ifdef DEBUG
92 /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
93 const char *name = so->shader->nir->info.name;
94 if (name)
95 fd_emit_string5(ring, name, strlen(name));
96 #endif
97
98 OUT_PKT4(ring, instrlen, 1);
99 OUT_RING(ring, so->instrlen);
100
101 OUT_PKT4(ring, obj_start, 2);
102 OUT_RELOC(ring, so->bo, 0, 0, 0);
103
104 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
105 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
106 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
107 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
108 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
109 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
110 OUT_RELOC(ring, so->bo, 0, 0, 0);
111 }
112
113 /* Add any missing varyings needed for stream-out. Otherwise varyings not
114 * used by fragment shader will be stripped out.
115 */
116 static void
link_stream_out(struct ir3_shader_linkage * l,const struct ir3_shader_variant * v)117 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
118 {
119 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
120
121 /*
122 * First, any stream-out varyings not already in linkage map (ie. also
123 * consumed by frag shader) need to be added:
124 */
125 for (unsigned i = 0; i < strmout->num_outputs; i++) {
126 const struct ir3_stream_output *out = &strmout->output[i];
127 unsigned k = out->register_index;
128 unsigned compmask =
129 (1 << (out->num_components + out->start_component)) - 1;
130 unsigned idx, nextloc = 0;
131
132 /* psize/pos need to be the last entries in linkage map, and will
133 * get added link_stream_out, so skip over them:
134 */
135 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
136 (v->outputs[k].slot == VARYING_SLOT_POS))
137 continue;
138
139 for (idx = 0; idx < l->cnt; idx++) {
140 if (l->var[idx].regid == v->outputs[k].regid)
141 break;
142 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
143 }
144
145 /* add if not already in linkage map: */
146 if (idx == l->cnt)
147 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
148
149 /* expand component-mask if needed, ie streaming out all components
150 * but frag shader doesn't consume all components:
151 */
152 if (compmask & ~l->var[idx].compmask) {
153 l->var[idx].compmask |= compmask;
154 l->max_loc = MAX2(l->max_loc,
155 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
156 }
157 }
158 }
159
160 static void
setup_stream_out(struct fd6_program_state * state,const struct ir3_shader_variant * v,struct ir3_shader_linkage * l)161 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
162 struct ir3_shader_linkage *l)
163 {
164 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
165
166 uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
167 uint32_t prog[256/2];
168 uint32_t prog_count;
169
170 memset(ncomp, 0, sizeof(ncomp));
171 memset(prog, 0, sizeof(prog));
172
173 prog_count = align(l->max_loc, 2) / 2;
174
175 debug_assert(prog_count < ARRAY_SIZE(prog));
176
177 for (unsigned i = 0; i < strmout->num_outputs; i++) {
178 const struct ir3_stream_output *out = &strmout->output[i];
179 unsigned k = out->register_index;
180 unsigned idx;
181
182 ncomp[out->output_buffer] += out->num_components;
183
184 /* linkage map sorted by order frag shader wants things, so
185 * a bit less ideal here..
186 */
187 for (idx = 0; idx < l->cnt; idx++)
188 if (l->var[idx].regid == v->outputs[k].regid)
189 break;
190
191 debug_assert(idx < l->cnt);
192
193 for (unsigned j = 0; j < out->num_components; j++) {
194 unsigned c = j + out->start_component;
195 unsigned loc = l->var[idx].loc + c;
196 unsigned off = j + out->dst_offset; /* in dwords */
197
198 if (loc & 1) {
199 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
200 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
201 A6XX_VPC_SO_PROG_B_OFF(off * 4);
202 } else {
203 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
204 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
205 A6XX_VPC_SO_PROG_A_OFF(off * 4);
206 }
207 }
208 }
209
210 struct fd_ringbuffer *ring = state->streamout_stateobj;
211
212 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
213 OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
214 OUT_RING(ring, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) |
215 COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
216 COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
217 COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
218 COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
219 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
220 OUT_RING(ring, ncomp[0]);
221 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
222 OUT_RING(ring, ncomp[1]);
223 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
224 OUT_RING(ring, ncomp[2]);
225 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
226 OUT_RING(ring, ncomp[3]);
227 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
228 OUT_RING(ring, A6XX_VPC_SO_CNTL_RESET);
229 for (unsigned i = 0; i < prog_count; i++) {
230 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
231 OUT_RING(ring, prog[i]);
232 }
233 }
234
235 static void
setup_config_stateobj(struct fd_ringbuffer * ring,struct fd6_program_state * state)236 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
237 {
238 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
239 .vs_state = true,
240 .hs_state = true,
241 .ds_state = true,
242 .gs_state = true,
243 .fs_state = true,
244 .cs_state = true,
245 .gfx_ibo = true,
246 .cs_ibo = true,
247 ));
248
249 debug_assert(state->vs->constlen >= state->bs->constlen);
250
251 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
252 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
253 A6XX_HLSQ_VS_CNTL_ENABLED);
254 OUT_RING(ring, COND(state->hs,
255 A6XX_HLSQ_HS_CNTL_ENABLED |
256 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
257 OUT_RING(ring, COND(state->ds,
258 A6XX_HLSQ_DS_CNTL_ENABLED |
259 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
260 OUT_RING(ring, COND(state->gs,
261 A6XX_HLSQ_GS_CNTL_ENABLED |
262 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
263 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
264 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
265 A6XX_HLSQ_FS_CNTL_ENABLED);
266
267 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
268 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
269 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
270 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
271 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
272
273 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
274 OUT_RING(ring, COND(state->hs,
275 A6XX_SP_HS_CONFIG_ENABLED |
276 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
277 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
278 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
279
280 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
281 OUT_RING(ring, COND(state->ds,
282 A6XX_SP_DS_CONFIG_ENABLED |
283 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
284 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
285 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
286
287 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
288 OUT_RING(ring, COND(state->gs,
289 A6XX_SP_GS_CONFIG_ENABLED |
290 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
291 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
292 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
293
294 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
295 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
296 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
297 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
298 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
299
300 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
301 OUT_RING(ring, ir3_shader_nibo(state->fs));
302 }
303
304 static inline uint32_t
next_regid(uint32_t reg,uint32_t increment)305 next_regid(uint32_t reg, uint32_t increment)
306 {
307 if (VALIDREG(reg))
308 return reg + increment;
309 else
310 return regid(63,0);
311 }
312
313 static void
setup_stateobj(struct fd_ringbuffer * ring,struct fd_screen * screen,struct fd6_program_state * state,const struct ir3_shader_key * key,bool binning_pass)314 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
315 struct fd6_program_state *state, const struct ir3_shader_key *key,
316 bool binning_pass)
317 {
318 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
319 uint32_t clip0_regid, clip1_regid;
320 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
321 uint32_t smask_in_regid, smask_regid;
322 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
323 uint32_t hs_invocation_regid;
324 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
325 uint32_t ij_regid[IJ_COUNT];
326 uint32_t gs_header_regid;
327 enum a3xx_threadsize fssz;
328 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
329 uint8_t clip0_loc, clip1_loc;
330 int i, j;
331
332 static const struct ir3_shader_variant dummy_fs = {0};
333 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
334 const struct ir3_shader_variant *hs = state->hs;
335 const struct ir3_shader_variant *ds = state->ds;
336 const struct ir3_shader_variant *gs = state->gs;
337 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
338
339 /* binning VS is wrong when GS is present, so use nonbinning VS
340 * TODO: compile both binning VS/GS variants correctly
341 */
342 if (binning_pass && state->gs)
343 vs = state->vs;
344
345 bool sample_shading = fs->per_samp | key->sample_shading;
346
347 fssz = FOUR_QUADS;
348
349 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
350 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
351 clip0_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST0);
352 clip1_regid = ir3_find_output_regid(vs, VARYING_SLOT_CLIP_DIST1);
353 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
354 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
355
356 if (hs) {
357 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
358 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
359 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
360 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
361 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
362
363 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
364 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
365 clip0_regid = ir3_find_output_regid(ds, VARYING_SLOT_CLIP_DIST0);
366 clip1_regid = ir3_find_output_regid(ds, VARYING_SLOT_CLIP_DIST1);
367 } else {
368 tess_coord_x_regid = regid(63, 0);
369 tess_coord_y_regid = regid(63, 0);
370 hs_patch_regid = regid(63, 0);
371 ds_patch_regid = regid(63, 0);
372 hs_invocation_regid = regid(63, 0);
373 }
374
375 if (gs) {
376 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
377 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
378 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
379 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
380 clip0_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST0);
381 clip1_regid = ir3_find_output_regid(gs, VARYING_SLOT_CLIP_DIST1);
382 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
383 } else {
384 gs_header_regid = regid(63, 0);
385 primitive_regid = regid(63, 0);
386 layer_regid = regid(63, 0);
387 }
388
389 if (fs->color0_mrt) {
390 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
391 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
392 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
393 } else {
394 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
395 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
396 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
397 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
398 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
399 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
400 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
401 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
402 }
403
404 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
405 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
406 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
407 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
408 zwcoord_regid = next_regid(coord_regid, 2);
409 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
410 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
411 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
412 ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
413
414 /* If we have pre-dispatch texture fetches, then ij_pix should not
415 * be DCE'd, even if not actually used in the shader itself:
416 */
417 if (fs->num_sampler_prefetch > 0) {
418 assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
419 /* also, it seems like ij_pix is *required* to be r0.x */
420 assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
421 }
422
423 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
424 * end up masking the single sample!!
425 */
426 if (!key->msaa)
427 smask_regid = regid(63, 0);
428
429 /* we could probably divide this up into things that need to be
430 * emitted if frag-prog is dirty vs if vert-prog is dirty..
431 */
432
433 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
434 OUT_RING(ring, 0x0);
435
436 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
437 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
438 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
439 0x7000); // XXX
440 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
441 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
442 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
443 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
444 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
445 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
446 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
447 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
448 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
449 }
450
451 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
452 OUT_RING(ring, 0);
453
454 OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
455 OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
456
457 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
458 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
459 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
460 0xfc000000);
461
462 enum a3xx_threadsize vssz;
463 if (ds || hs) {
464 vssz = TWO_QUADS;
465 } else {
466 vssz = FOUR_QUADS;
467 }
468
469 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
470 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
471 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
472 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
473 COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
474 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
475 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
476
477 fd6_emit_shader(ring, vs);
478 fd6_emit_immediates(screen, vs, ring);
479
480 struct ir3_shader_linkage l = {0};
481 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
482
483 bool do_streamout = (last_shader->shader->stream_output.num_outputs > 0);
484 uint8_t clip_mask = last_shader->clip_mask, cull_mask = last_shader->cull_mask;
485 uint8_t clip_cull_mask = clip_mask | cull_mask;
486
487 /* If we have streamout, link against the real FS, rather than the
488 * dummy FS used for binning pass state, to ensure the OUTLOC's
489 * match. Depending on whether we end up doing sysmem or gmem,
490 * the actual streamout could happen with either the binning pass
491 * or draw pass program, but the same streamout stateobj is used
492 * in either case:
493 */
494 ir3_link_shaders(&l, last_shader, do_streamout ? state->fs : fs, true);
495
496 bool primid_passthru = l.primid_loc != 0xff;
497 clip0_loc = l.clip0_loc;
498 clip1_loc = l.clip1_loc;
499
500 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
501 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
502 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
503 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
504 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
505
506 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
507 link_stream_out(&l, last_shader);
508
509 if (VALIDREG(layer_regid)) {
510 layer_loc = l.max_loc;
511 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
512 }
513
514 if (VALIDREG(pos_regid)) {
515 pos_loc = l.max_loc;
516 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
517 }
518
519 if (VALIDREG(psize_regid)) {
520 psize_loc = l.max_loc;
521 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
522 }
523
524 /* Handle the case where clip/cull distances aren't read by the FS. Make
525 * sure to avoid adding an output with an empty writemask if the user
526 * disables all the clip distances in the API so that the slot is unused.
527 */
528 if (clip0_loc == 0xff && VALIDREG(clip0_regid) && (clip_cull_mask & 0xf) != 0) {
529 clip0_loc = l.max_loc;
530 ir3_link_add(&l, clip0_regid, clip_cull_mask & 0xf, l.max_loc);
531 }
532
533 if (clip1_loc == 0xff && VALIDREG(clip1_regid) && (clip_cull_mask >> 4) != 0) {
534 clip1_loc = l.max_loc;
535 ir3_link_add(&l, clip1_regid, clip_cull_mask >> 4, l.max_loc);
536 }
537
538 /* If we have stream-out, we use the full shader for binning
539 * pass, rather than the optimized binning pass one, so that we
540 * have all the varying outputs available for xfb. So streamout
541 * state should always be derived from the non-binning pass
542 * program:
543 */
544 if (do_streamout && !binning_pass) {
545 setup_stream_out(state, last_shader, &l);
546 }
547
548 debug_assert(l.cnt <= 32);
549 if (gs)
550 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
551 else if (ds)
552 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
553 else
554 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
555
556 for (j = 0; j < l.cnt; ) {
557 uint32_t reg = 0;
558
559 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
560 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
561 j++;
562
563 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
564 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
565 j++;
566
567 OUT_RING(ring, reg);
568 }
569
570 if (gs)
571 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
572 else if (ds)
573 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
574 else
575 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
576
577 for (j = 0; j < l.cnt; ) {
578 uint32_t reg = 0;
579
580 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
581 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
582 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
583 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
584
585 OUT_RING(ring, reg);
586 }
587
588 if (hs) {
589 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
590 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
591 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
592 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
593 COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
594 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
595 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
596
597 fd6_emit_shader(ring, hs);
598 fd6_emit_immediates(screen, hs, ring);
599 fd6_emit_link_map(screen, vs, hs, ring);
600
601 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
602 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
603 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
604 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
605 COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
606 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
607 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
608
609 fd6_emit_shader(ring, ds);
610 fd6_emit_immediates(screen, ds, ring);
611 fd6_emit_link_map(screen, hs, ds, ring);
612
613 shader_info *hs_info = &hs->shader->nir->info;
614 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
615 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
616
617 /* Total attribute slots in HS incoming patch. */
618 OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
619 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
620
621 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
622 OUT_RING(ring, vs->output_size);
623
624 shader_info *ds_info = &ds->shader->nir->info;
625 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
626 uint32_t output;
627 if (ds_info->tess.point_mode)
628 output = TESS_POINTS;
629 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
630 output = TESS_LINES;
631 else if (ds_info->tess.ccw)
632 output = TESS_CCW_TRIS;
633 else
634 output = TESS_CW_TRIS;
635
636 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
637 A6XX_PC_TESS_CNTL_OUTPUT(output));
638
639 OUT_PKT4(ring, REG_A6XX_VPC_DS_CLIP_CNTL, 1);
640 OUT_RING(ring, A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
641 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
642 A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
643
644 OUT_PKT4(ring, REG_A6XX_VPC_DS_LAYER_CNTL, 1);
645 OUT_RING(ring, 0x0000ffff);
646
647 OUT_PKT4(ring, REG_A6XX_GRAS_DS_LAYER_CNTL, 1);
648 OUT_RING(ring, 0x0);
649
650 OUT_PKT4(ring, REG_A6XX_GRAS_DS_CL_CNTL, 1);
651 OUT_RING(ring, A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(clip_mask) |
652 A6XX_GRAS_DS_CL_CNTL_CULL_MASK(cull_mask));
653
654 OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
655 OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
656 A6XX_VPC_VS_PACK_PSIZELOC(255) |
657 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
658
659 OUT_PKT4(ring, REG_A6XX_VPC_DS_PACK, 1);
660 OUT_RING(ring, A6XX_VPC_DS_PACK_POSITIONLOC(pos_loc) |
661 A6XX_VPC_DS_PACK_PSIZELOC(psize_loc) |
662 A6XX_VPC_DS_PACK_STRIDE_IN_VPC(l.max_loc));
663
664 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
665 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_OUT(l.cnt));
666
667 OUT_PKT4(ring, REG_A6XX_PC_DS_OUT_CNTL, 1);
668 OUT_RING(ring, A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
669 CONDREG(psize_regid, A6XX_PC_DS_OUT_CNTL_PSIZE) |
670 A6XX_PC_DS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
671
672 } else {
673 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
674 OUT_RING(ring, 0);
675 }
676
677 OUT_PKT4(ring, REG_A6XX_SP_VS_PRIMITIVE_CNTL, 1);
678 OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(l.cnt));
679
680 bool enable_varyings = fs->total_in > 0;
681
682 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
683 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
684 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
685 A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
686 A6XX_VPC_CNTL_0_VIEWIDLOC(0xff));
687
688 OUT_PKT4(ring, REG_A6XX_PC_VS_OUT_CNTL, 1);
689 OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
690 CONDREG(psize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
691 A6XX_PC_VS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
692
693 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
694 OUT_RING(ring, 0);
695
696 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
697 OUT_RING(ring, 0x7); /* XXX */
698 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
699 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
700 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
701 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
702 OUT_RING(ring,
703 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
704 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
705 A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
706 A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
707 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
708 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
709 A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
710 A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
711 OUT_RING(ring, 0xfc); /* XXX */
712
713 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
714 OUT_RING(ring, enable_varyings ? 3 : 1);
715
716 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
717 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
718 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
719 0x1000000 |
720 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
721 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
722 COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
723 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
724 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
725
726 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
727 OUT_RING(ring, 0); /* XXX */
728
729 OUT_PKT4(ring, REG_A6XX_VPC_VS_LAYER_CNTL, 1);
730 OUT_RING(ring, 0x0000ffff); /* XXX */
731
732 bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
733 bool need_size_persamp = false;
734 if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
735 if (sample_shading)
736 need_size_persamp = true;
737 else
738 need_size = true;
739 }
740 if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
741 need_size = true;
742
743 /* XXX: enable bits for linear centroid and linear sample bary */
744
745 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
746 OUT_RING(ring,
747 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
748 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
749 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
750 COND(need_size, A6XX_GRAS_CNTL_SIZE) |
751 COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
752 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
753
754 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
755 OUT_RING(ring,
756 CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
757 CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
758 CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
759 COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
760 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
761 COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
762 COND(fs->fragcoord_compmask != 0,
763 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
764
765 OUT_RING(ring,
766 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
767 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
768 CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
769 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
770
771 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
772 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
773
774 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
775 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
776
777 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
778 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
779
780 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
781 for (i = 0; i < 8; i++) {
782 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
783 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
784 }
785
786 OUT_PKT4(ring, REG_A6XX_VPC_VS_PACK, 1);
787 OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(pos_loc) |
788 A6XX_VPC_VS_PACK_PSIZELOC(psize_loc) |
789 A6XX_VPC_VS_PACK_STRIDE_IN_VPC(l.max_loc));
790
791 if (gs) {
792 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
793 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
794 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
795 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
796 COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
797 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
798 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
799
800 fd6_emit_shader(ring, gs);
801 fd6_emit_immediates(screen, gs, ring);
802 if (ds)
803 fd6_emit_link_map(screen, ds, gs, ring);
804 else
805 fd6_emit_link_map(screen, vs, gs, ring);
806
807 OUT_PKT4(ring, REG_A6XX_VPC_GS_PACK, 1);
808 OUT_RING(ring, A6XX_VPC_GS_PACK_POSITIONLOC(pos_loc) |
809 A6XX_VPC_GS_PACK_PSIZELOC(psize_loc) |
810 A6XX_VPC_GS_PACK_STRIDE_IN_VPC(l.max_loc));
811
812 OUT_PKT4(ring, REG_A6XX_VPC_GS_LAYER_CNTL, 1);
813 OUT_RING(ring, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
814
815 OUT_PKT4(ring, REG_A6XX_GRAS_GS_LAYER_CNTL, 1);
816 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
817
818 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
819
820 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIMITIVE_CNTL, 1);
821 OUT_RING(ring, A6XX_SP_GS_PRIMITIVE_CNTL_OUT(l.cnt) |
822 A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
823
824 OUT_PKT4(ring, REG_A6XX_PC_GS_OUT_CNTL, 1);
825 OUT_RING(ring, A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(l.max_loc) |
826 CONDREG(psize_regid, A6XX_PC_GS_OUT_CNTL_PSIZE) |
827 CONDREG(layer_regid, A6XX_PC_GS_OUT_CNTL_LAYER) |
828 CONDREG(primitive_regid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID) |
829 A6XX_PC_GS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
830
831 uint32_t output;
832 switch (gs->shader->nir->info.gs.output_primitive) {
833 case GL_POINTS:
834 output = TESS_POINTS;
835 break;
836 case GL_LINE_STRIP:
837 output = TESS_LINES;
838 break;
839 case GL_TRIANGLE_STRIP:
840 output = TESS_CW_TRIS;
841 break;
842 default:
843 unreachable("");
844 }
845 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
846 OUT_RING(ring,
847 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
848 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
849 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
850
851 OUT_PKT4(ring, REG_A6XX_GRAS_GS_CL_CNTL, 1);
852 OUT_RING(ring, A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(clip_mask) |
853 A6XX_GRAS_GS_CL_CNTL_CULL_MASK(cull_mask));
854
855 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
856 OUT_RING(ring, 0xff);
857
858 OUT_PKT4(ring, REG_A6XX_VPC_GS_CLIP_CNTL, 1);
859 OUT_RING(ring, A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
860 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
861 A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
862
863 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
864
865 /* Size of per-primitive alloction in ldlw memory in vec4s. */
866 uint32_t vec4_size =
867 gs->shader->nir->info.gs.vertices_in *
868 DIV_ROUND_UP(prev->output_size, 4);
869 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
870 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
871
872 OUT_PKT4(ring, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
873 OUT_RING(ring, 0);
874
875 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
876 OUT_RING(ring, prev->output_size);
877 } else {
878 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
879 OUT_RING(ring, 0);
880 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
881 OUT_RING(ring, 0);
882 }
883
884 OUT_PKT4(ring, REG_A6XX_VPC_VS_CLIP_CNTL, 1);
885 OUT_RING(ring, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
886 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
887 A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
888
889 OUT_PKT4(ring, REG_A6XX_GRAS_VS_CL_CNTL, 1);
890 OUT_RING(ring, A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
891 A6XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
892
893 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
894 OUT_RING(ring, 0);
895
896 if (fs->instrlen)
897 fd6_emit_shader(ring, fs);
898
899 OUT_REG(ring, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
900
901 uint32_t non_sysval_input_count = 0;
902 for (uint32_t i = 0; i < vs->inputs_count; i++)
903 if (!vs->inputs[i].sysval)
904 non_sysval_input_count++;
905
906 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
907 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
908 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
909
910 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
911 for (uint32_t i = 0; i < non_sysval_input_count; i++) {
912 assert(vs->inputs[i].compmask);
913 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
914 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
915 }
916
917 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
918 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
919 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
920 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
921 0xfc000000);
922 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
923 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
924 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
925 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
926 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
927 0xfc);
928 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
929 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
930 0xfc00); /* VFD_CONTROL_5 */
931 OUT_RING(ring,
932 COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
933
934 if (!binning_pass)
935 fd6_emit_immediates(screen, fs, ring);
936 }
937
938 static void emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
939 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable);
940
941 static struct fd_ringbuffer *
create_interp_stateobj(struct fd_context * ctx,struct fd6_program_state * state)942 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
943 {
944 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
945
946 emit_interp_state(ring, state->fs, false, false, 0);
947
948 return ring;
949 }
950
951 /* build the program streaming state which is not part of the pre-
952 * baked stateobj because of dependency on other gl state (rasterflat
953 * or sprite-coord-replacement)
954 */
955 struct fd_ringbuffer *
fd6_program_interp_state(struct fd6_emit * emit)956 fd6_program_interp_state(struct fd6_emit *emit)
957 {
958 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
959
960 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
961 /* fastpath: */
962 return fd_ringbuffer_ref(state->interp_stateobj);
963 } else {
964 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
965 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
966
967 emit_interp_state(ring, state->fs, emit->rasterflat,
968 emit->sprite_coord_mode, emit->sprite_coord_enable);
969
970 return ring;
971 }
972 }
973
974 static void
emit_interp_state(struct fd_ringbuffer * ring,struct ir3_shader_variant * fs,bool rasterflat,bool sprite_coord_mode,uint32_t sprite_coord_enable)975 emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
976 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable)
977 {
978 uint32_t vinterp[8], vpsrepl[8];
979
980 memset(vinterp, 0, sizeof(vinterp));
981 memset(vpsrepl, 0, sizeof(vpsrepl));
982
983 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
984
985 /* NOTE: varyings are packed, so if compmask is 0xb
986 * then first, third, and fourth component occupy
987 * three consecutive varying slots:
988 */
989 unsigned compmask = fs->inputs[j].compmask;
990
991 uint32_t inloc = fs->inputs[j].inloc;
992
993 if (fs->inputs[j].flat ||
994 (fs->inputs[j].rasterflat && rasterflat)) {
995 uint32_t loc = inloc;
996
997 for (int i = 0; i < 4; i++) {
998 if (compmask & (1 << i)) {
999 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
1000 loc++;
1001 }
1002 }
1003 }
1004
1005 bool coord_mode = sprite_coord_mode;
1006 if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
1007 /* mask is two 2-bit fields, where:
1008 * '01' -> S
1009 * '10' -> T
1010 * '11' -> 1 - T (flip mode)
1011 */
1012 unsigned mask = coord_mode ? 0b1101 : 0b1001;
1013 uint32_t loc = inloc;
1014 if (compmask & 0x1) {
1015 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
1016 loc++;
1017 }
1018 if (compmask & 0x2) {
1019 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
1020 loc++;
1021 }
1022 if (compmask & 0x4) {
1023 /* .z <- 0.0f */
1024 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
1025 loc++;
1026 }
1027 if (compmask & 0x8) {
1028 /* .w <- 1.0f */
1029 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
1030 loc++;
1031 }
1032 }
1033 }
1034
1035 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1036 for (int i = 0; i < 8; i++)
1037 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
1038
1039 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1040 for (int i = 0; i < 8; i++)
1041 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
1042 }
1043
1044 static struct ir3_program_state *
fd6_program_create(void * data,struct ir3_shader_variant * bs,struct ir3_shader_variant * vs,struct ir3_shader_variant * hs,struct ir3_shader_variant * ds,struct ir3_shader_variant * gs,struct ir3_shader_variant * fs,const struct ir3_shader_key * key)1045 fd6_program_create(void *data, struct ir3_shader_variant *bs,
1046 struct ir3_shader_variant *vs,
1047 struct ir3_shader_variant *hs,
1048 struct ir3_shader_variant *ds,
1049 struct ir3_shader_variant *gs,
1050 struct ir3_shader_variant *fs,
1051 const struct ir3_shader_key *key)
1052 {
1053 struct fd_context *ctx = data;
1054 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
1055
1056 /* if we have streamout, use full VS in binning pass, as the
1057 * binning pass VS will have outputs on other than position/psize
1058 * stripped out:
1059 */
1060 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
1061 state->vs = vs;
1062 state->hs = hs;
1063 state->ds = ds;
1064 state->gs = gs;
1065 state->fs = fs;
1066 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1067 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1068 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1069 state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1070
1071
1072 #ifdef DEBUG
1073 if (!ds) {
1074 for (unsigned i = 0; i < bs->inputs_count; i++) {
1075 if (vs->inputs[i].sysval)
1076 continue;
1077 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
1078 }
1079 }
1080 #endif
1081
1082 setup_config_stateobj(state->config_stateobj, state);
1083 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
1084 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
1085 state->interp_stateobj = create_interp_stateobj(ctx, state);
1086
1087 return &state->base;
1088 }
1089
1090 static void
fd6_program_destroy(void * data,struct ir3_program_state * state)1091 fd6_program_destroy(void *data, struct ir3_program_state *state)
1092 {
1093 struct fd6_program_state *so = fd6_program_state(state);
1094 fd_ringbuffer_del(so->stateobj);
1095 fd_ringbuffer_del(so->binning_stateobj);
1096 fd_ringbuffer_del(so->config_stateobj);
1097 fd_ringbuffer_del(so->interp_stateobj);
1098 fd_ringbuffer_del(so->streamout_stateobj);
1099 free(so);
1100 }
1101
1102 static const struct ir3_cache_funcs cache_funcs = {
1103 .create_state = fd6_program_create,
1104 .destroy_state = fd6_program_destroy,
1105 };
1106
1107 static void *
fd6_shader_state_create(struct pipe_context * pctx,const struct pipe_shader_state * cso)1108 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1109 {
1110 return ir3_shader_state_create(pctx, cso);
1111 }
1112
1113 static void
fd6_shader_state_delete(struct pipe_context * pctx,void * hwcso)1114 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1115 {
1116 struct fd_context *ctx = fd_context(pctx);
1117 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1118 ir3_shader_state_delete(pctx, hwcso);
1119 }
1120
1121 void
fd6_prog_init(struct pipe_context * pctx)1122 fd6_prog_init(struct pipe_context *pctx)
1123 {
1124 struct fd_context *ctx = fd_context(pctx);
1125
1126 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1127
1128 pctx->create_vs_state = fd6_shader_state_create;
1129 pctx->delete_vs_state = fd6_shader_state_delete;
1130
1131 pctx->create_tcs_state = fd6_shader_state_create;
1132 pctx->delete_tcs_state = fd6_shader_state_delete;
1133
1134 pctx->create_tes_state = fd6_shader_state_create;
1135 pctx->delete_tes_state = fd6_shader_state_delete;
1136
1137 pctx->create_gs_state = fd6_shader_state_create;
1138 pctx->delete_gs_state = fd6_shader_state_delete;
1139
1140 pctx->create_gs_state = fd6_shader_state_create;
1141 pctx->delete_gs_state = fd6_shader_state_delete;
1142
1143 pctx->create_fs_state = fd6_shader_state_create;
1144 pctx->delete_fs_state = fd6_shader_state_delete;
1145
1146 fd_prog_init(pctx);
1147 }
1148