1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 /**
28 * \file glsl_to_tgsi.cpp
29 *
30 * Translate GLSL IR to TGSI.
31 */
32
33 #include "st_glsl_to_tgsi.h"
34
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
38
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
45
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_to_tgsi_temprename.h"
56
57 #include "util/hash_table.h"
58 #include <algorithm>
59
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
63
64 #define MAX_GLSL_TEXTURE_OFFSET 4
65
66 #ifndef NDEBUG
67 #include "util/u_atomic.h"
68 #include "util/simple_mtx.h"
69 #include <fstream>
70 #include <ios>
71
72 /* Prepare to make it possible to specify log file */
73 static std::ofstream stats_log;
74
75 /* Helper function to check whether we want to write some statistics
76 * of the shader conversion.
77 */
78
79 static simple_mtx_t print_stats_mutex = _SIMPLE_MTX_INITIALIZER_NP;
80
print_stats_enabled()81 static inline bool print_stats_enabled ()
82 {
83 static int stats_enabled = 0;
84
85 if (!stats_enabled) {
86 simple_mtx_lock(&print_stats_mutex);
87 if (!stats_enabled) {
88 const char *stats_filename = getenv("GLSL_TO_TGSI_PRINT_STATS");
89 if (stats_filename) {
90 bool write_header = std::ifstream(stats_filename).fail();
91 stats_log.open(stats_filename, std::ios_base::out | std::ios_base::app);
92 stats_enabled = stats_log.good() ? 1 : -1;
93 if (write_header)
94 stats_log << "arrays,temps,temps in arrays,total,instructions\n";
95 } else {
96 stats_enabled = -1;
97 }
98 }
99 simple_mtx_unlock(&print_stats_mutex);
100 }
101 return stats_enabled > 0;
102 }
103 #define PRINT_STATS(X) if (print_stats_enabled()) do { X; } while (false);
104 #else
105 #define PRINT_STATS(X)
106 #endif
107
108
is_precise(const ir_variable * ir)109 static unsigned is_precise(const ir_variable *ir)
110 {
111 if (!ir)
112 return 0;
113 return ir->data.precise || ir->data.invariant;
114 }
115
116 class variable_storage {
117 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage)
118
119 public:
variable_storage(ir_variable * var,gl_register_file file,int index,unsigned array_id=0)120 variable_storage(ir_variable *var, gl_register_file file, int index,
121 unsigned array_id = 0)
122 : file(file), index(index), component(0), var(var), array_id(array_id)
123 {
124 assert(file != PROGRAM_ARRAY || array_id != 0);
125 }
126
127 gl_register_file file;
128 int index;
129
130 /* Explicit component location. This is given in terms of the GLSL-style
131 * swizzles where each double is a single component, i.e. for 64-bit types
132 * it can only be 0 or 1.
133 */
134 int component;
135 ir_variable *var; /* variable that maps to this, if any */
136 unsigned array_id;
137 };
138
139 class immediate_storage : public exec_node {
140 public:
immediate_storage(gl_constant_value * values,int size32,GLenum type)141 immediate_storage(gl_constant_value *values, int size32, GLenum type)
142 {
143 memcpy(this->values, values, size32 * sizeof(gl_constant_value));
144 this->size32 = size32;
145 this->type = type;
146 }
147
148 /* doubles are stored across 2 gl_constant_values */
149 gl_constant_value values[4];
150 int size32; /**< Number of 32-bit components (1-4) */
151 GLenum type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
152 };
153
154 static const st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, GLSL_TYPE_ERROR);
155 static const st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, GLSL_TYPE_ERROR);
156
157 struct inout_decl {
158 unsigned mesa_index;
159 unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
160 unsigned size;
161 unsigned interp_loc;
162 unsigned gs_out_streams;
163 enum glsl_interp_mode interp;
164 enum glsl_base_type base_type;
165 ubyte usage_mask; /* GLSL-style usage-mask, i.e. single bit per double */
166 bool invariant;
167 };
168
169 static struct inout_decl *
find_inout_array(struct inout_decl * decls,unsigned count,unsigned array_id)170 find_inout_array(struct inout_decl *decls, unsigned count, unsigned array_id)
171 {
172 assert(array_id != 0);
173
174 for (unsigned i = 0; i < count; i++) {
175 struct inout_decl *decl = &decls[i];
176
177 if (array_id == decl->array_id) {
178 return decl;
179 }
180 }
181
182 return NULL;
183 }
184
185 static enum glsl_base_type
find_array_type(struct inout_decl * decls,unsigned count,unsigned array_id)186 find_array_type(struct inout_decl *decls, unsigned count, unsigned array_id)
187 {
188 if (!array_id)
189 return GLSL_TYPE_ERROR;
190 struct inout_decl *decl = find_inout_array(decls, count, array_id);
191 if (decl)
192 return decl->base_type;
193 return GLSL_TYPE_ERROR;
194 }
195
196 struct hwatomic_decl {
197 unsigned location;
198 unsigned binding;
199 unsigned size;
200 unsigned array_id;
201 };
202
203 struct glsl_to_tgsi_visitor : public ir_visitor {
204 public:
205 glsl_to_tgsi_visitor();
206 ~glsl_to_tgsi_visitor();
207
208 struct gl_context *ctx;
209 struct gl_program *prog;
210 struct gl_shader_program *shader_program;
211 struct gl_linked_shader *shader;
212 struct gl_shader_compiler_options *options;
213
214 int next_temp;
215
216 unsigned *array_sizes;
217 unsigned max_num_arrays;
218 unsigned next_array;
219
220 struct inout_decl inputs[4 * PIPE_MAX_SHADER_INPUTS];
221 unsigned num_inputs;
222 unsigned num_input_arrays;
223 struct inout_decl outputs[4 * PIPE_MAX_SHADER_OUTPUTS];
224 unsigned num_outputs;
225 unsigned num_output_arrays;
226
227 struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
228 unsigned num_atomics;
229 unsigned num_atomic_arrays;
230 int num_address_regs;
231 uint32_t samplers_used;
232 glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
233 enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
234 int images_used;
235 enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
236 enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
237 bool image_wr[PIPE_MAX_SHADER_IMAGES];
238 bool indirect_addr_consts;
239 int wpos_transform_const;
240
241 bool native_integers;
242 bool have_sqrt;
243 bool have_fma;
244 bool use_shared_memory;
245 bool has_tex_txf_lz;
246 bool precise;
247 bool need_uarl;
248 bool tg4_component_in_swizzle;
249
250 variable_storage *find_variable_storage(ir_variable *var);
251
252 int add_constant(gl_register_file file, gl_constant_value values[8],
253 int size, GLenum datatype, uint16_t *swizzle_out);
254
255 st_src_reg get_temp(const glsl_type *type);
256 void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
257
258 st_src_reg st_src_reg_for_double(double val);
259 st_src_reg st_src_reg_for_float(float val);
260 st_src_reg st_src_reg_for_int(int val);
261 st_src_reg st_src_reg_for_int64(int64_t val);
262 st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
263
264 /**
265 * \name Visit methods
266 *
267 * As typical for the visitor pattern, there must be one \c visit method for
268 * each concrete subclass of \c ir_instruction. Virtual base classes within
269 * the hierarchy should not have \c visit methods.
270 */
271 /*@{*/
272 virtual void visit(ir_variable *);
273 virtual void visit(ir_loop *);
274 virtual void visit(ir_loop_jump *);
275 virtual void visit(ir_function_signature *);
276 virtual void visit(ir_function *);
277 virtual void visit(ir_expression *);
278 virtual void visit(ir_swizzle *);
279 virtual void visit(ir_dereference_variable *);
280 virtual void visit(ir_dereference_array *);
281 virtual void visit(ir_dereference_record *);
282 virtual void visit(ir_assignment *);
283 virtual void visit(ir_constant *);
284 virtual void visit(ir_call *);
285 virtual void visit(ir_return *);
286 virtual void visit(ir_discard *);
287 virtual void visit(ir_demote *);
288 virtual void visit(ir_texture *);
289 virtual void visit(ir_if *);
290 virtual void visit(ir_emit_vertex *);
291 virtual void visit(ir_end_primitive *);
292 virtual void visit(ir_barrier *);
293 /*@}*/
294
295 void ATTRIBUTE_NOINLINE visit_expression(ir_expression *, st_src_reg *);
296
297 void visit_atomic_counter_intrinsic(ir_call *);
298 void visit_ssbo_intrinsic(ir_call *);
299 void visit_membar_intrinsic(ir_call *);
300 void visit_shared_intrinsic(ir_call *);
301 void visit_image_intrinsic(ir_call *);
302 void visit_generic_intrinsic(ir_call *, enum tgsi_opcode op);
303
304 st_src_reg result;
305
306 /** List of variable_storage */
307 struct hash_table *variables;
308
309 /** List of immediate_storage */
310 exec_list immediates;
311 unsigned num_immediates;
312
313 /** List of glsl_to_tgsi_instruction */
314 exec_list instructions;
315
316 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
317 st_dst_reg dst = undef_dst,
318 st_src_reg src0 = undef_src,
319 st_src_reg src1 = undef_src,
320 st_src_reg src2 = undef_src,
321 st_src_reg src3 = undef_src);
322
323 glsl_to_tgsi_instruction *emit_asm(ir_instruction *ir, enum tgsi_opcode op,
324 st_dst_reg dst, st_dst_reg dst1,
325 st_src_reg src0 = undef_src,
326 st_src_reg src1 = undef_src,
327 st_src_reg src2 = undef_src,
328 st_src_reg src3 = undef_src);
329
330 enum tgsi_opcode get_opcode(enum tgsi_opcode op,
331 st_dst_reg dst,
332 st_src_reg src0, st_src_reg src1);
333
334 /**
335 * Emit the correct dot-product instruction for the type of arguments
336 */
337 glsl_to_tgsi_instruction *emit_dp(ir_instruction *ir,
338 st_dst_reg dst,
339 st_src_reg src0,
340 st_src_reg src1,
341 unsigned elements);
342
343 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
344 st_dst_reg dst, st_src_reg src0);
345
346 void emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
347 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
348
349 void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
350
351 void get_deref_offsets(ir_dereference *ir,
352 unsigned *array_size,
353 unsigned *base,
354 uint16_t *index,
355 st_src_reg *reladdr,
356 bool opaque);
357 void calc_deref_offsets(ir_dereference *tail,
358 unsigned *array_elements,
359 uint16_t *index,
360 st_src_reg *indirect,
361 unsigned *location);
362 st_src_reg canonicalize_gather_offset(st_src_reg offset);
363 bool handle_bound_deref(ir_dereference *ir);
364
365 bool try_emit_mad(ir_expression *ir,
366 int mul_operand);
367 bool try_emit_mad_for_and_not(ir_expression *ir,
368 int mul_operand);
369
370 void emit_swz(ir_expression *ir);
371
372 bool process_move_condition(ir_rvalue *ir);
373
374 void simplify_cmp(void);
375
376 void rename_temp_registers(struct rename_reg_pair *renames);
377 void get_first_temp_read(int *first_reads);
378 void get_first_temp_write(int *first_writes);
379 void get_last_temp_read_first_temp_write(int *last_reads, int *first_writes);
380 void get_last_temp_write(int *last_writes);
381
382 void copy_propagate(void);
383 int eliminate_dead_code(void);
384
385 void split_arrays(void);
386 void merge_two_dsts(void);
387 void merge_registers(void);
388 void renumber_registers(void);
389
390 void emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
391 st_dst_reg *l, st_src_reg *r,
392 st_src_reg *cond, bool cond_swap);
393
394 void print_stats();
395
396 void *mem_ctx;
397 };
398
399 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
400 GLSL_TYPE_FLOAT, 0);
401 static st_dst_reg address_reg2 = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
402 GLSL_TYPE_FLOAT, 1);
403 static st_dst_reg sampler_reladdr = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X,
404 GLSL_TYPE_FLOAT, 2);
405
406 static void
407 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
408 PRINTFLIKE(2, 3);
409
410 static void
fail_link(struct gl_shader_program * prog,const char * fmt,...)411 fail_link(struct gl_shader_program *prog, const char *fmt, ...)
412 {
413 va_list args;
414 va_start(args, fmt);
415 ralloc_vasprintf_append(&prog->data->InfoLog, fmt, args);
416 va_end(args);
417
418 prog->data->LinkStatus = LINKING_FAILURE;
419 }
420
421 int
swizzle_for_size(int size)422 swizzle_for_size(int size)
423 {
424 static const int size_swizzles[4] = {
425 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
426 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
427 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
428 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
429 };
430
431 assert((size >= 1) && (size <= 4));
432 return size_swizzles[size - 1];
433 }
434
435
436 glsl_to_tgsi_instruction *
emit_asm(ir_instruction * ir,enum tgsi_opcode op,st_dst_reg dst,st_dst_reg dst1,st_src_reg src0,st_src_reg src1,st_src_reg src2,st_src_reg src3)437 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
438 st_dst_reg dst, st_dst_reg dst1,
439 st_src_reg src0, st_src_reg src1,
440 st_src_reg src2, st_src_reg src3)
441 {
442 glsl_to_tgsi_instruction *inst = new(mem_ctx) glsl_to_tgsi_instruction();
443 int num_reladdr = 0, i, j;
444 bool dst_is_64bit[2];
445
446 op = get_opcode(op, dst, src0, src1);
447
448 /* If we have to do relative addressing, we want to load the ARL
449 * reg directly for one of the regs, and preload the other reladdr
450 * sources into temps.
451 */
452 num_reladdr += dst.reladdr != NULL || dst.reladdr2;
453 assert(!dst1.reladdr); /* should be lowered in earlier passes */
454 num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
455 num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
456 num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
457 num_reladdr += src3.reladdr != NULL || src3.reladdr2 != NULL;
458
459 reladdr_to_temp(ir, &src3, &num_reladdr);
460 reladdr_to_temp(ir, &src2, &num_reladdr);
461 reladdr_to_temp(ir, &src1, &num_reladdr);
462 reladdr_to_temp(ir, &src0, &num_reladdr);
463
464 if (dst.reladdr || dst.reladdr2) {
465 if (dst.reladdr)
466 emit_arl(ir, address_reg, *dst.reladdr);
467 if (dst.reladdr2)
468 emit_arl(ir, address_reg2, *dst.reladdr2);
469 num_reladdr--;
470 }
471
472 assert(num_reladdr == 0);
473
474 /* inst->op has only 8 bits. */
475 STATIC_ASSERT(TGSI_OPCODE_LAST <= 255);
476
477 inst->op = op;
478 inst->precise = this->precise;
479 inst->info = tgsi_get_opcode_info(op);
480 inst->dst[0] = dst;
481 inst->dst[1] = dst1;
482 inst->src[0] = src0;
483 inst->src[1] = src1;
484 inst->src[2] = src2;
485 inst->src[3] = src3;
486 inst->is_64bit_expanded = false;
487 inst->ir = ir;
488 inst->dead_mask = 0;
489 inst->tex_offsets = NULL;
490 inst->tex_offset_num_offset = 0;
491 inst->saturate = 0;
492 inst->tex_shadow = 0;
493 /* default to float, for paths where this is not initialized
494 * (since 0==UINT which is likely wrong):
495 */
496 inst->tex_type = GLSL_TYPE_FLOAT;
497
498 /* Update indirect addressing status used by TGSI */
499 if (dst.reladdr || dst.reladdr2) {
500 switch (dst.file) {
501 case PROGRAM_STATE_VAR:
502 case PROGRAM_CONSTANT:
503 case PROGRAM_UNIFORM:
504 this->indirect_addr_consts = true;
505 break;
506 case PROGRAM_IMMEDIATE:
507 assert(!"immediates should not have indirect addressing");
508 break;
509 default:
510 break;
511 }
512 }
513 else {
514 for (i = 0; i < 4; i++) {
515 if (inst->src[i].reladdr) {
516 switch (inst->src[i].file) {
517 case PROGRAM_STATE_VAR:
518 case PROGRAM_CONSTANT:
519 case PROGRAM_UNIFORM:
520 this->indirect_addr_consts = true;
521 break;
522 case PROGRAM_IMMEDIATE:
523 assert(!"immediates should not have indirect addressing");
524 break;
525 default:
526 break;
527 }
528 }
529 }
530 }
531
532 /*
533 * This section contains the double processing.
534 * GLSL just represents doubles as single channel values,
535 * however most HW and TGSI represent doubles as pairs of register channels.
536 *
537 * so we have to fixup destination writemask/index and src swizzle/indexes.
538 * dest writemasks need to translate from single channel write mask
539 * to a dual-channel writemask, but also need to modify the index,
540 * if we are touching the Z,W fields in the pre-translated writemask.
541 *
542 * src channels have similiar index modifications along with swizzle
543 * changes to we pick the XY, ZW pairs from the correct index.
544 *
545 * GLSL [0].x -> TGSI [0].xy
546 * GLSL [0].y -> TGSI [0].zw
547 * GLSL [0].z -> TGSI [1].xy
548 * GLSL [0].w -> TGSI [1].zw
549 */
550 for (j = 0; j < 2; j++) {
551 dst_is_64bit[j] = glsl_base_type_is_64bit(inst->dst[j].type);
552 if (!dst_is_64bit[j] && inst->dst[j].file == PROGRAM_OUTPUT &&
553 inst->dst[j].type == GLSL_TYPE_ARRAY) {
554 enum glsl_base_type type = find_array_type(this->outputs,
555 this->num_outputs,
556 inst->dst[j].array_id);
557 if (glsl_base_type_is_64bit(type))
558 dst_is_64bit[j] = true;
559 }
560 }
561
562 if (dst_is_64bit[0] || dst_is_64bit[1] ||
563 glsl_base_type_is_64bit(inst->src[0].type)) {
564 glsl_to_tgsi_instruction *dinst = NULL;
565 int initial_src_swz[4], initial_src_idx[4];
566 int initial_dst_idx[2], initial_dst_writemask[2];
567 /* select the writemask for dst0 or dst1 */
568 unsigned writemask = inst->dst[1].file == PROGRAM_UNDEFINED
569 ? inst->dst[0].writemask : inst->dst[1].writemask;
570
571 /* copy out the writemask, index and swizzles for all src/dsts. */
572 for (j = 0; j < 2; j++) {
573 initial_dst_writemask[j] = inst->dst[j].writemask;
574 initial_dst_idx[j] = inst->dst[j].index;
575 }
576
577 for (j = 0; j < 4; j++) {
578 initial_src_swz[j] = inst->src[j].swizzle;
579 initial_src_idx[j] = inst->src[j].index;
580 }
581
582 /*
583 * scan all the components in the dst writemask
584 * generate an instruction for each of them if required.
585 */
586 st_src_reg addr;
587 while (writemask) {
588
589 int i = u_bit_scan(&writemask);
590
591 /* before emitting the instruction, see if we have to adjust
592 * load / store address */
593 if (i > 1 && (inst->op == TGSI_OPCODE_LOAD ||
594 inst->op == TGSI_OPCODE_STORE) &&
595 addr.file == PROGRAM_UNDEFINED) {
596 /* We have to advance the buffer address by 16 */
597 addr = get_temp(glsl_type::uint_type);
598 emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
599 inst->src[0], st_src_reg_for_int(16));
600 }
601
602 /* first time use previous instruction */
603 if (dinst == NULL) {
604 dinst = inst;
605 } else {
606 /* create a new instructions for subsequent attempts */
607 dinst = new(mem_ctx) glsl_to_tgsi_instruction();
608 *dinst = *inst;
609 dinst->next = NULL;
610 dinst->prev = NULL;
611 }
612 this->instructions.push_tail(dinst);
613 dinst->is_64bit_expanded = true;
614
615 /* modify the destination if we are splitting */
616 for (j = 0; j < 2; j++) {
617 if (dst_is_64bit[j]) {
618 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
619 dinst->dst[j].index = initial_dst_idx[j];
620 if (i > 1) {
621 if (dinst->op == TGSI_OPCODE_LOAD ||
622 dinst->op == TGSI_OPCODE_STORE)
623 dinst->src[0] = addr;
624 if (dinst->op != TGSI_OPCODE_STORE)
625 dinst->dst[j].index++;
626 }
627 } else {
628 /* if we aren't writing to a double, just get the bit of the
629 * initial writemask for this channel
630 */
631 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
632 }
633 }
634
635 /* modify the src registers */
636 for (j = 0; j < 4; j++) {
637 int swz = GET_SWZ(initial_src_swz[j], i);
638
639 if (glsl_base_type_is_64bit(dinst->src[j].type)) {
640 dinst->src[j].index = initial_src_idx[j];
641 if (swz > 1) {
642 dinst->src[j].double_reg2 = true;
643 dinst->src[j].index++;
644 }
645
646 if (swz & 1)
647 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W,
648 SWIZZLE_Z, SWIZZLE_W);
649 else
650 dinst->src[j].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
651 SWIZZLE_X, SWIZZLE_Y);
652
653 } else {
654 /* some opcodes are special case in what they use as sources
655 * - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
656 * integer src1
657 */
658 if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D ||
659 op == TGSI_OPCODE_I2D ||
660 op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
661 op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
662 (op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
663 dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
664 }
665 }
666 }
667 }
668 inst = dinst;
669 } else {
670 this->instructions.push_tail(inst);
671 }
672
673
674 return inst;
675 }
676
677 glsl_to_tgsi_instruction *
emit_asm(ir_instruction * ir,enum tgsi_opcode op,st_dst_reg dst,st_src_reg src0,st_src_reg src1,st_src_reg src2,st_src_reg src3)678 glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, enum tgsi_opcode op,
679 st_dst_reg dst,
680 st_src_reg src0, st_src_reg src1,
681 st_src_reg src2, st_src_reg src3)
682 {
683 return emit_asm(ir, op, dst, undef_dst, src0, src1, src2, src3);
684 }
685
686 /**
687 * Determines whether to use an integer, unsigned integer, or float opcode
688 * based on the operands and input opcode, then emits the result.
689 */
690 enum tgsi_opcode
get_opcode(enum tgsi_opcode op,st_dst_reg dst,st_src_reg src0,st_src_reg src1)691 glsl_to_tgsi_visitor::get_opcode(enum tgsi_opcode op,
692 st_dst_reg dst,
693 st_src_reg src0, st_src_reg src1)
694 {
695 enum glsl_base_type type = GLSL_TYPE_FLOAT;
696
697 if (op == TGSI_OPCODE_MOV)
698 return op;
699
700 assert(src0.type != GLSL_TYPE_ARRAY);
701 assert(src0.type != GLSL_TYPE_STRUCT);
702 assert(src1.type != GLSL_TYPE_ARRAY);
703 assert(src1.type != GLSL_TYPE_STRUCT);
704
705 if (is_resource_instruction(op))
706 type = src1.type;
707 else if (src0.type == GLSL_TYPE_INT64 || src1.type == GLSL_TYPE_INT64)
708 type = GLSL_TYPE_INT64;
709 else if (src0.type == GLSL_TYPE_UINT64 || src1.type == GLSL_TYPE_UINT64)
710 type = GLSL_TYPE_UINT64;
711 else if (src0.type == GLSL_TYPE_DOUBLE || src1.type == GLSL_TYPE_DOUBLE)
712 type = GLSL_TYPE_DOUBLE;
713 else if (src0.type == GLSL_TYPE_FLOAT || src1.type == GLSL_TYPE_FLOAT)
714 type = GLSL_TYPE_FLOAT;
715 else if (native_integers)
716 type = src0.type == GLSL_TYPE_BOOL ? GLSL_TYPE_INT : src0.type;
717
718 #define case7(c, f, i, u, d, i64, ui64) \
719 case TGSI_OPCODE_##c: \
720 if (type == GLSL_TYPE_UINT64) \
721 op = TGSI_OPCODE_##ui64; \
722 else if (type == GLSL_TYPE_INT64) \
723 op = TGSI_OPCODE_##i64; \
724 else if (type == GLSL_TYPE_DOUBLE) \
725 op = TGSI_OPCODE_##d; \
726 else if (type == GLSL_TYPE_INT) \
727 op = TGSI_OPCODE_##i; \
728 else if (type == GLSL_TYPE_UINT) \
729 op = TGSI_OPCODE_##u; \
730 else \
731 op = TGSI_OPCODE_##f; \
732 break;
733
734 #define casecomp(c, f, i, u, d, i64, ui64) \
735 case TGSI_OPCODE_##c: \
736 if (type == GLSL_TYPE_INT64) \
737 op = TGSI_OPCODE_##i64; \
738 else if (type == GLSL_TYPE_UINT64) \
739 op = TGSI_OPCODE_##ui64; \
740 else if (type == GLSL_TYPE_DOUBLE) \
741 op = TGSI_OPCODE_##d; \
742 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
743 op = TGSI_OPCODE_##i; \
744 else if (type == GLSL_TYPE_UINT) \
745 op = TGSI_OPCODE_##u; \
746 else if (native_integers) \
747 op = TGSI_OPCODE_##f; \
748 else \
749 op = TGSI_OPCODE_##c; \
750 break;
751
752 switch (op) {
753 /* Some instructions are initially selected without considering the type.
754 * This fixes the type:
755 *
756 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
757 */
758 case7(ADD, ADD, UADD, UADD, DADD, U64ADD, U64ADD);
759 case7(CEIL, CEIL, LAST, LAST, DCEIL, LAST, LAST);
760 case7(DIV, DIV, IDIV, UDIV, DDIV, I64DIV, U64DIV);
761 case7(FMA, FMA, UMAD, UMAD, DFMA, LAST, LAST);
762 case7(FLR, FLR, LAST, LAST, DFLR, LAST, LAST);
763 case7(FRC, FRC, LAST, LAST, DFRAC, LAST, LAST);
764 case7(MUL, MUL, UMUL, UMUL, DMUL, U64MUL, U64MUL);
765 case7(MAD, MAD, UMAD, UMAD, DMAD, LAST, LAST);
766 case7(MAX, MAX, IMAX, UMAX, DMAX, I64MAX, U64MAX);
767 case7(MIN, MIN, IMIN, UMIN, DMIN, I64MIN, U64MIN);
768 case7(RCP, RCP, LAST, LAST, DRCP, LAST, LAST);
769 case7(ROUND, ROUND,LAST, LAST, DROUND, LAST, LAST);
770 case7(RSQ, RSQ, LAST, LAST, DRSQ, LAST, LAST);
771 case7(SQRT, SQRT, LAST, LAST, DSQRT, LAST, LAST);
772 case7(SSG, SSG, ISSG, ISSG, DSSG, I64SSG, I64SSG);
773 case7(TRUNC, TRUNC,LAST, LAST, DTRUNC, LAST, LAST);
774
775 case7(MOD, LAST, MOD, UMOD, LAST, I64MOD, U64MOD);
776 case7(SHL, LAST, SHL, SHL, LAST, U64SHL, U64SHL);
777 case7(IBFE, LAST, IBFE, UBFE, LAST, LAST, LAST);
778 case7(IMSB, LAST, IMSB, UMSB, LAST, LAST, LAST);
779 case7(IMUL_HI, LAST, IMUL_HI, UMUL_HI, LAST, LAST, LAST);
780 case7(ISHR, LAST, ISHR, USHR, LAST, I64SHR, U64SHR);
781 case7(ATOMIMAX,LAST, ATOMIMAX,ATOMUMAX,LAST, LAST, LAST);
782 case7(ATOMIMIN,LAST, ATOMIMIN,ATOMUMIN,LAST, LAST, LAST);
783 case7(ATOMUADD,ATOMFADD,ATOMUADD,ATOMUADD,LAST, LAST, LAST);
784
785 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
786 casecomp(SNE, FSNE, USNE, USNE, DSNE, U64SNE, U64SNE);
787 casecomp(SGE, FSGE, ISGE, USGE, DSGE, I64SGE, U64SGE);
788 casecomp(SLT, FSLT, ISLT, USLT, DSLT, I64SLT, U64SLT);
789
790 default:
791 break;
792 }
793
794 assert(op != TGSI_OPCODE_LAST);
795 return op;
796 }
797
798 glsl_to_tgsi_instruction *
emit_dp(ir_instruction * ir,st_dst_reg dst,st_src_reg src0,st_src_reg src1,unsigned elements)799 glsl_to_tgsi_visitor::emit_dp(ir_instruction *ir,
800 st_dst_reg dst, st_src_reg src0, st_src_reg src1,
801 unsigned elements)
802 {
803 static const enum tgsi_opcode dot_opcodes[] = {
804 TGSI_OPCODE_DP2, TGSI_OPCODE_DP3, TGSI_OPCODE_DP4
805 };
806
807 return emit_asm(ir, dot_opcodes[elements - 2], dst, src0, src1);
808 }
809
810 /**
811 * Emits TGSI scalar opcodes to produce unique answers across channels.
812 *
813 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
814 * channel determines the result across all channels. So to do a vec4
815 * of this operation, we want to emit a scalar per source channel used
816 * to produce dest channels.
817 */
818 void
emit_scalar(ir_instruction * ir,enum tgsi_opcode op,st_dst_reg dst,st_src_reg orig_src0,st_src_reg orig_src1)819 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
820 st_dst_reg dst,
821 st_src_reg orig_src0, st_src_reg orig_src1)
822 {
823 int i, j;
824 int done_mask = ~dst.writemask;
825
826 /* TGSI RCP is a scalar operation splatting results to all channels,
827 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
828 * dst channels.
829 */
830 for (i = 0; i < 4; i++) {
831 GLuint this_mask = (1 << i);
832 st_src_reg src0 = orig_src0;
833 st_src_reg src1 = orig_src1;
834
835 if (done_mask & this_mask)
836 continue;
837
838 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
839 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
840 for (j = i + 1; j < 4; j++) {
841 /* If there is another enabled component in the destination that is
842 * derived from the same inputs, generate its value on this pass as
843 * well.
844 */
845 if (!(done_mask & (1 << j)) &&
846 GET_SWZ(src0.swizzle, j) == src0_swiz &&
847 GET_SWZ(src1.swizzle, j) == src1_swiz) {
848 this_mask |= (1 << j);
849 }
850 }
851 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
852 src0_swiz, src0_swiz);
853 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
854 src1_swiz, src1_swiz);
855
856 dst.writemask = this_mask;
857 emit_asm(ir, op, dst, src0, src1);
858 done_mask |= this_mask;
859 }
860 }
861
862 void
emit_scalar(ir_instruction * ir,enum tgsi_opcode op,st_dst_reg dst,st_src_reg src0)863 glsl_to_tgsi_visitor::emit_scalar(ir_instruction *ir, enum tgsi_opcode op,
864 st_dst_reg dst, st_src_reg src0)
865 {
866 st_src_reg undef = undef_src;
867
868 undef.swizzle = SWIZZLE_XXXX;
869
870 emit_scalar(ir, op, dst, src0, undef);
871 }
872
873 void
emit_arl(ir_instruction * ir,st_dst_reg dst,st_src_reg src0)874 glsl_to_tgsi_visitor::emit_arl(ir_instruction *ir,
875 st_dst_reg dst, st_src_reg src0)
876 {
877 enum tgsi_opcode op = TGSI_OPCODE_ARL;
878
879 if (src0.type == GLSL_TYPE_INT || src0.type == GLSL_TYPE_UINT) {
880 if (!this->need_uarl && src0.is_legal_tgsi_address_operand())
881 return;
882
883 op = TGSI_OPCODE_UARL;
884 }
885
886 assert(dst.file == PROGRAM_ADDRESS);
887 if (dst.index >= this->num_address_regs)
888 this->num_address_regs = dst.index + 1;
889
890 emit_asm(NULL, op, dst, src0);
891 }
892
893 int
add_constant(gl_register_file file,gl_constant_value values[8],int size,GLenum datatype,uint16_t * swizzle_out)894 glsl_to_tgsi_visitor::add_constant(gl_register_file file,
895 gl_constant_value values[8], int size,
896 GLenum datatype,
897 uint16_t *swizzle_out)
898 {
899 if (file == PROGRAM_CONSTANT) {
900 GLuint swizzle = swizzle_out ? *swizzle_out : 0;
901 int result = _mesa_add_typed_unnamed_constant(this->prog->Parameters,
902 values, size, datatype,
903 &swizzle);
904 if (swizzle_out)
905 *swizzle_out = swizzle;
906 return result;
907 }
908
909 assert(file == PROGRAM_IMMEDIATE);
910
911 int index = 0;
912 immediate_storage *entry;
913 int size32 = size * ((datatype == GL_DOUBLE ||
914 datatype == GL_INT64_ARB ||
915 datatype == GL_UNSIGNED_INT64_ARB) ? 2 : 1);
916 int i;
917
918 /* Search immediate storage to see if we already have an identical
919 * immediate that we can use instead of adding a duplicate entry.
920 */
921 foreach_in_list(immediate_storage, entry, &this->immediates) {
922 immediate_storage *tmp = entry;
923
924 for (i = 0; i * 4 < size32; i++) {
925 int slot_size = MIN2(size32 - (i * 4), 4);
926 if (tmp->type != datatype || tmp->size32 != slot_size)
927 break;
928 if (memcmp(tmp->values, &values[i * 4],
929 slot_size * sizeof(gl_constant_value)))
930 break;
931
932 /* Everything matches, keep going until the full size is matched */
933 tmp = (immediate_storage *)tmp->next;
934 }
935
936 /* The full value matched */
937 if (i * 4 >= size32)
938 return index;
939
940 index++;
941 }
942
943 for (i = 0; i * 4 < size32; i++) {
944 int slot_size = MIN2(size32 - (i * 4), 4);
945 /* Add this immediate to the list. */
946 entry = new(mem_ctx) immediate_storage(&values[i * 4],
947 slot_size, datatype);
948 this->immediates.push_tail(entry);
949 this->num_immediates++;
950 }
951 return index;
952 }
953
954 st_src_reg
st_src_reg_for_float(float val)955 glsl_to_tgsi_visitor::st_src_reg_for_float(float val)
956 {
957 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_FLOAT);
958 union gl_constant_value uval;
959
960 uval.f = val;
961 src.index = add_constant(src.file, &uval, 1, GL_FLOAT, &src.swizzle);
962
963 return src;
964 }
965
966 st_src_reg
st_src_reg_for_double(double val)967 glsl_to_tgsi_visitor::st_src_reg_for_double(double val)
968 {
969 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_DOUBLE);
970 union gl_constant_value uval[2];
971
972 memcpy(uval, &val, sizeof(uval));
973 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
974 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
975 return src;
976 }
977
978 st_src_reg
st_src_reg_for_int(int val)979 glsl_to_tgsi_visitor::st_src_reg_for_int(int val)
980 {
981 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT);
982 union gl_constant_value uval;
983
984 assert(native_integers);
985
986 uval.i = val;
987 src.index = add_constant(src.file, &uval, 1, GL_INT, &src.swizzle);
988
989 return src;
990 }
991
992 st_src_reg
st_src_reg_for_int64(int64_t val)993 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val)
994 {
995 st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64);
996 union gl_constant_value uval[2];
997
998 memcpy(uval, &val, sizeof(uval));
999 src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle);
1000 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y);
1001
1002 return src;
1003 }
1004
1005 st_src_reg
st_src_reg_for_type(enum glsl_base_type type,int val)1006 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val)
1007 {
1008 if (native_integers)
1009 return type == GLSL_TYPE_FLOAT ? st_src_reg_for_float(val) :
1010 st_src_reg_for_int(val);
1011 else
1012 return st_src_reg_for_float(val);
1013 }
1014
1015 static int
attrib_type_size(const struct glsl_type * type,bool is_vs_input)1016 attrib_type_size(const struct glsl_type *type, bool is_vs_input)
1017 {
1018 return type->count_attribute_slots(is_vs_input);
1019 }
1020
1021 static int
type_size(const struct glsl_type * type)1022 type_size(const struct glsl_type *type)
1023 {
1024 return type->count_attribute_slots(false);
1025 }
1026
1027 static void
add_buffer_to_load_and_stores(glsl_to_tgsi_instruction * inst,st_src_reg * buf,exec_list * instructions,ir_constant * access)1028 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction *inst, st_src_reg *buf,
1029 exec_list *instructions, ir_constant *access)
1030 {
1031 /**
1032 * emit_asm() might have actually split the op into pieces, e.g. for
1033 * double stores. We have to go back and fix up all the generated ops.
1034 */
1035 enum tgsi_opcode op = inst->op;
1036 do {
1037 inst->resource = *buf;
1038 if (access)
1039 inst->buffer_access = access->value.u[0];
1040
1041 if (inst == instructions->get_head_raw())
1042 break;
1043 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1044
1045 if (inst->op == TGSI_OPCODE_UADD) {
1046 if (inst == instructions->get_head_raw())
1047 break;
1048 inst = (glsl_to_tgsi_instruction *)inst->get_prev();
1049 }
1050 } while (inst->op == op && inst->resource.file == PROGRAM_UNDEFINED);
1051 }
1052
1053 /**
1054 * If the given GLSL type is an array or matrix or a structure containing
1055 * an array/matrix member, return true. Else return false.
1056 *
1057 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1058 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1059 * we have an array that might be indexed with a variable, we need to use
1060 * the later storage type.
1061 */
1062 static bool
type_has_array_or_matrix(const glsl_type * type)1063 type_has_array_or_matrix(const glsl_type *type)
1064 {
1065 if (type->is_array() || type->is_matrix())
1066 return true;
1067
1068 if (type->is_struct()) {
1069 for (unsigned i = 0; i < type->length; i++) {
1070 if (type_has_array_or_matrix(type->fields.structure[i].type)) {
1071 return true;
1072 }
1073 }
1074 }
1075
1076 return false;
1077 }
1078
1079
1080 /**
1081 * In the initial pass of codegen, we assign temporary numbers to
1082 * intermediate results. (not SSA -- variable assignments will reuse
1083 * storage).
1084 */
1085 st_src_reg
get_temp(const glsl_type * type)1086 glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
1087 {
1088 st_src_reg src;
1089
1090 src.type = native_integers ? type->base_type : GLSL_TYPE_FLOAT;
1091 src.reladdr = NULL;
1092 src.negate = 0;
1093 src.abs = 0;
1094
1095 if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
1096 if (next_array >= max_num_arrays) {
1097 max_num_arrays += 32;
1098 array_sizes = (unsigned*)
1099 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
1100 }
1101
1102 src.file = PROGRAM_ARRAY;
1103 src.index = 0;
1104 src.array_id = next_array + 1;
1105 array_sizes[next_array] = type_size(type);
1106 ++next_array;
1107
1108 } else {
1109 src.file = PROGRAM_TEMPORARY;
1110 src.index = next_temp;
1111 next_temp += type_size(type);
1112 }
1113
1114 if (type->is_array() || type->is_struct()) {
1115 src.swizzle = SWIZZLE_NOOP;
1116 } else {
1117 src.swizzle = swizzle_for_size(type->vector_elements);
1118 }
1119
1120 return src;
1121 }
1122
1123 variable_storage *
find_variable_storage(ir_variable * var)1124 glsl_to_tgsi_visitor::find_variable_storage(ir_variable *var)
1125 {
1126 struct hash_entry *entry;
1127
1128 entry = _mesa_hash_table_search(this->variables, var);
1129 if (!entry)
1130 return NULL;
1131
1132 return (variable_storage *)entry->data;
1133 }
1134
1135 void
visit(ir_variable * ir)1136 glsl_to_tgsi_visitor::visit(ir_variable *ir)
1137 {
1138 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
1139 unsigned int i;
1140 const ir_state_slot *const slots = ir->get_state_slots();
1141 assert(slots != NULL);
1142
1143 /* Check if this statevar's setup in the STATE file exactly
1144 * matches how we'll want to reference it as a
1145 * struct/array/whatever. If not, then we need to move it into
1146 * temporary storage and hope that it'll get copy-propagated
1147 * out.
1148 */
1149 for (i = 0; i < ir->get_num_state_slots(); i++) {
1150 if (slots[i].swizzle != SWIZZLE_XYZW) {
1151 break;
1152 }
1153 }
1154
1155 variable_storage *storage;
1156 st_dst_reg dst;
1157 if (i == ir->get_num_state_slots()) {
1158 /* We'll set the index later. */
1159 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
1160
1161 _mesa_hash_table_insert(this->variables, ir, storage);
1162
1163 dst = undef_dst;
1164 } else {
1165 /* The variable_storage constructor allocates slots based on the size
1166 * of the type. However, this had better match the number of state
1167 * elements that we're going to copy into the new temporary.
1168 */
1169 assert((int) ir->get_num_state_slots() == type_size(ir->type));
1170
1171 dst = st_dst_reg(get_temp(ir->type));
1172
1173 storage = new(mem_ctx) variable_storage(ir, dst.file, dst.index,
1174 dst.array_id);
1175
1176 _mesa_hash_table_insert(this->variables, ir, storage);
1177 }
1178
1179
1180 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
1181 int index = _mesa_add_state_reference(this->prog->Parameters,
1182 slots[i].tokens);
1183
1184 if (storage->file == PROGRAM_STATE_VAR) {
1185 if (storage->index == -1) {
1186 storage->index = index;
1187 } else {
1188 assert(index == storage->index + (int)i);
1189 }
1190 } else {
1191 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1192 * the data being moved since MOV does not care about the type of
1193 * data it is moving, and we don't want to declare registers with
1194 * array or struct types.
1195 */
1196 st_src_reg src(PROGRAM_STATE_VAR, index, GLSL_TYPE_FLOAT);
1197 src.swizzle = slots[i].swizzle;
1198 emit_asm(ir, TGSI_OPCODE_MOV, dst, src);
1199 /* even a float takes up a whole vec4 reg in a struct/array. */
1200 dst.index++;
1201 }
1202 }
1203
1204 if (storage->file == PROGRAM_TEMPORARY &&
1205 dst.index != storage->index + (int) ir->get_num_state_slots()) {
1206 fail_link(this->shader_program,
1207 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1208 ir->name, dst.index - storage->index,
1209 type_size(ir->type));
1210 }
1211 }
1212 }
1213
1214 void
visit(ir_loop * ir)1215 glsl_to_tgsi_visitor::visit(ir_loop *ir)
1216 {
1217 emit_asm(NULL, TGSI_OPCODE_BGNLOOP);
1218
1219 visit_exec_list(&ir->body_instructions, this);
1220
1221 emit_asm(NULL, TGSI_OPCODE_ENDLOOP);
1222 }
1223
1224 void
visit(ir_loop_jump * ir)1225 glsl_to_tgsi_visitor::visit(ir_loop_jump *ir)
1226 {
1227 switch (ir->mode) {
1228 case ir_loop_jump::jump_break:
1229 emit_asm(NULL, TGSI_OPCODE_BRK);
1230 break;
1231 case ir_loop_jump::jump_continue:
1232 emit_asm(NULL, TGSI_OPCODE_CONT);
1233 break;
1234 }
1235 }
1236
1237
1238 void
visit(ir_function_signature * ir)1239 glsl_to_tgsi_visitor::visit(ir_function_signature *ir)
1240 {
1241 assert(0);
1242 (void)ir;
1243 }
1244
1245 void
visit(ir_function * ir)1246 glsl_to_tgsi_visitor::visit(ir_function *ir)
1247 {
1248 /* Ignore function bodies other than main() -- we shouldn't see calls to
1249 * them since they should all be inlined before we get to glsl_to_tgsi.
1250 */
1251 if (strcmp(ir->name, "main") == 0) {
1252 const ir_function_signature *sig;
1253 exec_list empty;
1254
1255 sig = ir->matching_signature(NULL, &empty, false);
1256
1257 assert(sig);
1258
1259 foreach_in_list(ir_instruction, ir, &sig->body) {
1260 ir->accept(this);
1261 }
1262 }
1263 }
1264
1265 bool
try_emit_mad(ir_expression * ir,int mul_operand)1266 glsl_to_tgsi_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
1267 {
1268 int nonmul_operand = 1 - mul_operand;
1269 st_src_reg a, b, c;
1270 st_dst_reg result_dst;
1271
1272 // there is no TGSI opcode for this
1273 if (ir->type->is_integer_64())
1274 return false;
1275
1276 ir_expression *expr = ir->operands[mul_operand]->as_expression();
1277 if (!expr || expr->operation != ir_binop_mul)
1278 return false;
1279
1280 expr->operands[0]->accept(this);
1281 a = this->result;
1282 expr->operands[1]->accept(this);
1283 b = this->result;
1284 ir->operands[nonmul_operand]->accept(this);
1285 c = this->result;
1286
1287 this->result = get_temp(ir->type);
1288 result_dst = st_dst_reg(this->result);
1289 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1290 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, a, b, c);
1291
1292 return true;
1293 }
1294
1295 /**
1296 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1297 *
1298 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1299 * implemented using multiplication, and logical-or is implemented using
1300 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1301 * As result, the logical expression (a & !b) can be rewritten as:
1302 *
1303 * - a * !b
1304 * - a * (1 - b)
1305 * - (a * 1) - (a * b)
1306 * - a + -(a * b)
1307 * - a + (a * -b)
1308 *
1309 * This final expression can be implemented as a single MAD(a, -b, a)
1310 * instruction.
1311 */
1312 bool
try_emit_mad_for_and_not(ir_expression * ir,int try_operand)1313 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression *ir,
1314 int try_operand)
1315 {
1316 const int other_operand = 1 - try_operand;
1317 st_src_reg a, b;
1318
1319 ir_expression *expr = ir->operands[try_operand]->as_expression();
1320 if (!expr || expr->operation != ir_unop_logic_not)
1321 return false;
1322
1323 ir->operands[other_operand]->accept(this);
1324 a = this->result;
1325 expr->operands[0]->accept(this);
1326 b = this->result;
1327
1328 b.negate = ~b.negate;
1329
1330 this->result = get_temp(ir->type);
1331 emit_asm(ir, TGSI_OPCODE_MAD, st_dst_reg(this->result), a, b, a);
1332
1333 return true;
1334 }
1335
1336 void
reladdr_to_temp(ir_instruction * ir,st_src_reg * reg,int * num_reladdr)1337 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
1338 st_src_reg *reg, int *num_reladdr)
1339 {
1340 if (!reg->reladdr && !reg->reladdr2)
1341 return;
1342
1343 if (reg->reladdr)
1344 emit_arl(ir, address_reg, *reg->reladdr);
1345 if (reg->reladdr2)
1346 emit_arl(ir, address_reg2, *reg->reladdr2);
1347
1348 if (*num_reladdr != 1) {
1349 st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
1350
1351 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
1352 *reg = temp;
1353 }
1354
1355 (*num_reladdr)--;
1356 }
1357
1358 void
visit(ir_expression * ir)1359 glsl_to_tgsi_visitor::visit(ir_expression *ir)
1360 {
1361 st_src_reg op[ARRAY_SIZE(ir->operands)];
1362
1363 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1364 */
1365 if (!this->precise && ir->operation == ir_binop_add) {
1366 if (try_emit_mad(ir, 1))
1367 return;
1368 if (try_emit_mad(ir, 0))
1369 return;
1370 }
1371
1372 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1373 */
1374 if (!native_integers && ir->operation == ir_binop_logic_and) {
1375 if (try_emit_mad_for_and_not(ir, 1))
1376 return;
1377 if (try_emit_mad_for_and_not(ir, 0))
1378 return;
1379 }
1380
1381 if (ir->operation == ir_quadop_vector)
1382 assert(!"ir_quadop_vector should have been lowered");
1383
1384 for (unsigned int operand = 0; operand < ir->num_operands; operand++) {
1385 this->result.file = PROGRAM_UNDEFINED;
1386 ir->operands[operand]->accept(this);
1387 if (this->result.file == PROGRAM_UNDEFINED) {
1388 printf("Failed to get tree for expression operand:\n");
1389 ir->operands[operand]->print();
1390 printf("\n");
1391 exit(1);
1392 }
1393 op[operand] = this->result;
1394
1395 /* Matrix expression operands should have been broken down to vector
1396 * operations already.
1397 */
1398 assert(!ir->operands[operand]->type->is_matrix());
1399 }
1400
1401 visit_expression(ir, op);
1402 }
1403
1404 /* The non-recursive part of the expression visitor lives in a separate
1405 * function and should be prevented from being inlined, to avoid a stack
1406 * explosion when deeply nested expressions are visited.
1407 */
1408 void
visit_expression(ir_expression * ir,st_src_reg * op)1409 glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op)
1410 {
1411 st_src_reg result_src;
1412 st_dst_reg result_dst;
1413
1414 int vector_elements = ir->operands[0]->type->vector_elements;
1415 if (ir->operands[1] &&
1416 ir->operation != ir_binop_interpolate_at_offset &&
1417 ir->operation != ir_binop_interpolate_at_sample) {
1418 st_src_reg *swz_op = NULL;
1419 if (vector_elements > ir->operands[1]->type->vector_elements) {
1420 assert(ir->operands[1]->type->vector_elements == 1);
1421 swz_op = &op[1];
1422 } else if (vector_elements < ir->operands[1]->type->vector_elements) {
1423 assert(ir->operands[0]->type->vector_elements == 1);
1424 swz_op = &op[0];
1425 }
1426 if (swz_op) {
1427 uint16_t swizzle_x = GET_SWZ(swz_op->swizzle, 0);
1428 swz_op->swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1429 swizzle_x, swizzle_x);
1430 }
1431 vector_elements = MAX2(vector_elements,
1432 ir->operands[1]->type->vector_elements);
1433 }
1434 if (ir->operands[2] &&
1435 ir->operands[2]->type->vector_elements != vector_elements) {
1436 /* This can happen with ir_triop_lrp, i.e. glsl mix */
1437 assert(ir->operands[2]->type->vector_elements == 1);
1438 uint16_t swizzle_x = GET_SWZ(op[2].swizzle, 0);
1439 op[2].swizzle = MAKE_SWIZZLE4(swizzle_x, swizzle_x,
1440 swizzle_x, swizzle_x);
1441 }
1442
1443 this->result.file = PROGRAM_UNDEFINED;
1444
1445 /* Storage for our result. Ideally for an assignment we'd be using
1446 * the actual storage for the result here, instead.
1447 */
1448 result_src = get_temp(ir->type);
1449 /* convenience for the emit functions below. */
1450 result_dst = st_dst_reg(result_src);
1451 /* Limit writes to the channels that will be used by result_src later.
1452 * This does limit this temp's use as a temporary for multi-instruction
1453 * sequences.
1454 */
1455 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1456
1457 switch (ir->operation) {
1458 case ir_unop_logic_not:
1459 if (result_dst.type != GLSL_TYPE_FLOAT)
1460 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1461 else {
1462 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1463 * older GPUs implement SEQ using multiple instructions (i915 uses two
1464 * SGE instructions and a MUL instruction). Since our logic values are
1465 * 0.0 and 1.0, 1-x also implements !x.
1466 */
1467 op[0].negate = ~op[0].negate;
1468 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0],
1469 st_src_reg_for_float(1.0));
1470 }
1471 break;
1472 case ir_unop_neg:
1473 if (result_dst.type == GLSL_TYPE_INT64 ||
1474 result_dst.type == GLSL_TYPE_UINT64)
1475 emit_asm(ir, TGSI_OPCODE_I64NEG, result_dst, op[0]);
1476 else if (result_dst.type == GLSL_TYPE_INT ||
1477 result_dst.type == GLSL_TYPE_UINT)
1478 emit_asm(ir, TGSI_OPCODE_INEG, result_dst, op[0]);
1479 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1480 emit_asm(ir, TGSI_OPCODE_DNEG, result_dst, op[0]);
1481 else {
1482 op[0].negate = ~op[0].negate;
1483 result_src = op[0];
1484 }
1485 break;
1486 case ir_unop_subroutine_to_int:
1487 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1488 break;
1489 case ir_unop_abs:
1490 if (result_dst.type == GLSL_TYPE_FLOAT)
1491 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0].get_abs());
1492 else if (result_dst.type == GLSL_TYPE_DOUBLE)
1493 emit_asm(ir, TGSI_OPCODE_DABS, result_dst, op[0]);
1494 else if (result_dst.type == GLSL_TYPE_INT64 ||
1495 result_dst.type == GLSL_TYPE_UINT64)
1496 emit_asm(ir, TGSI_OPCODE_I64ABS, result_dst, op[0]);
1497 else
1498 emit_asm(ir, TGSI_OPCODE_IABS, result_dst, op[0]);
1499 break;
1500 case ir_unop_sign:
1501 emit_asm(ir, TGSI_OPCODE_SSG, result_dst, op[0]);
1502 break;
1503 case ir_unop_rcp:
1504 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, op[0]);
1505 break;
1506
1507 case ir_unop_exp2:
1508 emit_scalar(ir, TGSI_OPCODE_EX2, result_dst, op[0]);
1509 break;
1510 case ir_unop_exp:
1511 assert(!"not reached: should be handled by exp_to_exp2");
1512 break;
1513 case ir_unop_log:
1514 assert(!"not reached: should be handled by log_to_log2");
1515 break;
1516 case ir_unop_log2:
1517 emit_scalar(ir, TGSI_OPCODE_LG2, result_dst, op[0]);
1518 break;
1519 case ir_unop_sin:
1520 emit_scalar(ir, TGSI_OPCODE_SIN, result_dst, op[0]);
1521 break;
1522 case ir_unop_cos:
1523 emit_scalar(ir, TGSI_OPCODE_COS, result_dst, op[0]);
1524 break;
1525 case ir_unop_saturate: {
1526 glsl_to_tgsi_instruction *inst;
1527 inst = emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1528 inst->saturate = true;
1529 break;
1530 }
1531
1532 case ir_unop_dFdx:
1533 case ir_unop_dFdx_coarse:
1534 emit_asm(ir, TGSI_OPCODE_DDX, result_dst, op[0]);
1535 break;
1536 case ir_unop_dFdx_fine:
1537 emit_asm(ir, TGSI_OPCODE_DDX_FINE, result_dst, op[0]);
1538 break;
1539 case ir_unop_dFdy:
1540 case ir_unop_dFdy_coarse:
1541 case ir_unop_dFdy_fine:
1542 {
1543 /* The X component contains 1 or -1 depending on whether the framebuffer
1544 * is a FBO or the window system buffer, respectively.
1545 * It is then multiplied with the source operand of DDY.
1546 */
1547 static const gl_state_index16 transform_y_state[STATE_LENGTH]
1548 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
1549
1550 unsigned transform_y_index =
1551 _mesa_add_state_reference(this->prog->Parameters,
1552 transform_y_state);
1553
1554 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
1555 transform_y_index,
1556 glsl_type::vec4_type);
1557 transform_y.swizzle = SWIZZLE_XXXX;
1558
1559 st_src_reg temp = get_temp(glsl_type::vec4_type);
1560
1561 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(temp), transform_y, op[0]);
1562 emit_asm(ir, ir->operation == ir_unop_dFdy_fine ?
1563 TGSI_OPCODE_DDY_FINE : TGSI_OPCODE_DDY, result_dst, temp);
1564 break;
1565 }
1566
1567 case ir_unop_frexp_sig:
1568 emit_asm(ir, TGSI_OPCODE_DFRACEXP, result_dst, undef_dst, op[0]);
1569 break;
1570
1571 case ir_unop_frexp_exp:
1572 emit_asm(ir, TGSI_OPCODE_DFRACEXP, undef_dst, result_dst, op[0]);
1573 break;
1574
1575 case ir_binop_add:
1576 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1577 break;
1578 case ir_binop_sub:
1579 op[1].negate = ~op[1].negate;
1580 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1581 break;
1582
1583 case ir_binop_mul:
1584 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1585 break;
1586 case ir_binop_div:
1587 emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
1588 break;
1589 case ir_binop_mod:
1590 if (result_dst.type == GLSL_TYPE_FLOAT)
1591 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1592 else
1593 emit_asm(ir, TGSI_OPCODE_MOD, result_dst, op[0], op[1]);
1594 break;
1595
1596 case ir_binop_less:
1597 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, op[0], op[1]);
1598 break;
1599 case ir_binop_gequal:
1600 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, op[0], op[1]);
1601 break;
1602 case ir_binop_equal:
1603 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1604 break;
1605 case ir_binop_nequal:
1606 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1607 break;
1608 case ir_binop_all_equal:
1609 /* "==" operator producing a scalar boolean. */
1610 if (ir->operands[0]->type->is_vector() ||
1611 ir->operands[1]->type->is_vector()) {
1612 st_src_reg temp = get_temp(native_integers ?
1613 glsl_type::uvec4_type :
1614 glsl_type::vec4_type);
1615
1616 if (native_integers) {
1617 st_dst_reg temp_dst = st_dst_reg(temp);
1618 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1619
1620 if (ir->operands[0]->type->is_boolean() &&
1621 ir->operands[1]->as_constant() &&
1622 ir->operands[1]->as_constant()->is_one()) {
1623 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1624 } else {
1625 emit_asm(ir, TGSI_OPCODE_SEQ, st_dst_reg(temp), op[0], op[1]);
1626 }
1627
1628 /* Emit 1-3 AND operations to combine the SEQ results. */
1629 switch (ir->operands[0]->type->vector_elements) {
1630 case 2:
1631 break;
1632 case 3:
1633 temp_dst.writemask = WRITEMASK_Y;
1634 temp1.swizzle = SWIZZLE_YYYY;
1635 temp2.swizzle = SWIZZLE_ZZZZ;
1636 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1637 break;
1638 case 4:
1639 temp_dst.writemask = WRITEMASK_X;
1640 temp1.swizzle = SWIZZLE_XXXX;
1641 temp2.swizzle = SWIZZLE_YYYY;
1642 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1643 temp_dst.writemask = WRITEMASK_Y;
1644 temp1.swizzle = SWIZZLE_ZZZZ;
1645 temp2.swizzle = SWIZZLE_WWWW;
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2);
1647 }
1648
1649 temp1.swizzle = SWIZZLE_XXXX;
1650 temp2.swizzle = SWIZZLE_YYYY;
1651 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2);
1652 } else {
1653 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1654
1655 /* After the dot-product, the value will be an integer on the
1656 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1657 */
1658 emit_dp(ir, result_dst, temp, temp, vector_elements);
1659
1660 /* Negating the result of the dot-product gives values on the range
1661 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1662 * This is achieved using SGE.
1663 */
1664 st_src_reg sge_src = result_src;
1665 sge_src.negate = ~sge_src.negate;
1666 emit_asm(ir, TGSI_OPCODE_SGE, result_dst, sge_src,
1667 st_src_reg_for_float(0.0));
1668 }
1669 } else {
1670 emit_asm(ir, TGSI_OPCODE_SEQ, result_dst, op[0], op[1]);
1671 }
1672 break;
1673 case ir_binop_any_nequal:
1674 /* "!=" operator producing a scalar boolean. */
1675 if (ir->operands[0]->type->is_vector() ||
1676 ir->operands[1]->type->is_vector()) {
1677 st_src_reg temp = get_temp(native_integers ?
1678 glsl_type::uvec4_type :
1679 glsl_type::vec4_type);
1680 if (ir->operands[0]->type->is_boolean() &&
1681 ir->operands[1]->as_constant() &&
1682 ir->operands[1]->as_constant()->is_zero()) {
1683 emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), op[0]);
1684 } else {
1685 emit_asm(ir, TGSI_OPCODE_SNE, st_dst_reg(temp), op[0], op[1]);
1686 }
1687
1688 if (native_integers) {
1689 st_dst_reg temp_dst = st_dst_reg(temp);
1690 st_src_reg temp1 = st_src_reg(temp), temp2 = st_src_reg(temp);
1691
1692 /* Emit 1-3 OR operations to combine the SNE results. */
1693 switch (ir->operands[0]->type->vector_elements) {
1694 case 2:
1695 break;
1696 case 3:
1697 temp_dst.writemask = WRITEMASK_Y;
1698 temp1.swizzle = SWIZZLE_YYYY;
1699 temp2.swizzle = SWIZZLE_ZZZZ;
1700 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1701 break;
1702 case 4:
1703 temp_dst.writemask = WRITEMASK_X;
1704 temp1.swizzle = SWIZZLE_XXXX;
1705 temp2.swizzle = SWIZZLE_YYYY;
1706 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1707 temp_dst.writemask = WRITEMASK_Y;
1708 temp1.swizzle = SWIZZLE_ZZZZ;
1709 temp2.swizzle = SWIZZLE_WWWW;
1710 emit_asm(ir, TGSI_OPCODE_OR, temp_dst, temp1, temp2);
1711 }
1712
1713 temp1.swizzle = SWIZZLE_XXXX;
1714 temp2.swizzle = SWIZZLE_YYYY;
1715 emit_asm(ir, TGSI_OPCODE_OR, result_dst, temp1, temp2);
1716 } else {
1717 /* After the dot-product, the value will be an integer on the
1718 * range [0,4]. Zero stays zero, and positive values become 1.0.
1719 */
1720 glsl_to_tgsi_instruction *const dp =
1721 emit_dp(ir, result_dst, temp, temp, vector_elements);
1722 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1723 /* The clamping to [0,1] can be done for free in the fragment
1724 * shader with a saturate.
1725 */
1726 dp->saturate = true;
1727 } else {
1728 /* Negating the result of the dot-product gives values on the
1729 * range [-4, 0]. Zero stays zero, and negative values become
1730 * 1.0. This achieved using SLT.
1731 */
1732 st_src_reg slt_src = result_src;
1733 slt_src.negate = ~slt_src.negate;
1734 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1735 st_src_reg_for_float(0.0));
1736 }
1737 }
1738 } else {
1739 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1740 }
1741 break;
1742
1743 case ir_binop_logic_xor:
1744 if (native_integers)
1745 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1746 else
1747 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0], op[1]);
1748 break;
1749
1750 case ir_binop_logic_or: {
1751 if (native_integers) {
1752 /* If integers are used as booleans, we can use an actual "or"
1753 * instruction.
1754 */
1755 assert(native_integers);
1756 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1757 } else {
1758 /* After the addition, the value will be an integer on the
1759 * range [0,2]. Zero stays zero, and positive values become 1.0.
1760 */
1761 glsl_to_tgsi_instruction *add =
1762 emit_asm(ir, TGSI_OPCODE_ADD, result_dst, op[0], op[1]);
1763 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1764 /* The clamping to [0,1] can be done for free in the fragment
1765 * shader with a saturate if floats are being used as boolean
1766 * values.
1767 */
1768 add->saturate = true;
1769 } else {
1770 /* Negating the result of the addition gives values on the range
1771 * [-2, 0]. Zero stays zero, and negative values become 1.0
1772 * This is achieved using SLT.
1773 */
1774 st_src_reg slt_src = result_src;
1775 slt_src.negate = ~slt_src.negate;
1776 emit_asm(ir, TGSI_OPCODE_SLT, result_dst, slt_src,
1777 st_src_reg_for_float(0.0));
1778 }
1779 }
1780 break;
1781 }
1782
1783 case ir_binop_logic_and:
1784 /* If native integers are disabled, the bool args are stored as float 0.0
1785 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1786 * actual AND opcode.
1787 */
1788 if (native_integers)
1789 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1790 else
1791 emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
1792 break;
1793
1794 case ir_binop_dot:
1795 assert(ir->operands[0]->type->is_vector());
1796 assert(ir->operands[0]->type == ir->operands[1]->type);
1797 emit_dp(ir, result_dst, op[0], op[1],
1798 ir->operands[0]->type->vector_elements);
1799 break;
1800
1801 case ir_unop_sqrt:
1802 if (have_sqrt) {
1803 emit_scalar(ir, TGSI_OPCODE_SQRT, result_dst, op[0]);
1804 } else {
1805 /* This is the only instruction sequence that makes the game "Risen"
1806 * render correctly. ABS is not required for the game, but since GLSL
1807 * declares negative values as "undefined", allowing us to do whatever
1808 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1809 * behavior.
1810 */
1811 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0].get_abs());
1812 emit_scalar(ir, TGSI_OPCODE_RCP, result_dst, result_src);
1813 }
1814 break;
1815 case ir_unop_rsq:
1816 emit_scalar(ir, TGSI_OPCODE_RSQ, result_dst, op[0]);
1817 break;
1818 case ir_unop_i2f:
1819 if (native_integers) {
1820 emit_asm(ir, TGSI_OPCODE_I2F, result_dst, op[0]);
1821 break;
1822 }
1823 /* fallthrough to next case otherwise */
1824 case ir_unop_b2f:
1825 if (native_integers) {
1826 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1827 st_src_reg_for_float(1.0));
1828 break;
1829 }
1830 /* fallthrough to next case otherwise */
1831 case ir_unop_i2u:
1832 case ir_unop_u2i:
1833 case ir_unop_i642u64:
1834 case ir_unop_u642i64:
1835 /* Converting between signed and unsigned integers is a no-op. */
1836 result_src = op[0];
1837 result_src.type = result_dst.type;
1838 break;
1839 case ir_unop_b2i:
1840 if (native_integers) {
1841 /* Booleans are stored as integers using ~0 for true and 0 for false.
1842 * GLSL requires that int(bool) return 1 for true and 0 for false.
1843 * This conversion is done with AND, but it could be done with NEG.
1844 */
1845 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0],
1846 st_src_reg_for_int(1));
1847 } else {
1848 /* Booleans and integers are both stored as floats when native
1849 * integers are disabled.
1850 */
1851 result_src = op[0];
1852 }
1853 break;
1854 case ir_unop_f2i:
1855 if (native_integers)
1856 emit_asm(ir, TGSI_OPCODE_F2I, result_dst, op[0]);
1857 else
1858 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1859 break;
1860 case ir_unop_f2u:
1861 if (native_integers)
1862 emit_asm(ir, TGSI_OPCODE_F2U, result_dst, op[0]);
1863 else
1864 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1865 break;
1866 case ir_unop_bitcast_f2i:
1867 case ir_unop_bitcast_f2u:
1868 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1869 if (op[0].negate || op[0].abs)
1870 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
1871 else
1872 result_src = op[0];
1873 result_src.type = ir->operation == ir_unop_bitcast_f2i ? GLSL_TYPE_INT :
1874 GLSL_TYPE_UINT;
1875 break;
1876 case ir_unop_bitcast_i2f:
1877 case ir_unop_bitcast_u2f:
1878 result_src = op[0];
1879 result_src.type = GLSL_TYPE_FLOAT;
1880 break;
1881 case ir_unop_f2b:
1882 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1883 st_src_reg_for_float(0.0));
1884 break;
1885 case ir_unop_d2b:
1886 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1887 st_src_reg_for_double(0.0));
1888 break;
1889 case ir_unop_i2b:
1890 if (native_integers)
1891 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, op[0],
1892 st_src_reg_for_int(0));
1893 else
1894 emit_asm(ir, TGSI_OPCODE_SNE, result_dst, op[0],
1895 st_src_reg_for_float(0.0));
1896 break;
1897 case ir_unop_bitcast_u642d:
1898 case ir_unop_bitcast_i642d:
1899 result_src = op[0];
1900 result_src.type = GLSL_TYPE_DOUBLE;
1901 break;
1902 case ir_unop_bitcast_d2i64:
1903 result_src = op[0];
1904 result_src.type = GLSL_TYPE_INT64;
1905 break;
1906 case ir_unop_bitcast_d2u64:
1907 result_src = op[0];
1908 result_src.type = GLSL_TYPE_UINT64;
1909 break;
1910 case ir_unop_trunc:
1911 emit_asm(ir, TGSI_OPCODE_TRUNC, result_dst, op[0]);
1912 break;
1913 case ir_unop_ceil:
1914 emit_asm(ir, TGSI_OPCODE_CEIL, result_dst, op[0]);
1915 break;
1916 case ir_unop_floor:
1917 emit_asm(ir, TGSI_OPCODE_FLR, result_dst, op[0]);
1918 break;
1919 case ir_unop_round_even:
1920 emit_asm(ir, TGSI_OPCODE_ROUND, result_dst, op[0]);
1921 break;
1922 case ir_unop_fract:
1923 emit_asm(ir, TGSI_OPCODE_FRC, result_dst, op[0]);
1924 break;
1925
1926 case ir_binop_min:
1927 emit_asm(ir, TGSI_OPCODE_MIN, result_dst, op[0], op[1]);
1928 break;
1929 case ir_binop_max:
1930 emit_asm(ir, TGSI_OPCODE_MAX, result_dst, op[0], op[1]);
1931 break;
1932 case ir_binop_pow:
1933 emit_scalar(ir, TGSI_OPCODE_POW, result_dst, op[0], op[1]);
1934 break;
1935
1936 case ir_unop_bit_not:
1937 if (native_integers) {
1938 emit_asm(ir, TGSI_OPCODE_NOT, result_dst, op[0]);
1939 break;
1940 }
1941 /* fallthrough */
1942 case ir_unop_u2f:
1943 if (native_integers) {
1944 emit_asm(ir, TGSI_OPCODE_U2F, result_dst, op[0]);
1945 break;
1946 }
1947 /* fallthrough */
1948 case ir_binop_lshift:
1949 case ir_binop_rshift:
1950 if (native_integers) {
1951 enum tgsi_opcode opcode = ir->operation == ir_binop_lshift
1952 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR;
1953 st_src_reg count;
1954
1955 if (glsl_base_type_is_64bit(op[0].type)) {
1956 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1957 * 64 bits.
1958 */
1959 count = get_temp(glsl_type::u64vec(ir->operands[1]
1960 ->type->components()));
1961 emit_asm(ir, TGSI_OPCODE_U2I64, st_dst_reg(count), op[1]);
1962 } else {
1963 count = op[1];
1964 }
1965
1966 emit_asm(ir, opcode, result_dst, op[0], count);
1967 break;
1968 }
1969 /* fallthrough */
1970 case ir_binop_bit_and:
1971 if (native_integers) {
1972 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]);
1973 break;
1974 }
1975 /* fallthrough */
1976 case ir_binop_bit_xor:
1977 if (native_integers) {
1978 emit_asm(ir, TGSI_OPCODE_XOR, result_dst, op[0], op[1]);
1979 break;
1980 }
1981 /* fallthrough */
1982 case ir_binop_bit_or:
1983 if (native_integers) {
1984 emit_asm(ir, TGSI_OPCODE_OR, result_dst, op[0], op[1]);
1985 break;
1986 }
1987
1988 assert(!"GLSL 1.30 features unsupported");
1989 break;
1990
1991 case ir_binop_ubo_load: {
1992 if (ctx->Const.UseSTD430AsDefaultPacking) {
1993 ir_rvalue *block = ir->operands[0];
1994 ir_rvalue *offset = ir->operands[1];
1995 ir_constant *const_block = block->as_constant();
1996
1997 st_src_reg cbuf(PROGRAM_CONSTANT,
1998 (const_block ? const_block->value.u[0] + 1 : 1),
1999 ir->type->base_type);
2000
2001 cbuf.has_index2 = true;
2002
2003 if (!const_block) {
2004 block->accept(this);
2005 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2006 *cbuf.reladdr = this->result;
2007 emit_arl(ir, sampler_reladdr, this->result);
2008 }
2009
2010 /* Calculate the surface offset */
2011 offset->accept(this);
2012 st_src_reg off = this->result;
2013
2014 glsl_to_tgsi_instruction *inst =
2015 emit_asm(ir, TGSI_OPCODE_LOAD, result_dst, off);
2016
2017 if (result_dst.type == GLSL_TYPE_BOOL)
2018 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, st_src_reg(result_dst),
2019 st_src_reg_for_int(0));
2020
2021 add_buffer_to_load_and_stores(inst, &cbuf, &this->instructions,
2022 NULL);
2023 } else {
2024 ir_constant *const_uniform_block = ir->operands[0]->as_constant();
2025 ir_constant *const_offset_ir = ir->operands[1]->as_constant();
2026 unsigned const_offset = const_offset_ir ?
2027 const_offset_ir->value.u[0] : 0;
2028 unsigned const_block = const_uniform_block ?
2029 const_uniform_block->value.u[0] + 1 : 1;
2030 st_src_reg index_reg = get_temp(glsl_type::uint_type);
2031 st_src_reg cbuf;
2032
2033 cbuf.type = ir->type->base_type;
2034 cbuf.file = PROGRAM_CONSTANT;
2035 cbuf.index = 0;
2036 cbuf.reladdr = NULL;
2037 cbuf.negate = 0;
2038 cbuf.abs = 0;
2039 cbuf.index2D = const_block;
2040
2041 assert(ir->type->is_vector() || ir->type->is_scalar());
2042
2043 if (const_offset_ir) {
2044 /* Constant index into constant buffer */
2045 cbuf.reladdr = NULL;
2046 cbuf.index = const_offset / 16;
2047 } else {
2048 ir_expression *offset_expr = ir->operands[1]->as_expression();
2049 st_src_reg offset = op[1];
2050
2051 /* The OpenGL spec is written in such a way that accesses with
2052 * non-constant offset are almost always vec4-aligned. The only
2053 * exception to this are members of structs in arrays of structs:
2054 * each struct in an array of structs is at least vec4-aligned,
2055 * but single-element and [ui]vec2 members of the struct may be at
2056 * an offset that is not a multiple of 16 bytes.
2057 *
2058 * Here, we extract that offset, relying on previous passes to
2059 * always generate offset expressions of the form
2060 * (+ expr constant_offset).
2061 *
2062 * Note that the std430 layout, which allows more cases of
2063 * alignment less than vec4 in arrays, is not supported for
2064 * uniform blocks, so we do not have to deal with it here.
2065 */
2066 if (offset_expr && offset_expr->operation == ir_binop_add) {
2067 const_offset_ir = offset_expr->operands[1]->as_constant();
2068 if (const_offset_ir) {
2069 const_offset = const_offset_ir->value.u[0];
2070 cbuf.index = const_offset / 16;
2071 offset_expr->operands[0]->accept(this);
2072 offset = this->result;
2073 }
2074 }
2075
2076 /* Relative/variable index into constant buffer */
2077 emit_asm(ir, TGSI_OPCODE_USHR, st_dst_reg(index_reg), offset,
2078 st_src_reg_for_int(4));
2079 cbuf.reladdr = ralloc(mem_ctx, st_src_reg);
2080 *cbuf.reladdr = index_reg;
2081 }
2082
2083 if (const_uniform_block) {
2084 /* Constant constant buffer */
2085 cbuf.reladdr2 = NULL;
2086 } else {
2087 /* Relative/variable constant buffer */
2088 cbuf.reladdr2 = ralloc(mem_ctx, st_src_reg);
2089 *cbuf.reladdr2 = op[0];
2090 }
2091 cbuf.has_index2 = true;
2092
2093 cbuf.swizzle = swizzle_for_size(ir->type->vector_elements);
2094 if (glsl_base_type_is_64bit(cbuf.type))
2095 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 8,
2096 const_offset % 16 / 8,
2097 const_offset % 16 / 8,
2098 const_offset % 16 / 8);
2099 else
2100 cbuf.swizzle += MAKE_SWIZZLE4(const_offset % 16 / 4,
2101 const_offset % 16 / 4,
2102 const_offset % 16 / 4,
2103 const_offset % 16 / 4);
2104
2105 if (ir->type->is_boolean()) {
2106 emit_asm(ir, TGSI_OPCODE_USNE, result_dst, cbuf,
2107 st_src_reg_for_int(0));
2108 } else {
2109 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, cbuf);
2110 }
2111 }
2112 break;
2113 }
2114 case ir_triop_lrp:
2115 /* note: we have to reorder the three args here */
2116 emit_asm(ir, TGSI_OPCODE_LRP, result_dst, op[2], op[1], op[0]);
2117 break;
2118 case ir_triop_csel:
2119 if (this->ctx->Const.NativeIntegers)
2120 emit_asm(ir, TGSI_OPCODE_UCMP, result_dst, op[0], op[1], op[2]);
2121 else {
2122 op[0].negate = ~op[0].negate;
2123 emit_asm(ir, TGSI_OPCODE_CMP, result_dst, op[0], op[1], op[2]);
2124 }
2125 break;
2126 case ir_triop_bitfield_extract:
2127 emit_asm(ir, TGSI_OPCODE_IBFE, result_dst, op[0], op[1], op[2]);
2128 break;
2129 case ir_quadop_bitfield_insert:
2130 emit_asm(ir, TGSI_OPCODE_BFI, result_dst, op[0], op[1], op[2], op[3]);
2131 break;
2132 case ir_unop_bitfield_reverse:
2133 emit_asm(ir, TGSI_OPCODE_BREV, result_dst, op[0]);
2134 break;
2135 case ir_unop_bit_count:
2136 emit_asm(ir, TGSI_OPCODE_POPC, result_dst, op[0]);
2137 break;
2138 case ir_unop_find_msb:
2139 emit_asm(ir, TGSI_OPCODE_IMSB, result_dst, op[0]);
2140 break;
2141 case ir_unop_find_lsb:
2142 emit_asm(ir, TGSI_OPCODE_LSB, result_dst, op[0]);
2143 break;
2144 case ir_binop_imul_high:
2145 emit_asm(ir, TGSI_OPCODE_IMUL_HI, result_dst, op[0], op[1]);
2146 break;
2147 case ir_triop_fma:
2148 /* In theory, MAD is incorrect here. */
2149 if (have_fma)
2150 emit_asm(ir, TGSI_OPCODE_FMA, result_dst, op[0], op[1], op[2]);
2151 else
2152 emit_asm(ir, TGSI_OPCODE_MAD, result_dst, op[0], op[1], op[2]);
2153 break;
2154 case ir_unop_interpolate_at_centroid:
2155 emit_asm(ir, TGSI_OPCODE_INTERP_CENTROID, result_dst, op[0]);
2156 break;
2157 case ir_binop_interpolate_at_offset: {
2158 /* The y coordinate needs to be flipped for the default fb */
2159 static const gl_state_index16 transform_y_state[STATE_LENGTH]
2160 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM };
2161
2162 unsigned transform_y_index =
2163 _mesa_add_state_reference(this->prog->Parameters,
2164 transform_y_state);
2165
2166 st_src_reg transform_y = st_src_reg(PROGRAM_STATE_VAR,
2167 transform_y_index,
2168 glsl_type::vec4_type);
2169 transform_y.swizzle = SWIZZLE_XXXX;
2170
2171 st_src_reg temp = get_temp(glsl_type::vec2_type);
2172 st_dst_reg temp_dst = st_dst_reg(temp);
2173
2174 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[1]);
2175 temp_dst.writemask = WRITEMASK_Y;
2176 emit_asm(ir, TGSI_OPCODE_MUL, temp_dst, transform_y, op[1]);
2177 emit_asm(ir, TGSI_OPCODE_INTERP_OFFSET, result_dst, op[0], temp);
2178 break;
2179 }
2180 case ir_binop_interpolate_at_sample:
2181 emit_asm(ir, TGSI_OPCODE_INTERP_SAMPLE, result_dst, op[0], op[1]);
2182 break;
2183
2184 case ir_unop_d2f:
2185 emit_asm(ir, TGSI_OPCODE_D2F, result_dst, op[0]);
2186 break;
2187 case ir_unop_f2d:
2188 emit_asm(ir, TGSI_OPCODE_F2D, result_dst, op[0]);
2189 break;
2190 case ir_unop_d2i:
2191 emit_asm(ir, TGSI_OPCODE_D2I, result_dst, op[0]);
2192 break;
2193 case ir_unop_i2d:
2194 emit_asm(ir, TGSI_OPCODE_I2D, result_dst, op[0]);
2195 break;
2196 case ir_unop_d2u:
2197 emit_asm(ir, TGSI_OPCODE_D2U, result_dst, op[0]);
2198 break;
2199 case ir_unop_u2d:
2200 emit_asm(ir, TGSI_OPCODE_U2D, result_dst, op[0]);
2201 break;
2202 case ir_unop_unpack_double_2x32:
2203 case ir_unop_pack_double_2x32:
2204 case ir_unop_unpack_int_2x32:
2205 case ir_unop_pack_int_2x32:
2206 case ir_unop_unpack_uint_2x32:
2207 case ir_unop_pack_uint_2x32:
2208 case ir_unop_unpack_sampler_2x32:
2209 case ir_unop_pack_sampler_2x32:
2210 case ir_unop_unpack_image_2x32:
2211 case ir_unop_pack_image_2x32:
2212 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]);
2213 break;
2214
2215 case ir_binop_ldexp:
2216 if (ir->operands[0]->type->is_double()) {
2217 emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
2218 } else if (ir->operands[0]->type->is_float()) {
2219 emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
2220 } else {
2221 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2222 }
2223 break;
2224
2225 case ir_unop_pack_half_2x16:
2226 emit_asm(ir, TGSI_OPCODE_PK2H, result_dst, op[0]);
2227 break;
2228 case ir_unop_unpack_half_2x16:
2229 emit_asm(ir, TGSI_OPCODE_UP2H, result_dst, op[0]);
2230 break;
2231
2232 case ir_unop_get_buffer_size: {
2233 ir_constant *const_offset = ir->operands[0]->as_constant();
2234 st_src_reg buffer(
2235 PROGRAM_BUFFER,
2236 const_offset ? const_offset->value.u[0] : 0,
2237 GLSL_TYPE_UINT);
2238 if (!const_offset) {
2239 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
2240 *buffer.reladdr = op[0];
2241 emit_arl(ir, sampler_reladdr, op[0]);
2242 }
2243 emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
2244 break;
2245 }
2246
2247 case ir_unop_u2i64:
2248 case ir_unop_u2u64:
2249 case ir_unop_b2i64: {
2250 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2251 st_dst_reg temp_dst = st_dst_reg(temp);
2252 unsigned orig_swz = op[0].swizzle;
2253 /*
2254 * To convert unsigned to 64-bit:
2255 * zero Y channel, copy X channel.
2256 */
2257 temp_dst.writemask = WRITEMASK_Y;
2258 if (vector_elements > 1)
2259 temp_dst.writemask |= WRITEMASK_W;
2260 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2261 temp_dst.writemask = WRITEMASK_X;
2262 if (vector_elements > 1)
2263 temp_dst.writemask |= WRITEMASK_Z;
2264 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 0), GET_SWZ(orig_swz, 0),
2265 GET_SWZ(orig_swz, 1), GET_SWZ(orig_swz, 1));
2266 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2267 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2268 else
2269 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1));
2270 result_src = temp;
2271 result_src.type = GLSL_TYPE_UINT64;
2272 if (vector_elements > 2) {
2273 /* Subtle: We rely on the fact that get_temp here returns the next
2274 * TGSI temporary register directly after the temp register used for
2275 * the first two components, so that the result gets picked up
2276 * automatically.
2277 */
2278 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2279 st_dst_reg temp_dst = st_dst_reg(temp);
2280 temp_dst.writemask = WRITEMASK_Y;
2281 if (vector_elements > 3)
2282 temp_dst.writemask |= WRITEMASK_W;
2283 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, st_src_reg_for_int(0));
2284
2285 temp_dst.writemask = WRITEMASK_X;
2286 if (vector_elements > 3)
2287 temp_dst.writemask |= WRITEMASK_Z;
2288 op[0].swizzle = MAKE_SWIZZLE4(GET_SWZ(orig_swz, 2),
2289 GET_SWZ(orig_swz, 2),
2290 GET_SWZ(orig_swz, 3),
2291 GET_SWZ(orig_swz, 3));
2292 if (ir->operation == ir_unop_u2i64 || ir->operation == ir_unop_u2u64)
2293 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2294 else
2295 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0],
2296 st_src_reg_for_int(1));
2297 }
2298 break;
2299 }
2300 case ir_unop_i642i:
2301 case ir_unop_u642i:
2302 case ir_unop_u642u:
2303 case ir_unop_i642u: {
2304 st_src_reg temp = get_temp(glsl_type::uvec4_type);
2305 st_dst_reg temp_dst = st_dst_reg(temp);
2306 unsigned orig_swz = op[0].swizzle;
2307 unsigned orig_idx = op[0].index;
2308 int el;
2309 temp_dst.writemask = WRITEMASK_X;
2310
2311 for (el = 0; el < vector_elements; el++) {
2312 unsigned swz = GET_SWZ(orig_swz, el);
2313 if (swz & 1)
2314 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_Z,
2315 SWIZZLE_Z, SWIZZLE_Z);
2316 else
2317 op[0].swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
2318 SWIZZLE_X, SWIZZLE_X);
2319 if (swz > 2)
2320 op[0].index = orig_idx + 1;
2321 op[0].type = GLSL_TYPE_UINT;
2322 temp_dst.writemask = WRITEMASK_X << el;
2323 emit_asm(ir, TGSI_OPCODE_MOV, temp_dst, op[0]);
2324 }
2325 result_src = temp;
2326 if (ir->operation == ir_unop_u642u || ir->operation == ir_unop_i642u)
2327 result_src.type = GLSL_TYPE_UINT;
2328 else
2329 result_src.type = GLSL_TYPE_INT;
2330 break;
2331 }
2332 case ir_unop_i642b:
2333 emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0],
2334 st_src_reg_for_int64(0));
2335 break;
2336 case ir_unop_i642f:
2337 emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]);
2338 break;
2339 case ir_unop_u642f:
2340 emit_asm(ir, TGSI_OPCODE_U642F, result_dst, op[0]);
2341 break;
2342 case ir_unop_i642d:
2343 emit_asm(ir, TGSI_OPCODE_I642D, result_dst, op[0]);
2344 break;
2345 case ir_unop_u642d:
2346 emit_asm(ir, TGSI_OPCODE_U642D, result_dst, op[0]);
2347 break;
2348 case ir_unop_i2i64:
2349 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2350 break;
2351 case ir_unop_f2i64:
2352 emit_asm(ir, TGSI_OPCODE_F2I64, result_dst, op[0]);
2353 break;
2354 case ir_unop_d2i64:
2355 emit_asm(ir, TGSI_OPCODE_D2I64, result_dst, op[0]);
2356 break;
2357 case ir_unop_i2u64:
2358 emit_asm(ir, TGSI_OPCODE_I2I64, result_dst, op[0]);
2359 break;
2360 case ir_unop_f2u64:
2361 emit_asm(ir, TGSI_OPCODE_F2U64, result_dst, op[0]);
2362 break;
2363 case ir_unop_d2u64:
2364 emit_asm(ir, TGSI_OPCODE_D2U64, result_dst, op[0]);
2365 break;
2366 /* these might be needed */
2367 case ir_unop_pack_snorm_2x16:
2368 case ir_unop_pack_unorm_2x16:
2369 case ir_unop_pack_snorm_4x8:
2370 case ir_unop_pack_unorm_4x8:
2371
2372 case ir_unop_unpack_snorm_2x16:
2373 case ir_unop_unpack_unorm_2x16:
2374 case ir_unop_unpack_snorm_4x8:
2375 case ir_unop_unpack_unorm_4x8:
2376
2377 case ir_quadop_vector:
2378 case ir_binop_vector_extract:
2379 case ir_triop_vector_insert:
2380 case ir_binop_carry:
2381 case ir_binop_borrow:
2382 case ir_unop_ssbo_unsized_array_length:
2383 case ir_unop_atan:
2384 case ir_binop_atan2:
2385 case ir_unop_clz:
2386 case ir_binop_add_sat:
2387 case ir_binop_sub_sat:
2388 case ir_binop_abs_sub:
2389 case ir_binop_avg:
2390 case ir_binop_avg_round:
2391 case ir_binop_mul_32x16:
2392 case ir_unop_f162f:
2393 case ir_unop_f2f16:
2394 case ir_unop_f2fmp:
2395 case ir_unop_f162b:
2396 case ir_unop_b2f16:
2397 case ir_unop_i2i:
2398 case ir_unop_i2imp:
2399 case ir_unop_u2u:
2400 case ir_unop_u2ump:
2401 /* This operation is not supported, or should have already been handled.
2402 */
2403 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2404 break;
2405 }
2406
2407 this->result = result_src;
2408 }
2409
2410
2411 void
visit(ir_swizzle * ir)2412 glsl_to_tgsi_visitor::visit(ir_swizzle *ir)
2413 {
2414 st_src_reg src;
2415 int i;
2416 int swizzle[4] = {0};
2417
2418 /* Note that this is only swizzles in expressions, not those on the left
2419 * hand side of an assignment, which do write masking. See ir_assignment
2420 * for that.
2421 */
2422
2423 ir->val->accept(this);
2424 src = this->result;
2425 assert(src.file != PROGRAM_UNDEFINED);
2426 assert(ir->type->vector_elements > 0);
2427
2428 for (i = 0; i < 4; i++) {
2429 if (i < ir->type->vector_elements) {
2430 switch (i) {
2431 case 0:
2432 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
2433 break;
2434 case 1:
2435 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
2436 break;
2437 case 2:
2438 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
2439 break;
2440 case 3:
2441 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
2442 break;
2443 }
2444 } else {
2445 /* If the type is smaller than a vec4, replicate the last
2446 * channel out.
2447 */
2448 swizzle[i] = swizzle[ir->type->vector_elements - 1];
2449 }
2450 }
2451
2452 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2453
2454 this->result = src;
2455 }
2456
2457 /* Test if the variable is an array. Note that geometry and
2458 * tessellation shader inputs are outputs are always arrays (except
2459 * for patch inputs), so only the array element type is considered.
2460 */
2461 static bool
is_inout_array(unsigned stage,ir_variable * var,bool * remove_array)2462 is_inout_array(unsigned stage, ir_variable *var, bool *remove_array)
2463 {
2464 const glsl_type *type = var->type;
2465
2466 *remove_array = false;
2467
2468 if ((stage == MESA_SHADER_VERTEX && var->data.mode == ir_var_shader_in) ||
2469 (stage == MESA_SHADER_FRAGMENT && var->data.mode == ir_var_shader_out))
2470 return false;
2471
2472 if (((stage == MESA_SHADER_GEOMETRY && var->data.mode == ir_var_shader_in) ||
2473 (stage == MESA_SHADER_TESS_EVAL && var->data.mode == ir_var_shader_in) ||
2474 stage == MESA_SHADER_TESS_CTRL) &&
2475 !var->data.patch) {
2476 if (!var->type->is_array())
2477 return false; /* a system value probably */
2478
2479 type = var->type->fields.array;
2480 *remove_array = true;
2481 }
2482
2483 return type->is_array() || type->is_matrix();
2484 }
2485
2486 static unsigned
st_translate_interp_loc(ir_variable * var)2487 st_translate_interp_loc(ir_variable *var)
2488 {
2489 if (var->data.centroid)
2490 return TGSI_INTERPOLATE_LOC_CENTROID;
2491 else if (var->data.sample)
2492 return TGSI_INTERPOLATE_LOC_SAMPLE;
2493 else
2494 return TGSI_INTERPOLATE_LOC_CENTER;
2495 }
2496
2497 void
visit(ir_dereference_variable * ir)2498 glsl_to_tgsi_visitor::visit(ir_dereference_variable *ir)
2499 {
2500 variable_storage *entry;
2501 ir_variable *var = ir->var;
2502 bool remove_array;
2503
2504 if (handle_bound_deref(ir->as_dereference()))
2505 return;
2506
2507 entry = find_variable_storage(ir->var);
2508
2509 if (!entry) {
2510 switch (var->data.mode) {
2511 case ir_var_uniform:
2512 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
2513 var->data.param_index);
2514 _mesa_hash_table_insert(this->variables, var, entry);
2515 break;
2516 case ir_var_shader_in: {
2517 /* The linker assigns locations for varyings and attributes,
2518 * including deprecated builtins (like gl_Color), user-assign
2519 * generic attributes (glBindVertexLocation), and
2520 * user-defined varyings.
2521 */
2522 assert(var->data.location != -1);
2523
2524 const glsl_type *type_without_array = var->type->without_array();
2525 struct inout_decl *decl = &inputs[num_inputs];
2526 unsigned component = var->data.location_frac;
2527 unsigned num_components;
2528 num_inputs++;
2529
2530 if (type_without_array->is_64bit())
2531 component = component / 2;
2532 if (type_without_array->vector_elements)
2533 num_components = type_without_array->vector_elements;
2534 else
2535 num_components = 4;
2536
2537 decl->mesa_index = var->data.location;
2538 decl->interp = (glsl_interp_mode) var->data.interpolation;
2539 decl->interp_loc = st_translate_interp_loc(var);
2540 decl->base_type = type_without_array->base_type;
2541 decl->usage_mask = u_bit_consecutive(component, num_components);
2542
2543 if (is_inout_array(shader->Stage, var, &remove_array)) {
2544 decl->array_id = num_input_arrays + 1;
2545 num_input_arrays++;
2546 } else {
2547 decl->array_id = 0;
2548 }
2549
2550 if (remove_array)
2551 decl->size = type_size(var->type->fields.array);
2552 else
2553 decl->size = type_size(var->type);
2554
2555 entry = new(mem_ctx) variable_storage(var,
2556 PROGRAM_INPUT,
2557 decl->mesa_index,
2558 decl->array_id);
2559 entry->component = component;
2560
2561 _mesa_hash_table_insert(this->variables, var, entry);
2562
2563 break;
2564 }
2565 case ir_var_shader_out: {
2566 assert(var->data.location != -1);
2567
2568 const glsl_type *type_without_array = var->type->without_array();
2569 struct inout_decl *decl = &outputs[num_outputs];
2570 unsigned component = var->data.location_frac;
2571 unsigned num_components;
2572 num_outputs++;
2573
2574 decl->invariant = var->data.invariant;
2575
2576 if (type_without_array->is_64bit())
2577 component = component / 2;
2578 if (type_without_array->vector_elements)
2579 num_components = type_without_array->vector_elements;
2580 else
2581 num_components = 4;
2582
2583 decl->mesa_index = var->data.location + FRAG_RESULT_MAX * var->data.index;
2584 decl->base_type = type_without_array->base_type;
2585 decl->usage_mask = u_bit_consecutive(component, num_components);
2586 if (var->data.stream & (1u << 31)) {
2587 decl->gs_out_streams = var->data.stream & ~(1u << 31);
2588 } else {
2589 assert(var->data.stream < 4);
2590 decl->gs_out_streams = 0;
2591 for (unsigned i = 0; i < num_components; ++i)
2592 decl->gs_out_streams |= var->data.stream << (2 * (component + i));
2593 }
2594
2595 if (is_inout_array(shader->Stage, var, &remove_array)) {
2596 decl->array_id = num_output_arrays + 1;
2597 num_output_arrays++;
2598 } else {
2599 decl->array_id = 0;
2600 }
2601
2602 if (remove_array)
2603 decl->size = type_size(var->type->fields.array);
2604 else
2605 decl->size = type_size(var->type);
2606
2607 if (var->data.fb_fetch_output) {
2608 st_dst_reg dst = st_dst_reg(get_temp(var->type));
2609 st_src_reg src = st_src_reg(PROGRAM_OUTPUT, decl->mesa_index,
2610 var->type, component, decl->array_id);
2611 emit_asm(NULL, TGSI_OPCODE_FBFETCH, dst, src);
2612 entry = new(mem_ctx) variable_storage(var, dst.file, dst.index,
2613 dst.array_id);
2614 } else {
2615 entry = new(mem_ctx) variable_storage(var,
2616 PROGRAM_OUTPUT,
2617 decl->mesa_index,
2618 decl->array_id);
2619 }
2620 entry->component = component;
2621
2622 _mesa_hash_table_insert(this->variables, var, entry);
2623
2624 break;
2625 }
2626 case ir_var_system_value:
2627 entry = new(mem_ctx) variable_storage(var,
2628 PROGRAM_SYSTEM_VALUE,
2629 var->data.location);
2630 break;
2631 case ir_var_auto:
2632 case ir_var_temporary:
2633 st_src_reg src = get_temp(var->type);
2634
2635 entry = new(mem_ctx) variable_storage(var, src.file, src.index,
2636 src.array_id);
2637 _mesa_hash_table_insert(this->variables, var, entry);
2638
2639 break;
2640 }
2641
2642 if (!entry) {
2643 printf("Failed to make storage for %s\n", var->name);
2644 exit(1);
2645 }
2646 }
2647
2648 this->result = st_src_reg(entry->file, entry->index, var->type,
2649 entry->component, entry->array_id);
2650 if (this->shader->Stage == MESA_SHADER_VERTEX &&
2651 var->data.mode == ir_var_shader_in &&
2652 var->type->without_array()->is_double())
2653 this->result.is_double_vertex_input = true;
2654 if (!native_integers)
2655 this->result.type = GLSL_TYPE_FLOAT;
2656 }
2657
2658 static void
shrink_array_declarations(struct inout_decl * decls,unsigned count,GLbitfield64 * usage_mask,GLbitfield64 double_usage_mask,GLbitfield * patch_usage_mask)2659 shrink_array_declarations(struct inout_decl *decls, unsigned count,
2660 GLbitfield64* usage_mask,
2661 GLbitfield64 double_usage_mask,
2662 GLbitfield* patch_usage_mask)
2663 {
2664 unsigned i;
2665 int j;
2666
2667 /* Fix array declarations by removing unused array elements at both ends
2668 * of the arrays. For example, mat4[3] where only mat[1] is used.
2669 */
2670 for (i = 0; i < count; i++) {
2671 struct inout_decl *decl = &decls[i];
2672 if (!decl->array_id)
2673 continue;
2674
2675 /* Shrink the beginning. */
2676 for (j = 0; j < (int)decl->size; j++) {
2677 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2678 if (*patch_usage_mask &
2679 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2680 break;
2681 }
2682 else {
2683 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2684 break;
2685 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2686 break;
2687 }
2688
2689 decl->mesa_index++;
2690 decl->size--;
2691 j--;
2692 }
2693
2694 /* Shrink the end. */
2695 for (j = decl->size-1; j >= 0; j--) {
2696 if (decl->mesa_index >= VARYING_SLOT_PATCH0) {
2697 if (*patch_usage_mask &
2698 BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j))
2699 break;
2700 }
2701 else {
2702 if (*usage_mask & BITFIELD64_BIT(decl->mesa_index+j))
2703 break;
2704 if (double_usage_mask & BITFIELD64_BIT(decl->mesa_index+j-1))
2705 break;
2706 }
2707
2708 decl->size--;
2709 }
2710
2711 /* When not all entries of an array are accessed, we mark them as used
2712 * here anyway, to ensure that the input/output mapping logic doesn't get
2713 * confused.
2714 *
2715 * TODO This happens when an array isn't used via indirect access, which
2716 * some game ports do (at least eON-based). There is an optimization
2717 * opportunity here by replacing the array declaration with non-array
2718 * declarations of those slots that are actually used.
2719 */
2720 for (j = 1; j < (int)decl->size; ++j) {
2721 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2722 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2723 else
2724 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2725 }
2726 }
2727 }
2728
2729
2730 static void
mark_array_io(struct inout_decl * decls,unsigned count,GLbitfield64 * usage_mask,GLbitfield64 double_usage_mask,GLbitfield * patch_usage_mask)2731 mark_array_io(struct inout_decl *decls, unsigned count,
2732 GLbitfield64* usage_mask,
2733 GLbitfield64 double_usage_mask,
2734 GLbitfield* patch_usage_mask)
2735 {
2736 unsigned i;
2737 int j;
2738
2739 /* Fix array declarations by removing unused array elements at both ends
2740 * of the arrays. For example, mat4[3] where only mat[1] is used.
2741 */
2742 for (i = 0; i < count; i++) {
2743 struct inout_decl *decl = &decls[i];
2744 if (!decl->array_id)
2745 continue;
2746
2747 /* When not all entries of an array are accessed, we mark them as used
2748 * here anyway, to ensure that the input/output mapping logic doesn't get
2749 * confused.
2750 *
2751 * TODO This happens when an array isn't used via indirect access, which
2752 * some game ports do (at least eON-based). There is an optimization
2753 * opportunity here by replacing the array declaration with non-array
2754 * declarations of those slots that are actually used.
2755 */
2756 for (j = 0; j < (int)decl->size; ++j) {
2757 if (decl->mesa_index >= VARYING_SLOT_PATCH0)
2758 *patch_usage_mask |= BITFIELD64_BIT(decl->mesa_index - VARYING_SLOT_PATCH0 + j);
2759 else
2760 *usage_mask |= BITFIELD64_BIT(decl->mesa_index + j);
2761 }
2762 }
2763 }
2764
2765 void
visit(ir_dereference_array * ir)2766 glsl_to_tgsi_visitor::visit(ir_dereference_array *ir)
2767 {
2768 ir_constant *index;
2769 st_src_reg src;
2770 bool is_2D = false;
2771 ir_variable *var = ir->variable_referenced();
2772
2773 if (handle_bound_deref(ir->as_dereference()))
2774 return;
2775
2776 /* We only need the logic provided by count_vec4_slots()
2777 * for arrays of structs. Indirect sampler and image indexing is handled
2778 * elsewhere.
2779 */
2780 int element_size = ir->type->without_array()->is_struct() ?
2781 ir->type->count_vec4_slots(false, var->data.bindless) :
2782 type_size(ir->type);
2783
2784 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
2785
2786 ir->array->accept(this);
2787 src = this->result;
2788
2789 if (!src.has_index2) {
2790 switch (this->prog->Target) {
2791 case GL_TESS_CONTROL_PROGRAM_NV:
2792 is_2D = (src.file == PROGRAM_INPUT || src.file == PROGRAM_OUTPUT) &&
2793 !ir->variable_referenced()->data.patch;
2794 break;
2795 case GL_TESS_EVALUATION_PROGRAM_NV:
2796 is_2D = src.file == PROGRAM_INPUT &&
2797 !ir->variable_referenced()->data.patch;
2798 break;
2799 case GL_GEOMETRY_PROGRAM_NV:
2800 is_2D = src.file == PROGRAM_INPUT;
2801 break;
2802 }
2803 }
2804
2805 if (is_2D)
2806 element_size = 1;
2807
2808 if (index) {
2809
2810 if (this->prog->Target == GL_VERTEX_PROGRAM_ARB &&
2811 src.file == PROGRAM_INPUT)
2812 element_size = attrib_type_size(ir->type, true);
2813 if (is_2D) {
2814 src.index2D = index->value.i[0];
2815 src.has_index2 = true;
2816 } else
2817 src.index += index->value.i[0] * element_size;
2818 } else {
2819 /* Variable index array dereference. It eats the "vec4" of the
2820 * base of the array and an index that offsets the TGSI register
2821 * index.
2822 */
2823 ir->array_index->accept(this);
2824
2825 st_src_reg index_reg;
2826
2827 if (element_size == 1) {
2828 index_reg = this->result;
2829 } else {
2830 index_reg = get_temp(native_integers ?
2831 glsl_type::int_type : glsl_type::float_type);
2832
2833 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(index_reg),
2834 this->result, st_src_reg_for_type(index_reg.type, element_size));
2835 }
2836
2837 /* If there was already a relative address register involved, add the
2838 * new and the old together to get the new offset.
2839 */
2840 if (!is_2D && src.reladdr != NULL) {
2841 st_src_reg accum_reg = get_temp(native_integers ?
2842 glsl_type::int_type : glsl_type::float_type);
2843
2844 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(accum_reg),
2845 index_reg, *src.reladdr);
2846
2847 index_reg = accum_reg;
2848 }
2849
2850 if (is_2D) {
2851 src.reladdr2 = ralloc(mem_ctx, st_src_reg);
2852 *src.reladdr2 = index_reg;
2853 src.index2D = 0;
2854 src.has_index2 = true;
2855 } else {
2856 src.reladdr = ralloc(mem_ctx, st_src_reg);
2857 *src.reladdr = index_reg;
2858 }
2859 }
2860
2861 /* Change the register type to the element type of the array. */
2862 src.type = ir->type->base_type;
2863
2864 this->result = src;
2865 }
2866
2867 void
visit(ir_dereference_record * ir)2868 glsl_to_tgsi_visitor::visit(ir_dereference_record *ir)
2869 {
2870 unsigned int i;
2871 const glsl_type *struct_type = ir->record->type;
2872 ir_variable *var = ir->record->variable_referenced();
2873 int offset = 0;
2874
2875 if (handle_bound_deref(ir->as_dereference()))
2876 return;
2877
2878 ir->record->accept(this);
2879
2880 assert(ir->field_idx >= 0);
2881 assert(var);
2882 for (i = 0; i < struct_type->length; i++) {
2883 if (i == (unsigned) ir->field_idx)
2884 break;
2885 const glsl_type *member_type = struct_type->fields.structure[i].type;
2886 offset += member_type->count_vec4_slots(false, var->data.bindless);
2887 }
2888
2889 /* If the type is smaller than a vec4, replicate the last channel out. */
2890 if (ir->type->is_scalar() || ir->type->is_vector())
2891 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
2892 else
2893 this->result.swizzle = SWIZZLE_NOOP;
2894
2895 this->result.index += offset;
2896 this->result.type = ir->type->base_type;
2897 }
2898
2899 /**
2900 * We want to be careful in assignment setup to hit the actual storage
2901 * instead of potentially using a temporary like we might with the
2902 * ir_dereference handler.
2903 */
2904 static st_dst_reg
get_assignment_lhs(ir_dereference * ir,glsl_to_tgsi_visitor * v,int * component)2905 get_assignment_lhs(ir_dereference *ir, glsl_to_tgsi_visitor *v, int *component)
2906 {
2907 /* The LHS must be a dereference. If the LHS is a variable indexed array
2908 * access of a vector, it must be separated into a series conditional moves
2909 * before reaching this point (see ir_vec_index_to_cond_assign).
2910 */
2911 assert(ir->as_dereference());
2912 ir_dereference_array *deref_array = ir->as_dereference_array();
2913 if (deref_array) {
2914 assert(!deref_array->array->type->is_vector());
2915 }
2916
2917 /* Use the rvalue deref handler for the most part. We write swizzles using
2918 * the writemask, but we do extract the base component for enhanced layouts
2919 * from the source swizzle.
2920 */
2921 ir->accept(v);
2922 *component = GET_SWZ(v->result.swizzle, 0);
2923 return st_dst_reg(v->result);
2924 }
2925
2926 /**
2927 * Process the condition of a conditional assignment
2928 *
2929 * Examines the condition of a conditional assignment to generate the optimal
2930 * first operand of a \c CMP instruction. If the condition is a relational
2931 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2932 * used as the source for the \c CMP instruction. Otherwise the comparison
2933 * is processed to a boolean result, and the boolean result is used as the
2934 * operand to the CMP instruction.
2935 */
2936 bool
process_move_condition(ir_rvalue * ir)2937 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue *ir)
2938 {
2939 ir_rvalue *src_ir = ir;
2940 bool negate = true;
2941 bool switch_order = false;
2942
2943 ir_expression *const expr = ir->as_expression();
2944
2945 if (native_integers) {
2946 if ((expr != NULL) && (expr->num_operands == 2)) {
2947 enum glsl_base_type type = expr->operands[0]->type->base_type;
2948 if (type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT ||
2949 type == GLSL_TYPE_BOOL) {
2950 if (expr->operation == ir_binop_equal) {
2951 if (expr->operands[0]->is_zero()) {
2952 src_ir = expr->operands[1];
2953 switch_order = true;
2954 }
2955 else if (expr->operands[1]->is_zero()) {
2956 src_ir = expr->operands[0];
2957 switch_order = true;
2958 }
2959 }
2960 else if (expr->operation == ir_binop_nequal) {
2961 if (expr->operands[0]->is_zero()) {
2962 src_ir = expr->operands[1];
2963 }
2964 else if (expr->operands[1]->is_zero()) {
2965 src_ir = expr->operands[0];
2966 }
2967 }
2968 }
2969 }
2970
2971 src_ir->accept(this);
2972 return switch_order;
2973 }
2974
2975 if ((expr != NULL) && (expr->num_operands == 2)) {
2976 bool zero_on_left = false;
2977
2978 if (expr->operands[0]->is_zero()) {
2979 src_ir = expr->operands[1];
2980 zero_on_left = true;
2981 } else if (expr->operands[1]->is_zero()) {
2982 src_ir = expr->operands[0];
2983 zero_on_left = false;
2984 }
2985
2986 /* a is - 0 + - 0 +
2987 * (a < 0) T F F ( a < 0) T F F
2988 * (0 < a) F F T (-a < 0) F F T
2989 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2990 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2991 *
2992 * Note that exchanging the order of 0 and 'a' in the comparison simply
2993 * means that the value of 'a' should be negated.
2994 */
2995 if (src_ir != ir) {
2996 switch (expr->operation) {
2997 case ir_binop_less:
2998 switch_order = false;
2999 negate = zero_on_left;
3000 break;
3001
3002 case ir_binop_gequal:
3003 switch_order = true;
3004 negate = zero_on_left;
3005 break;
3006
3007 default:
3008 /* This isn't the right kind of comparison afterall, so make sure
3009 * the whole condition is visited.
3010 */
3011 src_ir = ir;
3012 break;
3013 }
3014 }
3015 }
3016
3017 src_ir->accept(this);
3018
3019 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3020 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3021 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3022 * computing the condition.
3023 */
3024 if (negate)
3025 this->result.negate = ~this->result.negate;
3026
3027 return switch_order;
3028 }
3029
3030 void
emit_block_mov(ir_assignment * ir,const struct glsl_type * type,st_dst_reg * l,st_src_reg * r,st_src_reg * cond,bool cond_swap)3031 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment *ir, const struct glsl_type *type,
3032 st_dst_reg *l, st_src_reg *r,
3033 st_src_reg *cond, bool cond_swap)
3034 {
3035 if (type->is_struct()) {
3036 for (unsigned int i = 0; i < type->length; i++) {
3037 emit_block_mov(ir, type->fields.structure[i].type, l, r,
3038 cond, cond_swap);
3039 }
3040 return;
3041 }
3042
3043 if (type->is_array()) {
3044 for (unsigned int i = 0; i < type->length; i++) {
3045 emit_block_mov(ir, type->fields.array, l, r, cond, cond_swap);
3046 }
3047 return;
3048 }
3049
3050 if (type->is_matrix()) {
3051 const struct glsl_type *vec_type;
3052
3053 vec_type = glsl_type::get_instance(type->is_double()
3054 ? GLSL_TYPE_DOUBLE : GLSL_TYPE_FLOAT,
3055 type->vector_elements, 1);
3056
3057 for (int i = 0; i < type->matrix_columns; i++) {
3058 emit_block_mov(ir, vec_type, l, r, cond, cond_swap);
3059 }
3060 return;
3061 }
3062
3063 assert(type->is_scalar() || type->is_vector());
3064
3065 l->type = type->base_type;
3066 r->type = type->base_type;
3067 if (cond) {
3068 st_src_reg l_src = st_src_reg(*l);
3069
3070 if (l_src.file == PROGRAM_OUTPUT &&
3071 this->prog->Target == GL_FRAGMENT_PROGRAM_ARB &&
3072 (l_src.index == FRAG_RESULT_DEPTH ||
3073 l_src.index == FRAG_RESULT_STENCIL)) {
3074 /* This is a special case because the source swizzles will be shifted
3075 * later to account for the difference between GLSL (where they're
3076 * plain floats) and TGSI (where they're Z and Y components). */
3077 l_src.swizzle = SWIZZLE_XXXX;
3078 }
3079
3080 if (native_integers) {
3081 emit_asm(ir, TGSI_OPCODE_UCMP, *l, *cond,
3082 cond_swap ? l_src : *r,
3083 cond_swap ? *r : l_src);
3084 } else {
3085 emit_asm(ir, TGSI_OPCODE_CMP, *l, *cond,
3086 cond_swap ? l_src : *r,
3087 cond_swap ? *r : l_src);
3088 }
3089 } else {
3090 emit_asm(ir, TGSI_OPCODE_MOV, *l, *r);
3091 }
3092 l->index++;
3093 r->index++;
3094 if (type->is_dual_slot()) {
3095 l->index++;
3096 if (r->is_double_vertex_input == false)
3097 r->index++;
3098 }
3099 }
3100
3101 void
visit(ir_assignment * ir)3102 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
3103 {
3104 int dst_component;
3105 st_dst_reg l;
3106 st_src_reg r;
3107
3108 /* all generated instructions need to be flaged as precise */
3109 this->precise = is_precise(ir->lhs->variable_referenced());
3110 ir->rhs->accept(this);
3111 r = this->result;
3112
3113 l = get_assignment_lhs(ir->lhs, this, &dst_component);
3114
3115 {
3116 int swizzles[4];
3117 int first_enabled_chan = 0;
3118 int rhs_chan = 0;
3119 ir_variable *variable = ir->lhs->variable_referenced();
3120
3121 if (shader->Stage == MESA_SHADER_FRAGMENT &&
3122 variable->data.mode == ir_var_shader_out &&
3123 (variable->data.location == FRAG_RESULT_DEPTH ||
3124 variable->data.location == FRAG_RESULT_STENCIL)) {
3125 assert(ir->lhs->type->is_scalar());
3126 assert(ir->write_mask == WRITEMASK_X);
3127
3128 if (variable->data.location == FRAG_RESULT_DEPTH)
3129 l.writemask = WRITEMASK_Z;
3130 else {
3131 assert(variable->data.location == FRAG_RESULT_STENCIL);
3132 l.writemask = WRITEMASK_Y;
3133 }
3134 } else if (ir->write_mask == 0) {
3135 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
3136
3137 unsigned num_elements =
3138 ir->lhs->type->without_array()->vector_elements;
3139
3140 if (num_elements) {
3141 l.writemask = u_bit_consecutive(0, num_elements);
3142 } else {
3143 /* The type is a struct or an array of (array of) structs. */
3144 l.writemask = WRITEMASK_XYZW;
3145 }
3146 } else {
3147 l.writemask = ir->write_mask;
3148 }
3149
3150 for (int i = 0; i < 4; i++) {
3151 if (l.writemask & (1 << i)) {
3152 first_enabled_chan = GET_SWZ(r.swizzle, i);
3153 break;
3154 }
3155 }
3156
3157 l.writemask = l.writemask << dst_component;
3158
3159 /* Swizzle a small RHS vector into the channels being written.
3160 *
3161 * glsl ir treats write_mask as dictating how many channels are
3162 * present on the RHS while TGSI treats write_mask as just
3163 * showing which channels of the vec4 RHS get written.
3164 */
3165 for (int i = 0; i < 4; i++) {
3166 if (l.writemask & (1 << i))
3167 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
3168 else
3169 swizzles[i] = first_enabled_chan;
3170 }
3171 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
3172 swizzles[2], swizzles[3]);
3173 }
3174
3175 assert(l.file != PROGRAM_UNDEFINED);
3176 assert(r.file != PROGRAM_UNDEFINED);
3177
3178 if (ir->condition) {
3179 const bool switch_order = this->process_move_condition(ir->condition);
3180 st_src_reg condition = this->result;
3181
3182 emit_block_mov(ir, ir->lhs->type, &l, &r, &condition, switch_order);
3183 } else if (ir->rhs->as_expression() &&
3184 this->instructions.get_tail() &&
3185 ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir &&
3186 !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded &&
3187 type_size(ir->lhs->type) == 1 &&
3188 l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) {
3189 /* To avoid emitting an extra MOV when assigning an expression to a
3190 * variable, emit the last instruction of the expression again, but
3191 * replace the destination register with the target of the assignment.
3192 * Dead code elimination will remove the original instruction.
3193 */
3194 glsl_to_tgsi_instruction *inst, *new_inst;
3195 inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
3196 new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1], inst->src[2], inst->src[3]);
3197 new_inst->saturate = inst->saturate;
3198 new_inst->resource = inst->resource;
3199 inst->dead_mask = inst->dst[0].writemask;
3200 } else {
3201 emit_block_mov(ir, ir->rhs->type, &l, &r, NULL, false);
3202 }
3203 this->precise = 0;
3204 }
3205
3206
3207 void
visit(ir_constant * ir)3208 glsl_to_tgsi_visitor::visit(ir_constant *ir)
3209 {
3210 st_src_reg src;
3211 GLdouble stack_vals[4] = { 0 };
3212 gl_constant_value *values = (gl_constant_value *) stack_vals;
3213 GLenum gl_type = GL_NONE;
3214 unsigned int i, elements;
3215 static int in_array = 0;
3216 gl_register_file file = in_array ? PROGRAM_CONSTANT : PROGRAM_IMMEDIATE;
3217
3218 /* Unfortunately, 4 floats is all we can get into
3219 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3220 * aggregate constant and move each constant value into it. If we
3221 * get lucky, copy propagation will eliminate the extra moves.
3222 */
3223 if (ir->type->is_struct()) {
3224 st_src_reg temp_base = get_temp(ir->type);
3225 st_dst_reg temp = st_dst_reg(temp_base);
3226
3227 for (i = 0; i < ir->type->length; i++) {
3228 ir_constant *const field_value = ir->get_record_field(i);
3229 int size = type_size(field_value->type);
3230
3231 assert(size > 0);
3232
3233 field_value->accept(this);
3234 src = this->result;
3235
3236 for (unsigned j = 0; j < (unsigned int)size; j++) {
3237 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3238
3239 src.index++;
3240 temp.index++;
3241 }
3242 }
3243 this->result = temp_base;
3244 return;
3245 }
3246
3247 if (ir->type->is_array()) {
3248 st_src_reg temp_base = get_temp(ir->type);
3249 st_dst_reg temp = st_dst_reg(temp_base);
3250 int size = type_size(ir->type->fields.array);
3251
3252 assert(size > 0);
3253 in_array++;
3254
3255 for (i = 0; i < ir->type->length; i++) {
3256 ir->const_elements[i]->accept(this);
3257 src = this->result;
3258 for (int j = 0; j < size; j++) {
3259 emit_asm(ir, TGSI_OPCODE_MOV, temp, src);
3260
3261 src.index++;
3262 temp.index++;
3263 }
3264 }
3265 this->result = temp_base;
3266 in_array--;
3267 return;
3268 }
3269
3270 if (ir->type->is_matrix()) {
3271 st_src_reg mat = get_temp(ir->type);
3272 st_dst_reg mat_column = st_dst_reg(mat);
3273
3274 for (i = 0; i < ir->type->matrix_columns; i++) {
3275 switch (ir->type->base_type) {
3276 case GLSL_TYPE_FLOAT:
3277 values = (gl_constant_value *)
3278 &ir->value.f[i * ir->type->vector_elements];
3279
3280 src = st_src_reg(file, -1, ir->type->base_type);
3281 src.index = add_constant(file,
3282 values,
3283 ir->type->vector_elements,
3284 GL_FLOAT,
3285 &src.swizzle);
3286 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3287 break;
3288 case GLSL_TYPE_DOUBLE:
3289 values = (gl_constant_value *)
3290 &ir->value.d[i * ir->type->vector_elements];
3291 src = st_src_reg(file, -1, ir->type->base_type);
3292 src.index = add_constant(file,
3293 values,
3294 ir->type->vector_elements,
3295 GL_DOUBLE,
3296 &src.swizzle);
3297 if (ir->type->vector_elements >= 2) {
3298 mat_column.writemask = WRITEMASK_XY;
3299 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3300 SWIZZLE_X, SWIZZLE_Y);
3301 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3302 } else {
3303 mat_column.writemask = WRITEMASK_X;
3304 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X,
3305 SWIZZLE_X, SWIZZLE_X);
3306 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3307 }
3308 src.index++;
3309 if (ir->type->vector_elements > 2) {
3310 if (ir->type->vector_elements == 4) {
3311 mat_column.writemask = WRITEMASK_ZW;
3312 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3313 SWIZZLE_X, SWIZZLE_Y);
3314 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3315 } else {
3316 mat_column.writemask = WRITEMASK_Z;
3317 src.swizzle = MAKE_SWIZZLE4(SWIZZLE_Y, SWIZZLE_Y,
3318 SWIZZLE_Y, SWIZZLE_Y);
3319 emit_asm(ir, TGSI_OPCODE_MOV, mat_column, src);
3320 mat_column.writemask = WRITEMASK_XYZW;
3321 src.swizzle = SWIZZLE_XYZW;
3322 }
3323 mat_column.index++;
3324 }
3325 break;
3326 default:
3327 unreachable("Illegal matrix constant type.\n");
3328 break;
3329 }
3330 mat_column.index++;
3331 }
3332 this->result = mat;
3333 return;
3334 }
3335
3336 elements = ir->type->vector_elements;
3337 switch (ir->type->base_type) {
3338 case GLSL_TYPE_FLOAT:
3339 gl_type = GL_FLOAT;
3340 for (i = 0; i < ir->type->vector_elements; i++) {
3341 values[i].f = ir->value.f[i];
3342 }
3343 break;
3344 case GLSL_TYPE_DOUBLE:
3345 gl_type = GL_DOUBLE;
3346 for (i = 0; i < ir->type->vector_elements; i++) {
3347 memcpy(&values[i * 2], &ir->value.d[i], sizeof(double));
3348 }
3349 break;
3350 case GLSL_TYPE_INT64:
3351 gl_type = GL_INT64_ARB;
3352 for (i = 0; i < ir->type->vector_elements; i++) {
3353 memcpy(&values[i * 2], &ir->value.d[i], sizeof(int64_t));
3354 }
3355 break;
3356 case GLSL_TYPE_UINT64:
3357 gl_type = GL_UNSIGNED_INT64_ARB;
3358 for (i = 0; i < ir->type->vector_elements; i++) {
3359 memcpy(&values[i * 2], &ir->value.d[i], sizeof(uint64_t));
3360 }
3361 break;
3362 case GLSL_TYPE_UINT:
3363 gl_type = native_integers ? GL_UNSIGNED_INT : GL_FLOAT;
3364 for (i = 0; i < ir->type->vector_elements; i++) {
3365 if (native_integers)
3366 values[i].u = ir->value.u[i];
3367 else
3368 values[i].f = ir->value.u[i];
3369 }
3370 break;
3371 case GLSL_TYPE_INT:
3372 gl_type = native_integers ? GL_INT : GL_FLOAT;
3373 for (i = 0; i < ir->type->vector_elements; i++) {
3374 if (native_integers)
3375 values[i].i = ir->value.i[i];
3376 else
3377 values[i].f = ir->value.i[i];
3378 }
3379 break;
3380 case GLSL_TYPE_BOOL:
3381 gl_type = native_integers ? GL_BOOL : GL_FLOAT;
3382 for (i = 0; i < ir->type->vector_elements; i++) {
3383 values[i].u = ir->value.b[i] ? ctx->Const.UniformBooleanTrue : 0;
3384 }
3385 break;
3386 case GLSL_TYPE_SAMPLER:
3387 case GLSL_TYPE_IMAGE:
3388 gl_type = GL_UNSIGNED_INT;
3389 elements = 2;
3390 values[0].u = ir->value.u64[0] & 0xffffffff;
3391 values[1].u = ir->value.u64[0] >> 32;
3392 break;
3393 default:
3394 assert(!"Non-float/uint/int/bool/sampler/image constant");
3395 }
3396
3397 this->result = st_src_reg(file, -1, ir->type);
3398 this->result.index = add_constant(file,
3399 values,
3400 elements,
3401 gl_type,
3402 &this->result.swizzle);
3403 }
3404
3405 void
visit_atomic_counter_intrinsic(ir_call * ir)3406 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
3407 {
3408 exec_node *param = ir->actual_parameters.get_head();
3409 ir_dereference *deref = static_cast<ir_dereference *>(param);
3410 ir_variable *location = deref->variable_referenced();
3411 bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
3412 /* Calculate the surface offset */
3413 st_src_reg offset;
3414 unsigned array_size = 0, base = 0;
3415 uint16_t index = 0;
3416 st_src_reg resource;
3417
3418 get_deref_offsets(deref, &array_size, &base, &index, &offset, false);
3419
3420 if (has_hw_atomics) {
3421 variable_storage *entry = find_variable_storage(location);
3422 st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT,
3423 location->data.binding);
3424
3425 if (!entry) {
3426 entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
3427 num_atomics);
3428 _mesa_hash_table_insert(this->variables, location, entry);
3429
3430 atomic_info[num_atomics].location = location->data.location;
3431 atomic_info[num_atomics].binding = location->data.binding;
3432 atomic_info[num_atomics].size = location->type->arrays_of_arrays_size();
3433 if (atomic_info[num_atomics].size == 0)
3434 atomic_info[num_atomics].size = 1;
3435 atomic_info[num_atomics].array_id = 0;
3436 num_atomics++;
3437 }
3438
3439 if (offset.file != PROGRAM_UNDEFINED) {
3440 if (atomic_info[entry->index].array_id == 0) {
3441 num_atomic_arrays++;
3442 atomic_info[entry->index].array_id = num_atomic_arrays;
3443 }
3444 buffer.array_id = atomic_info[entry->index].array_id;
3445 }
3446
3447 buffer.index = index;
3448 buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
3449 buffer.has_index2 = true;
3450
3451 if (offset.file != PROGRAM_UNDEFINED) {
3452 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3453 *buffer.reladdr = offset;
3454 emit_arl(ir, sampler_reladdr, offset);
3455 }
3456 offset = st_src_reg_for_int(0);
3457
3458 resource = buffer;
3459 } else {
3460 st_src_reg buffer(PROGRAM_BUFFER,
3461 prog->info.num_ssbos +
3462 location->data.binding,
3463 GLSL_TYPE_ATOMIC_UINT);
3464
3465 if (offset.file != PROGRAM_UNDEFINED) {
3466 emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
3467 offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
3468 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
3469 offset, st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE));
3470 } else {
3471 offset = st_src_reg_for_int(location->data.offset + index * ATOMIC_COUNTER_SIZE);
3472 }
3473 resource = buffer;
3474 }
3475
3476 ir->return_deref->accept(this);
3477 st_dst_reg dst(this->result);
3478 dst.writemask = WRITEMASK_X;
3479
3480 glsl_to_tgsi_instruction *inst;
3481
3482 if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_read) {
3483 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, offset);
3484 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_increment) {
3485 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3486 st_src_reg_for_int(1));
3487 } else if (ir->callee->intrinsic_id == ir_intrinsic_atomic_counter_predecrement) {
3488 inst = emit_asm(ir, TGSI_OPCODE_ATOMUADD, dst, offset,
3489 st_src_reg_for_int(-1));
3490 emit_asm(ir, TGSI_OPCODE_ADD, dst, this->result, st_src_reg_for_int(-1));
3491 } else {
3492 param = param->get_next();
3493 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3494 val->accept(this);
3495
3496 st_src_reg data = this->result, data2 = undef_src;
3497 enum tgsi_opcode opcode;
3498 switch (ir->callee->intrinsic_id) {
3499 case ir_intrinsic_atomic_counter_add:
3500 opcode = TGSI_OPCODE_ATOMUADD;
3501 break;
3502 case ir_intrinsic_atomic_counter_min:
3503 opcode = TGSI_OPCODE_ATOMIMIN;
3504 break;
3505 case ir_intrinsic_atomic_counter_max:
3506 opcode = TGSI_OPCODE_ATOMIMAX;
3507 break;
3508 case ir_intrinsic_atomic_counter_and:
3509 opcode = TGSI_OPCODE_ATOMAND;
3510 break;
3511 case ir_intrinsic_atomic_counter_or:
3512 opcode = TGSI_OPCODE_ATOMOR;
3513 break;
3514 case ir_intrinsic_atomic_counter_xor:
3515 opcode = TGSI_OPCODE_ATOMXOR;
3516 break;
3517 case ir_intrinsic_atomic_counter_exchange:
3518 opcode = TGSI_OPCODE_ATOMXCHG;
3519 break;
3520 case ir_intrinsic_atomic_counter_comp_swap: {
3521 opcode = TGSI_OPCODE_ATOMCAS;
3522 param = param->get_next();
3523 val = ((ir_instruction *)param)->as_rvalue();
3524 val->accept(this);
3525 data2 = this->result;
3526 break;
3527 }
3528 default:
3529 assert(!"Unexpected intrinsic");
3530 return;
3531 }
3532
3533 inst = emit_asm(ir, opcode, dst, offset, data, data2);
3534 }
3535
3536 inst->resource = resource;
3537 }
3538
3539 void
visit_ssbo_intrinsic(ir_call * ir)3540 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
3541 {
3542 exec_node *param = ir->actual_parameters.get_head();
3543
3544 ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
3545
3546 param = param->get_next();
3547 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3548
3549 ir_constant *const_block = block->as_constant();
3550 st_src_reg buffer(
3551 PROGRAM_BUFFER,
3552 const_block ? const_block->value.u[0] : 0,
3553 GLSL_TYPE_UINT);
3554
3555 if (!const_block) {
3556 block->accept(this);
3557 buffer.reladdr = ralloc(mem_ctx, st_src_reg);
3558 *buffer.reladdr = this->result;
3559 emit_arl(ir, sampler_reladdr, this->result);
3560 }
3561
3562 /* Calculate the surface offset */
3563 offset->accept(this);
3564 st_src_reg off = this->result;
3565
3566 st_dst_reg dst = undef_dst;
3567 if (ir->return_deref) {
3568 ir->return_deref->accept(this);
3569 dst = st_dst_reg(this->result);
3570 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3571 }
3572
3573 glsl_to_tgsi_instruction *inst;
3574
3575 if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_load) {
3576 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3577 if (dst.type == GLSL_TYPE_BOOL)
3578 emit_asm(ir, TGSI_OPCODE_USNE, dst, st_src_reg(dst),
3579 st_src_reg_for_int(0));
3580 } else if (ir->callee->intrinsic_id == ir_intrinsic_ssbo_store) {
3581 param = param->get_next();
3582 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3583 val->accept(this);
3584
3585 param = param->get_next();
3586 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3587 assert(write_mask);
3588 dst.writemask = write_mask->value.u[0];
3589
3590 dst.type = this->result.type;
3591 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3592 } else {
3593 param = param->get_next();
3594 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3595 val->accept(this);
3596
3597 st_src_reg data = this->result, data2 = undef_src;
3598 enum tgsi_opcode opcode;
3599 switch (ir->callee->intrinsic_id) {
3600 case ir_intrinsic_ssbo_atomic_add:
3601 opcode = TGSI_OPCODE_ATOMUADD;
3602 break;
3603 case ir_intrinsic_ssbo_atomic_min:
3604 opcode = TGSI_OPCODE_ATOMIMIN;
3605 break;
3606 case ir_intrinsic_ssbo_atomic_max:
3607 opcode = TGSI_OPCODE_ATOMIMAX;
3608 break;
3609 case ir_intrinsic_ssbo_atomic_and:
3610 opcode = TGSI_OPCODE_ATOMAND;
3611 break;
3612 case ir_intrinsic_ssbo_atomic_or:
3613 opcode = TGSI_OPCODE_ATOMOR;
3614 break;
3615 case ir_intrinsic_ssbo_atomic_xor:
3616 opcode = TGSI_OPCODE_ATOMXOR;
3617 break;
3618 case ir_intrinsic_ssbo_atomic_exchange:
3619 opcode = TGSI_OPCODE_ATOMXCHG;
3620 break;
3621 case ir_intrinsic_ssbo_atomic_comp_swap:
3622 opcode = TGSI_OPCODE_ATOMCAS;
3623 param = param->get_next();
3624 val = ((ir_instruction *)param)->as_rvalue();
3625 val->accept(this);
3626 data2 = this->result;
3627 break;
3628 default:
3629 assert(!"Unexpected intrinsic");
3630 return;
3631 }
3632
3633 inst = emit_asm(ir, opcode, dst, off, data, data2);
3634 }
3635
3636 param = param->get_next();
3637 ir_constant *access = NULL;
3638 if (!param->is_tail_sentinel()) {
3639 access = ((ir_instruction *)param)->as_constant();
3640 assert(access);
3641 }
3642
3643 add_buffer_to_load_and_stores(inst, &buffer, &this->instructions, access);
3644 }
3645
3646 void
visit_membar_intrinsic(ir_call * ir)3647 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
3648 {
3649 switch (ir->callee->intrinsic_id) {
3650 case ir_intrinsic_memory_barrier:
3651 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3652 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3653 TGSI_MEMBAR_ATOMIC_BUFFER |
3654 TGSI_MEMBAR_SHADER_IMAGE |
3655 TGSI_MEMBAR_SHARED));
3656 break;
3657 case ir_intrinsic_memory_barrier_atomic_counter:
3658 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3659 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER));
3660 break;
3661 case ir_intrinsic_memory_barrier_buffer:
3662 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3663 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER));
3664 break;
3665 case ir_intrinsic_memory_barrier_image:
3666 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3667 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE));
3668 break;
3669 case ir_intrinsic_memory_barrier_shared:
3670 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3671 st_src_reg_for_int(TGSI_MEMBAR_SHARED));
3672 break;
3673 case ir_intrinsic_group_memory_barrier:
3674 emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
3675 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
3676 TGSI_MEMBAR_ATOMIC_BUFFER |
3677 TGSI_MEMBAR_SHADER_IMAGE |
3678 TGSI_MEMBAR_SHARED |
3679 TGSI_MEMBAR_THREAD_GROUP));
3680 break;
3681 default:
3682 assert(!"Unexpected memory barrier intrinsic");
3683 }
3684 }
3685
3686 void
visit_shared_intrinsic(ir_call * ir)3687 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call *ir)
3688 {
3689 exec_node *param = ir->actual_parameters.get_head();
3690
3691 ir_rvalue *offset = ((ir_instruction *)param)->as_rvalue();
3692
3693 st_src_reg buffer(PROGRAM_MEMORY, 0, GLSL_TYPE_UINT);
3694
3695 /* Calculate the surface offset */
3696 offset->accept(this);
3697 st_src_reg off = this->result;
3698
3699 st_dst_reg dst = undef_dst;
3700 if (ir->return_deref) {
3701 ir->return_deref->accept(this);
3702 dst = st_dst_reg(this->result);
3703 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3704 }
3705
3706 glsl_to_tgsi_instruction *inst;
3707
3708 if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
3709 inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
3710 inst->resource = buffer;
3711 } else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
3712 param = param->get_next();
3713 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3714 val->accept(this);
3715
3716 param = param->get_next();
3717 ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
3718 assert(write_mask);
3719 dst.writemask = write_mask->value.u[0];
3720
3721 dst.type = this->result.type;
3722 inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
3723 inst->resource = buffer;
3724 } else {
3725 param = param->get_next();
3726 ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
3727 val->accept(this);
3728
3729 st_src_reg data = this->result, data2 = undef_src;
3730 enum tgsi_opcode opcode;
3731 switch (ir->callee->intrinsic_id) {
3732 case ir_intrinsic_shared_atomic_add:
3733 opcode = TGSI_OPCODE_ATOMUADD;
3734 break;
3735 case ir_intrinsic_shared_atomic_min:
3736 opcode = TGSI_OPCODE_ATOMIMIN;
3737 break;
3738 case ir_intrinsic_shared_atomic_max:
3739 opcode = TGSI_OPCODE_ATOMIMAX;
3740 break;
3741 case ir_intrinsic_shared_atomic_and:
3742 opcode = TGSI_OPCODE_ATOMAND;
3743 break;
3744 case ir_intrinsic_shared_atomic_or:
3745 opcode = TGSI_OPCODE_ATOMOR;
3746 break;
3747 case ir_intrinsic_shared_atomic_xor:
3748 opcode = TGSI_OPCODE_ATOMXOR;
3749 break;
3750 case ir_intrinsic_shared_atomic_exchange:
3751 opcode = TGSI_OPCODE_ATOMXCHG;
3752 break;
3753 case ir_intrinsic_shared_atomic_comp_swap:
3754 opcode = TGSI_OPCODE_ATOMCAS;
3755 param = param->get_next();
3756 val = ((ir_instruction *)param)->as_rvalue();
3757 val->accept(this);
3758 data2 = this->result;
3759 break;
3760 default:
3761 assert(!"Unexpected intrinsic");
3762 return;
3763 }
3764
3765 inst = emit_asm(ir, opcode, dst, off, data, data2);
3766 inst->resource = buffer;
3767 }
3768 }
3769
3770 static void
get_image_qualifiers(ir_dereference * ir,const glsl_type ** type,bool * memory_coherent,bool * memory_volatile,bool * memory_restrict,bool * memory_read_only,enum pipe_format * image_format)3771 get_image_qualifiers(ir_dereference *ir, const glsl_type **type,
3772 bool *memory_coherent, bool *memory_volatile,
3773 bool *memory_restrict, bool *memory_read_only,
3774 enum pipe_format *image_format)
3775 {
3776
3777 switch (ir->ir_type) {
3778 case ir_type_dereference_record: {
3779 ir_dereference_record *deref_record = ir->as_dereference_record();
3780 const glsl_type *struct_type = deref_record->record->type;
3781 int fild_idx = deref_record->field_idx;
3782
3783 *type = struct_type->fields.structure[fild_idx].type->without_array();
3784 *memory_coherent =
3785 struct_type->fields.structure[fild_idx].memory_coherent;
3786 *memory_volatile =
3787 struct_type->fields.structure[fild_idx].memory_volatile;
3788 *memory_restrict =
3789 struct_type->fields.structure[fild_idx].memory_restrict;
3790 *memory_read_only =
3791 struct_type->fields.structure[fild_idx].memory_read_only;
3792 *image_format =
3793 struct_type->fields.structure[fild_idx].image_format;
3794 break;
3795 }
3796
3797 case ir_type_dereference_array: {
3798 ir_dereference_array *deref_arr = ir->as_dereference_array();
3799 get_image_qualifiers((ir_dereference *)deref_arr->array, type,
3800 memory_coherent, memory_volatile, memory_restrict,
3801 memory_read_only, image_format);
3802 break;
3803 }
3804
3805 case ir_type_dereference_variable: {
3806 ir_variable *var = ir->variable_referenced();
3807
3808 *type = var->type->without_array();
3809 *memory_coherent = var->data.memory_coherent;
3810 *memory_volatile = var->data.memory_volatile;
3811 *memory_restrict = var->data.memory_restrict;
3812 *memory_read_only = var->data.memory_read_only;
3813 *image_format = var->data.image_format;
3814 break;
3815 }
3816
3817 default:
3818 break;
3819 }
3820 }
3821
3822 void
visit_image_intrinsic(ir_call * ir)3823 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call *ir)
3824 {
3825 exec_node *param = ir->actual_parameters.get_head();
3826
3827 ir_dereference *img = (ir_dereference *)param;
3828 const ir_variable *imgvar = img->variable_referenced();
3829 unsigned sampler_array_size = 1, sampler_base = 0;
3830 bool memory_coherent = false, memory_volatile = false,
3831 memory_restrict = false, memory_read_only = false;
3832 enum pipe_format image_format = PIPE_FORMAT_NONE;
3833 const glsl_type *type = NULL;
3834
3835 get_image_qualifiers(img, &type, &memory_coherent, &memory_volatile,
3836 &memory_restrict, &memory_read_only, &image_format);
3837
3838 st_src_reg reladdr;
3839 st_src_reg image(PROGRAM_IMAGE, 0, GLSL_TYPE_UINT);
3840 uint16_t index = 0;
3841 get_deref_offsets(img, &sampler_array_size, &sampler_base,
3842 &index, &reladdr, !imgvar->contains_bindless());
3843
3844 image.index = index;
3845 if (reladdr.file != PROGRAM_UNDEFINED) {
3846 image.reladdr = ralloc(mem_ctx, st_src_reg);
3847 *image.reladdr = reladdr;
3848 emit_arl(ir, sampler_reladdr, reladdr);
3849 }
3850
3851 st_dst_reg dst = undef_dst;
3852 if (ir->return_deref) {
3853 ir->return_deref->accept(this);
3854 dst = st_dst_reg(this->result);
3855 dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
3856 }
3857
3858 glsl_to_tgsi_instruction *inst;
3859
3860 st_src_reg bindless;
3861 if (imgvar->contains_bindless()) {
3862 img->accept(this);
3863 bindless = this->result;
3864 }
3865
3866 if (ir->callee->intrinsic_id == ir_intrinsic_image_size) {
3867 dst.writemask = WRITEMASK_XYZ;
3868 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dst);
3869 } else if (ir->callee->intrinsic_id == ir_intrinsic_image_samples) {
3870 st_src_reg res = get_temp(glsl_type::ivec4_type);
3871 st_dst_reg dstres = st_dst_reg(res);
3872 dstres.writemask = WRITEMASK_W;
3873 inst = emit_asm(ir, TGSI_OPCODE_RESQ, dstres);
3874 res.swizzle = SWIZZLE_WWWW;
3875 emit_asm(ir, TGSI_OPCODE_MOV, dst, res);
3876 } else {
3877 st_src_reg arg1 = undef_src, arg2 = undef_src;
3878 st_src_reg coord;
3879 st_dst_reg coord_dst;
3880 coord = get_temp(glsl_type::ivec4_type);
3881 coord_dst = st_dst_reg(coord);
3882 coord_dst.writemask = (1 << type->coordinate_components()) - 1;
3883 param = param->get_next();
3884 ((ir_dereference *)param)->accept(this);
3885 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
3886 coord.swizzle = SWIZZLE_XXXX;
3887 switch (type->coordinate_components()) {
3888 case 4: assert(!"unexpected coord count");
3889 /* fallthrough */
3890 case 3: coord.swizzle |= SWIZZLE_Z << 6;
3891 /* fallthrough */
3892 case 2: coord.swizzle |= SWIZZLE_Y << 3;
3893 }
3894
3895 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_MS) {
3896 param = param->get_next();
3897 ((ir_dereference *)param)->accept(this);
3898 st_src_reg sample = this->result;
3899 sample.swizzle = SWIZZLE_XXXX;
3900 coord_dst.writemask = WRITEMASK_W;
3901 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample);
3902 coord.swizzle |= SWIZZLE_W << 9;
3903 }
3904
3905 param = param->get_next();
3906 if (!param->is_tail_sentinel()) {
3907 ((ir_dereference *)param)->accept(this);
3908 arg1 = this->result;
3909 param = param->get_next();
3910 }
3911
3912 if (!param->is_tail_sentinel()) {
3913 ((ir_dereference *)param)->accept(this);
3914 arg2 = this->result;
3915 param = param->get_next();
3916 }
3917
3918 assert(param->is_tail_sentinel());
3919
3920 enum tgsi_opcode opcode;
3921 switch (ir->callee->intrinsic_id) {
3922 case ir_intrinsic_image_load:
3923 opcode = TGSI_OPCODE_LOAD;
3924 break;
3925 case ir_intrinsic_image_store:
3926 opcode = TGSI_OPCODE_STORE;
3927 break;
3928 case ir_intrinsic_image_atomic_add:
3929 opcode = TGSI_OPCODE_ATOMUADD;
3930 break;
3931 case ir_intrinsic_image_atomic_min:
3932 opcode = TGSI_OPCODE_ATOMIMIN;
3933 break;
3934 case ir_intrinsic_image_atomic_max:
3935 opcode = TGSI_OPCODE_ATOMIMAX;
3936 break;
3937 case ir_intrinsic_image_atomic_and:
3938 opcode = TGSI_OPCODE_ATOMAND;
3939 break;
3940 case ir_intrinsic_image_atomic_or:
3941 opcode = TGSI_OPCODE_ATOMOR;
3942 break;
3943 case ir_intrinsic_image_atomic_xor:
3944 opcode = TGSI_OPCODE_ATOMXOR;
3945 break;
3946 case ir_intrinsic_image_atomic_exchange:
3947 opcode = TGSI_OPCODE_ATOMXCHG;
3948 break;
3949 case ir_intrinsic_image_atomic_comp_swap:
3950 opcode = TGSI_OPCODE_ATOMCAS;
3951 break;
3952 case ir_intrinsic_image_atomic_inc_wrap: {
3953 /* There's a bit of disagreement between GLSL and the hardware. The
3954 * hardware wants to wrap after the given wrap value, while GLSL
3955 * wants to wrap at the value. Subtract 1 to make up the difference.
3956 */
3957 st_src_reg wrap = get_temp(glsl_type::uint_type);
3958 emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(wrap),
3959 arg1, st_src_reg_for_int(-1));
3960 arg1 = wrap;
3961 opcode = TGSI_OPCODE_ATOMINC_WRAP;
3962 break;
3963 }
3964 case ir_intrinsic_image_atomic_dec_wrap:
3965 opcode = TGSI_OPCODE_ATOMDEC_WRAP;
3966 break;
3967 default:
3968 assert(!"Unexpected intrinsic");
3969 return;
3970 }
3971
3972 inst = emit_asm(ir, opcode, dst, coord, arg1, arg2);
3973 if (opcode == TGSI_OPCODE_STORE)
3974 inst->dst[0].writemask = WRITEMASK_XYZW;
3975 }
3976
3977 if (imgvar->contains_bindless()) {
3978 inst->resource = bindless;
3979 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
3980 SWIZZLE_X, SWIZZLE_Y);
3981 } else {
3982 inst->resource = image;
3983 inst->sampler_array_size = sampler_array_size;
3984 inst->sampler_base = sampler_base;
3985 }
3986
3987 inst->tex_target = type->sampler_index();
3988 inst->image_format = image_format;
3989 inst->read_only = memory_read_only;
3990
3991 if (memory_coherent)
3992 inst->buffer_access |= TGSI_MEMORY_COHERENT;
3993 if (memory_restrict)
3994 inst->buffer_access |= TGSI_MEMORY_RESTRICT;
3995 if (memory_volatile)
3996 inst->buffer_access |= TGSI_MEMORY_VOLATILE;
3997 }
3998
3999 void
visit_generic_intrinsic(ir_call * ir,enum tgsi_opcode op)4000 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call *ir, enum tgsi_opcode op)
4001 {
4002 ir->return_deref->accept(this);
4003 st_dst_reg dst = st_dst_reg(this->result);
4004
4005 dst.writemask = u_bit_consecutive(0, ir->return_deref->var->type->vector_elements);
4006
4007 st_src_reg src[4] = { undef_src, undef_src, undef_src, undef_src };
4008 unsigned num_src = 0;
4009 foreach_in_list(ir_rvalue, param, &ir->actual_parameters) {
4010 assert(num_src < ARRAY_SIZE(src));
4011
4012 this->result.file = PROGRAM_UNDEFINED;
4013 param->accept(this);
4014 assert(this->result.file != PROGRAM_UNDEFINED);
4015
4016 src[num_src] = this->result;
4017 num_src++;
4018 }
4019
4020 emit_asm(ir, op, dst, src[0], src[1], src[2], src[3]);
4021 }
4022
4023 void
visit(ir_call * ir)4024 glsl_to_tgsi_visitor::visit(ir_call *ir)
4025 {
4026 ir_function_signature *sig = ir->callee;
4027
4028 /* Filter out intrinsics */
4029 switch (sig->intrinsic_id) {
4030 case ir_intrinsic_atomic_counter_read:
4031 case ir_intrinsic_atomic_counter_increment:
4032 case ir_intrinsic_atomic_counter_predecrement:
4033 case ir_intrinsic_atomic_counter_add:
4034 case ir_intrinsic_atomic_counter_min:
4035 case ir_intrinsic_atomic_counter_max:
4036 case ir_intrinsic_atomic_counter_and:
4037 case ir_intrinsic_atomic_counter_or:
4038 case ir_intrinsic_atomic_counter_xor:
4039 case ir_intrinsic_atomic_counter_exchange:
4040 case ir_intrinsic_atomic_counter_comp_swap:
4041 visit_atomic_counter_intrinsic(ir);
4042 return;
4043
4044 case ir_intrinsic_ssbo_load:
4045 case ir_intrinsic_ssbo_store:
4046 case ir_intrinsic_ssbo_atomic_add:
4047 case ir_intrinsic_ssbo_atomic_min:
4048 case ir_intrinsic_ssbo_atomic_max:
4049 case ir_intrinsic_ssbo_atomic_and:
4050 case ir_intrinsic_ssbo_atomic_or:
4051 case ir_intrinsic_ssbo_atomic_xor:
4052 case ir_intrinsic_ssbo_atomic_exchange:
4053 case ir_intrinsic_ssbo_atomic_comp_swap:
4054 visit_ssbo_intrinsic(ir);
4055 return;
4056
4057 case ir_intrinsic_memory_barrier:
4058 case ir_intrinsic_memory_barrier_atomic_counter:
4059 case ir_intrinsic_memory_barrier_buffer:
4060 case ir_intrinsic_memory_barrier_image:
4061 case ir_intrinsic_memory_barrier_shared:
4062 case ir_intrinsic_group_memory_barrier:
4063 visit_membar_intrinsic(ir);
4064 return;
4065
4066 case ir_intrinsic_shared_load:
4067 case ir_intrinsic_shared_store:
4068 case ir_intrinsic_shared_atomic_add:
4069 case ir_intrinsic_shared_atomic_min:
4070 case ir_intrinsic_shared_atomic_max:
4071 case ir_intrinsic_shared_atomic_and:
4072 case ir_intrinsic_shared_atomic_or:
4073 case ir_intrinsic_shared_atomic_xor:
4074 case ir_intrinsic_shared_atomic_exchange:
4075 case ir_intrinsic_shared_atomic_comp_swap:
4076 visit_shared_intrinsic(ir);
4077 return;
4078
4079 case ir_intrinsic_image_load:
4080 case ir_intrinsic_image_store:
4081 case ir_intrinsic_image_atomic_add:
4082 case ir_intrinsic_image_atomic_min:
4083 case ir_intrinsic_image_atomic_max:
4084 case ir_intrinsic_image_atomic_and:
4085 case ir_intrinsic_image_atomic_or:
4086 case ir_intrinsic_image_atomic_xor:
4087 case ir_intrinsic_image_atomic_exchange:
4088 case ir_intrinsic_image_atomic_comp_swap:
4089 case ir_intrinsic_image_size:
4090 case ir_intrinsic_image_samples:
4091 case ir_intrinsic_image_atomic_inc_wrap:
4092 case ir_intrinsic_image_atomic_dec_wrap:
4093 visit_image_intrinsic(ir);
4094 return;
4095
4096 case ir_intrinsic_shader_clock:
4097 visit_generic_intrinsic(ir, TGSI_OPCODE_CLOCK);
4098 return;
4099
4100 case ir_intrinsic_vote_all:
4101 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ALL);
4102 return;
4103 case ir_intrinsic_vote_any:
4104 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_ANY);
4105 return;
4106 case ir_intrinsic_vote_eq:
4107 visit_generic_intrinsic(ir, TGSI_OPCODE_VOTE_EQ);
4108 return;
4109 case ir_intrinsic_ballot:
4110 visit_generic_intrinsic(ir, TGSI_OPCODE_BALLOT);
4111 return;
4112 case ir_intrinsic_read_first_invocation:
4113 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_FIRST);
4114 return;
4115 case ir_intrinsic_read_invocation:
4116 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_INVOC);
4117 return;
4118
4119 case ir_intrinsic_helper_invocation:
4120 visit_generic_intrinsic(ir, TGSI_OPCODE_READ_HELPER);
4121 return;
4122
4123 case ir_intrinsic_invalid:
4124 case ir_intrinsic_generic_load:
4125 case ir_intrinsic_generic_store:
4126 case ir_intrinsic_generic_atomic_add:
4127 case ir_intrinsic_generic_atomic_and:
4128 case ir_intrinsic_generic_atomic_or:
4129 case ir_intrinsic_generic_atomic_xor:
4130 case ir_intrinsic_generic_atomic_min:
4131 case ir_intrinsic_generic_atomic_max:
4132 case ir_intrinsic_generic_atomic_exchange:
4133 case ir_intrinsic_generic_atomic_comp_swap:
4134 case ir_intrinsic_begin_invocation_interlock:
4135 case ir_intrinsic_end_invocation_interlock:
4136 unreachable("Invalid intrinsic");
4137 }
4138 }
4139
4140 void
calc_deref_offsets(ir_dereference * tail,unsigned * array_elements,uint16_t * index,st_src_reg * indirect,unsigned * location)4141 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
4142 unsigned *array_elements,
4143 uint16_t *index,
4144 st_src_reg *indirect,
4145 unsigned *location)
4146 {
4147 switch (tail->ir_type) {
4148 case ir_type_dereference_record: {
4149 ir_dereference_record *deref_record = tail->as_dereference_record();
4150 const glsl_type *struct_type = deref_record->record->type;
4151 int field_index = deref_record->field_idx;
4152
4153 calc_deref_offsets(deref_record->record->as_dereference(), array_elements, index, indirect, location);
4154
4155 assert(field_index >= 0);
4156 *location += struct_type->struct_location_offset(field_index);
4157 break;
4158 }
4159
4160 case ir_type_dereference_array: {
4161 ir_dereference_array *deref_arr = tail->as_dereference_array();
4162
4163 void *mem_ctx = ralloc_parent(deref_arr);
4164 ir_constant *array_index =
4165 deref_arr->array_index->constant_expression_value(mem_ctx);
4166
4167 if (!array_index) {
4168 st_src_reg temp_reg;
4169 st_dst_reg temp_dst;
4170
4171 temp_reg = get_temp(glsl_type::uint_type);
4172 temp_dst = st_dst_reg(temp_reg);
4173 temp_dst.writemask = 1;
4174
4175 deref_arr->array_index->accept(this);
4176 if (*array_elements != 1)
4177 emit_asm(NULL, TGSI_OPCODE_MUL, temp_dst, this->result, st_src_reg_for_int(*array_elements));
4178 else
4179 emit_asm(NULL, TGSI_OPCODE_MOV, temp_dst, this->result);
4180
4181 if (indirect->file == PROGRAM_UNDEFINED)
4182 *indirect = temp_reg;
4183 else {
4184 temp_dst = st_dst_reg(*indirect);
4185 temp_dst.writemask = 1;
4186 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
4187 }
4188 } else
4189 *index += array_index->value.u[0] * *array_elements;
4190
4191 *array_elements *= deref_arr->array->type->length;
4192
4193 calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, index, indirect, location);
4194 break;
4195 }
4196 default:
4197 break;
4198 }
4199 }
4200
4201 void
get_deref_offsets(ir_dereference * ir,unsigned * array_size,unsigned * base,uint16_t * index,st_src_reg * reladdr,bool opaque)4202 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
4203 unsigned *array_size,
4204 unsigned *base,
4205 uint16_t *index,
4206 st_src_reg *reladdr,
4207 bool opaque)
4208 {
4209 GLuint shader = _mesa_program_enum_to_shader_stage(this->prog->Target);
4210 unsigned location = 0;
4211 ir_variable *var = ir->variable_referenced();
4212
4213 reladdr->reset();
4214
4215 *base = 0;
4216 *array_size = 1;
4217
4218 assert(var);
4219 location = var->data.location;
4220 calc_deref_offsets(ir, array_size, index, reladdr, &location);
4221
4222 /*
4223 * If we end up with no indirect then adjust the base to the index,
4224 * and set the array size to 1.
4225 */
4226 if (reladdr->file == PROGRAM_UNDEFINED) {
4227 *base = *index;
4228 *array_size = 1;
4229 }
4230
4231 if (opaque) {
4232 assert(location != 0xffffffff);
4233 *base += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4234 *index += this->shader_program->data->UniformStorage[location].opaque[shader].index;
4235 }
4236 }
4237
4238 st_src_reg
canonicalize_gather_offset(st_src_reg offset)4239 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset)
4240 {
4241 if (offset.reladdr || offset.reladdr2 ||
4242 offset.has_index2 ||
4243 offset.file == PROGRAM_UNIFORM ||
4244 offset.file == PROGRAM_CONSTANT ||
4245 offset.file == PROGRAM_STATE_VAR) {
4246 st_src_reg tmp = get_temp(glsl_type::ivec2_type);
4247 st_dst_reg tmp_dst = st_dst_reg(tmp);
4248 tmp_dst.writemask = WRITEMASK_XY;
4249 emit_asm(NULL, TGSI_OPCODE_MOV, tmp_dst, offset);
4250 return tmp;
4251 }
4252
4253 return offset;
4254 }
4255
4256 bool
handle_bound_deref(ir_dereference * ir)4257 glsl_to_tgsi_visitor::handle_bound_deref(ir_dereference *ir)
4258 {
4259 ir_variable *var = ir->variable_referenced();
4260
4261 if (!var || var->data.mode != ir_var_uniform || var->data.bindless ||
4262 !(ir->type->is_image() || ir->type->is_sampler()))
4263 return false;
4264
4265 /* Convert from bound sampler/image to bindless handle. */
4266 bool is_image = ir->type->is_image();
4267 st_src_reg resource(is_image ? PROGRAM_IMAGE : PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4268 uint16_t index = 0;
4269 unsigned array_size = 1, base = 0;
4270 st_src_reg reladdr;
4271 get_deref_offsets(ir, &array_size, &base, &index, &reladdr, true);
4272
4273 resource.index = index;
4274 if (reladdr.file != PROGRAM_UNDEFINED) {
4275 resource.reladdr = ralloc(mem_ctx, st_src_reg);
4276 *resource.reladdr = reladdr;
4277 emit_arl(ir, sampler_reladdr, reladdr);
4278 }
4279
4280 this->result = get_temp(glsl_type::uvec2_type);
4281 st_dst_reg dst(this->result);
4282 dst.writemask = WRITEMASK_XY;
4283
4284 glsl_to_tgsi_instruction *inst = emit_asm(
4285 ir, is_image ? TGSI_OPCODE_IMG2HND : TGSI_OPCODE_SAMP2HND, dst);
4286
4287 inst->tex_target = ir->type->sampler_index();
4288 inst->resource = resource;
4289 inst->sampler_array_size = array_size;
4290 inst->sampler_base = base;
4291
4292 return true;
4293 }
4294
4295 void
visit(ir_texture * ir)4296 glsl_to_tgsi_visitor::visit(ir_texture *ir)
4297 {
4298 st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy;
4299 st_src_reg offset[MAX_GLSL_TEXTURE_OFFSET], sample_index, component;
4300 st_src_reg levels_src, reladdr;
4301 st_dst_reg result_dst, coord_dst, cube_sc_dst;
4302 glsl_to_tgsi_instruction *inst = NULL;
4303 enum tgsi_opcode opcode = TGSI_OPCODE_NOP;
4304 const glsl_type *sampler_type = ir->sampler->type;
4305 unsigned sampler_array_size = 1, sampler_base = 0;
4306 bool is_cube_array = false;
4307 ir_variable *var = ir->sampler->variable_referenced();
4308 unsigned i;
4309
4310 /* if we are a cube array sampler or a cube shadow */
4311 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4312 is_cube_array = sampler_type->sampler_array;
4313 }
4314
4315 if (ir->coordinate) {
4316 ir->coordinate->accept(this);
4317
4318 /* Put our coords in a temp. We'll need to modify them for shadow,
4319 * projection, or LOD, so the only case we'd use it as-is is if
4320 * we're doing plain old texturing. The optimization passes on
4321 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4322 */
4323 coord = get_temp(glsl_type::vec4_type);
4324 coord_dst = st_dst_reg(coord);
4325 coord_dst.writemask = (1 << ir->coordinate->type->vector_elements) - 1;
4326 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4327 }
4328
4329 if (ir->projector) {
4330 ir->projector->accept(this);
4331 projector = this->result;
4332 }
4333
4334 /* Storage for our result. Ideally for an assignment we'd be using
4335 * the actual storage for the result here, instead.
4336 */
4337 result_src = get_temp(ir->type);
4338 result_dst = st_dst_reg(result_src);
4339 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
4340
4341 switch (ir->op) {
4342 case ir_tex:
4343 opcode = (is_cube_array && ir->shadow_comparator) ? TGSI_OPCODE_TEX2 : TGSI_OPCODE_TEX;
4344 if (ir->offset) {
4345 ir->offset->accept(this);
4346 offset[0] = this->result;
4347 }
4348 break;
4349 case ir_txb:
4350 if (is_cube_array ||
4351 (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) {
4352 opcode = TGSI_OPCODE_TXB2;
4353 }
4354 else {
4355 opcode = TGSI_OPCODE_TXB;
4356 }
4357 ir->lod_info.bias->accept(this);
4358 lod_info = this->result;
4359 if (ir->offset) {
4360 ir->offset->accept(this);
4361 offset[0] = this->result;
4362 }
4363 break;
4364 case ir_txl:
4365 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4366 opcode = TGSI_OPCODE_TEX_LZ;
4367 } else {
4368 opcode = (is_cube_array || (sampler_type->sampler_shadow && sampler_type->coordinate_components() >= 3)) ? TGSI_OPCODE_TXL2 : TGSI_OPCODE_TXL;
4369 ir->lod_info.lod->accept(this);
4370 lod_info = this->result;
4371 }
4372 if (ir->offset) {
4373 ir->offset->accept(this);
4374 offset[0] = this->result;
4375 }
4376 break;
4377 case ir_txd:
4378 opcode = TGSI_OPCODE_TXD;
4379 ir->lod_info.grad.dPdx->accept(this);
4380 dx = this->result;
4381 ir->lod_info.grad.dPdy->accept(this);
4382 dy = this->result;
4383 if (ir->offset) {
4384 ir->offset->accept(this);
4385 offset[0] = this->result;
4386 }
4387 break;
4388 case ir_txs:
4389 opcode = TGSI_OPCODE_TXQ;
4390 ir->lod_info.lod->accept(this);
4391 lod_info = this->result;
4392 break;
4393 case ir_query_levels:
4394 opcode = TGSI_OPCODE_TXQ;
4395 lod_info = undef_src;
4396 levels_src = get_temp(ir->type);
4397 break;
4398 case ir_txf:
4399 if (this->has_tex_txf_lz && ir->lod_info.lod->is_zero()) {
4400 opcode = TGSI_OPCODE_TXF_LZ;
4401 } else {
4402 opcode = TGSI_OPCODE_TXF;
4403 ir->lod_info.lod->accept(this);
4404 lod_info = this->result;
4405 }
4406 if (ir->offset) {
4407 ir->offset->accept(this);
4408 offset[0] = this->result;
4409 }
4410 break;
4411 case ir_txf_ms:
4412 opcode = TGSI_OPCODE_TXF;
4413 ir->lod_info.sample_index->accept(this);
4414 sample_index = this->result;
4415 break;
4416 case ir_tg4:
4417 opcode = TGSI_OPCODE_TG4;
4418 ir->lod_info.component->accept(this);
4419 component = this->result;
4420 if (ir->offset) {
4421 ir->offset->accept(this);
4422 if (ir->offset->type->is_array()) {
4423 const glsl_type *elt_type = ir->offset->type->fields.array;
4424 for (i = 0; i < ir->offset->type->length; i++) {
4425 offset[i] = this->result;
4426 offset[i].index += i * type_size(elt_type);
4427 offset[i].type = elt_type->base_type;
4428 offset[i].swizzle = swizzle_for_size(elt_type->vector_elements);
4429 offset[i] = canonicalize_gather_offset(offset[i]);
4430 }
4431 } else {
4432 offset[0] = canonicalize_gather_offset(this->result);
4433 }
4434 }
4435 break;
4436 case ir_lod:
4437 opcode = TGSI_OPCODE_LODQ;
4438 break;
4439 case ir_texture_samples:
4440 opcode = TGSI_OPCODE_TXQS;
4441 break;
4442 case ir_samples_identical:
4443 unreachable("Unexpected ir_samples_identical opcode");
4444 }
4445
4446 if (ir->projector) {
4447 if (opcode == TGSI_OPCODE_TEX) {
4448 /* Slot the projector in as the last component of the coord. */
4449 coord_dst.writemask = WRITEMASK_W;
4450 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, projector);
4451 coord_dst.writemask = WRITEMASK_XYZW;
4452 opcode = TGSI_OPCODE_TXP;
4453 } else {
4454 st_src_reg coord_w = coord;
4455 coord_w.swizzle = SWIZZLE_WWWW;
4456
4457 /* For the other TEX opcodes there's no projective version
4458 * since the last slot is taken up by LOD info. Do the
4459 * projective divide now.
4460 */
4461 coord_dst.writemask = WRITEMASK_W;
4462 emit_asm(ir, TGSI_OPCODE_RCP, coord_dst, projector);
4463
4464 /* In the case where we have to project the coordinates "by hand,"
4465 * the shadow comparator value must also be projected.
4466 */
4467 st_src_reg tmp_src = coord;
4468 if (ir->shadow_comparator) {
4469 /* Slot the shadow value in as the second to last component of the
4470 * coord.
4471 */
4472 ir->shadow_comparator->accept(this);
4473
4474 tmp_src = get_temp(glsl_type::vec4_type);
4475 st_dst_reg tmp_dst = st_dst_reg(tmp_src);
4476
4477 /* Projective division not allowed for array samplers. */
4478 assert(!sampler_type->sampler_array);
4479
4480 tmp_dst.writemask = WRITEMASK_Z;
4481 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, this->result);
4482
4483 tmp_dst.writemask = WRITEMASK_XY;
4484 emit_asm(ir, TGSI_OPCODE_MOV, tmp_dst, coord);
4485 }
4486
4487 coord_dst.writemask = WRITEMASK_XYZ;
4488 emit_asm(ir, TGSI_OPCODE_MUL, coord_dst, tmp_src, coord_w);
4489
4490 coord_dst.writemask = WRITEMASK_XYZW;
4491 coord.swizzle = SWIZZLE_XYZW;
4492 }
4493 }
4494
4495 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the
4496 * shadow comparator was put in the correct place (and projected) by the
4497 * code, above, that handles by-hand projection.
4498 */
4499 if (ir->shadow_comparator && (!ir->projector || opcode == TGSI_OPCODE_TXP)) {
4500 /* Slot the shadow value in as the second to last component of the
4501 * coord.
4502 */
4503 ir->shadow_comparator->accept(this);
4504
4505 if (is_cube_array) {
4506 if (lod_info.file != PROGRAM_UNDEFINED) {
4507 // If we have both a cube array *and* a bias/lod, stick the
4508 // comparator into the .Y of the second argument.
4509 st_src_reg tmp = get_temp(glsl_type::vec2_type);
4510 cube_sc_dst = st_dst_reg(tmp);
4511 cube_sc_dst.writemask = WRITEMASK_X;
4512 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, lod_info);
4513 lod_info = tmp;
4514 cube_sc_dst.writemask = WRITEMASK_Y;
4515 } else {
4516 cube_sc = get_temp(glsl_type::float_type);
4517 cube_sc_dst = st_dst_reg(cube_sc);
4518 cube_sc_dst.writemask = WRITEMASK_X;
4519 }
4520 emit_asm(ir, TGSI_OPCODE_MOV, cube_sc_dst, this->result);
4521 }
4522 else {
4523 if ((sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
4524 sampler_type->sampler_array) ||
4525 sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE) {
4526 coord_dst.writemask = WRITEMASK_W;
4527 } else {
4528 coord_dst.writemask = WRITEMASK_Z;
4529 }
4530 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, this->result);
4531 coord_dst.writemask = WRITEMASK_XYZW;
4532 }
4533 }
4534
4535 if (ir->op == ir_txf_ms) {
4536 coord_dst.writemask = WRITEMASK_W;
4537 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, sample_index);
4538 coord_dst.writemask = WRITEMASK_XYZW;
4539 } else if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXB ||
4540 opcode == TGSI_OPCODE_TXF) {
4541 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4542 coord_dst.writemask = WRITEMASK_W;
4543 emit_asm(ir, TGSI_OPCODE_MOV, coord_dst, lod_info);
4544 coord_dst.writemask = WRITEMASK_XYZW;
4545 }
4546
4547 st_src_reg sampler(PROGRAM_SAMPLER, 0, GLSL_TYPE_UINT);
4548
4549 uint16_t index = 0;
4550 get_deref_offsets(ir->sampler, &sampler_array_size, &sampler_base,
4551 &index, &reladdr, !var->contains_bindless());
4552
4553 sampler.index = index;
4554 if (reladdr.file != PROGRAM_UNDEFINED) {
4555 sampler.reladdr = ralloc(mem_ctx, st_src_reg);
4556 *sampler.reladdr = reladdr;
4557 emit_arl(ir, sampler_reladdr, reladdr);
4558 }
4559
4560 st_src_reg bindless;
4561 if (var->contains_bindless()) {
4562 ir->sampler->accept(this);
4563 bindless = this->result;
4564 }
4565
4566 if (opcode == TGSI_OPCODE_TXD)
4567 inst = emit_asm(ir, opcode, result_dst, coord, dx, dy);
4568 else if (opcode == TGSI_OPCODE_TXQ) {
4569 if (ir->op == ir_query_levels) {
4570 /* the level is stored in W */
4571 inst = emit_asm(ir, opcode, st_dst_reg(levels_src), lod_info);
4572 result_dst.writemask = WRITEMASK_X;
4573 levels_src.swizzle = SWIZZLE_WWWW;
4574 emit_asm(ir, TGSI_OPCODE_MOV, result_dst, levels_src);
4575 } else
4576 inst = emit_asm(ir, opcode, result_dst, lod_info);
4577 } else if (opcode == TGSI_OPCODE_TXQS) {
4578 inst = emit_asm(ir, opcode, result_dst);
4579 } else if (opcode == TGSI_OPCODE_TXL2 || opcode == TGSI_OPCODE_TXB2) {
4580 inst = emit_asm(ir, opcode, result_dst, coord, lod_info);
4581 } else if (opcode == TGSI_OPCODE_TEX2) {
4582 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4583 } else if (opcode == TGSI_OPCODE_TG4) {
4584 if (is_cube_array && ir->shadow_comparator) {
4585 inst = emit_asm(ir, opcode, result_dst, coord, cube_sc);
4586 } else {
4587 if (this->tg4_component_in_swizzle) {
4588 inst = emit_asm(ir, opcode, result_dst, coord);
4589 int idx = 0;
4590 foreach_in_list(immediate_storage, entry, &this->immediates) {
4591 if (component.index == idx) {
4592 gl_constant_value value = entry->values[component.swizzle];
4593 inst->gather_component = value.i;
4594 break;
4595 }
4596 idx++;
4597 }
4598 } else {
4599 inst = emit_asm(ir, opcode, result_dst, coord, component);
4600 }
4601 }
4602 } else
4603 inst = emit_asm(ir, opcode, result_dst, coord);
4604
4605 if (ir->shadow_comparator)
4606 inst->tex_shadow = GL_TRUE;
4607
4608 if (var->contains_bindless()) {
4609 inst->resource = bindless;
4610 inst->resource.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y,
4611 SWIZZLE_X, SWIZZLE_Y);
4612 } else {
4613 inst->resource = sampler;
4614 inst->sampler_array_size = sampler_array_size;
4615 inst->sampler_base = sampler_base;
4616 }
4617
4618 if (ir->offset) {
4619 if (!inst->tex_offsets)
4620 inst->tex_offsets = rzalloc_array(inst, st_src_reg,
4621 MAX_GLSL_TEXTURE_OFFSET);
4622
4623 for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET &&
4624 offset[i].file != PROGRAM_UNDEFINED; i++)
4625 inst->tex_offsets[i] = offset[i];
4626 inst->tex_offset_num_offset = i;
4627 }
4628
4629 inst->tex_target = sampler_type->sampler_index();
4630 inst->tex_type = ir->type->base_type;
4631
4632 this->result = result_src;
4633 }
4634
4635 void
visit(ir_return * ir)4636 glsl_to_tgsi_visitor::visit(ir_return *ir)
4637 {
4638 assert(!ir->get_value());
4639
4640 emit_asm(ir, TGSI_OPCODE_RET);
4641 }
4642
4643 void
visit(ir_discard * ir)4644 glsl_to_tgsi_visitor::visit(ir_discard *ir)
4645 {
4646 if (ir->condition) {
4647 ir->condition->accept(this);
4648 st_src_reg condition = this->result;
4649
4650 /* Convert the bool condition to a float so we can negate. */
4651 if (native_integers) {
4652 st_src_reg temp = get_temp(ir->condition->type);
4653 emit_asm(ir, TGSI_OPCODE_AND, st_dst_reg(temp),
4654 condition, st_src_reg_for_float(1.0));
4655 condition = temp;
4656 }
4657
4658 condition.negate = ~condition.negate;
4659 emit_asm(ir, TGSI_OPCODE_KILL_IF, undef_dst, condition);
4660 } else {
4661 /* unconditional kil */
4662 emit_asm(ir, TGSI_OPCODE_KILL);
4663 }
4664 }
4665
4666 void
visit(ir_demote * ir)4667 glsl_to_tgsi_visitor::visit(ir_demote *ir)
4668 {
4669 emit_asm(ir, TGSI_OPCODE_DEMOTE);
4670 }
4671
4672 void
visit(ir_if * ir)4673 glsl_to_tgsi_visitor::visit(ir_if *ir)
4674 {
4675 enum tgsi_opcode if_opcode;
4676 glsl_to_tgsi_instruction *if_inst;
4677
4678 ir->condition->accept(this);
4679 assert(this->result.file != PROGRAM_UNDEFINED);
4680
4681 if_opcode = native_integers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF;
4682
4683 if_inst = emit_asm(ir->condition, if_opcode, undef_dst, this->result);
4684
4685 this->instructions.push_tail(if_inst);
4686
4687 visit_exec_list(&ir->then_instructions, this);
4688
4689 if (!ir->else_instructions.is_empty()) {
4690 emit_asm(ir->condition, TGSI_OPCODE_ELSE);
4691 visit_exec_list(&ir->else_instructions, this);
4692 }
4693
4694 if_inst = emit_asm(ir->condition, TGSI_OPCODE_ENDIF);
4695 }
4696
4697
4698 void
visit(ir_emit_vertex * ir)4699 glsl_to_tgsi_visitor::visit(ir_emit_vertex *ir)
4700 {
4701 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4702
4703 ir->stream->accept(this);
4704 emit_asm(ir, TGSI_OPCODE_EMIT, undef_dst, this->result);
4705 }
4706
4707 void
visit(ir_end_primitive * ir)4708 glsl_to_tgsi_visitor::visit(ir_end_primitive *ir)
4709 {
4710 assert(this->prog->Target == GL_GEOMETRY_PROGRAM_NV);
4711
4712 ir->stream->accept(this);
4713 emit_asm(ir, TGSI_OPCODE_ENDPRIM, undef_dst, this->result);
4714 }
4715
4716 void
visit(ir_barrier * ir)4717 glsl_to_tgsi_visitor::visit(ir_barrier *ir)
4718 {
4719 assert(this->prog->Target == GL_TESS_CONTROL_PROGRAM_NV ||
4720 this->prog->Target == GL_COMPUTE_PROGRAM_NV);
4721
4722 emit_asm(ir, TGSI_OPCODE_BARRIER);
4723 }
4724
glsl_to_tgsi_visitor()4725 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4726 {
4727 STATIC_ASSERT(sizeof(samplers_used) * 8 >= PIPE_MAX_SAMPLERS);
4728
4729 result.file = PROGRAM_UNDEFINED;
4730 next_temp = 1;
4731 array_sizes = NULL;
4732 max_num_arrays = 0;
4733 next_array = 0;
4734 num_inputs = 0;
4735 num_outputs = 0;
4736 num_input_arrays = 0;
4737 num_output_arrays = 0;
4738 num_atomics = 0;
4739 num_atomic_arrays = 0;
4740 num_immediates = 0;
4741 num_address_regs = 0;
4742 samplers_used = 0;
4743 images_used = 0;
4744 indirect_addr_consts = false;
4745 wpos_transform_const = -1;
4746 native_integers = false;
4747 mem_ctx = ralloc_context(NULL);
4748 ctx = NULL;
4749 prog = NULL;
4750 precise = 0;
4751 need_uarl = false;
4752 tg4_component_in_swizzle = false;
4753 shader_program = NULL;
4754 shader = NULL;
4755 options = NULL;
4756 have_sqrt = false;
4757 have_fma = false;
4758 use_shared_memory = false;
4759 has_tex_txf_lz = false;
4760 variables = NULL;
4761 }
4762
var_destroy(struct hash_entry * entry)4763 static void var_destroy(struct hash_entry *entry)
4764 {
4765 variable_storage *storage = (variable_storage *)entry->data;
4766
4767 delete storage;
4768 }
4769
~glsl_to_tgsi_visitor()4770 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4771 {
4772 _mesa_hash_table_destroy(variables, var_destroy);
4773 free(array_sizes);
4774 ralloc_free(mem_ctx);
4775 }
4776
free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor * v)4777 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor *v)
4778 {
4779 delete v;
4780 }
4781
4782
4783 /**
4784 * Count resources used by the given gpu program (number of texture
4785 * samplers, etc).
4786 */
4787 static void
count_resources(glsl_to_tgsi_visitor * v,gl_program * prog)4788 count_resources(glsl_to_tgsi_visitor *v, gl_program *prog)
4789 {
4790 v->samplers_used = 0;
4791 v->images_used = 0;
4792 prog->info.textures_used_by_txf = 0;
4793
4794 foreach_in_list(glsl_to_tgsi_instruction, inst, &v->instructions) {
4795 if (inst->info->is_tex) {
4796 for (int i = 0; i < inst->sampler_array_size; i++) {
4797 unsigned idx = inst->sampler_base + i;
4798 v->samplers_used |= 1u << idx;
4799
4800 debug_assert(idx < (int)ARRAY_SIZE(v->sampler_types));
4801 v->sampler_types[idx] = inst->tex_type;
4802 v->sampler_targets[idx] =
4803 st_translate_texture_target(inst->tex_target, inst->tex_shadow);
4804
4805 if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ) {
4806 prog->info.textures_used_by_txf |= 1u << idx;
4807 }
4808 }
4809 }
4810
4811 if (inst->tex_target == TEXTURE_EXTERNAL_INDEX)
4812 prog->ExternalSamplersUsed |= 1 << inst->resource.index;
4813
4814 if (inst->resource.file != PROGRAM_UNDEFINED && (
4815 is_resource_instruction(inst->op) ||
4816 inst->op == TGSI_OPCODE_STORE)) {
4817 if (inst->resource.file == PROGRAM_MEMORY) {
4818 v->use_shared_memory = true;
4819 } else if (inst->resource.file == PROGRAM_IMAGE) {
4820 for (int i = 0; i < inst->sampler_array_size; i++) {
4821 unsigned idx = inst->sampler_base + i;
4822 v->images_used |= 1 << idx;
4823 v->image_targets[idx] =
4824 st_translate_texture_target(inst->tex_target, false);
4825 v->image_formats[idx] = inst->image_format;
4826 v->image_wr[idx] = !inst->read_only;
4827 }
4828 }
4829 }
4830 }
4831 prog->SamplersUsed = v->samplers_used;
4832
4833 if (v->shader_program != NULL)
4834 _mesa_update_shader_textures_used(v->shader_program, prog);
4835 }
4836
4837 /**
4838 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4839 * are read from the given src in this instruction
4840 */
4841 static int
get_src_arg_mask(st_dst_reg dst,st_src_reg src)4842 get_src_arg_mask(st_dst_reg dst, st_src_reg src)
4843 {
4844 int read_mask = 0, comp;
4845
4846 /* Now, given the src swizzle and the written channels, find which
4847 * components are actually read
4848 */
4849 for (comp = 0; comp < 4; ++comp) {
4850 const unsigned coord = GET_SWZ(src.swizzle, comp);
4851 assert(coord < 4);
4852 if (dst.writemask & (1 << comp) && coord <= SWIZZLE_W)
4853 read_mask |= 1 << coord;
4854 }
4855
4856 return read_mask;
4857 }
4858
4859 /**
4860 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4861 * instruction is the first instruction to write to register T0. There are
4862 * several lowering passes done in GLSL IR (e.g. branches and
4863 * relative addressing) that create a large number of conditional assignments
4864 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4865 *
4866 * Here is why this conversion is safe:
4867 * CMP T0, T1 T2 T0 can be expanded to:
4868 * if (T1 < 0.0)
4869 * MOV T0, T2;
4870 * else
4871 * MOV T0, T0;
4872 *
4873 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4874 * as the original program. If (T1 < 0.0) evaluates to false, executing
4875 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4876 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4877 * because any instruction that was going to read from T0 after this was going
4878 * to read a garbage value anyway.
4879 */
4880 void
simplify_cmp(void)4881 glsl_to_tgsi_visitor::simplify_cmp(void)
4882 {
4883 int tempWritesSize = 0;
4884 unsigned *tempWrites = NULL;
4885 unsigned outputWrites[VARYING_SLOT_TESS_MAX];
4886
4887 memset(outputWrites, 0, sizeof(outputWrites));
4888
4889 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4890 unsigned prevWriteMask = 0;
4891
4892 /* Give up if we encounter relative addressing or flow control. */
4893 if (inst->dst[0].reladdr || inst->dst[0].reladdr2 ||
4894 inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
4895 inst->info->is_branch ||
4896 inst->op == TGSI_OPCODE_CONT ||
4897 inst->op == TGSI_OPCODE_END ||
4898 inst->op == TGSI_OPCODE_RET) {
4899 break;
4900 }
4901
4902 if (inst->dst[0].file == PROGRAM_OUTPUT) {
4903 assert(inst->dst[0].index < (signed)ARRAY_SIZE(outputWrites));
4904 prevWriteMask = outputWrites[inst->dst[0].index];
4905 outputWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4906 } else if (inst->dst[0].file == PROGRAM_TEMPORARY) {
4907 if (inst->dst[0].index >= tempWritesSize) {
4908 const int inc = 4096;
4909
4910 tempWrites = (unsigned*)
4911 realloc(tempWrites,
4912 (tempWritesSize + inc) * sizeof(unsigned));
4913 if (!tempWrites)
4914 return;
4915
4916 memset(tempWrites + tempWritesSize, 0, inc * sizeof(unsigned));
4917 tempWritesSize += inc;
4918 }
4919
4920 prevWriteMask = tempWrites[inst->dst[0].index];
4921 tempWrites[inst->dst[0].index] |= inst->dst[0].writemask;
4922 } else
4923 continue;
4924
4925 /* For a CMP to be considered a conditional write, the destination
4926 * register and source register two must be the same. */
4927 if (inst->op == TGSI_OPCODE_CMP
4928 && !(inst->dst[0].writemask & prevWriteMask)
4929 && inst->src[2].file == inst->dst[0].file
4930 && inst->src[2].index == inst->dst[0].index
4931 && inst->dst[0].writemask ==
4932 get_src_arg_mask(inst->dst[0], inst->src[2])) {
4933
4934 inst->op = TGSI_OPCODE_MOV;
4935 inst->info = tgsi_get_opcode_info(inst->op);
4936 inst->src[0] = inst->src[1];
4937 }
4938 }
4939
4940 free(tempWrites);
4941 }
4942
4943 static void
rename_temp_handle_src(struct rename_reg_pair * renames,st_src_reg * src)4944 rename_temp_handle_src(struct rename_reg_pair *renames, st_src_reg *src)
4945 {
4946 if (src && src->file == PROGRAM_TEMPORARY) {
4947 int old_idx = src->index;
4948 if (renames[old_idx].valid)
4949 src->index = renames[old_idx].new_reg;
4950 }
4951 }
4952
4953 /* Replaces all references to a temporary register index with another index. */
4954 void
rename_temp_registers(struct rename_reg_pair * renames)4955 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair *renames)
4956 {
4957 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4958 unsigned j;
4959 for (j = 0; j < num_inst_src_regs(inst); j++) {
4960 rename_temp_handle_src(renames, &inst->src[j]);
4961 rename_temp_handle_src(renames, inst->src[j].reladdr);
4962 rename_temp_handle_src(renames, inst->src[j].reladdr2);
4963 }
4964
4965 for (j = 0; j < inst->tex_offset_num_offset; j++) {
4966 rename_temp_handle_src(renames, &inst->tex_offsets[j]);
4967 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr);
4968 rename_temp_handle_src(renames, inst->tex_offsets[j].reladdr2);
4969 }
4970
4971 rename_temp_handle_src(renames, &inst->resource);
4972 rename_temp_handle_src(renames, inst->resource.reladdr);
4973 rename_temp_handle_src(renames, inst->resource.reladdr2);
4974
4975 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4976 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4977 int old_idx = inst->dst[j].index;
4978 if (renames[old_idx].valid)
4979 inst->dst[j].index = renames[old_idx].new_reg;
4980 }
4981 rename_temp_handle_src(renames, inst->dst[j].reladdr);
4982 rename_temp_handle_src(renames, inst->dst[j].reladdr2);
4983 }
4984 }
4985 }
4986
4987 void
get_first_temp_write(int * first_writes)4988 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes)
4989 {
4990 int depth = 0; /* loop depth */
4991 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
4992 unsigned i = 0, j;
4993
4994 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
4995 for (j = 0; j < num_inst_dst_regs(inst); j++) {
4996 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
4997 if (first_writes[inst->dst[j].index] == -1)
4998 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
4999 }
5000 }
5001
5002 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5003 if (depth++ == 0)
5004 loop_start = i;
5005 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5006 if (--depth == 0)
5007 loop_start = -1;
5008 }
5009 assert(depth >= 0);
5010 i++;
5011 }
5012 }
5013
5014 void
get_first_temp_read(int * first_reads)5015 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads)
5016 {
5017 int depth = 0; /* loop depth */
5018 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5019 unsigned i = 0, j;
5020
5021 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5022 for (j = 0; j < num_inst_src_regs(inst); j++) {
5023 if (inst->src[j].file == PROGRAM_TEMPORARY) {
5024 if (first_reads[inst->src[j].index] == -1)
5025 first_reads[inst->src[j].index] = (depth == 0) ? i : loop_start;
5026 }
5027 }
5028 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5029 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY) {
5030 if (first_reads[inst->tex_offsets[j].index] == -1)
5031 first_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : loop_start;
5032 }
5033 }
5034 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5035 if (depth++ == 0)
5036 loop_start = i;
5037 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5038 if (--depth == 0)
5039 loop_start = -1;
5040 }
5041 assert(depth >= 0);
5042 i++;
5043 }
5044 }
5045
5046 void
get_last_temp_read_first_temp_write(int * last_reads,int * first_writes)5047 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads, int *first_writes)
5048 {
5049 int depth = 0; /* loop depth */
5050 int loop_start = -1; /* index of the first active BGNLOOP (if any) */
5051 unsigned i = 0, j;
5052 int k;
5053 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5054 for (j = 0; j < num_inst_src_regs(inst); j++) {
5055 if (inst->src[j].file == PROGRAM_TEMPORARY)
5056 last_reads[inst->src[j].index] = (depth == 0) ? i : -2;
5057 }
5058 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5059 if (inst->dst[j].file == PROGRAM_TEMPORARY) {
5060 if (first_writes[inst->dst[j].index] == -1)
5061 first_writes[inst->dst[j].index] = (depth == 0) ? i : loop_start;
5062 last_reads[inst->dst[j].index] = (depth == 0) ? i : -2;
5063 }
5064 }
5065 for (j = 0; j < inst->tex_offset_num_offset; j++) {
5066 if (inst->tex_offsets[j].file == PROGRAM_TEMPORARY)
5067 last_reads[inst->tex_offsets[j].index] = (depth == 0) ? i : -2;
5068 }
5069 if (inst->op == TGSI_OPCODE_BGNLOOP) {
5070 if (depth++ == 0)
5071 loop_start = i;
5072 } else if (inst->op == TGSI_OPCODE_ENDLOOP) {
5073 if (--depth == 0) {
5074 loop_start = -1;
5075 for (k = 0; k < this->next_temp; k++) {
5076 if (last_reads[k] == -2) {
5077 last_reads[k] = i;
5078 }
5079 }
5080 }
5081 }
5082 assert(depth >= 0);
5083 i++;
5084 }
5085 }
5086
5087 void
get_last_temp_write(int * last_writes)5088 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes)
5089 {
5090 int depth = 0; /* loop depth */
5091 int i = 0, k;
5092 unsigned j;
5093
5094 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5095 for (j = 0; j < num_inst_dst_regs(inst); j++) {
5096 if (inst->dst[j].file == PROGRAM_TEMPORARY)
5097 last_writes[inst->dst[j].index] = (depth == 0) ? i : -2;
5098 }
5099
5100 if (inst->op == TGSI_OPCODE_BGNLOOP)
5101 depth++;
5102 else if (inst->op == TGSI_OPCODE_ENDLOOP)
5103 if (--depth == 0) {
5104 for (k = 0; k < this->next_temp; k++) {
5105 if (last_writes[k] == -2) {
5106 last_writes[k] = i;
5107 }
5108 }
5109 }
5110 assert(depth >= 0);
5111 i++;
5112 }
5113 }
5114
5115 /*
5116 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
5117 * channels for copy propagation and updates following instructions to
5118 * use the original versions.
5119 *
5120 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5121 * will occur. As an example, a TXP production before this pass:
5122 *
5123 * 0: MOV TEMP[1], INPUT[4].xyyy;
5124 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5125 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5126 *
5127 * and after:
5128 *
5129 * 0: MOV TEMP[1], INPUT[4].xyyy;
5130 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5131 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5132 *
5133 * which allows for dead code elimination on TEMP[1]'s writes.
5134 */
5135 void
copy_propagate(void)5136 glsl_to_tgsi_visitor::copy_propagate(void)
5137 {
5138 glsl_to_tgsi_instruction **acp = rzalloc_array(mem_ctx,
5139 glsl_to_tgsi_instruction *,
5140 this->next_temp * 4);
5141 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5142 int level = 0;
5143
5144 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5145 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5146 || inst->dst[0].index < this->next_temp);
5147
5148 /* First, do any copy propagation possible into the src regs. */
5149 for (int r = 0; r < 3; r++) {
5150 glsl_to_tgsi_instruction *first = NULL;
5151 bool good = true;
5152 int acp_base = inst->src[r].index * 4;
5153
5154 if (inst->src[r].file != PROGRAM_TEMPORARY ||
5155 inst->src[r].reladdr ||
5156 inst->src[r].reladdr2)
5157 continue;
5158
5159 /* See if we can find entries in the ACP consisting of MOVs
5160 * from the same src register for all the swizzled channels
5161 * of this src register reference.
5162 */
5163 for (int i = 0; i < 4; i++) {
5164 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5165 glsl_to_tgsi_instruction *copy_chan = acp[acp_base + src_chan];
5166
5167 if (!copy_chan) {
5168 good = false;
5169 break;
5170 }
5171
5172 assert(acp_level[acp_base + src_chan] <= level);
5173
5174 if (!first) {
5175 first = copy_chan;
5176 } else {
5177 if (first->src[0].file != copy_chan->src[0].file ||
5178 first->src[0].index != copy_chan->src[0].index ||
5179 first->src[0].double_reg2 != copy_chan->src[0].double_reg2 ||
5180 first->src[0].index2D != copy_chan->src[0].index2D) {
5181 good = false;
5182 break;
5183 }
5184 }
5185 }
5186
5187 if (good) {
5188 /* We've now validated that we can copy-propagate to
5189 * replace this src register reference. Do it.
5190 */
5191 inst->src[r].file = first->src[0].file;
5192 inst->src[r].index = first->src[0].index;
5193 inst->src[r].index2D = first->src[0].index2D;
5194 inst->src[r].has_index2 = first->src[0].has_index2;
5195 inst->src[r].double_reg2 = first->src[0].double_reg2;
5196 inst->src[r].array_id = first->src[0].array_id;
5197
5198 int swizzle = 0;
5199 for (int i = 0; i < 4; i++) {
5200 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
5201 glsl_to_tgsi_instruction *copy_inst = acp[acp_base + src_chan];
5202 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) << (3 * i));
5203 }
5204 inst->src[r].swizzle = swizzle;
5205 }
5206 }
5207
5208 switch (inst->op) {
5209 case TGSI_OPCODE_BGNLOOP:
5210 case TGSI_OPCODE_ENDLOOP:
5211 /* End of a basic block, clear the ACP entirely. */
5212 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5213 break;
5214
5215 case TGSI_OPCODE_IF:
5216 case TGSI_OPCODE_UIF:
5217 ++level;
5218 break;
5219
5220 case TGSI_OPCODE_ENDIF:
5221 case TGSI_OPCODE_ELSE:
5222 /* Clear all channels written inside the block from the ACP, but
5223 * leaving those that were not touched.
5224 */
5225 for (int r = 0; r < this->next_temp; r++) {
5226 for (int c = 0; c < 4; c++) {
5227 if (!acp[4 * r + c])
5228 continue;
5229
5230 if (acp_level[4 * r + c] >= level)
5231 acp[4 * r + c] = NULL;
5232 }
5233 }
5234 if (inst->op == TGSI_OPCODE_ENDIF)
5235 --level;
5236 break;
5237
5238 default:
5239 /* Continuing the block, clear any written channels from
5240 * the ACP.
5241 */
5242 for (int d = 0; d < 2; d++) {
5243 if (inst->dst[d].file == PROGRAM_TEMPORARY && inst->dst[d].reladdr) {
5244 /* Any temporary might be written, so no copy propagation
5245 * across this instruction.
5246 */
5247 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
5248 } else if (inst->dst[d].file == PROGRAM_OUTPUT &&
5249 inst->dst[d].reladdr) {
5250 /* Any output might be written, so no copy propagation
5251 * from outputs across this instruction.
5252 */
5253 for (int r = 0; r < this->next_temp; r++) {
5254 for (int c = 0; c < 4; c++) {
5255 if (!acp[4 * r + c])
5256 continue;
5257
5258 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
5259 acp[4 * r + c] = NULL;
5260 }
5261 }
5262 } else if (inst->dst[d].file == PROGRAM_TEMPORARY ||
5263 inst->dst[d].file == PROGRAM_OUTPUT) {
5264 /* Clear where it's used as dst. */
5265 if (inst->dst[d].file == PROGRAM_TEMPORARY) {
5266 for (int c = 0; c < 4; c++) {
5267 if (inst->dst[d].writemask & (1 << c))
5268 acp[4 * inst->dst[d].index + c] = NULL;
5269 }
5270 }
5271
5272 /* Clear where it's used as src. */
5273 for (int r = 0; r < this->next_temp; r++) {
5274 for (int c = 0; c < 4; c++) {
5275 if (!acp[4 * r + c])
5276 continue;
5277
5278 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
5279
5280 if (acp[4 * r + c]->src[0].file == inst->dst[d].file &&
5281 acp[4 * r + c]->src[0].index == inst->dst[d].index &&
5282 inst->dst[d].writemask & (1 << src_chan)) {
5283 acp[4 * r + c] = NULL;
5284 }
5285 }
5286 }
5287 }
5288 }
5289 break;
5290 }
5291
5292 /* If this is a copy, add it to the ACP. */
5293 if (inst->op == TGSI_OPCODE_MOV &&
5294 inst->dst[0].file == PROGRAM_TEMPORARY &&
5295 !(inst->dst[0].file == inst->src[0].file &&
5296 inst->dst[0].index == inst->src[0].index) &&
5297 !inst->dst[0].reladdr &&
5298 !inst->dst[0].reladdr2 &&
5299 !inst->saturate &&
5300 inst->src[0].file != PROGRAM_ARRAY &&
5301 (inst->src[0].file != PROGRAM_OUTPUT ||
5302 this->shader->Stage != MESA_SHADER_TESS_CTRL) &&
5303 !inst->src[0].reladdr &&
5304 !inst->src[0].reladdr2 &&
5305 !inst->src[0].negate &&
5306 !inst->src[0].abs) {
5307 for (int i = 0; i < 4; i++) {
5308 if (inst->dst[0].writemask & (1 << i)) {
5309 acp[4 * inst->dst[0].index + i] = inst;
5310 acp_level[4 * inst->dst[0].index + i] = level;
5311 }
5312 }
5313 }
5314 }
5315
5316 ralloc_free(acp_level);
5317 ralloc_free(acp);
5318 }
5319
5320 static void
dead_code_handle_reladdr(glsl_to_tgsi_instruction ** writes,st_src_reg * reladdr)5321 dead_code_handle_reladdr(glsl_to_tgsi_instruction **writes, st_src_reg *reladdr)
5322 {
5323 if (reladdr && reladdr->file == PROGRAM_TEMPORARY) {
5324 /* Clear where it's used as src. */
5325 int swz = GET_SWZ(reladdr->swizzle, 0);
5326 writes[4 * reladdr->index + swz] = NULL;
5327 }
5328 }
5329
5330 /*
5331 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5332 * code elimination.
5333 *
5334 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5335 * will occur. As an example, a TXP production after copy propagation but
5336 * before this pass:
5337 *
5338 * 0: MOV TEMP[1], INPUT[4].xyyy;
5339 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5340 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5341 *
5342 * and after this pass:
5343 *
5344 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5345 */
5346 int
eliminate_dead_code(void)5347 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5348 {
5349 glsl_to_tgsi_instruction **writes = rzalloc_array(mem_ctx,
5350 glsl_to_tgsi_instruction *,
5351 this->next_temp * 4);
5352 int *write_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
5353 int level = 0;
5354 int removed = 0;
5355
5356 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5357 assert(inst->dst[0].file != PROGRAM_TEMPORARY
5358 || inst->dst[0].index < this->next_temp);
5359
5360 switch (inst->op) {
5361 case TGSI_OPCODE_BGNLOOP:
5362 case TGSI_OPCODE_ENDLOOP:
5363 case TGSI_OPCODE_CONT:
5364 case TGSI_OPCODE_BRK:
5365 /* End of a basic block, clear the write array entirely.
5366 *
5367 * This keeps us from killing dead code when the writes are
5368 * on either side of a loop, even when the register isn't touched
5369 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5370 * dead code of this type, so it shouldn't make a difference as long as
5371 * the dead code elimination pass in the GLSL compiler does its job.
5372 */
5373 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5374 break;
5375
5376 case TGSI_OPCODE_ENDIF:
5377 case TGSI_OPCODE_ELSE:
5378 /* Promote the recorded level of all channels written inside the
5379 * preceding if or else block to the level above the if/else block.
5380 */
5381 for (int r = 0; r < this->next_temp; r++) {
5382 for (int c = 0; c < 4; c++) {
5383 if (!writes[4 * r + c])
5384 continue;
5385
5386 if (write_level[4 * r + c] == level)
5387 write_level[4 * r + c] = level-1;
5388 }
5389 }
5390 if (inst->op == TGSI_OPCODE_ENDIF)
5391 --level;
5392 break;
5393
5394 case TGSI_OPCODE_IF:
5395 case TGSI_OPCODE_UIF:
5396 ++level;
5397 /* fallthrough to default case to mark the condition as read */
5398 default:
5399 /* Continuing the block, clear any channels from the write array that
5400 * are read by this instruction.
5401 */
5402 for (unsigned i = 0; i < ARRAY_SIZE(inst->src); i++) {
5403 if (inst->src[i].file == PROGRAM_TEMPORARY && inst->src[i].reladdr){
5404 /* Any temporary might be read, so no dead code elimination
5405 * across this instruction.
5406 */
5407 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5408 } else if (inst->src[i].file == PROGRAM_TEMPORARY) {
5409 /* Clear where it's used as src. */
5410 int src_chans = 1 << GET_SWZ(inst->src[i].swizzle, 0);
5411 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 1);
5412 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 2);
5413 src_chans |= 1 << GET_SWZ(inst->src[i].swizzle, 3);
5414
5415 for (int c = 0; c < 4; c++) {
5416 if (src_chans & (1 << c))
5417 writes[4 * inst->src[i].index + c] = NULL;
5418 }
5419 }
5420 dead_code_handle_reladdr(writes, inst->src[i].reladdr);
5421 dead_code_handle_reladdr(writes, inst->src[i].reladdr2);
5422 }
5423 for (unsigned i = 0; i < inst->tex_offset_num_offset; i++) {
5424 if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY && inst->tex_offsets[i].reladdr){
5425 /* Any temporary might be read, so no dead code elimination
5426 * across this instruction.
5427 */
5428 memset(writes, 0, sizeof(*writes) * this->next_temp * 4);
5429 } else if (inst->tex_offsets[i].file == PROGRAM_TEMPORARY) {
5430 /* Clear where it's used as src. */
5431 int src_chans = 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 0);
5432 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 1);
5433 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 2);
5434 src_chans |= 1 << GET_SWZ(inst->tex_offsets[i].swizzle, 3);
5435
5436 for (int c = 0; c < 4; c++) {
5437 if (src_chans & (1 << c))
5438 writes[4 * inst->tex_offsets[i].index + c] = NULL;
5439 }
5440 }
5441 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr);
5442 dead_code_handle_reladdr(writes, inst->tex_offsets[i].reladdr2);
5443 }
5444
5445 if (inst->resource.file == PROGRAM_TEMPORARY) {
5446 int src_chans;
5447
5448 src_chans = 1 << GET_SWZ(inst->resource.swizzle, 0);
5449 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 1);
5450 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 2);
5451 src_chans |= 1 << GET_SWZ(inst->resource.swizzle, 3);
5452
5453 for (int c = 0; c < 4; c++) {
5454 if (src_chans & (1 << c))
5455 writes[4 * inst->resource.index + c] = NULL;
5456 }
5457 }
5458 dead_code_handle_reladdr(writes, inst->resource.reladdr);
5459 dead_code_handle_reladdr(writes, inst->resource.reladdr2);
5460
5461 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5462 dead_code_handle_reladdr(writes, inst->dst[i].reladdr);
5463 dead_code_handle_reladdr(writes, inst->dst[i].reladdr2);
5464 }
5465 break;
5466 }
5467
5468 /* If this instruction writes to a temporary, add it to the write array.
5469 * If there is already an instruction in the write array for one or more
5470 * of the channels, flag that channel write as dead.
5471 */
5472 for (unsigned i = 0; i < ARRAY_SIZE(inst->dst); i++) {
5473 if (inst->dst[i].file == PROGRAM_TEMPORARY &&
5474 !inst->dst[i].reladdr) {
5475 for (int c = 0; c < 4; c++) {
5476 if (inst->dst[i].writemask & (1 << c)) {
5477 if (writes[4 * inst->dst[i].index + c]) {
5478 if (write_level[4 * inst->dst[i].index + c] < level)
5479 continue;
5480 else
5481 writes[4 * inst->dst[i].index + c]->dead_mask |= (1 << c);
5482 }
5483 writes[4 * inst->dst[i].index + c] = inst;
5484 write_level[4 * inst->dst[i].index + c] = level;
5485 }
5486 }
5487 }
5488 }
5489 }
5490
5491 /* Anything still in the write array at this point is dead code. */
5492 for (int r = 0; r < this->next_temp; r++) {
5493 for (int c = 0; c < 4; c++) {
5494 glsl_to_tgsi_instruction *inst = writes[4 * r + c];
5495 if (inst)
5496 inst->dead_mask |= (1 << c);
5497 }
5498 }
5499
5500 /* Now actually remove the instructions that are completely dead and update
5501 * the writemask of other instructions with dead channels.
5502 */
5503 foreach_in_list_safe(glsl_to_tgsi_instruction, inst, &this->instructions) {
5504 if (!inst->dead_mask || !inst->dst[0].writemask)
5505 continue;
5506 /* No amount of dead masks should remove memory stores */
5507 if (inst->info->is_store)
5508 continue;
5509
5510 if ((inst->dst[0].writemask & ~inst->dead_mask) == 0) {
5511 inst->remove();
5512 delete inst;
5513 removed++;
5514 } else {
5515 if (glsl_base_type_is_64bit(inst->dst[0].type)) {
5516 if (inst->dead_mask == WRITEMASK_XY ||
5517 inst->dead_mask == WRITEMASK_ZW)
5518 inst->dst[0].writemask &= ~(inst->dead_mask);
5519 } else
5520 inst->dst[0].writemask &= ~(inst->dead_mask);
5521 }
5522 }
5523
5524 ralloc_free(write_level);
5525 ralloc_free(writes);
5526
5527 return removed;
5528 }
5529
5530 /* merge DFRACEXP instructions into one. */
5531 void
merge_two_dsts(void)5532 glsl_to_tgsi_visitor::merge_two_dsts(void)
5533 {
5534 /* We never delete inst, but we may delete its successor. */
5535 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5536 glsl_to_tgsi_instruction *inst2;
5537 unsigned defined;
5538
5539 if (num_inst_dst_regs(inst) != 2)
5540 continue;
5541
5542 if (inst->dst[0].file != PROGRAM_UNDEFINED &&
5543 inst->dst[1].file != PROGRAM_UNDEFINED)
5544 continue;
5545
5546 assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
5547 inst->dst[1].file != PROGRAM_UNDEFINED);
5548
5549 if (inst->dst[0].file == PROGRAM_UNDEFINED)
5550 defined = 1;
5551 else
5552 defined = 0;
5553
5554 inst2 = (glsl_to_tgsi_instruction *) inst->next;
5555 while (!inst2->is_tail_sentinel()) {
5556 if (inst->op == inst2->op &&
5557 inst2->dst[defined].file == PROGRAM_UNDEFINED &&
5558 inst->src[0].file == inst2->src[0].file &&
5559 inst->src[0].index == inst2->src[0].index &&
5560 inst->src[0].type == inst2->src[0].type &&
5561 inst->src[0].swizzle == inst2->src[0].swizzle)
5562 break;
5563 inst2 = (glsl_to_tgsi_instruction *) inst2->next;
5564 }
5565
5566 if (inst2->is_tail_sentinel()) {
5567 /* Undefined destinations are not allowed, substitute with an unused
5568 * temporary register.
5569 */
5570 st_src_reg tmp = get_temp(glsl_type::vec4_type);
5571 inst->dst[defined ^ 1] = st_dst_reg(tmp);
5572 inst->dst[defined ^ 1].writemask = 0;
5573 continue;
5574 }
5575
5576 inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
5577 inst2->remove();
5578 delete inst2;
5579 }
5580 }
5581
5582 template <typename st_reg>
test_indirect_access(const st_reg & reg,bool * has_indirect_access)5583 void test_indirect_access(const st_reg& reg, bool *has_indirect_access)
5584 {
5585 if (reg.file == PROGRAM_ARRAY) {
5586 if (reg.reladdr || reg.reladdr2 || reg.has_index2) {
5587 has_indirect_access[reg.array_id] = true;
5588 if (reg.reladdr)
5589 test_indirect_access(*reg.reladdr, has_indirect_access);
5590 if (reg.reladdr2)
5591 test_indirect_access(*reg.reladdr2, has_indirect_access);
5592 }
5593 }
5594 }
5595
5596 template <typename st_reg>
remap_array(st_reg & reg,const int * array_remap_info,const bool * has_indirect_access)5597 void remap_array(st_reg& reg, const int *array_remap_info,
5598 const bool *has_indirect_access)
5599 {
5600 if (reg.file == PROGRAM_ARRAY) {
5601 if (!has_indirect_access[reg.array_id]) {
5602 reg.file = PROGRAM_TEMPORARY;
5603 reg.index = reg.index + array_remap_info[reg.array_id];
5604 reg.array_id = 0;
5605 } else {
5606 reg.array_id = array_remap_info[reg.array_id];
5607 }
5608
5609 if (reg.reladdr)
5610 remap_array(*reg.reladdr, array_remap_info, has_indirect_access);
5611
5612 if (reg.reladdr2)
5613 remap_array(*reg.reladdr2, array_remap_info, has_indirect_access);
5614 }
5615 }
5616
5617 /* One-dimensional arrays whose elements are only accessed directly are
5618 * replaced by an according set of temporary registers that then can become
5619 * subject to further optimization steps like copy propagation and
5620 * register merging.
5621 */
5622 void
split_arrays(void)5623 glsl_to_tgsi_visitor::split_arrays(void)
5624 {
5625 if (!next_array)
5626 return;
5627
5628 bool *has_indirect_access = rzalloc_array(mem_ctx, bool, next_array + 1);
5629
5630 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5631 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5632 test_indirect_access(inst->src[j], has_indirect_access);
5633
5634 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5635 test_indirect_access(inst->tex_offsets[j], has_indirect_access);
5636
5637 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++)
5638 test_indirect_access(inst->dst[j], has_indirect_access);
5639
5640 test_indirect_access(inst->resource, has_indirect_access);
5641 }
5642
5643 unsigned array_offset = 0;
5644 unsigned n_remaining_arrays = 0;
5645
5646 /* Double use: For arrays that get split this value will contain
5647 * the base index of the temporary registers this array is replaced
5648 * with. For arrays that remain it contains the new array ID.
5649 */
5650 int *array_remap_info = rzalloc_array(has_indirect_access, int,
5651 next_array + 1);
5652
5653 for (unsigned i = 1; i <= next_array; ++i) {
5654 if (!has_indirect_access[i]) {
5655 array_remap_info[i] = this->next_temp + array_offset;
5656 array_offset += array_sizes[i - 1];
5657 } else {
5658 array_sizes[n_remaining_arrays] = array_sizes[i-1];
5659 array_remap_info[i] = ++n_remaining_arrays;
5660 }
5661 }
5662
5663 if (next_array != n_remaining_arrays) {
5664 foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
5665 for (unsigned j = 0; j < num_inst_src_regs(inst); j++)
5666 remap_array(inst->src[j], array_remap_info, has_indirect_access);
5667
5668 for (unsigned j = 0; j < inst->tex_offset_num_offset; j++)
5669 remap_array(inst->tex_offsets[j], array_remap_info, has_indirect_access);
5670
5671 for (unsigned j = 0; j < num_inst_dst_regs(inst); j++) {
5672 remap_array(inst->dst[j], array_remap_info, has_indirect_access);
5673 }
5674 remap_array(inst->resource, array_remap_info, has_indirect_access);
5675 }
5676 }
5677
5678 ralloc_free(has_indirect_access);
5679 this->next_temp += array_offset;
5680 next_array = n_remaining_arrays;
5681 }
5682
5683 /* Merges temporary registers together where possible to reduce the number of
5684 * registers needed to run a program.
5685 *
5686 * Produces optimal code only after copy propagation and dead code elimination
5687 * have been run. */
5688 void
merge_registers(void)5689 glsl_to_tgsi_visitor::merge_registers(void)
5690 {
5691 class array_live_range *arr_live_ranges = NULL;
5692
5693 struct register_live_range *reg_live_ranges =
5694 rzalloc_array(mem_ctx, struct register_live_range, this->next_temp);
5695
5696 if (this->next_array > 0) {
5697 arr_live_ranges = new array_live_range[this->next_array];
5698 for (unsigned i = 0; i < this->next_array; ++i)
5699 arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
5700 }
5701
5702
5703 if (get_temp_registers_required_live_ranges(reg_live_ranges, &this->instructions,
5704 this->next_temp, reg_live_ranges,
5705 this->next_array, arr_live_ranges)) {
5706 struct rename_reg_pair *renames =
5707 rzalloc_array(reg_live_ranges, struct rename_reg_pair, this->next_temp);
5708 get_temp_registers_remapping(reg_live_ranges, this->next_temp,
5709 reg_live_ranges, renames);
5710 rename_temp_registers(renames);
5711
5712 this->next_array = merge_arrays(this->next_array, this->array_sizes,
5713 &this->instructions, arr_live_ranges);
5714 }
5715
5716 if (arr_live_ranges)
5717 delete[] arr_live_ranges;
5718
5719 ralloc_free(reg_live_ranges);
5720 }
5721
5722 /* Reassign indices to temporary registers by reusing unused indices created
5723 * by optimization passes. */
5724 void
renumber_registers(void)5725 glsl_to_tgsi_visitor::renumber_registers(void)
5726 {
5727 int i = 0;
5728 int new_index = 0;
5729 int *first_writes = ralloc_array(mem_ctx, int, this->next_temp);
5730 struct rename_reg_pair *renames = rzalloc_array(mem_ctx, struct rename_reg_pair, this->next_temp);
5731
5732 for (i = 0; i < this->next_temp; i++) {
5733 first_writes[i] = -1;
5734 }
5735 get_first_temp_write(first_writes);
5736
5737 for (i = 0; i < this->next_temp; i++) {
5738 if (first_writes[i] < 0) continue;
5739 if (i != new_index) {
5740 renames[i].new_reg = new_index;
5741 renames[i].valid = true;
5742 }
5743 new_index++;
5744 }
5745
5746 rename_temp_registers(renames);
5747 this->next_temp = new_index;
5748 ralloc_free(renames);
5749 ralloc_free(first_writes);
5750 }
5751
5752 #ifndef NDEBUG
print_stats()5753 void glsl_to_tgsi_visitor::print_stats()
5754 {
5755 int narray_registers = 0;
5756 for (unsigned i = 0; i < this->next_array; ++i)
5757 narray_registers += this->array_sizes[i];
5758
5759 int ninstructions = 0;
5760 foreach_in_list(glsl_to_tgsi_instruction, inst, &instructions) {
5761 ++ninstructions;
5762 }
5763
5764 simple_mtx_lock(&print_stats_mutex);
5765 stats_log << next_array << ", "
5766 << next_temp << ", "
5767 << narray_registers << ", "
5768 << next_temp + narray_registers << ", "
5769 << ninstructions << "\n";
5770 simple_mtx_unlock(&print_stats_mutex);
5771 }
5772 #endif
5773 /* ------------------------- TGSI conversion stuff -------------------------- */
5774
5775 /**
5776 * Intermediate state used during shader translation.
5777 */
5778 struct st_translate {
5779 struct ureg_program *ureg;
5780
5781 unsigned temps_size;
5782 struct ureg_dst *temps;
5783
5784 struct ureg_dst *arrays;
5785 unsigned num_temp_arrays;
5786 struct ureg_src *constants;
5787 int num_constants;
5788 struct ureg_src *immediates;
5789 int num_immediates;
5790 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
5791 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
5792 struct ureg_dst address[3];
5793 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
5794 struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
5795 struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
5796 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
5797 struct ureg_src hw_atomics[PIPE_MAX_HW_ATOMIC_BUFFERS];
5798 struct ureg_src shared_memory;
5799 unsigned *array_sizes;
5800 struct inout_decl *input_decls;
5801 unsigned num_input_decls;
5802 struct inout_decl *output_decls;
5803 unsigned num_output_decls;
5804
5805 const ubyte *inputMapping;
5806 const ubyte *outputMapping;
5807
5808 enum pipe_shader_type procType; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5809 bool need_uarl;
5810 bool tg4_component_in_swizzle;
5811 };
5812
5813 /**
5814 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5815 */
5816 static struct ureg_src
emit_immediate(struct st_translate * t,gl_constant_value values[4],GLenum type,int size)5817 emit_immediate(struct st_translate *t,
5818 gl_constant_value values[4],
5819 GLenum type, int size)
5820 {
5821 struct ureg_program *ureg = t->ureg;
5822
5823 switch (type) {
5824 case GL_FLOAT:
5825 return ureg_DECL_immediate(ureg, &values[0].f, size);
5826 case GL_DOUBLE:
5827 return ureg_DECL_immediate_f64(ureg, (double *)&values[0].f, size);
5828 case GL_INT64_ARB:
5829 return ureg_DECL_immediate_int64(ureg, (int64_t *)&values[0].f, size);
5830 case GL_UNSIGNED_INT64_ARB:
5831 return ureg_DECL_immediate_uint64(ureg, (uint64_t *)&values[0].f, size);
5832 case GL_INT:
5833 return ureg_DECL_immediate_int(ureg, &values[0].i, size);
5834 case GL_UNSIGNED_INT:
5835 case GL_BOOL:
5836 return ureg_DECL_immediate_uint(ureg, &values[0].u, size);
5837 default:
5838 assert(!"should not get here - type must be float, int, uint, or bool");
5839 return ureg_src_undef();
5840 }
5841 }
5842
5843 /**
5844 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5845 */
5846 static struct ureg_dst
dst_register(struct st_translate * t,gl_register_file file,unsigned index,unsigned array_id)5847 dst_register(struct st_translate *t, gl_register_file file, unsigned index,
5848 unsigned array_id)
5849 {
5850 unsigned array;
5851
5852 switch (file) {
5853 case PROGRAM_UNDEFINED:
5854 return ureg_dst_undef();
5855
5856 case PROGRAM_TEMPORARY:
5857 /* Allocate space for temporaries on demand. */
5858 if (index >= t->temps_size) {
5859 const int inc = align(index - t->temps_size + 1, 4096);
5860
5861 t->temps = (struct ureg_dst*)
5862 realloc(t->temps,
5863 (t->temps_size + inc) * sizeof(struct ureg_dst));
5864 if (!t->temps)
5865 return ureg_dst_undef();
5866
5867 memset(t->temps + t->temps_size, 0, inc * sizeof(struct ureg_dst));
5868 t->temps_size += inc;
5869 }
5870
5871 if (ureg_dst_is_undef(t->temps[index]))
5872 t->temps[index] = ureg_DECL_local_temporary(t->ureg);
5873
5874 return t->temps[index];
5875
5876 case PROGRAM_ARRAY:
5877 assert(array_id && array_id <= t->num_temp_arrays);
5878 array = array_id - 1;
5879
5880 if (ureg_dst_is_undef(t->arrays[array]))
5881 t->arrays[array] = ureg_DECL_array_temporary(
5882 t->ureg, t->array_sizes[array], TRUE);
5883
5884 return ureg_dst_array_offset(t->arrays[array], index);
5885
5886 case PROGRAM_OUTPUT:
5887 if (!array_id) {
5888 if (t->procType == PIPE_SHADER_FRAGMENT)
5889 assert(index < 2 * FRAG_RESULT_MAX);
5890 else if (t->procType == PIPE_SHADER_TESS_CTRL ||
5891 t->procType == PIPE_SHADER_TESS_EVAL)
5892 assert(index < VARYING_SLOT_TESS_MAX);
5893 else
5894 assert(index < VARYING_SLOT_MAX);
5895
5896 assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
5897 assert(t->outputs[t->outputMapping[index]].File != TGSI_FILE_NULL);
5898 return t->outputs[t->outputMapping[index]];
5899 }
5900 else {
5901 struct inout_decl *decl =
5902 find_inout_array(t->output_decls,
5903 t->num_output_decls, array_id);
5904 unsigned mesa_index = decl->mesa_index;
5905 int slot = t->outputMapping[mesa_index];
5906
5907 assert(slot != -1 && t->outputs[slot].File == TGSI_FILE_OUTPUT);
5908
5909 struct ureg_dst dst = t->outputs[slot];
5910 dst.ArrayID = array_id;
5911 return ureg_dst_array_offset(dst, index - mesa_index);
5912 }
5913
5914 case PROGRAM_ADDRESS:
5915 return t->address[index];
5916
5917 default:
5918 assert(!"unknown dst register file");
5919 return ureg_dst_undef();
5920 }
5921 }
5922
5923 static struct ureg_src
5924 translate_src(struct st_translate *t, const st_src_reg *src_reg);
5925
5926 static struct ureg_src
translate_addr(struct st_translate * t,const st_src_reg * reladdr,unsigned addr_index)5927 translate_addr(struct st_translate *t, const st_src_reg *reladdr,
5928 unsigned addr_index)
5929 {
5930 if (t->need_uarl || !reladdr->is_legal_tgsi_address_operand())
5931 return ureg_src(t->address[addr_index]);
5932
5933 return translate_src(t, reladdr);
5934 }
5935
5936 /**
5937 * Create a TGSI ureg_dst register from an st_dst_reg.
5938 */
5939 static struct ureg_dst
translate_dst(struct st_translate * t,const st_dst_reg * dst_reg,bool saturate)5940 translate_dst(struct st_translate *t,
5941 const st_dst_reg *dst_reg,
5942 bool saturate)
5943 {
5944 struct ureg_dst dst = dst_register(t, dst_reg->file, dst_reg->index,
5945 dst_reg->array_id);
5946
5947 if (dst.File == TGSI_FILE_NULL)
5948 return dst;
5949
5950 dst = ureg_writemask(dst, dst_reg->writemask);
5951
5952 if (saturate)
5953 dst = ureg_saturate(dst);
5954
5955 if (dst_reg->reladdr != NULL) {
5956 assert(dst_reg->file != PROGRAM_TEMPORARY);
5957 dst = ureg_dst_indirect(dst, translate_addr(t, dst_reg->reladdr, 0));
5958 }
5959
5960 if (dst_reg->has_index2) {
5961 if (dst_reg->reladdr2)
5962 dst = ureg_dst_dimension_indirect(dst,
5963 translate_addr(t, dst_reg->reladdr2, 1),
5964 dst_reg->index2D);
5965 else
5966 dst = ureg_dst_dimension(dst, dst_reg->index2D);
5967 }
5968
5969 return dst;
5970 }
5971
5972 /**
5973 * Create a TGSI ureg_src register from an st_src_reg.
5974 */
5975 static struct ureg_src
translate_src(struct st_translate * t,const st_src_reg * src_reg)5976 translate_src(struct st_translate *t, const st_src_reg *src_reg)
5977 {
5978 struct ureg_src src;
5979 int index = src_reg->index;
5980 int double_reg2 = src_reg->double_reg2 ? 1 : 0;
5981
5982 switch (src_reg->file) {
5983 case PROGRAM_UNDEFINED:
5984 src = ureg_imm4f(t->ureg, 0, 0, 0, 0);
5985 break;
5986
5987 case PROGRAM_TEMPORARY:
5988 case PROGRAM_ARRAY:
5989 src = ureg_src(dst_register(t, src_reg->file, src_reg->index,
5990 src_reg->array_id));
5991 break;
5992
5993 case PROGRAM_OUTPUT: {
5994 struct ureg_dst dst = dst_register(t, src_reg->file, src_reg->index,
5995 src_reg->array_id);
5996 assert(dst.WriteMask != 0);
5997 unsigned shift = ffs(dst.WriteMask) - 1;
5998 src = ureg_swizzle(ureg_src(dst),
5999 shift,
6000 MIN2(shift + 1, 3),
6001 MIN2(shift + 2, 3),
6002 MIN2(shift + 3, 3));
6003 break;
6004 }
6005
6006 case PROGRAM_UNIFORM:
6007 assert(src_reg->index >= 0);
6008 src = src_reg->index < t->num_constants ?
6009 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6010 break;
6011 case PROGRAM_STATE_VAR:
6012 case PROGRAM_CONSTANT: /* ie, immediate */
6013 if (src_reg->has_index2)
6014 src = ureg_src_register(TGSI_FILE_CONSTANT, src_reg->index);
6015 else
6016 src = src_reg->index >= 0 && src_reg->index < t->num_constants ?
6017 t->constants[src_reg->index] : ureg_imm4f(t->ureg, 0, 0, 0, 0);
6018 break;
6019
6020 case PROGRAM_IMMEDIATE:
6021 assert(src_reg->index >= 0 && src_reg->index < t->num_immediates);
6022 src = t->immediates[src_reg->index];
6023 break;
6024
6025 case PROGRAM_INPUT:
6026 /* GLSL inputs are 64-bit containers, so we have to
6027 * map back to the original index and add the offset after
6028 * mapping. */
6029 index -= double_reg2;
6030 if (!src_reg->array_id) {
6031 assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
6032 assert(t->inputs[t->inputMapping[index]].File != TGSI_FILE_NULL);
6033 src = t->inputs[t->inputMapping[index] + double_reg2];
6034 }
6035 else {
6036 struct inout_decl *decl = find_inout_array(t->input_decls,
6037 t->num_input_decls,
6038 src_reg->array_id);
6039 unsigned mesa_index = decl->mesa_index;
6040 int slot = t->inputMapping[mesa_index];
6041
6042 assert(slot != -1 && t->inputs[slot].File == TGSI_FILE_INPUT);
6043
6044 src = t->inputs[slot];
6045 src.ArrayID = src_reg->array_id;
6046 src = ureg_src_array_offset(src, index + double_reg2 - mesa_index);
6047 }
6048 break;
6049
6050 case PROGRAM_ADDRESS:
6051 src = ureg_src(t->address[src_reg->index]);
6052 break;
6053
6054 case PROGRAM_SYSTEM_VALUE:
6055 assert(src_reg->index < (int) ARRAY_SIZE(t->systemValues));
6056 src = t->systemValues[src_reg->index];
6057 break;
6058
6059 case PROGRAM_HW_ATOMIC:
6060 src = ureg_src_array_register(TGSI_FILE_HW_ATOMIC, src_reg->index,
6061 src_reg->array_id);
6062 break;
6063
6064 default:
6065 assert(!"unknown src register file");
6066 return ureg_src_undef();
6067 }
6068
6069 if (src_reg->has_index2) {
6070 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
6071 * and UBO constant buffers (buffer, position).
6072 */
6073 if (src_reg->reladdr2)
6074 src = ureg_src_dimension_indirect(src,
6075 translate_addr(t, src_reg->reladdr2, 1),
6076 src_reg->index2D);
6077 else
6078 src = ureg_src_dimension(src, src_reg->index2D);
6079 }
6080
6081 src = ureg_swizzle(src,
6082 GET_SWZ(src_reg->swizzle, 0) & 0x3,
6083 GET_SWZ(src_reg->swizzle, 1) & 0x3,
6084 GET_SWZ(src_reg->swizzle, 2) & 0x3,
6085 GET_SWZ(src_reg->swizzle, 3) & 0x3);
6086
6087 if (src_reg->abs)
6088 src = ureg_abs(src);
6089
6090 if ((src_reg->negate & 0xf) == NEGATE_XYZW)
6091 src = ureg_negate(src);
6092
6093 if (src_reg->reladdr != NULL) {
6094 assert(src_reg->file != PROGRAM_TEMPORARY);
6095 src = ureg_src_indirect(src, translate_addr(t, src_reg->reladdr, 0));
6096 }
6097
6098 return src;
6099 }
6100
6101 static struct tgsi_texture_offset
translate_tex_offset(struct st_translate * t,const st_src_reg * in_offset)6102 translate_tex_offset(struct st_translate *t,
6103 const st_src_reg *in_offset)
6104 {
6105 struct tgsi_texture_offset offset;
6106 struct ureg_src src = translate_src(t, in_offset);
6107
6108 offset.File = src.File;
6109 offset.Index = src.Index;
6110 offset.SwizzleX = src.SwizzleX;
6111 offset.SwizzleY = src.SwizzleY;
6112 offset.SwizzleZ = src.SwizzleZ;
6113 offset.Padding = 0;
6114
6115 assert(!src.Indirect);
6116 assert(!src.DimIndirect);
6117 assert(!src.Dimension);
6118 assert(!src.Absolute); /* those shouldn't be used with integers anyway */
6119 assert(!src.Negate);
6120
6121 return offset;
6122 }
6123
6124 static void
compile_tgsi_instruction(struct st_translate * t,const glsl_to_tgsi_instruction * inst)6125 compile_tgsi_instruction(struct st_translate *t,
6126 const glsl_to_tgsi_instruction *inst)
6127 {
6128 struct ureg_program *ureg = t->ureg;
6129 int i;
6130 struct ureg_dst dst[2];
6131 struct ureg_src src[4];
6132 struct tgsi_texture_offset texoffsets[MAX_GLSL_TEXTURE_OFFSET];
6133
6134 int num_dst;
6135 int num_src;
6136 enum tgsi_texture_type tex_target = TGSI_TEXTURE_BUFFER;
6137
6138 num_dst = num_inst_dst_regs(inst);
6139 num_src = num_inst_src_regs(inst);
6140
6141 for (i = 0; i < num_dst; i++)
6142 dst[i] = translate_dst(t,
6143 &inst->dst[i],
6144 inst->saturate);
6145
6146 for (i = 0; i < num_src; i++)
6147 src[i] = translate_src(t, &inst->src[i]);
6148
6149 switch (inst->op) {
6150 case TGSI_OPCODE_BGNLOOP:
6151 case TGSI_OPCODE_ELSE:
6152 case TGSI_OPCODE_ENDLOOP:
6153 case TGSI_OPCODE_IF:
6154 case TGSI_OPCODE_UIF:
6155 assert(num_dst == 0);
6156 ureg_insn(ureg, inst->op, NULL, 0, src, num_src, inst->precise);
6157 return;
6158
6159 case TGSI_OPCODE_TEX:
6160 case TGSI_OPCODE_TEX_LZ:
6161 case TGSI_OPCODE_TXB:
6162 case TGSI_OPCODE_TXD:
6163 case TGSI_OPCODE_TXL:
6164 case TGSI_OPCODE_TXP:
6165 case TGSI_OPCODE_TXQ:
6166 case TGSI_OPCODE_TXQS:
6167 case TGSI_OPCODE_TXF:
6168 case TGSI_OPCODE_TXF_LZ:
6169 case TGSI_OPCODE_TEX2:
6170 case TGSI_OPCODE_TXB2:
6171 case TGSI_OPCODE_TXL2:
6172 case TGSI_OPCODE_TG4:
6173 case TGSI_OPCODE_LODQ:
6174 case TGSI_OPCODE_SAMP2HND:
6175 if (inst->resource.file == PROGRAM_SAMPLER) {
6176 src[num_src] = t->samplers[inst->resource.index];
6177 if (t->tg4_component_in_swizzle && inst->op == TGSI_OPCODE_TG4)
6178 src[num_src].SwizzleX = inst->gather_component;
6179 } else {
6180 /* Bindless samplers. */
6181 src[num_src] = translate_src(t, &inst->resource);
6182 }
6183 assert(src[num_src].File != TGSI_FILE_NULL);
6184 if (inst->resource.reladdr)
6185 src[num_src] =
6186 ureg_src_indirect(src[num_src],
6187 translate_addr(t, inst->resource.reladdr, 2));
6188 num_src++;
6189 for (i = 0; i < (int)inst->tex_offset_num_offset; i++) {
6190 texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
6191 }
6192 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6193
6194 ureg_tex_insn(ureg,
6195 inst->op,
6196 dst, num_dst,
6197 tex_target,
6198 st_translate_texture_type(inst->tex_type),
6199 texoffsets, inst->tex_offset_num_offset,
6200 src, num_src);
6201 return;
6202
6203 case TGSI_OPCODE_RESQ:
6204 case TGSI_OPCODE_LOAD:
6205 case TGSI_OPCODE_ATOMUADD:
6206 case TGSI_OPCODE_ATOMXCHG:
6207 case TGSI_OPCODE_ATOMCAS:
6208 case TGSI_OPCODE_ATOMAND:
6209 case TGSI_OPCODE_ATOMOR:
6210 case TGSI_OPCODE_ATOMXOR:
6211 case TGSI_OPCODE_ATOMUMIN:
6212 case TGSI_OPCODE_ATOMUMAX:
6213 case TGSI_OPCODE_ATOMIMIN:
6214 case TGSI_OPCODE_ATOMIMAX:
6215 case TGSI_OPCODE_ATOMFADD:
6216 case TGSI_OPCODE_IMG2HND:
6217 case TGSI_OPCODE_ATOMINC_WRAP:
6218 case TGSI_OPCODE_ATOMDEC_WRAP:
6219 for (i = num_src - 1; i >= 0; i--)
6220 src[i + 1] = src[i];
6221 num_src++;
6222 if (inst->resource.file == PROGRAM_MEMORY) {
6223 src[0] = t->shared_memory;
6224 } else if (inst->resource.file == PROGRAM_BUFFER) {
6225 src[0] = t->buffers[inst->resource.index];
6226 } else if (inst->resource.file == PROGRAM_HW_ATOMIC) {
6227 src[0] = translate_src(t, &inst->resource);
6228 } else if (inst->resource.file == PROGRAM_CONSTANT) {
6229 assert(inst->resource.has_index2);
6230 src[0] = ureg_src_register(TGSI_FILE_CONSTBUF, inst->resource.index);
6231 } else {
6232 assert(inst->resource.file != PROGRAM_UNDEFINED);
6233 if (inst->resource.file == PROGRAM_IMAGE) {
6234 src[0] = t->images[inst->resource.index];
6235 } else {
6236 /* Bindless images. */
6237 src[0] = translate_src(t, &inst->resource);
6238 }
6239 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6240 }
6241 if (inst->resource.reladdr)
6242 src[0] = ureg_src_indirect(src[0],
6243 translate_addr(t, inst->resource.reladdr, 2));
6244 assert(src[0].File != TGSI_FILE_NULL);
6245 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6246 inst->buffer_access,
6247 tex_target, inst->image_format);
6248 break;
6249
6250 case TGSI_OPCODE_STORE:
6251 if (inst->resource.file == PROGRAM_MEMORY) {
6252 dst[0] = ureg_dst(t->shared_memory);
6253 } else if (inst->resource.file == PROGRAM_BUFFER) {
6254 dst[0] = ureg_dst(t->buffers[inst->resource.index]);
6255 } else {
6256 if (inst->resource.file == PROGRAM_IMAGE) {
6257 dst[0] = ureg_dst(t->images[inst->resource.index]);
6258 } else {
6259 /* Bindless images. */
6260 dst[0] = ureg_dst(translate_src(t, &inst->resource));
6261 }
6262 tex_target = st_translate_texture_target(inst->tex_target, inst->tex_shadow);
6263 }
6264 dst[0] = ureg_writemask(dst[0], inst->dst[0].writemask);
6265 if (inst->resource.reladdr)
6266 dst[0] = ureg_dst_indirect(dst[0],
6267 translate_addr(t, inst->resource.reladdr, 2));
6268 assert(dst[0].File != TGSI_FILE_NULL);
6269 ureg_memory_insn(ureg, inst->op, dst, num_dst, src, num_src,
6270 inst->buffer_access,
6271 tex_target, inst->image_format);
6272 break;
6273
6274 default:
6275 ureg_insn(ureg,
6276 inst->op,
6277 dst, num_dst,
6278 src, num_src, inst->precise);
6279 break;
6280 }
6281 }
6282
6283 /* Invert SamplePos.y when rendering to the default framebuffer. */
6284 static void
emit_samplepos_adjustment(struct st_translate * t,int wpos_y_transform)6285 emit_samplepos_adjustment(struct st_translate *t, int wpos_y_transform)
6286 {
6287 struct ureg_program *ureg = t->ureg;
6288
6289 assert(wpos_y_transform >= 0);
6290 struct ureg_src trans_const = ureg_DECL_constant(ureg, wpos_y_transform);
6291 struct ureg_src samplepos_sysval = t->systemValues[SYSTEM_VALUE_SAMPLE_POS];
6292 struct ureg_dst samplepos_flipped = ureg_DECL_temporary(ureg);
6293 struct ureg_dst is_fbo = ureg_DECL_temporary(ureg);
6294
6295 ureg_ADD(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6296 ureg_imm1f(ureg, 1), ureg_negate(samplepos_sysval));
6297
6298 /* If trans.x == 1, use samplepos.y, else use 1 - samplepos.y. */
6299 ureg_FSEQ(ureg, ureg_writemask(is_fbo, TGSI_WRITEMASK_Y),
6300 ureg_scalar(trans_const, TGSI_SWIZZLE_X), ureg_imm1f(ureg, 1));
6301 ureg_UCMP(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_Y),
6302 ureg_src(is_fbo), samplepos_sysval, ureg_src(samplepos_flipped));
6303 ureg_MOV(ureg, ureg_writemask(samplepos_flipped, TGSI_WRITEMASK_X),
6304 samplepos_sysval);
6305
6306 /* Use the result in place of the system value. */
6307 t->systemValues[SYSTEM_VALUE_SAMPLE_POS] = ureg_src(samplepos_flipped);
6308 }
6309
6310
6311 /**
6312 * Emit the TGSI instructions for inverting and adjusting WPOS.
6313 * This code is unavoidable because it also depends on whether
6314 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6315 */
6316 static void
emit_wpos_adjustment(struct gl_context * ctx,struct st_translate * t,int wpos_transform_const,boolean invert,GLfloat adjX,GLfloat adjY[2])6317 emit_wpos_adjustment(struct gl_context *ctx,
6318 struct st_translate *t,
6319 int wpos_transform_const,
6320 boolean invert,
6321 GLfloat adjX, GLfloat adjY[2])
6322 {
6323 struct ureg_program *ureg = t->ureg;
6324
6325 assert(wpos_transform_const >= 0);
6326
6327 /* Fragment program uses fragment position input.
6328 * Need to replace instances of INPUT[WPOS] with temp T
6329 * where T = INPUT[WPOS] is inverted by Y.
6330 */
6331 struct ureg_src wpostrans = ureg_DECL_constant(ureg, wpos_transform_const);
6332 struct ureg_dst wpos_temp = ureg_DECL_temporary(ureg);
6333 struct ureg_src *wpos =
6334 ctx->Const.GLSLFragCoordIsSysVal ?
6335 &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
6336 &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
6337 struct ureg_src wpos_input = *wpos;
6338
6339 /* First, apply the coordinate shift: */
6340 if (adjX || adjY[0] || adjY[1]) {
6341 if (adjY[0] != adjY[1]) {
6342 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6343 * depending on whether inversion is actually going to be applied
6344 * or not, which is determined by testing against the inversion
6345 * state variable used below, which will be either +1 or -1.
6346 */
6347 struct ureg_dst adj_temp = ureg_DECL_local_temporary(ureg);
6348
6349 ureg_CMP(ureg, adj_temp,
6350 ureg_scalar(wpostrans, invert ? 2 : 0),
6351 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
6352 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
6353 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
6354 } else {
6355 ureg_ADD(ureg, wpos_temp, wpos_input,
6356 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
6357 }
6358 wpos_input = ureg_src(wpos_temp);
6359 } else {
6360 /* MOV wpos_temp, input[wpos]
6361 */
6362 ureg_MOV(ureg, wpos_temp, wpos_input);
6363 }
6364
6365 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6366 * inversion/identity, or the other way around if we're drawing to an FBO.
6367 */
6368 if (invert) {
6369 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6370 */
6371 ureg_MAD(ureg,
6372 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6373 wpos_input,
6374 ureg_scalar(wpostrans, 0),
6375 ureg_scalar(wpostrans, 1));
6376 } else {
6377 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6378 */
6379 ureg_MAD(ureg,
6380 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y),
6381 wpos_input,
6382 ureg_scalar(wpostrans, 2),
6383 ureg_scalar(wpostrans, 3));
6384 }
6385
6386 /* Use wpos_temp as position input from here on:
6387 */
6388 *wpos = ureg_src(wpos_temp);
6389 }
6390
6391
6392 /**
6393 * Emit fragment position/ooordinate code.
6394 */
6395 static void
emit_wpos(struct st_context * st,struct st_translate * t,const struct gl_program * program,struct ureg_program * ureg,int wpos_transform_const)6396 emit_wpos(struct st_context *st,
6397 struct st_translate *t,
6398 const struct gl_program *program,
6399 struct ureg_program *ureg,
6400 int wpos_transform_const)
6401 {
6402 struct pipe_screen *pscreen = st->pipe->screen;
6403 GLfloat adjX = 0.0f;
6404 GLfloat adjY[2] = { 0.0f, 0.0f };
6405 boolean invert = FALSE;
6406
6407 /* Query the pixel center conventions supported by the pipe driver and set
6408 * adjX, adjY to help out if it cannot handle the requested one internally.
6409 *
6410 * The bias of the y-coordinate depends on whether y-inversion takes place
6411 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6412 * drawing to an FBO (causes additional inversion), and whether the pipe
6413 * driver origin and the requested origin differ (the latter condition is
6414 * stored in the 'invert' variable).
6415 *
6416 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6417 *
6418 * center shift only:
6419 * i -> h: +0.5
6420 * h -> i: -0.5
6421 *
6422 * inversion only:
6423 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6424 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6425 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6426 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6427 *
6428 * inversion and center shift:
6429 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6430 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6431 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6432 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6433 */
6434 if (program->info.fs.origin_upper_left) {
6435 /* Fragment shader wants origin in upper-left */
6436 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
6437 /* the driver supports upper-left origin */
6438 }
6439 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
6440 /* the driver supports lower-left origin, need to invert Y */
6441 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6442 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6443 invert = TRUE;
6444 }
6445 else
6446 assert(0);
6447 }
6448 else {
6449 /* Fragment shader wants origin in lower-left */
6450 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
6451 /* the driver supports lower-left origin */
6452 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
6453 TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
6454 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
6455 /* the driver supports upper-left origin, need to invert Y */
6456 invert = TRUE;
6457 else
6458 assert(0);
6459 }
6460
6461 if (program->info.fs.pixel_center_integer) {
6462 /* Fragment shader wants pixel center integer */
6463 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6464 /* the driver supports pixel center integer */
6465 adjY[1] = 1.0f;
6466 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6467 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6468 }
6469 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6470 /* the driver supports pixel center half integer, need to bias X,Y */
6471 adjX = -0.5f;
6472 adjY[0] = -0.5f;
6473 adjY[1] = 0.5f;
6474 }
6475 else
6476 assert(0);
6477 }
6478 else {
6479 /* Fragment shader wants pixel center half integer */
6480 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
6481 /* the driver supports pixel center half integer */
6482 }
6483 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
6484 /* the driver supports pixel center integer, need to bias X,Y */
6485 adjX = adjY[0] = adjY[1] = 0.5f;
6486 ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
6487 TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
6488 }
6489 else
6490 assert(0);
6491 }
6492
6493 /* we invert after adjustment so that we avoid the MOV to temporary,
6494 * and reuse the adjustment ADD instead */
6495 emit_wpos_adjustment(st->ctx, t, wpos_transform_const, invert, adjX, adjY);
6496 }
6497
6498 /**
6499 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6500 * TGSI uses +1 for front, -1 for back.
6501 * This function converts the TGSI value to the GL value. Simply clamping/
6502 * saturating the value to [0,1] does the job.
6503 */
6504 static void
emit_face_var(struct gl_context * ctx,struct st_translate * t)6505 emit_face_var(struct gl_context *ctx, struct st_translate *t)
6506 {
6507 struct ureg_program *ureg = t->ureg;
6508 struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
6509 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
6510
6511 if (ctx->Const.NativeIntegers) {
6512 ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
6513 }
6514 else {
6515 /* MOV_SAT face_temp, input[face] */
6516 ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
6517 }
6518
6519 /* Use face_temp as face input from here on: */
6520 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
6521 }
6522
6523 struct sort_inout_decls {
operator ()sort_inout_decls6524 bool operator()(const struct inout_decl &a, const struct inout_decl &b) const {
6525 return mapping[a.mesa_index] < mapping[b.mesa_index];
6526 }
6527
6528 const ubyte *mapping;
6529 };
6530
6531 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6532 *
6533 * This is for the benefit of older drivers which are broken when the
6534 * declarations aren't sorted in this way.
6535 */
6536 static void
sort_inout_decls_by_slot(struct inout_decl * decls,unsigned count,const ubyte mapping[])6537 sort_inout_decls_by_slot(struct inout_decl *decls,
6538 unsigned count,
6539 const ubyte mapping[])
6540 {
6541 sort_inout_decls sorter;
6542 sorter.mapping = mapping;
6543 std::sort(decls, decls + count, sorter);
6544 }
6545
6546 /**
6547 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6548 * \param program the program to translate
6549 * \param numInputs number of input registers used
6550 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6551 * input indexes
6552 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6553 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6554 * each input
6555 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6556 * \param numOutputs number of output registers used
6557 * \param outputMapping maps Mesa fragment program outputs to TGSI
6558 * generic outputs
6559 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6560 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6561 * each output
6562 *
6563 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6564 */
6565 extern "C" enum pipe_error
st_translate_program(struct gl_context * ctx,enum pipe_shader_type procType,struct ureg_program * ureg,glsl_to_tgsi_visitor * program,const struct gl_program * proginfo,GLuint numInputs,const ubyte inputMapping[],const ubyte inputSlotToAttr[],const ubyte inputSemanticName[],const ubyte inputSemanticIndex[],const ubyte interpMode[],GLuint numOutputs,const ubyte outputMapping[],const ubyte outputSemanticName[],const ubyte outputSemanticIndex[])6566 st_translate_program(
6567 struct gl_context *ctx,
6568 enum pipe_shader_type procType,
6569 struct ureg_program *ureg,
6570 glsl_to_tgsi_visitor *program,
6571 const struct gl_program *proginfo,
6572 GLuint numInputs,
6573 const ubyte inputMapping[],
6574 const ubyte inputSlotToAttr[],
6575 const ubyte inputSemanticName[],
6576 const ubyte inputSemanticIndex[],
6577 const ubyte interpMode[],
6578 GLuint numOutputs,
6579 const ubyte outputMapping[],
6580 const ubyte outputSemanticName[],
6581 const ubyte outputSemanticIndex[])
6582 {
6583 struct pipe_screen *screen = st_context(ctx)->pipe->screen;
6584 struct st_translate *t;
6585 unsigned i;
6586 struct gl_program_constants *frag_const =
6587 &ctx->Const.Program[MESA_SHADER_FRAGMENT];
6588 enum pipe_error ret = PIPE_OK;
6589
6590 assert(numInputs <= ARRAY_SIZE(t->inputs));
6591 assert(numOutputs <= ARRAY_SIZE(t->outputs));
6592
6593 ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
6594 ASSERT_BITFIELD_SIZE(st_src_reg, file, PROGRAM_FILE_MAX);
6595 ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
6596 ASSERT_BITFIELD_SIZE(st_dst_reg, file, PROGRAM_FILE_MAX);
6597 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
6598 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
6599 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
6600 (gl_texture_index) (NUM_TEXTURE_TARGETS - 1));
6601 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format,
6602 (enum pipe_format) (PIPE_FORMAT_COUNT - 1));
6603 ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, op,
6604 (enum tgsi_opcode) (TGSI_OPCODE_LAST - 1));
6605
6606 t = CALLOC_STRUCT(st_translate);
6607 if (!t) {
6608 ret = PIPE_ERROR_OUT_OF_MEMORY;
6609 goto out;
6610 }
6611
6612 t->procType = procType;
6613 t->need_uarl = !screen->get_param(screen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
6614 t->tg4_component_in_swizzle = screen->get_param(screen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
6615 t->inputMapping = inputMapping;
6616 t->outputMapping = outputMapping;
6617 t->ureg = ureg;
6618 t->num_temp_arrays = program->next_array;
6619 if (t->num_temp_arrays)
6620 t->arrays = (struct ureg_dst*)
6621 calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
6622
6623 /*
6624 * Declare input attributes.
6625 */
6626 switch (procType) {
6627 case PIPE_SHADER_FRAGMENT:
6628 case PIPE_SHADER_GEOMETRY:
6629 case PIPE_SHADER_TESS_EVAL:
6630 case PIPE_SHADER_TESS_CTRL:
6631 sort_inout_decls_by_slot(program->inputs, program->num_inputs, inputMapping);
6632
6633 for (i = 0; i < program->num_inputs; ++i) {
6634 struct inout_decl *decl = &program->inputs[i];
6635 unsigned slot = inputMapping[decl->mesa_index];
6636 struct ureg_src src;
6637 ubyte tgsi_usage_mask = decl->usage_mask;
6638
6639 if (glsl_base_type_is_64bit(decl->base_type)) {
6640 if (tgsi_usage_mask == 1)
6641 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6642 else if (tgsi_usage_mask == 2)
6643 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6644 else
6645 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6646 }
6647
6648 enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
6649 enum tgsi_interpolate_loc interp_location = TGSI_INTERPOLATE_LOC_CENTER;
6650 if (procType == PIPE_SHADER_FRAGMENT) {
6651 assert(interpMode);
6652 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
6653 (enum tgsi_interpolate_mode) interpMode[slot] :
6654 tgsi_get_interp_mode(decl->interp,
6655 inputSlotToAttr[slot] == VARYING_SLOT_COL0 ||
6656 inputSlotToAttr[slot] == VARYING_SLOT_COL1);
6657
6658 interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
6659 }
6660
6661 src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
6662 (enum tgsi_semantic) inputSemanticName[slot],
6663 inputSemanticIndex[slot],
6664 interp_mode, 0, interp_location, slot, tgsi_usage_mask,
6665 decl->array_id, decl->size);
6666
6667 for (unsigned j = 0; j < decl->size; ++j) {
6668 if (t->inputs[slot + j].File != TGSI_FILE_INPUT) {
6669 /* The ArrayID is set up in dst_register */
6670 t->inputs[slot + j] = src;
6671 t->inputs[slot + j].ArrayID = 0;
6672 t->inputs[slot + j].Index += j;
6673 }
6674 }
6675 }
6676 break;
6677 case PIPE_SHADER_VERTEX:
6678 for (i = 0; i < numInputs; i++) {
6679 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
6680 }
6681 break;
6682 case PIPE_SHADER_COMPUTE:
6683 break;
6684 default:
6685 assert(0);
6686 }
6687
6688 /*
6689 * Declare output attributes.
6690 */
6691 switch (procType) {
6692 case PIPE_SHADER_FRAGMENT:
6693 case PIPE_SHADER_COMPUTE:
6694 break;
6695 case PIPE_SHADER_GEOMETRY:
6696 case PIPE_SHADER_TESS_EVAL:
6697 case PIPE_SHADER_TESS_CTRL:
6698 case PIPE_SHADER_VERTEX:
6699 sort_inout_decls_by_slot(program->outputs, program->num_outputs, outputMapping);
6700
6701 for (i = 0; i < program->num_outputs; ++i) {
6702 struct inout_decl *decl = &program->outputs[i];
6703 unsigned slot = outputMapping[decl->mesa_index];
6704 struct ureg_dst dst;
6705 ubyte tgsi_usage_mask = decl->usage_mask;
6706
6707 if (glsl_base_type_is_64bit(decl->base_type)) {
6708 if (tgsi_usage_mask == 1)
6709 tgsi_usage_mask = TGSI_WRITEMASK_XY;
6710 else if (tgsi_usage_mask == 2)
6711 tgsi_usage_mask = TGSI_WRITEMASK_ZW;
6712 else
6713 tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
6714 }
6715
6716 dst = ureg_DECL_output_layout(ureg,
6717 (enum tgsi_semantic) outputSemanticName[slot],
6718 outputSemanticIndex[slot],
6719 decl->gs_out_streams,
6720 slot, tgsi_usage_mask, decl->array_id, decl->size, decl->invariant);
6721 dst.Invariant = decl->invariant;
6722 for (unsigned j = 0; j < decl->size; ++j) {
6723 if (t->outputs[slot + j].File != TGSI_FILE_OUTPUT) {
6724 /* The ArrayID is set up in dst_register */
6725 t->outputs[slot + j] = dst;
6726 t->outputs[slot + j].ArrayID = 0;
6727 t->outputs[slot + j].Index += j;
6728 t->outputs[slot + j].Invariant = decl->invariant;
6729 }
6730 }
6731 }
6732 break;
6733 default:
6734 assert(0);
6735 }
6736
6737 if (procType == PIPE_SHADER_FRAGMENT) {
6738 if (proginfo->info.inputs_read & VARYING_BIT_POS) {
6739 /* Must do this after setting up t->inputs. */
6740 emit_wpos(st_context(ctx), t, proginfo, ureg,
6741 program->wpos_transform_const);
6742 }
6743
6744 if (proginfo->info.inputs_read & VARYING_BIT_FACE)
6745 emit_face_var(ctx, t);
6746
6747 for (i = 0; i < numOutputs; i++) {
6748 switch (outputSemanticName[i]) {
6749 case TGSI_SEMANTIC_POSITION:
6750 t->outputs[i] = ureg_DECL_output(ureg,
6751 TGSI_SEMANTIC_POSITION, /* Z/Depth */
6752 outputSemanticIndex[i]);
6753 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Z);
6754 break;
6755 case TGSI_SEMANTIC_STENCIL:
6756 t->outputs[i] = ureg_DECL_output(ureg,
6757 TGSI_SEMANTIC_STENCIL, /* Stencil */
6758 outputSemanticIndex[i]);
6759 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_Y);
6760 break;
6761 case TGSI_SEMANTIC_COLOR:
6762 t->outputs[i] = ureg_DECL_output(ureg,
6763 TGSI_SEMANTIC_COLOR,
6764 outputSemanticIndex[i]);
6765 break;
6766 case TGSI_SEMANTIC_SAMPLEMASK:
6767 t->outputs[i] = ureg_DECL_output(ureg,
6768 TGSI_SEMANTIC_SAMPLEMASK,
6769 outputSemanticIndex[i]);
6770 /* TODO: If we ever support more than 32 samples, this will have
6771 * to become an array.
6772 */
6773 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6774 break;
6775 default:
6776 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6777 ret = PIPE_ERROR_BAD_INPUT;
6778 goto out;
6779 }
6780 }
6781
6782 if (program->shader->Program->sh.fs.BlendSupport)
6783 ureg_property(ureg,
6784 TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED,
6785 program->shader->Program->sh.fs.BlendSupport);
6786
6787 }
6788 else if (procType == PIPE_SHADER_VERTEX) {
6789 for (i = 0; i < numOutputs; i++) {
6790 if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
6791 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6792 ureg_MOV(ureg,
6793 ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
6794 ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
6795 t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
6796 }
6797 }
6798 }
6799
6800 /* Declare address register.
6801 */
6802 if (program->num_address_regs > 0) {
6803 assert(program->num_address_regs <= 3);
6804 for (int i = 0; i < program->num_address_regs; i++)
6805 t->address[i] = ureg_DECL_address(ureg);
6806 }
6807
6808 /* Declare misc input registers
6809 */
6810 BITSET_FOREACH_SET(i, proginfo->info.system_values_read, SYSTEM_VALUE_MAX) {
6811 enum tgsi_semantic semName = tgsi_get_sysval_semantic(i);
6812
6813 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
6814
6815 if (semName == TGSI_SEMANTIC_INSTANCEID ||
6816 semName == TGSI_SEMANTIC_VERTEXID) {
6817 /* From Gallium perspective, these system values are always
6818 * integer, and require native integer support. However, if
6819 * native integer is supported on the vertex stage but not the
6820 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6821 * assumes these system values are floats. To resolve the
6822 * inconsistency, we insert a U2F.
6823 */
6824 struct st_context *st = st_context(ctx);
6825 struct pipe_screen *pscreen = st->pipe->screen;
6826 assert(procType == PIPE_SHADER_VERTEX);
6827 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
6828 (void) pscreen;
6829 if (!ctx->Const.NativeIntegers) {
6830 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
6831 ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
6832 t->systemValues[i]);
6833 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
6834 }
6835 }
6836
6837 if (procType == PIPE_SHADER_FRAGMENT &&
6838 semName == TGSI_SEMANTIC_POSITION)
6839 emit_wpos(st_context(ctx), t, proginfo, ureg,
6840 program->wpos_transform_const);
6841
6842 if (procType == PIPE_SHADER_FRAGMENT &&
6843 semName == TGSI_SEMANTIC_SAMPLEPOS)
6844 emit_samplepos_adjustment(t, program->wpos_transform_const);
6845 }
6846
6847 t->array_sizes = program->array_sizes;
6848 t->input_decls = program->inputs;
6849 t->num_input_decls = program->num_inputs;
6850 t->output_decls = program->outputs;
6851 t->num_output_decls = program->num_outputs;
6852
6853 /* Emit constants and uniforms. TGSI uses a single index space for these,
6854 * so we put all the translated regs in t->constants.
6855 */
6856 if (proginfo->Parameters) {
6857 t->constants = (struct ureg_src *)
6858 calloc(proginfo->Parameters->NumParameters, sizeof(t->constants[0]));
6859 if (t->constants == NULL) {
6860 ret = PIPE_ERROR_OUT_OF_MEMORY;
6861 goto out;
6862 }
6863 t->num_constants = proginfo->Parameters->NumParameters;
6864
6865 for (i = 0; i < proginfo->Parameters->NumParameters; i++) {
6866 unsigned pvo = proginfo->Parameters->ParameterValueOffset[i];
6867
6868 switch (proginfo->Parameters->Parameters[i].Type) {
6869 case PROGRAM_STATE_VAR:
6870 case PROGRAM_UNIFORM:
6871 t->constants[i] = ureg_DECL_constant(ureg, i);
6872 break;
6873
6874 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6875 * addressing of the const buffer.
6876 * FIXME: Be smarter and recognize param arrays:
6877 * indirect addressing is only valid within the referenced
6878 * array.
6879 */
6880 case PROGRAM_CONSTANT:
6881 if (program->indirect_addr_consts)
6882 t->constants[i] = ureg_DECL_constant(ureg, i);
6883 else
6884 t->constants[i] = emit_immediate(t,
6885 proginfo->Parameters->ParameterValues + pvo,
6886 proginfo->Parameters->Parameters[i].DataType,
6887 4);
6888 break;
6889 default:
6890 break;
6891 }
6892 }
6893 }
6894
6895 for (i = 0; i < proginfo->info.num_ubos; i++) {
6896 unsigned size = proginfo->sh.UniformBlocks[i]->UniformBufferSize;
6897 unsigned num_const_vecs = (size + 15) / 16;
6898 unsigned first, last;
6899 assert(num_const_vecs > 0);
6900 first = 0;
6901 last = num_const_vecs > 0 ? num_const_vecs - 1 : 0;
6902 ureg_DECL_constant2D(t->ureg, first, last, i + 1);
6903 }
6904
6905 /* Emit immediate values.
6906 */
6907 t->immediates = (struct ureg_src *)
6908 calloc(program->num_immediates, sizeof(struct ureg_src));
6909 if (t->immediates == NULL) {
6910 ret = PIPE_ERROR_OUT_OF_MEMORY;
6911 goto out;
6912 }
6913 t->num_immediates = program->num_immediates;
6914
6915 i = 0;
6916 foreach_in_list(immediate_storage, imm, &program->immediates) {
6917 assert(i < program->num_immediates);
6918 t->immediates[i++] = emit_immediate(t, imm->values, imm->type, imm->size32);
6919 }
6920 assert(i == program->num_immediates);
6921
6922 /* texture samplers */
6923 for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
6924 if (program->samplers_used & (1u << i)) {
6925 enum tgsi_return_type type =
6926 st_translate_texture_type(program->sampler_types[i]);
6927
6928 t->samplers[i] = ureg_DECL_sampler(ureg, i);
6929
6930 ureg_DECL_sampler_view(ureg, i, program->sampler_targets[i],
6931 type, type, type, type);
6932 }
6933 }
6934
6935 /* Declare atomic and shader storage buffers. */
6936 {
6937 struct gl_program *prog = program->prog;
6938
6939 if (!st_context(ctx)->has_hw_atomics) {
6940 for (i = 0; i < prog->info.num_abos; i++) {
6941 unsigned index = (prog->info.num_ssbos +
6942 prog->sh.AtomicBuffers[i]->Binding);
6943 assert(prog->sh.AtomicBuffers[i]->Binding <
6944 frag_const->MaxAtomicBuffers);
6945 t->buffers[index] = ureg_DECL_buffer(ureg, index, true);
6946 }
6947 } else {
6948 for (i = 0; i < program->num_atomics; i++) {
6949 struct hwatomic_decl *ainfo = &program->atomic_info[i];
6950 gl_uniform_storage *uni_storage = &prog->sh.data->UniformStorage[ainfo->location];
6951 int base = uni_storage->offset / ATOMIC_COUNTER_SIZE;
6952 ureg_DECL_hw_atomic(ureg, base, base + ainfo->size - 1, ainfo->binding,
6953 ainfo->array_id);
6954 }
6955 }
6956
6957 assert(prog->info.num_ssbos <= frag_const->MaxShaderStorageBlocks);
6958 for (i = 0; i < prog->info.num_ssbos; i++) {
6959 t->buffers[i] = ureg_DECL_buffer(ureg, i, false);
6960 }
6961 }
6962
6963 if (program->use_shared_memory)
6964 t->shared_memory = ureg_DECL_memory(ureg, TGSI_MEMORY_TYPE_SHARED);
6965
6966 for (i = 0; i < program->shader->Program->info.num_images; i++) {
6967 if (program->images_used & (1 << i)) {
6968 t->images[i] = ureg_DECL_image(ureg, i,
6969 program->image_targets[i],
6970 program->image_formats[i],
6971 program->image_wr[i],
6972 false);
6973 }
6974 }
6975
6976 /* Emit each instruction in turn:
6977 */
6978 foreach_in_list(glsl_to_tgsi_instruction, inst, &program->instructions)
6979 compile_tgsi_instruction(t, inst);
6980
6981 out:
6982 if (t) {
6983 free(t->arrays);
6984 free(t->temps);
6985 free(t->constants);
6986 t->num_constants = 0;
6987 free(t->immediates);
6988 t->num_immediates = 0;
6989 FREE(t);
6990 }
6991
6992 return ret;
6993 }
6994 /* ----------------------------- End TGSI code ------------------------------ */
6995
6996
6997 /**
6998 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6999 * generating Mesa IR.
7000 */
7001 static struct gl_program *
get_mesa_program_tgsi(struct gl_context * ctx,struct gl_shader_program * shader_program,struct gl_linked_shader * shader)7002 get_mesa_program_tgsi(struct gl_context *ctx,
7003 struct gl_shader_program *shader_program,
7004 struct gl_linked_shader *shader)
7005 {
7006 glsl_to_tgsi_visitor* v;
7007 struct gl_program *prog;
7008 struct gl_shader_compiler_options *options =
7009 &ctx->Const.ShaderCompilerOptions[shader->Stage];
7010 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7011 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(shader->Stage);
7012 unsigned skip_merge_registers;
7013
7014 validate_ir_tree(shader->ir);
7015
7016 prog = shader->Program;
7017
7018 prog->Parameters = _mesa_new_parameter_list();
7019 v = new glsl_to_tgsi_visitor();
7020 v->ctx = ctx;
7021 v->prog = prog;
7022 v->shader_program = shader_program;
7023 v->shader = shader;
7024 v->options = options;
7025 v->native_integers = ctx->Const.NativeIntegers;
7026
7027 v->have_sqrt = pscreen->get_shader_param(pscreen, ptarget,
7028 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED);
7029 v->have_fma = pscreen->get_shader_param(pscreen, ptarget,
7030 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED);
7031 v->has_tex_txf_lz = pscreen->get_param(pscreen,
7032 PIPE_CAP_TGSI_TEX_TXF_LZ);
7033 v->need_uarl = !pscreen->get_param(pscreen, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS);
7034
7035 v->tg4_component_in_swizzle = pscreen->get_param(pscreen, PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE);
7036 v->variables = _mesa_hash_table_create(v->mem_ctx, _mesa_hash_pointer,
7037 _mesa_key_pointer_equal);
7038 skip_merge_registers =
7039 pscreen->get_shader_param(pscreen, ptarget,
7040 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS);
7041
7042 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
7043 prog->Parameters);
7044
7045 /* Remove reads from output registers. */
7046 if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS))
7047 lower_output_reads(shader->Stage, shader->ir);
7048
7049 /* Emit intermediate IR for main(). */
7050 visit_exec_list(shader->ir, v);
7051
7052 #if 0
7053 /* Print out some information (for debugging purposes) used by the
7054 * optimization passes. */
7055 {
7056 int i;
7057 int *first_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7058 int *first_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7059 int *last_writes = ralloc_array(v->mem_ctx, int, v->next_temp);
7060 int *last_reads = ralloc_array(v->mem_ctx, int, v->next_temp);
7061
7062 for (i = 0; i < v->next_temp; i++) {
7063 first_writes[i] = -1;
7064 first_reads[i] = -1;
7065 last_writes[i] = -1;
7066 last_reads[i] = -1;
7067 }
7068 v->get_first_temp_read(first_reads);
7069 v->get_last_temp_read_first_temp_write(last_reads, first_writes);
7070 v->get_last_temp_write(last_writes);
7071 for (i = 0; i < v->next_temp; i++)
7072 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i, first_reads[i],
7073 first_writes[i],
7074 last_reads[i],
7075 last_writes[i]);
7076 ralloc_free(first_writes);
7077 ralloc_free(first_reads);
7078 ralloc_free(last_writes);
7079 ralloc_free(last_reads);
7080 }
7081 #endif
7082
7083 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
7084 v->simplify_cmp();
7085 v->copy_propagate();
7086
7087 while (v->eliminate_dead_code());
7088
7089 v->merge_two_dsts();
7090
7091 if (!skip_merge_registers) {
7092 v->split_arrays();
7093 v->copy_propagate();
7094 while (v->eliminate_dead_code());
7095
7096 v->merge_registers();
7097 v->copy_propagate();
7098 while (v->eliminate_dead_code());
7099 }
7100
7101 v->renumber_registers();
7102
7103 /* Write the END instruction. */
7104 v->emit_asm(NULL, TGSI_OPCODE_END);
7105
7106 if (ctx->_Shader->Flags & GLSL_DUMP) {
7107 _mesa_log("\n");
7108 _mesa_log("GLSL IR for linked %s program %d:\n",
7109 _mesa_shader_stage_to_string(shader->Stage),
7110 shader_program->Name);
7111 _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
7112 _mesa_log("\n\n");
7113 }
7114
7115 do_set_program_inouts(shader->ir, prog, shader->Stage);
7116
7117 _mesa_copy_linked_program_data(shader_program, shader);
7118
7119 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS)) {
7120 mark_array_io(v->inputs, v->num_inputs,
7121 &prog->info.inputs_read,
7122 prog->DualSlotInputs,
7123 &prog->info.patch_inputs_read);
7124
7125 mark_array_io(v->outputs, v->num_outputs,
7126 &prog->info.outputs_written, 0ULL,
7127 &prog->info.patch_outputs_written);
7128 } else {
7129 shrink_array_declarations(v->inputs, v->num_inputs,
7130 &prog->info.inputs_read,
7131 prog->DualSlotInputs,
7132 &prog->info.patch_inputs_read);
7133 shrink_array_declarations(v->outputs, v->num_outputs,
7134 &prog->info.outputs_written, 0ULL,
7135 &prog->info.patch_outputs_written);
7136 }
7137
7138 count_resources(v, prog);
7139
7140 /* The GLSL IR won't be needed anymore. */
7141 ralloc_free(shader->ir);
7142 shader->ir = NULL;
7143
7144 /* This must be done before the uniform storage is associated. */
7145 if (shader->Stage == MESA_SHADER_FRAGMENT &&
7146 (prog->info.inputs_read & VARYING_BIT_POS ||
7147 BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
7148 BITSET_TEST(prog->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS))) {
7149 static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
7150 STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
7151 };
7152
7153 v->wpos_transform_const = _mesa_add_state_reference(prog->Parameters,
7154 wposTransformState);
7155 }
7156
7157 /* Avoid reallocation of the program parameter list, because the uniform
7158 * storage is only associated with the original parameter list.
7159 * This should be enough for Bitmap and DrawPixels constants.
7160 */
7161 _mesa_reserve_parameter_storage(prog->Parameters, 8);
7162
7163 /* This has to be done last. Any operation the can cause
7164 * prog->ParameterValues to get reallocated (e.g., anything that adds a
7165 * program constant) has to happen before creating this linkage.
7166 */
7167 _mesa_associate_uniform_storage(ctx, shader_program, prog);
7168 if (!shader_program->data->LinkStatus) {
7169 free_glsl_to_tgsi_visitor(v);
7170 _mesa_reference_program(ctx, &shader->Program, NULL);
7171 return NULL;
7172 }
7173
7174 st_program(prog)->glsl_to_tgsi = v;
7175
7176 PRINT_STATS(v->print_stats());
7177
7178 return prog;
7179 }
7180
7181 /* See if there are unsupported control flow statements. */
7182 class ir_control_flow_info_visitor : public ir_hierarchical_visitor {
7183 private:
7184 const struct gl_shader_compiler_options *options;
7185 public:
ir_control_flow_info_visitor(const struct gl_shader_compiler_options * options)7186 ir_control_flow_info_visitor(const struct gl_shader_compiler_options *options)
7187 : options(options),
7188 unsupported(false)
7189 {
7190 }
7191
visit_enter(ir_function * ir)7192 virtual ir_visitor_status visit_enter(ir_function *ir)
7193 {
7194 /* Other functions are skipped (same as glsl_to_tgsi). */
7195 if (strcmp(ir->name, "main") == 0)
7196 return visit_continue;
7197
7198 return visit_continue_with_parent;
7199 }
7200
visit_enter(ir_call * ir)7201 virtual ir_visitor_status visit_enter(ir_call *ir)
7202 {
7203 if (!ir->callee->is_intrinsic()) {
7204 unsupported = true; /* it's a function call */
7205 return visit_stop;
7206 }
7207 return visit_continue;
7208 }
7209
visit_enter(ir_return * ir)7210 virtual ir_visitor_status visit_enter(ir_return *ir)
7211 {
7212 if (options->EmitNoMainReturn) {
7213 unsupported = true;
7214 return visit_stop;
7215 }
7216 return visit_continue;
7217 }
7218
7219 bool unsupported;
7220 };
7221
7222 static bool
has_unsupported_control_flow(exec_list * ir,const struct gl_shader_compiler_options * options)7223 has_unsupported_control_flow(exec_list *ir,
7224 const struct gl_shader_compiler_options *options)
7225 {
7226 ir_control_flow_info_visitor visitor(options);
7227 visit_list_elements(&visitor, ir);
7228 return visitor.unsupported;
7229 }
7230
7231 /**
7232 * Link a shader.
7233 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7234 * with code lowering and other optimizations.
7235 */
7236 GLboolean
st_link_tgsi(struct gl_context * ctx,struct gl_shader_program * prog)7237 st_link_tgsi(struct gl_context *ctx, struct gl_shader_program *prog)
7238 {
7239 struct pipe_screen *pscreen = ctx->st->pipe->screen;
7240
7241 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
7242 struct gl_linked_shader *shader = prog->_LinkedShaders[i];
7243 if (shader == NULL)
7244 continue;
7245
7246 exec_list *ir = shader->ir;
7247 gl_shader_stage stage = shader->Stage;
7248 enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
7249 const struct gl_shader_compiler_options *options =
7250 &ctx->Const.ShaderCompilerOptions[stage];
7251
7252 unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
7253 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
7254 if (ctx->Const.GLSLOptimizeConservatively) {
7255 /* Do it once and repeat only if there's unsupported control flow. */
7256 do {
7257 do_common_optimization(ir, true, true, options,
7258 ctx->Const.NativeIntegers);
7259 lower_if_to_cond_assign((gl_shader_stage)i, ir,
7260 options->MaxIfDepth, if_threshold);
7261 } while (has_unsupported_control_flow(ir, options));
7262 } else {
7263 /* Repeat it until it stops making changes. */
7264 bool progress;
7265 do {
7266 progress = do_common_optimization(ir, true, true, options,
7267 ctx->Const.NativeIntegers);
7268 progress |= lower_if_to_cond_assign((gl_shader_stage)i, ir,
7269 options->MaxIfDepth, if_threshold);
7270 } while (progress);
7271 }
7272
7273 /* Do this again to lower ir_binop_vector_extract introduced
7274 * by optimization passes.
7275 */
7276 do_vec_index_to_cond_assign(ir);
7277
7278 validate_ir_tree(ir);
7279
7280 struct gl_program *linked_prog =
7281 get_mesa_program_tgsi(ctx, prog, shader);
7282 st_set_prog_affected_state_flags(linked_prog);
7283
7284 if (linked_prog) {
7285 /* This is really conservative: */
7286 linked_prog->info.writes_memory =
7287 linked_prog->info.num_ssbos ||
7288 linked_prog->info.num_images ||
7289 ctx->Extensions.ARB_bindless_texture ||
7290 (linked_prog->sh.LinkedTransformFeedback &&
7291 linked_prog->sh.LinkedTransformFeedback->NumVarying);
7292
7293 if (!ctx->Driver.ProgramStringNotify(ctx,
7294 _mesa_shader_stage_to_program(i),
7295 linked_prog)) {
7296 _mesa_reference_program(ctx, &shader->Program, NULL);
7297 return GL_FALSE;
7298 }
7299 }
7300 }
7301
7302 return GL_TRUE;
7303 }
7304