1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef GEN8_CONTEXT_H
25 #define GEN8_CONTEXT_H
26
gen8_render_context_init(const struct gen_context_parameters * params,uint32_t * data,uint32_t * size)27 static inline void gen8_render_context_init(const struct gen_context_parameters *params,
28 uint32_t *data, uint32_t *size)
29 {
30 *size = CONTEXT_RENDER_SIZE;
31 if (!data)
32 return;
33
34 *data++ = 0 /* MI_NOOP */;
35 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
36 0x2244 /* CONTEXT_CONTROL */,
37 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
38 0x2034 /* RING_HEAD */, 0,
39 0x2030 /* RING_TAIL */, 0,
40 0x2038 /* RING_BUFFER_START */, params->ring_addr,
41 0x203C /* RING_BUFFER_CONTROL */, (params->ring_addr - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
42 0x2168 /* BB_HEAD_U */, 0,
43 0x2140 /* BB_HEAD_L */, 0,
44 0x2110 /* BB_STATE */, 0,
45 0x211C /* SECOND_BB_HEAD_U */, 0,
46 0x2114 /* SECOND_BB_HEAD_L */, 0,
47 0x2118 /* SECOND_BB_STATE */, 0,
48 0x21C0 /* BB_PER_CTX_PTR */, 0,
49 0x21C4 /* RCS_INDIRECT_CTX */, 0,
50 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0);
51 /* MI_NOOP */
52 *data++ = 0;
53 *data++ = 0;
54
55 *data++ = 0; /* MI_NOOP */
56 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
57 0x23A8 /* CTX_TIMESTAMP */, 0,
58 0x228C /* PDP3_UDW */, 0,
59 0x2288 /* PDP3_LDW */, 0,
60 0x2284 /* PDP2_UDW */, 0,
61 0x2280 /* PDP2_LDW */, 0,
62 0x227C /* PDP1_UDW */, 0,
63 0x2278 /* PDP1_LDW */, 0,
64 0x2274 /* PDP0_UDW */, params->pml4_addr >> 32,
65 0x2270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff);
66 /* MI_NOOP */
67 for (int i = 0; i < 12; i++)
68 *data++ = 0 /* MI_NOOP */;
69
70 *data++ = 0 /* MI_NOOP */;
71 MI_LOAD_REGISTER_IMM_vals(data, 0,
72 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF);
73 *data++ = MI_BATCH_BUFFER_END;
74 }
75
gen8_blitter_context_init(const struct gen_context_parameters * params,uint32_t * data,uint32_t * size)76 static inline void gen8_blitter_context_init(const struct gen_context_parameters *params,
77 uint32_t *data, uint32_t *size)
78 {
79 *size = CONTEXT_OTHER_SIZE;
80 if (!data)
81 return;
82
83 *data++ = 0 /* MI_NOOP */;
84 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
85 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
86 0x22034 /* RING_HEAD */, 0,
87 0x22030 /* RING_TAIL */, 0,
88 0x22038 /* RING_BUFFER_START */, params->ring_addr,
89 0x2203C /* RING_BUFFER_CONTROL */, (params->ring_size - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
90 0x22168 /* BB_HEAD_U */, 0,
91 0x22140 /* BB_HEAD_L */, 0,
92 0x22110 /* BB_STATE */, 0,
93 0x2211C /* SECOND_BB_HEAD_U */, 0,
94 0x22114 /* SECOND_BB_HEAD_L */, 0,
95 0x22118 /* SECOND_BB_STATE */, 0);
96
97 for (int i = 0; i < 8; i++)
98 *data++ = 0 /* MI_NOOP */;
99
100 *data = 0 /* MI_NOOP */;
101 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
102 0x223A8 /* CTX_TIMESTAMP */, 0,
103 0x2228C /* PDP3_UDW */, 0,
104 0x22288 /* PDP3_LDW */, 0,
105 0x22284 /* PDP2_UDW */, 0,
106 0x22280 /* PDP2_LDW */, 0,
107 0x2227C /* PDP1_UDW */, 0,
108 0x22278 /* PDP1_LDW */, 0,
109 0x22274 /* PDP0_UDW */, params->pml4_addr >> 32,
110 0x22270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff);
111
112 for (int i = 0; i < 12; i++)
113 *data++ = 0 /* MI_NOOP */;
114
115 *data++ = MI_BATCH_BUFFER_END;
116 }
117
gen8_video_context_init(const struct gen_context_parameters * params,uint32_t * data,uint32_t * size)118 static inline void gen8_video_context_init(const struct gen_context_parameters *params,
119 uint32_t *data, uint32_t *size)
120 {
121 *size = CONTEXT_OTHER_SIZE;
122 if (!data)
123 return;
124
125 *data++ = 0 /* MI_NOOP */;
126 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
127 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
128 0x1C034 /* RING_HEAD */, 0,
129 0x1C030 /* RING_TAIL */, 0,
130 0x1C038 /* RING_BUFFER_START */, params->ring_addr,
131 0x1C03C /* RING_BUFFER_CONTROL */, (params->ring_size - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
132 0x1C168 /* BB_HEAD_U */, 0,
133 0x1C140 /* BB_HEAD_L */, 0,
134 0x1C110 /* BB_STATE */, 0,
135 0x1C11C /* SECOND_BB_HEAD_U */, 0,
136 0x1C114 /* SECOND_BB_HEAD_L */, 0,
137 0x1C118 /* SECOND_BB_STATE */, 0);
138 for (int i = 0; i < 8; i++)
139 *data++ = 0 /* MI_NOOP */;
140
141 *data++ = 0 /* MI_NOOP */;
142 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
143 0x1C3A8 /* CTX_TIMESTAMP */, 0,
144 0x1C28C /* PDP3_UDW */, 0,
145 0x1C288 /* PDP3_LDW */, 0,
146 0x1C284 /* PDP2_UDW */, 0,
147 0x1C280 /* PDP2_LDW */, 0,
148 0x1C27C /* PDP1_UDW */, 0,
149 0x1C278 /* PDP1_LDW */, 0,
150 0x1C274 /* PDP0_UDW */, params->pml4_addr >> 32,
151 0x1C270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff);
152 for (int i = 0; i < 12; i++)
153 *data++ = 0 /* MI_NOOP */;
154
155 *data++ = MI_BATCH_BUFFER_END;
156 }
157
158 #endif /* GEN8_CONTEXT_H */
159