1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "util/mesa-sha1.h"
34
35 static enum brw_reg_file
brw_file_from_reg(fs_reg * reg)36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
brw_reg_from_fs_reg(const struct gen_device_info * devinfo,fs_inst * inst,fs_reg * reg,bool compressed)57 brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
58 fs_reg *reg, bool compressed)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else {
70 /* From the Haswell PRM:
71 *
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
74 * boundaries."
75 *
76 * The maximum width value that could satisfy this restriction is:
77 */
78 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
79
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
84 */
85 const unsigned phys_width = compressed ? inst->exec_size / 2 :
86 inst->exec_size;
87
88 const unsigned max_hw_width = 16;
89
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
95 */
96 if (reg->stride > 4) {
97 assert(reg != &inst->dst);
98 assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
99 brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
100 brw_reg = stride(brw_reg, reg->stride, 1, 0);
101 } else {
102 const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
103 brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
104 brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
105 }
106
107 if (devinfo->gen == 7 && !devinfo->is_haswell) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
114 * appropriately."
115 *
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
122 * of floats."
123 *
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
126 *
127 * It applies to BayTrail too.
128 */
129 if (type_sz(reg->type) == 8) {
130 brw_reg.width++;
131 if (brw_reg.vstride > 0)
132 brw_reg.vstride++;
133 assert(brw_reg.hstride == BRW_HORIZONTAL_STRIDE_1);
134 }
135
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
141 */
142 if (reg == &inst->dst && get_exec_type_size(inst) == 8 &&
143 type_sz(inst->dst.type) < 8) {
144 assert(brw_reg.hstride > BRW_HORIZONTAL_STRIDE_1);
145 brw_reg.hstride--;
146 }
147 }
148 }
149
150 brw_reg = retype(brw_reg, reg->type);
151 brw_reg = byte_offset(brw_reg, reg->offset);
152 brw_reg.abs = reg->abs;
153 brw_reg.negate = reg->negate;
154 break;
155 case ARF:
156 case FIXED_GRF:
157 case IMM:
158 assert(reg->offset == 0);
159 brw_reg = reg->as_brw_reg();
160 break;
161 case BAD_FILE:
162 /* Probably unused. */
163 brw_reg = brw_null_reg();
164 break;
165 case ATTR:
166 case UNIFORM:
167 unreachable("not reached");
168 }
169
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
173 */
174 if (devinfo->gen == 7 && !devinfo->is_haswell &&
175 type_sz(reg->type) == 8 &&
176 brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
177 brw_reg.width == BRW_WIDTH_1 &&
178 brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
179 brw_reg.width = BRW_WIDTH_2;
180 brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1;
181 }
182
183 return brw_reg;
184 }
185
fs_generator(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,struct brw_stage_prog_data * prog_data,bool runtime_check_aads_emit,gl_shader_stage stage)186 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
187 void *mem_ctx,
188 struct brw_stage_prog_data *prog_data,
189 bool runtime_check_aads_emit,
190 gl_shader_stage stage)
191
192 : compiler(compiler), log_data(log_data),
193 devinfo(compiler->devinfo),
194 prog_data(prog_data), dispatch_width(0),
195 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
196 shader_name(NULL), stage(stage), mem_ctx(mem_ctx)
197 {
198 p = rzalloc(mem_ctx, struct brw_codegen);
199 brw_init_codegen(devinfo, p, mem_ctx);
200
201 /* In the FS code generator, we are very careful to ensure that we always
202 * set the right execution size so we don't need the EU code to "help" us
203 * by trying to infer it. Sometimes, it infers the wrong thing.
204 */
205 p->automatic_exec_sizes = false;
206 }
207
~fs_generator()208 fs_generator::~fs_generator()
209 {
210 }
211
212 class ip_record : public exec_node {
213 public:
214 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
215
ip_record(int ip)216 ip_record(int ip)
217 {
218 this->ip = ip;
219 }
220
221 int ip;
222 };
223
224 bool
patch_discard_jumps_to_fb_writes()225 fs_generator::patch_discard_jumps_to_fb_writes()
226 {
227 if (this->discard_halt_patches.is_empty())
228 return false;
229
230 int scale = brw_jump_scale(p->devinfo);
231
232 if (devinfo->gen >= 6) {
233 /* There is a somewhat strange undocumented requirement of using
234 * HALT, according to the simulator. If some channel has HALTed to
235 * a particular UIP, then by the end of the program, every channel
236 * must have HALTed to that UIP. Furthermore, the tracking is a
237 * stack, so you can't do the final halt of a UIP after starting
238 * halting to a new UIP.
239 *
240 * Symptoms of not emitting this instruction on actual hardware
241 * included GPU hangs and sparkly rendering on the piglit discard
242 * tests.
243 */
244 brw_inst *last_halt = brw_HALT(p);
245 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
246 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
247 }
248
249 int ip = p->nr_insn;
250
251 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
252 brw_inst *patch = &p->store[patch_ip->ip];
253
254 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
255 if (devinfo->gen >= 6) {
256 /* HALT takes a half-instruction distance from the pre-incremented IP. */
257 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
258 } else {
259 brw_set_src1(p, patch, brw_imm_d((ip - patch_ip->ip) * scale));
260 }
261 }
262
263 this->discard_halt_patches.make_empty();
264
265 if (devinfo->gen < 6) {
266 /* From the g965 PRM:
267 *
268 * "As DMask is not automatically reloaded into AMask upon completion
269 * of this instruction, software has to manually restore AMask upon
270 * completion."
271 *
272 * DMask lives in the bottom 16 bits of sr0.1.
273 */
274 brw_inst *reset = brw_MOV(p, brw_mask_reg(BRW_AMASK),
275 retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW));
276 brw_inst_set_exec_size(devinfo, reset, BRW_EXECUTE_1);
277 brw_inst_set_mask_control(devinfo, reset, BRW_MASK_DISABLE);
278 brw_inst_set_qtr_control(devinfo, reset, BRW_COMPRESSION_NONE);
279 brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH);
280 }
281
282 if (devinfo->gen == 4 && !devinfo->is_g4x) {
283 /* From the g965 PRM:
284 *
285 * "[DevBW, DevCL] Erratum: The subfields in mask stack register are
286 * reset to zero during graphics reset, however, they are not
287 * initialized at thread dispatch. These subfields will retain the
288 * values from the previous thread. Software should make sure the
289 * mask stack is empty (reset to zero) before terminating the thread.
290 * In case that this is not practical, software may have to reset the
291 * mask stack at the beginning of each kernel, which will impact the
292 * performance."
293 *
294 * Luckily we can rely on:
295 *
296 * "[DevBW, DevCL] This register access restriction is not
297 * applicable, hardware does ensure execution pipeline coherency,
298 * when a mask stack register is used as an explicit source and/or
299 * destination."
300 */
301 brw_push_insn_state(p);
302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
303 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
304
305 brw_set_default_exec_size(p, BRW_EXECUTE_2);
306 brw_MOV(p, vec2(brw_mask_stack_depth_reg(0)), brw_imm_uw(0));
307
308 brw_set_default_exec_size(p, BRW_EXECUTE_16);
309 /* Reset the if stack. */
310 brw_MOV(p, retype(brw_mask_stack_reg(0), BRW_REGISTER_TYPE_UW),
311 brw_imm_uw(0));
312
313 brw_pop_insn_state(p);
314 }
315
316 return true;
317 }
318
319 void
generate_send(fs_inst * inst,struct brw_reg dst,struct brw_reg desc,struct brw_reg ex_desc,struct brw_reg payload,struct brw_reg payload2)320 fs_generator::generate_send(fs_inst *inst,
321 struct brw_reg dst,
322 struct brw_reg desc,
323 struct brw_reg ex_desc,
324 struct brw_reg payload,
325 struct brw_reg payload2)
326 {
327 const bool dst_is_null = dst.file == BRW_ARCHITECTURE_REGISTER_FILE &&
328 dst.nr == BRW_ARF_NULL;
329 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE;
330
331 uint32_t desc_imm = inst->desc |
332 brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size);
333
334 uint32_t ex_desc_imm = brw_message_ex_desc(devinfo, inst->ex_mlen);
335
336 if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm) {
337 /* If we have any sort of extended descriptor, then we need SENDS. This
338 * also covers the dual-payload case because ex_mlen goes in ex_desc.
339 */
340 brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2,
341 desc, desc_imm, ex_desc, ex_desc_imm,
342 inst->eot);
343 if (inst->check_tdr)
344 brw_inst_set_opcode(p->devinfo, brw_last_inst,
345 devinfo->gen >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
346 } else {
347 brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
348 inst->eot);
349 if (inst->check_tdr)
350 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
351 }
352 }
353
354 void
fire_fb_write(fs_inst * inst,struct brw_reg payload,struct brw_reg implied_header,GLuint nr)355 fs_generator::fire_fb_write(fs_inst *inst,
356 struct brw_reg payload,
357 struct brw_reg implied_header,
358 GLuint nr)
359 {
360 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
361
362 if (devinfo->gen < 6) {
363 brw_push_insn_state(p);
364 brw_set_default_exec_size(p, BRW_EXECUTE_8);
365 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
366 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
367 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
368 brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
369 offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
370 brw_pop_insn_state(p);
371 }
372
373 uint32_t msg_control = brw_fb_write_msg_control(inst, prog_data);
374
375 /* We assume render targets start at 0, because headerless FB write
376 * messages set "Render Target Index" to 0. Using a different binding
377 * table index would make it impossible to use headerless messages.
378 */
379 const uint32_t surf_index = inst->target;
380
381 brw_inst *insn = brw_fb_WRITE(p,
382 payload,
383 retype(implied_header, BRW_REGISTER_TYPE_UW),
384 msg_control,
385 surf_index,
386 nr,
387 0,
388 inst->eot,
389 inst->last_rt,
390 inst->header_size != 0);
391
392 if (devinfo->gen >= 6)
393 brw_inst_set_rt_slot_group(devinfo, insn, inst->group / 16);
394 }
395
396 void
generate_fb_write(fs_inst * inst,struct brw_reg payload)397 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
398 {
399 if (devinfo->gen < 8 && !devinfo->is_haswell) {
400 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
401 brw_set_default_flag_reg(p, 0, 0);
402 }
403
404 const struct brw_reg implied_header =
405 devinfo->gen < 6 ? payload : brw_null_reg();
406
407 if (inst->base_mrf >= 0)
408 payload = brw_message_reg(inst->base_mrf);
409
410 if (!runtime_check_aads_emit) {
411 fire_fb_write(inst, payload, implied_header, inst->mlen);
412 } else {
413 /* This can only happen in gen < 6 */
414 assert(devinfo->gen < 6);
415
416 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
417
418 /* Check runtime bit to detect if we have to send AA data or not */
419 brw_push_insn_state(p);
420 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
421 brw_set_default_exec_size(p, BRW_EXECUTE_1);
422 brw_AND(p,
423 v1_null_ud,
424 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
425 brw_imm_ud(1<<26));
426 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
427
428 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
429 brw_pop_insn_state(p);
430 {
431 /* Don't send AA data */
432 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
433 }
434 brw_land_fwd_jump(p, jmp);
435 fire_fb_write(inst, payload, implied_header, inst->mlen);
436 }
437 }
438
439 void
generate_fb_read(fs_inst * inst,struct brw_reg dst,struct brw_reg payload)440 fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst,
441 struct brw_reg payload)
442 {
443 assert(inst->size_written % REG_SIZE == 0);
444 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
445 /* We assume that render targets start at binding table index 0. */
446 const unsigned surf_index = inst->target;
447
448 gen9_fb_READ(p, dst, payload, surf_index,
449 inst->header_size, inst->size_written / REG_SIZE,
450 prog_data->persample_dispatch);
451 }
452
453 void
generate_mov_indirect(fs_inst * inst,struct brw_reg dst,struct brw_reg reg,struct brw_reg indirect_byte_offset)454 fs_generator::generate_mov_indirect(fs_inst *inst,
455 struct brw_reg dst,
456 struct brw_reg reg,
457 struct brw_reg indirect_byte_offset)
458 {
459 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
460 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
461 assert(!reg.abs && !reg.negate);
462 assert(reg.type == dst.type);
463
464 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
465
466 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
467 imm_byte_offset += indirect_byte_offset.ud;
468
469 reg.nr = imm_byte_offset / REG_SIZE;
470 reg.subnr = imm_byte_offset % REG_SIZE;
471 if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
472 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
473 subscript(reg, BRW_REGISTER_TYPE_D, 0));
474 brw_set_default_swsb(p, tgl_swsb_null());
475 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
476 subscript(reg, BRW_REGISTER_TYPE_D, 1));
477 } else {
478 brw_MOV(p, dst, reg);
479 }
480 } else {
481 /* Prior to Broadwell, there are only 8 address registers. */
482 assert(inst->exec_size <= 8 || devinfo->gen >= 8);
483
484 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
485 struct brw_reg addr = vec8(brw_address_reg(0));
486
487 /* Whether we can use destination dependency control without running the
488 * risk of a hang if an instruction gets shot down.
489 */
490 const bool use_dep_ctrl = !inst->predicate &&
491 inst->exec_size == dispatch_width;
492 brw_inst *insn;
493
494 /* The destination stride of an instruction (in bytes) must be greater
495 * than or equal to the size of the rest of the instruction. Since the
496 * address register is of type UW, we can't use a D-type instruction.
497 * In order to get around this, re retype to UW and use a stride.
498 */
499 indirect_byte_offset =
500 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
501
502 /* There are a number of reasons why we don't use the base offset here.
503 * One reason is that the field is only 9 bits which means we can only
504 * use it to access the first 16 GRFs. Also, from the Haswell PRM
505 * section "Register Region Restrictions":
506 *
507 * "The lower bits of the AddressImmediate must not overflow to
508 * change the register address. The lower 5 bits of Address
509 * Immediate when added to lower 5 bits of address register gives
510 * the sub-register offset. The upper bits of Address Immediate
511 * when added to upper bits of address register gives the register
512 * address. Any overflow from sub-register offset is dropped."
513 *
514 * Since the indirect may cause us to cross a register boundary, this
515 * makes the base offset almost useless. We could try and do something
516 * clever where we use a actual base offset if base_offset % 32 == 0 but
517 * that would mean we were generating different code depending on the
518 * base offset. Instead, for the sake of consistency, we'll just do the
519 * add ourselves. This restriction is only listed in the Haswell PRM
520 * but empirical testing indicates that it applies on all older
521 * generations and is lifted on Broadwell.
522 *
523 * In the end, while base_offset is nice to look at in the generated
524 * code, using it saves us 0 instructions and would require quite a bit
525 * of case-by-case work. It's just not worth it.
526 *
527 * Due to a hardware bug some platforms (particularly Gen11+) seem to
528 * require the address components of all channels to be valid whether or
529 * not they're active, which causes issues if we use VxH addressing
530 * under non-uniform control-flow. We can easily work around that by
531 * initializing the whole address register with a pipelined NoMask MOV
532 * instruction.
533 */
534 if (devinfo->gen >= 7) {
535 insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
536 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
537 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
538 if (devinfo->gen >= 12)
539 brw_set_default_swsb(p, tgl_swsb_null());
540 else
541 brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
542 }
543
544 insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
545 if (devinfo->gen >= 12)
546 brw_set_default_swsb(p, tgl_swsb_regdist(1));
547 else if (devinfo->gen >= 7)
548 brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
549
550 if (type_sz(reg.type) > 4 &&
551 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
552 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
553 !devinfo->has_64bit_float)) {
554 /* IVB has an issue (which we found empirically) where it reads two
555 * address register components per channel for indirectly addressed
556 * 64-bit sources.
557 *
558 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
559 *
560 * "When source or destination datatype is 64b or operation is
561 * integer DWord multiply, indirect addressing must not be used."
562 *
563 * To work around both of these, we do two integer MOVs insead of one
564 * 64-bit MOV. Because no double value should ever cross a register
565 * boundary, it's safe to use the immediate offset in the indirect
566 * here to handle adding 4 bytes to the offset and avoid the extra
567 * ADD to the register file.
568 */
569 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
570 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
571 brw_set_default_swsb(p, tgl_swsb_null());
572 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
573 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
574 } else {
575 struct brw_reg ind_src = brw_VxH_indirect(0, 0);
576
577 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type));
578
579 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
580 !inst->get_next()->is_tail_sentinel() &&
581 ((fs_inst *)inst->get_next())->mlen > 0) {
582 /* From the Sandybridge PRM:
583 *
584 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
585 * instruction that “indexed/indirect” source AND is followed
586 * by a send, the instruction requires a “Switch”. This is to
587 * avoid race condition where send may dispatch before MRF is
588 * updated."
589 */
590 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
591 }
592 }
593 }
594 }
595
596 void
generate_shuffle(fs_inst * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg idx)597 fs_generator::generate_shuffle(fs_inst *inst,
598 struct brw_reg dst,
599 struct brw_reg src,
600 struct brw_reg idx)
601 {
602 /* Ivy bridge has some strange behavior that makes this a real pain to
603 * implement for 64-bit values so we just don't bother.
604 */
605 assert(devinfo->gen >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
606
607 /* Because we're using the address register, we're limited to 8-wide
608 * execution on gen7. On gen8, we're limited to 16-wide by the address
609 * register file and 8-wide for 64-bit types. We could try and make this
610 * instruction splittable higher up in the compiler but that gets weird
611 * because it reads all of the channels regardless of execution size. It's
612 * easier just to split it here.
613 */
614 const unsigned lower_width =
615 (devinfo->gen <= 7 || type_sz(src.type) > 4) ?
616 8 : MIN2(16, inst->exec_size);
617
618 brw_set_default_exec_size(p, cvt(lower_width) - 1);
619 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
620 brw_set_default_group(p, group);
621
622 if ((src.vstride == 0 && src.hstride == 0) ||
623 idx.file == BRW_IMMEDIATE_VALUE) {
624 /* Trivial, the source is already uniform or the index is a constant.
625 * We will typically not get here if the optimizer is doing its job,
626 * but asserting would be mean.
627 */
628 const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
629 brw_MOV(p, suboffset(dst, group), stride(suboffset(src, i), 0, 1, 0));
630 } else {
631 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
632 struct brw_reg addr = vec8(brw_address_reg(0));
633
634 struct brw_reg group_idx = suboffset(idx, group);
635
636 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
637 /* Things get grumpy if the register is too wide. */
638 group_idx.width--;
639 group_idx.vstride--;
640 }
641
642 assert(type_sz(group_idx.type) <= 4);
643 if (type_sz(group_idx.type) == 4) {
644 /* The destination stride of an instruction (in bytes) must be
645 * greater than or equal to the size of the rest of the
646 * instruction. Since the address register is of type UW, we
647 * can't use a D-type instruction. In order to get around this,
648 * re retype to UW and use a stride.
649 */
650 group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W);
651 }
652
653 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
654
655 /* From the Haswell PRM:
656 *
657 * "When a sequence of NoDDChk and NoDDClr are used, the last
658 * instruction that completes the scoreboard clear must have a
659 * non-zero execution mask. This means, if any kind of predication
660 * can change the execution mask or channel enable of the last
661 * instruction, the optimization must be avoided. This is to
662 * avoid instructions being shot down the pipeline when no writes
663 * are required."
664 *
665 * Whenever predication is enabled or the instructions being emitted
666 * aren't the full width, it's possible that it will be run with zero
667 * channels enabled so we can't use dependency control without
668 * running the risk of a hang if an instruction gets shot down.
669 */
670 const bool use_dep_ctrl = !inst->predicate &&
671 lower_width == dispatch_width;
672 brw_inst *insn;
673
674 /* Due to a hardware bug some platforms (particularly Gen11+) seem
675 * to require the address components of all channels to be valid
676 * whether or not they're active, which causes issues if we use VxH
677 * addressing under non-uniform control-flow. We can easily work
678 * around that by initializing the whole address register with a
679 * pipelined NoMask MOV instruction.
680 */
681 insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset));
682 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
683 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
684 if (devinfo->gen >= 12)
685 brw_set_default_swsb(p, tgl_swsb_null());
686 else
687 brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
688
689 /* Take into account the component size and horizontal stride. */
690 assert(src.vstride == src.hstride + src.width);
691 insn = brw_SHL(p, addr, group_idx,
692 brw_imm_uw(util_logbase2(type_sz(src.type)) +
693 src.hstride - 1));
694 if (devinfo->gen >= 12)
695 brw_set_default_swsb(p, tgl_swsb_regdist(1));
696 else
697 brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
698
699 /* Add on the register start offset */
700 brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
701
702 if (type_sz(src.type) > 4 &&
703 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
704 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
705 /* IVB has an issue (which we found empirically) where it reads
706 * two address register components per channel for indirectly
707 * addressed 64-bit sources.
708 *
709 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
710 *
711 * "When source or destination datatype is 64b or operation is
712 * integer DWord multiply, indirect addressing must not be
713 * used."
714 *
715 * To work around both of these, we do two integer MOVs insead of
716 * one 64-bit MOV. Because no double value should ever cross a
717 * register boundary, it's safe to use the immediate offset in the
718 * indirect here to handle adding 4 bytes to the offset and avoid
719 * the extra ADD to the register file.
720 */
721 struct brw_reg gdst = suboffset(dst, group);
722 struct brw_reg dst_d = retype(spread(gdst, 2),
723 BRW_REGISTER_TYPE_D);
724 assert(dst.hstride == 1);
725 brw_MOV(p, dst_d,
726 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
727 brw_set_default_swsb(p, tgl_swsb_null());
728 brw_MOV(p, byte_offset(dst_d, 4),
729 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
730 } else {
731 brw_MOV(p, suboffset(dst, group * dst.hstride),
732 retype(brw_VxH_indirect(0, 0), src.type));
733 }
734 }
735
736 brw_set_default_swsb(p, tgl_swsb_null());
737 }
738 }
739
740 void
generate_quad_swizzle(const fs_inst * inst,struct brw_reg dst,struct brw_reg src,unsigned swiz)741 fs_generator::generate_quad_swizzle(const fs_inst *inst,
742 struct brw_reg dst, struct brw_reg src,
743 unsigned swiz)
744 {
745 /* Requires a quad. */
746 assert(inst->exec_size >= 4);
747
748 if (src.file == BRW_IMMEDIATE_VALUE ||
749 has_scalar_region(src)) {
750 /* The value is uniform across all channels */
751 brw_MOV(p, dst, src);
752
753 } else if (devinfo->gen < 11 && type_sz(src.type) == 4) {
754 /* This only works on 8-wide 32-bit values */
755 assert(inst->exec_size == 8);
756 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
757 assert(src.vstride == src.width + 1);
758 brw_set_default_access_mode(p, BRW_ALIGN_16);
759 struct brw_reg swiz_src = stride(src, 4, 4, 1);
760 swiz_src.swizzle = swiz;
761 brw_MOV(p, dst, swiz_src);
762
763 } else {
764 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
765 assert(src.vstride == src.width + 1);
766 const struct brw_reg src_0 = suboffset(src, BRW_GET_SWZ(swiz, 0));
767
768 switch (swiz) {
769 case BRW_SWIZZLE_XXXX:
770 case BRW_SWIZZLE_YYYY:
771 case BRW_SWIZZLE_ZZZZ:
772 case BRW_SWIZZLE_WWWW:
773 brw_MOV(p, dst, stride(src_0, 4, 4, 0));
774 break;
775
776 case BRW_SWIZZLE_XXZZ:
777 case BRW_SWIZZLE_YYWW:
778 brw_MOV(p, dst, stride(src_0, 2, 2, 0));
779 break;
780
781 case BRW_SWIZZLE_XYXY:
782 case BRW_SWIZZLE_ZWZW:
783 assert(inst->exec_size == 4);
784 brw_MOV(p, dst, stride(src_0, 0, 2, 1));
785 break;
786
787 default:
788 assert(inst->force_writemask_all);
789 brw_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
790
791 for (unsigned c = 0; c < 4; c++) {
792 brw_inst *insn = brw_MOV(
793 p, stride(suboffset(dst, c),
794 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
795 stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
796
797 if (devinfo->gen < 12) {
798 brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
799 brw_inst_set_no_dd_check(devinfo, insn, c > 0);
800 }
801
802 brw_set_default_swsb(p, tgl_swsb_null());
803 }
804
805 break;
806 }
807 }
808 }
809
810 void
generate_urb_read(fs_inst * inst,struct brw_reg dst,struct brw_reg header)811 fs_generator::generate_urb_read(fs_inst *inst,
812 struct brw_reg dst,
813 struct brw_reg header)
814 {
815 assert(inst->size_written % REG_SIZE == 0);
816 assert(header.file == BRW_GENERAL_REGISTER_FILE);
817 assert(header.type == BRW_REGISTER_TYPE_UD);
818
819 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
820 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
821 brw_set_src0(p, send, header);
822 if (devinfo->gen < 12)
823 brw_set_src1(p, send, brw_imm_ud(0u));
824
825 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
826 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
827
828 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
829 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
830
831 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
832 brw_inst_set_rlen(p->devinfo, send, inst->size_written / REG_SIZE);
833 brw_inst_set_header_present(p->devinfo, send, true);
834 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
835 }
836
837 void
generate_urb_write(fs_inst * inst,struct brw_reg payload)838 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
839 {
840 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
841
842 brw_set_dest(p, insn, brw_null_reg());
843 brw_set_src0(p, insn, payload);
844 if (devinfo->gen < 12)
845 brw_set_src1(p, insn, brw_imm_ud(0u));
846
847 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
848 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
849
850 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
851 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
852 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
853
854 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
855 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
856 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
857
858 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
859 brw_inst_set_rlen(p->devinfo, insn, 0);
860 brw_inst_set_eot(p->devinfo, insn, inst->eot);
861 brw_inst_set_header_present(p->devinfo, insn, true);
862 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
863 }
864
865 void
generate_cs_terminate(fs_inst * inst,struct brw_reg payload)866 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
867 {
868 struct brw_inst *insn;
869
870 insn = brw_next_insn(p, BRW_OPCODE_SEND);
871
872 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
873 brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
874 if (devinfo->gen < 12)
875 brw_set_src1(p, insn, brw_imm_ud(0u));
876
877 /* Terminate a compute shader by sending a message to the thread spawner.
878 */
879 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
880 brw_inst_set_mlen(devinfo, insn, 1);
881 brw_inst_set_rlen(devinfo, insn, 0);
882 brw_inst_set_eot(devinfo, insn, inst->eot);
883 brw_inst_set_header_present(devinfo, insn, false);
884
885 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
886
887 if (devinfo->gen < 11) {
888 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
889
890 /* Note that even though the thread has a URB resource associated with it,
891 * we set the "do not dereference URB" bit, because the URB resource is
892 * managed by the fixed-function unit, so it will free it automatically.
893 */
894 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
895 }
896
897 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
898 }
899
900 void
generate_barrier(fs_inst *,struct brw_reg src)901 fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
902 {
903 brw_barrier(p, src);
904 if (devinfo->gen >= 12) {
905 brw_set_default_swsb(p, tgl_swsb_null());
906 brw_SYNC(p, TGL_SYNC_BAR);
907 } else {
908 brw_WAIT(p);
909 }
910 }
911
912 bool
generate_linterp(fs_inst * inst,struct brw_reg dst,struct brw_reg * src)913 fs_generator::generate_linterp(fs_inst *inst,
914 struct brw_reg dst, struct brw_reg *src)
915 {
916 /* PLN reads:
917 * / in SIMD16 \
918 * -----------------------------------
919 * | src1+0 | src1+1 | src1+2 | src1+3 |
920 * |-----------------------------------|
921 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
922 * -----------------------------------
923 *
924 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
925 *
926 * -----------------------------------
927 * | src1+0 | src1+1 | src1+2 | src1+3 |
928 * |-----------------------------------|
929 * |(x0, x1)|(y0, y1)| | | in SIMD8
930 * |-----------------------------------|
931 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
932 * -----------------------------------
933 *
934 * See also: emit_interpolation_setup_gen4().
935 */
936 struct brw_reg delta_x = src[0];
937 struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
938 struct brw_reg interp = src[1];
939 brw_inst *i[2];
940
941 /* nir_lower_interpolation() will do the lowering to MAD instructions for
942 * us on gen11+
943 */
944 assert(devinfo->gen < 11);
945
946 if (devinfo->has_pln) {
947 if (devinfo->gen <= 6 && (delta_x.nr & 1) != 0) {
948 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
949 *
950 * "[DevSNB]:<src1> must be even register aligned.
951 *
952 * This restriction is lifted on Ivy Bridge.
953 *
954 * This means that we need to split PLN into LINE+MAC on-the-fly.
955 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
956 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
957 * coordinate registers are laid out differently so we leave it as a
958 * SIMD16 instruction.
959 */
960 assert(inst->exec_size == 8 || inst->exec_size == 16);
961 assert(inst->group % 16 == 0);
962
963 brw_push_insn_state(p);
964 brw_set_default_exec_size(p, BRW_EXECUTE_8);
965
966 /* Thanks to two accumulators, we can emit all the LINEs and then all
967 * the MACs. This improves parallelism a bit.
968 */
969 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
970 brw_inst *line = brw_LINE(p, brw_null_reg(), interp,
971 offset(delta_x, g * 2));
972 brw_inst_set_group(devinfo, line, inst->group + g * 8);
973
974 /* LINE writes the accumulator automatically on gen4-5. On Sandy
975 * Bridge and later, we have to explicitly enable it.
976 */
977 if (devinfo->gen >= 6)
978 brw_inst_set_acc_wr_control(p->devinfo, line, true);
979
980 /* brw_set_default_saturate() is called before emitting
981 * instructions, so the saturate bit is set in each instruction,
982 * so we need to unset it on the LINE instructions.
983 */
984 brw_inst_set_saturate(p->devinfo, line, false);
985 }
986
987 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
988 brw_inst *mac = brw_MAC(p, offset(dst, g), suboffset(interp, 1),
989 offset(delta_x, g * 2 + 1));
990 brw_inst_set_group(devinfo, mac, inst->group + g * 8);
991 brw_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod);
992 }
993
994 brw_pop_insn_state(p);
995
996 return true;
997 } else {
998 brw_PLN(p, dst, interp, delta_x);
999
1000 return false;
1001 }
1002 } else {
1003 i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
1004 i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1005
1006 brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
1007
1008 /* brw_set_default_saturate() is called before emitting instructions, so
1009 * the saturate bit is set in each instruction, so we need to unset it on
1010 * the first instruction.
1011 */
1012 brw_inst_set_saturate(p->devinfo, i[0], false);
1013
1014 return true;
1015 }
1016 }
1017
1018 void
generate_get_buffer_size(fs_inst * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg surf_index)1019 fs_generator::generate_get_buffer_size(fs_inst *inst,
1020 struct brw_reg dst,
1021 struct brw_reg src,
1022 struct brw_reg surf_index)
1023 {
1024 assert(devinfo->gen >= 7);
1025 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
1026
1027 uint32_t simd_mode;
1028 int rlen = 4;
1029
1030 switch (inst->exec_size) {
1031 case 8:
1032 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1033 break;
1034 case 16:
1035 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1036 break;
1037 default:
1038 unreachable("Invalid width for texture instruction");
1039 }
1040
1041 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
1042 rlen = 8;
1043 dst = vec16(dst);
1044 }
1045
1046 brw_SAMPLE(p,
1047 retype(dst, BRW_REGISTER_TYPE_UW),
1048 inst->base_mrf,
1049 src,
1050 surf_index.ud,
1051 0,
1052 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1053 rlen, /* response length */
1054 inst->mlen,
1055 inst->header_size > 0,
1056 simd_mode,
1057 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1058 }
1059
1060 void
generate_tex(fs_inst * inst,struct brw_reg dst,struct brw_reg surface_index,struct brw_reg sampler_index)1061 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
1062 struct brw_reg surface_index,
1063 struct brw_reg sampler_index)
1064 {
1065 assert(devinfo->gen < 7);
1066 assert(inst->size_written % REG_SIZE == 0);
1067 int msg_type = -1;
1068 uint32_t simd_mode;
1069 uint32_t return_format;
1070
1071 /* Sampler EOT message of less than the dispatch width would kill the
1072 * thread prematurely.
1073 */
1074 assert(!inst->eot || inst->exec_size == dispatch_width);
1075
1076 switch (dst.type) {
1077 case BRW_REGISTER_TYPE_D:
1078 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
1079 break;
1080 case BRW_REGISTER_TYPE_UD:
1081 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
1082 break;
1083 default:
1084 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1085 break;
1086 }
1087
1088 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
1089 * is set as part of the message descriptor. On gen4, the PRM seems to
1090 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
1091 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1092 * gone from the message descriptor entirely and you just get UINT32 all
1093 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
1094 * just stomp it to UINT32 all the time.
1095 */
1096 if (inst->opcode == SHADER_OPCODE_TXS)
1097 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
1098
1099 switch (inst->exec_size) {
1100 case 8:
1101 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1102 break;
1103 case 16:
1104 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1105 break;
1106 default:
1107 unreachable("Invalid width for texture instruction");
1108 }
1109
1110 if (devinfo->gen >= 5) {
1111 switch (inst->opcode) {
1112 case SHADER_OPCODE_TEX:
1113 if (inst->shadow_compare) {
1114 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
1115 } else {
1116 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
1117 }
1118 break;
1119 case FS_OPCODE_TXB:
1120 if (inst->shadow_compare) {
1121 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
1122 } else {
1123 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
1124 }
1125 break;
1126 case SHADER_OPCODE_TXL:
1127 if (inst->shadow_compare) {
1128 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
1129 } else {
1130 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
1131 }
1132 break;
1133 case SHADER_OPCODE_TXS:
1134 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
1135 break;
1136 case SHADER_OPCODE_TXD:
1137 assert(!inst->shadow_compare);
1138 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
1139 break;
1140 case SHADER_OPCODE_TXF:
1141 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1142 break;
1143 case SHADER_OPCODE_TXF_CMS:
1144 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1145 break;
1146 case SHADER_OPCODE_LOD:
1147 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
1148 break;
1149 case SHADER_OPCODE_TG4:
1150 assert(devinfo->gen == 6);
1151 assert(!inst->shadow_compare);
1152 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
1153 break;
1154 case SHADER_OPCODE_SAMPLEINFO:
1155 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
1156 break;
1157 default:
1158 unreachable("not reached");
1159 }
1160 } else {
1161 switch (inst->opcode) {
1162 case SHADER_OPCODE_TEX:
1163 /* Note that G45 and older determines shadow compare and dispatch width
1164 * from message length for most messages.
1165 */
1166 if (inst->exec_size == 8) {
1167 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
1168 if (inst->shadow_compare) {
1169 assert(inst->mlen == 6);
1170 } else {
1171 assert(inst->mlen <= 4);
1172 }
1173 } else {
1174 if (inst->shadow_compare) {
1175 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1176 assert(inst->mlen == 9);
1177 } else {
1178 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1179 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
1180 }
1181 }
1182 break;
1183 case FS_OPCODE_TXB:
1184 if (inst->shadow_compare) {
1185 assert(inst->exec_size == 8);
1186 assert(inst->mlen == 6);
1187 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
1188 } else {
1189 assert(inst->mlen == 9);
1190 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1191 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1192 }
1193 break;
1194 case SHADER_OPCODE_TXL:
1195 if (inst->shadow_compare) {
1196 assert(inst->exec_size == 8);
1197 assert(inst->mlen == 6);
1198 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
1199 } else {
1200 assert(inst->mlen == 9);
1201 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
1202 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1203 }
1204 break;
1205 case SHADER_OPCODE_TXD:
1206 /* There is no sample_d_c message; comparisons are done manually */
1207 assert(inst->exec_size == 8);
1208 assert(inst->mlen == 7 || inst->mlen == 10);
1209 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
1210 break;
1211 case SHADER_OPCODE_TXF:
1212 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
1213 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1214 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1215 break;
1216 case SHADER_OPCODE_TXS:
1217 assert(inst->mlen == 3);
1218 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
1219 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1220 break;
1221 default:
1222 unreachable("not reached");
1223 }
1224 }
1225 assert(msg_type != -1);
1226
1227 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
1228 dst = vec16(dst);
1229 }
1230
1231 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
1232
1233 /* Load the message header if present. If there's a texture offset,
1234 * we need to set it up explicitly and load the offset bitfield.
1235 * Otherwise, we can use an implied move from g0 to the first message reg.
1236 */
1237 struct brw_reg src = brw_null_reg();
1238 if (inst->header_size != 0) {
1239 if (devinfo->gen < 6 && !inst->offset) {
1240 /* Set up an implied move from g0 to the MRF. */
1241 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
1242 } else {
1243 const tgl_swsb swsb = brw_get_default_swsb(p);
1244 assert(inst->base_mrf != -1);
1245 struct brw_reg header_reg = brw_message_reg(inst->base_mrf);
1246
1247 brw_push_insn_state(p);
1248 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1249 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1250 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1251 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1252 /* Explicitly set up the message header by copying g0 to the MRF. */
1253 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
1254 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1255
1256 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1257 if (inst->offset) {
1258 /* Set the offset bits in DWord 2. */
1259 brw_MOV(p, get_element_ud(header_reg, 2),
1260 brw_imm_ud(inst->offset));
1261 }
1262
1263 brw_pop_insn_state(p);
1264 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1265 }
1266 }
1267
1268 uint32_t base_binding_table_index;
1269 switch (inst->opcode) {
1270 case SHADER_OPCODE_TG4:
1271 base_binding_table_index = prog_data->binding_table.gather_texture_start;
1272 break;
1273 default:
1274 base_binding_table_index = prog_data->binding_table.texture_start;
1275 break;
1276 }
1277
1278 assert(surface_index.file == BRW_IMMEDIATE_VALUE);
1279 assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
1280
1281 brw_SAMPLE(p,
1282 retype(dst, BRW_REGISTER_TYPE_UW),
1283 inst->base_mrf,
1284 src,
1285 surface_index.ud + base_binding_table_index,
1286 sampler_index.ud % 16,
1287 msg_type,
1288 inst->size_written / REG_SIZE,
1289 inst->mlen,
1290 inst->header_size != 0,
1291 simd_mode,
1292 return_format);
1293 }
1294
1295
1296 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1297 * looking like:
1298 *
1299 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1300 *
1301 * Ideally, we want to produce:
1302 *
1303 * DDX DDY
1304 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1305 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1306 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1307 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1308 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1309 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1310 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1311 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1312 *
1313 * and add another set of two more subspans if in 16-pixel dispatch mode.
1314 *
1315 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1316 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1317 * pair. But the ideal approximation may impose a huge performance cost on
1318 * sample_d. On at least Haswell, sample_d instruction does some
1319 * optimizations if the same LOD is used for all pixels in the subspan.
1320 *
1321 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1322 * appropriate swizzling.
1323 */
1324 void
generate_ddx(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)1325 fs_generator::generate_ddx(const fs_inst *inst,
1326 struct brw_reg dst, struct brw_reg src)
1327 {
1328 unsigned vstride, width;
1329
1330 if (devinfo->gen >= 8) {
1331 if (inst->opcode == FS_OPCODE_DDX_FINE) {
1332 /* produce accurate derivatives */
1333 vstride = BRW_VERTICAL_STRIDE_2;
1334 width = BRW_WIDTH_2;
1335 } else {
1336 /* replicate the derivative at the top-left pixel to other pixels */
1337 vstride = BRW_VERTICAL_STRIDE_4;
1338 width = BRW_WIDTH_4;
1339 }
1340
1341 struct brw_reg src0 = byte_offset(src, type_sz(src.type));;
1342 struct brw_reg src1 = src;
1343
1344 src0.vstride = vstride;
1345 src0.width = width;
1346 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1347 src1.vstride = vstride;
1348 src1.width = width;
1349 src1.hstride = BRW_HORIZONTAL_STRIDE_0;
1350
1351 brw_ADD(p, dst, src0, negate(src1));
1352 } else {
1353 /* On Haswell and earlier, the region used above appears to not work
1354 * correctly for compressed instructions. At least on Haswell and
1355 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1356 * would have to split to SIMD8 no matter which method we choose, we
1357 * may as well use ALIGN16 on all platforms gen7 and earlier.
1358 */
1359 struct brw_reg src0 = stride(src, 4, 4, 1);
1360 struct brw_reg src1 = stride(src, 4, 4, 1);
1361 if (inst->opcode == FS_OPCODE_DDX_FINE) {
1362 src0.swizzle = BRW_SWIZZLE_XXZZ;
1363 src1.swizzle = BRW_SWIZZLE_YYWW;
1364 } else {
1365 src0.swizzle = BRW_SWIZZLE_XXXX;
1366 src1.swizzle = BRW_SWIZZLE_YYYY;
1367 }
1368
1369 brw_push_insn_state(p);
1370 brw_set_default_access_mode(p, BRW_ALIGN_16);
1371 brw_ADD(p, dst, negate(src0), src1);
1372 brw_pop_insn_state(p);
1373 }
1374 }
1375
1376 /* The negate_value boolean is used to negate the derivative computation for
1377 * FBOs, since they place the origin at the upper left instead of the lower
1378 * left.
1379 */
1380 void
generate_ddy(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)1381 fs_generator::generate_ddy(const fs_inst *inst,
1382 struct brw_reg dst, struct brw_reg src)
1383 {
1384 const uint32_t type_size = type_sz(src.type);
1385
1386 if (inst->opcode == FS_OPCODE_DDY_FINE) {
1387 /* produce accurate derivatives.
1388 *
1389 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1390 * "Register Region Restrictions", Section "1. Special Restrictions":
1391 *
1392 * "In Align16 mode, the channel selects and channel enables apply to
1393 * a pair of half-floats, because these parameters are defined for
1394 * DWord elements ONLY. This is applicable when both source and
1395 * destination are half-floats."
1396 *
1397 * So for half-float operations we use the Gen11+ Align1 path. CHV
1398 * inherits its FP16 hardware from SKL, so it is not affected.
1399 */
1400 if (devinfo->gen >= 11 ||
1401 (devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) {
1402 src = stride(src, 0, 2, 1);
1403
1404 brw_push_insn_state(p);
1405 brw_set_default_exec_size(p, BRW_EXECUTE_4);
1406 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
1407 brw_set_default_group(p, inst->group + g);
1408 brw_ADD(p, byte_offset(dst, g * type_size),
1409 negate(byte_offset(src, g * type_size)),
1410 byte_offset(src, (g + 2) * type_size));
1411 brw_set_default_swsb(p, tgl_swsb_null());
1412 }
1413 brw_pop_insn_state(p);
1414 } else {
1415 struct brw_reg src0 = stride(src, 4, 4, 1);
1416 struct brw_reg src1 = stride(src, 4, 4, 1);
1417 src0.swizzle = BRW_SWIZZLE_XYXY;
1418 src1.swizzle = BRW_SWIZZLE_ZWZW;
1419
1420 brw_push_insn_state(p);
1421 brw_set_default_access_mode(p, BRW_ALIGN_16);
1422 brw_ADD(p, dst, negate(src0), src1);
1423 brw_pop_insn_state(p);
1424 }
1425 } else {
1426 /* replicate the derivative at the top-left pixel to other pixels */
1427 if (devinfo->gen >= 8) {
1428 struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
1429 struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
1430
1431 brw_ADD(p, dst, negate(src0), src1);
1432 } else {
1433 /* On Haswell and earlier, the region used above appears to not work
1434 * correctly for compressed instructions. At least on Haswell and
1435 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1436 * would have to split to SIMD8 no matter which method we choose, we
1437 * may as well use ALIGN16 on all platforms gen7 and earlier.
1438 */
1439 struct brw_reg src0 = stride(src, 4, 4, 1);
1440 struct brw_reg src1 = stride(src, 4, 4, 1);
1441 src0.swizzle = BRW_SWIZZLE_XXXX;
1442 src1.swizzle = BRW_SWIZZLE_ZZZZ;
1443
1444 brw_push_insn_state(p);
1445 brw_set_default_access_mode(p, BRW_ALIGN_16);
1446 brw_ADD(p, dst, negate(src0), src1);
1447 brw_pop_insn_state(p);
1448 }
1449 }
1450 }
1451
1452 void
generate_discard_jump(fs_inst *)1453 fs_generator::generate_discard_jump(fs_inst *)
1454 {
1455 /* This HALT will be patched up at FB write time to point UIP at the end of
1456 * the program, and at brw_uip_jip() JIP will be set to the end of the
1457 * current block (or the program).
1458 */
1459 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1460 brw_HALT(p);
1461 }
1462
1463 void
generate_scratch_write(fs_inst * inst,struct brw_reg src)1464 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1465 {
1466 /* The 32-wide messages only respect the first 16-wide half of the channel
1467 * enable signals which are replicated identically for the second group of
1468 * 16 channels, so we cannot use them unless the write is marked
1469 * force_writemask_all.
1470 */
1471 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1472 MIN2(16, inst->exec_size);
1473 const unsigned block_size = 4 * lower_size / REG_SIZE;
1474 const tgl_swsb swsb = brw_get_default_swsb(p);
1475 assert(inst->mlen != 0);
1476
1477 brw_push_insn_state(p);
1478 brw_set_default_exec_size(p, cvt(lower_size) - 1);
1479 brw_set_default_compression(p, lower_size > 8);
1480
1481 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1482 brw_set_default_group(p, inst->group + lower_size * i);
1483
1484 if (i > 0) {
1485 assert(swsb.mode & TGL_SBID_SET);
1486 brw_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid));
1487 } else {
1488 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1489 }
1490
1491 brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1492 retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
1493
1494 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1495 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1496 block_size,
1497 inst->offset + block_size * REG_SIZE * i);
1498 }
1499
1500 brw_pop_insn_state(p);
1501 }
1502
1503 void
generate_scratch_read(fs_inst * inst,struct brw_reg dst)1504 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1505 {
1506 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1507 assert(inst->mlen != 0);
1508
1509 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1510 inst->exec_size / 8, inst->offset);
1511 }
1512
1513 void
generate_scratch_read_gen7(fs_inst * inst,struct brw_reg dst)1514 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1515 {
1516 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1517
1518 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1519 }
1520
1521 /* The A32 messages take a buffer base address in header.5:[31:0] (See
1522 * MH1_A32_PSM for typed messages or MH_A32_GO for byte/dword scattered
1523 * and OWord block messages in the SKL PRM Vol. 2d for more details.)
1524 * Unfortunately, there are a number of subtle differences:
1525 *
1526 * For the block read/write messages:
1527 *
1528 * - We always stomp header.2 to fill in the actual scratch address (in
1529 * units of OWORDs) so we don't care what's in there.
1530 *
1531 * - They rely on per-thread scratch space value in header.3[3:0] to do
1532 * bounds checking so that needs to be valid. The upper bits of
1533 * header.3 are ignored, though, so we can copy all of g0.3.
1534 *
1535 * - They ignore header.5[9:0] and assumes the address is 1KB aligned.
1536 *
1537 *
1538 * For the byte/dword scattered read/write messages:
1539 *
1540 * - We want header.2 to be zero because that gets added to the per-channel
1541 * offset in the non-header portion of the message.
1542 *
1543 * - Contrary to what the docs claim, they don't do any bounds checking so
1544 * the value of header.3[3:0] doesn't matter.
1545 *
1546 * - They consider all of header.5 for the base address and header.5[9:0]
1547 * are not ignored. This means that we can't copy g0.5 verbatim because
1548 * g0.5[9:0] contains the FFTID on most platforms. Instead, we have to
1549 * use an AND to mask off the bottom 10 bits.
1550 *
1551 *
1552 * For block messages, just copying g0 gives a valid header because all the
1553 * garbage gets ignored except for header.2 which we stomp as part of message
1554 * setup. For byte/dword scattered messages, we can just zero out the header
1555 * and copy over the bits we need from g0.5. This opcode, however, tries to
1556 * satisfy the requirements of both by starting with 0 and filling out the
1557 * information required by either set of opcodes.
1558 */
1559 void
generate_scratch_header(fs_inst * inst,struct brw_reg dst)1560 fs_generator::generate_scratch_header(fs_inst *inst, struct brw_reg dst)
1561 {
1562 assert(inst->exec_size == 8 && inst->force_writemask_all);
1563 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
1564
1565 dst.type = BRW_REGISTER_TYPE_UD;
1566
1567 brw_inst *insn = brw_MOV(p, dst, brw_imm_ud(0));
1568 if (devinfo->gen >= 12)
1569 brw_set_default_swsb(p, tgl_swsb_null());
1570 else
1571 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1572
1573 /* Copy the per-thread scratch space size from g0.3[3:0] */
1574 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1575 insn = brw_AND(p, suboffset(dst, 3),
1576 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
1577 brw_imm_ud(INTEL_MASK(3, 0)));
1578 if (devinfo->gen < 12) {
1579 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1580 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1581 }
1582
1583 /* Copy the scratch base address from g0.5[31:10] */
1584 insn = brw_AND(p, suboffset(dst, 5),
1585 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
1586 brw_imm_ud(INTEL_MASK(31, 10)));
1587 if (devinfo->gen < 12)
1588 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1589 }
1590
1591 void
generate_uniform_pull_constant_load(fs_inst * inst,struct brw_reg dst,struct brw_reg index,struct brw_reg offset)1592 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1593 struct brw_reg dst,
1594 struct brw_reg index,
1595 struct brw_reg offset)
1596 {
1597 assert(type_sz(dst.type) == 4);
1598 assert(inst->mlen != 0);
1599
1600 assert(index.file == BRW_IMMEDIATE_VALUE &&
1601 index.type == BRW_REGISTER_TYPE_UD);
1602 uint32_t surf_index = index.ud;
1603
1604 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1605 offset.type == BRW_REGISTER_TYPE_UD);
1606 uint32_t read_offset = offset.ud;
1607
1608 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1609 read_offset, surf_index);
1610 }
1611
1612 void
generate_uniform_pull_constant_load_gen7(fs_inst * inst,struct brw_reg dst,struct brw_reg index,struct brw_reg payload)1613 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1614 struct brw_reg dst,
1615 struct brw_reg index,
1616 struct brw_reg payload)
1617 {
1618 assert(index.type == BRW_REGISTER_TYPE_UD);
1619 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1620 assert(type_sz(dst.type) == 4);
1621
1622 if (index.file == BRW_IMMEDIATE_VALUE) {
1623 const uint32_t surf_index = index.ud;
1624
1625 brw_push_insn_state(p);
1626 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1627 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1628 brw_pop_insn_state(p);
1629
1630 brw_inst_set_sfid(devinfo, send, GEN6_SFID_DATAPORT_CONSTANT_CACHE);
1631 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
1632 brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
1633 brw_set_desc(p, send,
1634 brw_message_desc(devinfo, 1, DIV_ROUND_UP(inst->size_written,
1635 REG_SIZE), true) |
1636 brw_dp_read_desc(devinfo, surf_index,
1637 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1638 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1639 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1640
1641 } else {
1642 const tgl_swsb swsb = brw_get_default_swsb(p);
1643 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1644
1645 brw_push_insn_state(p);
1646 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1647
1648 /* a0.0 = surf_index & 0xff */
1649 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1650 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1651 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1652 brw_set_dest(p, insn_and, addr);
1653 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1654 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1655
1656 /* dst = send(payload, a0.0 | <descriptor>) */
1657 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1658 brw_send_indirect_message(
1659 p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
1660 retype(dst, BRW_REGISTER_TYPE_UD),
1661 retype(payload, BRW_REGISTER_TYPE_UD), addr,
1662 brw_message_desc(devinfo, 1,
1663 DIV_ROUND_UP(inst->size_written, REG_SIZE), true) |
1664 brw_dp_read_desc(devinfo, 0 /* surface */,
1665 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1666 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1667 BRW_DATAPORT_READ_TARGET_DATA_CACHE),
1668 false /* EOT */);
1669
1670 brw_pop_insn_state(p);
1671 }
1672 }
1673
1674 void
generate_varying_pull_constant_load_gen4(fs_inst * inst,struct brw_reg dst,struct brw_reg index)1675 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1676 struct brw_reg dst,
1677 struct brw_reg index)
1678 {
1679 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1680 assert(inst->header_size != 0);
1681 assert(inst->mlen);
1682
1683 assert(index.file == BRW_IMMEDIATE_VALUE &&
1684 index.type == BRW_REGISTER_TYPE_UD);
1685 uint32_t surf_index = index.ud;
1686
1687 uint32_t simd_mode, rlen, msg_type;
1688 if (inst->exec_size == 16) {
1689 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1690 rlen = 8;
1691 } else {
1692 assert(inst->exec_size == 8);
1693 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1694 rlen = 4;
1695 }
1696
1697 if (devinfo->gen >= 5)
1698 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1699 else {
1700 /* We always use the SIMD16 message so that we only have to load U, and
1701 * not V or R.
1702 */
1703 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1704 assert(inst->mlen == 3);
1705 assert(inst->size_written == 8 * REG_SIZE);
1706 rlen = 8;
1707 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1708 }
1709
1710 struct brw_reg header = brw_vec8_grf(0, 0);
1711 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1712
1713 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1714 brw_inst_set_compression(devinfo, send, false);
1715 brw_inst_set_sfid(devinfo, send, BRW_SFID_SAMPLER);
1716 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1717 brw_set_src0(p, send, header);
1718 if (devinfo->gen < 6)
1719 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1720
1721 /* Our surface is set up as floats, regardless of what actual data is
1722 * stored in it.
1723 */
1724 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1725 brw_set_desc(p, send,
1726 brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size) |
1727 brw_sampler_desc(devinfo, surf_index,
1728 0, /* sampler (unused) */
1729 msg_type, simd_mode, return_format));
1730 }
1731
1732 void
generate_pixel_interpolator_query(fs_inst * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg msg_data,unsigned msg_type)1733 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1734 struct brw_reg dst,
1735 struct brw_reg src,
1736 struct brw_reg msg_data,
1737 unsigned msg_type)
1738 {
1739 const bool has_payload = inst->src[0].file != BAD_FILE;
1740 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1741 assert(inst->size_written % REG_SIZE == 0);
1742
1743 brw_pixel_interpolator_query(p,
1744 retype(dst, BRW_REGISTER_TYPE_UW),
1745 /* If we don't have a payload, what we send doesn't matter */
1746 has_payload ? src : brw_vec8_grf(0, 0),
1747 inst->pi_noperspective,
1748 msg_type,
1749 msg_data,
1750 has_payload ? 2 * inst->exec_size / 8 : 1,
1751 inst->size_written / REG_SIZE);
1752 }
1753
1754 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1755 * the ADD instruction.
1756 */
1757 void
generate_set_sample_id(fs_inst * inst,struct brw_reg dst,struct brw_reg src0,struct brw_reg src1)1758 fs_generator::generate_set_sample_id(fs_inst *inst,
1759 struct brw_reg dst,
1760 struct brw_reg src0,
1761 struct brw_reg src1)
1762 {
1763 assert(dst.type == BRW_REGISTER_TYPE_D ||
1764 dst.type == BRW_REGISTER_TYPE_UD);
1765 assert(src0.type == BRW_REGISTER_TYPE_D ||
1766 src0.type == BRW_REGISTER_TYPE_UD);
1767
1768 const struct brw_reg reg = stride(src1, 1, 4, 0);
1769 const unsigned lower_size = MIN2(inst->exec_size,
1770 devinfo->gen >= 8 ? 16 : 8);
1771
1772 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1773 brw_inst *insn = brw_ADD(p, offset(dst, i * lower_size / 8),
1774 offset(src0, (src0.vstride == 0 ? 0 : (1 << (src0.vstride - 1)) *
1775 (i * lower_size / (1 << src0.width))) *
1776 type_sz(src0.type) / REG_SIZE),
1777 suboffset(reg, i * lower_size / 4));
1778 brw_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1);
1779 brw_inst_set_group(devinfo, insn, inst->group + lower_size * i);
1780 brw_inst_set_compression(devinfo, insn, lower_size > 8);
1781 brw_set_default_swsb(p, tgl_swsb_null());
1782 }
1783 }
1784
1785 void
generate_pack_half_2x16_split(fs_inst *,struct brw_reg dst,struct brw_reg x,struct brw_reg y)1786 fs_generator::generate_pack_half_2x16_split(fs_inst *,
1787 struct brw_reg dst,
1788 struct brw_reg x,
1789 struct brw_reg y)
1790 {
1791 assert(devinfo->gen >= 7);
1792 assert(dst.type == BRW_REGISTER_TYPE_UD);
1793 assert(x.type == BRW_REGISTER_TYPE_F);
1794 assert(y.type == BRW_REGISTER_TYPE_F);
1795
1796 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1797 *
1798 * Because this instruction does not have a 16-bit floating-point type,
1799 * the destination data type must be Word (W).
1800 *
1801 * The destination must be DWord-aligned and specify a horizontal stride
1802 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1803 * each destination channel and the upper word is not modified.
1804 */
1805 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1806
1807 /* Give each 32-bit channel of dst the form below, where "." means
1808 * unchanged.
1809 * 0x....hhhh
1810 */
1811 brw_F32TO16(p, dst_w, y);
1812
1813 /* Now the form:
1814 * 0xhhhh0000
1815 */
1816 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1817 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1818
1819 /* And, finally the form of packHalf2x16's output:
1820 * 0xhhhhllll
1821 */
1822 brw_F32TO16(p, dst_w, x);
1823 }
1824
1825 void
generate_shader_time_add(fs_inst *,struct brw_reg payload,struct brw_reg offset,struct brw_reg value)1826 fs_generator::generate_shader_time_add(fs_inst *,
1827 struct brw_reg payload,
1828 struct brw_reg offset,
1829 struct brw_reg value)
1830 {
1831 const tgl_swsb swsb = brw_get_default_swsb(p);
1832
1833 assert(devinfo->gen >= 7);
1834 brw_push_insn_state(p);
1835 brw_set_default_mask_control(p, true);
1836 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1837
1838 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1839 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1840 offset.type);
1841 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1842 value.type);
1843
1844 assert(offset.file == BRW_IMMEDIATE_VALUE);
1845 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1846 value.width = BRW_WIDTH_1;
1847 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1848 value.vstride = BRW_VERTICAL_STRIDE_0;
1849 } else {
1850 assert(value.file == BRW_IMMEDIATE_VALUE);
1851 }
1852
1853 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1854 * case, and we don't really care about squeezing every bit of performance
1855 * out of this path, so we just emit the MOVs from here.
1856 */
1857 brw_MOV(p, payload_offset, offset);
1858 brw_set_default_swsb(p, tgl_swsb_null());
1859 brw_MOV(p, payload_value, value);
1860 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1861 brw_shader_time_add(p, payload,
1862 prog_data->binding_table.shader_time_start);
1863 brw_pop_insn_state(p);
1864 }
1865
1866 void
enable_debug(const char * shader_name)1867 fs_generator::enable_debug(const char *shader_name)
1868 {
1869 debug_flag = true;
1870 this->shader_name = shader_name;
1871 }
1872
1873 int
generate_code(const cfg_t * cfg,int dispatch_width,struct shader_stats shader_stats,const brw::performance & perf,struct brw_compile_stats * stats)1874 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
1875 struct shader_stats shader_stats,
1876 const brw::performance &perf,
1877 struct brw_compile_stats *stats)
1878 {
1879 /* align to 64 byte boundary. */
1880 brw_realign(p, 64);
1881
1882 this->dispatch_width = dispatch_width;
1883
1884 int start_offset = p->next_insn_offset;
1885
1886 /* `send_count` explicitly does not include spills or fills, as we'd
1887 * like to use it as a metric for intentional memory access or other
1888 * shared function use. Otherwise, subtle changes to scheduling or
1889 * register allocation could cause it to fluctuate wildly - and that
1890 * effect is already counted in spill/fill counts.
1891 */
1892 int spill_count = 0, fill_count = 0;
1893 int loop_count = 0, send_count = 0, nop_count = 0;
1894 bool is_accum_used = false;
1895
1896 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1897
1898 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1899 if (inst->opcode == SHADER_OPCODE_UNDEF)
1900 continue;
1901
1902 struct brw_reg src[4], dst;
1903 unsigned int last_insn_offset = p->next_insn_offset;
1904 bool multiple_instructions_emitted = false;
1905
1906 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1907 * "Register Region Restrictions" section: for BDW, SKL:
1908 *
1909 * "A POW/FDIV operation must not be followed by an instruction
1910 * that requires two destination registers."
1911 *
1912 * The documentation is often lacking annotations for Atom parts,
1913 * and empirically this affects CHV as well.
1914 */
1915 if (devinfo->gen >= 8 &&
1916 devinfo->gen <= 9 &&
1917 p->nr_insn > 1 &&
1918 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1919 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1920 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1921 brw_NOP(p);
1922 last_insn_offset = p->next_insn_offset;
1923
1924 /* In order to avoid spurious instruction count differences when the
1925 * instruction schedule changes, keep track of the number of inserted
1926 * NOPs.
1927 */
1928 nop_count++;
1929 }
1930
1931 /* GEN:BUG:14010017096:
1932 *
1933 * Clear accumulator register before end of thread.
1934 */
1935 if (inst->eot && is_accum_used && devinfo->gen >= 12) {
1936 brw_set_default_exec_size(p, BRW_EXECUTE_16);
1937 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1938 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1939 brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
1940 last_insn_offset = p->next_insn_offset;
1941 }
1942
1943 if (!is_accum_used && !inst->eot) {
1944 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
1945 inst->dst.is_accumulator();
1946 }
1947
1948 if (unlikely(debug_flag))
1949 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1950
1951 /* If the instruction writes to more than one register, it needs to be
1952 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1953 * hardware figures out by itself what the right compression mode is,
1954 * but we still need to know whether the instruction is compressed to
1955 * set up the source register regions appropriately.
1956 *
1957 * XXX - This is wrong for instructions that write a single register but
1958 * read more than one which should strictly speaking be treated as
1959 * compressed. For instructions that don't write any registers it
1960 * relies on the destination being a null register of the correct
1961 * type and regioning so the instruction is considered compressed
1962 * or not accordingly.
1963 */
1964 const bool compressed =
1965 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1966 brw_set_default_compression(p, compressed);
1967 brw_set_default_group(p, inst->group);
1968
1969 for (unsigned int i = 0; i < inst->sources; i++) {
1970 src[i] = brw_reg_from_fs_reg(devinfo, inst,
1971 &inst->src[i], compressed);
1972 /* The accumulator result appears to get used for the
1973 * conditional modifier generation. When negating a UD
1974 * value, there is a 33rd bit generated for the sign in the
1975 * accumulator value, so now you can't check, for example,
1976 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1977 */
1978 assert(!inst->conditional_mod ||
1979 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1980 !inst->src[i].negate);
1981 }
1982 dst = brw_reg_from_fs_reg(devinfo, inst,
1983 &inst->dst, compressed);
1984
1985 brw_set_default_access_mode(p, BRW_ALIGN_1);
1986 brw_set_default_predicate_control(p, inst->predicate);
1987 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1988 /* On gen7 and above, hardware automatically adds the group onto the
1989 * flag subregister number. On Sandy Bridge and older, we have to do it
1990 * ourselves.
1991 */
1992 const unsigned flag_subreg = inst->flag_subreg +
1993 (devinfo->gen >= 7 ? 0 : inst->group / 16);
1994 brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
1995 brw_set_default_saturate(p, inst->saturate);
1996 brw_set_default_mask_control(p, inst->force_writemask_all);
1997 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1998 brw_set_default_swsb(p, inst->sched);
1999
2000 unsigned exec_size = inst->exec_size;
2001 if (devinfo->gen == 7 && !devinfo->is_haswell &&
2002 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
2003 exec_size *= 2;
2004 }
2005
2006 brw_set_default_exec_size(p, cvt(exec_size) - 1);
2007
2008 assert(inst->force_writemask_all || inst->exec_size >= 4);
2009 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
2010 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
2011 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
2012
2013 switch (inst->opcode) {
2014 case BRW_OPCODE_SYNC:
2015 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2016 brw_SYNC(p, tgl_sync_function(src[0].ud));
2017 break;
2018 case BRW_OPCODE_MOV:
2019 brw_MOV(p, dst, src[0]);
2020 break;
2021 case BRW_OPCODE_ADD:
2022 brw_ADD(p, dst, src[0], src[1]);
2023 break;
2024 case BRW_OPCODE_MUL:
2025 brw_MUL(p, dst, src[0], src[1]);
2026 break;
2027 case BRW_OPCODE_AVG:
2028 brw_AVG(p, dst, src[0], src[1]);
2029 break;
2030 case BRW_OPCODE_MACH:
2031 brw_MACH(p, dst, src[0], src[1]);
2032 break;
2033
2034 case BRW_OPCODE_LINE:
2035 brw_LINE(p, dst, src[0], src[1]);
2036 break;
2037
2038 case BRW_OPCODE_MAD:
2039 assert(devinfo->gen >= 6);
2040 if (devinfo->gen < 10)
2041 brw_set_default_access_mode(p, BRW_ALIGN_16);
2042 brw_MAD(p, dst, src[0], src[1], src[2]);
2043 break;
2044
2045 case BRW_OPCODE_LRP:
2046 assert(devinfo->gen >= 6 && devinfo->gen <= 10);
2047 if (devinfo->gen < 10)
2048 brw_set_default_access_mode(p, BRW_ALIGN_16);
2049 brw_LRP(p, dst, src[0], src[1], src[2]);
2050 break;
2051
2052 case BRW_OPCODE_FRC:
2053 brw_FRC(p, dst, src[0]);
2054 break;
2055 case BRW_OPCODE_RNDD:
2056 brw_RNDD(p, dst, src[0]);
2057 break;
2058 case BRW_OPCODE_RNDE:
2059 brw_RNDE(p, dst, src[0]);
2060 break;
2061 case BRW_OPCODE_RNDZ:
2062 brw_RNDZ(p, dst, src[0]);
2063 break;
2064
2065 case BRW_OPCODE_AND:
2066 brw_AND(p, dst, src[0], src[1]);
2067 break;
2068 case BRW_OPCODE_OR:
2069 brw_OR(p, dst, src[0], src[1]);
2070 break;
2071 case BRW_OPCODE_XOR:
2072 brw_XOR(p, dst, src[0], src[1]);
2073 break;
2074 case BRW_OPCODE_NOT:
2075 brw_NOT(p, dst, src[0]);
2076 break;
2077 case BRW_OPCODE_ASR:
2078 brw_ASR(p, dst, src[0], src[1]);
2079 break;
2080 case BRW_OPCODE_SHR:
2081 brw_SHR(p, dst, src[0], src[1]);
2082 break;
2083 case BRW_OPCODE_SHL:
2084 brw_SHL(p, dst, src[0], src[1]);
2085 break;
2086 case BRW_OPCODE_ROL:
2087 assert(devinfo->gen >= 11);
2088 assert(src[0].type == dst.type);
2089 brw_ROL(p, dst, src[0], src[1]);
2090 break;
2091 case BRW_OPCODE_ROR:
2092 assert(devinfo->gen >= 11);
2093 assert(src[0].type == dst.type);
2094 brw_ROR(p, dst, src[0], src[1]);
2095 break;
2096 case BRW_OPCODE_F32TO16:
2097 assert(devinfo->gen >= 7);
2098 brw_F32TO16(p, dst, src[0]);
2099 break;
2100 case BRW_OPCODE_F16TO32:
2101 assert(devinfo->gen >= 7);
2102 brw_F16TO32(p, dst, src[0]);
2103 break;
2104 case BRW_OPCODE_CMP:
2105 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
2106 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
2107 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
2108 * implemented in the compiler is not sufficient. Overriding the
2109 * type when the destination is the null register is necessary but
2110 * not sufficient by itself.
2111 */
2112 assert(dst.nr == BRW_ARF_NULL);
2113 dst.type = BRW_REGISTER_TYPE_D;
2114 }
2115 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
2116 break;
2117 case BRW_OPCODE_SEL:
2118 brw_SEL(p, dst, src[0], src[1]);
2119 break;
2120 case BRW_OPCODE_CSEL:
2121 assert(devinfo->gen >= 8);
2122 if (devinfo->gen < 10)
2123 brw_set_default_access_mode(p, BRW_ALIGN_16);
2124 brw_CSEL(p, dst, src[0], src[1], src[2]);
2125 break;
2126 case BRW_OPCODE_BFREV:
2127 assert(devinfo->gen >= 7);
2128 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
2129 retype(src[0], BRW_REGISTER_TYPE_UD));
2130 break;
2131 case BRW_OPCODE_FBH:
2132 assert(devinfo->gen >= 7);
2133 brw_FBH(p, retype(dst, src[0].type), src[0]);
2134 break;
2135 case BRW_OPCODE_FBL:
2136 assert(devinfo->gen >= 7);
2137 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
2138 retype(src[0], BRW_REGISTER_TYPE_UD));
2139 break;
2140 case BRW_OPCODE_LZD:
2141 brw_LZD(p, dst, src[0]);
2142 break;
2143 case BRW_OPCODE_CBIT:
2144 assert(devinfo->gen >= 7);
2145 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
2146 retype(src[0], BRW_REGISTER_TYPE_UD));
2147 break;
2148 case BRW_OPCODE_ADDC:
2149 assert(devinfo->gen >= 7);
2150 brw_ADDC(p, dst, src[0], src[1]);
2151 break;
2152 case BRW_OPCODE_SUBB:
2153 assert(devinfo->gen >= 7);
2154 brw_SUBB(p, dst, src[0], src[1]);
2155 break;
2156 case BRW_OPCODE_MAC:
2157 brw_MAC(p, dst, src[0], src[1]);
2158 break;
2159
2160 case BRW_OPCODE_BFE:
2161 assert(devinfo->gen >= 7);
2162 if (devinfo->gen < 10)
2163 brw_set_default_access_mode(p, BRW_ALIGN_16);
2164 brw_BFE(p, dst, src[0], src[1], src[2]);
2165 break;
2166
2167 case BRW_OPCODE_BFI1:
2168 assert(devinfo->gen >= 7);
2169 brw_BFI1(p, dst, src[0], src[1]);
2170 break;
2171 case BRW_OPCODE_BFI2:
2172 assert(devinfo->gen >= 7);
2173 if (devinfo->gen < 10)
2174 brw_set_default_access_mode(p, BRW_ALIGN_16);
2175 brw_BFI2(p, dst, src[0], src[1], src[2]);
2176 break;
2177
2178 case BRW_OPCODE_IF:
2179 if (inst->src[0].file != BAD_FILE) {
2180 /* The instruction has an embedded compare (only allowed on gen6) */
2181 assert(devinfo->gen == 6);
2182 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
2183 } else {
2184 brw_IF(p, brw_get_default_exec_size(p));
2185 }
2186 break;
2187
2188 case BRW_OPCODE_ELSE:
2189 brw_ELSE(p);
2190 break;
2191 case BRW_OPCODE_ENDIF:
2192 brw_ENDIF(p);
2193 break;
2194
2195 case BRW_OPCODE_DO:
2196 brw_DO(p, brw_get_default_exec_size(p));
2197 break;
2198
2199 case BRW_OPCODE_BREAK:
2200 brw_BREAK(p);
2201 break;
2202 case BRW_OPCODE_CONTINUE:
2203 brw_CONT(p);
2204 break;
2205
2206 case BRW_OPCODE_WHILE:
2207 brw_WHILE(p);
2208 loop_count++;
2209 break;
2210
2211 case SHADER_OPCODE_RCP:
2212 case SHADER_OPCODE_RSQ:
2213 case SHADER_OPCODE_SQRT:
2214 case SHADER_OPCODE_EXP2:
2215 case SHADER_OPCODE_LOG2:
2216 case SHADER_OPCODE_SIN:
2217 case SHADER_OPCODE_COS:
2218 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2219 if (devinfo->gen >= 6) {
2220 assert(inst->mlen == 0);
2221 assert(devinfo->gen >= 7 || inst->exec_size == 8);
2222 gen6_math(p, dst, brw_math_function(inst->opcode),
2223 src[0], brw_null_reg());
2224 } else {
2225 assert(inst->mlen >= 1);
2226 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
2227 gen4_math(p, dst,
2228 brw_math_function(inst->opcode),
2229 inst->base_mrf, src[0],
2230 BRW_MATH_PRECISION_FULL);
2231 send_count++;
2232 }
2233 break;
2234 case SHADER_OPCODE_INT_QUOTIENT:
2235 case SHADER_OPCODE_INT_REMAINDER:
2236 case SHADER_OPCODE_POW:
2237 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2238 if (devinfo->gen >= 6) {
2239 assert(inst->mlen == 0);
2240 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
2241 inst->exec_size == 8);
2242 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2243 } else {
2244 assert(inst->mlen >= 1);
2245 assert(inst->exec_size == 8);
2246 gen4_math(p, dst, brw_math_function(inst->opcode),
2247 inst->base_mrf, src[0],
2248 BRW_MATH_PRECISION_FULL);
2249 send_count++;
2250 }
2251 break;
2252 case FS_OPCODE_LINTERP:
2253 multiple_instructions_emitted = generate_linterp(inst, dst, src);
2254 break;
2255 case FS_OPCODE_PIXEL_X:
2256 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2257 src[0].subnr = 0 * type_sz(src[0].type);
2258 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2259 break;
2260 case FS_OPCODE_PIXEL_Y:
2261 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2262 src[0].subnr = 4 * type_sz(src[0].type);
2263 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2264 break;
2265
2266 case SHADER_OPCODE_SEND:
2267 generate_send(inst, dst, src[0], src[1], src[2],
2268 inst->ex_mlen > 0 ? src[3] : brw_null_reg());
2269 if ((inst->desc & 0xff) == BRW_BTI_STATELESS ||
2270 (inst->desc & 0xff) == GEN8_BTI_STATELESS_NON_COHERENT) {
2271 if (inst->size_written)
2272 fill_count++;
2273 else
2274 spill_count++;
2275 } else {
2276 send_count++;
2277 }
2278 break;
2279
2280 case SHADER_OPCODE_GET_BUFFER_SIZE:
2281 generate_get_buffer_size(inst, dst, src[0], src[1]);
2282 send_count++;
2283 break;
2284 case SHADER_OPCODE_TEX:
2285 case FS_OPCODE_TXB:
2286 case SHADER_OPCODE_TXD:
2287 case SHADER_OPCODE_TXF:
2288 case SHADER_OPCODE_TXF_CMS:
2289 case SHADER_OPCODE_TXL:
2290 case SHADER_OPCODE_TXS:
2291 case SHADER_OPCODE_LOD:
2292 case SHADER_OPCODE_TG4:
2293 case SHADER_OPCODE_SAMPLEINFO:
2294 assert(inst->src[0].file == BAD_FILE);
2295 generate_tex(inst, dst, src[1], src[2]);
2296 send_count++;
2297 break;
2298
2299 case FS_OPCODE_DDX_COARSE:
2300 case FS_OPCODE_DDX_FINE:
2301 generate_ddx(inst, dst, src[0]);
2302 break;
2303 case FS_OPCODE_DDY_COARSE:
2304 case FS_OPCODE_DDY_FINE:
2305 generate_ddy(inst, dst, src[0]);
2306 break;
2307
2308 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2309 generate_scratch_write(inst, src[0]);
2310 spill_count++;
2311 break;
2312
2313 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2314 generate_scratch_read(inst, dst);
2315 fill_count++;
2316 break;
2317
2318 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2319 generate_scratch_read_gen7(inst, dst);
2320 fill_count++;
2321 break;
2322
2323 case SHADER_OPCODE_SCRATCH_HEADER:
2324 generate_scratch_header(inst, dst);
2325 break;
2326
2327 case SHADER_OPCODE_MOV_INDIRECT:
2328 generate_mov_indirect(inst, dst, src[0], src[1]);
2329 break;
2330
2331 case SHADER_OPCODE_MOV_RELOC_IMM:
2332 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2333 brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud);
2334 break;
2335
2336 case SHADER_OPCODE_URB_READ_SIMD8:
2337 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2338 generate_urb_read(inst, dst, src[0]);
2339 send_count++;
2340 break;
2341
2342 case SHADER_OPCODE_URB_WRITE_SIMD8:
2343 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2344 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2345 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2346 generate_urb_write(inst, src[0]);
2347 send_count++;
2348 break;
2349
2350 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2351 assert(inst->force_writemask_all);
2352 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2353 send_count++;
2354 break;
2355
2356 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2357 assert(inst->force_writemask_all);
2358 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2359 send_count++;
2360 break;
2361
2362 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
2363 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
2364 send_count++;
2365 break;
2366
2367 case FS_OPCODE_REP_FB_WRITE:
2368 case FS_OPCODE_FB_WRITE:
2369 generate_fb_write(inst, src[0]);
2370 send_count++;
2371 break;
2372
2373 case FS_OPCODE_FB_READ:
2374 generate_fb_read(inst, dst, src[0]);
2375 send_count++;
2376 break;
2377
2378 case FS_OPCODE_DISCARD_JUMP:
2379 generate_discard_jump(inst);
2380 break;
2381
2382 case SHADER_OPCODE_SHADER_TIME_ADD:
2383 generate_shader_time_add(inst, src[0], src[1], src[2]);
2384 break;
2385
2386 case SHADER_OPCODE_INTERLOCK:
2387 case SHADER_OPCODE_MEMORY_FENCE: {
2388 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2389 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2390
2391 const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ?
2392 BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
2393
2394 brw_memory_fence(p, dst, src[0], send_op,
2395 brw_message_target(inst->sfid),
2396 /* commit_enable */ src[1].ud,
2397 /* bti */ src[2].ud);
2398 send_count++;
2399 break;
2400 }
2401
2402 case FS_OPCODE_SCHEDULING_FENCE:
2403 if (inst->sources == 0 && inst->sched.regdist == 0 &&
2404 inst->sched.mode == TGL_SBID_NULL) {
2405 if (unlikely(debug_flag))
2406 disasm_info->use_tail = true;
2407 break;
2408 }
2409
2410 if (devinfo->gen >= 12) {
2411 /* Use the available SWSB information to stall. A single SYNC is
2412 * sufficient since if there were multiple dependencies, the
2413 * scoreboard algorithm already injected other SYNCs before this
2414 * instruction.
2415 */
2416 brw_SYNC(p, TGL_SYNC_NOP);
2417 } else {
2418 for (unsigned i = 0; i < inst->sources; i++) {
2419 /* Emit a MOV to force a stall until the instruction producing the
2420 * registers finishes.
2421 */
2422 brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW),
2423 retype(src[i], BRW_REGISTER_TYPE_UW));
2424 }
2425
2426 if (inst->sources > 1)
2427 multiple_instructions_emitted = true;
2428 }
2429
2430 break;
2431
2432 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
2433 const struct brw_reg mask =
2434 brw_stage_has_packed_dispatch(devinfo, stage,
2435 prog_data) ? brw_imm_ud(~0u) :
2436 stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
2437 brw_dmask_reg();
2438 brw_find_live_channel(p, dst, mask);
2439 break;
2440 }
2441 case FS_OPCODE_LOAD_LIVE_CHANNELS: {
2442 assert(devinfo->gen >= 8);
2443 assert(inst->force_writemask_all && inst->group == 0);
2444 assert(inst->dst.file == BAD_FILE);
2445 brw_set_default_exec_size(p, BRW_EXECUTE_1);
2446 brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg),
2447 BRW_REGISTER_TYPE_UD),
2448 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
2449 break;
2450 }
2451 case SHADER_OPCODE_BROADCAST:
2452 assert(inst->force_writemask_all);
2453 brw_broadcast(p, dst, src[0], src[1]);
2454 break;
2455
2456 case SHADER_OPCODE_SHUFFLE:
2457 generate_shuffle(inst, dst, src[0], src[1]);
2458 break;
2459
2460 case SHADER_OPCODE_SEL_EXEC:
2461 assert(inst->force_writemask_all);
2462 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
2463 brw_MOV(p, dst, src[1]);
2464 brw_set_default_mask_control(p, BRW_MASK_ENABLE);
2465 brw_set_default_swsb(p, tgl_swsb_null());
2466 brw_MOV(p, dst, src[0]);
2467 break;
2468
2469 case SHADER_OPCODE_QUAD_SWIZZLE:
2470 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2471 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2472 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
2473 break;
2474
2475 case SHADER_OPCODE_CLUSTER_BROADCAST: {
2476 assert(!src[0].negate && !src[0].abs);
2477 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2478 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2479 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2480 assert(src[2].type == BRW_REGISTER_TYPE_UD);
2481 const unsigned component = src[1].ud;
2482 const unsigned cluster_size = src[2].ud;
2483 unsigned vstride = cluster_size;
2484 unsigned width = cluster_size;
2485
2486 /* The maximum exec_size is 32, but the maximum width is only 16. */
2487 if (inst->exec_size == width) {
2488 vstride = 0;
2489 width = 1;
2490 }
2491
2492 struct brw_reg strided = stride(suboffset(src[0], component),
2493 vstride, width, 0);
2494 if (type_sz(src[0].type) > 4 &&
2495 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
2496 /* IVB has an issue (which we found empirically) where it reads
2497 * two address register components per channel for indirectly
2498 * addressed 64-bit sources.
2499 *
2500 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2501 *
2502 * "When source or destination datatype is 64b or operation is
2503 * integer DWord multiply, indirect addressing must not be
2504 * used."
2505 *
2506 * To work around both of these, we do two integer MOVs insead of
2507 * one 64-bit MOV. Because no double value should ever cross a
2508 * register boundary, it's safe to use the immediate offset in the
2509 * indirect here to handle adding 4 bytes to the offset and avoid
2510 * the extra ADD to the register file.
2511 */
2512 assert(src[0].type == dst.type);
2513 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
2514 subscript(strided, BRW_REGISTER_TYPE_D, 0));
2515 brw_set_default_swsb(p, tgl_swsb_null());
2516 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
2517 subscript(strided, BRW_REGISTER_TYPE_D, 1));
2518 } else {
2519 brw_MOV(p, dst, strided);
2520 }
2521 break;
2522 }
2523
2524 case FS_OPCODE_SET_SAMPLE_ID:
2525 generate_set_sample_id(inst, dst, src[0], src[1]);
2526 break;
2527
2528 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2529 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2530 break;
2531
2532 case FS_OPCODE_PLACEHOLDER_HALT:
2533 /* This is the place where the final HALT needs to be inserted if
2534 * we've emitted any discards. If not, this will emit no code.
2535 */
2536 if (!patch_discard_jumps_to_fb_writes()) {
2537 if (unlikely(debug_flag)) {
2538 disasm_info->use_tail = true;
2539 }
2540 }
2541 break;
2542
2543 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2544 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2545 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2546 send_count++;
2547 break;
2548
2549 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2550 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2551 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2552 send_count++;
2553 break;
2554
2555 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2556 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2557 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2558 send_count++;
2559 break;
2560
2561 case CS_OPCODE_CS_TERMINATE:
2562 generate_cs_terminate(inst, src[0]);
2563 send_count++;
2564 break;
2565
2566 case SHADER_OPCODE_BARRIER:
2567 generate_barrier(inst, src[0]);
2568 send_count++;
2569 break;
2570
2571 case BRW_OPCODE_DIM:
2572 assert(devinfo->is_haswell);
2573 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2574 assert(dst.type == BRW_REGISTER_TYPE_DF);
2575 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2576 break;
2577
2578 case SHADER_OPCODE_RND_MODE: {
2579 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2580 /*
2581 * Changes the floating point rounding mode updating the control
2582 * register field defined at cr0.0[5-6] bits.
2583 */
2584 enum brw_rnd_mode mode =
2585 (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
2586 brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
2587 }
2588 break;
2589
2590 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
2591 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2592 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2593 brw_float_controls_mode(p, src[0].d, src[1].d);
2594 break;
2595
2596 default:
2597 unreachable("Unsupported opcode");
2598
2599 case SHADER_OPCODE_LOAD_PAYLOAD:
2600 unreachable("Should be lowered by lower_load_payload()");
2601 }
2602
2603 if (multiple_instructions_emitted)
2604 continue;
2605
2606 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2607 assert(p->next_insn_offset == last_insn_offset + 16 ||
2608 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2609 "emitting more than 1 instruction");
2610
2611 brw_inst *last = &p->store[last_insn_offset / 16];
2612
2613 if (inst->conditional_mod)
2614 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2615 if (devinfo->gen < 12) {
2616 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2617 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2618 }
2619 }
2620 }
2621
2622 brw_set_uip_jip(p, start_offset);
2623
2624 /* end of program sentinel */
2625 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2626
2627 #ifndef NDEBUG
2628 bool validated =
2629 #else
2630 if (unlikely(debug_flag))
2631 #endif
2632 brw_validate_instructions(devinfo, p->store,
2633 start_offset,
2634 p->next_insn_offset,
2635 disasm_info);
2636
2637 int before_size = p->next_insn_offset - start_offset;
2638 brw_compact_instructions(p, start_offset, disasm_info);
2639 int after_size = p->next_insn_offset - start_offset;
2640
2641 if (unlikely(debug_flag)) {
2642 unsigned char sha1[21];
2643 char sha1buf[41];
2644
2645 _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst),
2646 after_size, sha1);
2647 _mesa_sha1_format(sha1buf, sha1);
2648
2649 fprintf(stderr, "Native code for %s (sha1 %s)\n"
2650 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2651 "%d:%d spills:fills, %u sends, "
2652 "scheduled with mode %s. "
2653 "Promoted %u constants. "
2654 "Compacted %d to %d bytes (%.0f%%)\n",
2655 shader_name, sha1buf,
2656 dispatch_width, before_size / 16,
2657 loop_count, perf.latency,
2658 spill_count, fill_count, send_count,
2659 shader_stats.scheduler_mode,
2660 shader_stats.promoted_constants,
2661 before_size, after_size,
2662 100.0f * (before_size - after_size) / before_size);
2663
2664 /* overriding the shader makes disasm_info invalid */
2665 if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
2666 dump_assembly(p->store, start_offset, p->next_insn_offset,
2667 disasm_info, perf.block_latency);
2668 } else {
2669 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2670 }
2671 }
2672 ralloc_free(disasm_info);
2673 #ifndef NDEBUG
2674 if (!validated && !debug_flag) {
2675 fprintf(stderr,
2676 "Validation failed. Rerun with INTEL_DEBUG=shaders to get more information.\n");
2677 }
2678 #endif
2679 assert(validated);
2680
2681 compiler->shader_debug_log(log_data,
2682 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2683 "%d:%d spills:fills, %u sends, "
2684 "scheduled with mode %s, "
2685 "Promoted %u constants, "
2686 "compacted %d to %d bytes.",
2687 _mesa_shader_stage_to_abbrev(stage),
2688 dispatch_width, before_size / 16 - nop_count,
2689 loop_count, perf.latency,
2690 spill_count, fill_count, send_count,
2691 shader_stats.scheduler_mode,
2692 shader_stats.promoted_constants,
2693 before_size, after_size);
2694 if (stats) {
2695 stats->dispatch_width = dispatch_width;
2696 stats->instructions = before_size / 16 - nop_count;
2697 stats->sends = send_count;
2698 stats->loops = loop_count;
2699 stats->cycles = perf.latency;
2700 stats->spills = spill_count;
2701 stats->fills = fill_count;
2702 }
2703
2704 return start_offset;
2705 }
2706
2707 void
add_const_data(void * data,unsigned size)2708 fs_generator::add_const_data(void *data, unsigned size)
2709 {
2710 assert(prog_data->const_data_size == 0);
2711 if (size > 0) {
2712 prog_data->const_data_size = size;
2713 prog_data->const_data_offset = brw_append_data(p, data, size, 32);
2714 }
2715 }
2716
2717 const unsigned *
get_assembly()2718 fs_generator::get_assembly()
2719 {
2720 prog_data->relocs = brw_get_shader_relocs(p, &prog_data->num_relocs);
2721
2722 return brw_get_program(p, &prog_data->program_size);
2723 }
2724