1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines structures to encapsulate information gleaned from the
10 // target register and register class definitions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "CodeGenRegisters.h"
15 #include "CodeGenTarget.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/IntEqClasses.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Twine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/TableGen/Error.h"
32 #include "llvm/TableGen/Record.h"
33 #include <algorithm>
34 #include <cassert>
35 #include <cstdint>
36 #include <iterator>
37 #include <map>
38 #include <queue>
39 #include <set>
40 #include <string>
41 #include <tuple>
42 #include <utility>
43 #include <vector>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "regalloc-emitter"
48 
49 //===----------------------------------------------------------------------===//
50 //                             CodeGenSubRegIndex
51 //===----------------------------------------------------------------------===//
52 
CodeGenSubRegIndex(Record * R,unsigned Enum)53 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
54   : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
55   Name = std::string(R->getName());
56   if (R->getValue("Namespace"))
57     Namespace = std::string(R->getValueAsString("Namespace"));
58   Size = R->getValueAsInt("Size");
59   Offset = R->getValueAsInt("Offset");
60 }
61 
CodeGenSubRegIndex(StringRef N,StringRef Nspace,unsigned Enum)62 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
63                                        unsigned Enum)
64     : TheDef(nullptr), Name(std::string(N)), Namespace(std::string(Nspace)),
65       Size(-1), Offset(-1), EnumValue(Enum), AllSuperRegsCovered(true),
66       Artificial(true) {}
67 
getQualifiedName() const68 std::string CodeGenSubRegIndex::getQualifiedName() const {
69   std::string N = getNamespace();
70   if (!N.empty())
71     N += "::";
72   N += getName();
73   return N;
74 }
75 
updateComponents(CodeGenRegBank & RegBank)76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
77   if (!TheDef)
78     return;
79 
80   std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
81   if (!Comps.empty()) {
82     if (Comps.size() != 2)
83       PrintFatalError(TheDef->getLoc(),
84                       "ComposedOf must have exactly two entries");
85     CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
86     CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
87     CodeGenSubRegIndex *X = A->addComposite(B, this);
88     if (X)
89       PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
90   }
91 
92   std::vector<Record*> Parts =
93     TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
94   if (!Parts.empty()) {
95     if (Parts.size() < 2)
96       PrintFatalError(TheDef->getLoc(),
97                       "CoveredBySubRegs must have two or more entries");
98     SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
99     for (Record *Part : Parts)
100       IdxParts.push_back(RegBank.getSubRegIdx(Part));
101     setConcatenationOf(IdxParts);
102   }
103 }
104 
computeLaneMask() const105 LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
106   // Already computed?
107   if (LaneMask.any())
108     return LaneMask;
109 
110   // Recursion guard, shouldn't be required.
111   LaneMask = LaneBitmask::getAll();
112 
113   // The lane mask is simply the union of all sub-indices.
114   LaneBitmask M;
115   for (const auto &C : Composed)
116     M |= C.second->computeLaneMask();
117   assert(M.any() && "Missing lane mask, sub-register cycle?");
118   LaneMask = M;
119   return LaneMask;
120 }
121 
setConcatenationOf(ArrayRef<CodeGenSubRegIndex * > Parts)122 void CodeGenSubRegIndex::setConcatenationOf(
123     ArrayRef<CodeGenSubRegIndex*> Parts) {
124   if (ConcatenationOf.empty())
125     ConcatenationOf.assign(Parts.begin(), Parts.end());
126   else
127     assert(std::equal(Parts.begin(), Parts.end(),
128                       ConcatenationOf.begin()) && "parts consistent");
129 }
130 
computeConcatTransitiveClosure()131 void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
132   for (SmallVectorImpl<CodeGenSubRegIndex*>::iterator
133        I = ConcatenationOf.begin(); I != ConcatenationOf.end(); /*empty*/) {
134     CodeGenSubRegIndex *SubIdx = *I;
135     SubIdx->computeConcatTransitiveClosure();
136 #ifndef NDEBUG
137     for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf)
138       assert(SRI->ConcatenationOf.empty() && "No transitive closure?");
139 #endif
140 
141     if (SubIdx->ConcatenationOf.empty()) {
142       ++I;
143     } else {
144       I = ConcatenationOf.erase(I);
145       I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(),
146                                  SubIdx->ConcatenationOf.end());
147       I += SubIdx->ConcatenationOf.size();
148     }
149   }
150 }
151 
152 //===----------------------------------------------------------------------===//
153 //                              CodeGenRegister
154 //===----------------------------------------------------------------------===//
155 
CodeGenRegister(Record * R,unsigned Enum)156 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
157   : TheDef(R),
158     EnumValue(Enum),
159     CostPerUse(R->getValueAsInt("CostPerUse")),
160     CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
161     HasDisjunctSubRegs(false),
162     SubRegsComplete(false),
163     SuperRegsComplete(false),
164     TopoSig(~0u) {
165   Artificial = R->getValueAsBit("isArtificial");
166 }
167 
buildObjectGraph(CodeGenRegBank & RegBank)168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
169   std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
170   std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
171 
172   if (SRIs.size() != SRs.size())
173     PrintFatalError(TheDef->getLoc(),
174                     "SubRegs and SubRegIndices must have the same size");
175 
176   for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
177     ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
178     ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
179   }
180 
181   // Also compute leading super-registers. Each register has a list of
182   // covered-by-subregs super-registers where it appears as the first explicit
183   // sub-register.
184   //
185   // This is used by computeSecondarySubRegs() to find candidates.
186   if (CoveredBySubRegs && !ExplicitSubRegs.empty())
187     ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
188 
189   // Add ad hoc alias links. This is a symmetric relationship between two
190   // registers, so build a symmetric graph by adding links in both ends.
191   std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
192   for (Record *Alias : Aliases) {
193     CodeGenRegister *Reg = RegBank.getReg(Alias);
194     ExplicitAliases.push_back(Reg);
195     Reg->ExplicitAliases.push_back(this);
196   }
197 }
198 
getName() const199 const StringRef CodeGenRegister::getName() const {
200   assert(TheDef && "no def");
201   return TheDef->getName();
202 }
203 
204 namespace {
205 
206 // Iterate over all register units in a set of registers.
207 class RegUnitIterator {
208   CodeGenRegister::Vec::const_iterator RegI, RegE;
209   CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
210 
211 public:
RegUnitIterator(const CodeGenRegister::Vec & Regs)212   RegUnitIterator(const CodeGenRegister::Vec &Regs):
213     RegI(Regs.begin()), RegE(Regs.end()) {
214 
215     if (RegI != RegE) {
216       UnitI = (*RegI)->getRegUnits().begin();
217       UnitE = (*RegI)->getRegUnits().end();
218       advance();
219     }
220   }
221 
isValid() const222   bool isValid() const { return UnitI != UnitE; }
223 
operator *() const224   unsigned operator* () const { assert(isValid()); return *UnitI; }
225 
getReg() const226   const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
227 
228   /// Preincrement.  Move to the next unit.
operator ++()229   void operator++() {
230     assert(isValid() && "Cannot advance beyond the last operand");
231     ++UnitI;
232     advance();
233   }
234 
235 protected:
advance()236   void advance() {
237     while (UnitI == UnitE) {
238       if (++RegI == RegE)
239         break;
240       UnitI = (*RegI)->getRegUnits().begin();
241       UnitE = (*RegI)->getRegUnits().end();
242     }
243   }
244 };
245 
246 } // end anonymous namespace
247 
248 // Return true of this unit appears in RegUnits.
hasRegUnit(CodeGenRegister::RegUnitList & RegUnits,unsigned Unit)249 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
250   return RegUnits.test(Unit);
251 }
252 
253 // Inherit register units from subregisters.
254 // Return true if the RegUnits changed.
inheritRegUnits(CodeGenRegBank & RegBank)255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
256   bool changed = false;
257   for (const auto &SubReg : SubRegs) {
258     CodeGenRegister *SR = SubReg.second;
259     // Merge the subregister's units into this register's RegUnits.
260     changed |= (RegUnits |= SR->RegUnits);
261   }
262 
263   return changed;
264 }
265 
266 const CodeGenRegister::SubRegMap &
computeSubRegs(CodeGenRegBank & RegBank)267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
268   // Only compute this map once.
269   if (SubRegsComplete)
270     return SubRegs;
271   SubRegsComplete = true;
272 
273   HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
274 
275   // First insert the explicit subregs and make sure they are fully indexed.
276   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
277     CodeGenRegister *SR = ExplicitSubRegs[i];
278     CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
279     if (!SR->Artificial)
280       Idx->Artificial = false;
281     if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
282       PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
283                       " appears twice in Register " + getName());
284     // Map explicit sub-registers first, so the names take precedence.
285     // The inherited sub-registers are mapped below.
286     SubReg2Idx.insert(std::make_pair(SR, Idx));
287   }
288 
289   // Keep track of inherited subregs and how they can be reached.
290   SmallPtrSet<CodeGenRegister*, 8> Orphans;
291 
292   // Clone inherited subregs and place duplicate entries in Orphans.
293   // Here the order is important - earlier subregs take precedence.
294   for (CodeGenRegister *ESR : ExplicitSubRegs) {
295     const SubRegMap &Map = ESR->computeSubRegs(RegBank);
296     HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs;
297 
298     for (const auto &SR : Map) {
299       if (!SubRegs.insert(SR).second)
300         Orphans.insert(SR.second);
301     }
302   }
303 
304   // Expand any composed subreg indices.
305   // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
306   // qsub_1 subreg, add a dsub_2 subreg.  Keep growing Indices and process
307   // expanded subreg indices recursively.
308   SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
309   for (unsigned i = 0; i != Indices.size(); ++i) {
310     CodeGenSubRegIndex *Idx = Indices[i];
311     const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
312     CodeGenRegister *SR = SubRegs[Idx];
313     const SubRegMap &Map = SR->computeSubRegs(RegBank);
314 
315     // Look at the possible compositions of Idx.
316     // They may not all be supported by SR.
317     for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
318            E = Comps.end(); I != E; ++I) {
319       SubRegMap::const_iterator SRI = Map.find(I->first);
320       if (SRI == Map.end())
321         continue; // Idx + I->first doesn't exist in SR.
322       // Add I->second as a name for the subreg SRI->second, assuming it is
323       // orphaned, and the name isn't already used for something else.
324       if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
325         continue;
326       // We found a new name for the orphaned sub-register.
327       SubRegs.insert(std::make_pair(I->second, SRI->second));
328       Indices.push_back(I->second);
329     }
330   }
331 
332   // Now Orphans contains the inherited subregisters without a direct index.
333   // Create inferred indexes for all missing entries.
334   // Work backwards in the Indices vector in order to compose subregs bottom-up.
335   // Consider this subreg sequence:
336   //
337   //   qsub_1 -> dsub_0 -> ssub_0
338   //
339   // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
340   // can be reached in two different ways:
341   //
342   //   qsub_1 -> ssub_0
343   //   dsub_2 -> ssub_0
344   //
345   // We pick the latter composition because another register may have [dsub_0,
346   // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg.  The
347   // dsub_2 -> ssub_0 composition can be shared.
348   while (!Indices.empty() && !Orphans.empty()) {
349     CodeGenSubRegIndex *Idx = Indices.pop_back_val();
350     CodeGenRegister *SR = SubRegs[Idx];
351     const SubRegMap &Map = SR->computeSubRegs(RegBank);
352     for (const auto &SubReg : Map)
353       if (Orphans.erase(SubReg.second))
354         SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second;
355   }
356 
357   // Compute the inverse SubReg -> Idx map.
358   for (const auto &SubReg : SubRegs) {
359     if (SubReg.second == this) {
360       ArrayRef<SMLoc> Loc;
361       if (TheDef)
362         Loc = TheDef->getLoc();
363       PrintFatalError(Loc, "Register " + getName() +
364                       " has itself as a sub-register");
365     }
366 
367     // Compute AllSuperRegsCovered.
368     if (!CoveredBySubRegs)
369       SubReg.first->AllSuperRegsCovered = false;
370 
371     // Ensure that every sub-register has a unique name.
372     DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
373       SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
374     if (Ins->second == SubReg.first)
375       continue;
376     // Trouble: Two different names for SubReg.second.
377     ArrayRef<SMLoc> Loc;
378     if (TheDef)
379       Loc = TheDef->getLoc();
380     PrintFatalError(Loc, "Sub-register can't have two names: " +
381                   SubReg.second->getName() + " available as " +
382                   SubReg.first->getName() + " and " + Ins->second->getName());
383   }
384 
385   // Derive possible names for sub-register concatenations from any explicit
386   // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
387   // that getConcatSubRegIndex() won't invent any concatenated indices that the
388   // user already specified.
389   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
390     CodeGenRegister *SR = ExplicitSubRegs[i];
391     if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 ||
392         SR->Artificial)
393       continue;
394 
395     // SR is composed of multiple sub-regs. Find their names in this register.
396     SmallVector<CodeGenSubRegIndex*, 8> Parts;
397     for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
398       CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
399       if (!I.Artificial)
400         Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
401     }
402 
403     // Offer this as an existing spelling for the concatenation of Parts.
404     CodeGenSubRegIndex &Idx = *ExplicitSubRegIndices[i];
405     Idx.setConcatenationOf(Parts);
406   }
407 
408   // Initialize RegUnitList. Because getSubRegs is called recursively, this
409   // processes the register hierarchy in postorder.
410   //
411   // Inherit all sub-register units. It is good enough to look at the explicit
412   // sub-registers, the other registers won't contribute any more units.
413   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
414     CodeGenRegister *SR = ExplicitSubRegs[i];
415     RegUnits |= SR->RegUnits;
416   }
417 
418   // Absent any ad hoc aliasing, we create one register unit per leaf register.
419   // These units correspond to the maximal cliques in the register overlap
420   // graph which is optimal.
421   //
422   // When there is ad hoc aliasing, we simply create one unit per edge in the
423   // undirected ad hoc aliasing graph. Technically, we could do better by
424   // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
425   // are extremely rare anyway (I've never seen one), so we don't bother with
426   // the added complexity.
427   for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
428     CodeGenRegister *AR = ExplicitAliases[i];
429     // Only visit each edge once.
430     if (AR->SubRegsComplete)
431       continue;
432     // Create a RegUnit representing this alias edge, and add it to both
433     // registers.
434     unsigned Unit = RegBank.newRegUnit(this, AR);
435     RegUnits.set(Unit);
436     AR->RegUnits.set(Unit);
437   }
438 
439   // Finally, create units for leaf registers without ad hoc aliases. Note that
440   // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
441   // necessary. This means the aliasing leaf registers can share a single unit.
442   if (RegUnits.empty())
443     RegUnits.set(RegBank.newRegUnit(this));
444 
445   // We have now computed the native register units. More may be adopted later
446   // for balancing purposes.
447   NativeRegUnits = RegUnits;
448 
449   return SubRegs;
450 }
451 
452 // In a register that is covered by its sub-registers, try to find redundant
453 // sub-registers. For example:
454 //
455 //   QQ0 = {Q0, Q1}
456 //   Q0 = {D0, D1}
457 //   Q1 = {D2, D3}
458 //
459 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in
460 // the register definition.
461 //
462 // The explicitly specified registers form a tree. This function discovers
463 // sub-register relationships that would force a DAG.
464 //
computeSecondarySubRegs(CodeGenRegBank & RegBank)465 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
466   SmallVector<SubRegMap::value_type, 8> NewSubRegs;
467 
468   std::queue<std::pair<CodeGenSubRegIndex*,CodeGenRegister*>> SubRegQueue;
469   for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : SubRegs)
470     SubRegQueue.push(P);
471 
472   // Look at the leading super-registers of each sub-register. Those are the
473   // candidates for new sub-registers, assuming they are fully contained in
474   // this register.
475   while (!SubRegQueue.empty()) {
476     CodeGenSubRegIndex *SubRegIdx;
477     const CodeGenRegister *SubReg;
478     std::tie(SubRegIdx, SubReg) = SubRegQueue.front();
479     SubRegQueue.pop();
480 
481     const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
482     for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
483       CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
484       // Already got this sub-register?
485       if (Cand == this || getSubRegIndex(Cand))
486         continue;
487       // Check if each component of Cand is already a sub-register.
488       assert(!Cand->ExplicitSubRegs.empty() &&
489              "Super-register has no sub-registers");
490       if (Cand->ExplicitSubRegs.size() == 1)
491         continue;
492       SmallVector<CodeGenSubRegIndex*, 8> Parts;
493       // We know that the first component is (SubRegIdx,SubReg). However we
494       // may still need to split it into smaller subregister parts.
495       assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
496       assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
497       for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
498         if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
499           if (SubRegIdx->ConcatenationOf.empty()) {
500             Parts.push_back(SubRegIdx);
501           } else
502             for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
503               Parts.push_back(SubIdx);
504         } else {
505           // Sub-register doesn't exist.
506           Parts.clear();
507           break;
508         }
509       }
510       // There is nothing to do if some Cand sub-register is not part of this
511       // register.
512       if (Parts.empty())
513         continue;
514 
515       // Each part of Cand is a sub-register of this. Make the full Cand also
516       // a sub-register with a concatenated sub-register index.
517       CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
518       std::pair<CodeGenSubRegIndex*,CodeGenRegister*> NewSubReg =
519           std::make_pair(Concat, Cand);
520 
521       if (!SubRegs.insert(NewSubReg).second)
522         continue;
523 
524       // We inserted a new subregister.
525       NewSubRegs.push_back(NewSubReg);
526       SubRegQueue.push(NewSubReg);
527       SubReg2Idx.insert(std::make_pair(Cand, Concat));
528     }
529   }
530 
531   // Create sub-register index composition maps for the synthesized indices.
532   for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
533     CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
534     CodeGenRegister *NewSubReg = NewSubRegs[i].second;
535     for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
536            SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
537       CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
538       if (!SubIdx)
539         PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
540                         SI->second->getName() + " in " + getName());
541       NewIdx->addComposite(SI->first, SubIdx);
542     }
543   }
544 }
545 
computeSuperRegs(CodeGenRegBank & RegBank)546 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
547   // Only visit each register once.
548   if (SuperRegsComplete)
549     return;
550   SuperRegsComplete = true;
551 
552   // Make sure all sub-registers have been visited first, so the super-reg
553   // lists will be topologically ordered.
554   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
555        I != E; ++I)
556     I->second->computeSuperRegs(RegBank);
557 
558   // Now add this as a super-register on all sub-registers.
559   // Also compute the TopoSigId in post-order.
560   TopoSigId Id;
561   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
562        I != E; ++I) {
563     // Topological signature computed from SubIdx, TopoId(SubReg).
564     // Loops and idempotent indices have TopoSig = ~0u.
565     Id.push_back(I->first->EnumValue);
566     Id.push_back(I->second->TopoSig);
567 
568     // Don't add duplicate entries.
569     if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
570       continue;
571     I->second->SuperRegs.push_back(this);
572   }
573   TopoSig = RegBank.getTopoSig(Id);
574 }
575 
576 void
addSubRegsPreOrder(SetVector<const CodeGenRegister * > & OSet,CodeGenRegBank & RegBank) const577 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
578                                     CodeGenRegBank &RegBank) const {
579   assert(SubRegsComplete && "Must precompute sub-registers");
580   for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
581     CodeGenRegister *SR = ExplicitSubRegs[i];
582     if (OSet.insert(SR))
583       SR->addSubRegsPreOrder(OSet, RegBank);
584   }
585   // Add any secondary sub-registers that weren't part of the explicit tree.
586   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
587        I != E; ++I)
588     OSet.insert(I->second);
589 }
590 
591 // Get the sum of this register's unit weights.
getWeight(const CodeGenRegBank & RegBank) const592 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
593   unsigned Weight = 0;
594   for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
595        I != E; ++I) {
596     Weight += RegBank.getRegUnit(*I).Weight;
597   }
598   return Weight;
599 }
600 
601 //===----------------------------------------------------------------------===//
602 //                               RegisterTuples
603 //===----------------------------------------------------------------------===//
604 
605 // A RegisterTuples def is used to generate pseudo-registers from lists of
606 // sub-registers. We provide a SetTheory expander class that returns the new
607 // registers.
608 namespace {
609 
610 struct TupleExpander : SetTheory::Expander {
611   // Reference to SynthDefs in the containing CodeGenRegBank, to keep track of
612   // the synthesized definitions for their lifetime.
613   std::vector<std::unique_ptr<Record>> &SynthDefs;
614 
TupleExpander__anon74a933d80211::TupleExpander615   TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs)
616       : SynthDefs(SynthDefs) {}
617 
expand__anon74a933d80211::TupleExpander618   void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619     std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
620     unsigned Dim = Indices.size();
621     ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
622     if (Dim != SubRegs->size())
623       PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
624     if (Dim < 2)
625       PrintFatalError(Def->getLoc(),
626                       "Tuples must have at least 2 sub-registers");
627 
628     // Evaluate the sub-register lists to be zipped.
629     unsigned Length = ~0u;
630     SmallVector<SetTheory::RecSet, 4> Lists(Dim);
631     for (unsigned i = 0; i != Dim; ++i) {
632       ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
633       Length = std::min(Length, unsigned(Lists[i].size()));
634     }
635 
636     if (Length == 0)
637       return;
638 
639     // Precompute some types.
640     Record *RegisterCl = Def->getRecords().getClass("Register");
641     RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
642     std::vector<StringRef> RegNames =
643       Def->getValueAsListOfStrings("RegAsmNames");
644 
645     // Zip them up.
646     for (unsigned n = 0; n != Length; ++n) {
647       std::string Name;
648       Record *Proto = Lists[0][n];
649       std::vector<Init*> Tuple;
650       unsigned CostPerUse = 0;
651       for (unsigned i = 0; i != Dim; ++i) {
652         Record *Reg = Lists[i][n];
653         if (i) Name += '_';
654         Name += Reg->getName();
655         Tuple.push_back(DefInit::get(Reg));
656         CostPerUse = std::max(CostPerUse,
657                               unsigned(Reg->getValueAsInt("CostPerUse")));
658       }
659 
660       StringInit *AsmName = StringInit::get("");
661       if (!RegNames.empty()) {
662         if (RegNames.size() <= n)
663           PrintFatalError(Def->getLoc(),
664                           "Register tuple definition missing name for '" +
665                             Name + "'.");
666         AsmName = StringInit::get(RegNames[n]);
667       }
668 
669       // Create a new Record representing the synthesized register. This record
670       // is only for consumption by CodeGenRegister, it is not added to the
671       // RecordKeeper.
672       SynthDefs.emplace_back(
673           std::make_unique<Record>(Name, Def->getLoc(), Def->getRecords()));
674       Record *NewReg = SynthDefs.back().get();
675       Elts.insert(NewReg);
676 
677       // Copy Proto super-classes.
678       ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses();
679       for (const auto &SuperPair : Supers)
680         NewReg->addSuperClass(SuperPair.first, SuperPair.second);
681 
682       // Copy Proto fields.
683       for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
684         RecordVal RV = Proto->getValues()[i];
685 
686         // Skip existing fields, like NAME.
687         if (NewReg->getValue(RV.getNameInit()))
688           continue;
689 
690         StringRef Field = RV.getName();
691 
692         // Replace the sub-register list with Tuple.
693         if (Field == "SubRegs")
694           RV.setValue(ListInit::get(Tuple, RegisterRecTy));
695 
696         if (Field == "AsmName")
697           RV.setValue(AsmName);
698 
699         // CostPerUse is aggregated from all Tuple members.
700         if (Field == "CostPerUse")
701           RV.setValue(IntInit::get(CostPerUse));
702 
703         // Composite registers are always covered by sub-registers.
704         if (Field == "CoveredBySubRegs")
705           RV.setValue(BitInit::get(true));
706 
707         // Copy fields from the RegisterTuples def.
708         if (Field == "SubRegIndices" ||
709             Field == "CompositeIndices") {
710           NewReg->addValue(*Def->getValue(Field));
711           continue;
712         }
713 
714         // Some fields get their default uninitialized value.
715         if (Field == "DwarfNumbers" ||
716             Field == "DwarfAlias" ||
717             Field == "Aliases") {
718           if (const RecordVal *DefRV = RegisterCl->getValue(Field))
719             NewReg->addValue(*DefRV);
720           continue;
721         }
722 
723         // Everything else is copied from Proto.
724         NewReg->addValue(RV);
725       }
726     }
727   }
728 };
729 
730 } // end anonymous namespace
731 
732 //===----------------------------------------------------------------------===//
733 //                            CodeGenRegisterClass
734 //===----------------------------------------------------------------------===//
735 
sortAndUniqueRegisters(CodeGenRegister::Vec & M)736 static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
737   llvm::sort(M, deref<std::less<>>());
738   M.erase(std::unique(M.begin(), M.end(), deref<std::equal_to<>>()), M.end());
739 }
740 
CodeGenRegisterClass(CodeGenRegBank & RegBank,Record * R)741 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
742     : TheDef(R), Name(std::string(R->getName())),
743       TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
744   GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
745   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
746   if (TypeList.empty())
747     PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
748   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
749     Record *Type = TypeList[i];
750     if (!Type->isSubClassOf("ValueType"))
751       PrintFatalError(R->getLoc(),
752                       "RegTypes list member '" + Type->getName() +
753                           "' does not derive from the ValueType class!");
754     VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
755   }
756 
757   // Allocation order 0 is the full set. AltOrders provides others.
758   const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
759   ListInit *AltOrders = R->getValueAsListInit("AltOrders");
760   Orders.resize(1 + AltOrders->size());
761 
762   // Default allocation order always contains all registers.
763   Artificial = true;
764   for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
765     Orders[0].push_back((*Elements)[i]);
766     const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
767     Members.push_back(Reg);
768     Artificial &= Reg->Artificial;
769     TopoSigs.set(Reg->getTopoSig());
770   }
771   sortAndUniqueRegisters(Members);
772 
773   // Alternative allocation orders may be subsets.
774   SetTheory::RecSet Order;
775   for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
776     RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
777     Orders[1 + i].append(Order.begin(), Order.end());
778     // Verify that all altorder members are regclass members.
779     while (!Order.empty()) {
780       CodeGenRegister *Reg = RegBank.getReg(Order.back());
781       Order.pop_back();
782       if (!contains(Reg))
783         PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
784                       " is not a class member");
785     }
786   }
787 
788   Namespace = R->getValueAsString("Namespace");
789 
790   if (const RecordVal *RV = R->getValue("RegInfos"))
791     if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue()))
792       RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes());
793   unsigned Size = R->getValueAsInt("Size");
794   assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&
795          "Impossible to determine register size");
796   if (!RSI.hasDefault()) {
797     RegSizeInfo RI;
798     RI.RegSize = RI.SpillSize = Size ? Size
799                                      : VTs[0].getSimple().getSizeInBits();
800     RI.SpillAlignment = R->getValueAsInt("Alignment");
801     RSI.Map.insert({DefaultMode, RI});
802   }
803 
804   CopyCost = R->getValueAsInt("CopyCost");
805   Allocatable = R->getValueAsBit("isAllocatable");
806   AltOrderSelect = R->getValueAsString("AltOrderSelect");
807   int AllocationPriority = R->getValueAsInt("AllocationPriority");
808   if (AllocationPriority < 0 || AllocationPriority > 63)
809     PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
810   this->AllocationPriority = AllocationPriority;
811 }
812 
813 // Create an inferred register class that was missing from the .td files.
814 // Most properties will be inherited from the closest super-class after the
815 // class structure has been computed.
CodeGenRegisterClass(CodeGenRegBank & RegBank,StringRef Name,Key Props)816 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
817                                            StringRef Name, Key Props)
818     : Members(*Props.Members), TheDef(nullptr), Name(std::string(Name)),
819       TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI),
820       CopyCost(0), Allocatable(true), AllocationPriority(0) {
821   Artificial = true;
822   GeneratePressureSet = false;
823   for (const auto R : Members) {
824     TopoSigs.set(R->getTopoSig());
825     Artificial &= R->Artificial;
826   }
827 }
828 
829 // Compute inherited propertied for a synthesized register class.
inheritProperties(CodeGenRegBank & RegBank)830 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
831   assert(!getDef() && "Only synthesized classes can inherit properties");
832   assert(!SuperClasses.empty() && "Synthesized class without super class");
833 
834   // The last super-class is the smallest one.
835   CodeGenRegisterClass &Super = *SuperClasses.back();
836 
837   // Most properties are copied directly.
838   // Exceptions are members, size, and alignment
839   Namespace = Super.Namespace;
840   VTs = Super.VTs;
841   CopyCost = Super.CopyCost;
842   Allocatable = Super.Allocatable;
843   AltOrderSelect = Super.AltOrderSelect;
844   AllocationPriority = Super.AllocationPriority;
845   GeneratePressureSet |= Super.GeneratePressureSet;
846 
847   // Copy all allocation orders, filter out foreign registers from the larger
848   // super-class.
849   Orders.resize(Super.Orders.size());
850   for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
851     for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
852       if (contains(RegBank.getReg(Super.Orders[i][j])))
853         Orders[i].push_back(Super.Orders[i][j]);
854 }
855 
contains(const CodeGenRegister * Reg) const856 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
857   return std::binary_search(Members.begin(), Members.end(), Reg,
858                             deref<std::less<>>());
859 }
860 
getWeight(const CodeGenRegBank & RegBank) const861 unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const {
862   if (TheDef && !TheDef->isValueUnset("Weight"))
863     return TheDef->getValueAsInt("Weight");
864 
865   if (Members.empty() || Artificial)
866     return 0;
867 
868   return (*Members.begin())->getWeight(RegBank);
869 }
870 
871 namespace llvm {
872 
operator <<(raw_ostream & OS,const CodeGenRegisterClass::Key & K)873   raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
874     OS << "{ " << K.RSI;
875     for (const auto R : *K.Members)
876       OS << ", " << R->getName();
877     return OS << " }";
878   }
879 
880 } // end namespace llvm
881 
882 // This is a simple lexicographical order that can be used to search for sets.
883 // It is not the same as the topological order provided by TopoOrderRC.
884 bool CodeGenRegisterClass::Key::
operator <(const CodeGenRegisterClass::Key & B) const885 operator<(const CodeGenRegisterClass::Key &B) const {
886   assert(Members && B.Members);
887   return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
888 }
889 
890 // Returns true if RC is a strict subclass.
891 // RC is a sub-class of this class if it is a valid replacement for any
892 // instruction operand where a register of this classis required. It must
893 // satisfy these conditions:
894 //
895 // 1. All RC registers are also in this.
896 // 2. The RC spill size must not be smaller than our spill size.
897 // 3. RC spill alignment must be compatible with ours.
898 //
testSubClass(const CodeGenRegisterClass * A,const CodeGenRegisterClass * B)899 static bool testSubClass(const CodeGenRegisterClass *A,
900                          const CodeGenRegisterClass *B) {
901   return A->RSI.isSubClassOf(B->RSI) &&
902          std::includes(A->getMembers().begin(), A->getMembers().end(),
903                        B->getMembers().begin(), B->getMembers().end(),
904                        deref<std::less<>>());
905 }
906 
907 /// Sorting predicate for register classes.  This provides a topological
908 /// ordering that arranges all register classes before their sub-classes.
909 ///
910 /// Register classes with the same registers, spill size, and alignment form a
911 /// clique.  They will be ordered alphabetically.
912 ///
TopoOrderRC(const CodeGenRegisterClass & PA,const CodeGenRegisterClass & PB)913 static bool TopoOrderRC(const CodeGenRegisterClass &PA,
914                         const CodeGenRegisterClass &PB) {
915   auto *A = &PA;
916   auto *B = &PB;
917   if (A == B)
918     return false;
919 
920   if (A->RSI < B->RSI)
921     return true;
922   if (A->RSI != B->RSI)
923     return false;
924 
925   // Order by descending set size.  Note that the classes' allocation order may
926   // not have been computed yet.  The Members set is always vaild.
927   if (A->getMembers().size() > B->getMembers().size())
928     return true;
929   if (A->getMembers().size() < B->getMembers().size())
930     return false;
931 
932   // Finally order by name as a tie breaker.
933   return StringRef(A->getName()) < B->getName();
934 }
935 
getQualifiedName() const936 std::string CodeGenRegisterClass::getQualifiedName() const {
937   if (Namespace.empty())
938     return getName();
939   else
940     return (Namespace + "::" + getName()).str();
941 }
942 
943 // Compute sub-classes of all register classes.
944 // Assume the classes are ordered topologically.
computeSubClasses(CodeGenRegBank & RegBank)945 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
946   auto &RegClasses = RegBank.getRegClasses();
947 
948   // Visit backwards so sub-classes are seen first.
949   for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
950     CodeGenRegisterClass &RC = *I;
951     RC.SubClasses.resize(RegClasses.size());
952     RC.SubClasses.set(RC.EnumValue);
953     if (RC.Artificial)
954       continue;
955 
956     // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
957     for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
958       CodeGenRegisterClass &SubRC = *I2;
959       if (RC.SubClasses.test(SubRC.EnumValue))
960         continue;
961       if (!testSubClass(&RC, &SubRC))
962         continue;
963       // SubRC is a sub-class. Grap all its sub-classes so we won't have to
964       // check them again.
965       RC.SubClasses |= SubRC.SubClasses;
966     }
967 
968     // Sweep up missed clique members.  They will be immediately preceding RC.
969     for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2)
970       RC.SubClasses.set(I2->EnumValue);
971   }
972 
973   // Compute the SuperClasses lists from the SubClasses vectors.
974   for (auto &RC : RegClasses) {
975     const BitVector &SC = RC.getSubClasses();
976     auto I = RegClasses.begin();
977     for (int s = 0, next_s = SC.find_first(); next_s != -1;
978          next_s = SC.find_next(s)) {
979       std::advance(I, next_s - s);
980       s = next_s;
981       if (&*I == &RC)
982         continue;
983       I->SuperClasses.push_back(&RC);
984     }
985   }
986 
987   // With the class hierarchy in place, let synthesized register classes inherit
988   // properties from their closest super-class. The iteration order here can
989   // propagate properties down multiple levels.
990   for (auto &RC : RegClasses)
991     if (!RC.getDef())
992       RC.inheritProperties(RegBank);
993 }
994 
995 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
getMatchingSubClassWithSubRegs(CodeGenRegBank & RegBank,const CodeGenSubRegIndex * SubIdx) const996 CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
997     CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
998   auto SizeOrder = [this](const CodeGenRegisterClass *A,
999                       const CodeGenRegisterClass *B) {
1000     // If there are multiple, identical register classes, prefer the original
1001     // register class.
1002     if (A == B)
1003       return false;
1004     if (A->getMembers().size() == B->getMembers().size())
1005       return A == this;
1006     return A->getMembers().size() > B->getMembers().size();
1007   };
1008 
1009   auto &RegClasses = RegBank.getRegClasses();
1010 
1011   // Find all the subclasses of this one that fully support the sub-register
1012   // index and order them by size. BiggestSuperRC should always be first.
1013   CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
1014   if (!BiggestSuperRegRC)
1015     return None;
1016   BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
1017   std::vector<CodeGenRegisterClass *> SuperRegRCs;
1018   for (auto &RC : RegClasses)
1019     if (SuperRegRCsBV[RC.EnumValue])
1020       SuperRegRCs.emplace_back(&RC);
1021   llvm::stable_sort(SuperRegRCs, SizeOrder);
1022 
1023   assert(SuperRegRCs.front() == BiggestSuperRegRC &&
1024          "Biggest class wasn't first");
1025 
1026   // Find all the subreg classes and order them by size too.
1027   std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
1028   for (auto &RC: RegClasses) {
1029     BitVector SuperRegClassesBV(RegClasses.size());
1030     RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
1031     if (SuperRegClassesBV.any())
1032       SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
1033   }
1034   llvm::sort(SuperRegClasses,
1035              [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1036                  const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1037                return SizeOrder(A.first, B.first);
1038              });
1039 
1040   // Find the biggest subclass and subreg class such that R:subidx is in the
1041   // subreg class for all R in subclass.
1042   //
1043   // For example:
1044   // All registers in X86's GR64 have a sub_32bit subregister but no class
1045   // exists that contains all the 32-bit subregisters because GR64 contains RIP
1046   // but GR32 does not contain EIP. Instead, we constrain SuperRegRC to
1047   // GR32_with_sub_8bit (which is identical to GR32_with_sub_32bit) and then,
1048   // having excluded RIP, we are able to find a SubRegRC (GR32).
1049   CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
1050   CodeGenRegisterClass *SubRegRC = nullptr;
1051   for (auto *SuperRegRC : SuperRegRCs) {
1052     for (const auto &SuperRegClassPair : SuperRegClasses) {
1053       const BitVector &SuperRegClassBV = SuperRegClassPair.second;
1054       if (SuperRegClassBV[SuperRegRC->EnumValue]) {
1055         SubRegRC = SuperRegClassPair.first;
1056         ChosenSuperRegClass = SuperRegRC;
1057 
1058         // If SubRegRC is bigger than SuperRegRC then there are members of
1059         // SubRegRC that don't have super registers via SubIdx. Keep looking to
1060         // find a better fit and fall back on this one if there isn't one.
1061         //
1062         // This is intended to prevent X86 from making odd choices such as
1063         // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above.
1064         // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that
1065         // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
1066         // mapping.
1067         if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
1068           return std::make_pair(ChosenSuperRegClass, SubRegRC);
1069       }
1070     }
1071 
1072     // If we found a fit but it wasn't quite ideal because SubRegRC had excess
1073     // registers, then we're done.
1074     if (ChosenSuperRegClass)
1075       return std::make_pair(ChosenSuperRegClass, SubRegRC);
1076   }
1077 
1078   return None;
1079 }
1080 
getSuperRegClasses(const CodeGenSubRegIndex * SubIdx,BitVector & Out) const1081 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
1082                                               BitVector &Out) const {
1083   auto FindI = SuperRegClasses.find(SubIdx);
1084   if (FindI == SuperRegClasses.end())
1085     return;
1086   for (CodeGenRegisterClass *RC : FindI->second)
1087     Out.set(RC->EnumValue);
1088 }
1089 
1090 // Populate a unique sorted list of units from a register set.
buildRegUnitSet(const CodeGenRegBank & RegBank,std::vector<unsigned> & RegUnits) const1091 void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
1092   std::vector<unsigned> &RegUnits) const {
1093   std::vector<unsigned> TmpUnits;
1094   for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) {
1095     const RegUnit &RU = RegBank.getRegUnit(*UnitI);
1096     if (!RU.Artificial)
1097       TmpUnits.push_back(*UnitI);
1098   }
1099   llvm::sort(TmpUnits);
1100   std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
1101                    std::back_inserter(RegUnits));
1102 }
1103 
1104 //===----------------------------------------------------------------------===//
1105 //                               CodeGenRegBank
1106 //===----------------------------------------------------------------------===//
1107 
CodeGenRegBank(RecordKeeper & Records,const CodeGenHwModes & Modes)1108 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
1109                                const CodeGenHwModes &Modes) : CGH(Modes) {
1110   // Configure register Sets to understand register classes and tuples.
1111   Sets.addFieldExpander("RegisterClass", "MemberList");
1112   Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
1113   Sets.addExpander("RegisterTuples",
1114                    std::make_unique<TupleExpander>(SynthDefs));
1115 
1116   // Read in the user-defined (named) sub-register indices.
1117   // More indices will be synthesized later.
1118   std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
1119   llvm::sort(SRIs, LessRecord());
1120   for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
1121     getSubRegIdx(SRIs[i]);
1122   // Build composite maps from ComposedOf fields.
1123   for (auto &Idx : SubRegIndices)
1124     Idx.updateComponents(*this);
1125 
1126   // Read in the register definitions.
1127   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1128   llvm::sort(Regs, LessRecordRegister());
1129   // Assign the enumeration values.
1130   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1131     getReg(Regs[i]);
1132 
1133   // Expand tuples and number the new registers.
1134   std::vector<Record*> Tups =
1135     Records.getAllDerivedDefinitions("RegisterTuples");
1136 
1137   for (Record *R : Tups) {
1138     std::vector<Record *> TupRegs = *Sets.expand(R);
1139     llvm::sort(TupRegs, LessRecordRegister());
1140     for (Record *RC : TupRegs)
1141       getReg(RC);
1142   }
1143 
1144   // Now all the registers are known. Build the object graph of explicit
1145   // register-register references.
1146   for (auto &Reg : Registers)
1147     Reg.buildObjectGraph(*this);
1148 
1149   // Compute register name map.
1150   for (auto &Reg : Registers)
1151     // FIXME: This could just be RegistersByName[name] = register, except that
1152     // causes some failures in MIPS - perhaps they have duplicate register name
1153     // entries? (or maybe there's a reason for it - I don't know much about this
1154     // code, just drive-by refactoring)
1155     RegistersByName.insert(
1156         std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
1157 
1158   // Precompute all sub-register maps.
1159   // This will create Composite entries for all inferred sub-register indices.
1160   for (auto &Reg : Registers)
1161     Reg.computeSubRegs(*this);
1162 
1163   // Compute transitive closure of subregister index ConcatenationOf vectors
1164   // and initialize ConcatIdx map.
1165   for (CodeGenSubRegIndex &SRI : SubRegIndices) {
1166     SRI.computeConcatTransitiveClosure();
1167     if (!SRI.ConcatenationOf.empty())
1168       ConcatIdx.insert(std::make_pair(
1169           SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(),
1170                                              SRI.ConcatenationOf.end()), &SRI));
1171   }
1172 
1173   // Infer even more sub-registers by combining leading super-registers.
1174   for (auto &Reg : Registers)
1175     if (Reg.CoveredBySubRegs)
1176       Reg.computeSecondarySubRegs(*this);
1177 
1178   // After the sub-register graph is complete, compute the topologically
1179   // ordered SuperRegs list.
1180   for (auto &Reg : Registers)
1181     Reg.computeSuperRegs(*this);
1182 
1183   // For each pair of Reg:SR, if both are non-artificial, mark the
1184   // corresponding sub-register index as non-artificial.
1185   for (auto &Reg : Registers) {
1186     if (Reg.Artificial)
1187       continue;
1188     for (auto P : Reg.getSubRegs()) {
1189       const CodeGenRegister *SR = P.second;
1190       if (!SR->Artificial)
1191         P.first->Artificial = false;
1192     }
1193   }
1194 
1195   // Native register units are associated with a leaf register. They've all been
1196   // discovered now.
1197   NumNativeRegUnits = RegUnits.size();
1198 
1199   // Read in register class definitions.
1200   std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
1201   if (RCs.empty())
1202     PrintFatalError("No 'RegisterClass' subclasses defined!");
1203 
1204   // Allocate user-defined register classes.
1205   for (auto *R : RCs) {
1206     RegClasses.emplace_back(*this, R);
1207     CodeGenRegisterClass &RC = RegClasses.back();
1208     if (!RC.Artificial)
1209       addToMaps(&RC);
1210   }
1211 
1212   // Infer missing classes to create a full algebra.
1213   computeInferredRegisterClasses();
1214 
1215   // Order register classes topologically and assign enum values.
1216   RegClasses.sort(TopoOrderRC);
1217   unsigned i = 0;
1218   for (auto &RC : RegClasses)
1219     RC.EnumValue = i++;
1220   CodeGenRegisterClass::computeSubClasses(*this);
1221 }
1222 
1223 // Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1224 CodeGenSubRegIndex*
createSubRegIndex(StringRef Name,StringRef Namespace)1225 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1226   SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
1227   return &SubRegIndices.back();
1228 }
1229 
getSubRegIdx(Record * Def)1230 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1231   CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1232   if (Idx)
1233     return Idx;
1234   SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1);
1235   Idx = &SubRegIndices.back();
1236   return Idx;
1237 }
1238 
1239 const CodeGenSubRegIndex *
findSubRegIdx(const Record * Def) const1240 CodeGenRegBank::findSubRegIdx(const Record* Def) const {
1241   auto I = Def2SubRegIdx.find(Def);
1242   return (I == Def2SubRegIdx.end()) ? nullptr : I->second;
1243 }
1244 
getReg(Record * Def)1245 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1246   CodeGenRegister *&Reg = Def2Reg[Def];
1247   if (Reg)
1248     return Reg;
1249   Registers.emplace_back(Def, Registers.size() + 1);
1250   Reg = &Registers.back();
1251   return Reg;
1252 }
1253 
addToMaps(CodeGenRegisterClass * RC)1254 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1255   if (Record *Def = RC->getDef())
1256     Def2RC.insert(std::make_pair(Def, RC));
1257 
1258   // Duplicate classes are rejected by insert().
1259   // That's OK, we only care about the properties handled by CGRC::Key.
1260   CodeGenRegisterClass::Key K(*RC);
1261   Key2RC.insert(std::make_pair(K, RC));
1262 }
1263 
1264 // Create a synthetic sub-class if it is missing.
1265 CodeGenRegisterClass*
getOrCreateSubClass(const CodeGenRegisterClass * RC,const CodeGenRegister::Vec * Members,StringRef Name)1266 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1267                                     const CodeGenRegister::Vec *Members,
1268                                     StringRef Name) {
1269   // Synthetic sub-class has the same size and alignment as RC.
1270   CodeGenRegisterClass::Key K(Members, RC->RSI);
1271   RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1272   if (FoundI != Key2RC.end())
1273     return FoundI->second;
1274 
1275   // Sub-class doesn't exist, create a new one.
1276   RegClasses.emplace_back(*this, Name, K);
1277   addToMaps(&RegClasses.back());
1278   return &RegClasses.back();
1279 }
1280 
getRegClass(const Record * Def) const1281 CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
1282   if (CodeGenRegisterClass *RC = Def2RC.lookup(Def))
1283     return RC;
1284 
1285   PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1286 }
1287 
1288 CodeGenSubRegIndex*
getCompositeSubRegIndex(CodeGenSubRegIndex * A,CodeGenSubRegIndex * B)1289 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1290                                         CodeGenSubRegIndex *B) {
1291   // Look for an existing entry.
1292   CodeGenSubRegIndex *Comp = A->compose(B);
1293   if (Comp)
1294     return Comp;
1295 
1296   // None exists, synthesize one.
1297   std::string Name = A->getName() + "_then_" + B->getName();
1298   Comp = createSubRegIndex(Name, A->getNamespace());
1299   A->addComposite(B, Comp);
1300   return Comp;
1301 }
1302 
1303 CodeGenSubRegIndex *CodeGenRegBank::
getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *,8> & Parts)1304 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
1305   assert(Parts.size() > 1 && "Need two parts to concatenate");
1306 #ifndef NDEBUG
1307   for (CodeGenSubRegIndex *Idx : Parts) {
1308     assert(Idx->ConcatenationOf.empty() && "No transitive closure?");
1309   }
1310 #endif
1311 
1312   // Look for an existing entry.
1313   CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1314   if (Idx)
1315     return Idx;
1316 
1317   // None exists, synthesize one.
1318   std::string Name = Parts.front()->getName();
1319   // Determine whether all parts are contiguous.
1320   bool isContinuous = true;
1321   unsigned Size = Parts.front()->Size;
1322   unsigned LastOffset = Parts.front()->Offset;
1323   unsigned LastSize = Parts.front()->Size;
1324   for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1325     Name += '_';
1326     Name += Parts[i]->getName();
1327     Size += Parts[i]->Size;
1328     if (Parts[i]->Offset != (LastOffset + LastSize))
1329       isContinuous = false;
1330     LastOffset = Parts[i]->Offset;
1331     LastSize = Parts[i]->Size;
1332   }
1333   Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1334   Idx->Size = Size;
1335   Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
1336   Idx->ConcatenationOf.assign(Parts.begin(), Parts.end());
1337   return Idx;
1338 }
1339 
computeComposites()1340 void CodeGenRegBank::computeComposites() {
1341   using RegMap = std::map<const CodeGenRegister*, const CodeGenRegister*>;
1342 
1343   // Subreg -> { Reg->Reg }, where the right-hand side is the mapping from
1344   // register to (sub)register associated with the action of the left-hand
1345   // side subregister.
1346   std::map<const CodeGenSubRegIndex*, RegMap> SubRegAction;
1347   for (const CodeGenRegister &R : Registers) {
1348     const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
1349     for (std::pair<const CodeGenSubRegIndex*, const CodeGenRegister*> P : SM)
1350       SubRegAction[P.first].insert({&R, P.second});
1351   }
1352 
1353   // Calculate the composition of two subregisters as compositions of their
1354   // associated actions.
1355   auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1,
1356                                   const CodeGenSubRegIndex *Sub2) {
1357     RegMap C;
1358     const RegMap &Img1 = SubRegAction.at(Sub1);
1359     const RegMap &Img2 = SubRegAction.at(Sub2);
1360     for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Img1) {
1361       auto F = Img2.find(P.second);
1362       if (F != Img2.end())
1363         C.insert({P.first, F->second});
1364     }
1365     return C;
1366   };
1367 
1368   // Check if the two maps agree on the intersection of their domains.
1369   auto agree = [] (const RegMap &Map1, const RegMap &Map2) {
1370     // Technically speaking, an empty map agrees with any other map, but
1371     // this could flag false positives. We're interested in non-vacuous
1372     // agreements.
1373     if (Map1.empty() || Map2.empty())
1374       return false;
1375     for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Map1) {
1376       auto F = Map2.find(P.first);
1377       if (F == Map2.end() || P.second != F->second)
1378         return false;
1379     }
1380     return true;
1381   };
1382 
1383   using CompositePair = std::pair<const CodeGenSubRegIndex*,
1384                                   const CodeGenSubRegIndex*>;
1385   SmallSet<CompositePair,4> UserDefined;
1386   for (const CodeGenSubRegIndex &Idx : SubRegIndices)
1387     for (auto P : Idx.getComposites())
1388       UserDefined.insert(std::make_pair(&Idx, P.first));
1389 
1390   // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1391   // and many registers will share TopoSigs on regular architectures.
1392   BitVector TopoSigs(getNumTopoSigs());
1393 
1394   for (const auto &Reg1 : Registers) {
1395     // Skip identical subreg structures already processed.
1396     if (TopoSigs.test(Reg1.getTopoSig()))
1397       continue;
1398     TopoSigs.set(Reg1.getTopoSig());
1399 
1400     const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1401     for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1402          e1 = SRM1.end(); i1 != e1; ++i1) {
1403       CodeGenSubRegIndex *Idx1 = i1->first;
1404       CodeGenRegister *Reg2 = i1->second;
1405       // Ignore identity compositions.
1406       if (&Reg1 == Reg2)
1407         continue;
1408       const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1409       // Try composing Idx1 with another SubRegIndex.
1410       for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1411            e2 = SRM2.end(); i2 != e2; ++i2) {
1412         CodeGenSubRegIndex *Idx2 = i2->first;
1413         CodeGenRegister *Reg3 = i2->second;
1414         // Ignore identity compositions.
1415         if (Reg2 == Reg3)
1416           continue;
1417         // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1418         CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
1419         assert(Idx3 && "Sub-register doesn't have an index");
1420 
1421         // Conflicting composition? Emit a warning but allow it.
1422         if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) {
1423           // If the composition was not user-defined, always emit a warning.
1424           if (!UserDefined.count({Idx1, Idx2}) ||
1425               agree(compose(Idx1, Idx2), SubRegAction.at(Idx3)))
1426             PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1427                          " and " + Idx2->getQualifiedName() +
1428                          " compose ambiguously as " + Prev->getQualifiedName() +
1429                          " or " + Idx3->getQualifiedName());
1430         }
1431       }
1432     }
1433   }
1434 }
1435 
1436 // Compute lane masks. This is similar to register units, but at the
1437 // sub-register index level. Each bit in the lane mask is like a register unit
1438 // class, and two lane masks will have a bit in common if two sub-register
1439 // indices overlap in some register.
1440 //
1441 // Conservatively share a lane mask bit if two sub-register indices overlap in
1442 // some registers, but not in others. That shouldn't happen a lot.
computeSubRegLaneMasks()1443 void CodeGenRegBank::computeSubRegLaneMasks() {
1444   // First assign individual bits to all the leaf indices.
1445   unsigned Bit = 0;
1446   // Determine mask of lanes that cover their registers.
1447   CoveringLanes = LaneBitmask::getAll();
1448   for (auto &Idx : SubRegIndices) {
1449     if (Idx.getComposites().empty()) {
1450       if (Bit > LaneBitmask::BitWidth) {
1451         PrintFatalError(
1452           Twine("Ran out of lanemask bits to represent subregister ")
1453           + Idx.getName());
1454       }
1455       Idx.LaneMask = LaneBitmask::getLane(Bit);
1456       ++Bit;
1457     } else {
1458       Idx.LaneMask = LaneBitmask::getNone();
1459     }
1460   }
1461 
1462   // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1463   // here is that for each possible target subregister we look at the leafs
1464   // in the subregister graph that compose for this target and create
1465   // transformation sequences for the lanemasks. Each step in the sequence
1466   // consists of a bitmask and a bitrotate operation. As the rotation amounts
1467   // are usually the same for many subregisters we can easily combine the steps
1468   // by combining the masks.
1469   for (const auto &Idx : SubRegIndices) {
1470     const auto &Composites = Idx.getComposites();
1471     auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1472 
1473     if (Composites.empty()) {
1474       // Moving from a class with no subregisters we just had a single lane:
1475       // The subregister must be a leaf subregister and only occupies 1 bit.
1476       // Move the bit from the class without subregisters into that position.
1477       unsigned DstBit = Idx.LaneMask.getHighestLane();
1478       assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
1479              "Must be a leaf subregister");
1480       MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
1481       LaneTransforms.push_back(MaskRol);
1482     } else {
1483       // Go through all leaf subregisters and find the ones that compose with
1484       // Idx. These make out all possible valid bits in the lane mask we want to
1485       // transform. Looking only at the leafs ensure that only a single bit in
1486       // the mask is set.
1487       unsigned NextBit = 0;
1488       for (auto &Idx2 : SubRegIndices) {
1489         // Skip non-leaf subregisters.
1490         if (!Idx2.getComposites().empty())
1491           continue;
1492         // Replicate the behaviour from the lane mask generation loop above.
1493         unsigned SrcBit = NextBit;
1494         LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
1495         if (NextBit < LaneBitmask::BitWidth-1)
1496           ++NextBit;
1497         assert(Idx2.LaneMask == SrcMask);
1498 
1499         // Get the composed subregister if there is any.
1500         auto C = Composites.find(&Idx2);
1501         if (C == Composites.end())
1502           continue;
1503         const CodeGenSubRegIndex *Composite = C->second;
1504         // The Composed subreg should be a leaf subreg too
1505         assert(Composite->getComposites().empty());
1506 
1507         // Create Mask+Rotate operation and merge with existing ops if possible.
1508         unsigned DstBit = Composite->LaneMask.getHighestLane();
1509         int Shift = DstBit - SrcBit;
1510         uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
1511                                         : LaneBitmask::BitWidth + Shift;
1512         for (auto &I : LaneTransforms) {
1513           if (I.RotateLeft == RotateLeft) {
1514             I.Mask |= SrcMask;
1515             SrcMask = LaneBitmask::getNone();
1516           }
1517         }
1518         if (SrcMask.any()) {
1519           MaskRolPair MaskRol = { SrcMask, RotateLeft };
1520           LaneTransforms.push_back(MaskRol);
1521         }
1522       }
1523     }
1524 
1525     // Optimize if the transformation consists of one step only: Set mask to
1526     // 0xffffffff (including some irrelevant invalid bits) so that it should
1527     // merge with more entries later while compressing the table.
1528     if (LaneTransforms.size() == 1)
1529       LaneTransforms[0].Mask = LaneBitmask::getAll();
1530 
1531     // Further compression optimization: For invalid compositions resulting
1532     // in a sequence with 0 entries we can just pick any other. Choose
1533     // Mask 0xffffffff with Rotation 0.
1534     if (LaneTransforms.size() == 0) {
1535       MaskRolPair P = { LaneBitmask::getAll(), 0 };
1536       LaneTransforms.push_back(P);
1537     }
1538   }
1539 
1540   // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1541   // by the sub-register graph? This doesn't occur in any known targets.
1542 
1543   // Inherit lanes from composites.
1544   for (const auto &Idx : SubRegIndices) {
1545     LaneBitmask Mask = Idx.computeLaneMask();
1546     // If some super-registers without CoveredBySubRegs use this index, we can
1547     // no longer assume that the lanes are covering their registers.
1548     if (!Idx.AllSuperRegsCovered)
1549       CoveringLanes &= ~Mask;
1550   }
1551 
1552   // Compute lane mask combinations for register classes.
1553   for (auto &RegClass : RegClasses) {
1554     LaneBitmask LaneMask;
1555     for (const auto &SubRegIndex : SubRegIndices) {
1556       if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1557         continue;
1558       LaneMask |= SubRegIndex.LaneMask;
1559     }
1560 
1561     // For classes without any subregisters set LaneMask to 1 instead of 0.
1562     // This makes it easier for client code to handle classes uniformly.
1563     if (LaneMask.none())
1564       LaneMask = LaneBitmask::getLane(0);
1565 
1566     RegClass.LaneMask = LaneMask;
1567   }
1568 }
1569 
1570 namespace {
1571 
1572 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1573 // the transitive closure of the union of overlapping register
1574 // classes. Together, the UberRegSets form a partition of the registers. If we
1575 // consider overlapping register classes to be connected, then each UberRegSet
1576 // is a set of connected components.
1577 //
1578 // An UberRegSet will likely be a horizontal slice of register names of
1579 // the same width. Nontrivial subregisters should then be in a separate
1580 // UberRegSet. But this property isn't required for valid computation of
1581 // register unit weights.
1582 //
1583 // A Weight field caches the max per-register unit weight in each UberRegSet.
1584 //
1585 // A set of SingularDeterminants flags single units of some register in this set
1586 // for which the unit weight equals the set weight. These units should not have
1587 // their weight increased.
1588 struct UberRegSet {
1589   CodeGenRegister::Vec Regs;
1590   unsigned Weight = 0;
1591   CodeGenRegister::RegUnitList SingularDeterminants;
1592 
1593   UberRegSet() = default;
1594 };
1595 
1596 } // end anonymous namespace
1597 
1598 // Partition registers into UberRegSets, where each set is the transitive
1599 // closure of the union of overlapping register classes.
1600 //
1601 // UberRegSets[0] is a special non-allocatable set.
computeUberSets(std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,CodeGenRegBank & RegBank)1602 static void computeUberSets(std::vector<UberRegSet> &UberSets,
1603                             std::vector<UberRegSet*> &RegSets,
1604                             CodeGenRegBank &RegBank) {
1605   const auto &Registers = RegBank.getRegisters();
1606 
1607   // The Register EnumValue is one greater than its index into Registers.
1608   assert(Registers.size() == Registers.back().EnumValue &&
1609          "register enum value mismatch");
1610 
1611   // For simplicitly make the SetID the same as EnumValue.
1612   IntEqClasses UberSetIDs(Registers.size()+1);
1613   std::set<unsigned> AllocatableRegs;
1614   for (auto &RegClass : RegBank.getRegClasses()) {
1615     if (!RegClass.Allocatable)
1616       continue;
1617 
1618     const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1619     if (Regs.empty())
1620       continue;
1621 
1622     unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1623     assert(USetID && "register number 0 is invalid");
1624 
1625     AllocatableRegs.insert((*Regs.begin())->EnumValue);
1626     for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1627       AllocatableRegs.insert((*I)->EnumValue);
1628       UberSetIDs.join(USetID, (*I)->EnumValue);
1629     }
1630   }
1631   // Combine non-allocatable regs.
1632   for (const auto &Reg : Registers) {
1633     unsigned RegNum = Reg.EnumValue;
1634     if (AllocatableRegs.count(RegNum))
1635       continue;
1636 
1637     UberSetIDs.join(0, RegNum);
1638   }
1639   UberSetIDs.compress();
1640 
1641   // Make the first UberSet a special unallocatable set.
1642   unsigned ZeroID = UberSetIDs[0];
1643 
1644   // Insert Registers into the UberSets formed by union-find.
1645   // Do not resize after this.
1646   UberSets.resize(UberSetIDs.getNumClasses());
1647   unsigned i = 0;
1648   for (const CodeGenRegister &Reg : Registers) {
1649     unsigned USetID = UberSetIDs[Reg.EnumValue];
1650     if (!USetID)
1651       USetID = ZeroID;
1652     else if (USetID == ZeroID)
1653       USetID = 0;
1654 
1655     UberRegSet *USet = &UberSets[USetID];
1656     USet->Regs.push_back(&Reg);
1657     sortAndUniqueRegisters(USet->Regs);
1658     RegSets[i++] = USet;
1659   }
1660 }
1661 
1662 // Recompute each UberSet weight after changing unit weights.
computeUberWeights(std::vector<UberRegSet> & UberSets,CodeGenRegBank & RegBank)1663 static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1664                                CodeGenRegBank &RegBank) {
1665   // Skip the first unallocatable set.
1666   for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
1667          E = UberSets.end(); I != E; ++I) {
1668 
1669     // Initialize all unit weights in this set, and remember the max units/reg.
1670     const CodeGenRegister *Reg = nullptr;
1671     unsigned MaxWeight = 0, Weight = 0;
1672     for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1673       if (Reg != UnitI.getReg()) {
1674         if (Weight > MaxWeight)
1675           MaxWeight = Weight;
1676         Reg = UnitI.getReg();
1677         Weight = 0;
1678       }
1679       if (!RegBank.getRegUnit(*UnitI).Artificial) {
1680         unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1681         if (!UWeight) {
1682           UWeight = 1;
1683           RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1684         }
1685         Weight += UWeight;
1686       }
1687     }
1688     if (Weight > MaxWeight)
1689       MaxWeight = Weight;
1690     if (I->Weight != MaxWeight) {
1691       LLVM_DEBUG(dbgs() << "UberSet " << I - UberSets.begin() << " Weight "
1692                         << MaxWeight;
1693                  for (auto &Unit
1694                       : I->Regs) dbgs()
1695                  << " " << Unit->getName();
1696                  dbgs() << "\n");
1697       // Update the set weight.
1698       I->Weight = MaxWeight;
1699     }
1700 
1701     // Find singular determinants.
1702     for (const auto R : I->Regs) {
1703       if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) {
1704         I->SingularDeterminants |= R->getRegUnits();
1705       }
1706     }
1707   }
1708 }
1709 
1710 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1711 // a register and its subregisters so that they have the same weight as their
1712 // UberSet. Self-recursion processes the subregister tree in postorder so
1713 // subregisters are normalized first.
1714 //
1715 // Side effects:
1716 // - creates new adopted register units
1717 // - causes superregisters to inherit adopted units
1718 // - increases the weight of "singular" units
1719 // - induces recomputation of UberWeights.
normalizeWeight(CodeGenRegister * Reg,std::vector<UberRegSet> & UberSets,std::vector<UberRegSet * > & RegSets,BitVector & NormalRegs,CodeGenRegister::RegUnitList & NormalUnits,CodeGenRegBank & RegBank)1720 static bool normalizeWeight(CodeGenRegister *Reg,
1721                             std::vector<UberRegSet> &UberSets,
1722                             std::vector<UberRegSet*> &RegSets,
1723                             BitVector &NormalRegs,
1724                             CodeGenRegister::RegUnitList &NormalUnits,
1725                             CodeGenRegBank &RegBank) {
1726   NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size()));
1727   if (NormalRegs.test(Reg->EnumValue))
1728     return false;
1729   NormalRegs.set(Reg->EnumValue);
1730 
1731   bool Changed = false;
1732   const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1733   for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1734          SRE = SRM.end(); SRI != SRE; ++SRI) {
1735     if (SRI->second == Reg)
1736       continue; // self-cycles happen
1737 
1738     Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1739                                NormalRegs, NormalUnits, RegBank);
1740   }
1741   // Postorder register normalization.
1742 
1743   // Inherit register units newly adopted by subregisters.
1744   if (Reg->inheritRegUnits(RegBank))
1745     computeUberWeights(UberSets, RegBank);
1746 
1747   // Check if this register is too skinny for its UberRegSet.
1748   UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1749 
1750   unsigned RegWeight = Reg->getWeight(RegBank);
1751   if (UberSet->Weight > RegWeight) {
1752     // A register unit's weight can be adjusted only if it is the singular unit
1753     // for this register, has not been used to normalize a subregister's set,
1754     // and has not already been used to singularly determine this UberRegSet.
1755     unsigned AdjustUnit = *Reg->getRegUnits().begin();
1756     if (Reg->getRegUnits().count() != 1
1757         || hasRegUnit(NormalUnits, AdjustUnit)
1758         || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1759       // We don't have an adjustable unit, so adopt a new one.
1760       AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1761       Reg->adoptRegUnit(AdjustUnit);
1762       // Adopting a unit does not immediately require recomputing set weights.
1763     }
1764     else {
1765       // Adjust the existing single unit.
1766       if (!RegBank.getRegUnit(AdjustUnit).Artificial)
1767         RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1768       // The unit may be shared among sets and registers within this set.
1769       computeUberWeights(UberSets, RegBank);
1770     }
1771     Changed = true;
1772   }
1773 
1774   // Mark these units normalized so superregisters can't change their weights.
1775   NormalUnits |= Reg->getRegUnits();
1776 
1777   return Changed;
1778 }
1779 
1780 // Compute a weight for each register unit created during getSubRegs.
1781 //
1782 // The goal is that two registers in the same class will have the same weight,
1783 // where each register's weight is defined as sum of its units' weights.
computeRegUnitWeights()1784 void CodeGenRegBank::computeRegUnitWeights() {
1785   std::vector<UberRegSet> UberSets;
1786   std::vector<UberRegSet*> RegSets(Registers.size());
1787   computeUberSets(UberSets, RegSets, *this);
1788   // UberSets and RegSets are now immutable.
1789 
1790   computeUberWeights(UberSets, *this);
1791 
1792   // Iterate over each Register, normalizing the unit weights until reaching
1793   // a fix point.
1794   unsigned NumIters = 0;
1795   for (bool Changed = true; Changed; ++NumIters) {
1796     assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
1797     Changed = false;
1798     for (auto &Reg : Registers) {
1799       CodeGenRegister::RegUnitList NormalUnits;
1800       BitVector NormalRegs;
1801       Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
1802                                  NormalUnits, *this);
1803     }
1804   }
1805 }
1806 
1807 // Find a set in UniqueSets with the same elements as Set.
1808 // Return an iterator into UniqueSets.
1809 static std::vector<RegUnitSet>::const_iterator
findRegUnitSet(const std::vector<RegUnitSet> & UniqueSets,const RegUnitSet & Set)1810 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1811                const RegUnitSet &Set) {
1812   std::vector<RegUnitSet>::const_iterator
1813     I = UniqueSets.begin(), E = UniqueSets.end();
1814   for(;I != E; ++I) {
1815     if (I->Units == Set.Units)
1816       break;
1817   }
1818   return I;
1819 }
1820 
1821 // Return true if the RUSubSet is a subset of RUSuperSet.
isRegUnitSubSet(const std::vector<unsigned> & RUSubSet,const std::vector<unsigned> & RUSuperSet)1822 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1823                             const std::vector<unsigned> &RUSuperSet) {
1824   return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1825                        RUSubSet.begin(), RUSubSet.end());
1826 }
1827 
1828 /// Iteratively prune unit sets. Prune subsets that are close to the superset,
1829 /// but with one or two registers removed. We occasionally have registers like
1830 /// APSR and PC thrown in with the general registers. We also see many
1831 /// special-purpose register subsets, such as tail-call and Thumb
1832 /// encodings. Generating all possible overlapping sets is combinatorial and
1833 /// overkill for modeling pressure. Ideally we could fix this statically in
1834 /// tablegen by (1) having the target define register classes that only include
1835 /// the allocatable registers and marking other classes as non-allocatable and
1836 /// (2) having a way to mark special purpose classes as "don't-care" classes for
1837 /// the purpose of pressure.  However, we make an attempt to handle targets that
1838 /// are not nicely defined by merging nearly identical register unit sets
1839 /// statically. This generates smaller tables. Then, dynamically, we adjust the
1840 /// set limit by filtering the reserved registers.
1841 ///
1842 /// Merge sets only if the units have the same weight. For example, on ARM,
1843 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1844 /// should not expand the S set to include D regs.
pruneUnitSets()1845 void CodeGenRegBank::pruneUnitSets() {
1846   assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
1847 
1848   // Form an equivalence class of UnitSets with no significant difference.
1849   std::vector<unsigned> SuperSetIDs;
1850   for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1851        SubIdx != EndIdx; ++SubIdx) {
1852     const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1853     unsigned SuperIdx = 0;
1854     for (; SuperIdx != EndIdx; ++SuperIdx) {
1855       if (SuperIdx == SubIdx)
1856         continue;
1857 
1858       unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
1859       const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1860       if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1861           && (SubSet.Units.size() + 3 > SuperSet.Units.size())
1862           && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
1863           && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
1864         LLVM_DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
1865                           << "\n");
1866         // We can pick any of the set names for the merged set. Go for the
1867         // shortest one to avoid picking the name of one of the classes that are
1868         // artificially created by tablegen. So "FPR128_lo" instead of
1869         // "QQQQ_with_qsub3_in_FPR128_lo".
1870         if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
1871           RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
1872         break;
1873       }
1874     }
1875     if (SuperIdx == EndIdx)
1876       SuperSetIDs.push_back(SubIdx);
1877   }
1878   // Populate PrunedUnitSets with each equivalence class's superset.
1879   std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1880   for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1881     unsigned SuperIdx = SuperSetIDs[i];
1882     PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1883     PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1884   }
1885   RegUnitSets.swap(PrunedUnitSets);
1886 }
1887 
1888 // Create a RegUnitSet for each RegClass that contains all units in the class
1889 // including adopted units that are necessary to model register pressure. Then
1890 // iteratively compute RegUnitSets such that the union of any two overlapping
1891 // RegUnitSets is repreresented.
1892 //
1893 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1894 // RegUnitSet that is a superset of that RegUnitClass.
computeRegUnitSets()1895 void CodeGenRegBank::computeRegUnitSets() {
1896   assert(RegUnitSets.empty() && "dirty RegUnitSets");
1897 
1898   // Compute a unique RegUnitSet for each RegClass.
1899   auto &RegClasses = getRegClasses();
1900   for (auto &RC : RegClasses) {
1901     if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet)
1902       continue;
1903 
1904     // Speculatively grow the RegUnitSets to hold the new set.
1905     RegUnitSets.resize(RegUnitSets.size() + 1);
1906     RegUnitSets.back().Name = RC.getName();
1907 
1908     // Compute a sorted list of units in this class.
1909     RC.buildRegUnitSet(*this, RegUnitSets.back().Units);
1910 
1911     // Find an existing RegUnitSet.
1912     std::vector<RegUnitSet>::const_iterator SetI =
1913       findRegUnitSet(RegUnitSets, RegUnitSets.back());
1914     if (SetI != std::prev(RegUnitSets.end()))
1915       RegUnitSets.pop_back();
1916   }
1917 
1918   LLVM_DEBUG(dbgs() << "\nBefore pruning:\n"; for (unsigned USIdx = 0,
1919                                                    USEnd = RegUnitSets.size();
1920                                                    USIdx < USEnd; ++USIdx) {
1921     dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1922     for (auto &U : RegUnitSets[USIdx].Units)
1923       printRegUnitName(U);
1924     dbgs() << "\n";
1925   });
1926 
1927   // Iteratively prune unit sets.
1928   pruneUnitSets();
1929 
1930   LLVM_DEBUG(dbgs() << "\nBefore union:\n"; for (unsigned USIdx = 0,
1931                                                  USEnd = RegUnitSets.size();
1932                                                  USIdx < USEnd; ++USIdx) {
1933     dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1934     for (auto &U : RegUnitSets[USIdx].Units)
1935       printRegUnitName(U);
1936     dbgs() << "\n";
1937   } dbgs() << "\nUnion sets:\n");
1938 
1939   // Iterate over all unit sets, including new ones added by this loop.
1940   unsigned NumRegUnitSubSets = RegUnitSets.size();
1941   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1942     // In theory, this is combinatorial. In practice, it needs to be bounded
1943     // by a small number of sets for regpressure to be efficient.
1944     // If the assert is hit, we need to implement pruning.
1945     assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
1946 
1947     // Compare new sets with all original classes.
1948     for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1949          SearchIdx != EndIdx; ++SearchIdx) {
1950       std::set<unsigned> Intersection;
1951       std::set_intersection(RegUnitSets[Idx].Units.begin(),
1952                             RegUnitSets[Idx].Units.end(),
1953                             RegUnitSets[SearchIdx].Units.begin(),
1954                             RegUnitSets[SearchIdx].Units.end(),
1955                             std::inserter(Intersection, Intersection.begin()));
1956       if (Intersection.empty())
1957         continue;
1958 
1959       // Speculatively grow the RegUnitSets to hold the new set.
1960       RegUnitSets.resize(RegUnitSets.size() + 1);
1961       RegUnitSets.back().Name =
1962         RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name;
1963 
1964       std::set_union(RegUnitSets[Idx].Units.begin(),
1965                      RegUnitSets[Idx].Units.end(),
1966                      RegUnitSets[SearchIdx].Units.begin(),
1967                      RegUnitSets[SearchIdx].Units.end(),
1968                      std::inserter(RegUnitSets.back().Units,
1969                                    RegUnitSets.back().Units.begin()));
1970 
1971       // Find an existing RegUnitSet, or add the union to the unique sets.
1972       std::vector<RegUnitSet>::const_iterator SetI =
1973         findRegUnitSet(RegUnitSets, RegUnitSets.back());
1974       if (SetI != std::prev(RegUnitSets.end()))
1975         RegUnitSets.pop_back();
1976       else {
1977         LLVM_DEBUG(dbgs() << "UnitSet " << RegUnitSets.size() - 1 << " "
1978                           << RegUnitSets.back().Name << ":";
1979                    for (auto &U
1980                         : RegUnitSets.back().Units) printRegUnitName(U);
1981                    dbgs() << "\n";);
1982       }
1983     }
1984   }
1985 
1986   // Iteratively prune unit sets after inferring supersets.
1987   pruneUnitSets();
1988 
1989   LLVM_DEBUG(
1990       dbgs() << "\n"; for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
1991                            USIdx < USEnd; ++USIdx) {
1992         dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";
1993         for (auto &U : RegUnitSets[USIdx].Units)
1994           printRegUnitName(U);
1995         dbgs() << "\n";
1996       });
1997 
1998   // For each register class, list the UnitSets that are supersets.
1999   RegClassUnitSets.resize(RegClasses.size());
2000   int RCIdx = -1;
2001   for (auto &RC : RegClasses) {
2002     ++RCIdx;
2003     if (!RC.Allocatable)
2004       continue;
2005 
2006     // Recompute the sorted list of units in this class.
2007     std::vector<unsigned> RCRegUnits;
2008     RC.buildRegUnitSet(*this, RCRegUnits);
2009 
2010     // Don't increase pressure for unallocatable regclasses.
2011     if (RCRegUnits.empty())
2012       continue;
2013 
2014     LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n";
2015                for (auto U
2016                     : RCRegUnits) printRegUnitName(U);
2017                dbgs() << "\n  UnitSetIDs:");
2018 
2019     // Find all supersets.
2020     for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
2021          USIdx != USEnd; ++USIdx) {
2022       if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
2023         LLVM_DEBUG(dbgs() << " " << USIdx);
2024         RegClassUnitSets[RCIdx].push_back(USIdx);
2025       }
2026     }
2027     LLVM_DEBUG(dbgs() << "\n");
2028     assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
2029   }
2030 
2031   // For each register unit, ensure that we have the list of UnitSets that
2032   // contain the unit. Normally, this matches an existing list of UnitSets for a
2033   // register class. If not, we create a new entry in RegClassUnitSets as a
2034   // "fake" register class.
2035   for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
2036        UnitIdx < UnitEnd; ++UnitIdx) {
2037     std::vector<unsigned> RUSets;
2038     for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
2039       RegUnitSet &RUSet = RegUnitSets[i];
2040       if (!is_contained(RUSet.Units, UnitIdx))
2041         continue;
2042       RUSets.push_back(i);
2043     }
2044     unsigned RCUnitSetsIdx = 0;
2045     for (unsigned e = RegClassUnitSets.size();
2046          RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
2047       if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
2048         break;
2049       }
2050     }
2051     RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
2052     if (RCUnitSetsIdx == RegClassUnitSets.size()) {
2053       // Create a new list of UnitSets as a "fake" register class.
2054       RegClassUnitSets.resize(RCUnitSetsIdx + 1);
2055       RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
2056     }
2057   }
2058 }
2059 
computeRegUnitLaneMasks()2060 void CodeGenRegBank::computeRegUnitLaneMasks() {
2061   for (auto &Register : Registers) {
2062     // Create an initial lane mask for all register units.
2063     const auto &RegUnits = Register.getRegUnits();
2064     CodeGenRegister::RegUnitLaneMaskList
2065         RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
2066     // Iterate through SubRegisters.
2067     typedef CodeGenRegister::SubRegMap SubRegMap;
2068     const SubRegMap &SubRegs = Register.getSubRegs();
2069     for (SubRegMap::const_iterator S = SubRegs.begin(),
2070          SE = SubRegs.end(); S != SE; ++S) {
2071       CodeGenRegister *SubReg = S->second;
2072       // Ignore non-leaf subregisters, their lane masks are fully covered by
2073       // the leaf subregisters anyway.
2074       if (!SubReg->getSubRegs().empty())
2075         continue;
2076       CodeGenSubRegIndex *SubRegIndex = S->first;
2077       const CodeGenRegister *SubRegister = S->second;
2078       LaneBitmask LaneMask = SubRegIndex->LaneMask;
2079       // Distribute LaneMask to Register Units touched.
2080       for (unsigned SUI : SubRegister->getRegUnits()) {
2081         bool Found = false;
2082         unsigned u = 0;
2083         for (unsigned RU : RegUnits) {
2084           if (SUI == RU) {
2085             RegUnitLaneMasks[u] |= LaneMask;
2086             assert(!Found);
2087             Found = true;
2088           }
2089           ++u;
2090         }
2091         (void)Found;
2092         assert(Found);
2093       }
2094     }
2095     Register.setRegUnitLaneMasks(RegUnitLaneMasks);
2096   }
2097 }
2098 
computeDerivedInfo()2099 void CodeGenRegBank::computeDerivedInfo() {
2100   computeComposites();
2101   computeSubRegLaneMasks();
2102 
2103   // Compute a weight for each register unit created during getSubRegs.
2104   // This may create adopted register units (with unit # >= NumNativeRegUnits).
2105   computeRegUnitWeights();
2106 
2107   // Compute a unique set of RegUnitSets. One for each RegClass and inferred
2108   // supersets for the union of overlapping sets.
2109   computeRegUnitSets();
2110 
2111   computeRegUnitLaneMasks();
2112 
2113   // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
2114   for (CodeGenRegisterClass &RC : RegClasses) {
2115     RC.HasDisjunctSubRegs = false;
2116     RC.CoveredBySubRegs = true;
2117     for (const CodeGenRegister *Reg : RC.getMembers()) {
2118       RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
2119       RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
2120     }
2121   }
2122 
2123   // Get the weight of each set.
2124   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2125     RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units);
2126 
2127   // Find the order of each set.
2128   RegUnitSetOrder.reserve(RegUnitSets.size());
2129   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2130     RegUnitSetOrder.push_back(Idx);
2131 
2132   llvm::stable_sort(RegUnitSetOrder, [this](unsigned ID1, unsigned ID2) {
2133     return getRegPressureSet(ID1).Units.size() <
2134            getRegPressureSet(ID2).Units.size();
2135   });
2136   for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
2137     RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
2138   }
2139 }
2140 
2141 //
2142 // Synthesize missing register class intersections.
2143 //
2144 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
2145 // returns a maximal register class for all X.
2146 //
inferCommonSubClass(CodeGenRegisterClass * RC)2147 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
2148   assert(!RegClasses.empty());
2149   // Stash the iterator to the last element so that this loop doesn't visit
2150   // elements added by the getOrCreateSubClass call within it.
2151   for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end());
2152        I != std::next(E); ++I) {
2153     CodeGenRegisterClass *RC1 = RC;
2154     CodeGenRegisterClass *RC2 = &*I;
2155     if (RC1 == RC2)
2156       continue;
2157 
2158     // Compute the set intersection of RC1 and RC2.
2159     const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
2160     const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
2161     CodeGenRegister::Vec Intersection;
2162     std::set_intersection(Memb1.begin(), Memb1.end(), Memb2.begin(),
2163                           Memb2.end(),
2164                           std::inserter(Intersection, Intersection.begin()),
2165                           deref<std::less<>>());
2166 
2167     // Skip disjoint class pairs.
2168     if (Intersection.empty())
2169       continue;
2170 
2171     // If RC1 and RC2 have different spill sizes or alignments, use the
2172     // stricter one for sub-classing.  If they are equal, prefer RC1.
2173     if (RC2->RSI.hasStricterSpillThan(RC1->RSI))
2174       std::swap(RC1, RC2);
2175 
2176     getOrCreateSubClass(RC1, &Intersection,
2177                         RC1->getName() + "_and_" + RC2->getName());
2178   }
2179 }
2180 
2181 //
2182 // Synthesize missing sub-classes for getSubClassWithSubReg().
2183 //
2184 // Make sure that the set of registers in RC with a given SubIdx sub-register
2185 // form a register class.  Update RC->SubClassWithSubReg.
2186 //
inferSubClassWithSubReg(CodeGenRegisterClass * RC)2187 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
2188   // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
2189   typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
2190                    deref<std::less<>>>
2191       SubReg2SetMap;
2192 
2193   // Compute the set of registers supporting each SubRegIndex.
2194   SubReg2SetMap SRSets;
2195   for (const auto R : RC->getMembers()) {
2196     if (R->Artificial)
2197       continue;
2198     const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
2199     for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2200          E = SRM.end(); I != E; ++I) {
2201       if (!I->first->Artificial)
2202         SRSets[I->first].push_back(R);
2203     }
2204   }
2205 
2206   for (auto I : SRSets)
2207     sortAndUniqueRegisters(I.second);
2208 
2209   // Find matching classes for all SRSets entries.  Iterate in SubRegIndex
2210   // numerical order to visit synthetic indices last.
2211   for (const auto &SubIdx : SubRegIndices) {
2212     if (SubIdx.Artificial)
2213       continue;
2214     SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
2215     // Unsupported SubRegIndex. Skip it.
2216     if (I == SRSets.end())
2217       continue;
2218     // In most cases, all RC registers support the SubRegIndex.
2219     if (I->second.size() == RC->getMembers().size()) {
2220       RC->setSubClassWithSubReg(&SubIdx, RC);
2221       continue;
2222     }
2223     // This is a real subset.  See if we have a matching class.
2224     CodeGenRegisterClass *SubRC =
2225       getOrCreateSubClass(RC, &I->second,
2226                           RC->getName() + "_with_" + I->first->getName());
2227     RC->setSubClassWithSubReg(&SubIdx, SubRC);
2228   }
2229 }
2230 
2231 //
2232 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
2233 //
2234 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
2235 // has a maximal result for any SubIdx and any X >= FirstSubRegRC.
2236 //
2237 
inferMatchingSuperRegClass(CodeGenRegisterClass * RC,std::list<CodeGenRegisterClass>::iterator FirstSubRegRC)2238 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
2239                                                 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
2240   SmallVector<std::pair<const CodeGenRegister*,
2241                         const CodeGenRegister*>, 16> SSPairs;
2242   BitVector TopoSigs(getNumTopoSigs());
2243 
2244   // Iterate in SubRegIndex numerical order to visit synthetic indices last.
2245   for (auto &SubIdx : SubRegIndices) {
2246     // Skip indexes that aren't fully supported by RC's registers. This was
2247     // computed by inferSubClassWithSubReg() above which should have been
2248     // called first.
2249     if (RC->getSubClassWithSubReg(&SubIdx) != RC)
2250       continue;
2251 
2252     // Build list of (Super, Sub) pairs for this SubIdx.
2253     SSPairs.clear();
2254     TopoSigs.reset();
2255     for (const auto Super : RC->getMembers()) {
2256       const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second;
2257       assert(Sub && "Missing sub-register");
2258       SSPairs.push_back(std::make_pair(Super, Sub));
2259       TopoSigs.set(Sub->getTopoSig());
2260     }
2261 
2262     // Iterate over sub-register class candidates.  Ignore classes created by
2263     // this loop. They will never be useful.
2264     // Store an iterator to the last element (not end) so that this loop doesn't
2265     // visit newly inserted elements.
2266     assert(!RegClasses.empty());
2267     for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end());
2268          I != std::next(E); ++I) {
2269       CodeGenRegisterClass &SubRC = *I;
2270       if (SubRC.Artificial)
2271         continue;
2272       // Topological shortcut: SubRC members have the wrong shape.
2273       if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
2274         continue;
2275       // Compute the subset of RC that maps into SubRC.
2276       CodeGenRegister::Vec SubSetVec;
2277       for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
2278         if (SubRC.contains(SSPairs[i].second))
2279           SubSetVec.push_back(SSPairs[i].first);
2280 
2281       if (SubSetVec.empty())
2282         continue;
2283 
2284       // RC injects completely into SubRC.
2285       sortAndUniqueRegisters(SubSetVec);
2286       if (SubSetVec.size() == SSPairs.size()) {
2287         SubRC.addSuperRegClass(&SubIdx, RC);
2288         continue;
2289       }
2290 
2291       // Only a subset of RC maps into SubRC. Make sure it is represented by a
2292       // class.
2293       getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
2294                                           SubIdx.getName() + "_in_" +
2295                                           SubRC.getName());
2296     }
2297   }
2298 }
2299 
2300 //
2301 // Infer missing register classes.
2302 //
computeInferredRegisterClasses()2303 void CodeGenRegBank::computeInferredRegisterClasses() {
2304   assert(!RegClasses.empty());
2305   // When this function is called, the register classes have not been sorted
2306   // and assigned EnumValues yet.  That means getSubClasses(),
2307   // getSuperClasses(), and hasSubClass() functions are defunct.
2308 
2309   // Use one-before-the-end so it doesn't move forward when new elements are
2310   // added.
2311   auto FirstNewRC = std::prev(RegClasses.end());
2312 
2313   // Visit all register classes, including the ones being added by the loop.
2314   // Watch out for iterator invalidation here.
2315   for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2316     CodeGenRegisterClass *RC = &*I;
2317     if (RC->Artificial)
2318       continue;
2319 
2320     // Synthesize answers for getSubClassWithSubReg().
2321     inferSubClassWithSubReg(RC);
2322 
2323     // Synthesize answers for getCommonSubClass().
2324     inferCommonSubClass(RC);
2325 
2326     // Synthesize answers for getMatchingSuperRegClass().
2327     inferMatchingSuperRegClass(RC);
2328 
2329     // New register classes are created while this loop is running, and we need
2330     // to visit all of them.  I  particular, inferMatchingSuperRegClass needs
2331     // to match old super-register classes with sub-register classes created
2332     // after inferMatchingSuperRegClass was called.  At this point,
2333     // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2334     // [0..FirstNewRC).  We need to cover SubRC = [FirstNewRC..rci].
2335     if (I == FirstNewRC) {
2336       auto NextNewRC = std::prev(RegClasses.end());
2337       for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2;
2338            ++I2)
2339         inferMatchingSuperRegClass(&*I2, E2);
2340       FirstNewRC = NextNewRC;
2341     }
2342   }
2343 }
2344 
2345 /// getRegisterClassForRegister - Find the register class that contains the
2346 /// specified physical register.  If the register is not in a register class,
2347 /// return null. If the register is in multiple classes, and the classes have a
2348 /// superset-subset relationship and the same set of types, return the
2349 /// superclass.  Otherwise return null.
2350 const CodeGenRegisterClass*
getRegClassForRegister(Record * R)2351 CodeGenRegBank::getRegClassForRegister(Record *R) {
2352   const CodeGenRegister *Reg = getReg(R);
2353   const CodeGenRegisterClass *FoundRC = nullptr;
2354   for (const auto &RC : getRegClasses()) {
2355     if (!RC.contains(Reg))
2356       continue;
2357 
2358     // If this is the first class that contains the register,
2359     // make a note of it and go on to the next class.
2360     if (!FoundRC) {
2361       FoundRC = &RC;
2362       continue;
2363     }
2364 
2365     // If a register's classes have different types, return null.
2366     if (RC.getValueTypes() != FoundRC->getValueTypes())
2367       return nullptr;
2368 
2369     // Check to see if the previously found class that contains
2370     // the register is a subclass of the current class. If so,
2371     // prefer the superclass.
2372     if (RC.hasSubClass(FoundRC)) {
2373       FoundRC = &RC;
2374       continue;
2375     }
2376 
2377     // Check to see if the previously found class that contains
2378     // the register is a superclass of the current class. If so,
2379     // prefer the superclass.
2380     if (FoundRC->hasSubClass(&RC))
2381       continue;
2382 
2383     // Multiple classes, and neither is a superclass of the other.
2384     // Return null.
2385     return nullptr;
2386   }
2387   return FoundRC;
2388 }
2389 
2390 const CodeGenRegisterClass *
getMinimalPhysRegClass(Record * RegRecord,ValueTypeByHwMode * VT)2391 CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
2392                                        ValueTypeByHwMode *VT) {
2393   const CodeGenRegister *Reg = getReg(RegRecord);
2394   const CodeGenRegisterClass *BestRC = nullptr;
2395   for (const auto &RC : getRegClasses()) {
2396     if ((!VT || RC.hasType(*VT)) &&
2397         RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC)))
2398       BestRC = &RC;
2399   }
2400 
2401   assert(BestRC && "Couldn't find the register class");
2402   return BestRC;
2403 }
2404 
computeCoveredRegisters(ArrayRef<Record * > Regs)2405 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2406   SetVector<const CodeGenRegister*> Set;
2407 
2408   // First add Regs with all sub-registers.
2409   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2410     CodeGenRegister *Reg = getReg(Regs[i]);
2411     if (Set.insert(Reg))
2412       // Reg is new, add all sub-registers.
2413       // The pre-ordering is not important here.
2414       Reg->addSubRegsPreOrder(Set, *this);
2415   }
2416 
2417   // Second, find all super-registers that are completely covered by the set.
2418   for (unsigned i = 0; i != Set.size(); ++i) {
2419     const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
2420     for (unsigned j = 0, e = SR.size(); j != e; ++j) {
2421       const CodeGenRegister *Super = SR[j];
2422       if (!Super->CoveredBySubRegs || Set.count(Super))
2423         continue;
2424       // This new super-register is covered by its sub-registers.
2425       bool AllSubsInSet = true;
2426       const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2427       for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2428              E = SRM.end(); I != E; ++I)
2429         if (!Set.count(I->second)) {
2430           AllSubsInSet = false;
2431           break;
2432         }
2433       // All sub-registers in Set, add Super as well.
2434       // We will visit Super later to recheck its super-registers.
2435       if (AllSubsInSet)
2436         Set.insert(Super);
2437     }
2438   }
2439 
2440   // Convert to BitVector.
2441   BitVector BV(Registers.size() + 1);
2442   for (unsigned i = 0, e = Set.size(); i != e; ++i)
2443     BV.set(Set[i]->EnumValue);
2444   return BV;
2445 }
2446 
printRegUnitName(unsigned Unit) const2447 void CodeGenRegBank::printRegUnitName(unsigned Unit) const {
2448   if (Unit < NumNativeRegUnits)
2449     dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
2450   else
2451     dbgs() << " #" << Unit;
2452 }
2453