1 /*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <common/bl_common.h>
9 #include <drivers/arm/gicv3.h>
10
11 #include <platform.h>
12 #include <platform_def.h>
13 #include <qti_plat.h>
14 #include <qtiseclib_defs.h>
15 #include <qtiseclib_defs_plat.h>
16
17 /* The GICv3 driver only needs to be initialized in EL3 */
18 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
19
20 /* Array of interrupts to be configured by the gic driver */
21 static const interrupt_prop_t qti_interrupt_props[] = {
22 INTR_PROP_DESC(QTISECLIB_INT_ID_CPU_WAKEUP_SGI,
23 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
24 GIC_INTR_CFG_EDGE),
25 INTR_PROP_DESC(QTISECLIB_INT_ID_RESET_SGI, GIC_HIGHEST_SEC_PRIORITY,
26 INTR_GROUP0,
27 GIC_INTR_CFG_EDGE),
28 INTR_PROP_DESC(QTISECLIB_INT_ID_SEC_WDOG_BARK, GIC_HIGHEST_SEC_PRIORITY,
29 INTR_GROUP0,
30 GIC_INTR_CFG_EDGE),
31 INTR_PROP_DESC(QTISECLIB_INT_ID_NON_SEC_WDOG_BITE,
32 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
33 GIC_INTR_CFG_LEVEL),
34 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC,
35 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
36 GIC_INTR_CFG_EDGE),
37 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC,
38 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
39 GIC_INTR_CFG_EDGE),
40 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC,
41 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
42 GIC_INTR_CFG_EDGE),
43 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC,
44 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
45 GIC_INTR_CFG_EDGE),
46 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_SEC, GIC_HIGHEST_SEC_PRIORITY,
47 INTR_GROUP0,
48 GIC_INTR_CFG_EDGE),
49 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_NON_SEC, GIC_HIGHEST_SEC_PRIORITY,
50 INTR_GROUP0,
51 GIC_INTR_CFG_EDGE),
52 #ifdef QTISECLIB_INT_ID_A1_NOC_ERROR
53 INTR_PROP_DESC(QTISECLIB_INT_ID_A1_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
54 INTR_GROUP0,
55 GIC_INTR_CFG_EDGE),
56 #endif
57 INTR_PROP_DESC(QTISECLIB_INT_ID_A2_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
58 INTR_GROUP0,
59 GIC_INTR_CFG_EDGE),
60 INTR_PROP_DESC(QTISECLIB_INT_ID_CONFIG_NOC_ERROR,
61 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
62 GIC_INTR_CFG_EDGE),
63 INTR_PROP_DESC(QTISECLIB_INT_ID_DC_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
64 INTR_GROUP0,
65 GIC_INTR_CFG_EDGE),
66 INTR_PROP_DESC(QTISECLIB_INT_ID_MEM_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
67 INTR_GROUP0,
68 GIC_INTR_CFG_EDGE),
69 INTR_PROP_DESC(QTISECLIB_INT_ID_SYSTEM_NOC_ERROR,
70 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
71 GIC_INTR_CFG_EDGE),
72 INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR,
73 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
74 GIC_INTR_CFG_EDGE),
75 };
76
77 const gicv3_driver_data_t qti_gic_data = {
78 .gicd_base = QTI_GICD_BASE,
79 .gicr_base = QTI_GICR_BASE,
80 .interrupt_props = qti_interrupt_props,
81 .interrupt_props_num = ARRAY_SIZE(qti_interrupt_props),
82 .rdistif_num = PLATFORM_CORE_COUNT,
83 .rdistif_base_addrs = rdistif_base_addrs,
84 .mpidr_to_core_pos = plat_qti_core_pos_by_mpidr
85 };
86
plat_qti_gic_driver_init(void)87 void plat_qti_gic_driver_init(void)
88 {
89 /*
90 * The GICv3 driver is initialized in EL3 and does not need
91 * to be initialized again in SEL1. This is because the S-EL1
92 * can use GIC system registers to manage interrupts and does
93 * not need GIC interface base addresses to be configured.
94 */
95 gicv3_driver_init(&qti_gic_data);
96 }
97
98 /******************************************************************************
99 * ARM common helper to initialize the GIC. Only invoked by BL31
100 *****************************************************************************/
plat_qti_gic_init(void)101 void plat_qti_gic_init(void)
102 {
103 unsigned int i;
104
105 gicv3_distif_init();
106 gicv3_rdistif_init(plat_my_core_pos());
107 gicv3_cpuif_enable(plat_my_core_pos());
108
109 /* Route secure spi interrupt to ANY. */
110 for (i = 0; i < ARRAY_SIZE(qti_interrupt_props); i++) {
111 unsigned int int_id = qti_interrupt_props[i].intr_num;
112
113 if (plat_ic_is_spi(int_id)) {
114 gicv3_set_spi_routing(int_id, GICV3_IRM_ANY, 0x0);
115 }
116 }
117 }
118
gic_set_spi_routing(unsigned int id,unsigned int irm,u_register_t target)119 void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t target)
120 {
121 gicv3_set_spi_routing(id, irm, target);
122 }
123
124 /******************************************************************************
125 * ARM common helper to enable the GIC CPU interface
126 *****************************************************************************/
plat_qti_gic_cpuif_enable(void)127 void plat_qti_gic_cpuif_enable(void)
128 {
129 gicv3_cpuif_enable(plat_my_core_pos());
130 }
131
132 /******************************************************************************
133 * ARM common helper to disable the GIC CPU interface
134 *****************************************************************************/
plat_qti_gic_cpuif_disable(void)135 void plat_qti_gic_cpuif_disable(void)
136 {
137 gicv3_cpuif_disable(plat_my_core_pos());
138 }
139
140 /******************************************************************************
141 * ARM common helper to initialize the per-CPU redistributor interface in GICv3
142 *****************************************************************************/
plat_qti_gic_pcpu_init(void)143 void plat_qti_gic_pcpu_init(void)
144 {
145 gicv3_rdistif_init(plat_my_core_pos());
146 }
147
148 /******************************************************************************
149 * ARM common helpers to power GIC redistributor interface
150 *****************************************************************************/
plat_qti_gic_redistif_on(void)151 void plat_qti_gic_redistif_on(void)
152 {
153 gicv3_rdistif_on(plat_my_core_pos());
154 }
155
plat_qti_gic_redistif_off(void)156 void plat_qti_gic_redistif_off(void)
157 {
158 gicv3_rdistif_off(plat_my_core_pos());
159 }
160