1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20
21 /**
22 *******************************************************************************
23 * @file
24 * ih264e_api.c
25 *
26 * @brief
27 * Contains api function definitions for H264 encoder
28 *
29 * @author
30 * ittiam
31 *
32 * @par List of Functions:
33 * - api_check_struct_sanity()
34 * - ih264e_codec_update_config()
35 * - ih264e_set_default_params()
36 * - ih264e_init()
37 * - ih264e_get_num_rec()
38 * - ih264e_fill_num_mem_rec()
39 * - ih264e_init_mem_rec()
40 * - ih264e_retrieve_memrec()
41 * - ih264e_set_flush_mode()
42 * - ih264e_get_buf_info()
43 * - ih264e_set_dimensions()
44 * - ih264e_set_frame_rate()
45 * - ih264e_set_bit_rate()
46 * - ih264e_set_frame_type()
47 * - ih264e_set_qp()
48 * - ih264e_set_enc_mode()
49 * - ih264e_set_vbv_params()
50 * - ih264_set_air_params()
51 * - ih264_set_me_params()
52 * - ih264_set_ipe_params()
53 * - ih264_set_gop_params()
54 * - ih264_set_profile_params()
55 * - ih264_set_deblock_params()
56 * - ih264e_set_num_cores()
57 * - ih264e_reset()
58 * - ih264e_ctl()
59 * - ih264e_api_function()
60 *
61 * @remarks
62 * None
63 *
64 *******************************************************************************
65 */
66
67 /*****************************************************************************/
68 /* File Includes */
69 /*****************************************************************************/
70
71 /* System Include Files */
72 #include <stdio.h>
73 #include <stddef.h>
74 #include <stdlib.h>
75 #include <string.h>
76 #include <assert.h>
77
78 /* User Include Files */
79 #include "ih264e_config.h"
80 #include "ih264_typedefs.h"
81 #include "ih264_size_defs.h"
82 #include "iv2.h"
83 #include "ive2.h"
84 #include "ih264e.h"
85 #include "ithread.h"
86 #include "ih264_debug.h"
87 #include "ih264_defs.h"
88 #include "ih264_error.h"
89 #include "ih264_structs.h"
90 #include "ih264_trans_quant_itrans_iquant.h"
91 #include "ih264_inter_pred_filters.h"
92 #include "ih264_mem_fns.h"
93 #include "ih264_padding.h"
94 #include "ih264_intra_pred_filters.h"
95 #include "ih264_deblk_edge_filters.h"
96 #include "ih264_cabac_tables.h"
97 #include "ih264_macros.h"
98 #include "ih264e_defs.h"
99 #include "ih264e_globals.h"
100 #include "ih264_buf_mgr.h"
101 #include "irc_mem_req_and_acq.h"
102 #include "irc_cntrl_param.h"
103 #include "irc_frame_info_collector.h"
104 #include "irc_rate_control_api.h"
105 #include "ih264e_time_stamp.h"
106 #include "ih264e_modify_frm_rate.h"
107 #include "ih264e_rate_control.h"
108 #include "ih264e_error.h"
109 #include "ih264e_bitstream.h"
110 #include "ime_defs.h"
111 #include "ime_distortion_metrics.h"
112 #include "ime_structs.h"
113 #include "ih264e_cabac_structs.h"
114 #include "ih264e_structs.h"
115 #include "ih264e_utils.h"
116 #include "ih264e_core_coding.h"
117 #include "ih264_platform_macros.h"
118 #include "ih264e_platform_macros.h"
119 #include "ih264_list.h"
120 #include "ih264_dpb_mgr.h"
121 #include "ih264_cavlc_tables.h"
122 #include "ih264e_cavlc.h"
123 #include "ih264_common_tables.h"
124 #include "ih264e_master.h"
125 #include "ih264e_fmt_conv.h"
126 #include "ih264e_version.h"
127
128
129 /*****************************************************************************/
130 /* Function Declarations */
131 /*****************************************************************************/
132 WORD32 ih264e_get_rate_control_mem_tab(void *pv_rate_control,
133 iv_mem_rec_t *ps_mem,
134 ITT_FUNC_TYPE_E e_func_type);
135
136
137 /*****************************************************************************/
138 /* Function Definitions */
139 /*****************************************************************************/
140
141 /**
142 *******************************************************************************
143 *
144 * @brief
145 * Used to test validity of input dimensions
146 *
147 * @par Description:
148 * Dimensions of the input buffer passed to encode call are validated
149 *
150 * @param[in] ps_codec
151 * Codec context
152 *
153 * @param[in] ps_ip
154 * Pointer to input structure
155 *
156 * @param[out] ps_op
157 * Pointer to output structure
158 *
159 * @returns error status
160 *
161 * @remarks none
162 *
163 *******************************************************************************
164 */
api_check_input_dimensions(codec_t * ps_codec,ih264e_video_encode_ip_t * ps_ip,ih264e_video_encode_op_t * ps_op)165 static IV_STATUS_T api_check_input_dimensions(codec_t *ps_codec,
166 ih264e_video_encode_ip_t *ps_ip,
167 ih264e_video_encode_op_t *ps_op)
168 {
169 UWORD32 u4_wd, u4_ht;
170 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
171 iv_raw_buf_t *ps_inp_buf = &ps_ip->s_ive_ip.s_inp_buf;
172
173 u4_wd = ps_inp_buf->au4_wd[0];
174 u4_ht = ps_inp_buf->au4_ht[0];
175 switch (ps_inp_buf->e_color_fmt)
176 {
177 case IV_YUV_420P:
178 if (((ps_inp_buf->au4_wd[0] / 2) != ps_inp_buf->au4_wd[1]) ||
179 ((ps_inp_buf->au4_wd[0] / 2) != ps_inp_buf->au4_wd[2]) ||
180 (ps_inp_buf->au4_wd[1] != ps_inp_buf->au4_wd[2]))
181 {
182 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
183 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
184 return (IV_FAIL);
185 }
186 if (((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[1]) ||
187 ((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[2]) ||
188 (ps_inp_buf->au4_ht[1] != ps_inp_buf->au4_ht[2]))
189 {
190 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
191 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
192 return (IV_FAIL);
193 }
194 break;
195 case IV_YUV_420SP_UV:
196 case IV_YUV_420SP_VU:
197 if ((ps_inp_buf->au4_wd[0] / 2) != ps_inp_buf->au4_wd[1])
198 {
199 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
200 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
201 return (IV_FAIL);
202 }
203 if ((ps_inp_buf->au4_ht[0] / 2) != ps_inp_buf->au4_ht[1])
204 {
205 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
206 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
207 return (IV_FAIL);
208 }
209 break;
210 case IV_YUV_422ILE:
211 u4_wd = ps_inp_buf->au4_wd[0] / 2;
212 break;
213 default:
214 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
215 ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
216 return (IV_FAIL);
217 }
218
219 if (u4_wd != ps_curr_cfg->u4_disp_wd)
220 {
221 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
222 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
223 return (IV_FAIL);
224 }
225
226 if (u4_ht != ps_curr_cfg->u4_disp_ht)
227 {
228 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
229 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
230 return (IV_FAIL);
231 }
232
233 return IV_SUCCESS;
234 }
235
236 /**
237 *******************************************************************************
238 *
239 * @brief
240 * Used to test arguments for corresponding API call
241 *
242 * @par Description:
243 * For each command the arguments are validated
244 *
245 * @param[in] ps_handle
246 * Codec handle at API level
247 *
248 * @param[in] pv_api_ip
249 * Pointer to input structure
250 *
251 * @param[out] pv_api_op
252 * Pointer to output structure
253 *
254 * @returns error status
255 *
256 * @remarks none
257 *
258 *******************************************************************************
259 */
api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)260 static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
261 void *pv_api_ip,
262 void *pv_api_op)
263 {
264 /* api call */
265 WORD32 command = IV_CMD_NA;
266
267 /* input structure expected by the api call */
268 UWORD32 *pu4_api_ip = pv_api_ip;
269
270 /* output structure expected by the api call */
271 UWORD32 *pu4_api_op = pv_api_op;
272
273 /* temp var */
274 WORD32 i, j;
275
276 if (NULL == pv_api_op || NULL == pv_api_ip)
277 {
278 return (IV_FAIL);
279 }
280
281 /* get command */
282 command = pu4_api_ip[1];
283
284 /* set error code */
285 pu4_api_op[1] = 0;
286
287 /* error checks on handle */
288 switch (command)
289 {
290 case IV_CMD_GET_NUM_MEM_REC:
291 case IV_CMD_FILL_NUM_MEM_REC:
292 break;
293
294 case IV_CMD_INIT:
295 if (ps_handle == NULL)
296 {
297 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
298 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
299 return IV_FAIL;
300 }
301
302 if (ps_handle->u4_size != sizeof(iv_obj_t))
303 {
304 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
305 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
306 return IV_FAIL;
307 }
308 break;
309
310 case IVE_CMD_QUEUE_INPUT:
311 case IVE_CMD_QUEUE_OUTPUT:
312 case IVE_CMD_DEQUEUE_OUTPUT:
313 case IVE_CMD_GET_RECON:
314 case IV_CMD_RETRIEVE_MEMREC:
315 case IVE_CMD_VIDEO_CTL:
316 case IVE_CMD_VIDEO_ENCODE:
317
318 if (ps_handle == NULL)
319 {
320 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
321 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
322 return IV_FAIL;
323 }
324
325 if (ps_handle->u4_size != sizeof(iv_obj_t))
326 {
327 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
328 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
329 return IV_FAIL;
330 }
331
332 if (ps_handle->pv_fxns != ih264e_api_function)
333 {
334 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
335 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
336 return IV_FAIL;
337 }
338
339 if (ps_handle->pv_codec_handle == NULL)
340 {
341 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
342 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
343 return IV_FAIL;
344 }
345 break;
346
347 default:
348 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
349 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
350 return IV_FAIL;
351 }
352
353 /* error checks on input output structures */
354 switch (command)
355 {
356 case IV_CMD_GET_NUM_MEM_REC:
357 {
358 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip;
359 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
360
361 ps_op->s_ive_op.u4_error_code = 0;
362
363 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t))
364 {
365 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
366 ps_op->s_ive_op.u4_error_code |=
367 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
368 return (IV_FAIL);
369 }
370
371 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t))
372 {
373 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
374 ps_op->s_ive_op.u4_error_code |=
375 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
376 return (IV_FAIL);
377 }
378 break;
379 }
380
381 case IV_CMD_FILL_NUM_MEM_REC:
382 {
383 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
384 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
385
386 iv_mem_rec_t *ps_mem_rec = NULL;
387
388 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
389 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
390
391 ps_op->s_ive_op.u4_error_code = 0;
392
393 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t))
394 {
395 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
396 ps_op->s_ive_op.u4_error_code |=
397 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
398 return (IV_FAIL);
399 }
400
401 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t))
402 {
403 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
404 ps_op->s_ive_op.u4_error_code |=
405 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
406 return (IV_FAIL);
407 }
408
409 if (max_wd < MIN_WD || max_wd > MAX_WD)
410 {
411 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
412 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
413 return (IV_FAIL);
414 }
415
416 if (max_ht < MIN_HT || max_ht > MAX_HT)
417 {
418 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
419 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
420 return (IV_FAIL);
421 }
422
423 /* verify number of mem rec ptr */
424 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
425 {
426 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
427 ps_op->s_ive_op.u4_error_code |=
428 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
429 return (IV_FAIL);
430 }
431
432 /* verify number of mem records */
433 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
434 {
435 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
436 ps_op->s_ive_op.u4_error_code |=
437 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
438 return IV_FAIL;
439 }
440
441 /* check mem records sizes are correct */
442 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
443 for (i = 0; i < MEM_REC_CNT; i++)
444 {
445 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
446 {
447 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
448 ps_op->s_ive_op.u4_error_code |=
449 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
450 return IV_FAIL;
451 }
452 }
453 break;
454 }
455
456 case IV_CMD_INIT:
457 {
458 ih264e_init_ip_t *ps_ip = pv_api_ip;
459 ih264e_init_op_t *ps_op = pv_api_op;
460
461 iv_mem_rec_t *ps_mem_rec = NULL;
462
463 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
464 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
465
466 ps_op->s_ive_op.u4_error_code = 0;
467
468 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t))
469 {
470 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
471 ps_op->s_ive_op.u4_error_code |=
472 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
473 return (IV_FAIL);
474 }
475
476 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t))
477 {
478 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
479 ps_op->s_ive_op.u4_error_code |=
480 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
481 return (IV_FAIL);
482 }
483
484 if (max_wd < MIN_WD || max_wd > MAX_WD)
485 {
486 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
487 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
488 return (IV_FAIL);
489 }
490
491 if (max_ht < MIN_HT || max_ht > MAX_HT)
492 {
493 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
494 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
495 return (IV_FAIL);
496 }
497
498 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
499 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
500 {
501 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
502 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
503 return (IV_FAIL);
504 }
505
506 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
507 {
508 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
509 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
510 return (IV_FAIL);
511 }
512
513 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10)
514 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B)
515 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11)
516 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12)
517 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13)
518 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20)
519 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21)
520 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22)
521 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30)
522 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31)
523 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32)
524 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40)
525 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41)
526 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42)
527 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50)
528 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
529 {
530 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
531 ps_op->s_ive_op.u4_error_code |=
532 IH264E_CODEC_LEVEL_NOT_SUPPORTED;
533 return (IV_FAIL);
534 }
535
536 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
537 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
538 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
539 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
540 {
541 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
542 ps_op->s_ive_op.u4_error_code |=
543 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
544 return (IV_FAIL);
545 }
546
547 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
548 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV)
549 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU))
550 {
551 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
552 ps_op->s_ive_op.u4_error_code |=
553 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
554 return (IV_FAIL);
555 }
556
557 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE)
558 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE)
559 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
560 {
561 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
562 ps_op->s_ive_op.u4_error_code |=
563 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
564 return (IV_FAIL);
565 }
566
567 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
568 {
569 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
570 ps_op->s_ive_op.u4_error_code |=
571 IH264E_FRAME_RATE_NOT_SUPPORTED;
572 return (IV_FAIL);
573 }
574
575 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE)
576 {
577 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
578 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
579 return (IV_FAIL);
580 }
581
582 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES)
583 {
584 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
585 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
586 return (IV_FAIL);
587 }
588
589 if (ps_ip->s_ive_ip.u4_num_bframes
590 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
591 {
592 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
593 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
594 return (IV_FAIL);
595 }
596
597 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
598 {
599 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
600 ps_op->s_ive_op.u4_error_code |=
601 IH264E_CONTENT_TYPE_NOT_SUPPORTED;
602 return (IV_FAIL);
603 }
604
605 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
606 {
607 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
608 ps_op->s_ive_op.u4_error_code |=
609 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
610 return (IV_FAIL);
611 }
612
613 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
614 {
615 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
616 ps_op->s_ive_op.u4_error_code |=
617 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
618 return (IV_FAIL);
619 }
620
621 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
622 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS))
623 {
624 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
625 ps_op->s_ive_op.u4_error_code |=
626 IH264E_SLICE_TYPE_INPUT_INVALID;
627 return (IV_FAIL);
628 }
629
630 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS)
631 {
632 if (ps_ip->s_ive_ip.u4_slice_param == 0
633 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4))
634 {
635 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
636 ps_op->s_ive_op.u4_error_code |=
637 IH264E_SLICE_PARAM_INPUT_INVALID;
638 return (IV_FAIL);
639 }
640 }
641
642 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
643 {
644 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
645 ps_op->s_ive_op.u4_error_code |=
646 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
647 return (IV_FAIL);
648 }
649
650 /* verify number of mem records */
651 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
652 {
653 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
654 ps_op->s_ive_op.u4_error_code |=
655 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
656 return (IV_FAIL);
657 }
658
659 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
660
661 /* check memrecords sizes are correct */
662 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++)
663 {
664 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
665 {
666 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
667 ps_op->s_ive_op.u4_error_code |=
668 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
669 return IV_FAIL;
670 }
671
672 /* check memrecords pointers are not NULL */
673 if (ps_mem_rec[i].pv_base == NULL)
674 {
675 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
676 ps_op->s_ive_op.u4_error_code |=
677 IVE_ERR_MEM_REC_BASE_POINTER_NULL;
678 return IV_FAIL;
679 }
680 }
681
682 /* verify memtabs for overlapping regions */
683 {
684 void *start[MEM_REC_CNT];
685 void *end[MEM_REC_CNT];
686
687 start[0] = (ps_mem_rec[0].pv_base);
688 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base)
689 + ps_mem_rec[0].u4_mem_size - 1;
690
691 for (i = 1; i < MEM_REC_CNT; i++)
692 {
693 /* This array is populated to check memtab overlap */
694 start[i] = (ps_mem_rec[i].pv_base);
695 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base)
696 + ps_mem_rec[i].u4_mem_size - 1;
697
698 for (j = 0; j < i; j++)
699 {
700 if ((start[i] >= start[j]) && (start[i] <= end[j]))
701 {
702 ps_op->s_ive_op.u4_error_code |= 1
703 << IVE_UNSUPPORTEDPARAM;
704 ps_op->s_ive_op.u4_error_code |=
705 IVE_ERR_MEM_REC_OVERLAP_ERR;
706 return IV_FAIL;
707 }
708
709 if ((end[i] >= start[j]) && (end[i] <= end[j]))
710 {
711 ps_op->s_ive_op.u4_error_code |= 1
712 << IVE_UNSUPPORTEDPARAM;
713 ps_op->s_ive_op.u4_error_code |=
714 IVE_ERR_MEM_REC_OVERLAP_ERR;
715 return IV_FAIL;
716 }
717
718 if ((start[i] < start[j]) && (end[i] > end[j]))
719 {
720 ps_op->s_ive_op.u4_error_code |= 1
721 << IVE_UNSUPPORTEDPARAM;
722 ps_op->s_ive_op.u4_error_code |=
723 IVE_ERR_MEM_REC_OVERLAP_ERR;
724 return IV_FAIL;
725 }
726 }
727 }
728 }
729
730 /* re-validate mem records with init config */
731 {
732 /* mem records */
733 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT];
734
735 /* api interface structs */
736 ih264e_fill_mem_rec_ip_t s_ip;
737 ih264e_fill_mem_rec_op_t s_op;
738
739 /* error status */
740 IV_STATUS_T e_status;
741
742 /* temp var */
743 WORD32 i;
744
745 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t);
746 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t);
747
748 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
749 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
750 s_ip.s_ive_ip.u4_max_wd = max_wd;
751 s_ip.s_ive_ip.u4_max_ht = max_ht;
752 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
753 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
754 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
755 s_ip.s_ive_ip.u4_max_reorder_cnt =
756 ps_ip->s_ive_ip.u4_max_reorder_cnt;
757 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
758 s_ip.s_ive_ip.u4_max_srch_rng_x =
759 ps_ip->s_ive_ip.u4_max_srch_rng_x;
760 s_ip.s_ive_ip.u4_max_srch_rng_y =
761 ps_ip->s_ive_ip.u4_max_srch_rng_y;
762
763 for (i = 0; i < MEM_REC_CNT; i++)
764 {
765 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
766 }
767
768 /* fill mem records */
769 e_status = ih264e_api_function(NULL, (void *) &s_ip,
770 (void *) &s_op);
771
772 if (IV_FAIL == e_status)
773 {
774 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
775 return (IV_FAIL);
776 }
777
778 /* verify mem records */
779 for (i = 0; i < MEM_REC_CNT; i++)
780 {
781 if (ps_mem_rec[i].u4_mem_size
782 < s_mem_rec_ittiam_api[i].u4_mem_size)
783 {
784 ps_op->s_ive_op.u4_error_code |= 1
785 << IVE_UNSUPPORTEDPARAM;
786 ps_op->s_ive_op.u4_error_code |=
787 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
788
789 return IV_FAIL;
790 }
791
792 if (ps_mem_rec[i].u4_mem_alignment
793 != s_mem_rec_ittiam_api[i].u4_mem_alignment)
794 {
795 ps_op->s_ive_op.u4_error_code |= 1
796 << IVE_UNSUPPORTEDPARAM;
797 ps_op->s_ive_op.u4_error_code |=
798 IVE_ERR_MEM_REC_ALIGNMENT_ERR;
799
800 return IV_FAIL;
801 }
802
803 if (ps_mem_rec[i].e_mem_type
804 != s_mem_rec_ittiam_api[i].e_mem_type)
805 {
806 UWORD32 check = IV_SUCCESS;
807 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type
808 - ps_mem_rec[i].e_mem_type;
809
810 if ((ps_mem_rec[i].e_mem_type
811 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
812 && (s_mem_rec_ittiam_api[i].e_mem_type
813 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
814 {
815 check = IV_FAIL;
816 }
817
818 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
819 {
820 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
821 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
822
823 if ((diff < 1) || (diff > 3))
824 {
825 /* Difference between 1 and 3 is okay for all cases other than the
826 * two filtered with the MOD condition above */
827 check = IV_FAIL;
828 }
829 }
830 else
831 {
832 if (diff == 1)
833 {
834 /* This particular case is when codec asked for External Persistent,
835 * but got Internal Scratch */
836 check = IV_FAIL;
837 }
838 if ((diff != 2) && (diff != 3))
839 {
840 check = IV_FAIL;
841 }
842 }
843
844 if (check == IV_FAIL)
845 {
846 ps_op->s_ive_op.u4_error_code |= 1
847 << IVE_UNSUPPORTEDPARAM;
848 ps_op->s_ive_op.u4_error_code |=
849 IVE_ERR_MEM_REC_INCORRECT_TYPE;
850
851 return IV_FAIL;
852 }
853 }
854 }
855 }
856 break;
857 }
858
859 case IVE_CMD_QUEUE_INPUT:
860 case IVE_CMD_QUEUE_OUTPUT:
861 case IVE_CMD_DEQUEUE_OUTPUT:
862 case IVE_CMD_GET_RECON:
863 break;
864
865 case IV_CMD_RETRIEVE_MEMREC:
866 {
867 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
868 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
869
870 iv_mem_rec_t *ps_mem_rec = NULL;
871
872 ps_op->s_ive_op.u4_error_code = 0;
873
874 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t))
875 {
876 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
877 ps_op->s_ive_op.u4_error_code |=
878 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
879 return (IV_FAIL);
880 }
881
882 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t))
883 {
884 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
885 ps_op->s_ive_op.u4_error_code |=
886 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
887 return (IV_FAIL);
888 }
889
890 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
891 {
892 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
893 ps_op->s_ive_op.u4_error_code |=
894 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
895 return (IV_FAIL);
896 }
897
898 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
899
900 /* check memrecords sizes are correct */
901 for (i = 0; i < MEM_REC_CNT; i++)
902 {
903 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
904 {
905 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
906 ps_op->s_ive_op.u4_error_code |=
907 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
908 return IV_FAIL;
909 }
910 }
911 break;
912 }
913
914 case IVE_CMD_VIDEO_ENCODE:
915 {
916 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
917 ih264e_video_encode_ip_t *ps_ip = pv_api_ip;
918 ih264e_video_encode_op_t *ps_op = pv_api_op;
919
920 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t))
921 {
922 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
923 ps_op->s_ive_op.u4_error_code |=
924 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
925 return (IV_FAIL);
926 }
927
928 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t))
929 {
930 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
931 ps_op->s_ive_op.u4_error_code |=
932 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
933 return (IV_FAIL);
934 }
935
936 if (NULL != ps_ip->s_ive_ip.s_inp_buf.apv_bufs[0] &&
937 ps_codec->i4_header_mode != 1 &&
938 IV_SUCCESS != api_check_input_dimensions(ps_codec, ps_ip, ps_op))
939 {
940 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
941 ps_op->s_ive_op.u4_error_code |= IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
942 return (IV_FAIL);
943 }
944 break;
945 }
946
947 case IVE_CMD_VIDEO_CTL:
948 {
949 /* ptr to input structure */
950 WORD32 *pu4_ptr_cmd = pv_api_ip;
951
952 /* sub command */
953 WORD32 sub_command = pu4_ptr_cmd[2];
954
955 switch (sub_command)
956 {
957 case IVE_CMD_CTL_SETDEFAULT:
958 {
959 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
960 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
961
962 if (ps_ip->s_ive_ip.u4_size
963 != sizeof(ih264e_ctl_setdefault_ip_t))
964 {
965 ps_op->s_ive_op.u4_error_code |= 1
966 << IVE_UNSUPPORTEDPARAM;
967 ps_op->s_ive_op.u4_error_code |=
968 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
969 return IV_FAIL;
970 }
971
972 if (ps_op->s_ive_op.u4_size
973 != sizeof(ih264e_ctl_setdefault_op_t))
974 {
975 ps_op->s_ive_op.u4_error_code |= 1
976 << IVE_UNSUPPORTEDPARAM;
977 ps_op->s_ive_op.u4_error_code |=
978 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
979 return IV_FAIL;
980 }
981 break;
982 }
983
984 case IVE_CMD_CTL_GETBUFINFO:
985 {
986 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
987
988 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
989 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
990
991 if (ps_ip->s_ive_ip.u4_size
992 != sizeof(ih264e_ctl_getbufinfo_ip_t))
993 {
994 ps_op->s_ive_op.u4_error_code |= 1
995 << IVE_UNSUPPORTEDPARAM;
996 ps_op->s_ive_op.u4_error_code |=
997 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
998 return IV_FAIL;
999 }
1000
1001 if (ps_op->s_ive_op.u4_size
1002 != sizeof(ih264e_ctl_getbufinfo_op_t))
1003 {
1004 ps_op->s_ive_op.u4_error_code |= 1
1005 << IVE_UNSUPPORTEDPARAM;
1006 ps_op->s_ive_op.u4_error_code |=
1007 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
1008 return IV_FAIL;
1009 }
1010
1011 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
1012 {
1013 ps_op->s_ive_op.u4_error_code |= 1
1014 << IVE_UNSUPPORTEDPARAM;
1015 ps_op->s_ive_op.u4_error_code |=
1016 IH264E_WIDTH_NOT_SUPPORTED;
1017 return (IV_FAIL);
1018 }
1019
1020 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd)
1021 {
1022 ps_op->s_ive_op.u4_error_code |= 1
1023 << IVE_UNSUPPORTEDPARAM;
1024 ps_op->s_ive_op.u4_error_code |=
1025 IH264E_WIDTH_NOT_SUPPORTED;
1026 return (IV_FAIL);
1027 }
1028
1029 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
1030 {
1031 ps_op->s_ive_op.u4_error_code |= 1
1032 << IVE_UNSUPPORTEDPARAM;
1033 ps_op->s_ive_op.u4_error_code |=
1034 IH264E_HEIGHT_NOT_SUPPORTED;
1035 return (IV_FAIL);
1036 }
1037
1038 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht)
1039 {
1040 ps_op->s_ive_op.u4_error_code |= 1
1041 << IVE_UNSUPPORTEDPARAM;
1042 ps_op->s_ive_op.u4_error_code |=
1043 IH264E_HEIGHT_NOT_SUPPORTED;
1044 return (IV_FAIL);
1045 }
1046
1047 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
1048 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
1049 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
1050 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
1051 {
1052 ps_op->s_ive_op.u4_error_code |= 1
1053 << IVE_UNSUPPORTEDPARAM;
1054 ps_op->s_ive_op.u4_error_code |=
1055 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
1056 return (IV_FAIL);
1057 }
1058 break;
1059 }
1060
1061 case IVE_CMD_CTL_GETVERSION:
1062 {
1063 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
1064 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
1065
1066 if (ps_ip->s_ive_ip.u4_size
1067 != sizeof(ih264e_ctl_getversioninfo_ip_t))
1068 {
1069 ps_op->s_ive_op.u4_error_code |= 1
1070 << IVE_UNSUPPORTEDPARAM;
1071 ps_op->s_ive_op.u4_error_code |=
1072 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
1073 return IV_FAIL;
1074 }
1075
1076 if (ps_op->s_ive_op.u4_size
1077 != sizeof(ih264e_ctl_getversioninfo_op_t))
1078 {
1079 ps_op->s_ive_op.u4_error_code |= 1
1080 << IVE_UNSUPPORTEDPARAM;
1081 ps_op->s_ive_op.u4_error_code |=
1082 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
1083 return IV_FAIL;
1084 }
1085
1086 if (ps_ip->s_ive_ip.pu1_version == NULL)
1087 {
1088 ps_op->s_ive_op.u4_error_code |= 1
1089 << IVE_UNSUPPORTEDPARAM;
1090 ps_op->s_ive_op.u4_error_code |=
1091 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
1092 return IV_FAIL;
1093 }
1094
1095 break;
1096 }
1097
1098 case IVE_CMD_CTL_FLUSH:
1099 {
1100 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip;
1101 ih264e_ctl_flush_op_t *ps_op = pv_api_op;
1102
1103 if (ps_ip->s_ive_ip.u4_size
1104 != sizeof(ih264e_ctl_flush_ip_t))
1105 {
1106 ps_op->s_ive_op.u4_error_code |= 1
1107 << IVE_UNSUPPORTEDPARAM;
1108 ps_op->s_ive_op.u4_error_code |=
1109 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1110 return IV_FAIL;
1111 }
1112
1113 if (ps_op->s_ive_op.u4_size
1114 != sizeof(ih264e_ctl_flush_op_t))
1115 {
1116 ps_op->s_ive_op.u4_error_code |= 1
1117 << IVE_UNSUPPORTEDPARAM;
1118 ps_op->s_ive_op.u4_error_code |=
1119 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1120 return IV_FAIL;
1121 }
1122
1123 break;
1124 }
1125
1126 case IVE_CMD_CTL_RESET:
1127 {
1128 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip;
1129 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
1130
1131 if (ps_ip->s_ive_ip.u4_size
1132 != sizeof(ih264e_ctl_reset_ip_t))
1133 {
1134 ps_op->s_ive_op.u4_error_code |= 1
1135 << IVE_UNSUPPORTEDPARAM;
1136 ps_op->s_ive_op.u4_error_code |=
1137 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1138 return IV_FAIL;
1139 }
1140
1141 if (ps_op->s_ive_op.u4_size
1142 != sizeof(ih264e_ctl_reset_op_t))
1143 {
1144 ps_op->s_ive_op.u4_error_code |= 1
1145 << IVE_UNSUPPORTEDPARAM;
1146 ps_op->s_ive_op.u4_error_code |=
1147 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1148 return IV_FAIL;
1149 }
1150
1151 break;
1152 }
1153
1154 case IVE_CMD_CTL_SET_NUM_CORES:
1155 {
1156 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
1157 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
1158
1159 if (ps_ip->s_ive_ip.u4_size
1160 != sizeof(ih264e_ctl_set_num_cores_ip_t))
1161 {
1162 ps_op->s_ive_op.u4_error_code |= 1
1163 << IVE_UNSUPPORTEDPARAM;
1164 ps_op->s_ive_op.u4_error_code |=
1165 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1166 return IV_FAIL;
1167 }
1168
1169 if (ps_op->s_ive_op.u4_size
1170 != sizeof(ih264e_ctl_set_num_cores_op_t))
1171 {
1172 ps_op->s_ive_op.u4_error_code |= 1
1173 << IVE_UNSUPPORTEDPARAM;
1174 ps_op->s_ive_op.u4_error_code |=
1175 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1176 return IV_FAIL;
1177 }
1178
1179 if ((ps_ip->s_ive_ip.u4_num_cores < 1)
1180 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
1181 {
1182 ps_op->s_ive_op.u4_error_code |= 1
1183 << IVE_UNSUPPORTEDPARAM;
1184 ps_op->s_ive_op.u4_error_code |=
1185 IH264E_INVALID_NUM_CORES;
1186 return IV_FAIL;
1187 }
1188
1189 break;
1190 }
1191
1192 case IVE_CMD_CTL_SET_DIMENSIONS:
1193 {
1194 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1195
1196 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
1197 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
1198
1199 if (ps_ip->s_ive_ip.u4_size
1200 != sizeof(ih264e_ctl_set_dimensions_ip_t))
1201 {
1202 ps_op->s_ive_op.u4_error_code |= 1
1203 << IVE_UNSUPPORTEDPARAM;
1204 ps_op->s_ive_op.u4_error_code |=
1205 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1206 return IV_FAIL;
1207 }
1208
1209 if (ps_op->s_ive_op.u4_size
1210 != sizeof(ih264e_ctl_set_dimensions_op_t))
1211 {
1212 ps_op->s_ive_op.u4_error_code |= 1
1213 << IVE_UNSUPPORTEDPARAM;
1214 ps_op->s_ive_op.u4_error_code |=
1215 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1216 return IV_FAIL;
1217 }
1218
1219 if (ps_ip->s_ive_ip.u4_wd < MIN_WD)
1220 {
1221 ps_op->s_ive_op.u4_error_code |= 1
1222 << IVE_UNSUPPORTEDPARAM;
1223 ps_op->s_ive_op.u4_error_code |=
1224 IH264E_WIDTH_NOT_SUPPORTED;
1225 return (IV_FAIL);
1226 }
1227
1228 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
1229 {
1230 ps_op->s_ive_op.u4_error_code |= 1
1231 << IVE_UNSUPPORTEDPARAM;
1232 ps_op->s_ive_op.u4_error_code |=
1233 IH264E_WIDTH_NOT_SUPPORTED;
1234 return (IV_FAIL);
1235 }
1236
1237 if (ps_ip->s_ive_ip.u4_ht < MIN_HT)
1238 {
1239 ps_op->s_ive_op.u4_error_code |= 1
1240 << IVE_UNSUPPORTEDPARAM;
1241 ps_op->s_ive_op.u4_error_code |=
1242 IH264E_HEIGHT_NOT_SUPPORTED;
1243 return (IV_FAIL);
1244 }
1245
1246 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1247 {
1248 ps_op->s_ive_op.u4_error_code |= 1
1249 << IVE_UNSUPPORTEDPARAM;
1250 ps_op->s_ive_op.u4_error_code |=
1251 IH264E_HEIGHT_NOT_SUPPORTED;
1252 return (IV_FAIL);
1253 }
1254
1255 if(ps_ip->s_ive_ip.u4_wd & 1)
1256 {
1257 ps_op->s_ive_op.u4_error_code |= 1
1258 << IVE_UNSUPPORTEDPARAM;
1259 ps_op->s_ive_op.u4_error_code |=
1260 IH264E_WIDTH_NOT_SUPPORTED;
1261 return (IV_FAIL);
1262 }
1263
1264 if(ps_ip->s_ive_ip.u4_ht & 1)
1265 {
1266 ps_op->s_ive_op.u4_error_code |= 1
1267 << IVE_UNSUPPORTEDPARAM;
1268 ps_op->s_ive_op.u4_error_code |=
1269 IH264E_HEIGHT_NOT_SUPPORTED;
1270 return (IV_FAIL);
1271 }
1272
1273 break;
1274 }
1275
1276 case IVE_CMD_CTL_SET_FRAMERATE:
1277 {
1278 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1279 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1280
1281 if (ps_ip->s_ive_ip.u4_size
1282 != sizeof(ih264e_ctl_set_frame_rate_ip_t))
1283 {
1284 ps_op->s_ive_op.u4_error_code |= 1
1285 << IVE_UNSUPPORTEDPARAM;
1286 ps_op->s_ive_op.u4_error_code |=
1287 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1288 return IV_FAIL;
1289 }
1290
1291 if (ps_op->s_ive_op.u4_size
1292 != sizeof(ih264e_ctl_set_frame_rate_op_t))
1293 {
1294 ps_op->s_ive_op.u4_error_code |= 1
1295 << IVE_UNSUPPORTEDPARAM;
1296 ps_op->s_ive_op.u4_error_code |=
1297 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1298 return IV_FAIL;
1299 }
1300
1301 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)
1302 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1303 {
1304 ps_op->s_ive_op.u4_error_code |= 1
1305 << IVE_UNSUPPORTEDPARAM;
1306 ps_op->s_ive_op.u4_error_code |=
1307 IH264E_FRAME_RATE_NOT_SUPPORTED;
1308 return (IV_FAIL);
1309 }
1310
1311 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0)
1312 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1313 {
1314 ps_op->s_ive_op.u4_error_code |= 1
1315 << IVE_UNSUPPORTEDPARAM;
1316 ps_op->s_ive_op.u4_error_code |=
1317 IH264E_FRAME_RATE_NOT_SUPPORTED;
1318 return (IV_FAIL);
1319 }
1320
1321 if (ps_ip->s_ive_ip.u4_tgt_frame_rate
1322 > ps_ip->s_ive_ip.u4_src_frame_rate)
1323 {
1324 ps_op->s_ive_op.u4_error_code |= 1
1325 << IVE_UNSUPPORTEDPARAM;
1326 ps_op->s_ive_op.u4_error_code |=
1327 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1328 return (IV_FAIL);
1329 }
1330
1331 break;
1332 }
1333
1334 case IVE_CMD_CTL_SET_BITRATE:
1335 {
1336 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1337 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1338
1339 if (ps_ip->s_ive_ip.u4_size
1340 != sizeof(ih264e_ctl_set_bitrate_ip_t))
1341 {
1342 ps_op->s_ive_op.u4_error_code |= 1
1343 << IVE_UNSUPPORTEDPARAM;
1344 ps_op->s_ive_op.u4_error_code |=
1345 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1346 return IV_FAIL;
1347 }
1348
1349 if (ps_op->s_ive_op.u4_size
1350 != sizeof(ih264e_ctl_set_bitrate_op_t))
1351 {
1352 ps_op->s_ive_op.u4_error_code |= 1
1353 << IVE_UNSUPPORTEDPARAM;
1354 ps_op->s_ive_op.u4_error_code |=
1355 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1356 return IV_FAIL;
1357 }
1358
1359 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE)
1360 || (ps_ip->s_ive_ip.u4_target_bitrate == 0))
1361 {
1362 ps_op->s_ive_op.u4_error_code |= 1
1363 << IVE_UNSUPPORTEDPARAM;
1364 ps_op->s_ive_op.u4_error_code |=
1365 IH264E_BITRATE_NOT_SUPPORTED;
1366 return (IV_FAIL);
1367 }
1368
1369 break;
1370 }
1371
1372 case IVE_CMD_CTL_SET_FRAMETYPE:
1373 {
1374 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1375 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1376
1377 if (ps_ip->s_ive_ip.u4_size
1378 != sizeof(ih264e_ctl_set_frame_type_ip_t))
1379 {
1380 ps_op->s_ive_op.u4_error_code |= 1
1381 << IVE_UNSUPPORTEDPARAM;
1382 ps_op->s_ive_op.u4_error_code |=
1383 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1384 return IV_FAIL;
1385 }
1386
1387 if (ps_op->s_ive_op.u4_size
1388 != sizeof(ih264e_ctl_set_frame_type_op_t))
1389 {
1390 ps_op->s_ive_op.u4_error_code |= 1
1391 << IVE_UNSUPPORTEDPARAM;
1392 ps_op->s_ive_op.u4_error_code |=
1393 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1394 return IV_FAIL;
1395 }
1396
1397 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME)
1398 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME)
1399 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME)
1400 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1401 {
1402 ps_op->s_ive_op.u4_error_code |= 1
1403 << IVE_UNSUPPORTEDPARAM;
1404 ps_op->s_ive_op.u4_error_code |=
1405 IH264E_INVALID_FORCE_FRAME_INPUT;
1406 return IV_FAIL;
1407 }
1408 break;
1409 }
1410
1411 case IVE_CMD_CTL_SET_ME_PARAMS:
1412 {
1413 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1414
1415 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1416 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
1417
1418 if (ps_ip->s_ive_ip.u4_size
1419 != sizeof(ih264e_ctl_set_me_params_ip_t))
1420 {
1421 ps_op->s_ive_op.u4_error_code |= 1
1422 << IVE_UNSUPPORTEDPARAM;
1423 ps_op->s_ive_op.u4_error_code |=
1424 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1425 return IV_FAIL;
1426 }
1427
1428 if (ps_op->s_ive_op.u4_size
1429 != sizeof(ih264e_ctl_set_me_params_op_t))
1430 {
1431 ps_op->s_ive_op.u4_error_code |= 1
1432 << IVE_UNSUPPORTEDPARAM;
1433 ps_op->s_ive_op.u4_error_code |=
1434 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1435 return IV_FAIL;
1436 }
1437
1438 if ((ps_ip->s_ive_ip.u4_me_speed_preset != FULL_SRCH)
1439 && (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1440 && (ps_ip->s_ive_ip.u4_me_speed_preset != HEX_SRCH))
1441 {
1442 ps_op->s_ive_op.u4_error_code |= 1
1443 << IVE_UNSUPPORTEDPARAM;
1444 ps_op->s_ive_op.u4_error_code |=
1445 IH264E_INVALID_ME_SPEED_PRESET;
1446 return IV_FAIL;
1447 }
1448
1449 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0)
1450 && (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1451 {
1452 ps_op->s_ive_op.u4_error_code |= 1
1453 << IVE_UNSUPPORTEDPARAM;
1454 ps_op->s_ive_op.u4_error_code |=
1455 IH264E_INVALID_HALFPEL_OPTION;
1456 return IV_FAIL;
1457 }
1458
1459 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0)
1460 && (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1461 {
1462 ps_op->s_ive_op.u4_error_code |= 1
1463 << IVE_UNSUPPORTEDPARAM;
1464 ps_op->s_ive_op.u4_error_code |=
1465 IH264E_INVALID_QPEL_OPTION;
1466 return IV_FAIL;
1467 }
1468
1469 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0)
1470 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1))
1471 {
1472 ps_op->s_ive_op.u4_error_code |= 1
1473 << IVE_UNSUPPORTEDPARAM;
1474 ps_op->s_ive_op.u4_error_code |=
1475 IH264E_INVALID_FAST_SAD_OPTION;
1476 return IV_FAIL;
1477 }
1478
1479 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255)
1480 {
1481 ps_op->s_ive_op.u4_error_code |= 1
1482 << IVE_UNSUPPORTEDPARAM;
1483 ps_op->s_ive_op.u4_error_code |=
1484 IH264E_INVALID_ALT_REF_OPTION;
1485 return IV_FAIL;
1486 }
1487
1488 if (ps_ip->s_ive_ip.u4_srch_rng_x
1489 > ps_codec->s_cfg.u4_max_srch_rng_x)
1490 {
1491 ps_op->s_ive_op.u4_error_code |= 1
1492 << IVE_UNSUPPORTEDPARAM;
1493 ps_op->s_ive_op.u4_error_code |=
1494 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1495 return (IV_FAIL);
1496 }
1497
1498 if (ps_ip->s_ive_ip.u4_srch_rng_y
1499 > ps_codec->s_cfg.u4_max_srch_rng_y)
1500 {
1501 ps_op->s_ive_op.u4_error_code |= 1
1502 << IVE_UNSUPPORTEDPARAM;
1503 ps_op->s_ive_op.u4_error_code |=
1504 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1505 return (IV_FAIL);
1506 }
1507
1508 break;
1509 }
1510
1511 case IVE_CMD_CTL_SET_IPE_PARAMS:
1512 {
1513 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1514 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1515
1516 if (ps_ip->s_ive_ip.u4_size
1517 != sizeof(ih264e_ctl_set_ipe_params_ip_t))
1518 {
1519 ps_op->s_ive_op.u4_error_code |= 1
1520 << IVE_UNSUPPORTEDPARAM;
1521 ps_op->s_ive_op.u4_error_code |=
1522 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1523 return IV_FAIL;
1524 }
1525
1526 if (ps_op->s_ive_op.u4_size
1527 != sizeof(ih264e_ctl_set_ipe_params_op_t))
1528 {
1529 ps_op->s_ive_op.u4_error_code |= 1
1530 << IVE_UNSUPPORTEDPARAM;
1531 ps_op->s_ive_op.u4_error_code |=
1532 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1533 return IV_FAIL;
1534 }
1535
1536 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0)
1537 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1538 {
1539 ps_op->s_ive_op.u4_error_code |= 1
1540 << IVE_UNSUPPORTEDPARAM;
1541 ps_op->s_ive_op.u4_error_code |=
1542 IH264E_INVALID_INTRA4x4_OPTION;
1543 return IV_FAIL;
1544 }
1545
1546 if ((ps_ip->s_ive_ip.u4_constrained_intra_pred != 0)
1547 && (ps_ip->s_ive_ip.u4_constrained_intra_pred != 1))
1548 {
1549 ps_op->s_ive_op.u4_error_code |= 1
1550 << IVE_UNSUPPORTEDPARAM;
1551 ps_op->s_ive_op.u4_error_code |=
1552 IH264E_INVALID_CONSTRAINED_INTRA_PREDICTION_MODE;
1553 return IV_FAIL;
1554 }
1555
1556 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG)
1557 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST)
1558 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL)
1559 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST)
1560 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED)
1561 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1562 {
1563 ps_op->s_ive_op.u4_error_code |= 1
1564 << IVE_UNSUPPORTEDPARAM;
1565 ps_op->s_ive_op.u4_error_code |=
1566 IH264E_INVALID_ENC_SPEED_PRESET;
1567 return IV_FAIL;
1568 }
1569
1570 break;
1571 }
1572
1573 case IVE_CMD_CTL_SET_GOP_PARAMS:
1574 {
1575 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1576 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1577
1578 if (ps_ip->s_ive_ip.u4_size
1579 != sizeof(ih264e_ctl_set_gop_params_ip_t))
1580 {
1581 ps_op->s_ive_op.u4_error_code |= 1
1582 << IVE_UNSUPPORTEDPARAM;
1583 ps_op->s_ive_op.u4_error_code |=
1584 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1585 return IV_FAIL;
1586 }
1587
1588 if (ps_op->s_ive_op.u4_size
1589 != sizeof(ih264e_ctl_set_gop_params_op_t))
1590 {
1591 ps_op->s_ive_op.u4_error_code |= 1
1592 << IVE_UNSUPPORTEDPARAM;
1593 ps_op->s_ive_op.u4_error_code |=
1594 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1595 return IV_FAIL;
1596 }
1597
1598 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1599 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1600 {
1601 ps_op->s_ive_op.u4_error_code |= 1
1602 << IVE_UNSUPPORTEDPARAM;
1603 ps_op->s_ive_op.u4_error_code |=
1604 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1605 return IV_FAIL;
1606 }
1607
1608 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1609 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1610 {
1611 ps_op->s_ive_op.u4_error_code |= 1
1612 << IVE_UNSUPPORTEDPARAM;
1613 ps_op->s_ive_op.u4_error_code |=
1614 IH264E_INVALID_IDR_FRAME_INTERVAL;
1615 return IV_FAIL;
1616 }
1617
1618 break;
1619 }
1620
1621 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
1622 {
1623 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1624 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1625
1626 if (ps_ip->s_ive_ip.u4_size
1627 != sizeof(ih264e_ctl_set_deblock_params_ip_t))
1628 {
1629 ps_op->s_ive_op.u4_error_code |= 1
1630 << IVE_UNSUPPORTEDPARAM;
1631 ps_op->s_ive_op.u4_error_code |=
1632 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1633 return IV_FAIL;
1634 }
1635
1636 if (ps_op->s_ive_op.u4_size
1637 != sizeof(ih264e_ctl_set_deblock_params_op_t))
1638 {
1639 ps_op->s_ive_op.u4_error_code |= 1
1640 << IVE_UNSUPPORTEDPARAM;
1641 ps_op->s_ive_op.u4_error_code |=
1642 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1643 return IV_FAIL;
1644 }
1645
1646 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0)
1647 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2)
1648 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3)
1649 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1650 {
1651 ps_op->s_ive_op.u4_error_code |= 1
1652 << IVE_UNSUPPORTEDPARAM;
1653 ps_op->s_ive_op.u4_error_code |=
1654 IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1655 return IV_FAIL;
1656 }
1657
1658 break;
1659 }
1660
1661 case IVE_CMD_CTL_SET_QP:
1662 {
1663 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1664 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op;
1665
1666 if (ps_ip->s_ive_ip.u4_size
1667 != sizeof(ih264e_ctl_set_qp_ip_t))
1668 {
1669 ps_op->s_ive_op.u4_error_code |= 1
1670 << IVE_UNSUPPORTEDPARAM;
1671 ps_op->s_ive_op.u4_error_code |=
1672 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1673 return IV_FAIL;
1674 }
1675
1676 if (ps_op->s_ive_op.u4_size
1677 != sizeof(ih264e_ctl_set_qp_op_t))
1678 {
1679 ps_op->s_ive_op.u4_error_code |= 1
1680 << IVE_UNSUPPORTEDPARAM;
1681 ps_op->s_ive_op.u4_error_code |=
1682 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1683 return IV_FAIL;
1684 }
1685
1686 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP)
1687 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP)
1688 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP))
1689 {
1690 ps_op->s_ive_op.u4_error_code |= 1
1691 << IVE_UNSUPPORTEDPARAM;
1692 ps_op->s_ive_op.u4_error_code |=
1693 IH264E_INVALID_MAX_FRAME_QP;
1694 return IV_FAIL;
1695 }
1696
1697 /* We donot support QP < 4 */
1698 if ((ps_ip->s_ive_ip.u4_i_qp_min < 4)
1699 || (ps_ip->s_ive_ip.u4_p_qp_min < 4)
1700 || (ps_ip->s_ive_ip.u4_b_qp_min < 4)
1701 || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max)
1702 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max)
1703 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max))
1704 {
1705 ps_op->s_ive_op.u4_error_code |= 1
1706 << IVE_UNSUPPORTEDPARAM;
1707 ps_op->s_ive_op.u4_error_code |=
1708 IH264E_INVALID_MIN_FRAME_QP;
1709 return IV_FAIL;
1710 }
1711
1712 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max)
1713 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max)
1714 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max))
1715 {
1716 ps_op->s_ive_op.u4_error_code |= 1
1717 << IVE_UNSUPPORTEDPARAM;
1718 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1719 return IV_FAIL;
1720 }
1721
1722 if ((ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min)
1723 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min)
1724 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min))
1725 {
1726 ps_op->s_ive_op.u4_error_code |= 1
1727 << IVE_UNSUPPORTEDPARAM;
1728 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1729 return IV_FAIL;
1730 }
1731
1732 break;
1733 }
1734
1735 case IVE_CMD_CTL_SET_VUI_PARAMS:
1736 {
1737 ih264e_vui_ip_t *ps_ip = pv_api_ip;
1738 ih264e_vui_op_t *ps_op = pv_api_op;
1739
1740 if(ps_ip->u4_size != sizeof(ih264e_vui_ip_t))
1741 {
1742 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1743 ps_op->u4_error_code |=
1744 IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1745 return IV_FAIL;
1746 }
1747
1748 if(ps_op->u4_size != sizeof(ih264e_vui_op_t))
1749 {
1750 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1751 ps_op->u4_error_code |=
1752 IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1753 return IV_FAIL;
1754 }
1755
1756 break;
1757 }
1758
1759 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
1760 {
1761 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
1762 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
1763
1764 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_ip_t))
1765 {
1766 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1767 ps_op->u4_error_code |=
1768 IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1769 return IV_FAIL;
1770 }
1771
1772 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_op_t))
1773 {
1774 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1775 ps_op->u4_error_code |=
1776 IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT;
1777 return IV_FAIL;
1778 }
1779
1780 if((ps_ip->u1_sei_mdcv_params_present_flag != 0)
1781 && (ps_ip->u1_sei_mdcv_params_present_flag) != 1)
1782 {
1783 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1784 ps_op->u4_error_code |=
1785 IH264E_INVALID_SEI_MDCV_PARAMS;
1786 return IV_FAIL;
1787 }
1788
1789 if(1 == ps_ip->u1_sei_mdcv_params_present_flag)
1790 {
1791 /* Check values for u2_display_primaries_x and u2_display_primaries_y */
1792 for(i = 0; i < 3; i++)
1793 {
1794 if((ps_ip->au2_display_primaries_x[i] >
1795 DISPLAY_PRIMARIES_X_UPPER_LIMIT) ||
1796 (ps_ip->au2_display_primaries_x[i] <
1797 DISPLAY_PRIMARIES_X_LOWER_LIMIT) ||
1798 ((ps_ip->au2_display_primaries_x[i] %
1799 DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0))
1800 {
1801 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1802 ps_op->u4_error_code |=
1803 IH264E_INVALID_SEI_MDCV_PARAMS;
1804 return IV_FAIL;
1805 }
1806
1807 if((ps_ip->au2_display_primaries_y[i] >
1808 DISPLAY_PRIMARIES_Y_UPPER_LIMIT) ||
1809 (ps_ip->au2_display_primaries_y[i] <
1810 DISPLAY_PRIMARIES_Y_LOWER_LIMIT) ||
1811 ((ps_ip->au2_display_primaries_y[i] %
1812 DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0))
1813 {
1814 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1815 ps_op->u4_error_code |=
1816 IH264E_INVALID_SEI_MDCV_PARAMS;
1817 return IV_FAIL;
1818 }
1819 }
1820
1821 if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) ||
1822 (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) ||
1823 ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0))
1824 {
1825 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1826 ps_op->u4_error_code |=
1827 IH264E_INVALID_SEI_MDCV_PARAMS;
1828 return IV_FAIL;
1829 }
1830
1831 if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) ||
1832 (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) ||
1833 ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0))
1834 {
1835 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1836 ps_op->u4_error_code |=
1837 IH264E_INVALID_SEI_MDCV_PARAMS;
1838 return IV_FAIL;
1839 }
1840
1841 if((ps_ip->u4_max_display_mastering_luminance >
1842 MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) ||
1843 (ps_ip->u4_max_display_mastering_luminance <
1844 MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) ||
1845 ((ps_ip->u4_max_display_mastering_luminance %
1846 MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0))
1847 {
1848 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1849 ps_op->u4_error_code |=
1850 IH264E_INVALID_SEI_MDCV_PARAMS;
1851 return IV_FAIL;
1852 }
1853
1854 if((ps_ip->u4_min_display_mastering_luminance >
1855 MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT ) ||
1856 (ps_ip->u4_min_display_mastering_luminance <
1857 MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT))
1858 {
1859 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1860 ps_op->u4_error_code |=
1861 IH264E_INVALID_SEI_MDCV_PARAMS;
1862 return IV_FAIL;
1863 }
1864
1865 if(ps_ip->u4_max_display_mastering_luminance <=
1866 ps_ip->u4_min_display_mastering_luminance)
1867 {
1868 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1869 ps_op->u4_error_code |=
1870 IH264E_INVALID_SEI_MDCV_PARAMS;
1871 return IV_FAIL;
1872 }
1873 }
1874 break;
1875 }
1876
1877 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
1878 {
1879 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
1880 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
1881
1882 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_ip_t))
1883 {
1884 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1885 ps_op->u4_error_code |=
1886 IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1887 return IV_FAIL;
1888 }
1889
1890 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_op_t))
1891 {
1892 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1893 ps_op->u4_error_code |=
1894 IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT;
1895 return IV_FAIL;
1896 }
1897
1898 if((ps_ip->u1_sei_cll_params_present_flag != 0)
1899 && (ps_ip->u1_sei_cll_params_present_flag != 1))
1900 {
1901 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1902 ps_op->u4_error_code |=
1903 IH264E_INVALID_SEI_CLL_PARAMS;
1904 return IV_FAIL;
1905 }
1906 break;
1907 }
1908
1909 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
1910 {
1911 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
1912 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
1913
1914 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_ip_t))
1915 {
1916 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1917 ps_op->u4_error_code |=
1918 IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1919 return IV_FAIL;
1920 }
1921
1922 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_op_t))
1923 {
1924 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1925 ps_op->u4_error_code |=
1926 IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT;
1927 return IV_FAIL;
1928 }
1929
1930 if((ps_ip->u1_sei_ave_params_present_flag != 0)
1931 && (ps_ip->u1_sei_ave_params_present_flag != 1))
1932 {
1933 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1934 ps_op->u4_error_code |=
1935 IH264E_INVALID_SEI_AVE_PARAMS;
1936 return IV_FAIL;
1937 }
1938
1939 if(1 == ps_ip->u1_sei_ave_params_present_flag)
1940 {
1941 if((0 == ps_ip->u4_ambient_illuminance))
1942 {
1943 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1944 ps_op->u4_error_code |=
1945 IH264E_INVALID_SEI_AVE_PARAMS;
1946 return IV_FAIL;
1947 }
1948
1949 if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT)
1950 {
1951 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1952 ps_op->u4_error_code |=
1953 IH264E_INVALID_SEI_AVE_PARAMS;
1954 return IV_FAIL;
1955 }
1956
1957 if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT)
1958 {
1959 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1960 ps_op->u4_error_code |=
1961 IH264E_INVALID_SEI_AVE_PARAMS;
1962 return IV_FAIL;
1963 }
1964 }
1965 break;
1966 }
1967
1968 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
1969 {
1970 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
1971 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
1972
1973 if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_ip_t))
1974 {
1975 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1976 ps_op->u4_error_code |=
1977 IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1978 return IV_FAIL;
1979 }
1980
1981 if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_op_t))
1982 {
1983 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1984 ps_op->u4_error_code |=
1985 IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT;
1986 return IV_FAIL;
1987 }
1988
1989 if((ps_ip->u1_sei_ccv_params_present_flag != 0)
1990 && (ps_ip->u1_sei_ccv_params_present_flag != 1))
1991 {
1992 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1993 ps_op->u4_error_code |=
1994 IH264E_INVALID_SEI_CCV_PARAMS;
1995 return IV_FAIL;
1996 }
1997
1998
1999 if(1 == ps_ip->u1_sei_ccv_params_present_flag)
2000 {
2001 if((ps_ip->u1_ccv_cancel_flag != 0)
2002 && (ps_ip->u1_ccv_cancel_flag != 1))
2003 {
2004 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2005 ps_op->u4_error_code |=
2006 IH264E_INVALID_SEI_CCV_PARAMS;
2007 return IV_FAIL;
2008 }
2009
2010 if(0 == ps_ip->u1_ccv_cancel_flag)
2011 {
2012 if((ps_ip->u1_ccv_persistence_flag != 0)
2013 && (ps_ip->u1_ccv_persistence_flag != 1))
2014 {
2015 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2016 ps_op->u4_error_code |=
2017 IH264E_INVALID_SEI_CCV_PARAMS;
2018 return IV_FAIL;
2019 }
2020 if((ps_ip->u1_ccv_primaries_present_flag != 0)
2021 && (ps_ip->u1_ccv_primaries_present_flag != 1))
2022 {
2023 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2024 ps_op->u4_error_code |=
2025 IH264E_INVALID_SEI_CCV_PARAMS;
2026 return IV_FAIL;
2027 }
2028 if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0)
2029 && (ps_ip->u1_ccv_min_luminance_value_present_flag != 1))
2030 {
2031 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2032 ps_op->u4_error_code |=
2033 IH264E_INVALID_SEI_CCV_PARAMS;
2034 return IV_FAIL;
2035 }
2036 if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0)
2037 && (ps_ip->u1_ccv_max_luminance_value_present_flag != 1))
2038 {
2039 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2040 ps_op->u4_error_code |=
2041 IH264E_INVALID_SEI_CCV_PARAMS;
2042 return IV_FAIL;
2043 }
2044 if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0)
2045 && (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1))
2046 {
2047 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2048 ps_op->u4_error_code |=
2049 IH264E_INVALID_SEI_CCV_PARAMS;
2050 return IV_FAIL;
2051 }
2052 if((ps_ip->u1_ccv_primaries_present_flag == 0)
2053 && (ps_ip->u1_ccv_min_luminance_value_present_flag == 0)
2054 && (ps_ip->u1_ccv_max_luminance_value_present_flag == 0)
2055 && (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0))
2056 {
2057 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2058 ps_op->u4_error_code |=
2059 IH264E_INVALID_SEI_CCV_PARAMS;
2060 return IV_FAIL;
2061 }
2062
2063 if((ps_ip->u1_ccv_reserved_zero_2bits != 0))
2064 {
2065 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2066 ps_op->u4_error_code |=
2067 IH264E_INVALID_SEI_CCV_PARAMS;
2068 return IV_FAIL;
2069 }
2070
2071 if(1 == ps_ip->u1_ccv_primaries_present_flag)
2072 {
2073 for(i = 0; i < 3; i++)
2074 {
2075 if((ps_ip->ai4_ccv_primaries_x[i] >
2076 CCV_PRIMARIES_X_UPPER_LIMIT) ||
2077 (ps_ip->ai4_ccv_primaries_x[i] <
2078 CCV_PRIMARIES_X_LOWER_LIMIT))
2079 {
2080 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2081 ps_op->u4_error_code |=
2082 IH264E_INVALID_SEI_CCV_PARAMS;
2083 return IV_FAIL;
2084 }
2085
2086 if((ps_ip->ai4_ccv_primaries_y[i] >
2087 CCV_PRIMARIES_Y_UPPER_LIMIT) ||
2088 (ps_ip->ai4_ccv_primaries_y[i] <
2089 CCV_PRIMARIES_Y_LOWER_LIMIT))
2090 {
2091 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2092 ps_op->u4_error_code |=
2093 IH264E_INVALID_SEI_CCV_PARAMS;
2094 return IV_FAIL;
2095 }
2096 }
2097 }
2098
2099 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
2100 (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag))
2101 {
2102 if((ps_ip->u4_ccv_avg_luminance_value <
2103 ps_ip->u4_ccv_min_luminance_value))
2104 {
2105 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2106 ps_op->u4_error_code |=
2107 IH264E_INVALID_SEI_CCV_PARAMS;
2108 return IV_FAIL;
2109 }
2110 }
2111
2112 if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) &&
2113 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2114 {
2115 if((ps_ip->u4_ccv_max_luminance_value <
2116 ps_ip->u4_ccv_min_luminance_value))
2117 {
2118 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2119 ps_op->u4_error_code |=
2120 IH264E_INVALID_SEI_CCV_PARAMS;
2121 return IV_FAIL;
2122 }
2123 }
2124 if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) &&
2125 (1 == ps_ip->u1_ccv_max_luminance_value_present_flag))
2126 {
2127 if((ps_ip->u4_ccv_max_luminance_value <
2128 ps_ip->u4_ccv_avg_luminance_value))
2129 {
2130 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
2131 ps_op->u4_error_code |=
2132 IH264E_INVALID_SEI_CCV_PARAMS;
2133 return IV_FAIL;
2134 }
2135 }
2136 }
2137 }
2138 break;
2139 }
2140
2141 case IVE_CMD_CTL_SET_ENC_MODE:
2142 {
2143 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
2144 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
2145
2146 if (ps_ip->s_ive_ip.u4_size
2147 != sizeof(ih264e_ctl_set_enc_mode_ip_t))
2148 {
2149 ps_op->s_ive_op.u4_error_code |= 1
2150 << IVE_UNSUPPORTEDPARAM;
2151 ps_op->s_ive_op.u4_error_code |=
2152 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2153 return IV_FAIL;
2154 }
2155
2156 if (ps_op->s_ive_op.u4_size
2157 != sizeof(ih264e_ctl_set_enc_mode_op_t))
2158 {
2159 ps_op->s_ive_op.u4_error_code |= 1
2160 << IVE_UNSUPPORTEDPARAM;
2161 ps_op->s_ive_op.u4_error_code |=
2162 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
2163 return IV_FAIL;
2164 }
2165
2166 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER)
2167 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
2168 {
2169 ps_op->s_ive_op.u4_error_code |= 1
2170 << IVE_UNSUPPORTEDPARAM;
2171 ps_op->s_ive_op.u4_error_code |=
2172 IH264E_INVALID_ENC_OPERATION_MODE;
2173 return IV_FAIL;
2174 }
2175
2176 break;
2177 }
2178
2179 case IVE_CMD_CTL_SET_VBV_PARAMS:
2180 {
2181 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
2182 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
2183
2184 if (ps_ip->s_ive_ip.u4_size
2185 != sizeof(ih264e_ctl_set_vbv_params_ip_t))
2186 {
2187 ps_op->s_ive_op.u4_error_code |= 1
2188 << IVE_UNSUPPORTEDPARAM;
2189 ps_op->s_ive_op.u4_error_code |=
2190 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2191 return IV_FAIL;
2192 }
2193
2194 if (ps_op->s_ive_op.u4_size
2195 != sizeof(ih264e_ctl_set_vbv_params_op_t))
2196 {
2197 ps_op->s_ive_op.u4_error_code |= 1
2198 << IVE_UNSUPPORTEDPARAM;
2199 ps_op->s_ive_op.u4_error_code |=
2200 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
2201 return IV_FAIL;
2202 }
2203
2204 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY)
2205 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY))
2206 {
2207 ps_op->s_ive_op.u4_error_code |= 1
2208 << IVE_UNSUPPORTEDPARAM;
2209 ps_op->s_ive_op.u4_error_code |=
2210 IH264E_INVALID_BUFFER_DELAY;
2211 return IV_FAIL;
2212 }
2213
2214 break;
2215 }
2216
2217 case IVE_CMD_CTL_SET_AIR_PARAMS:
2218 {
2219 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
2220 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
2221
2222 if (ps_ip->s_ive_ip.u4_size
2223 != sizeof(ih264e_ctl_set_air_params_ip_t))
2224 {
2225 ps_op->s_ive_op.u4_error_code |= 1
2226 << IVE_UNSUPPORTEDPARAM;
2227 ps_op->s_ive_op.u4_error_code |=
2228 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2229 return IV_FAIL;
2230 }
2231
2232 if (ps_op->s_ive_op.u4_size
2233 != sizeof(ih264e_ctl_set_air_params_op_t))
2234 {
2235 ps_op->s_ive_op.u4_error_code |= 1
2236 << IVE_UNSUPPORTEDPARAM;
2237 ps_op->s_ive_op.u4_error_code |=
2238 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
2239 return IV_FAIL;
2240 }
2241
2242 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE)
2243 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC)
2244 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
2245 {
2246 ps_op->s_ive_op.u4_error_code |= 1
2247 << IVE_UNSUPPORTEDPARAM;
2248 ps_op->s_ive_op.u4_error_code |=
2249 IH264E_INVALID_AIR_MODE;
2250 return IV_FAIL;
2251 }
2252
2253 if (ps_ip->s_ive_ip.u4_air_refresh_period == 0)
2254 {
2255 ps_op->s_ive_op.u4_error_code |= 1
2256 << IVE_UNSUPPORTEDPARAM;
2257 ps_op->s_ive_op.u4_error_code |=
2258 IH264E_INVALID_AIR_REFRESH_PERIOD;
2259 return IV_FAIL;
2260 }
2261
2262 break;
2263 }
2264
2265 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
2266 {
2267 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
2268 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
2269
2270 if (ps_ip->s_ive_ip.u4_size
2271 != sizeof(ih264e_ctl_set_profile_params_ip_t))
2272 {
2273 ps_op->s_ive_op.u4_error_code |= 1
2274 << IVE_UNSUPPORTEDPARAM;
2275 ps_op->s_ive_op.u4_error_code |=
2276 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2277 return IV_FAIL;
2278 }
2279
2280 if (ps_op->s_ive_op.u4_size
2281 != sizeof(ih264e_ctl_set_profile_params_op_t))
2282 {
2283 ps_op->s_ive_op.u4_error_code |= 1
2284 << IVE_UNSUPPORTEDPARAM;
2285 ps_op->s_ive_op.u4_error_code |=
2286 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
2287 return IV_FAIL;
2288 }
2289
2290 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
2291 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
2292 {
2293 ps_op->s_ive_op.u4_error_code |= 1
2294 << IVE_UNSUPPORTEDPARAM;
2295 ps_op->s_ive_op.u4_error_code |=
2296 IH264E_PROFILE_NOT_SUPPORTED;
2297 return IV_FAIL;
2298 }
2299
2300 if (ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
2301 {
2302 ps_op->s_ive_op.u4_error_code |= 1
2303 << IVE_UNSUPPORTEDPARAM;
2304 ps_op->s_ive_op.u4_error_code |=
2305 IH264E_INVALID_ENTROPY_CODING_MODE;
2306 return IV_FAIL;
2307 }
2308
2309 break;
2310 }
2311
2312 default:
2313 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2314 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
2315 return IV_FAIL;
2316 }
2317
2318 break;
2319 }
2320
2321 default:
2322 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
2323 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
2324 return IV_FAIL;
2325 }
2326
2327 return IV_SUCCESS;
2328 }
2329
2330 /**
2331 *******************************************************************************
2332 *
2333 * @brief update encoder configuration parameters
2334 *
2335 * @par Description:
2336 * updates encoder configuration parameters from the given config set.
2337 * Initialize/reinitialize codec parameters according to new configurations.
2338 *
2339 * @param[in] ps_codec
2340 * Pointer to codec context
2341 *
2342 * @param[in] ps_cfg
2343 * Pointer to config param set
2344 *
2345 * @remarks none
2346 *
2347 *******************************************************************************
2348 */
ih264e_codec_update_config(codec_t * ps_codec,cfg_params_t * ps_cfg)2349 IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec,
2350 cfg_params_t *ps_cfg)
2351 {
2352 /* config params */
2353 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
2354
2355 /* error status */
2356 IH264E_ERROR_T err = IH264E_SUCCESS;
2357
2358 /* temp var */
2359 UWORD32 u4_init_rc = 0;
2360
2361 /***********************/
2362 /* UPDATE CODEC CONFIG */
2363 /***********************/
2364 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS)
2365 {
2366 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd);
2367 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht);
2368
2369 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln
2370 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd
2371 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht)
2372 {
2373 ps_curr_cfg->u4_wd = wd_aln;
2374 ps_curr_cfg->u4_ht = ht_aln;
2375
2376 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd;
2377 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht;
2378
2379 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4;
2380 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4;
2381
2382 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD;
2383
2384 /* If number of MBs in a frame changes the air map also changes.
2385 * Hence recompute air map also reset air pic cnt */
2386 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE)
2387 {
2388 /* re-init the air map */
2389 ih264e_init_air_map(ps_codec);
2390
2391 /* reset air counter */
2392 ps_codec->i4_air_pic_cnt = -1;
2393 }
2394
2395 /* initialize mv bank buffer manager */
2396 err = ih264e_mv_buf_mgr_add_bufs(ps_codec);
2397 if (err != IH264E_SUCCESS)
2398 return err;
2399
2400 /* initialize ref bank buffer manager */
2401 err = ih264e_pic_buf_mgr_add_bufs(ps_codec);
2402 if (err != IH264E_SUCCESS)
2403 return err;
2404
2405 /* since dimension changed, start new sequence by forcing IDR */
2406 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2407
2408 /* in case dimension changes, we need to reinitialize RC as the
2409 * old model shall not fit further */
2410 u4_init_rc = 1;
2411
2412 /* when the dimension changes, the header needs to be regenerated */
2413 ps_codec->i4_gen_header = 1;
2414 }
2415 }
2416 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE)
2417 {
2418 /* temp var */
2419 UWORD32 u4_src_ticks, u4_tgt_ticks;
2420
2421 u4_src_ticks = ih264e_frame_time_get_src_ticks(
2422 ps_codec->s_rate_control.pps_frame_time);
2423
2424 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks(
2425 ps_codec->s_rate_control.pps_frame_time);
2426
2427 /* Change frame rate */
2428 if (ps_codec->s_cfg.u4_src_frame_rate
2429 != ps_cfg->u4_src_frame_rate * 1000)
2430 {
2431 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate
2432 * 1000;
2433
2434 ih264e_frame_time_update_src_frame_rate(
2435 ps_codec->s_rate_control.pps_frame_time,
2436 ps_codec->s_cfg.u4_src_frame_rate);
2437
2438 ih264_time_stamp_update_frame_rate(
2439 ps_codec->s_rate_control.pps_time_stamp,
2440 ps_codec->s_cfg.u4_src_frame_rate);
2441
2442 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2443 ps_codec->s_cfg.u4_src_frame_rate,
2444 u4_src_ticks, u4_tgt_ticks);
2445 }
2446
2447 if (ps_codec->s_cfg.u4_tgt_frame_rate
2448 != ps_cfg->u4_tgt_frame_rate * 1000)
2449 {
2450 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate
2451 * 1000;
2452
2453 ih264e_frame_time_update_tgt_frame_rate(
2454 ps_codec->s_rate_control.pps_frame_time,
2455 ps_codec->s_cfg.u4_tgt_frame_rate);
2456
2457 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
2458 ps_codec->s_cfg.u4_src_frame_rate,
2459 u4_src_ticks, u4_tgt_ticks);
2460
2461 irc_change_frm_rate_for_bit_alloc(
2462 ps_codec->s_rate_control.pps_rate_control_api,
2463 ps_codec->s_cfg.u4_tgt_frame_rate);
2464 }
2465
2466 }
2467 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE)
2468 {
2469 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate)
2470 {
2471 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode)
2472 irc_change_avg_bit_rate(
2473 ps_codec->s_rate_control.pps_rate_control_api,
2474 ps_cfg->u4_target_bitrate);
2475
2476 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate;
2477 }
2478 }
2479 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE)
2480 {
2481 switch (ps_cfg->e_frame_type)
2482 {
2483 case IV_I_FRAME:
2484 ps_codec->force_curr_frame_type = IV_I_FRAME;
2485 break;
2486
2487 case IV_IDR_FRAME:
2488 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2489 break;
2490
2491 case IV_P_FRAME:
2492 default:
2493 break;
2494 }
2495 }
2496 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS)
2497 {
2498 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2499 {
2500 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel;
2501 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2502 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset;
2503 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel;
2504 }
2505 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2506 {
2507 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2508 }
2509 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x;
2510 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y;
2511
2512 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref)
2513 {
2514 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref;
2515 ps_codec->u4_is_curr_frm_ref = 1;
2516 }
2517 }
2518 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS)
2519 {
2520 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset;
2521 ps_curr_cfg->u4_constrained_intra_pred = ps_cfg->u4_constrained_intra_pred;
2522 if (ps_curr_cfg->u4_enc_speed_preset == IVE_SLOWEST)
2523 {/* high quality */
2524 /* enable diamond search */
2525 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2526 ps_curr_cfg->u4_enable_fast_sad = 0;
2527
2528 /* disable intra 4x4 */
2529 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2530 ps_codec->luma_energy_compaction[1] =
2531 ih264e_code_luma_intra_macroblock_4x4_rdopt_on;
2532
2533 /* sub pel off */
2534 ps_curr_cfg->u4_enable_hpel = 1;
2535
2536 /* deblocking off */
2537 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2538
2539 /* disabled intra inter gating in Inter slices */
2540 ps_codec->u4_inter_gate = 0;
2541 }
2542 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_NORMAL)
2543 {/* normal */
2544 /* enable diamond search */
2545 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2546 ps_curr_cfg->u4_enable_fast_sad = 0;
2547
2548 /* disable intra 4x4 */
2549 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2550
2551 /* sub pel off */
2552 ps_curr_cfg->u4_enable_hpel = 1;
2553
2554 /* deblocking off */
2555 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2556
2557 /* disabled intra inter gating in Inter slices */
2558 ps_codec->u4_inter_gate = 0;
2559 }
2560 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FAST)
2561 {/* normal */
2562 /* enable diamond search */
2563 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2564 ps_curr_cfg->u4_enable_fast_sad = 0;
2565
2566 /* disable intra 4x4 */
2567 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2568
2569 /* sub pel off */
2570 ps_curr_cfg->u4_enable_hpel = 1;
2571
2572 /* deblocking off */
2573 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2574
2575 /* disabled intra inter gating in Inter slices */
2576 ps_codec->u4_inter_gate = 1;
2577 }
2578 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_HIGH_SPEED)
2579 {/* fast */
2580 /* enable diamond search */
2581 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2582 ps_curr_cfg->u4_enable_fast_sad = 0;
2583
2584 /* disable intra 4x4 */
2585 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2586
2587 /* sub pel off */
2588 ps_curr_cfg->u4_enable_hpel = 0;
2589
2590 /* deblocking off */
2591 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2592
2593 /* disabled intra inter gating in Inter slices */
2594 ps_codec->u4_inter_gate = 0;
2595 }
2596 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2597 {/* fastest */
2598 /* enable diamond search */
2599 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2600 //u4_num_layers = 4;
2601
2602 /* disable intra 4x4 */
2603 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2604
2605 /* sub pel off */
2606 ps_curr_cfg->u4_enable_hpel = 0;
2607
2608 /* deblocking off */
2609 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2610
2611 /* disabled intra inter gating in Inter slices */
2612 ps_codec->u4_inter_gate = 1;
2613 }
2614 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2615 {
2616 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4;
2617 }
2618 }
2619 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS)
2620 {
2621 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval)
2622 {
2623 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval;
2624
2625 /* reset air counter */
2626 ps_codec->i4_air_pic_cnt = -1;
2627
2628 /* re-init air map */
2629 ih264e_init_air_map(ps_codec);
2630
2631 /*Effect intra frame interval change*/
2632
2633 irc_change_intra_frm_int_call(
2634 ps_codec->s_rate_control.pps_rate_control_api,
2635 ps_curr_cfg->u4_i_frm_interval);
2636 }
2637
2638 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval;
2639
2640 }
2641 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS)
2642 {
2643 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2644 {
2645 ps_curr_cfg->u4_disable_deblock_level =
2646 ps_cfg->u4_disable_deblock_level;
2647 }
2648 }
2649 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP)
2650 {
2651 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2652 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2653
2654 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max;
2655 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min;
2656 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp;
2657
2658 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max;
2659 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min;
2660 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp;
2661
2662 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max;
2663 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min;
2664 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp;
2665
2666 /* update rc lib with modified qp */
2667 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2668 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2669 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2670
2671 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api,
2672 au1_init_qp);
2673
2674 au1_min_max_qp[2 * I_PIC] =
2675 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2676 au1_min_max_qp[2 * I_PIC + 1] =
2677 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2678
2679 au1_min_max_qp[2 * P_PIC] =
2680 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2681 au1_min_max_qp[2 * P_PIC + 1] =
2682 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2683
2684 au1_min_max_qp[2 * B_PIC] =
2685 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2686 au1_min_max_qp[2 * B_PIC + 1] =
2687 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2688
2689 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api,
2690 au1_min_max_qp);
2691 }
2692 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE)
2693 {
2694 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode;
2695
2696 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER)
2697 {
2698 ps_codec->i4_header_mode = 1;
2699 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE;
2700 }
2701 else
2702 {
2703 ps_codec->i4_header_mode = 0;
2704 }
2705 }
2706 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS
2707 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode)
2708 {
2709 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size;
2710 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay;
2711
2712 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay);
2713
2714 // TODO: remove this when the support for changing buffer dynamically
2715 // is yet to be added.
2716 u4_init_rc = 1;
2717 }
2718 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS)
2719 {
2720 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode
2721 || ps_curr_cfg->u4_air_refresh_period
2722 != ps_cfg->u4_air_refresh_period)
2723 {
2724 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode;
2725 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period;
2726
2727 ih264e_init_air_map(ps_codec);
2728
2729 /* reset air counter */
2730 ps_codec->i4_air_pic_cnt = -1;
2731 }
2732 }
2733 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS)
2734 {
2735 ps_codec->s_cfg.e_profile = ps_cfg->e_profile;
2736 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode;
2737 }
2738 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES)
2739 {
2740 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores;
2741 }
2742 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VUI_PARAMS)
2743 {
2744 ps_codec->s_cfg.s_vui = ps_cfg->s_vui;
2745 }
2746
2747 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_MDCV_PARAMS)
2748 {
2749 ps_codec->s_cfg.s_sei.u1_sei_mdcv_params_present_flag =
2750 ps_cfg->s_sei.u1_sei_mdcv_params_present_flag;
2751 ps_codec->s_cfg.s_sei.s_sei_mdcv_params = ps_cfg->s_sei.s_sei_mdcv_params;
2752 }
2753 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CLL_PARAMS)
2754 {
2755 ps_codec->s_cfg.s_sei.u1_sei_cll_params_present_flag =
2756 ps_cfg->s_sei.u1_sei_cll_params_present_flag;
2757 ps_codec->s_cfg.s_sei.s_sei_cll_params = ps_cfg->s_sei.s_sei_cll_params;
2758 }
2759 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_AVE_PARAMS)
2760 {
2761 ps_codec->s_cfg.s_sei.u1_sei_ave_params_present_flag =
2762 ps_cfg->s_sei.u1_sei_ave_params_present_flag;
2763 ps_codec->s_cfg.s_sei.s_sei_ave_params = ps_cfg->s_sei.s_sei_ave_params;
2764 }
2765 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CCV_PARAMS)
2766 {
2767 ps_codec->s_cfg.s_sei.u1_sei_ccv_params_present_flag =
2768 ps_cfg->s_sei.u1_sei_ccv_params_present_flag;
2769 ps_codec->s_cfg.s_sei.s_sei_ccv_params = ps_cfg->s_sei.s_sei_ccv_params;
2770 }
2771
2772 /* reset RC model */
2773 if (u4_init_rc)
2774 {
2775 /* init qp */
2776 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2777
2778 /* min max qp */
2779 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2780
2781 /* init i,p,b qp */
2782 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2783 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2784 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2785
2786 /* init min max qp */
2787 au1_min_max_qp[2 * I_PIC] =
2788 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2789 au1_min_max_qp[2 * I_PIC + 1] =
2790 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2791
2792 au1_min_max_qp[2 * P_PIC] =
2793 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2794 au1_min_max_qp[2 * P_PIC + 1] =
2795 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2796
2797 au1_min_max_qp[2 * B_PIC] =
2798 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2799 au1_min_max_qp[2 * B_PIC + 1] =
2800 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2801
2802 /* get rc mode */
2803 switch (ps_codec->s_cfg.e_rc_mode)
2804 {
2805 case IVE_RC_STORAGE:
2806 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE;
2807 break;
2808
2809 case IVE_RC_CBR_NON_LOW_DELAY:
2810 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC;
2811 break;
2812
2813 case IVE_RC_CBR_LOW_DELAY:
2814 ps_codec->s_rate_control.e_rc_type = CBR_LDRC;
2815 break;
2816
2817 case IVE_RC_NONE:
2818 ps_codec->s_rate_control.e_rc_type = CONST_QP;
2819 break;
2820
2821 default:
2822 break;
2823 }
2824
2825 /* init rate control */
2826 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api,
2827 ps_codec->s_rate_control.pps_frame_time,
2828 ps_codec->s_rate_control.pps_time_stamp,
2829 ps_codec->s_rate_control.pps_pd_frm_rate,
2830 ps_codec->s_cfg.u4_max_framerate,
2831 ps_codec->s_cfg.u4_src_frame_rate,
2832 ps_codec->s_cfg.u4_tgt_frame_rate,
2833 ps_codec->s_rate_control.e_rc_type,
2834 ps_codec->s_cfg.u4_target_bitrate,
2835 ps_codec->s_cfg.u4_max_bitrate,
2836 ps_codec->s_cfg.u4_vbv_buffer_delay,
2837 ps_codec->s_cfg.u4_i_frm_interval,
2838 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp,
2839 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp,
2840 ps_codec->s_cfg.u4_max_level);
2841 }
2842
2843 return err;
2844 }
2845
2846 /**
2847 *******************************************************************************
2848 *
2849 * @brief
2850 * Sets default encoder config parameters
2851 *
2852 * @par Description:
2853 * Sets default dynamic parameters. Will be called in ih264e_init() to ensure
2854 * that even if set_params is not called, codec continues to work
2855 *
2856 * @param[in] ps_cfg
2857 * Pointer to encoder config params
2858 *
2859 * @returns error status
2860 *
2861 * @remarks none
2862 *
2863 *******************************************************************************
2864 */
ih264e_set_default_params(cfg_params_t * ps_cfg)2865 static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg)
2866 {
2867 WORD32 ret = IV_SUCCESS;
2868
2869 ps_cfg->u4_max_wd = MAX_WD;
2870 ps_cfg->u4_max_ht = MAX_HT;
2871 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
2872 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
2873 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
2874 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
2875 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
2876 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
2877 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
2878 ps_cfg->e_rc_mode = DEFAULT_RC;
2879 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
2880 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE;
2881 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
2882 ps_cfg->e_content_type = IV_PROGRESSIVE;
2883 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
2884 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
2885 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
2886 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
2887 ps_cfg->e_arch = ih264e_default_arch();
2888 ps_cfg->e_soc = SOC_GENERIC;
2889 ps_cfg->u4_disp_wd = MAX_WD;
2890 ps_cfg->u4_disp_ht = MAX_HT;
2891 ps_cfg->u4_wd = MAX_WD;
2892 ps_cfg->u4_ht = MAX_HT;
2893 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
2894 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
2895 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE;
2896 ps_cfg->e_frame_type = IV_NA_FRAME;
2897 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
2898 ps_cfg->u4_i_qp = DEFAULT_I_QP;
2899 ps_cfg->u4_p_qp = DEFAULT_P_QP;
2900 ps_cfg->u4_b_qp = DEFAULT_B_QP;
2901 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN;
2902 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX;
2903 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN;
2904 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX;
2905 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN;
2906 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX;
2907 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
2908 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
2909 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY;
2910 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE;
2911 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
2912 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
2913 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
2914 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
2915 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
2916 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2917 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2918 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2919 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2920 ps_cfg->i4_min_sad =
2921 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ?
2922 DEFAULT_MIN_SAD_ENABLE :
2923 DEFAULT_MIN_SAD_DISABLE;
2924 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2925 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2926 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2927 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
2928 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2929 ps_cfg->e_profile = DEFAULT_PROFILE;
2930 ps_cfg->u4_timestamp_low = 0;
2931 ps_cfg->u4_timestamp_high = 0;
2932 ps_cfg->u4_is_valid = 1;
2933 ps_cfg->e_cmd = IVE_CMD_CT_NA;
2934 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2935 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2936 ps_cfg->u4_entropy_coding_mode = CAVLC;
2937 ps_cfg->u4_weighted_prediction = 0;
2938 ps_cfg->u4_constrained_intra_pred = 0;
2939 ps_cfg->u4_pic_info_type = 0;
2940 ps_cfg->u4_mb_info_type = 0;
2941 ps_cfg->s_vui.u1_video_signal_type_present_flag = 1;
2942 ps_cfg->s_vui.u1_colour_description_present_flag = 1;
2943
2944 return ret;
2945 }
2946
2947 /**
2948 *******************************************************************************
2949 *
2950 * @brief
2951 * Initialize encoder context. This will be called by init_mem_rec and during
2952 * codec reset
2953 *
2954 * @par Description:
2955 * Initializes the context
2956 *
2957 * @param[in] ps_codec
2958 * Codec context pointer
2959 *
2960 * @returns error status
2961 *
2962 * @remarks none
2963 *
2964 *******************************************************************************
2965 */
ih264e_init(codec_t * ps_codec)2966 static WORD32 ih264e_init(codec_t *ps_codec)
2967 {
2968 /* enc config param set */
2969 cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2970
2971 /* temp var */
2972 WORD32 i;
2973
2974 /* coded pic count */
2975 ps_codec->i4_poc = 0;
2976
2977 /* Number of API calls to encode are made */
2978 ps_codec->i4_encode_api_call_cnt = -1;
2979
2980 /* Indicates no header has been generated yet */
2981 ps_codec->u4_header_generated = 0;
2982
2983 /* Number of pictures encoded */
2984 ps_codec->i4_pic_cnt = -1;
2985
2986 /* Number of threads created */
2987 ps_codec->i4_proc_thread_cnt = 0;
2988
2989 /* ctl mutex init */
2990 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2991
2992 /* Set encoder chroma format */
2993 ps_codec->e_codec_color_format =
2994 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ?
2995 IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2996
2997 /* Number of continuous frames where deblocking was disabled */
2998 ps_codec->i4_disable_deblk_pic_cnt = 0;
2999
3000 /* frame num */
3001 ps_codec->i4_frame_num = 0;
3002
3003 /* set the current frame type to I frame, since we are going to start encoding*/
3004 ps_codec->force_curr_frame_type = IV_NA_FRAME;
3005
3006 /* idr_pic_id */
3007 ps_codec->i4_idr_pic_id = -1;
3008
3009 /* Flush mode */
3010 ps_codec->i4_flush_mode = 0;
3011
3012 /* Encode header mode */
3013 ps_codec->i4_header_mode = 0;
3014
3015 /* Encode generate header */
3016 ps_codec->i4_gen_header = 0;
3017
3018 /* To signal successful completion of init */
3019 ps_codec->i4_init_done = 1;
3020
3021 /* To signal that at least one picture was decoded */
3022 ps_codec->i4_first_pic_done = 0;
3023
3024 /* Reset Codec */
3025 ps_codec->i4_reset_flag = 0;
3026
3027 /* Current error code */
3028 ps_codec->i4_error_code = IH264E_SUCCESS;
3029
3030 /* threshold residue */
3031 ps_codec->u4_thres_resi = 1;
3032
3033 /* inter gating enable */
3034 ps_codec->u4_inter_gate = 0;
3035
3036 /* entropy mutex init */
3037 ithread_mutex_init(ps_codec->pv_entropy_mutex);
3038
3039 /* sps id */
3040 ps_codec->i4_sps_id = 0;
3041
3042 /* sps id */
3043 ps_codec->i4_pps_id = 0;
3044
3045 /* Process thread created status */
3046 memset(ps_codec->ai4_process_thread_created, 0, MAX_PROCESS_THREADS);
3047
3048 /* Number of MBs processed together */
3049 ps_codec->i4_proc_nmb = 8;
3050
3051 /* Previous POC msb */
3052 ps_codec->i4_prev_poc_msb = 0;
3053
3054 /* Previous POC lsb */
3055 ps_codec->i4_prev_poc_lsb = -1;
3056
3057 /* max Previous POC lsb */
3058 ps_codec->i4_max_prev_poc_lsb = -1;
3059
3060 /* sps, pps status */
3061 {
3062 sps_t *ps_sps = ps_codec->ps_sps_base;
3063 pps_t *ps_pps = ps_codec->ps_pps_base;
3064
3065 for (i = 0; i < MAX_SPS_CNT; i++)
3066 {
3067 ps_sps->i1_sps_valid = 0;
3068 ps_sps++;
3069 }
3070
3071 for (i = 0; i < MAX_PPS_CNT; i++)
3072 {
3073 ps_pps->i1_pps_valid = 0;
3074 ps_pps++;
3075 }
3076 }
3077
3078 {
3079 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs;
3080
3081 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3082 WORD32 clz;
3083
3084 /* Use next power of two number of entries*/
3085 clz = CLZ(num_jobs);
3086 num_jobs = 1 << (32 - clz);
3087
3088 /* init process jobq */
3089 ps_codec->pv_proc_jobq = ih264_list_init(
3090 ps_codec->pv_proc_jobq_buf,
3091 ps_codec->i4_proc_jobq_buf_size, num_jobs,
3092 sizeof(job_t), 10);
3093 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
3094 ih264_list_reset(ps_codec->pv_proc_jobq);
3095
3096 /* init entropy jobq */
3097 ps_codec->pv_entropy_jobq = ih264_list_init(
3098 ps_codec->pv_entropy_jobq_buf,
3099 ps_codec->i4_entropy_jobq_buf_size, num_jobs,
3100 sizeof(job_t), 10);
3101 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
3102 ih264_list_reset(ps_codec->pv_entropy_jobq);
3103 }
3104
3105 /* Update the jobq context to all the threads */
3106 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3107 {
3108 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
3109 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
3110
3111 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
3112 ps_codec->as_process[i].i4_id =
3113 (i >= MAX_PROCESS_THREADS) ?
3114 (i - MAX_PROCESS_THREADS) : i;
3115 ps_codec->as_process[i].ps_codec = ps_codec;
3116
3117 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
3118 ps_codec->as_process[i].s_entropy.pv_entropy_jobq =
3119 ps_codec->pv_entropy_jobq;
3120 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
3121 }
3122
3123 /* Initialize MV Bank buffer manager */
3124 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base);
3125
3126 /* Initialize Picture buffer manager for reference buffers*/
3127 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(
3128 ps_codec->pv_ref_buf_mgr_base);
3129
3130 /* Initialize Picture buffer manager for input buffers*/
3131 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(
3132 ps_codec->pv_inp_buf_mgr_base);
3133
3134 /* Initialize buffer manager for output buffers*/
3135 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(
3136 ps_codec->pv_out_buf_mgr_base);
3137
3138 /* buffer cnt in buffer manager */
3139 ps_codec->i4_inp_buf_cnt = 0;
3140 ps_codec->i4_out_buf_cnt = 0;
3141 ps_codec->i4_ref_buf_cnt = 0;
3142
3143 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base;
3144 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
3145
3146 /* Initialize dpb manager */
3147 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr);
3148
3149 memset(ps_codec->as_ref_set, 0,
3150 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS));
3151 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++)
3152 {
3153 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
3154 }
3155
3156 /* fn ptr init */
3157 ih264e_init_function_ptr(ps_codec);
3158
3159 /* reset status flags */
3160 for (i = 0; i < MAX_CTXT_SETS; i++)
3161 {
3162 ps_codec->au4_entropy_thread_active[i] = 0;
3163 ps_codec->ai4_pic_cnt[i] = -1;
3164
3165 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
3166 ps_codec->s_rate_control.post_encode_skip[i] = 0;
3167 }
3168
3169 ps_codec->s_rate_control.num_intra_in_prev_frame = 0;
3170 ps_codec->s_rate_control.i4_avg_activity = 0;
3171
3172 return IV_SUCCESS;
3173 }
3174
3175 /**
3176 *******************************************************************************
3177 *
3178 * @brief
3179 * Gets number of memory records required by the codec
3180 *
3181 * @par Description:
3182 * Gets codec memory requirements
3183 *
3184 * @param[in] pv_api_ip
3185 * Pointer to input argument structure
3186 *
3187 * @param[out] pv_api_op
3188 * Pointer to output argument structure
3189 *
3190 * @returns status
3191 *
3192 * @remarks
3193 *
3194 *******************************************************************************
3195 */
ih264e_get_num_rec(void * pv_api_ip,void * pv_api_op)3196 static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op)
3197 {
3198 /* api call I/O structures */
3199 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
3200
3201 UNUSED(pv_api_ip);
3202
3203 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3204
3205 return IV_SUCCESS;
3206 }
3207
3208 /**
3209 *******************************************************************************
3210 *
3211 * @brief
3212 * Fills memory records of the codec
3213 *
3214 * @par Description:
3215 * Fills codec memory requirements
3216 *
3217 * @param[in] pv_api_ip
3218 * Pointer to input argument structure
3219 *
3220 * @param[out] pv_api_op
3221 * Pointer to output argument structure
3222 *
3223 * @returns error status
3224 *
3225 * @remarks none
3226 *
3227 *******************************************************************************
3228 */
ih264e_fill_num_mem_rec(void * pv_api_ip,void * pv_api_op)3229 static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
3230 {
3231 /* api call I/O structures */
3232 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
3233 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
3234
3235 /* profile / level info */
3236 WORD32 level;
3237 WORD32 num_reorder_frames;
3238 WORD32 num_ref_frames;
3239
3240 /* mem records */
3241 WORD32 no_of_mem_rec;
3242 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3243
3244 /* frame dimensions */
3245 WORD32 max_wd_luma, max_ht_luma;
3246 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3247
3248 /* temp var */
3249 WORD32 i;
3250
3251 /* error status */
3252 IV_STATUS_T status = IV_SUCCESS;
3253
3254 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3255 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
3256
3257 /* mem records */
3258 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3259 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
3260
3261 /* frame dimensions */
3262 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht;
3263 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd;
3264 max_ht_luma = ALIGN16(max_ht_luma);
3265 max_wd_luma = ALIGN16(max_wd_luma);
3266 max_mb_rows = max_ht_luma / MB_SIZE;
3267 max_mb_cols = max_wd_luma / MB_SIZE;
3268 max_mb_cnt = max_mb_rows * max_mb_cols;
3269
3270 /* profile / level info */
3271 level = ih264e_get_min_level(max_ht_luma, max_wd_luma);
3272
3273 /* validate params */
3274 if ((level < MIN_LEVEL) || (level > MAX_LEVEL))
3275 {
3276 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3277 level = MAX_LEVEL;
3278 }
3279
3280 if (num_ref_frames > MAX_REF_CNT)
3281 {
3282 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3283 num_ref_frames = MAX_REF_CNT;
3284 }
3285
3286 if (num_reorder_frames > MAX_REF_CNT)
3287 {
3288 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3289 num_reorder_frames = MAX_REF_CNT;
3290 }
3291
3292 /* Set all memory records as persistent and alignment as 128 by default */
3293 ps_mem_rec = ps_mem_rec_base;
3294 for (i = 0; i < no_of_mem_rec; i++)
3295 {
3296 ps_mem_rec->u4_mem_alignment = 128;
3297 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
3298 ps_mem_rec++;
3299 }
3300
3301 /************************************************************************
3302 * Request memory for h264 encoder handle *
3303 ***********************************************************************/
3304 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
3305 {
3306 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
3307 }
3308 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
3309
3310 /************************************************************************
3311 * Request memory for h264 encoder context *
3312 ***********************************************************************/
3313 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
3314 {
3315 ps_mem_rec->u4_mem_size = sizeof(codec_t);
3316 }
3317 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
3318
3319 /************************************************************************
3320 * Request memory for CABAC context *
3321 ***********************************************************************/
3322 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
3323 {
3324 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t);
3325 }
3326 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
3327
3328 /************************************************************************
3329 * Request memory for CABAC MB info *
3330 ***********************************************************************/
3331 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
3332 {
3333 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1)
3334 * sizeof(mb_info_ctxt_t);
3335 }
3336 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
3337
3338
3339 /************************************************************************
3340 * Request memory for entropy context *
3341 * In multi core encoding, each row is assumed to be launched on a *
3342 * thread. The rows below can only start after its neighbors are coded *
3343 * The status of an mb coded/uncoded is signaled via entropy map. *
3344 * 1. One word32 to store skip run cnt *
3345 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
3346 * of the entropy map is max mb cols. Further allocate one *
3347 * more additional row to evade checking for row -1. *
3348 * 3. size of bit stream buffer to store bit stream ctxt. *
3349 * 4. Entropy coding is dependent on nnz coefficient count for *
3350 * the neighbor blocks. It is sufficient to maintain one row *
3351 * worth of nnz as entropy for lower row waits on entropy map*
3352 ************************************************************************/
3353 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
3354 {
3355 /* total size of the mem record */
3356 WORD32 total_size = 0;
3357
3358 /* size of skip mb run */
3359 total_size += sizeof(WORD32);
3360 total_size = ALIGN8(total_size);
3361
3362 /* size in bytes to store entropy status of an entire frame */
3363 total_size += (max_mb_cols * max_mb_rows);
3364 /* add an additional 1 row of bytes to evade the special case of row 0 */
3365 total_size += max_mb_cols;
3366 total_size = ALIGN128(total_size);
3367
3368 /* size of bit stream buffer */
3369 total_size += sizeof(bitstrm_t);
3370 total_size = ALIGN128(total_size);
3371
3372 /* top nnz luma */
3373 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3374 total_size = ALIGN128(total_size);
3375
3376 /* top nnz cbcr */
3377 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
3378 total_size = ALIGN128(total_size);
3379
3380 /* total size per each proc ctxt */
3381 total_size *= MAX_CTXT_SETS;
3382
3383 ps_mem_rec->u4_mem_size = total_size;
3384 }
3385 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
3386
3387 /************************************************************************
3388 * The residue coefficients that needs to be entropy coded are packed *
3389 * at a buffer space by the proc threads. The entropy thread shall *
3390 * read from the buffer space, unpack them and encode the same. The *
3391 * buffer space required to pack a row of mbs are as follows. *
3392 * Assuming transform_8x8_flag is disabled, *
3393 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
3394 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
3395 * by 8 ac 4x4 chroma sub blocks. *
3396 * For the sake of simplicity we assume that all sub blocks are of *
3397 * type 4x4. The packing of each 4x4 is depicted by the structure *
3398 * tu_sblk_coeff_data_t *
3399 ************************************************************************/
3400 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
3401 {
3402 /* temp var */
3403 WORD32 size = 0;
3404
3405 /* size of coeff data of 1 mb */
3406 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3407
3408 /* size of coeff data of 1 row of mb's */
3409 size *= max_mb_cols;
3410
3411 /* align to avoid any false sharing across threads */
3412 size = ALIGN64(size);
3413
3414 /* size for one full frame */
3415 size *= max_mb_rows;
3416
3417 /* size of each proc buffer set (ping, pong) */
3418 size *= MAX_CTXT_SETS;
3419
3420 ps_mem_rec->u4_mem_size = size;
3421 }
3422 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
3423
3424 /************************************************************************
3425 * while encoding an mb, the mb header data is signaled to the entropy*
3426 * thread by writing to a buffer space. the size of header data per mb *
3427 * is assumed to be 40 bytes *
3428 * TODO: revisit this inference *
3429 ************************************************************************/
3430 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
3431 {
3432 /* temp var */
3433 WORD32 size;
3434
3435 /* size per MB */
3436 size = 40;
3437
3438 /* size for 1 row of mbs */
3439 size = size * max_mb_cols;
3440
3441 /* align to avoid any false sharing across threads */
3442 size = ALIGN64(size);
3443
3444 /* size for one full frame */
3445 size *= max_mb_rows;
3446
3447 /* size of each proc buffer set (ping, pong) */
3448 size *= MAX_CTXT_SETS;
3449
3450 ps_mem_rec->u4_mem_size = size;
3451 }
3452 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
3453
3454 /************************************************************************
3455 * Size for holding mv_buf_t for each MV Bank. *
3456 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3457 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3458 * max_dpb_size will be based on max_wd and max_ht *
3459 * For higher max_wd and max_ht this number will be smaller than *
3460 * MAX_DPB_SIZE But during actual initialization number of buffers *
3461 * allocated can be more. *
3462 * *
3463 * One extra MV Bank is needed to hold current pics MV bank. *
3464 * Since this is only a structure allocation and not actual buffer *
3465 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3466 ************************************************************************/
3467 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
3468 {
3469 /* max luma samples */
3470 WORD32 max_luma_samples = 0;
3471
3472 /* determine max luma samples */
3473 for (i = 0; i < 16; i++)
3474 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc)
3475 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs
3476 << (BLK_SIZE + BLK_SIZE);
3477
3478 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3479
3480 /************************************************************************
3481 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank *
3482 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3483 * is set to maximum number of luma samples allowed at the given level. *
3484 * This is done to ensure that any stream with width and height lesser *
3485 * than max_wd and max_ht is supported. Number of buffers required can *
3486 * be greater for lower width and heights at a given level and this *
3487 * increased number of buffers might require more memory than what *
3488 * max_wd and max_ht buffer would have required Also note one extra *
3489 * buffer is allocated to store current pictures MV bank. *
3490 ***********************************************************************/
3491
3492 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t);
3493
3494 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames
3495 + MAX_CTXT_SETS)
3496 * ih264e_get_pic_mv_bank_size(max_luma_samples);
3497 }
3498 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
3499
3500 /************************************************************************
3501 * While encoding inter slices, to compute the cost of encoding an mb *
3502 * with the mv's at hand, we employ the expression cost = sad + lambda *
3503 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
3504 * nt the mv in the stream. The mv bits for all the possible mv are *
3505 * stored in the look up table. The mem record for this look up table *
3506 * is given below. *
3507 ************************************************************************/
3508 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
3509 {
3510 /* max srch range x */
3511 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3512
3513 /* max srch range y */
3514 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3515
3516 /* max srch range */
3517 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3518
3519 /* due to subpel */
3520 u4_max_srch_range <<= 2;
3521
3522 /* due to mv on either direction */
3523 u4_max_srch_range = (u4_max_srch_range << 1);
3524
3525 /* due to pred mv + zero */
3526 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3527
3528 u4_max_srch_range = ALIGN128(u4_max_srch_range);
3529
3530 ps_mem_rec->u4_mem_size = u4_max_srch_range;
3531 }
3532 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
3533
3534 /************************************************************************
3535 * Request memory for SPS *
3536 ***********************************************************************/
3537 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3538 {
3539 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
3540 }
3541 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size);
3542
3543 /************************************************************************
3544 * Request memory for PPS *
3545 ***********************************************************************/
3546 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3547 {
3548 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
3549 }
3550 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size);
3551
3552 /************************************************************************
3553 * Request memory for Slice Header *
3554 ***********************************************************************/
3555 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3556 {
3557 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT
3558 * sizeof(slice_header_t);
3559 }
3560 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
3561
3562 /************************************************************************
3563 * Request memory for Adaptive Intra Refresh *
3564 ***********************************************************************/
3565 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3566 {
3567 /* total size of the mem record */
3568 WORD32 total_size = 0;
3569
3570 /* intra coded map */
3571 total_size += max_mb_cnt;
3572 total_size *= MAX_CTXT_SETS;
3573
3574 /* mb refresh map */
3575 total_size += sizeof(UWORD16) * max_mb_cnt;
3576
3577 /* alignment */
3578 total_size = ALIGN128(total_size);
3579
3580 ps_mem_rec->u4_mem_size = total_size;
3581 }
3582 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
3583
3584 /************************************************************************
3585 * In multi slice encoding, this memory record helps tracking the start*
3586 * of slice with reference to mb. *
3587 * MEM RECORD for holding *
3588 * 1. mb slice map *
3589 ************************************************************************/
3590 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3591 {
3592 /* total size of the mem record */
3593 WORD32 total_size = 0;
3594
3595 /* size in bytes to slice index of all mbs of a frame */
3596 total_size = ALIGN64(max_mb_cnt);
3597
3598 /* ih264e_update_proc_ctxt can overread by 1 at the end */
3599 total_size += 1;
3600
3601 /* total size per each proc ctxt */
3602 total_size *= MAX_CTXT_SETS;
3603 ps_mem_rec->u4_mem_size = total_size;
3604 }
3605 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
3606
3607 /************************************************************************
3608 * Request memory to hold thread handles for each processing thread *
3609 ************************************************************************/
3610 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3611 {
3612 WORD32 handle_size = ithread_get_handle_size();
3613
3614 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
3615 }
3616 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
3617
3618 /************************************************************************
3619 * Request memory to hold mutex for control calls *
3620 ************************************************************************/
3621 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3622 {
3623 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3624 }
3625 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
3626
3627 /************************************************************************
3628 * Request memory to hold mutex for entropy calls *
3629 ************************************************************************/
3630 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3631 {
3632 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3633 }
3634 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
3635
3636 /************************************************************************
3637 * Request memory to hold process jobs *
3638 ***********************************************************************/
3639 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3640 {
3641 /* One process job per row of MBs */
3642 /* Allocate for two pictures, so that wrap around can be handled easily */
3643 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3644
3645 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3646
3647 ps_mem_rec->u4_mem_size = job_queue_size;
3648 }
3649 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
3650
3651 /************************************************************************
3652 * Request memory to hold entropy jobs *
3653 ***********************************************************************/
3654 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3655 {
3656 /* One process job per row of MBs */
3657 /* Allocate for two pictures, so that wrap around can be handled easily */
3658 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
3659
3660 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3661
3662 ps_mem_rec->u4_mem_size = job_queue_size;
3663 }
3664 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
3665
3666 /************************************************************************
3667 * In multi core encoding, each row is assumed to be launched on a *
3668 * thread. The rows below can only start after its neighbors are coded *
3669 * The status of an mb coded/uncoded is signaled via proc map. *
3670 * MEM RECORD for holding *
3671 * 1. mb proc map (mb status core coded/uncoded) *
3672 ************************************************************************/
3673 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3674 {
3675 /* total size of the mem record */
3676 WORD32 total_size = 0;
3677
3678 /* size in bytes to mb core coding status of an entire frame */
3679 total_size = max_mb_cnt;
3680
3681 /* add an additional 1 row of bytes to evade the special case of row 0 */
3682 total_size += max_mb_cols;
3683
3684 /* total size per each proc ctxt */
3685 total_size *= MAX_CTXT_SETS;
3686 ps_mem_rec->u4_mem_size = total_size;
3687 }
3688 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
3689
3690 /************************************************************************
3691 * mem record for holding a particular MB is deblocked or not *
3692 * 1. mb deblk map (mb status deblocked/not deblocked) *
3693 ************************************************************************/
3694 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3695 {
3696 /* total size of the mem record */
3697 WORD32 total_size = 0;
3698
3699 /* size in bytes to mb core coding status of an entire frame */
3700 total_size = max_mb_cnt;
3701
3702 /* add an additional 1 row of bytes to evade the special case of row 0 */
3703 total_size += max_mb_cols;
3704
3705 total_size = ALIGN64(total_size);
3706
3707 /* total size per each proc ctxt */
3708 total_size *= MAX_CTXT_SETS;
3709 ps_mem_rec->u4_mem_size = total_size;
3710 }
3711 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
3712
3713 /************************************************************************
3714 * mem record for holding a particular MB's me is done or not *
3715 * 1. mb me map *
3716 ************************************************************************/
3717 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
3718 {
3719 /* total size of the mem record */
3720 WORD32 total_size = 0;
3721
3722 /* size in bytes to mb core coding status of an entire frame */
3723 total_size = max_mb_cnt;
3724
3725 /* add an additional 1 row of bytes to evade the special case of row 0 */
3726 total_size += max_mb_cols;
3727
3728 /* total size per each proc ctxt */
3729 total_size *= MAX_CTXT_SETS;
3730
3731 ps_mem_rec->u4_mem_size = total_size;
3732 }
3733 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
3734
3735 /************************************************************************
3736 * size for holding dpb manager context *
3737 ************************************************************************/
3738 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
3739 {
3740 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
3741 }
3742 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
3743
3744 /************************************************************************
3745 * luma or chroma core coding involves mb estimation, error computation*
3746 * between the estimated singnal and the actual signal, transform the *
3747 * error, quantize the error, then inverse transform and inverse quant *
3748 * ize the residue and add the result back to estimated signal. *
3749 * To perform all these, a set of temporary buffers are needed. *
3750 * MEM RECORD for holding scratch buffers *
3751 * 1. prediction buffer used during mb mode analysis *
3752 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
3753 * enabled *
3754 * - when intra 4x4 is enabled, rdopt is on, to store the *
3755 * reconstructed values and use them later this temp. buffer *
3756 * is used. *
3757 * 3. prediction buffer used during intra mode analysis *
3758 * 4. prediction buffer used during intra 16x16 plane mode *
3759 * analysis
3760 * 5. prediction buffer used during intra chroma mode analysis *
3761 * 6. prediction buffer used during intra chroma 16x16 plane *
3762 * mode analysis
3763 * 7. forward transform output buffer *
3764 * - to store the error between estimated and the actual inp *
3765 * ut and to store the fwd transformed quantized output *
3766 * 8. forward transform output buffer *
3767 * - when intra 4x4 is enabled, rdopt is on, to store the *
3768 * fwd transform values and use them later this temp. buffer *
3769 * is used. *
3770 * 9. temporary buffer for inverse transform *
3771 * - temporary buffer used in inverse transform and inverse *
3772 * quantization *
3773 * A. Buffers for holding half_x , half_y and half_xy planes *
3774 ************************************************************************/
3775 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
3776 {
3777 WORD32 total_size = 0;
3778 WORD32 i4_tmp_size;
3779
3780 /* size to hold prediction buffer */
3781 total_size += sizeof(UWORD8) * 16 * 16;
3782 total_size = ALIGN64(total_size);
3783
3784 /* size to hold recon for intra 4x4 buffer */
3785 total_size += sizeof(UWORD8) * 16 * 16;
3786 total_size = ALIGN64(total_size);
3787
3788 /* prediction buffer intra 16x16 */
3789 total_size += sizeof(UWORD8) * 16 * 16;
3790 total_size = ALIGN64(total_size);
3791
3792 /* prediction buffer intra 16x16 plane*/
3793 total_size += sizeof(UWORD8) * 16 * 16;
3794 total_size = ALIGN64(total_size);
3795
3796 /* prediction buffer intra chroma*/
3797 total_size += sizeof(UWORD8) * 16 * 8;
3798 total_size = ALIGN64(total_size);
3799
3800 /* prediction buffer intra chroma plane*/
3801 total_size += sizeof(UWORD8) * 16 * 8;
3802 total_size = ALIGN64(total_size);
3803
3804 /* size to hold fwd transform output */
3805 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3806 total_size = ALIGN64(total_size);
3807
3808 /* size to hold fwd transform output */
3809 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3810 total_size = ALIGN64(total_size);
3811
3812 /* size to hold temporary data during inverse transform */
3813 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3814 total_size = ALIGN64(total_size);
3815
3816 /* Buffers for holding half_x , half_y and half_xy planes */
3817 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3818 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
3819
3820 /* Allocate for each process thread */
3821 total_size *= MAX_PROCESS_CTXT;
3822
3823 ps_mem_rec->u4_mem_size = total_size;
3824 }
3825 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
3826
3827 /************************************************************************
3828 * When transform_8x8_flag is disabled, the size of a sub block is *
3829 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
3830 * block is 8x8. The threshold matrix and the forward scaling list *
3831 * is of the size of the sub block. *
3832 * MEM RECORD for holding *
3833 * 1. quantization parameters for plane y, cb, cr *
3834 * - threshold matrix for quantization *
3835 * - forward weight matrix *
3836 * - satqd threshold matrix *
3837 ************************************************************************/
3838 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
3839 {
3840 /* total size of the mem record */
3841 WORD32 total_size = 0;
3842
3843 /* quantization parameter list for planes y,cb and cr */
3844 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
3845
3846 /* size of threshold matrix for quantization
3847 * (assuming the transform_8x8_flag is disabled).
3848 * for all 3 planes */
3849 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3850
3851 /* size of forward weight matrix for quantization
3852 * (assuming the transform_8x8_flag is disabled).
3853 * for all 3 planes */
3854 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3855
3856 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
3857 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
3858
3859 /* total size per each proc thread */
3860 total_size *= MAX_PROCESS_CTXT;
3861
3862 ps_mem_rec->u4_mem_size = total_size;
3863 }
3864 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
3865
3866 /************************************************************************
3867 * While computing blocking strength for the current mb, the csbp, mb *
3868 * type for the neighboring mbs are necessary. memtab for storing top *
3869 * row mbtype and csbp is evaluated here. *
3870 * *
3871 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
3872 * and sent. The estimation is dependent on neighbor mbs. For this *
3873 * store the top row sub mb types for intra mbs *
3874 * *
3875 * During motion vector prediction, the curr mb mv is predicted from *
3876 * neigbors left, top, top right and sometimes top left depending on *
3877 * the availability. The top and top right content is accessed from *
3878 * the memtab specified below. *
3879 ************************************************************************/
3880 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
3881 {
3882 /* total size of the mem record */
3883 WORD32 total_size = 0;
3884
3885 /* size in bytes to store 1 row of mb_info_t */
3886 /* one additional mb, to avoid checking end of row condition */
3887 total_size += (max_mb_cols + 1) * sizeof(mb_info_t);
3888
3889 /* size in bytes to store 1 row of intra macroblock sub modes */
3890 total_size += max_mb_cols * sizeof(UWORD8) * 16;
3891
3892 /* size in bytes to store 1 row + 1 of enc_pu_t */
3893 /* one additional mb, to avoid checking end of row condition */
3894 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t);
3895
3896 /* total size per proc ctxt */
3897 total_size = ALIGN128(total_size);
3898
3899 /* total size per each proc ctxt */
3900 total_size *= MAX_CTXT_SETS;
3901 ps_mem_rec->u4_mem_size = total_size;
3902 }
3903 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
3904
3905 /************************************************************************
3906 * When transform_8x8_flag is disabled, the mb is partitioned into *
3907 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3908 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3909 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3910 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3911 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3912 * edge and 3 horizontal inner edges per mb. *
3913 * MEM RECORD for holding *
3914 * 1. vertical edge blocking strength *
3915 * 2. horizontal edge blocking strength *
3916 * 3. mb qp *
3917 * all are frame level *
3918 ************************************************************************/
3919 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
3920 {
3921 /* total size of the mem record */
3922 WORD32 total_size = 0;
3923
3924 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
3925 WORD32 vert_bs_size, horz_bs_size, qp_size;
3926
3927 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
3928 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3929 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3930 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3931
3932 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
3933 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3934 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3935 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3936
3937 /* qp of each mb requires 1 byte */
3938 qp_size = ALIGN64(max_mb_cnt);
3939
3940 /* total size */
3941 total_size = vert_bs_size + horz_bs_size + qp_size;
3942
3943 /* total size per each proc ctxt */
3944 total_size *= MAX_CTXT_SETS;
3945
3946 ps_mem_rec->u4_mem_size = total_size;
3947 }
3948 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3949
3950 /************************************************************************
3951 * size for holding dpb manager context *
3952 ************************************************************************/
3953 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
3954 {
3955 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3956 }
3957 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3958
3959 /************************************************************************
3960 * size for holding dpb manager context *
3961 ************************************************************************/
3962 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
3963 {
3964 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3965 }
3966 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3967
3968 /************************************************************************
3969 * Size for color space conversion *
3970 ************************************************************************/
3971 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
3972 {
3973 /* We need a total a memory for a single frame of 420 sp, ie
3974 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3975 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS
3976 * ((3 * max_ht_luma * max_wd_luma) >> 1);
3977 /* Allocate an extra row, since inverse transform functions for
3978 * chroma access(only read, not used) few extra bytes due to
3979 * interleaved input
3980 */
3981 ps_mem_rec->u4_mem_size += max_wd_luma;
3982 }
3983 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3984
3985 /************************************************************************
3986 * Size for holding pic_buf_t for each reference picture *
3987 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3988 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3989 * max_dpb_size will be based on max_wd and max_ht *
3990 * For higher max_wd and max_ht this number will be smaller than *
3991 * MAX_DPB_SIZE But during actual initialization number of buffers *
3992 * allocated can be more. *
3993 * *
3994 * Also to handle display depth application can allocate more than *
3995 * what codec asks for in case of non-shared mode *
3996 * Since this is only a structure allocation and not actual buffer *
3997 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3998 ************************************************************************/
3999 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4000 {
4001 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
4002 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
4003
4004 /************************************************************************
4005 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
4006 * is set to maximum number of luma samples allowed at the given level. *
4007 * This is done to ensure that any stream with width and height lesser *
4008 * than max_wd and max_ht is supported. Number of buffers required can *
4009 * be greater for lower width and heights at a given level and this *
4010 * increased number of buffers might require more memory than what *
4011 * max_wd and max_ht buffer would have required. Number of buffers is *
4012 * doubled in order to return one frame at a time instead of sending *
4013 * multiple outputs during dpb full case. Also note one extra buffer is *
4014 * allocted to store current picture. *
4015 * *
4016 * Half-pel planes for each reference buffer are allocated along with *
4017 * the reference buffer. So each reference buffer is 4 times the *
4018 * required size. This way buffer management for the half-pel planes is *
4019 * easier and while using the half-pel planes in MC, an offset can be *
4020 * used from a single pointer *
4021 ***********************************************************************/
4022 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT
4023 * ih264e_get_total_pic_buf_size(
4024 max_wd_luma * max_ht_luma, level,
4025 PAD_WD, PAD_HT, num_ref_frames,
4026 num_reorder_frames);
4027 }
4028 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
4029
4030 /************************************************************************
4031 * Request memory to hold mem recs to be returned during retrieve call *
4032 ************************************************************************/
4033 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
4034 {
4035 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
4036 }
4037 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
4038
4039 /************************************************************************
4040 * size for memory required by NMB info structs and buffer for storing *
4041 * half pel plane *
4042 ************************************************************************/
4043 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4044 {
4045 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols *
4046 (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE
4047 * sizeof(UWORD8));
4048 }
4049 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
4050
4051 /************************************************************************
4052 * RC mem records *
4053 ************************************************************************/
4054 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4055 {
4056 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
4057 }
4058 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size);
4059
4060 /* Each memtab size is aligned to next multiple of 128 bytes */
4061 /* This is to ensure all the memtabs start at different cache lines */
4062 ps_mem_rec = ps_mem_rec_base;
4063 for (i = 0; i < MEM_REC_CNT; i++)
4064 {
4065 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
4066 ps_mem_rec++;
4067 }
4068
4069 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
4070
4071 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
4072
4073 return (status);
4074 }
4075
4076 /**
4077 *******************************************************************************
4078 *
4079 * @brief
4080 * Initializes from mem records passed to the codec
4081 *
4082 * @par Description:
4083 * Initializes pointers based on mem records passed
4084 *
4085 * @param[in] ps_codec_obj
4086 * Pointer to codec object at API level
4087 *
4088 * @param[in] pv_api_ip
4089 * Pointer to input argument structure
4090 *
4091 * @param[out] pv_api_op
4092 * Pointer to output argument structure
4093 *
4094 * @returns error status
4095 *
4096 * @remarks none
4097 *
4098 *******************************************************************************
4099 */
ih264e_init_mem_rec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)4100 static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj,
4101 void *pv_api_ip,
4102 void *pv_api_op)
4103 {
4104 /* api call I/O structures */
4105 ih264e_init_ip_t *ps_ip = pv_api_ip;
4106 ih264e_init_op_t *ps_op = pv_api_op;
4107
4108 /* mem records */
4109 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
4110
4111 /* codec variables */
4112 codec_t * ps_codec;
4113 cabac_ctxt_t *ps_cabac;
4114 mb_info_ctxt_t *ps_mb_map_ctxt_inc;
4115
4116 cfg_params_t *ps_cfg;
4117
4118 /* frame dimensions */
4119 WORD32 max_wd_luma, max_ht_luma;
4120 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
4121
4122 /* temp var */
4123 WORD32 i, j;
4124 WORD32 status = IV_SUCCESS;
4125
4126 /* frame dimensions */
4127 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4128 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4129 max_mb_rows = max_ht_luma / MB_SIZE;
4130 max_mb_cols = max_wd_luma / MB_SIZE;
4131 max_mb_cnt = max_mb_rows * max_mb_cols;
4132
4133 /* mem records */
4134 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
4135
4136 /* Init mem records */
4137 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
4138 {
4139 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
4140 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
4141 }
4142 /* Init mem records_cabac ctxt */
4143 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
4144 {
4145 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base);
4146 }
4147
4148 /* Init mem records mb info array for CABAC */
4149 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
4150 {
4151 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base);
4152 }
4153
4154 /* Note this memset can not be done in init() call, since init will called
4155 during reset as well. And calling this during reset will mean all pointers
4156 need to reinitialized */
4157 memset(ps_codec, 0, sizeof(codec_t));
4158 memset(ps_cabac, 0, sizeof(cabac_ctxt_t));
4159
4160 /* Set default Config Params */
4161 ps_cfg = &ps_codec->s_cfg;
4162 ih264e_set_default_params(ps_cfg);
4163
4164 /* Update config params as per input */
4165 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4166 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4167
4168 /* Initialize dimensions to max dimensions during init */
4169 ps_cfg->u4_wd = ps_cfg->u4_disp_wd = ps_cfg->u4_max_wd;
4170 ps_cfg->u4_ht = ps_cfg->u4_disp_ht = ps_cfg->u4_max_ht;
4171
4172 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
4173 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
4174 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
4175 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
4176 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
4177 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
4178 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
4179 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
4180 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate;
4181 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
4182 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
4183 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4184 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4185 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
4186 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
4187 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
4188 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
4189 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
4190 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
4191
4192 /* Validate params */
4193 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL)
4194 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
4195 {
4196 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
4197 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
4198 }
4199
4200 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
4201 {
4202 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
4203 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
4204 }
4205
4206 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
4207 {
4208 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
4209 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
4210 }
4211
4212 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
4213 {
4214 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
4215
4216 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
4217 MEM_REC_CNT * sizeof(iv_mem_rec_t));
4218 }
4219
4220 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
4221 {
4222 /* temp var */
4223 WORD32 size = 0, offset;
4224
4225 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4226 {
4227 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4228 {
4229 /* base ptr */
4230 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4231
4232 /* reset size */
4233 size = 0;
4234
4235 /* skip mb run */
4236 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4237 (void *) (pu1_buf + size);
4238 size += sizeof(WORD32);
4239 size = ALIGN8(size);
4240
4241 /* entropy map */
4242 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4243 (void *) (pu1_buf + size + max_mb_cols);
4244 /* size in bytes to store entropy status of an entire frame */
4245 size += (max_mb_cols * max_mb_rows);
4246 /* add an additional 1 row of bytes to evade the special case of row 0 */
4247 size += max_mb_cols;
4248 size = ALIGN128(size);
4249
4250 /* bit stream ptr */
4251 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4252 + size);
4253 size += sizeof(bitstrm_t);
4254 size = ALIGN128(size);
4255
4256 /* nnz luma */
4257 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4258 (void *) (pu1_buf + size);
4259 size += (max_mb_cols * 4 * sizeof(UWORD8));
4260 size = ALIGN128(size);
4261
4262 /* nnz chroma */
4263 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4264 (void *) (pu1_buf + size);
4265 size += (max_mb_cols * 4 * sizeof(UWORD8));
4266 size = ALIGN128(size);
4267 offset = size;
4268 /* cabac Context */
4269 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4270 }
4271 else
4272 {
4273 /* base ptr */
4274 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4275
4276 /* reset size */
4277 size = offset;
4278
4279 /* skip mb run */
4280 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
4281 (void *) (pu1_buf + size);
4282 size += sizeof(WORD32);
4283 size = ALIGN8(size);
4284
4285 /* entropy map */
4286 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
4287 (void *) (pu1_buf + size + max_mb_cols);
4288 /* size in bytes to store entropy status of an entire frame */
4289 size += (max_mb_cols * max_mb_rows);
4290 /* add an additional 1 row of bytes to evade the special case of row 0 */
4291 size += max_mb_cols;
4292 size = ALIGN128(size);
4293
4294 /* bit stream ptr */
4295 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
4296 + size);
4297 size += sizeof(bitstrm_t);
4298 size = ALIGN128(size);
4299
4300 /* nnz luma */
4301 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
4302 (void *) (pu1_buf + size);
4303 size += (max_mb_cols * 4 * sizeof(UWORD8));
4304 size = ALIGN128(size);
4305
4306 /* nnz chroma */
4307 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
4308 (void *) (pu1_buf + size);
4309 size += (max_mb_cols * 4 * sizeof(UWORD8));
4310 size = ALIGN128(size);
4311 /* cabac Context */
4312 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
4313 }
4314 }
4315 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base =
4316 ps_mb_map_ctxt_inc;
4317 }
4318
4319 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
4320 {
4321 /* temp var */
4322 WORD32 size = 0, size_of_row;
4323 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4324
4325 /* size of coeff data of 1 mb */
4326 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
4327
4328 /* size of coeff data of 1 row of mb's */
4329 size *= max_mb_cols;
4330
4331 /* align to avoid false sharing */
4332 size = ALIGN64(size);
4333 size_of_row = size;
4334
4335 /* size for one full frame */
4336 size *= max_mb_rows;
4337
4338 ps_codec->u4_size_coeff_data = size_of_row;
4339
4340 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4341 {
4342 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4343 {
4344 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
4345 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data =
4346 pu1_buf;
4347 }
4348 else
4349 {
4350 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
4351 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf
4352 + size;
4353 }
4354 }
4355 }
4356
4357 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
4358 {
4359 /* temp var */
4360 WORD32 size, size_of_row;
4361 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4362
4363 /* size of header data of 1 mb */
4364 size = sizeof(mb_hdr_t);
4365
4366 /* size for 1 row of mbs */
4367 size = size * max_mb_cols;
4368
4369 /* align to avoid any false sharing across threads */
4370 size = ALIGN64(size);
4371 size_of_row = size;
4372
4373 /* size for one full frame */
4374 size *= max_mb_rows;
4375
4376 ps_codec->u4_size_header_data = size_of_row;
4377
4378 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4379 {
4380 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4381 {
4382 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
4383 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4384 pu1_buf;
4385 }
4386 else
4387 {
4388 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
4389 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
4390 pu1_buf + size;
4391 }
4392 }
4393 }
4394
4395 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
4396 {
4397 /* size of buf mgr struct */
4398 WORD32 size = ih264_buf_mgr_size();
4399
4400 /* temp var */
4401 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4402
4403 /* mv buffer mgr */
4404 ps_codec->pv_mv_buf_mgr_base = pu1_buf;
4405
4406 /* mv bank */
4407 ps_codec->pv_mv_bank_buf_base = pu1_buf + size;
4408 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size;
4409 }
4410
4411 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
4412 {
4413 /* max srch range x */
4414 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
4415
4416 /* max srch range y */
4417 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
4418
4419 /* max srch range */
4420 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
4421
4422 /* temp var */
4423 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4424
4425 /* due to subpel */
4426 u4_max_srch_range <<= 2;
4427
4428 // /* due to mv on either direction */
4429 // u4_max_srch_range = (u4_max_srch_range << 1);
4430
4431 /* due to pred mv + zero */
4432 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
4433
4434 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4435 {
4436 /* me ctxt */
4437 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
4438
4439 /* init at zero mv */
4440 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
4441 }
4442 }
4443
4444 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
4445 {
4446 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
4447 }
4448
4449 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
4450 {
4451 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
4452 }
4453
4454 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
4455 {
4456 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
4457
4458 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4459 {
4460 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4461 {
4462 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
4463 }
4464 else
4465 {
4466 /* temp var */
4467 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
4468 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
4469
4470 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
4471 }
4472 }
4473 }
4474
4475 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
4476 {
4477 /* temp var */
4478 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4479
4480 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4481 {
4482 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4483 {
4484 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
4485 }
4486 else
4487 {
4488 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf
4489 + max_mb_cnt;
4490 }
4491 }
4492
4493 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
4494 }
4495
4496 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
4497 {
4498 /* pointer to storage space */
4499 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4500
4501 /* init pointer */
4502 pu1_buf_ping = ps_mem_rec->pv_base;
4503 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
4504
4505 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4506 {
4507 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4508 {
4509 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
4510 }
4511 else
4512 {
4513 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
4514 }
4515 }
4516 }
4517
4518 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
4519 {
4520 WORD32 handle_size = ithread_get_handle_size();
4521
4522 for (i = 0; i < MAX_PROCESS_THREADS; i++)
4523 {
4524 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base
4525 + (i * handle_size);
4526 }
4527 }
4528
4529 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
4530 {
4531 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
4532 }
4533
4534 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
4535 {
4536 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
4537 }
4538
4539 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
4540 {
4541 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
4542 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
4543 }
4544
4545 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
4546 {
4547 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
4548 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
4549 }
4550
4551 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
4552 {
4553 /* pointer to storage space */
4554 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4555
4556 /* total size of the mem record */
4557 WORD32 total_size = 0;
4558
4559 /* size in bytes to mb core coding status of an entire frame */
4560 total_size = max_mb_cnt;
4561
4562 /* add an additional 1 row of bytes to evade the special case of row 0 */
4563 total_size += max_mb_cols;
4564
4565 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4566 {
4567 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4568 {
4569 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
4570 }
4571 else
4572 {
4573 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size
4574 + max_mb_cols;
4575 }
4576 }
4577 }
4578
4579 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
4580 {
4581 /* pointer to storage space */
4582 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4583
4584 /* total size of the mem record */
4585 WORD32 total_size = 0;
4586
4587 /* size in bytes to mb core coding status of an entire frame */
4588 total_size = max_mb_cnt;
4589
4590 /* add an additional 1 row of bytes to evade the special case of row 0 */
4591 total_size += max_mb_cols;
4592
4593 /*Align the memory offsets*/
4594 total_size = ALIGN64(total_size);
4595
4596 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4597 {
4598 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4599 {
4600 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
4601
4602 }
4603 else
4604 {
4605 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size
4606 + max_mb_cols;
4607
4608 }
4609 }
4610 }
4611
4612 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
4613 {
4614 /* pointer to storage space */
4615 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4616
4617 /* total size of the mem record */
4618 WORD32 total_size = 0;
4619
4620 /* size in bytes to mb core coding status of an entire frame */
4621 total_size = max_mb_cnt;
4622
4623 /* add an additional 1 row of bytes to evade the special case of row 0 */
4624 total_size += max_mb_cols;
4625
4626 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4627 {
4628 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4629 {
4630 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
4631 }
4632 else
4633 {
4634 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size
4635 + max_mb_cols;
4636 }
4637 }
4638 }
4639
4640 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
4641 {
4642 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
4643 }
4644
4645 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
4646 {
4647 /* pointer to storage space */
4648 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4649
4650 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
4651 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
4652
4653 /* temp var */
4654 WORD32 size = 0;
4655
4656 /* size to hold intra/inter prediction buffer */
4657 size_pred_luma = sizeof(UWORD8) * 16 * 16;
4658 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
4659
4660 /* size to hold fwd transform output */
4661 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
4662
4663 /* size to hold temporary data during inverse transform */
4664 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
4665
4666 /* size to hold half pel plane buffers */
4667 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
4668
4669 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4670 {
4671 /* prediction buffer */
4672 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
4673 ps_codec->as_process[i].i4_pred_strd = 16;
4674 size += size_pred_luma;
4675 size = ALIGN64(size);
4676
4677 /* prediction buffer */
4678 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf
4679 + size);
4680 size += size_pred_luma;
4681 size = ALIGN64(size);
4682
4683 /* prediction buffer intra 16x16 */
4684 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf
4685 + size);
4686 size += size_pred_luma;
4687 size = ALIGN64(size);
4688
4689 /* prediction buffer intra 16x16 plane*/
4690 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane =
4691 (void *) (pu1_buf + size);
4692 size += size_pred_luma;
4693 size = ALIGN64(size);
4694
4695 /* prediction buffer intra chroma*/
4696 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf
4697 + size);
4698 size += size_pred_chroma;
4699 size = ALIGN64(size);
4700
4701 /* prediction buffer intra chroma plane*/
4702 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane =
4703 (void *) (pu1_buf + size);
4704 size += size_pred_chroma;
4705 size = ALIGN64(size);
4706
4707 /* Fwd transform output */
4708 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4709 ps_codec->as_process[i].i4_res_strd = 16;
4710 size += size_fwd;
4711 size = ALIGN64(size);
4712
4713 /* Fwd transform output */
4714 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf
4715 + size);
4716 size += size_fwd;
4717 size = ALIGN64(size);
4718
4719 /* scratch buffer used during inverse transform */
4720 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4721 size += size_inv;
4722 size = ALIGN64(size);
4723
4724 for (j = 0; j < SUBPEL_BUFF_CNT; j++)
4725 {
4726 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4727 size += ALIGN64(size_hp);
4728 }
4729 }
4730 }
4731
4732 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
4733 {
4734 /* pointer to storage space */
4735 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4736
4737 /* size of qp, threshold matrix, fwd scaling list for one plane */
4738 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat,
4739 size_satqd_weight_mat;
4740
4741 /* temp var */
4742 WORD32 total_size = 0;
4743
4744 /* size of quantization parameter list of 1 plane */
4745 size_quant_param = ALIGN64(sizeof(quant_params_t));
4746
4747 /* size of threshold matrix for quantization
4748 * (assuming the transform_8x8_flag is disabled).
4749 * for 1 plane */
4750 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4751
4752 /* size of forward weight matrix for quantization
4753 * (assuming the transform_8x8_flag is disabled).
4754 * for 1 plane */
4755 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4756
4757 /* size of SATQD matrix*/
4758 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4759
4760 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4761 {
4762 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4763
4764 /* quantization param structure */
4765 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4766 total_size = total_size + size_quant_param;
4767 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4768 total_size = total_size + size_quant_param;
4769 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4770 total_size = total_size + size_quant_param;
4771
4772 /* threshold matrix for quantization */
4773 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4774 total_size = total_size + size_thres_mat;
4775 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4776 total_size = total_size + size_thres_mat;
4777 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4778 total_size = total_size + size_thres_mat;
4779
4780 /* fwd weight matrix */
4781 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4782 total_size = total_size + size_fwd_weight_mat;
4783 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4784 total_size = total_size + size_fwd_weight_mat;
4785 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4786 total_size = total_size + size_fwd_weight_mat;
4787
4788 /* threshold matrix for SATQD */
4789 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4790 total_size = total_size + size_satqd_weight_mat;
4791 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4792 total_size = total_size + size_satqd_weight_mat;
4793 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4794 total_size = total_size + size_satqd_weight_mat;
4795
4796 total_size = ALIGN128(total_size);
4797 }
4798 }
4799
4800 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
4801 {
4802 /* total size of the mem record */
4803 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv;
4804
4805 /* pointer to buffer */
4806 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4807
4808 /* size in bytes to store 1 row of mb_info_t */
4809 /* one additional mb, to avoid checking end of row condition */
4810 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t);
4811
4812 /* size in bytes to store 1 row of intra macroblock sub modes */
4813 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16;
4814
4815 /* size in bytes to store 1 row + 1 of enc_pu_t */
4816 /* one additional mb, to avoid checking end of row condition */
4817 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t);
4818
4819 /* total size per proc ctxt */
4820 total_size = size_csbp + size_intra_modes + size_mv;
4821
4822 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4823 {
4824 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4825 {
4826 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4827 (mb_info_t *) pu1_buf;
4828 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4829 + size_csbp;
4830 ps_codec->as_process[i].ps_top_row_pu_base =
4831 (enc_pu_t *) (pu1_buf + size_csbp
4832 + size_intra_modes);
4833 }
4834 else
4835 {
4836 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4837 (mb_info_t *) (pu1_buf + total_size);
4838 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4839 + total_size + size_csbp;
4840 ps_codec->as_process[i].ps_top_row_pu_base =
4841 (enc_pu_t *) (pu1_buf + total_size + size_csbp
4842 + size_intra_modes);
4843 }
4844 }
4845 }
4846
4847 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
4848 {
4849 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4850
4851 /* total size of the mem record */
4852 WORD32 total_size = 0;
4853
4854 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
4855 WORD32 vert_bs_size, horz_bs_size, qp_size;
4856
4857 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
4858 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4859 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4860 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4861
4862 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
4863 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4864 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4865 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4866
4867 /* qp of each mb requires 1 byte */
4868 qp_size = ALIGN64(max_mb_cnt);
4869
4870 /* total size */
4871 total_size = vert_bs_size + horz_bs_size + qp_size;
4872
4873 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4874 {
4875 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
4876 {
4877 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4878
4879 /* vertical edge bs storage space */
4880 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4881 (UWORD32 *) pu1_buf_ping;
4882 pu1_buf_ping += vert_bs_size;
4883
4884 /* horizontal edge bs storage space */
4885 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4886 (UWORD32 *) pu1_buf_ping;
4887 pu1_buf_ping += horz_bs_size;
4888
4889 /* qp */
4890 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4891 (UWORD8 *) pu1_buf_ping;
4892 pu1_buf_ping += qp_size;
4893 }
4894 else
4895 {
4896 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base;
4897 pu1_buf_pong += total_size;
4898
4899 /* vertical edge bs storage space */
4900 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4901 (UWORD32 *) pu1_buf_pong;
4902 pu1_buf_pong += vert_bs_size;
4903
4904 /* horizontal edge bs storage space */
4905 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4906 (UWORD32 *) pu1_buf_pong;
4907 pu1_buf_pong += horz_bs_size;
4908
4909 /* qp */
4910 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4911 (UWORD8 *) pu1_buf_pong;
4912 pu1_buf_pong += qp_size;
4913 }
4914 }
4915 }
4916
4917 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4918 {
4919 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4920 }
4921
4922 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4923 {
4924 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4925 }
4926
4927 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4928 {
4929 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4930 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base
4931 + (max_ht_luma * max_wd_luma);
4932 }
4933
4934 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4935 {
4936 /* size of buf mgr struct */
4937 WORD32 size = ih264_buf_mgr_size();
4938
4939 /* temp var */
4940 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4941
4942 /* pic buffer mgr */
4943 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4944
4945 /* picture bank */
4946 ps_codec->pv_pic_buf_base = pu1_buf + size;
4947 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4948 }
4949
4950 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4951 {
4952 /* temp var */
4953 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4954
4955 /* size of nmb ctxt */
4956 WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t);
4957
4958 WORD32 nmb_cntr, subpel_buf_size;
4959
4960 /* init nmb info structure pointer in all proc ctxts */
4961 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4962 {
4963 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf);
4964
4965 pu1_buf += size;
4966 }
4967
4968 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8);
4969
4970 /* adjusting pointers for nmb halfpel buffer */
4971 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4972 {
4973 mb_info_nmb_t* ps_mb_info_nmb =
4974 &ps_codec->as_process[i].ps_nmb_info[0];
4975
4976 for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
4977 {
4978 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4979
4980 pu1_buf = pu1_buf + subpel_buf_size;
4981
4982 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4983 }
4984 }
4985 }
4986
4987 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4988 {
4989 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec,
4990 USE_BASE);
4991 }
4992
4993 /* init codec ctxt */
4994 status = ih264e_init(ps_codec);
4995
4996 return status;
4997 }
4998
4999 /**
5000 *******************************************************************************
5001 *
5002 * @brief
5003 * Retrieves mem records passed to the codec
5004 *
5005 * @par Description:
5006 * Retrieves mem recs passed during init
5007 *
5008 * @param[in] ps_codec_obj
5009 * Pointer to codec object at API level
5010 *
5011 * @param[in] pv_api_ip
5012 * Pointer to input argument structure
5013 *
5014 * @param[out] pv_api_op
5015 * Pointer to output argument structure
5016 *
5017 * @returns error status
5018 *
5019 * @remarks none
5020 *
5021 *******************************************************************************
5022 */
ih264e_retrieve_memrec(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5023 static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj,
5024 void *pv_api_ip,
5025 void *pv_api_op)
5026 {
5027 /* codec ctxt */
5028 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5029
5030 /* ctrl call I/O structures */
5031 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
5032 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
5033
5034 if (ps_codec->i4_init_done != 1)
5035 {
5036 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5037 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5038 return IV_FAIL;
5039 }
5040
5041 /* join threads upon at end of sequence */
5042 ih264e_join_threads(ps_codec);
5043
5044 /* collect list of memory records used by the encoder library */
5045 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
5046 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
5047 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT;
5048
5049 /* clean up mutex memory */
5050 ih264_list_free(ps_codec->pv_entropy_jobq);
5051 ih264_list_free(ps_codec->pv_proc_jobq);
5052 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
5053 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
5054
5055
5056 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
5057 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr);
5058 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr);
5059 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr);
5060
5061 return IV_SUCCESS;
5062 }
5063
5064 /**
5065 *******************************************************************************
5066 *
5067 * @brief
5068 * Sets the encoder in flush mode.
5069 *
5070 * @par Description:
5071 * Sets the encoder in flush mode
5072 *
5073 * @param[in] ps_codec_obj
5074 * Pointer to codec object at API level
5075 *
5076 * @param[in] pv_api_ip
5077 * Pointer to input argument structure
5078 *
5079 * @param[out] pv_api_op
5080 * Pointer to output argument structure
5081 *
5082 * @returns error status
5083 *
5084 * @remarks This call has no real effect on encoder
5085 *
5086 *******************************************************************************
5087 */
ih264e_set_flush_mode(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5088 static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj,
5089 void *pv_api_ip,
5090 void *pv_api_op)
5091 {
5092 /* codec ctxt */
5093 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5094
5095 /* ctrl call I/O structures */
5096 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op;
5097
5098 UNUSED(pv_api_ip);
5099
5100 ps_ctl_op->s_ive_op.u4_error_code = 0;
5101
5102 /* signal flush frame control call */
5103 ps_codec->i4_flush_mode = 1;
5104
5105 return IV_SUCCESS;
5106 }
5107
5108 /**
5109 *******************************************************************************
5110 *
5111 * @brief
5112 * Gets encoder buffer requirements
5113 *
5114 * @par Description:
5115 * Gets the encoder buffer requirements. Basing on max width and max height
5116 * configuration settings, this routine, computes the sizes of necessary input,
5117 * output buffers returns this info to callee.
5118 *
5119 * @param[in] ps_codec_obj
5120 * Pointer to codec object at API level
5121 *
5122 * @param[in] pv_api_ip
5123 * Pointer to input argument structure
5124 *
5125 * @param[out] pv_api_op
5126 * Pointer to output argument structure
5127 *
5128 * @returns error status
5129 *
5130 * @remarks none
5131 *
5132 *******************************************************************************
5133 */
ih264e_get_buf_info(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)5134 static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj,
5135 void *pv_api_ip,
5136 void *pv_api_op)
5137 {
5138 /* ctrl call I/O structures */
5139 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
5140 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
5141
5142 /* temp var */
5143 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
5144 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
5145 WORD32 i;
5146
5147 UNUSED(ps_codec_obj);
5148
5149 ps_op->s_ive_op.u4_error_code = 0;
5150
5151 /* Number of components in input buffers required for codec &
5152 * Minimum sizes of each component in input buffer required */
5153 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
5154 {
5155 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
5156
5157 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5158 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
5159 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
5160 }
5161 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
5162 {
5163 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
5164
5165 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5166 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5167 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5168 }
5169 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
5170 {
5171 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
5172
5173 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
5174 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5175 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5176 }
5177 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
5178 {
5179 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
5180
5181 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
5182 ps_op->s_ive_op.au4_min_in_buf_size[1] =
5183 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5184 }
5185 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV)
5186 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
5187 {
5188 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
5189
5190 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
5191 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
5192 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
5193 }
5194
5195 /* Number of components in output buffers required for codec &
5196 * Minimum sizes of each component in output buffer required */
5197 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
5198
5199 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
5200 {
5201 ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE);
5202 }
5203
5204 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
5205 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
5206
5207 return IV_SUCCESS;
5208 }
5209
5210 /**
5211 *******************************************************************************
5212 *
5213 * @brief
5214 * Sets the picture dimensions
5215 *
5216 * @par Description:
5217 * Sets width, height, display width, display height and strides
5218 *
5219 * @param[in] pv_api_ip
5220 * Pointer to input argument structure
5221 *
5222 * @param[out] pv_api_op
5223 * Pointer to output argument structure
5224 *
5225 * @param[out] ps_cfg
5226 * Pointer to config structure to be updated
5227 *
5228 * @returns error status
5229 *
5230 * @remarks none
5231 *
5232 *******************************************************************************
5233 */
ih264e_set_dimensions(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5234 static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip,
5235 void *pv_api_op,
5236 cfg_params_t *ps_cfg)
5237 {
5238 /* ctrl call I/O structures */
5239 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
5240 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
5241
5242 ps_op->s_ive_op.u4_error_code = 0;
5243
5244 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd);
5245 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht);
5246 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4;
5247 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4;
5248 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd;
5249 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht;
5250
5251 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5252 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5253
5254 return IV_SUCCESS;
5255 }
5256
5257 /**
5258 *******************************************************************************
5259 *
5260 * @brief
5261 * Sets source and target frame rates
5262 *
5263 * @par Description:
5264 * Sets source and target frame rates
5265 *
5266 * @param[in] pv_api_ip
5267 * Pointer to input argument structure
5268 *
5269 * @param[out] pv_api_op
5270 * Pointer to output argument structure
5271 *
5272 * @param[out] ps_cfg
5273 * Pointer to config structure to be updated
5274 *
5275 * @returns error status
5276 *
5277 * @remarks none
5278 *
5279 *******************************************************************************
5280 */
ih264e_set_frame_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5281 static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip,
5282 void *pv_api_op,
5283 cfg_params_t *ps_cfg)
5284 {
5285 /* ctrl call I/O structures */
5286 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
5287 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
5288
5289 ps_op->s_ive_op.u4_error_code = 0;
5290
5291 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
5292 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
5293
5294 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5295 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5296
5297 return IV_SUCCESS;
5298 }
5299
5300 /**
5301 *******************************************************************************
5302 *
5303 * @brief
5304 * Sets target bit rate
5305 *
5306 * @par Description:
5307 * Sets target bit rate
5308 *
5309 * @param[in] pv_api_ip
5310 * Pointer to input argument structure
5311 *
5312 * @param[out] pv_api_op
5313 * Pointer to output argument structure
5314 *
5315 * @param[out] ps_cfg
5316 * Pointer to config structure to be updated
5317 *
5318 * @returns error status
5319 *
5320 * @remarks none
5321 *
5322 *******************************************************************************
5323 */
ih264e_set_bit_rate(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5324 static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip,
5325 void *pv_api_op,
5326 cfg_params_t *ps_cfg)
5327 {
5328 /* ctrl call I/O structures */
5329 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
5330 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
5331
5332 ps_op->s_ive_op.u4_error_code = 0;
5333
5334 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate;
5335
5336 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5337 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5338
5339 return IV_SUCCESS;
5340 }
5341
5342 /**
5343 *******************************************************************************
5344 *
5345 * @brief
5346 * Sets frame type
5347 *
5348 * @par Description:
5349 * Sets frame type
5350 *
5351 * @param[in] pv_api_ip
5352 * Pointer to input argument structure
5353 *
5354 * @param[out] pv_api_op
5355 * Pointer to output argument structure
5356 *
5357 * @param[out] ps_cfg
5358 * Pointer to config structure to be updated
5359 *
5360 * @returns error status
5361 *
5362 * @remarks not a sticky tag
5363 *
5364 *******************************************************************************
5365 */
ih264e_set_frame_type(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5366 static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip,
5367 void *pv_api_op,
5368 cfg_params_t *ps_cfg)
5369 {
5370 /* ctrl call I/O structures */
5371 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
5372 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
5373
5374 ps_op->s_ive_op.u4_error_code = 0;
5375
5376 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
5377
5378 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5379 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5380
5381 return IV_SUCCESS;
5382 }
5383
5384 /**
5385 *******************************************************************************
5386 *
5387 * @brief
5388 * Sets quantization params
5389 *
5390 * @par Description:
5391 * Sets the max, min and default qp for I frame, P frame and B frame
5392 *
5393 * @param[in] pv_api_ip
5394 * Pointer to input argument structure
5395 *
5396 * @param[out] pv_api_op
5397 * Pointer to output argument structure
5398 *
5399 * @param[out] ps_cfg
5400 * Pointer to config structure to be updated
5401 *
5402 * @returns error status
5403 *
5404 * @remarks none
5405 *
5406 *******************************************************************************
5407 */
ih264e_set_qp(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5408 static IV_STATUS_T ih264e_set_qp(void *pv_api_ip,
5409 void *pv_api_op,
5410 cfg_params_t *ps_cfg)
5411 {
5412 /* ctrl call I/O structures */
5413 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
5414 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
5415
5416 ps_set_qp_op->s_ive_op.u4_error_code = 0;
5417
5418 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max;
5419 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min;
5420 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp;
5421 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max;
5422 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min;
5423 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp;
5424 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max;
5425 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min;
5426 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp;
5427
5428 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
5429 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
5430
5431 return IV_SUCCESS;
5432 }
5433
5434 /**
5435 *******************************************************************************
5436 *
5437 * @brief
5438 * Sets encoding mode
5439 *
5440 * @par Description:
5441 * Sets encoding mode
5442 *
5443 * @param[in] pv_api_ip
5444 * Pointer to input argument structure
5445 *
5446 * @param[out] pv_api_op
5447 * Pointer to output argument structure
5448 *
5449 * @param[out] ps_cfg
5450 * Pointer to config structure to be updated
5451 *
5452 * @returns error status
5453 *
5454 * @remarks none
5455 *
5456 *******************************************************************************
5457 */
ih264e_set_enc_mode(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5458 static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip,
5459 void *pv_api_op,
5460 cfg_params_t *ps_cfg)
5461 {
5462 /* ctrl call I/O structures */
5463 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
5464 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
5465
5466 ps_op->s_ive_op.u4_error_code = 0;
5467
5468 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
5469
5470 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5471 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5472
5473 return IV_SUCCESS;
5474 }
5475
5476 /**
5477 *******************************************************************************
5478 *
5479 * @brief
5480 * Sets vbv parameters
5481 *
5482 * @par Description:
5483 * Sets vbv parameters
5484 *
5485 * @param[in] pv_api_ip
5486 * Pointer to input argument structure
5487 *
5488 * @param[out] pv_api_op
5489 * Pointer to output argument structure
5490 *
5491 * @param[out] ps_cfg
5492 * Pointer to config structure to be updated
5493 *
5494 * @returns error status
5495 *
5496 * @remarks none
5497 *
5498 *******************************************************************************
5499 */
ih264e_set_vbv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5500 static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip,
5501 void *pv_api_op,
5502 cfg_params_t *ps_cfg)
5503 {
5504 /* ctrl call I/O structures */
5505 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
5506 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
5507
5508 ps_op->s_ive_op.u4_error_code = 0;
5509
5510 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size;
5511 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay;
5512
5513 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5514 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5515
5516 return IV_SUCCESS;
5517 }
5518
5519 /**
5520 *******************************************************************************
5521 *
5522 * @brief
5523 * Sets AIR parameters
5524 *
5525 * @par Description:
5526 * Sets AIR parameters
5527 *
5528 * @param[in] pv_api_ip
5529 * Pointer to input argument structure
5530 *
5531 * @param[out] pv_api_op
5532 * Pointer to output argument structure
5533 *
5534 * @param[out] ps_cfg
5535 * Pointer to config structure to be updated
5536 *
5537 * @returns error status
5538 *
5539 * @remarks none
5540 *
5541 *******************************************************************************
5542 */
ih264_set_air_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5543 static IV_STATUS_T ih264_set_air_params(void *pv_api_ip,
5544 void *pv_api_op,
5545 cfg_params_t *ps_cfg)
5546 {
5547 /* ctrl call I/O structures */
5548 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
5549 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
5550
5551 ps_op->s_ive_op.u4_error_code = 0;
5552
5553 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
5554 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
5555
5556 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5557 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5558
5559 return IV_SUCCESS;
5560 }
5561
5562 /**
5563 *******************************************************************************
5564 *
5565 * @brief
5566 * Sets motion estimation parameters
5567 *
5568 * @par Description:
5569 * Sets motion estimation parameters
5570 *
5571 * @param[in] pv_api_ip
5572 * Pointer to input argument structure
5573 *
5574 * @param[out] pv_api_op
5575 * Pointer to output argument structure
5576 *
5577 * @param[out] ps_cfg
5578 * Pointer to config structure to be updated
5579 *
5580 * @returns error status
5581 *
5582 * @remarks none
5583 *
5584 *******************************************************************************
5585 */
ih264_set_me_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5586 static IV_STATUS_T ih264_set_me_params(void *pv_api_ip,
5587 void *pv_api_op,
5588 cfg_params_t *ps_cfg)
5589 {
5590 /* ctrl call I/O structures */
5591 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
5592 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
5593
5594 ps_op->s_ive_op.u4_error_code = 0;
5595
5596 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
5597 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
5598 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
5599 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
5600 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
5601 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
5602 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
5603
5604 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5605 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5606
5607 return IV_SUCCESS;
5608 }
5609
5610 /**
5611 *******************************************************************************
5612 *
5613 * @brief
5614 * Sets Intra/Inter Prediction estimation parameters
5615 *
5616 * @par Description:
5617 * Sets Intra/Inter Prediction estimation parameters
5618 *
5619 * @param[in] pv_api_ip
5620 * Pointer to input argument structure
5621 *
5622 * @param[out] pv_api_op
5623 * Pointer to output argument structure
5624 *
5625 * @param[out] ps_cfg
5626 * Pointer to config structure to be updated
5627 *
5628 * @returns error status
5629 *
5630 * @remarks none
5631 *
5632 *******************************************************************************
5633 */
ih264_set_ipe_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5634 static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip,
5635 void *pv_api_op,
5636 cfg_params_t *ps_cfg)
5637 {
5638 /* ctrl call I/O structures */
5639 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
5640 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
5641
5642 ps_op->s_ive_op.u4_error_code = 0;
5643
5644 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
5645 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
5646
5647 ps_cfg->u4_constrained_intra_pred = ps_ip->s_ive_ip.u4_constrained_intra_pred;
5648
5649 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5650 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5651
5652 return IV_SUCCESS;
5653 }
5654
5655 /**
5656 *******************************************************************************
5657 *
5658 * @brief
5659 * Sets GOP parameters
5660 *
5661 * @par Description:
5662 * Sets GOP parameters
5663 *
5664 * @param[in] pv_api_ip
5665 * Pointer to input argument structure
5666 *
5667 * @param[out] pv_api_op
5668 * Pointer to output argument structure
5669 *
5670 * @param[out] ps_cfg
5671 * Pointer to config structure to be updated
5672 *
5673 * @returns error status
5674 *
5675 * @remarks none
5676 *
5677 *******************************************************************************
5678 */
ih264_set_gop_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5679 static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip,
5680 void *pv_api_op,
5681 cfg_params_t *ps_cfg)
5682 {
5683 /* ctrl call I/O structures */
5684 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5685 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5686
5687 ps_op->s_ive_op.u4_error_code = 0;
5688
5689 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5690 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
5691
5692 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5693 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5694
5695 return IV_SUCCESS;
5696 }
5697
5698 /**
5699 *******************************************************************************
5700 *
5701 * @brief
5702 * Sets profile parameters
5703 *
5704 * @par Description:
5705 * Sets profile parameters
5706 *
5707 * @param[in] pv_api_ip
5708 * Pointer to input argument structure
5709 *
5710 * @param[out] pv_api_op
5711 * Pointer to output argument structure
5712 *
5713 * @param[out] ps_cfg
5714 * Pointer to config structure to be updated
5715 *
5716 * @returns error status
5717 *
5718 * @remarks none
5719 *
5720 *******************************************************************************
5721 */
ih264_set_profile_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5722 static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip,
5723 void *pv_api_op,
5724 cfg_params_t *ps_cfg)
5725 {
5726 /* ctrl call I/O structures */
5727 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5728 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5729
5730 ps_op->s_ive_op.u4_error_code = 0;
5731
5732 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5733
5734 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5735
5736 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5737 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5738
5739 return IV_SUCCESS;
5740 }
5741
5742 /**
5743 *******************************************************************************
5744 *
5745 * @brief
5746 * Sets disable deblock level
5747 *
5748 * @par Description:
5749 * Sets disable deblock level. Level 0 means no disabling and level 4 means
5750 * disable completely. 1, 2, 3 are intermediate levels that control amount
5751 * of deblocking done.
5752 *
5753 * @param[in] ps_codec_obj
5754 * Pointer to codec object at API level
5755 *
5756 * @param[in] pv_api_ip
5757 * Pointer to input argument structure
5758 *
5759 * @param[out] pv_api_op
5760 * Pointer to output argument structure
5761 *
5762 * @returns error status
5763 *
5764 * @remarks none
5765 *
5766 *******************************************************************************
5767 */
ih264_set_deblock_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5768 static WORD32 ih264_set_deblock_params(void *pv_api_ip,
5769 void *pv_api_op,
5770 cfg_params_t *ps_cfg)
5771 {
5772 /* ctrl call I/O structures */
5773 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5774 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5775
5776 ps_op->s_ive_op.u4_error_code = 0;
5777
5778 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5779
5780 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5781 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5782
5783 return IV_SUCCESS;
5784 }
5785 /**
5786 *******************************************************************************
5787 *
5788 * @brief
5789 * Sets vui params
5790 *
5791 * @par Description:
5792 * Video usability information
5793 *
5794 * @param[in] pv_api_ip
5795 * Pointer to input argument structure
5796 *
5797 * @param[out] pv_api_op
5798 * Pointer to output argument structure
5799 *
5800 * @param[out] ps_cfg
5801 * Pointer to config structure to be updated
5802 *
5803 * @returns error status
5804 *
5805 * @remarks none
5806 *
5807 *******************************************************************************
5808 */
ih264e_set_vui_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5809 static WORD32 ih264e_set_vui_params(void *pv_api_ip,
5810 void *pv_api_op,
5811 cfg_params_t *ps_cfg)
5812 {
5813 /* ctrl call I/O structures */
5814 ih264e_vui_ip_t *ps_ip = pv_api_ip;
5815 ih264e_vui_op_t *ps_op = pv_api_op;
5816 vui_t *ps_vui = &ps_cfg->s_vui;
5817
5818 ps_op->u4_error_code = 0;
5819
5820 ps_vui->u1_aspect_ratio_info_present_flag =
5821 ps_ip->u1_aspect_ratio_info_present_flag;
5822 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5823 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5824 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5825 ps_vui->u1_overscan_info_present_flag =
5826 ps_ip->u1_overscan_info_present_flag;
5827 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5828 ps_vui->u1_video_signal_type_present_flag =
5829 ps_ip->u1_video_signal_type_present_flag;
5830 ps_vui->u1_video_format = ps_ip->u1_video_format;
5831 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5832 ps_vui->u1_colour_description_present_flag =
5833 ps_ip->u1_colour_description_present_flag;
5834 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5835 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5836 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5837 ps_vui->u1_chroma_loc_info_present_flag =
5838 ps_ip->u1_chroma_loc_info_present_flag;
5839 ps_vui->u1_chroma_sample_loc_type_top_field =
5840 ps_ip->u1_chroma_sample_loc_type_top_field;
5841 ps_vui->u1_chroma_sample_loc_type_bottom_field =
5842 ps_ip->u1_chroma_sample_loc_type_bottom_field;
5843 ps_vui->u1_vui_timing_info_present_flag =
5844 ps_ip->u1_vui_timing_info_present_flag;
5845 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5846 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5847 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5848 ps_vui->u1_nal_hrd_parameters_present_flag =
5849 ps_ip->u1_nal_hrd_parameters_present_flag;
5850 ps_vui->u1_vcl_hrd_parameters_present_flag =
5851 ps_ip->u1_vcl_hrd_parameters_present_flag;
5852 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5853 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5854 ps_vui->u1_bitstream_restriction_flag =
5855 ps_ip->u1_bitstream_restriction_flag;
5856 ps_vui->u1_motion_vectors_over_pic_boundaries_flag =
5857 ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5858 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5859 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5860 ps_vui->u1_log2_max_mv_length_horizontal =
5861 ps_ip->u1_log2_max_mv_length_horizontal;
5862 ps_vui->u1_log2_max_mv_length_vertical =
5863 ps_ip->u1_log2_max_mv_length_vertical;
5864 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5865 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5866
5867 return IV_SUCCESS;
5868 }
5869
5870 /**
5871 *******************************************************************************
5872 *
5873 * @brief
5874 * Sets Mastering display color volume sei params
5875 *
5876 * @par Description:
5877 * Supplemental enhancement information
5878 *
5879 * @param[in] pv_api_ip
5880 * Pointer to input argument structure
5881 *
5882 * @param[out] pv_api_op
5883 * Pointer to output argument structure
5884 *
5885 * @param[out] ps_cfg
5886 * Pointer to config structure to be updated
5887 *
5888 * @return error status
5889 *
5890 * @remarks none
5891 *
5892 *******************************************************************************
5893 */
ih264e_set_sei_mdcv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5894 static WORD32 ih264e_set_sei_mdcv_params(void *pv_api_ip,
5895 void *pv_api_op,
5896 cfg_params_t *ps_cfg)
5897 {
5898 WORD32 i4_count;
5899 /* ctrl call I/O structures */
5900 ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip;
5901 ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op;
5902 sei_params_t *ps_sei = &ps_cfg->s_sei;
5903
5904 ps_op->u4_error_code = 0;
5905
5906 ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag;
5907 for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
5908 {
5909 ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] =
5910 ps_ip->au2_display_primaries_x[i4_count];
5911 ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] =
5912 ps_ip->au2_display_primaries_y[i4_count];
5913 }
5914
5915 ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x;
5916 ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y;
5917 ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance =
5918 ps_ip->u4_max_display_mastering_luminance;
5919 ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance =
5920 ps_ip->u4_min_display_mastering_luminance;
5921
5922 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5923 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5924
5925 return IV_SUCCESS;
5926 }
5927
5928 /**
5929 *******************************************************************************
5930 *
5931 * @brief
5932 * Sets content light level sei params
5933 *
5934 * @par Description:
5935 * Supplemental enhancement information
5936 *
5937 * @param[in] pv_api_ip
5938 * Pointer to input argument structure
5939 *
5940 * @param[out] pv_api_op
5941 * Pointer to output argument structure
5942 *
5943 * @param[out] ps_cfg
5944 * Pointer to config structure to be updated
5945 *
5946 * @return error status
5947 *
5948 * @remarks none
5949 *
5950 *******************************************************************************
5951 */
ih264e_set_sei_cll_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5952 static WORD32 ih264e_set_sei_cll_params(void *pv_api_ip,
5953 void *pv_api_op,
5954 cfg_params_t *ps_cfg)
5955 {
5956 /* ctrl call I/O structures */
5957 ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip;
5958 ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op;
5959 sei_params_t *ps_sei = &ps_cfg->s_sei;
5960
5961 ps_op->u4_error_code = 0;
5962
5963 ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag;
5964
5965 ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level;
5966 ps_sei->s_sei_cll_params.u2_max_pic_average_light_level =
5967 ps_ip->u2_max_pic_average_light_level;
5968
5969 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
5970 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
5971
5972 return IV_SUCCESS;
5973 }
5974
5975 /**
5976 *******************************************************************************
5977 *
5978 * @brief
5979 * Sets ambient viewing environment sei params
5980 *
5981 * @par Description:
5982 * Supplemental enhancement information
5983 *
5984 * @param[in] pv_api_ip
5985 * Pointer to input argument structure
5986 *
5987 * @param[out] pv_api_op
5988 * Pointer to output argument structure
5989 *
5990 * @param[out] ps_cfg
5991 * Pointer to config structure to be updated
5992 *
5993 * @return error status
5994 *
5995 * @remarks none
5996 *
5997 *******************************************************************************
5998 */
ih264e_set_sei_ave_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)5999 static WORD32 ih264e_set_sei_ave_params(void *pv_api_ip,
6000 void *pv_api_op,
6001 cfg_params_t *ps_cfg)
6002 {
6003 /* ctrl call I/O structures */
6004 ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip;
6005 ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op;
6006 sei_params_t *ps_sei = &ps_cfg->s_sei;
6007
6008 ps_op->u4_error_code = 0;
6009
6010 ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag;
6011
6012 ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance;
6013 ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x;
6014 ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y;
6015
6016 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6017 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6018
6019 return IV_SUCCESS;
6020 }
6021
6022 /**
6023 *******************************************************************************
6024 *
6025 * @brief
6026 * Sets content color volume sei params
6027 *
6028 * @par Description:
6029 * Supplemental enhancement information
6030 *
6031 * @param[in] pv_api_ip
6032 * Pointer to input argument structure
6033 *
6034 * @param[out] pv_api_op
6035 * Pointer to output argument structure
6036 *
6037 * @param[out] ps_cfg
6038 * Pointer to config structure to be updated
6039 *
6040 * @return error status
6041 *
6042 * @remarks none
6043 *
6044 *******************************************************************************
6045 */
ih264e_set_sei_ccv_params(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6046 static WORD32 ih264e_set_sei_ccv_params(void *pv_api_ip,
6047 void *pv_api_op,
6048 cfg_params_t *ps_cfg)
6049 {
6050 WORD32 i4_count;
6051 /* ctrl call I/O structures */
6052 ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip;
6053 ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op;
6054 sei_params_t *ps_sei = &ps_cfg->s_sei;
6055
6056 ps_op->u4_error_code = 0;
6057
6058 ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag;
6059
6060 ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag;
6061 ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag;
6062 ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag =
6063 ps_ip->u1_ccv_primaries_present_flag;
6064 ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag =
6065 ps_ip->u1_ccv_min_luminance_value_present_flag;
6066 ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag =
6067 ps_ip->u1_ccv_max_luminance_value_present_flag;
6068 ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag =
6069 ps_ip->u1_ccv_avg_luminance_value_present_flag;
6070 ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits =
6071 ps_ip->u1_ccv_reserved_zero_2bits;
6072
6073 for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
6074 {
6075 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] =
6076 ps_ip->ai4_ccv_primaries_x[i4_count];
6077 ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] =
6078 ps_ip->ai4_ccv_primaries_y[i4_count];
6079 }
6080
6081 ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value;
6082 ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value;
6083 ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value;
6084
6085 ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high;
6086 ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low;
6087
6088 return IV_SUCCESS;
6089 }
6090
6091 /**
6092 *******************************************************************************
6093 *
6094 * @brief
6095 * Sets number of cores
6096 *
6097 * @par Description:
6098 * Sets number of cores
6099 *
6100 * @param[in] ps_codec_obj
6101 * Pointer to codec object at API level
6102 *
6103 * @param[in] pv_api_ip
6104 * Pointer to input argument structure
6105 *
6106 * @param[out] pv_api_op
6107 * Pointer to output argument structure
6108 *
6109 * @returns error status
6110 *
6111 * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
6112 *
6113 *******************************************************************************
6114 */
ih264e_set_num_cores(void * pv_api_ip,void * pv_api_op,cfg_params_t * ps_cfg)6115 static WORD32 ih264e_set_num_cores(void *pv_api_ip,
6116 void *pv_api_op,
6117 cfg_params_t *ps_cfg)
6118 {
6119 /* ctrl call I/O structures */
6120 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
6121 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
6122
6123 ps_op->s_ive_op.u4_error_code = 0;
6124
6125 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
6126
6127 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
6128 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
6129
6130 return IV_SUCCESS;
6131 }
6132
6133 /**
6134 *******************************************************************************
6135 *
6136 * @brief
6137 * Resets encoder state
6138 *
6139 * @par Description:
6140 * Resets encoder state by calling ih264e_init()
6141 *
6142 * @param[in] ps_codec_obj
6143 * Pointer to codec object at API level
6144 *
6145 * @param[in] pv_api_ip
6146 * Pointer to input argument structure
6147 *
6148 * @param[out] pv_api_op
6149 * Pointer to output argument structure
6150 *
6151 * @returns error status
6152 *
6153 * @remarks none
6154 *
6155 *******************************************************************************
6156 */
ih264e_reset(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6157 static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj,
6158 void *pv_api_ip,
6159 void *pv_api_op)
6160 {
6161 /* codec ctxt */
6162 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
6163
6164 /* ctrl call I/O structures */
6165 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
6166
6167 UNUSED(pv_api_ip);
6168
6169 ps_op->s_ive_op.u4_error_code = 0;
6170
6171 if (ps_codec != NULL)
6172 {
6173 ih264e_init(ps_codec);
6174 }
6175 else
6176 {
6177 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
6178 }
6179
6180 return IV_SUCCESS;
6181 }
6182
6183 /**
6184 *******************************************************************************
6185 *
6186 * @brief
6187 * Codec control call
6188 *
6189 * @par Description:
6190 * Codec control call which in turn calls appropriate calls based on sub-command
6191 *
6192 * @param[in] ps_codec_obj
6193 * Pointer to codec object at API level
6194 *
6195 * @param[in] pv_api_ip
6196 * Pointer to input argument structure
6197 *
6198 * @param[out] pv_api_op
6199 * Pointer to output argument structure
6200 *
6201 * @returns error status
6202 *
6203 * @remarks none
6204 *
6205 *******************************************************************************
6206 */
ih264e_ctl(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)6207 static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj,
6208 void *pv_api_ip,
6209 void *pv_api_op)
6210 {
6211 /* codec ctxt */
6212 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
6213
6214 /* ctrl call I/O structures */
6215 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip;
6216 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op;
6217
6218 /* ctrl call sub cmd */
6219 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd;
6220
6221 /* error status */
6222 IV_STATUS_T ret = IV_SUCCESS;
6223
6224 /* temp var */
6225 WORD32 i;
6226 cfg_params_t *ps_cfg = NULL;
6227
6228 /* control call is for configuring encoding params, this is not to be called
6229 * before a successful init call */
6230 if (ps_codec->i4_init_done != 1)
6231 {
6232 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
6233 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
6234 return IV_FAIL;
6235 }
6236
6237 /* make it thread safe */
6238 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
6239
6240 /* find a free config param set to hold current parameters */
6241 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
6242 {
6243 if (0 == ps_codec->as_cfg[i].u4_is_valid)
6244 {
6245 ps_cfg = &ps_codec->as_cfg[i];
6246 break;
6247 }
6248 }
6249
6250 /* If all are invalid, then start overwriting from the head config params */
6251 if (NULL == ps_cfg)
6252 {
6253 ps_cfg = &ps_codec->as_cfg[0];
6254 }
6255
6256 ps_cfg->u4_is_valid = 1;
6257
6258 ps_cfg->e_cmd = sub_cmd;
6259
6260 switch (sub_cmd)
6261 {
6262 case IVE_CMD_CTL_SET_DIMENSIONS:
6263 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
6264 break;
6265
6266 case IVE_CMD_CTL_SET_FRAMERATE:
6267 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
6268 break;
6269
6270 case IVE_CMD_CTL_SET_BITRATE:
6271 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
6272 break;
6273
6274 case IVE_CMD_CTL_SET_FRAMETYPE:
6275 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
6276 break;
6277
6278 case IVE_CMD_CTL_SET_QP:
6279 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg);
6280 break;
6281
6282 case IVE_CMD_CTL_SET_ENC_MODE:
6283 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
6284 break;
6285
6286 case IVE_CMD_CTL_SET_VBV_PARAMS:
6287 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
6288 break;
6289
6290 case IVE_CMD_CTL_SET_AIR_PARAMS:
6291 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
6292 break;
6293
6294 case IVE_CMD_CTL_SET_ME_PARAMS:
6295 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
6296 break;
6297
6298 case IVE_CMD_CTL_SET_IPE_PARAMS:
6299 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
6300 break;
6301
6302 case IVE_CMD_CTL_SET_GOP_PARAMS:
6303 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
6304 break;
6305
6306 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
6307 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
6308 break;
6309
6310 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
6311 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
6312 break;
6313
6314 case IVE_CMD_CTL_SET_VUI_PARAMS:
6315 ret = ih264e_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
6316 break;
6317
6318 case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS:
6319 ret = ih264e_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg);
6320 break;
6321
6322 case IVE_CMD_CTL_SET_SEI_CLL_PARAMS:
6323 ret = ih264e_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg);
6324 break;
6325
6326 case IVE_CMD_CTL_SET_SEI_AVE_PARAMS:
6327 ret = ih264e_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg);
6328 break;
6329
6330 case IVE_CMD_CTL_SET_SEI_CCV_PARAMS:
6331 ret = ih264e_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg);
6332 break;
6333
6334 case IVE_CMD_CTL_RESET:
6335
6336 /* invalidate config param struct as it is being served right away */
6337 ps_codec->as_cfg[i].u4_is_valid = 0;
6338
6339 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op);
6340 break;
6341
6342 case IVE_CMD_CTL_SETDEFAULT:
6343 {
6344 /* ctrl call I/O structures */
6345 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
6346
6347 /* invalidate config param struct as it is being served right away */
6348 ps_codec->as_cfg[i].u4_is_valid = 0;
6349
6350 /* error status */
6351 ret = ih264e_set_default_params(ps_cfg);
6352
6353 ps_op->s_ive_op.u4_error_code = ret;
6354
6355 break;
6356 }
6357
6358 case IVE_CMD_CTL_FLUSH:
6359
6360 /* invalidate config param struct as it is being served right away */
6361 ps_codec->as_cfg[i].u4_is_valid = 0;
6362
6363 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
6364 break;
6365
6366 case IVE_CMD_CTL_GETBUFINFO:
6367
6368 /* invalidate config param struct as it is being served right away */
6369 ps_codec->as_cfg[i].u4_is_valid = 0;
6370
6371 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op);
6372 break;
6373
6374 case IVE_CMD_CTL_GETVERSION:
6375 {
6376 /* ctrl call I/O structures */
6377 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
6378 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
6379
6380 /* invalidate config param struct as it is being served right away */
6381 ps_codec->as_cfg[i].u4_is_valid = 0;
6382
6383 /* error status */
6384 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
6385
6386 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0)
6387 {
6388 ps_op->s_ive_op.u4_error_code =
6389 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6390 ret = IV_FAIL;
6391 }
6392 else
6393 {
6394 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
6395 ps_ip->s_ive_ip.u4_version_bufsize);
6396
6397 if (ret != IV_SUCCESS)
6398 {
6399 ps_op->s_ive_op.u4_error_code =
6400 IH264E_CXA_VERS_BUF_INSUFFICIENT;
6401 ret = IV_FAIL;
6402 }
6403 }
6404 break;
6405 }
6406
6407 case IVE_CMD_CTL_SET_NUM_CORES:
6408 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
6409 break;
6410
6411 default:
6412 /* invalidate config param struct as it is being served right away */
6413 ps_codec->as_cfg[i].u4_is_valid = 0;
6414
6415 DEBUG("Warning !! unrecognized control api command \n");
6416 break;
6417 }
6418
6419 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
6420
6421 return ret;
6422 }
6423
6424 /**
6425 *******************************************************************************
6426 *
6427 * @brief
6428 * Codec entry point function. All the function calls to the codec are done
6429 * using this function with different values specified in command
6430 *
6431 * @par Description:
6432 * Arguments are tested for validity and then based on the command
6433 * appropriate function is called
6434 *
6435 * @param[in] ps_handle
6436 * API level handle for codec
6437 *
6438 * @param[in] pv_api_ip
6439 * Input argument structure
6440 *
6441 * @param[out] pv_api_op
6442 * Output argument structure
6443 *
6444 * @returns error_status
6445 *
6446 * @remarks
6447 *
6448 *******************************************************************************
6449 */
ih264e_api_function(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)6450 IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle,
6451 void *pv_api_ip,
6452 void *pv_api_op)
6453 {
6454 /* api command */
6455 WORD32 command = IV_CMD_NA;
6456
6457 /* error status */
6458 IV_STATUS_T e_status;
6459 WORD32 ret;
6460
6461 /* tmp var */
6462 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip;
6463
6464 /* validate input / output structures */
6465 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op);
6466
6467 if (e_status != IV_SUCCESS)
6468 {
6469 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1));
6470 return IV_FAIL;
6471 }
6472
6473 pu4_ptr_cmd++;
6474
6475 command = *pu4_ptr_cmd;
6476
6477 switch (command)
6478 {
6479 case IV_CMD_GET_NUM_MEM_REC:
6480 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op);
6481 break;
6482
6483 case IV_CMD_FILL_NUM_MEM_REC:
6484 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op);
6485 break;
6486
6487 case IV_CMD_INIT:
6488 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
6489 break;
6490
6491 case IV_CMD_RETRIEVE_MEMREC:
6492 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
6493 break;
6494
6495 case IVE_CMD_VIDEO_CTL:
6496 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op);
6497 break;
6498
6499 case IVE_CMD_VIDEO_ENCODE:
6500 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op);
6501 break;
6502
6503 default:
6504 ret = IV_FAIL;
6505 break;
6506 }
6507
6508 return (IV_STATUS_T) ret;
6509 }
6510