1 /*
2 * Copyright © 2006,2009,2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include <errno.h>
29 #include <stdarg.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35 #include <strings.h>
36
37 #include "intel_chipset.h"
38 #include "intel_reg.h"
39
40 #include "intel_reg_spec.h"
41
42 /**
43 * DEBUGSTRING:
44 * @result: character string where to write
45 * @len: maximum number of bytes to write
46 * @reg: register offset
47 * @val: register value
48 * @devid: PCI device ID
49 *
50 * Print the decoded representation of the register value into @result.
51 *
52 * Returns: Number of bytes written to @result
53 */
54 #define _DEBUGSTRING(func) \
55 int func(char *result, int len, int reg, uint32_t val, uint32_t devid)
56 #define DEBUGSTRING(func) static _DEBUGSTRING(func)
57
58 /* snprintf that returns 0 when the thing didn't fit */
59 static int __attribute__((format(printf, 3, 4)))
z_snprintf(char * str,size_t size,const char * fmt,...)60 z_snprintf(char *str, size_t size, const char *fmt, ...)
61 {
62 va_list ap;
63 int ret;
64
65 va_start(ap, fmt);
66 ret = vsnprintf(str, size, fmt, ap);
67 va_end(ap);
68
69 if (ret >= size) {
70 fprintf(stderr, "snprintf() returned %d, expected < %zu\n",
71 ret, size);
72 return 0;
73 }
74
75 return ret;
76 }
77
DEBUGSTRING(i830_16bit_func)78 DEBUGSTRING(i830_16bit_func)
79 {
80 return z_snprintf(result, len, "0x%04x", (uint16_t) val);
81 }
82
DEBUGSTRING(i830_debug_dcc)83 DEBUGSTRING(i830_debug_dcc)
84 {
85 const char *addressing = NULL;
86
87 if (!IS_MOBILE(devid))
88 return 0;
89
90 if (IS_GEN4(devid)) {
91 if (val & (1 << 1))
92 addressing = "dual channel interleaved";
93 else
94 addressing = "single or dual channel asymmetric";
95 } else {
96 switch (val & 3) {
97 case 0:
98 addressing = "single channel";
99 break;
100 case 1:
101 addressing = "dual channel asymmetric";
102 break;
103 case 2:
104 addressing = "dual channel interleaved";
105 break;
106 case 3:
107 addressing = "unknown channel layout";
108 break;
109 }
110 }
111
112 return z_snprintf(result, len, "%s, XOR randomization: %sabled, XOR bit: %d",
113 addressing,
114 (val & (1 << 10)) ? "dis" : "en",
115 (val & (1 << 9)) ? 17 : 11);
116 }
117
DEBUGSTRING(i830_debug_chdecmisc)118 DEBUGSTRING(i830_debug_chdecmisc)
119 {
120 const char *enhmodesel = NULL;
121
122 switch ((val >> 5) & 3) {
123 case 1:
124 enhmodesel = "XOR bank/rank";
125 break;
126 case 2:
127 enhmodesel = "swap bank";
128 break;
129 case 3:
130 enhmodesel = "XOR bank";
131 break;
132 case 0:
133 enhmodesel = "none";
134 break;
135 }
136
137 return z_snprintf(result, len,
138 "%s, ch2 enh %sabled, ch1 enh %sabled, "
139 "ch0 enh %sabled, "
140 "flex %sabled, ep %spresent", enhmodesel,
141 (val & (1 << 4)) ? "en" : "dis",
142 (val & (1 << 3)) ? "en" : "dis",
143 (val & (1 << 2)) ? "en" : "dis",
144 (val & (1 << 1)) ? "en" : "dis",
145 (val & (1 << 0)) ? "" : "not ");
146 }
147
DEBUGSTRING(i830_debug_xyminus1)148 DEBUGSTRING(i830_debug_xyminus1)
149 {
150 return z_snprintf(result, len, "%d, %d", (val & 0xffff) + 1,
151 ((val & 0xffff0000) >> 16) + 1);
152 }
153
DEBUGSTRING(i830_debug_yxminus1)154 DEBUGSTRING(i830_debug_yxminus1)
155 {
156 return z_snprintf(result, len, "%d, %d", ((val & 0xffff0000) >> 16) + 1,
157 (val & 0xffff) + 1);
158 }
159
DEBUGSTRING(i830_debug_xy)160 DEBUGSTRING(i830_debug_xy)
161 {
162 return z_snprintf(result, len, "%d, %d", (val & 0xffff), ((val & 0xffff0000) >> 16));
163 }
164
DEBUGSTRING(i830_debug_dspstride)165 DEBUGSTRING(i830_debug_dspstride)
166 {
167 return z_snprintf(result, len, "%d bytes", val);
168 }
169
DEBUGSTRING(i830_debug_dspcntr)170 DEBUGSTRING(i830_debug_dspcntr)
171 {
172 const char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
173 char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
174 if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid))
175 return z_snprintf(result, len, "%s", enabled);
176 else
177 return z_snprintf(result, len, "%s, pipe %c", enabled, plane);
178 }
179
DEBUGSTRING(i830_debug_pipeconf)180 DEBUGSTRING(i830_debug_pipeconf)
181 {
182 const char *enabled = val & PIPEACONF_ENABLE ? "enabled" : "disabled";
183 const char *bit30;
184 char buf[256];
185 int buf_len;
186
187 if (IS_GEN2(devid) || IS_GEN3(devid))
188 bit30 = val & PIPEACONF_DOUBLE_WIDE ?
189 "double-wide" : "single-wide";
190 else
191 bit30 = val & I965_PIPECONF_ACTIVE ? "active" : "inactive";
192
193 buf_len = z_snprintf(buf, sizeof(buf), "%s, %s", enabled, bit30);
194
195 if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) {
196 const char *interlace;
197 int interlace_mode;
198
199 if ((IS_IVYBRIDGE(devid) || IS_HASWELL(devid) ||
200 IS_BROADWELL(devid) || IS_GEN9(devid)))
201 interlace_mode = (val >> 21) & 3;
202 else
203 interlace_mode = (val >> 21) & 7;
204
205 switch (interlace_mode) {
206 case 0:
207 interlace = "pf-pd";
208 break;
209 case 1:
210 interlace = "pf-id";
211 break;
212 case 3:
213 interlace = "if-id";
214 break;
215 case 4:
216 interlace = "if-id-dbl";
217 break;
218 case 5:
219 interlace = "pf-id-dbl";
220 break;
221 default:
222 interlace = "rsvd";
223 break;
224 }
225 if (buf_len < sizeof(buf))
226 buf_len += z_snprintf(&buf[buf_len], sizeof(buf) - buf_len,
227 ", %s", interlace);
228 } else if (IS_GEN4(devid) || IS_VALLEYVIEW(devid) ||
229 IS_CHERRYVIEW(devid)) {
230 const char *interlace;
231
232 switch ((val >> 21) & 7) {
233 case 0:
234 case 1:
235 case 2:
236 case 3:
237 interlace = "progressive";
238 break;
239 case 4:
240 interlace = "interlaced embedded";
241 break;
242 case 5:
243 interlace = "interlaced";
244 break;
245 case 6:
246 interlace = "interlaced sdvo";
247 break;
248 case 7:
249 interlace = "interlaced legacy";
250 break;
251 }
252 if (buf_len < sizeof(buf))
253 buf_len += z_snprintf(&buf[buf_len], sizeof(buf) - buf_len,
254 ", %s", interlace);
255 }
256
257 if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) ||
258 IS_GEN6(devid) || IS_GEN5(devid)) {
259 const char *rotation;
260
261 switch ((val >> 14) & 3) {
262 case 0:
263 rotation = "rotate 0";
264 break;
265 case 1:
266 rotation = "rotate 90";
267 break;
268 case 2:
269 rotation = "rotate 180";
270 break;
271 case 3:
272 rotation = "rotate 270";
273 break;
274 }
275 if (buf_len < sizeof(buf))
276 buf_len += z_snprintf(&buf[buf_len], sizeof(buf) - buf_len,
277 ", %s", rotation);
278 }
279
280 if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid)) {
281 const char *bpc;
282
283 switch (val & (7 << 5)) {
284 case PIPECONF_8BPP:
285 bpc = "8bpc";
286 break;
287 case PIPECONF_10BPP:
288 bpc = "10bpc";
289 break;
290 case PIPECONF_6BPP:
291 bpc = "6bpc";
292 break;
293 case PIPECONF_12BPP:
294 bpc = "12bpc";
295 break;
296 default:
297 bpc = "invalid bpc";
298 break;
299 }
300 if (buf_len < sizeof(buf))
301 buf_len += z_snprintf(&buf[buf_len], sizeof(buf) - buf_len,
302 ", %s", bpc);
303 }
304
305 return z_snprintf(result, len, "%s", buf);
306 }
307
DEBUGSTRING(i830_debug_pipestat)308 DEBUGSTRING(i830_debug_pipestat)
309 {
310 const char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
311 const char *_CRC_ERROR_ENABLE =
312 val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
313 const char *_CRC_DONE_ENABLE =
314 val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
315 const char *_GMBUS_EVENT_ENABLE =
316 val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
317 const char *_VSYNC_INT_ENABLE =
318 val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
319 const char *_DLINE_COMPARE_ENABLE =
320 val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
321 const char *_DPST_EVENT_ENABLE =
322 val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
323 const char *_LBLC_EVENT_ENABLE =
324 val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
325 const char *_OFIELD_INT_ENABLE =
326 val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
327 const char *_EFIELD_INT_ENABLE =
328 val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
329 const char *_SVBLANK_INT_ENABLE =
330 val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
331 const char *_VBLANK_INT_ENABLE =
332 val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
333 const char *_OREG_UPDATE_ENABLE =
334 val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
335 const char *_CRC_ERROR_INT_STATUS =
336 val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
337 const char *_CRC_DONE_INT_STATUS =
338 val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
339 const char *_GMBUS_INT_STATUS =
340 val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
341 const char *_VSYNC_INT_STATUS =
342 val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
343 const char *_DLINE_COMPARE_STATUS =
344 val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
345 const char *_DPST_EVENT_STATUS =
346 val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
347 const char *_LBLC_EVENT_STATUS =
348 val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
349 const char *_OFIELD_INT_STATUS =
350 val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
351 const char *_EFIELD_INT_STATUS =
352 val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
353 const char *_SVBLANK_INT_STATUS =
354 val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
355 const char *_VBLANK_INT_STATUS =
356 val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
357 const char *_OREG_UPDATE_STATUS =
358 val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
359 return z_snprintf(result, len,
360 "status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
361 _FIFO_UNDERRUN,
362 _CRC_ERROR_ENABLE,
363 _CRC_DONE_ENABLE,
364 _GMBUS_EVENT_ENABLE,
365 _VSYNC_INT_ENABLE,
366 _DLINE_COMPARE_ENABLE,
367 _DPST_EVENT_ENABLE,
368 _LBLC_EVENT_ENABLE,
369 _OFIELD_INT_ENABLE,
370 _EFIELD_INT_ENABLE,
371 _SVBLANK_INT_ENABLE,
372 _VBLANK_INT_ENABLE,
373 _OREG_UPDATE_ENABLE,
374 _CRC_ERROR_INT_STATUS,
375 _CRC_DONE_INT_STATUS,
376 _GMBUS_INT_STATUS,
377 _VSYNC_INT_STATUS,
378 _DLINE_COMPARE_STATUS,
379 _DPST_EVENT_STATUS,
380 _LBLC_EVENT_STATUS,
381 _OFIELD_INT_STATUS,
382 _EFIELD_INT_STATUS,
383 _SVBLANK_INT_STATUS,
384 _VBLANK_INT_STATUS,
385 _OREG_UPDATE_STATUS);
386 }
387
DEBUGSTRING(ivb_debug_port)388 DEBUGSTRING(ivb_debug_port)
389 {
390 const char *drrs = NULL;
391 switch (val & (2 << 30)) {
392 case PORT_DBG_DRRS_HW_STATE_OFF:
393 drrs = "off";
394 break;
395 case PORT_DBG_DRRS_HW_STATE_LOW:
396 drrs = "low";
397 break;
398 case PORT_DBG_DRRS_HW_STATE_HIGH:
399 drrs = "high";
400 break;
401 }
402 return z_snprintf(result, len, "HW DRRS %s",
403 drrs);
404 }
405
DEBUGSTRING(i830_debug_hvtotal)406 DEBUGSTRING(i830_debug_hvtotal)
407 {
408 return z_snprintf(result, len, "%d active, %d total",
409 (val & 0xffff) + 1,
410 ((val & 0xffff0000) >> 16) + 1);
411 }
412
DEBUGSTRING(i830_debug_hvsyncblank)413 DEBUGSTRING(i830_debug_hvsyncblank)
414 {
415 return z_snprintf(result, len, "%d start, %d end",
416 (val & 0xffff) + 1,
417 ((val & 0xffff0000) >> 16) + 1);
418 }
419
DEBUGSTRING(i830_debug_vgacntrl)420 DEBUGSTRING(i830_debug_vgacntrl)
421 {
422 return z_snprintf(result, len, "%s",
423 val & VGA_DISP_DISABLE ? "disabled" : "enabled");
424 }
425
DEBUGSTRING(i830_debug_fp)426 DEBUGSTRING(i830_debug_fp)
427 {
428 if (IS_PINEVIEW(devid)) {
429 return z_snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
430 ffs((val & FP_N_IGD_DIV_MASK) >>
431 FP_N_DIV_SHIFT) - 1,
432 ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
433 ((val & FP_M2_IGD_DIV_MASK) >>
434 FP_M2_DIV_SHIFT));
435 }
436 return z_snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
437 ((val & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT),
438 ((val & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT),
439 ((val & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT));
440 }
441
DEBUGSTRING(i830_debug_vga_pd)442 DEBUGSTRING(i830_debug_vga_pd)
443 {
444 int vga0_p1, vga0_p2, vga1_p1, vga1_p2;
445
446 /* XXX: i9xx version */
447
448 if (val & VGA0_PD_P1_DIV_2)
449 vga0_p1 = 2;
450 else
451 vga0_p1 = ((val & VGA0_PD_P1_MASK) >> VGA0_PD_P1_SHIFT) + 2;
452 vga0_p2 = (val & VGA0_PD_P2_DIV_4) ? 4 : 2;
453
454 if (val & VGA1_PD_P1_DIV_2)
455 vga1_p1 = 2;
456 else
457 vga1_p1 = ((val & VGA1_PD_P1_MASK) >> VGA1_PD_P1_SHIFT) + 2;
458 vga1_p2 = (val & VGA1_PD_P2_DIV_4) ? 4 : 2;
459
460 return z_snprintf(result, len, "vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d",
461 vga0_p1, vga0_p2, vga1_p1, vga1_p2);
462 }
463
DEBUGSTRING(i830_debug_pp_status)464 DEBUGSTRING(i830_debug_pp_status)
465 {
466 const char *status = val & PP_ON ? "on" : "off";
467 const char *ready = val & PP_READY ? "ready" : "not ready";
468 const char *seq = "unknown";
469
470 switch (val & PP_SEQUENCE_MASK) {
471 case PP_SEQUENCE_NONE:
472 seq = "idle";
473 break;
474 case PP_SEQUENCE_ON:
475 seq = "on";
476 break;
477 case PP_SEQUENCE_OFF:
478 seq = "off";
479 break;
480 }
481
482 return z_snprintf(result, len, "%s, %s, sequencing %s", status, ready, seq);
483 }
484
DEBUGSTRING(i830_debug_pp_control)485 DEBUGSTRING(i830_debug_pp_control)
486 {
487 return z_snprintf(result, len, "power target: %s",
488 val & POWER_TARGET_ON ? "on" : "off");
489 }
490
DEBUGSTRING(i830_debug_dpll)491 DEBUGSTRING(i830_debug_dpll)
492 {
493 const char *enabled = val & DPLL_VCO_ENABLE ? "enabled" : "disabled";
494 const char *dvomode = val & DPLL_DVO_HIGH_SPEED ? "dvo" : "non-dvo";
495 const char *vgamode = val & DPLL_VGA_MODE_DIS ? "" : ", VGA";
496 const char *mode = "unknown";
497 const char *clock = "unknown";
498 const char *fpextra = val & DISPLAY_RATE_SELECT_FPA1 ? ", using FPx1!" : "";
499 char sdvoextra[20];
500 int p1 = 0, p2 = 0;
501
502 if (IS_GEN2(devid)) {
503 #if 0 /* removed due to use of INREG */
504 char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
505
506 if (is_lvds) {
507 mode = "LVDS";
508 p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS)
509 >> DPLL_FPA01_P1_POST_DIV_SHIFT);
510 if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) ==
511 LVDS_CLKB_POWER_UP)
512 p2 = 7;
513 else
514 p2 = 14;
515
516 } else {
517 mode = "DAC/serial";
518 if (val & PLL_P1_DIVIDE_BY_TWO) {
519 p1 = 2;
520 } else {
521 /* Map the number in the field to (3, 33) */
522 p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830)
523 >> DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
524 }
525 if (val & PLL_P2_DIVIDE_BY_4)
526 p2 = 4;
527 else
528 p2 = 2;
529 }
530 #endif
531 } else {
532 if (IS_PINEVIEW(devid)) {
533 p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
534 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
535 } else {
536 p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
537 DPLL_FPA01_P1_POST_DIV_SHIFT);
538 }
539 switch (val & DPLL_MODE_MASK) {
540 case DPLLB_MODE_DAC_SERIAL:
541 mode = "DAC/serial";
542 p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
543 break;
544 case DPLLB_MODE_LVDS:
545 mode = "LVDS";
546 p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
547 break;
548 }
549 }
550
551 switch (val & PLL_REF_INPUT_MASK) {
552 case PLL_REF_INPUT_DREFCLK:
553 clock = "default";
554 break;
555 case PLL_REF_INPUT_TVCLKINA:
556 clock = "TV A";
557 break;
558 case PLL_REF_INPUT_TVCLKINBC:
559 clock = "TV B/C";
560 break;
561 case PLLB_REF_INPUT_SPREADSPECTRUMIN:
562 if (reg == DPLL_B)
563 clock = "spread spectrum";
564 break;
565 }
566
567 if (IS_945(devid)) {
568 sprintf(sdvoextra, ", SDVO mult %d",
569 (int)((val & SDVO_MULTIPLIER_MASK) >>
570 SDVO_MULTIPLIER_SHIFT_HIRES) + 1);
571 } else {
572 sdvoextra[0] = '\0';
573 }
574
575 return z_snprintf(result, len, "%s, %s%s, %s clock, %s mode, p1 = %d, "
576 "p2 = %d%s%s",
577 enabled, dvomode, vgamode, clock, mode, p1, p2,
578 fpextra, sdvoextra);
579 }
580
DEBUGSTRING(i830_debug_dpll_test)581 DEBUGSTRING(i830_debug_dpll_test)
582 {
583 const char *dpllandiv = val & DPLLA_TEST_N_BYPASS ? ", DPLLA N bypassed" : "";
584 const char *dpllamdiv = val & DPLLA_TEST_M_BYPASS ? ", DPLLA M bypassed" : "";
585 const char *dpllainput = val & DPLLA_INPUT_BUFFER_ENABLE ?
586 "" : ", DPLLA input buffer disabled";
587 const char *dpllbndiv = val & DPLLB_TEST_N_BYPASS ? ", DPLLB N bypassed" : "";
588 const char *dpllbmdiv = val & DPLLB_TEST_M_BYPASS ? ", DPLLB M bypassed" : "";
589 const char *dpllbinput = val & DPLLB_INPUT_BUFFER_ENABLE ?
590 "" : ", DPLLB input buffer disabled";
591
592 return z_snprintf(result, len, "%s%s%s%s%s%s",
593 dpllandiv, dpllamdiv, dpllainput,
594 dpllbndiv, dpllbmdiv, dpllbinput);
595 }
596
DEBUGSTRING(i830_debug_adpa)597 DEBUGSTRING(i830_debug_adpa)
598 {
599 char disp_pipe = (val & ADPA_PIPE_B_SELECT) ? 'B' : 'A';
600 const char *enable = (val & ADPA_DAC_ENABLE) ? "enabled" : "disabled";
601 char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
602 char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
603
604 if (HAS_CPT)
605 disp_pipe = val & (1<<29) ? 'B' : 'A';
606
607 if (HAS_PCH_SPLIT(devid))
608 return z_snprintf(result, len, "%s, transcoder %c, %chsync, %cvsync",
609 enable, disp_pipe, hsync, vsync);
610 else
611 return z_snprintf(result, len, "%s, pipe %c, %chsync, %cvsync",
612 enable, disp_pipe, hsync, vsync);
613 }
614
DEBUGSTRING(i830_debug_lvds)615 DEBUGSTRING(i830_debug_lvds)
616 {
617 char disp_pipe = val & LVDS_PIPEB_SELECT ? 'B' : 'A';
618 const char *enable = val & LVDS_PORT_EN ? "enabled" : "disabled";
619 int depth;
620 const char *channels;
621
622 if ((val & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
623 depth = 24;
624 else
625 depth = 18;
626 if ((val & LVDS_B0B3_POWER_MASK) == LVDS_B0B3_POWER_UP)
627 channels = "2 channels";
628 else
629 channels = "1 channel";
630
631 if (HAS_CPT)
632 disp_pipe = val & (1<<29) ? 'B' : 'A';
633
634 return z_snprintf(result, len, "%s, pipe %c, %d bit, %s",
635 enable, disp_pipe, depth, channels);
636 }
637
DEBUGSTRING(i830_debug_dvo)638 DEBUGSTRING(i830_debug_dvo)
639 {
640 const char *enable = val & DVO_ENABLE ? "enabled" : "disabled";
641 char disp_pipe = val & DVO_PIPE_B_SELECT ? 'B' : 'A';
642 const char *stall;
643 char hsync = val & DVO_HSYNC_ACTIVE_HIGH ? '+' : '-';
644 char vsync = val & DVO_VSYNC_ACTIVE_HIGH ? '+' : '-';
645
646 switch (val & DVO_PIPE_STALL_MASK) {
647 case DVO_PIPE_STALL_UNUSED:
648 stall = "no stall";
649 break;
650 case DVO_PIPE_STALL:
651 stall = "stall";
652 break;
653 case DVO_PIPE_STALL_TV:
654 stall = "TV stall";
655 break;
656 default:
657 stall = "unknown stall";
658 break;
659 }
660
661 return z_snprintf(result, len, "%s, pipe %c, %s, %chsync, %cvsync",
662 enable, disp_pipe, stall, hsync, vsync);
663 }
664
DEBUGSTRING(i830_debug_sdvo)665 DEBUGSTRING(i830_debug_sdvo)
666 {
667 const char *enable = val & SDVO_ENABLE ? "enabled" : "disabled";
668 char disp_pipe = val & SDVO_PIPE_B_SELECT ? 'B' : 'A';
669 const char *stall = val & SDVO_STALL_SELECT ? "enabled" : "disabled";
670 const char *detected = val & SDVO_DETECTED ? "" : "not ";
671 const char *gang = val & SDVOC_GANG_MODE ? ", gang mode" : "";
672 char sdvoextra[20];
673
674 if (IS_915(devid)) {
675 sprintf(sdvoextra, ", SDVO mult %d",
676 (int)((val & SDVO_PORT_MULTIPLY_MASK) >>
677 SDVO_PORT_MULTIPLY_SHIFT) + 1);
678 } else {
679 sdvoextra[0] = '\0';
680 }
681
682 return z_snprintf(result, len, "%s, pipe %c, stall %s, %sdetected%s%s",
683 enable, disp_pipe, stall, detected, sdvoextra, gang);
684 }
685
DEBUGSTRING(i830_debug_dspclk_gate_d)686 DEBUGSTRING(i830_debug_dspclk_gate_d)
687 {
688 const char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
689 const char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
690 const char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
691 const char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
692 const char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
693 const char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
694 const char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
695 const char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
696 const char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
697 const char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
698 const char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
699 const char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
700 const char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
701 const char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
702 const char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
703 const char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
704 const char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
705 const char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
706 const char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
707 const char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
708 const char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
709 const char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
710 const char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
711 const char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
712 const char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
713 const char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
714 const char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
715 const char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
716 const char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
717 const char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
718 const char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
719 const char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
720
721 return z_snprintf(result, len,
722 "clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
723 DPUNIT_B, VSUNIT, VRHUNIT, VRDUNIT, AUDUNIT, DPUNIT_A, DPCUNIT,
724 TVRUNIT, TVCUNIT, TVFUNIT, TVEUNIT, DVSUNIT, DSSUNIT, DDBUNIT,
725 DPRUNIT, DPFUNIT, DPBMUNIT, DPLSUNIT, DPLUNIT, DPOUNIT, DPBUNIT,
726 DCUNIT, DPUNIT, VRUNIT, OVHUNIT, DPIOUNIT, OVFUNIT, OVBUNIT,
727 OVRUNIT, OVCUNIT, OVUUNIT, OVLUNIT);
728 }
729
DEBUGSTRING(i810_debug_915_fence)730 DEBUGSTRING(i810_debug_915_fence)
731 {
732 char format = (val & 1 << 12) ? 'Y' : 'X';
733 int pitch = 128 << ((val & 0x70) >> 4);
734 unsigned int offset = val & 0x0ff00000;
735 int size = (1024 * 1024) << ((val & 0x700) >> 8);
736
737 if (IS_GEN4(devid) || (IS_915(devid) && reg >= FENCE_NEW))
738 return 0;
739
740 if (format == 'X')
741 pitch *= 4;
742 if (val & 1) {
743 return z_snprintf(result, len, "enabled, %c tiled, %4d pitch, 0x%08x - 0x%08x (%dkb)",
744 format, pitch, offset, offset + size,
745 size / 1024);
746 } else {
747 return z_snprintf(result, len, "disabled");
748 }
749 }
750
DEBUGSTRING(i810_debug_965_fence_start)751 DEBUGSTRING(i810_debug_965_fence_start)
752 {
753 const char *enable = (val & FENCE_VALID) ? " enabled" : "disabled";
754 char format = (val & I965_FENCE_Y_MAJOR) ? 'Y' : 'X';
755 int pitch = ((val & 0xffc) >> 2) * 128 + 128;
756 unsigned int offset = val & 0xfffff000;
757
758 if (!IS_GEN4(devid) && !IS_GEN5(devid))
759 return 0;
760
761 return z_snprintf(result, len, "%s, %c tile walk, %4d pitch, 0x%08x start",
762 enable, format, pitch, offset);
763 }
764
DEBUGSTRING(i810_debug_965_fence_end)765 DEBUGSTRING(i810_debug_965_fence_end)
766 {
767 unsigned int end = val & 0xfffff000;
768
769 if (!IS_GEN4(devid))
770 return 0;
771
772 return z_snprintf(result, len, " 0x%08x end", end);
773 }
774
775 #define DEFINEREG(reg) \
776 { reg, #reg, NULL }
777 #define DEFINEREG_16BIT(reg) \
778 { reg, #reg, i830_16bit_func }
779 #define DEFINEREG2(reg, func) \
780 { reg, #reg, func }
781
782 struct reg_debug {
783 int reg;
784 const char *name;
785 _DEBUGSTRING((*debug_output));
786 };
787
788 static const struct reg_debug intel_debug_regs[] = {
789 DEFINEREG2(DCC, i830_debug_dcc),
790 DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
791 DEFINEREG_16BIT(C0DRB0),
792 DEFINEREG_16BIT(C0DRB1),
793 DEFINEREG_16BIT(C0DRB2),
794 DEFINEREG_16BIT(C0DRB3),
795 DEFINEREG_16BIT(C1DRB0),
796 DEFINEREG_16BIT(C1DRB1),
797 DEFINEREG_16BIT(C1DRB2),
798 DEFINEREG_16BIT(C1DRB3),
799 DEFINEREG_16BIT(C0DRA01),
800 DEFINEREG_16BIT(C0DRA23),
801 DEFINEREG_16BIT(C1DRA01),
802 DEFINEREG_16BIT(C1DRA23),
803
804 DEFINEREG(PGETBL_CTL),
805
806 DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
807 DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
808 DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
809 DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
810 DEFINEREG(CACHE_MODE_0),
811 DEFINEREG(D_STATE),
812 DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
813 DEFINEREG(RENCLK_GATE_D1),
814 DEFINEREG(RENCLK_GATE_D2),
815 /* DEFINEREG(RAMCLK_GATE_D), CRL only */
816 DEFINEREG2(SDVOB, i830_debug_sdvo),
817 DEFINEREG2(SDVOC, i830_debug_sdvo),
818 /* DEFINEREG(UDIB_SVB_SHB_CODES), CRL only */
819 /* DEFINEREG(UDIB_SHA_BLANK_CODES), CRL only */
820 DEFINEREG(SDVOUDI),
821 DEFINEREG(DSPARB),
822 DEFINEREG(FW_BLC),
823 DEFINEREG(FW_BLC2),
824 DEFINEREG(FW_BLC_SELF),
825 DEFINEREG(DSPFW1),
826 DEFINEREG(DSPFW2),
827 DEFINEREG(DSPFW3),
828
829 DEFINEREG2(ADPA, i830_debug_adpa),
830 DEFINEREG2(LVDS, i830_debug_lvds),
831 DEFINEREG2(DVOA, i830_debug_dvo),
832 DEFINEREG2(DVOB, i830_debug_dvo),
833 DEFINEREG2(DVOC, i830_debug_dvo),
834 DEFINEREG(DVOA_SRCDIM),
835 DEFINEREG(DVOB_SRCDIM),
836 DEFINEREG(DVOC_SRCDIM),
837
838 DEFINEREG(BLC_PWM_CTL),
839 DEFINEREG(BLC_PWM_CTL2),
840
841 DEFINEREG2(PP_CONTROL, i830_debug_pp_control),
842 DEFINEREG2(PP_STATUS, i830_debug_pp_status),
843 DEFINEREG(PP_ON_DELAYS),
844 DEFINEREG(PP_OFF_DELAYS),
845 DEFINEREG(PP_DIVISOR),
846 DEFINEREG(PFIT_CONTROL),
847 DEFINEREG(PFIT_PGM_RATIOS),
848 DEFINEREG(PORT_HOTPLUG_EN),
849 DEFINEREG(PORT_HOTPLUG_STAT),
850
851 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
852 DEFINEREG2(DSPASTRIDE, i830_debug_dspstride),
853 DEFINEREG2(DSPAPOS, i830_debug_xy),
854 DEFINEREG2(DSPASIZE, i830_debug_xyminus1),
855 DEFINEREG(DSPABASE),
856 DEFINEREG(DSPASURF),
857 DEFINEREG(DSPATILEOFF),
858 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
859 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
860 DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
861 DEFINEREG(PIPEA_GMCH_DATA_M),
862 DEFINEREG(PIPEA_GMCH_DATA_N),
863 DEFINEREG(PIPEA_DP_LINK_M),
864 DEFINEREG(PIPEA_DP_LINK_N),
865 DEFINEREG(CURSOR_A_BASE),
866 DEFINEREG(CURSOR_A_CONTROL),
867 DEFINEREG(CURSOR_A_POSITION),
868
869 DEFINEREG2(FPA0, i830_debug_fp),
870 DEFINEREG2(FPA1, i830_debug_fp),
871 DEFINEREG2(DPLL_A, i830_debug_dpll),
872 DEFINEREG(DPLL_A_MD),
873 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
874 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
875 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
876 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
877 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
878 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
879 DEFINEREG(BCLRPAT_A),
880 DEFINEREG(VSYNCSHIFT_A),
881
882 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
883 DEFINEREG2(DSPBSTRIDE, i830_debug_dspstride),
884 DEFINEREG2(DSPBPOS, i830_debug_xy),
885 DEFINEREG2(DSPBSIZE, i830_debug_xyminus1),
886 DEFINEREG(DSPBBASE),
887 DEFINEREG(DSPBSURF),
888 DEFINEREG(DSPBTILEOFF),
889 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
890 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
891 DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
892 DEFINEREG(PIPEB_GMCH_DATA_M),
893 DEFINEREG(PIPEB_GMCH_DATA_N),
894 DEFINEREG(PIPEB_DP_LINK_M),
895 DEFINEREG(PIPEB_DP_LINK_N),
896 DEFINEREG(CURSOR_B_BASE),
897 DEFINEREG(CURSOR_B_CONTROL),
898 DEFINEREG(CURSOR_B_POSITION),
899
900 DEFINEREG2(FPB0, i830_debug_fp),
901 DEFINEREG2(FPB1, i830_debug_fp),
902 DEFINEREG2(DPLL_B, i830_debug_dpll),
903 DEFINEREG(DPLL_B_MD),
904 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
905 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
906 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
907 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
908 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
909 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
910 DEFINEREG(BCLRPAT_B),
911 DEFINEREG(VSYNCSHIFT_B),
912
913 DEFINEREG(VCLK_DIVISOR_VGA0),
914 DEFINEREG(VCLK_DIVISOR_VGA1),
915 DEFINEREG(VCLK_POST_DIV),
916 DEFINEREG2(VGACNTRL, i830_debug_vgacntrl),
917
918 DEFINEREG(TV_CTL),
919 DEFINEREG(TV_DAC),
920 DEFINEREG(TV_CSC_Y),
921 DEFINEREG(TV_CSC_Y2),
922 DEFINEREG(TV_CSC_U),
923 DEFINEREG(TV_CSC_U2),
924 DEFINEREG(TV_CSC_V),
925 DEFINEREG(TV_CSC_V2),
926 DEFINEREG(TV_CLR_KNOBS),
927 DEFINEREG(TV_CLR_LEVEL),
928 DEFINEREG(TV_H_CTL_1),
929 DEFINEREG(TV_H_CTL_2),
930 DEFINEREG(TV_H_CTL_3),
931 DEFINEREG(TV_V_CTL_1),
932 DEFINEREG(TV_V_CTL_2),
933 DEFINEREG(TV_V_CTL_3),
934 DEFINEREG(TV_V_CTL_4),
935 DEFINEREG(TV_V_CTL_5),
936 DEFINEREG(TV_V_CTL_6),
937 DEFINEREG(TV_V_CTL_7),
938 DEFINEREG(TV_SC_CTL_1),
939 DEFINEREG(TV_SC_CTL_2),
940 DEFINEREG(TV_SC_CTL_3),
941 DEFINEREG(TV_WIN_POS),
942 DEFINEREG(TV_WIN_SIZE),
943 DEFINEREG(TV_FILTER_CTL_1),
944 DEFINEREG(TV_FILTER_CTL_2),
945 DEFINEREG(TV_FILTER_CTL_3),
946 DEFINEREG(TV_CC_CONTROL),
947 DEFINEREG(TV_CC_DATA),
948 DEFINEREG(TV_H_LUMA_0),
949 DEFINEREG(TV_H_LUMA_59),
950 DEFINEREG(TV_H_CHROMA_0),
951 DEFINEREG(TV_H_CHROMA_59),
952
953 DEFINEREG(FBC_CFB_BASE),
954 DEFINEREG(FBC_LL_BASE),
955 DEFINEREG(FBC_CONTROL),
956 DEFINEREG(FBC_COMMAND),
957 DEFINEREG(FBC_STATUS),
958 DEFINEREG(FBC_CONTROL2),
959 DEFINEREG(FBC_FENCE_OFF),
960 DEFINEREG(FBC_MOD_NUM),
961
962 DEFINEREG(MI_MODE),
963 /* DEFINEREG(MI_DISPLAY_POWER_DOWN), CRL only */
964 DEFINEREG(MI_ARB_STATE),
965 DEFINEREG(MI_RDRET_STATE),
966 DEFINEREG(ECOSKPD),
967
968 DEFINEREG(DP_B),
969 DEFINEREG(DPB_AUX_CH_CTL),
970 DEFINEREG(DPB_AUX_CH_DATA1),
971 DEFINEREG(DPB_AUX_CH_DATA2),
972 DEFINEREG(DPB_AUX_CH_DATA3),
973 DEFINEREG(DPB_AUX_CH_DATA4),
974 DEFINEREG(DPB_AUX_CH_DATA5),
975
976 DEFINEREG(DP_C),
977 DEFINEREG(DPC_AUX_CH_CTL),
978 DEFINEREG(DPC_AUX_CH_DATA1),
979 DEFINEREG(DPC_AUX_CH_DATA2),
980 DEFINEREG(DPC_AUX_CH_DATA3),
981 DEFINEREG(DPC_AUX_CH_DATA4),
982 DEFINEREG(DPC_AUX_CH_DATA5),
983
984 DEFINEREG(DP_D),
985 DEFINEREG(DPD_AUX_CH_CTL),
986 DEFINEREG(DPD_AUX_CH_DATA1),
987 DEFINEREG(DPD_AUX_CH_DATA2),
988 DEFINEREG(DPD_AUX_CH_DATA3),
989 DEFINEREG(DPD_AUX_CH_DATA4),
990 DEFINEREG(DPD_AUX_CH_DATA5),
991
992 DEFINEREG(AUD_CONFIG),
993 DEFINEREG(AUD_HDMIW_STATUS),
994 DEFINEREG(AUD_CONV_CHCNT),
995 DEFINEREG(VIDEO_DIP_CTL),
996 DEFINEREG(AUD_PINW_CNTR),
997 DEFINEREG(AUD_CNTL_ST),
998 DEFINEREG(AUD_PIN_CAP),
999 DEFINEREG(AUD_PINW_CAP),
1000 DEFINEREG(AUD_PINW_UNSOLRESP),
1001 DEFINEREG(AUD_OUT_DIG_CNVT),
1002 DEFINEREG(AUD_OUT_CWCAP),
1003 DEFINEREG(AUD_GRP_CAP),
1004
1005 #define DEFINEFENCE_915(i) \
1006 { FENCE+i*4, "FENCE " #i, i810_debug_915_fence }
1007 #define DEFINEFENCE_945(i) \
1008 { FENCE_NEW+(i - 8) * 4, "FENCE " #i, i810_debug_915_fence }
1009
1010 DEFINEFENCE_915(0),
1011 DEFINEFENCE_915(1),
1012 DEFINEFENCE_915(2),
1013 DEFINEFENCE_915(3),
1014 DEFINEFENCE_915(4),
1015 DEFINEFENCE_915(5),
1016 DEFINEFENCE_915(6),
1017 DEFINEFENCE_915(7),
1018 DEFINEFENCE_945(8),
1019 DEFINEFENCE_945(9),
1020 DEFINEFENCE_945(10),
1021 DEFINEFENCE_945(11),
1022 DEFINEFENCE_945(12),
1023 DEFINEFENCE_945(13),
1024 DEFINEFENCE_945(14),
1025 DEFINEFENCE_945(15),
1026
1027 DEFINEREG(INST_PM),
1028 };
1029
1030 static const struct reg_debug i965_fences[] = {
1031 #define DEFINEFENCE_965(i) \
1032 { FENCE_NEW+i*8, "FENCE START " #i, i810_debug_965_fence_start }, \
1033 { FENCE_NEW+i*8+4, "FENCE END " #i, i810_debug_965_fence_end }
1034
1035 DEFINEFENCE_965(0),
1036 DEFINEFENCE_965(1),
1037 DEFINEFENCE_965(2),
1038 DEFINEFENCE_965(3),
1039 DEFINEFENCE_965(4),
1040 DEFINEFENCE_965(5),
1041 DEFINEFENCE_965(6),
1042 DEFINEFENCE_965(7),
1043 DEFINEFENCE_965(8),
1044 DEFINEFENCE_965(9),
1045 DEFINEFENCE_965(10),
1046 DEFINEFENCE_965(11),
1047 DEFINEFENCE_965(12),
1048 DEFINEFENCE_965(13),
1049 DEFINEFENCE_965(14),
1050 DEFINEFENCE_965(15),
1051 };
1052
DEBUGSTRING(ironlake_debug_rr_hw_ctl)1053 DEBUGSTRING(ironlake_debug_rr_hw_ctl)
1054 {
1055 return z_snprintf(result, len, "low %d, high %d", val & RR_HW_LOW_POWER_FRAMES_MASK,
1056 (val & RR_HW_HIGH_POWER_FRAMES_MASK) >> 8);
1057 }
1058
DEBUGSTRING(ironlake_debug_m_tu)1059 DEBUGSTRING(ironlake_debug_m_tu)
1060 {
1061 return z_snprintf(result, len, "TU %d, val 0x%x %d", (val >> 25) + 1, val & 0xffffff,
1062 val & 0xffffff);
1063 }
1064
DEBUGSTRING(ironlake_debug_n)1065 DEBUGSTRING(ironlake_debug_n)
1066 {
1067 return z_snprintf(result, len, "val 0x%x %d", val & 0xffffff, val & 0xffffff);
1068 }
1069
DEBUGSTRING(ironlake_debug_fdi_tx_ctl)1070 DEBUGSTRING(ironlake_debug_fdi_tx_ctl)
1071 {
1072 const char *train = NULL, *voltage = NULL, *pre_emphasis = NULL, *portw =
1073 NULL;
1074
1075 switch (val & FDI_LINK_TRAIN_NONE) {
1076 case FDI_LINK_TRAIN_PATTERN_1:
1077 train = "pattern_1";
1078 break;
1079 case FDI_LINK_TRAIN_PATTERN_2:
1080 train = "pattern_2";
1081 break;
1082 case FDI_LINK_TRAIN_PATTERN_IDLE:
1083 train = "pattern_idle";
1084 break;
1085 case FDI_LINK_TRAIN_NONE:
1086 train = "not train";
1087 break;
1088 }
1089
1090 if (HAS_CPT) {
1091 /* SNB B0 */
1092 switch (val & (0x3f << 22)) {
1093 case FDI_LINK_TRAIN_400MV_0DB_SNB_B:
1094 voltage = "0.4V";
1095 pre_emphasis = "0dB";
1096 break;
1097 case FDI_LINK_TRAIN_400MV_6DB_SNB_B:
1098 voltage = "0.4V";
1099 pre_emphasis = "6dB";
1100 break;
1101 case FDI_LINK_TRAIN_600MV_3_5DB_SNB_B:
1102 voltage = "0.6V";
1103 pre_emphasis = "3.5dB";
1104 break;
1105 case FDI_LINK_TRAIN_800MV_0DB_SNB_B:
1106 voltage = "0.8V";
1107 pre_emphasis = "0dB";
1108 break;
1109 }
1110
1111 } else {
1112
1113 switch (val & (7 << 25)) {
1114 case FDI_LINK_TRAIN_VOLTAGE_0_4V:
1115 voltage = "0.4V";
1116 break;
1117 case FDI_LINK_TRAIN_VOLTAGE_0_6V:
1118 voltage = "0.6V";
1119 break;
1120 case FDI_LINK_TRAIN_VOLTAGE_0_8V:
1121 voltage = "0.8V";
1122 break;
1123 case FDI_LINK_TRAIN_VOLTAGE_1_2V:
1124 voltage = "1.2V";
1125 break;
1126 default:
1127 voltage = "reserved";
1128 }
1129
1130 switch (val & (7 << 22)) {
1131 case FDI_LINK_TRAIN_PRE_EMPHASIS_NONE:
1132 pre_emphasis = "none";
1133 break;
1134 case FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X:
1135 pre_emphasis = "1.5x";
1136 break;
1137 case FDI_LINK_TRAIN_PRE_EMPHASIS_2X:
1138 pre_emphasis = "2x";
1139 break;
1140 case FDI_LINK_TRAIN_PRE_EMPHASIS_3X:
1141 pre_emphasis = "3x";
1142 break;
1143 default:
1144 pre_emphasis = "reserved";
1145 }
1146
1147 }
1148
1149 switch (val & (7 << 19)) {
1150 case FDI_DP_PORT_WIDTH_X1:
1151 portw = "X1";
1152 break;
1153 case FDI_DP_PORT_WIDTH_X2:
1154 portw = "X2";
1155 break;
1156 case FDI_DP_PORT_WIDTH_X3:
1157 portw = "X3";
1158 break;
1159 case FDI_DP_PORT_WIDTH_X4:
1160 portw = "X4";
1161 break;
1162 }
1163
1164 return z_snprintf(result, len, "%s, train pattern %s, voltage swing %s,"
1165 "pre-emphasis %s, port width %s, enhanced framing %s, FDI PLL %s, scrambing %s, master mode %s",
1166 val & FDI_TX_ENABLE ? "enable" : "disable",
1167 train, voltage, pre_emphasis, portw,
1168 val & FDI_TX_ENHANCE_FRAME_ENABLE ? "enable" :
1169 "disable",
1170 val & FDI_TX_PLL_ENABLE ? "enable" : "disable",
1171 val & (1 << 7) ? "disable" : "enable",
1172 val & (1 << 0) ? "enable" : "disable");
1173 }
1174
DEBUGSTRING(ironlake_debug_fdi_rx_ctl)1175 DEBUGSTRING(ironlake_debug_fdi_rx_ctl)
1176 {
1177 const char *train = NULL, *portw = NULL, *bpc = NULL;
1178
1179 if (HAS_CPT) {
1180 switch (val & FDI_LINK_TRAIN_PATTERN_MASK_CPT) {
1181 case FDI_LINK_TRAIN_PATTERN_1_CPT:
1182 train = "pattern_1";
1183 break;
1184 case FDI_LINK_TRAIN_PATTERN_2_CPT:
1185 train = "pattern_2";
1186 break;
1187 case FDI_LINK_TRAIN_PATTERN_IDLE_CPT:
1188 train = "pattern_idle";
1189 break;
1190 case FDI_LINK_TRAIN_NORMAL_CPT:
1191 train = "not train";
1192 break;
1193 }
1194 } else {
1195 switch (val & FDI_LINK_TRAIN_NONE) {
1196 case FDI_LINK_TRAIN_PATTERN_1:
1197 train = "pattern_1";
1198 break;
1199 case FDI_LINK_TRAIN_PATTERN_2:
1200 train = "pattern_2";
1201 break;
1202 case FDI_LINK_TRAIN_PATTERN_IDLE:
1203 train = "pattern_idle";
1204 break;
1205 case FDI_LINK_TRAIN_NONE:
1206 train = "not train";
1207 break;
1208 }
1209 }
1210
1211 switch (val & (7 << 19)) {
1212 case FDI_DP_PORT_WIDTH_X1:
1213 portw = "X1";
1214 break;
1215 case FDI_DP_PORT_WIDTH_X2:
1216 portw = "X2";
1217 break;
1218 case FDI_DP_PORT_WIDTH_X3:
1219 portw = "X3";
1220 break;
1221 case FDI_DP_PORT_WIDTH_X4:
1222 portw = "X4";
1223 break;
1224 }
1225
1226 switch (val & (7 << 16)) {
1227 case FDI_8BPC:
1228 bpc = "8bpc";
1229 break;
1230 case FDI_10BPC:
1231 bpc = "10bpc";
1232 break;
1233 case FDI_6BPC:
1234 bpc = "6bpc";
1235 break;
1236 case FDI_12BPC:
1237 bpc = "12bpc";
1238 break;
1239 }
1240
1241 return z_snprintf(result, len, "%s, train pattern %s, port width %s, %s,"
1242 "link_reverse_strap_overwrite %s, dmi_link_reverse %s, FDI PLL %s,"
1243 "FS ecc %s, FE ecc %s, FS err report %s, FE err report %s,"
1244 "scrambing %s, enhanced framing %s, %s",
1245 val & FDI_RX_ENABLE ? "enable" : "disable",
1246 train, portw, bpc,
1247 val & FDI_LINK_REVERSE_OVERWRITE ? "yes" : "no",
1248 val & FDI_DMI_LINK_REVERSE_MASK ? "yes" : "no",
1249 val & FDI_RX_PLL_ENABLE ? "enable" : "disable",
1250 val & FDI_FS_ERR_CORRECT_ENABLE ? "enable" : "disable",
1251 val & FDI_FE_ERR_CORRECT_ENABLE ? "enable" : "disable",
1252 val & FDI_FS_ERR_REPORT_ENABLE ? "enable" : "disable",
1253 val & FDI_FE_ERR_REPORT_ENABLE ? "enable" : "disable",
1254 val & (1 << 7) ? "disable" : "enable",
1255 val & FDI_RX_ENHANCE_FRAME_ENABLE ? "enable" :
1256 "disable", val & FDI_SEL_PCDCLK ? "PCDClk" : "RawClk");
1257 }
1258
DEBUGSTRING(ironlake_debug_dspstride)1259 DEBUGSTRING(ironlake_debug_dspstride)
1260 {
1261 return z_snprintf(result, len, "%d", val >> 6);
1262 }
1263
DEBUGSTRING(ironlake_debug_pch_dpll)1264 DEBUGSTRING(ironlake_debug_pch_dpll)
1265 {
1266 const char *enable = val & DPLL_VCO_ENABLE ? "enable" : "disable";
1267 const char *highspeed = val & DPLL_DVO_HIGH_SPEED ? "yes" : "no";
1268 const char *mode = NULL;
1269 const char *p2 = NULL;
1270 int fpa0_p1, fpa1_p1;
1271 const char *refclk = NULL;
1272 int sdvo_mul;
1273
1274 if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_LVDS) {
1275 mode = "LVDS";
1276 if (val & DPLLB_LVDS_P2_CLOCK_DIV_7)
1277 p2 = "Div 7";
1278 else
1279 p2 = "Div 14";
1280 } else if ((val & DPLLB_MODE_DAC_SERIAL) == DPLLB_MODE_DAC_SERIAL) {
1281 mode = "Non-LVDS";
1282 if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
1283 p2 = "Div 5";
1284 else
1285 p2 = "Div 10";
1286 }
1287 fpa0_p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >> 16);
1288 fpa1_p1 = ffs((val & DPLL_FPA1_P1_POST_DIV_MASK));
1289
1290 switch (val & PLL_REF_INPUT_MASK) {
1291 case PLL_REF_INPUT_DREFCLK:
1292 refclk = "default 120Mhz";
1293 break;
1294 case PLL_REF_INPUT_SUPER_SSC:
1295 refclk = "SuperSSC 120Mhz";
1296 break;
1297 case PLL_REF_INPUT_TVCLKINBC:
1298 refclk = "SDVO TVClkIn";
1299 break;
1300 case PLLB_REF_INPUT_SPREADSPECTRUMIN:
1301 refclk = "SSC";
1302 break;
1303 case PLL_REF_INPUT_DMICLK:
1304 refclk = "DMI RefCLK";
1305 break;
1306 }
1307
1308 sdvo_mul = ((val & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) >> 9) + 1;
1309
1310 return z_snprintf(result, len, "%s, sdvo high speed %s, mode %s, p2 %s, "
1311 "FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d",
1312 enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk,
1313 sdvo_mul);
1314 }
1315
DEBUGSTRING(ironlake_debug_dref_ctl)1316 DEBUGSTRING(ironlake_debug_dref_ctl)
1317 {
1318 const char *cpu_source;
1319 const char *ssc_source = val & DREF_SSC_SOURCE_ENABLE ? "enable" : "disable";
1320 const char *nonspread_source =
1321 val & DREF_NONSPREAD_SOURCE_ENABLE ? "enable" : "disable";
1322 const char *superspread_source =
1323 val & DREF_SUPERSPREAD_SOURCE_ENABLE ? "enable" : "disable";
1324 const char *ssc4_mode =
1325 val & DREF_SSC4_CENTERSPREAD ? "centerspread" : "downspread";
1326 const char *ssc1 = val & DREF_SSC1_ENABLE ? "enable" : "disable";
1327 const char *ssc4 = val & DREF_SSC4_ENABLE ? "enable" : "disable";
1328
1329 switch (val & DREF_CPU_SOURCE_OUTPUT_NONSPREAD) {
1330 case DREF_CPU_SOURCE_OUTPUT_DISABLE:
1331 cpu_source = "disable";
1332 break;
1333 case DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD:
1334 cpu_source = "downspread";
1335 break;
1336 case DREF_CPU_SOURCE_OUTPUT_NONSPREAD:
1337 cpu_source = "nonspread";
1338 break;
1339 default:
1340 cpu_source = "reserved";
1341 }
1342 return z_snprintf(result, len, "cpu source %s, ssc_source %s, nonspread_source %s, "
1343 "superspread_source %s, ssc4_mode %s, ssc1 %s, ssc4 %s",
1344 cpu_source, ssc_source, nonspread_source,
1345 superspread_source, ssc4_mode, ssc1, ssc4);
1346 }
1347
DEBUGSTRING(ironlake_debug_rawclk_freq)1348 DEBUGSTRING(ironlake_debug_rawclk_freq)
1349 {
1350 const char *tp1 = NULL, *tp2 = NULL;
1351
1352 switch (val & FDL_TP1_TIMER_MASK) {
1353 case 0:
1354 tp1 = "0.5us";
1355 break;
1356 case (1 << 12):
1357 tp1 = "1.0us";
1358 break;
1359 case (2 << 12):
1360 tp1 = "2.0us";
1361 break;
1362 case (3 << 12):
1363 tp1 = "4.0us";
1364 break;
1365 }
1366 switch (val & FDL_TP2_TIMER_MASK) {
1367 case 0:
1368 tp2 = "1.5us";
1369 break;
1370 case (1 << 10):
1371 tp2 = "3.0us";
1372 break;
1373 case (2 << 10):
1374 tp2 = "6.0us";
1375 break;
1376 case (3 << 10):
1377 tp2 = "12.0us";
1378 break;
1379 }
1380 return z_snprintf(result, len, "FDL_TP1 timer %s, FDL_TP2 timer %s, freq %d",
1381 tp1, tp2, val & RAWCLK_FREQ_MASK);
1382
1383 }
1384
DEBUGSTRING(ironlake_debug_fdi_rx_misc)1385 DEBUGSTRING(ironlake_debug_fdi_rx_misc)
1386 {
1387 return z_snprintf(result, len, "FDI Delay %d", val & ((1 << 13) - 1));
1388 }
1389
DEBUGSTRING(ironlake_debug_transconf)1390 DEBUGSTRING(ironlake_debug_transconf)
1391 {
1392 const char *enable = val & TRANS_ENABLE ? "enable" : "disable";
1393 const char *state = val & TRANS_STATE_ENABLE ? "active" : "inactive";
1394 const char *interlace;
1395
1396 switch ((val >> 21) & 7) {
1397 case 0:
1398 interlace = "progressive";
1399 break;
1400 case 2:
1401 if (IS_GEN5(devid))
1402 interlace = "interlaced sdvo";
1403 else
1404 interlace = "rsvd";
1405 break;
1406 case 3:
1407 interlace = "interlaced";
1408 break;
1409 default:
1410 interlace = "rsvd";
1411 }
1412
1413 return z_snprintf(result, len, "%s, %s, %s", enable, state, interlace);
1414 }
1415
DEBUGSTRING(ironlake_debug_panel_fitting)1416 DEBUGSTRING(ironlake_debug_panel_fitting)
1417 {
1418 const char *vadapt = NULL, *filter_sel = NULL;
1419
1420 switch (val & (3 << 25)) {
1421 case 0:
1422 vadapt = "least";
1423 break;
1424 case (1 << 25):
1425 vadapt = "moderate";
1426 break;
1427 case (2 << 25):
1428 vadapt = "reserved";
1429 break;
1430 case (3 << 25):
1431 vadapt = "most";
1432 break;
1433 }
1434
1435 switch (val & (3 << 23)) {
1436 case 0:
1437 filter_sel = "programmed";
1438 break;
1439 case (1 << 23):
1440 filter_sel = "hardcoded";
1441 break;
1442 case (2 << 23):
1443 filter_sel = "edge_enhance";
1444 break;
1445 case (3 << 23):
1446 filter_sel = "edge_soften";
1447 break;
1448 }
1449
1450 return z_snprintf(result, len,
1451 "%s, auto_scale %s, auto_scale_cal %s, v_filter %s, vadapt %s, mode %s, filter_sel %s,"
1452 "chroma pre-filter %s, vert3tap %s, v_inter_invert %s",
1453 val & PF_ENABLE ? "enable" : "disable",
1454 val & (1 << 30) ? "no" : "yes",
1455 val & (1 << 29) ? "yes" : "no",
1456 val & (1 << 28) ? "bypass" : "enable",
1457 val & (1 << 27) ? "enable" : "disable",
1458 vadapt,
1459 filter_sel,
1460 val & (1 << 22) ? "enable" : "disable",
1461 val & (1 << 21) ? "force" : "auto",
1462 val & (1 << 20) ? "field 0" : "field 1");
1463 }
1464
DEBUGSTRING(ironlake_debug_panel_fitting_2)1465 DEBUGSTRING(ironlake_debug_panel_fitting_2)
1466 {
1467 return z_snprintf(result, len,
1468 "vscale %f",
1469 val / (float) (1<<15));
1470 }
1471
DEBUGSTRING(ironlake_debug_panel_fitting_3)1472 DEBUGSTRING(ironlake_debug_panel_fitting_3)
1473 {
1474 return z_snprintf(result, len,
1475 "vscale initial phase %f",
1476 val / (float) (1<<15));
1477 }
1478
DEBUGSTRING(ironlake_debug_panel_fitting_4)1479 DEBUGSTRING(ironlake_debug_panel_fitting_4)
1480 {
1481 return z_snprintf(result, len,
1482 "hscale %f",
1483 val / (float) (1<<15));
1484 }
1485
DEBUGSTRING(ironlake_debug_pf_win)1486 DEBUGSTRING(ironlake_debug_pf_win)
1487 {
1488 int a, b;
1489
1490 a = (val >> 16) & 0x1fff;
1491 b = val & 0xfff;
1492
1493 return z_snprintf(result, len, "%d, %d", a, b);
1494 }
1495
DEBUGSTRING(ironlake_debug_hdmi)1496 DEBUGSTRING(ironlake_debug_hdmi)
1497 {
1498 int disp_pipe;
1499 const char *enable, *bpc = NULL, *encoding;
1500 const char *mode, *audio, *vsync, *hsync, *detect;
1501
1502 if (val & PORT_ENABLE)
1503 enable = "enabled";
1504 else
1505 enable = "disabled";
1506
1507 if (HAS_CPT)
1508 disp_pipe = (val & (3<<29)) >> 29;
1509 else
1510 disp_pipe = (val & TRANSCODER_B) >> 29;
1511
1512 switch (val & (7 << 26)) {
1513 case COLOR_FORMAT_8bpc:
1514 bpc = "8bpc";
1515 break;
1516 case COLOR_FORMAT_12bpc:
1517 bpc = "12bpc";
1518 break;
1519 }
1520
1521 if ((val & (3 << 10)) == TMDS_ENCODING)
1522 encoding = "TMDS";
1523 else
1524 encoding = "SDVO";
1525
1526 if (val & (1 << 9))
1527 mode = "HDMI";
1528 else
1529 mode = "DVI";
1530
1531 if (val & AUDIO_ENABLE)
1532 audio = "enabled";
1533 else
1534 audio = "disabled";
1535
1536 if (val & VSYNC_ACTIVE_HIGH)
1537 vsync = "+vsync";
1538 else
1539 vsync = "-vsync";
1540
1541 if (val & HSYNC_ACTIVE_HIGH)
1542 hsync = "+hsync";
1543 else
1544 hsync = "-hsync";
1545
1546 if (val & PORT_DETECTED)
1547 detect = "detected";
1548 else
1549 detect = "non-detected";
1550
1551 return z_snprintf(result, len, "%s pipe %c %s %s %s audio %s %s %s %s",
1552 enable, disp_pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect);
1553 }
1554
DEBUGSTRING(ironlake_debug_dp_buftrans)1555 DEBUGSTRING(ironlake_debug_dp_buftrans)
1556 {
1557 static const char * const reg_names[] = {
1558 "400mV, 0.0dB",
1559 "400mV, 3.5dB",
1560 "400mV, 6.0dB",
1561 "400mV, 9.5dB",
1562 "600mV, 0.0dB",
1563 "600mV, 3.5dB",
1564 "600mV, 6.0dB",
1565 "800mV, 0.0dB",
1566 "800mV, 3.5dB",
1567 "1200mV, 0.0dB",
1568 };
1569 int idx = (reg - DP_BUFTRANS(0)) / 4;
1570
1571 return z_snprintf(result, len, "%s: OE=%3d, pre-emphasis=%2d, P current drive=%2d, N current drive=%2d",
1572 reg_names[idx], (val >> 19) & 0x1ff, (val >> 12) & 0x1f, (val >> 6) & 0xf, val & 0xf);
1573 }
1574
DEBUGSTRING(snb_debug_dpll_sel)1575 DEBUGSTRING(snb_debug_dpll_sel)
1576 {
1577 const char *transa, *transb;
1578 const char *dplla = NULL, *dpllb = NULL;
1579
1580 if (!HAS_CPT)
1581 return 0;
1582
1583 if (val & TRANSA_DPLL_ENABLE) {
1584 transa = "enable";
1585 if (val & TRANSA_DPLLB_SEL)
1586 dplla = "B";
1587 else
1588 dplla = "A";
1589 } else
1590 transa = "disable";
1591
1592 if (val & TRANSB_DPLL_ENABLE) {
1593 transb = "enable";
1594 if (val & TRANSB_DPLLB_SEL)
1595 dpllb = "B";
1596 else
1597 dpllb = "A";
1598 } else
1599 transb = "disable";
1600
1601 return z_snprintf(result, len, "TransA DPLL %s (DPLL %s), TransB DPLL %s (DPLL %s)",
1602 transa, dplla, transb, dpllb);
1603 }
1604
DEBUGSTRING(snb_debug_trans_dp_ctl)1605 DEBUGSTRING(snb_debug_trans_dp_ctl)
1606 {
1607 const char *enable, *port = NULL, *bpc = NULL, *vsync, *hsync;
1608
1609 if (!HAS_CPT)
1610 return 0;
1611
1612 if (val & TRANS_DP_OUTPUT_ENABLE)
1613 enable = "enable";
1614 else
1615 enable = "disable";
1616
1617 switch (val & TRANS_DP_PORT_SEL_MASK) {
1618 case TRANS_DP_PORT_SEL_B:
1619 port = "B";
1620 break;
1621 case TRANS_DP_PORT_SEL_C:
1622 port = "C";
1623 break;
1624 case TRANS_DP_PORT_SEL_D:
1625 port = "D";
1626 break;
1627 default:
1628 port = "none";
1629 break;
1630 }
1631
1632 switch (val & (7<<9)) {
1633 case TRANS_DP_8BPC:
1634 bpc = "8bpc";
1635 break;
1636 case TRANS_DP_10BPC:
1637 bpc = "10bpc";
1638 break;
1639 case TRANS_DP_6BPC:
1640 bpc = "6bpc";
1641 break;
1642 case TRANS_DP_12BPC:
1643 bpc = "12bpc";
1644 break;
1645 }
1646
1647 if (val & TRANS_DP_VSYNC_ACTIVE_HIGH)
1648 vsync = "+vsync";
1649 else
1650 vsync = "-vsync";
1651
1652 if (val & TRANS_DP_HSYNC_ACTIVE_HIGH)
1653 hsync = "+hsync";
1654 else
1655 hsync = "-hsync";
1656
1657 return z_snprintf(result, len, "%s port %s %s %s %s",
1658 enable, port, bpc, vsync, hsync);
1659 }
1660
DEBUGSTRING(ilk_debug_pp_control)1661 DEBUGSTRING(ilk_debug_pp_control)
1662 {
1663 return z_snprintf(result, len, "blacklight %s, %spower down on reset, panel %s",
1664 (val & (1 << 2)) ? "enabled" : "disabled",
1665 (val & (1 << 1)) ? "" : "do not ",
1666 (val & (1 << 0)) ? "on" : "off");
1667 }
1668
DEBUGSTRING(hsw_debug_port_clk_sel)1669 DEBUGSTRING(hsw_debug_port_clk_sel)
1670 {
1671 const char *clock = NULL;
1672
1673 switch ((val >> 29 ) & 7) {
1674 case 0:
1675 clock = "LCPLL 2700";
1676 break;
1677 case 1:
1678 clock = "LCPLL 1350";
1679 break;
1680 case 2:
1681 clock = "LCPLL 810";
1682 break;
1683 case 3:
1684 clock = "SPLL";
1685 break;
1686 case 4:
1687 clock = "WRPLL 1";
1688 break;
1689 case 5:
1690 clock = "WRPLL 2";
1691 break;
1692 case 6:
1693 clock = "Reserved";
1694 break;
1695 case 7:
1696 clock = "None";
1697 break;
1698 }
1699
1700 return z_snprintf(result, len, "%s", clock);
1701 }
1702
DEBUGSTRING(hsw_debug_pipe_clk_sel)1703 DEBUGSTRING(hsw_debug_pipe_clk_sel)
1704 {
1705 const char *clock;
1706
1707 switch ((val >> 29) & 7) {
1708 case 0:
1709 clock = "None";
1710 break;
1711 case 2:
1712 clock = "DDIB";
1713 break;
1714 case 3:
1715 clock = "DDIC";
1716 break;
1717 case 4:
1718 clock = "DDID";
1719 break;
1720 case 5:
1721 clock = "DDIE";
1722 break;
1723 default:
1724 clock = "Reserved";
1725 break;
1726 }
1727
1728 return z_snprintf(result, len, "%s", clock);
1729 }
1730
DEBUGSTRING(hsw_debug_ddi_buf_ctl)1731 DEBUGSTRING(hsw_debug_ddi_buf_ctl)
1732 {
1733 const char *enable, *reversal, *width, *detected;
1734
1735 enable = (val & (1<<31)) ? "enabled" : "disabled";
1736 reversal = (val & (1<<16)) ? "reversed" : "not reversed";
1737
1738 switch ((val >> 1) & 7) {
1739 case 0:
1740 width = "x1";
1741 break;
1742 case 1:
1743 width = "x2";
1744 break;
1745 case 3:
1746 width = "x4";
1747 break;
1748 default:
1749 width = "reserved";
1750 break;
1751 }
1752
1753 detected = (val & 1) ? "detected" : "not detected";
1754
1755 return z_snprintf(result, len, "%s %s %s %s", enable, reversal, width, detected);
1756 }
1757
DEBUGSTRING(hsw_debug_sfuse_strap)1758 DEBUGSTRING(hsw_debug_sfuse_strap)
1759 {
1760 const char *display, *crt, *lane_reversal, *portb, *portc, *portd;
1761
1762 display = (val & (1<<7)) ? "disabled" : "enabled";
1763 crt = (val & (1<<6)) ? "yes" : "no";
1764 lane_reversal = (val & (1<<4)) ? "yes" : "no";
1765 portb = (val & (1<<2)) ? "yes" : "no";
1766 portc = (val & (1<<1)) ? "yes" : "no";
1767 portd = (val & (1<<0)) ? "yes" : "no";
1768
1769 return z_snprintf(result, len, "display %s, crt %s, lane reversal %s, "
1770 "port b %s, port c %s, port d %s", display, crt, lane_reversal,
1771 portb, portc, portd);
1772 }
1773
DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)1774 DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
1775 {
1776 const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input;
1777 const char *width;
1778
1779 enable = (val & (1<<31)) ? "enabled" : "disabled";
1780
1781 switch ((val >> 28) & 7) {
1782 case 0:
1783 port = "no port";
1784 break;
1785 case 1:
1786 port = "DDIB";
1787 break;
1788 case 2:
1789 port = "DDIC";
1790 break;
1791 case 3:
1792 port = "DDID";
1793 break;
1794 case 4:
1795 port = "DDIE";
1796 break;
1797 default:
1798 port = "port reserved";
1799 break;
1800 }
1801
1802 switch ((val >> 24) & 7) {
1803 case 0:
1804 mode = "HDMI";
1805 break;
1806 case 1:
1807 mode = "DVI";
1808 break;
1809 case 2:
1810 mode = "DP SST";
1811 break;
1812 case 3:
1813 mode = "DP MST";
1814 break;
1815 case 4:
1816 mode = "FDI";
1817 break;
1818 case 5:
1819 default:
1820 mode = "mode reserved";
1821 break;
1822 }
1823
1824 switch ((val >> 20) & 7) {
1825 case 0:
1826 bpc = "8 bpc";
1827 break;
1828 case 1:
1829 bpc = "10 bpc";
1830 break;
1831 case 2:
1832 bpc = "6 bpc";
1833 break;
1834 case 3:
1835 bpc = "12 bpc";
1836 break;
1837 default:
1838 bpc = "bpc reserved";
1839 break;
1840 }
1841
1842 hsync = (val & (1<<16)) ? "+HSync" : "-HSync";
1843 vsync = (val & (1<<17)) ? "+VSync" : "-VSync";
1844
1845 switch ((val >> 12) & 7) {
1846 case 0:
1847 edp_input = "EDP A ON";
1848 break;
1849 case 4:
1850 edp_input = "EDP A ONOFF";
1851 break;
1852 case 5:
1853 edp_input = "EDP B ONOFF";
1854 break;
1855 case 6:
1856 edp_input = "EDP C ONOFF";
1857 break;
1858 default:
1859 edp_input = "EDP input reserved";
1860 break;
1861 }
1862
1863 switch ((val >> 1) & 7) {
1864 case 0:
1865 width = "x1";
1866 break;
1867 case 1:
1868 width = "x2";
1869 break;
1870 case 3:
1871 width = "x4";
1872 break;
1873 default:
1874 width = "reserved width";
1875 break;
1876 }
1877
1878 return z_snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable,
1879 port, mode, bpc, vsync, hsync, edp_input, width);
1880 }
1881
DEBUGSTRING(hsw_debug_wm_pipe)1882 DEBUGSTRING(hsw_debug_wm_pipe)
1883 {
1884 uint32_t primary, sprite, cursor;
1885
1886 primary = (val >> 16) & 0x7F;
1887 sprite = (val >> 8) & 0x7F;
1888 cursor = val & 0x3F;
1889
1890 return z_snprintf(result, len, "primary %d, sprite %d, pipe %d", primary,
1891 sprite, cursor);
1892 }
1893
DEBUGSTRING(hsw_debug_lp_wm)1894 DEBUGSTRING(hsw_debug_lp_wm)
1895 {
1896 const char *enable;
1897 uint32_t latency, fbc, pri, cur;
1898
1899 enable = ((val >> 31) & 1) ? "enabled" : "disabled";
1900 latency = (val >> 24) & 0x7F;
1901 fbc = (val >> 20) & 0xF;
1902 pri = (val >> 8) & 0x3FF;
1903 cur = val & 0xFF;
1904
1905 return z_snprintf(result, len, "%s, latency %d, fbc %d, pri %d, cur %d",
1906 enable, latency, fbc, pri, cur);
1907 }
1908
DEBUGSTRING(hsw_debug_sinterrupt)1909 DEBUGSTRING(hsw_debug_sinterrupt)
1910 {
1911 int portd, portc, portb, crt;
1912
1913 portd = (val >> 23) & 1;
1914 portc = (val >> 22) & 1;
1915 portb = (val >> 21) & 1;
1916 crt = (val >> 19) & 1;
1917
1918 return z_snprintf(result, len, "port d:%d, port c:%d, port b:%d, crt:%d",
1919 portd, portc, portb, crt);
1920 }
1921
DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2)1922 DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl2)
1923 {
1924 int enable, blinking, granularity;
1925 const char *pipe;
1926
1927 enable = (val >> 31) & 1;
1928
1929 if (IS_GEN5(devid) || IS_GEN6(devid)) {
1930 pipe = ((val >> 29) & 1) ? "B" : "A";
1931 } else {
1932 switch ((val >> 29) & 3) {
1933 case 0:
1934 pipe = "A";
1935 break;
1936 case 1:
1937 pipe = "B";
1938 break;
1939 case 2:
1940 pipe = "C";
1941 break;
1942 case 3:
1943 if (IS_IVYBRIDGE(devid))
1944 pipe = "reserved";
1945 else
1946 pipe = "EDP";
1947 break;
1948 }
1949 }
1950
1951 if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) {
1952 return z_snprintf(result, len, "enable %d, pipe %s", enable, pipe);
1953 } else {
1954 blinking = (val >> 28) & 1;
1955 granularity = ((val >> 27) & 1) ? 8 : 128;
1956
1957 return z_snprintf(result, len, "enable %d, pipe %s, blinking %d, "
1958 "granularity %d", enable, pipe, blinking,
1959 granularity);
1960 }
1961 }
1962
DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl)1963 DEBUGSTRING(ilk_debug_blc_pwm_cpu_ctl)
1964 {
1965 int cycle, freq;
1966
1967 cycle = (val & 0xFFFF);
1968
1969 if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) {
1970 return z_snprintf(result, len, "cycle %d", cycle);
1971 } else {
1972 freq = (val >> 16) & 0xFFFF;
1973
1974 return z_snprintf(result, len, "cycle %d, freq %d", cycle, freq);
1975 }
1976 }
1977
DEBUGSTRING(ibx_debug_blc_pwm_ctl1)1978 DEBUGSTRING(ibx_debug_blc_pwm_ctl1)
1979 {
1980 int enable, override, inverted_polarity;
1981
1982 enable = (val >> 31) & 1;
1983 override = (val >> 30) & 1;
1984 inverted_polarity = (val >> 29) & 1;
1985
1986 return z_snprintf(result, len, "enable %d, override %d, inverted polarity %d",
1987 enable, override, inverted_polarity);
1988 }
1989
DEBUGSTRING(ibx_debug_blc_pwm_ctl2)1990 DEBUGSTRING(ibx_debug_blc_pwm_ctl2)
1991 {
1992 int freq, cycle;
1993
1994 freq = (val >> 16) & 0xFFFF;
1995 cycle = val & 0xFFFF;
1996
1997 return z_snprintf(result, len, "freq %d, cycle %d", freq, cycle);
1998 }
1999
DEBUGSTRING(hsw_debug_blc_misc_ctl)2000 DEBUGSTRING(hsw_debug_blc_misc_ctl)
2001 {
2002 const char *sel;
2003
2004 sel = (val & 1) ? "PWM1-CPU PWM2-PCH" : "PWM1-PCH PWM2-CPU";
2005
2006 return z_snprintf(result, len, "%s", sel);
2007 }
2008
DEBUGSTRING(hsw_debug_util_pin_ctl)2009 DEBUGSTRING(hsw_debug_util_pin_ctl)
2010 {
2011 int enable, data, inverted_polarity;
2012 const char *transcoder, *mode;
2013
2014 enable = (val >> 31) & 1;
2015
2016 switch ((val >> 29) & 3) {
2017 case 0:
2018 transcoder = "A";
2019 break;
2020 case 1:
2021 transcoder = "B";
2022 break;
2023 case 2:
2024 transcoder = "C";
2025 break;
2026 case 3:
2027 transcoder = "EDP";
2028 break;
2029 }
2030
2031 switch ((val >> 24) & 0xF) {
2032 case 0:
2033 mode = "data";
2034 break;
2035 case 1:
2036 mode = "PWM";
2037 break;
2038 case 4:
2039 mode = "Vblank";
2040 break;
2041 case 5:
2042 mode = "Vsync";
2043 break;
2044 default:
2045 mode = "reserved";
2046 break;
2047 }
2048
2049 data = (val >> 23) & 1;
2050 inverted_polarity = (val >> 22) & 1;
2051
2052 return z_snprintf(result, len, "enable %d, transcoder %s, mode %s, data %d "
2053 "inverted polarity %d", enable, transcoder, mode, data,
2054 inverted_polarity);
2055 }
2056
2057 static const struct reg_debug gen6_fences[] = {
2058 #define DEFINEFENCE_SNB(i) \
2059 { FENCE_REG_SANDYBRIDGE_0 + (i) * 8, "FENCE START "#i, NULL }, \
2060 { FENCE_REG_SANDYBRIDGE_0 + (i) * 8 + 4, "FENCE END "#i, NULL }
2061 DEFINEFENCE_SNB(0),
2062 DEFINEFENCE_SNB(1),
2063 DEFINEFENCE_SNB(2),
2064 DEFINEFENCE_SNB(3),
2065 DEFINEFENCE_SNB(4),
2066 DEFINEFENCE_SNB(5),
2067 DEFINEFENCE_SNB(6),
2068 DEFINEFENCE_SNB(7),
2069 DEFINEFENCE_SNB(8),
2070 DEFINEFENCE_SNB(9),
2071 DEFINEFENCE_SNB(10),
2072 DEFINEFENCE_SNB(11),
2073 DEFINEFENCE_SNB(12),
2074 DEFINEFENCE_SNB(13),
2075 DEFINEFENCE_SNB(14),
2076 DEFINEFENCE_SNB(15),
2077 DEFINEFENCE_SNB(16),
2078 DEFINEFENCE_SNB(17),
2079 DEFINEFENCE_SNB(18),
2080 DEFINEFENCE_SNB(19),
2081 DEFINEFENCE_SNB(20),
2082 DEFINEFENCE_SNB(20),
2083 DEFINEFENCE_SNB(21),
2084 DEFINEFENCE_SNB(22),
2085 DEFINEFENCE_SNB(23),
2086 DEFINEFENCE_SNB(24),
2087 DEFINEFENCE_SNB(25),
2088 DEFINEFENCE_SNB(26),
2089 DEFINEFENCE_SNB(27),
2090 DEFINEFENCE_SNB(28),
2091 DEFINEFENCE_SNB(29),
2092 DEFINEFENCE_SNB(30),
2093 DEFINEFENCE_SNB(31),
2094 };
2095
2096 static const struct reg_debug ironlake_debug_regs[] = {
2097 DEFINEREG(PGETBL_CTL),
2098 DEFINEREG(INSTDONE_I965),
2099 DEFINEREG(INSTDONE_1),
2100 DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
2101 DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL),
2102
2103 DEFINEREG2(RR_HW_CTL, ironlake_debug_rr_hw_ctl),
2104
2105 DEFINEREG(FDI_PLL_BIOS_0),
2106 DEFINEREG(FDI_PLL_BIOS_1),
2107 DEFINEREG(FDI_PLL_BIOS_2),
2108
2109 DEFINEREG(DISPLAY_PORT_PLL_BIOS_0),
2110 DEFINEREG(DISPLAY_PORT_PLL_BIOS_1),
2111 DEFINEREG(DISPLAY_PORT_PLL_BIOS_2),
2112
2113 DEFINEREG(FDI_PLL_FREQ_CTL),
2114
2115 /* pipe B */
2116
2117 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2118
2119 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2120 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2121 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2122 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2123 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2124 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2125 DEFINEREG(VSYNCSHIFT_A),
2126 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2127
2128 DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2129 DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2130 DEFINEREG2(PIPEA_DATA_M2, ironlake_debug_m_tu),
2131 DEFINEREG2(PIPEA_DATA_N2, ironlake_debug_n),
2132
2133 DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2134 DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2135 DEFINEREG2(PIPEA_LINK_M2, ironlake_debug_n),
2136 DEFINEREG2(PIPEA_LINK_N2, ironlake_debug_n),
2137
2138 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2139 DEFINEREG(DSPABASE),
2140 DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2141 DEFINEREG(DSPASURF),
2142 DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2143
2144 /* pipe B */
2145
2146 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2147
2148 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2149 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2150 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2151 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2152 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2153 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2154 DEFINEREG(VSYNCSHIFT_B),
2155 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2156
2157 DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2158 DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2159 DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
2160 DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
2161
2162 DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2163 DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2164 DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
2165 DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
2166
2167 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2168 DEFINEREG(DSPBBASE),
2169 DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2170 DEFINEREG(DSPBSURF),
2171 DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2172
2173 /* pipe C */
2174
2175 DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2176
2177 DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2178 DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2179 DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2180 DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2181 DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2182 DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2183 DEFINEREG(VSYNCSHIFT_C),
2184 DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2185
2186 DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2187 DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2188 DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
2189 DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
2190
2191 DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2192 DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2193 DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
2194 DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
2195
2196 DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2197 DEFINEREG(DSPCBASE),
2198 DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2199 DEFINEREG(DSPCSURF),
2200 DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2201
2202 /* Panel fitter */
2203
2204 DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2205 DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
2206 DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
2207 DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4),
2208 DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2209 DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2210 DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2211 DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2),
2212 DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3),
2213 DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4),
2214 DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2215 DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2216 DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2217 DEFINEREG2(PFC_CTL_2, ironlake_debug_panel_fitting_2),
2218 DEFINEREG2(PFC_CTL_3, ironlake_debug_panel_fitting_3),
2219 DEFINEREG2(PFC_CTL_4, ironlake_debug_panel_fitting_4),
2220 DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2221 DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2222
2223 /* PCH */
2224
2225 DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
2226 DEFINEREG2(PCH_RAWCLK_FREQ, ironlake_debug_rawclk_freq),
2227 DEFINEREG(PCH_DPLL_TMR_CFG),
2228 DEFINEREG(PCH_SSC4_PARMS),
2229 DEFINEREG(PCH_SSC4_AUX_PARMS),
2230 DEFINEREG2(PCH_DPLL_SEL, snb_debug_dpll_sel),
2231 DEFINEREG(PCH_DPLL_ANALOG_CTL),
2232
2233 DEFINEREG2(PCH_DPLL_A, ironlake_debug_pch_dpll),
2234 DEFINEREG2(PCH_DPLL_B, ironlake_debug_pch_dpll),
2235 DEFINEREG2(PCH_FPA0, i830_debug_fp),
2236 DEFINEREG2(PCH_FPA1, i830_debug_fp),
2237 DEFINEREG2(PCH_FPB0, i830_debug_fp),
2238 DEFINEREG2(PCH_FPB1, i830_debug_fp),
2239
2240 DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2241 DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2242 DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2243 DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2244 DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2245 DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2246 DEFINEREG(TRANS_VSYNCSHIFT_A),
2247
2248 DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
2249 DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
2250 DEFINEREG2(TRANSA_DATA_M2, ironlake_debug_m_tu),
2251 DEFINEREG2(TRANSA_DATA_N2, ironlake_debug_n),
2252 DEFINEREG2(TRANSA_DP_LINK_M1, ironlake_debug_n),
2253 DEFINEREG2(TRANSA_DP_LINK_N1, ironlake_debug_n),
2254 DEFINEREG2(TRANSA_DP_LINK_M2, ironlake_debug_n),
2255 DEFINEREG2(TRANSA_DP_LINK_N2, ironlake_debug_n),
2256
2257 DEFINEREG2(TRANS_HTOTAL_B, i830_debug_hvtotal),
2258 DEFINEREG2(TRANS_HBLANK_B, i830_debug_hvsyncblank),
2259 DEFINEREG2(TRANS_HSYNC_B, i830_debug_hvsyncblank),
2260 DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
2261 DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
2262 DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
2263 DEFINEREG(TRANS_VSYNCSHIFT_B),
2264
2265 DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
2266 DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
2267 DEFINEREG2(TRANSB_DATA_M2, ironlake_debug_m_tu),
2268 DEFINEREG2(TRANSB_DATA_N2, ironlake_debug_n),
2269 DEFINEREG2(TRANSB_DP_LINK_M1, ironlake_debug_n),
2270 DEFINEREG2(TRANSB_DP_LINK_N1, ironlake_debug_n),
2271 DEFINEREG2(TRANSB_DP_LINK_M2, ironlake_debug_n),
2272 DEFINEREG2(TRANSB_DP_LINK_N2, ironlake_debug_n),
2273
2274 DEFINEREG2(TRANS_HTOTAL_C, i830_debug_hvtotal),
2275 DEFINEREG2(TRANS_HBLANK_C, i830_debug_hvsyncblank),
2276 DEFINEREG2(TRANS_HSYNC_C, i830_debug_hvsyncblank),
2277 DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
2278 DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
2279 DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
2280 DEFINEREG(TRANS_VSYNCSHIFT_C),
2281
2282 DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
2283 DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),
2284 DEFINEREG2(TRANSC_DATA_M2, ironlake_debug_m_tu),
2285 DEFINEREG2(TRANSC_DATA_N2, ironlake_debug_n),
2286 DEFINEREG2(TRANSC_DP_LINK_M1, ironlake_debug_n),
2287 DEFINEREG2(TRANSC_DP_LINK_N1, ironlake_debug_n),
2288 DEFINEREG2(TRANSC_DP_LINK_M2, ironlake_debug_n),
2289 DEFINEREG2(TRANSC_DP_LINK_N2, ironlake_debug_n),
2290
2291 DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2292 DEFINEREG2(TRANSBCONF, ironlake_debug_transconf),
2293 DEFINEREG2(TRANSCCONF, ironlake_debug_transconf),
2294
2295 DEFINEREG2(FDI_TXA_CTL, ironlake_debug_fdi_tx_ctl),
2296 DEFINEREG2(FDI_TXB_CTL, ironlake_debug_fdi_tx_ctl),
2297 DEFINEREG2(FDI_TXC_CTL, ironlake_debug_fdi_tx_ctl),
2298 DEFINEREG2(FDI_RXA_CTL, ironlake_debug_fdi_rx_ctl),
2299 DEFINEREG2(FDI_RXB_CTL, ironlake_debug_fdi_rx_ctl),
2300 DEFINEREG2(FDI_RXC_CTL, ironlake_debug_fdi_rx_ctl),
2301
2302 DEFINEREG(DPAFE_BMFUNC),
2303 DEFINEREG(DPAFE_DL_IREFCAL0),
2304 DEFINEREG(DPAFE_DL_IREFCAL1),
2305 DEFINEREG(DPAFE_DP_IREFCAL),
2306
2307 DEFINEREG(PCH_DSPCLK_GATE_D),
2308 DEFINEREG(PCH_DSP_CHICKEN1),
2309 DEFINEREG(PCH_DSP_CHICKEN2),
2310 DEFINEREG(PCH_DSP_CHICKEN3),
2311
2312 DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2313 DEFINEREG2(FDI_RXB_MISC, ironlake_debug_fdi_rx_misc),
2314 DEFINEREG2(FDI_RXC_MISC, ironlake_debug_fdi_rx_misc),
2315 DEFINEREG(FDI_RXA_TUSIZE1),
2316 DEFINEREG(FDI_RXA_TUSIZE2),
2317 DEFINEREG(FDI_RXB_TUSIZE1),
2318 DEFINEREG(FDI_RXB_TUSIZE2),
2319 DEFINEREG(FDI_RXC_TUSIZE1),
2320 DEFINEREG(FDI_RXC_TUSIZE2),
2321
2322 DEFINEREG(FDI_PLL_CTL_1),
2323 DEFINEREG(FDI_PLL_CTL_2),
2324
2325 DEFINEREG(FDI_RXA_IIR),
2326 DEFINEREG(FDI_RXA_IMR),
2327 DEFINEREG(FDI_RXB_IIR),
2328 DEFINEREG(FDI_RXB_IMR),
2329
2330 DEFINEREG2(PCH_ADPA, i830_debug_adpa),
2331 DEFINEREG2(HDMIB, ironlake_debug_hdmi),
2332 DEFINEREG2(HDMIC, ironlake_debug_hdmi),
2333 DEFINEREG2(HDMID, ironlake_debug_hdmi),
2334 DEFINEREG2(PCH_LVDS, i830_debug_lvds),
2335 DEFINEREG(CPU_eDP_A),
2336 DEFINEREG(PCH_DP_B),
2337 DEFINEREG(PCH_DP_C),
2338 DEFINEREG(PCH_DP_D),
2339
2340 DEFINEREG2(DP_BUFTRANS(0), ironlake_debug_dp_buftrans),
2341 DEFINEREG2(DP_BUFTRANS(1), ironlake_debug_dp_buftrans),
2342 DEFINEREG2(DP_BUFTRANS(2), ironlake_debug_dp_buftrans),
2343 DEFINEREG2(DP_BUFTRANS(3), ironlake_debug_dp_buftrans),
2344 DEFINEREG2(DP_BUFTRANS(4), ironlake_debug_dp_buftrans),
2345 DEFINEREG2(DP_BUFTRANS(5), ironlake_debug_dp_buftrans),
2346 DEFINEREG2(DP_BUFTRANS(6), ironlake_debug_dp_buftrans),
2347 DEFINEREG2(DP_BUFTRANS(7), ironlake_debug_dp_buftrans),
2348 DEFINEREG2(DP_BUFTRANS(8), ironlake_debug_dp_buftrans),
2349 DEFINEREG2(DP_BUFTRANS(9), ironlake_debug_dp_buftrans),
2350
2351 DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl),
2352 DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl),
2353 DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl),
2354
2355 DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2356 DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2357 DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2358 DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2359
2360 DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2361 DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2362 DEFINEREG(PCH_PP_ON_DELAYS),
2363 DEFINEREG(PCH_PP_OFF_DELAYS),
2364 DEFINEREG(PCH_PP_DIVISOR),
2365
2366 DEFINEREG2(PORT_DBG, ivb_debug_port),
2367
2368 DEFINEREG(RC6_RESIDENCY_TIME),
2369 DEFINEREG(RC6p_RESIDENCY_TIME),
2370 DEFINEREG(RC6pp_RESIDENCY_TIME),
2371 };
2372
2373 static const struct reg_debug haswell_debug_regs[] = {
2374 /* Power wells */
2375 DEFINEREG(HSW_PWR_WELL_CTL1),
2376 DEFINEREG(HSW_PWR_WELL_CTL2),
2377 DEFINEREG(HSW_PWR_WELL_CTL3),
2378 DEFINEREG(HSW_PWR_WELL_CTL4),
2379 DEFINEREG(HSW_PWR_WELL_CTL5),
2380 DEFINEREG(HSW_PWR_WELL_CTL6),
2381
2382 /* DDI pipe function */
2383 DEFINEREG2(PIPE_DDI_FUNC_CTL_A, hsw_debug_pipe_ddi_func_ctl),
2384 DEFINEREG2(PIPE_DDI_FUNC_CTL_B, hsw_debug_pipe_ddi_func_ctl),
2385 DEFINEREG2(PIPE_DDI_FUNC_CTL_C, hsw_debug_pipe_ddi_func_ctl),
2386 DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
2387
2388 /* DP transport control */
2389 DEFINEREG(DP_TP_CTL_A),
2390 DEFINEREG(DP_TP_CTL_B),
2391 DEFINEREG(DP_TP_CTL_C),
2392 DEFINEREG(DP_TP_CTL_D),
2393 DEFINEREG(DP_TP_CTL_E),
2394
2395 /* DP status */
2396 DEFINEREG(DP_TP_STATUS_B),
2397 DEFINEREG(DP_TP_STATUS_C),
2398 DEFINEREG(DP_TP_STATUS_D),
2399 DEFINEREG(DP_TP_STATUS_E),
2400
2401 /* DDI buffer control */
2402 DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),
2403 DEFINEREG2(DDI_BUF_CTL_B, hsw_debug_ddi_buf_ctl),
2404 DEFINEREG2(DDI_BUF_CTL_C, hsw_debug_ddi_buf_ctl),
2405 DEFINEREG2(DDI_BUF_CTL_D, hsw_debug_ddi_buf_ctl),
2406 DEFINEREG2(DDI_BUF_CTL_E, hsw_debug_ddi_buf_ctl),
2407
2408 /* Clocks */
2409 DEFINEREG(SPLL_CTL),
2410 DEFINEREG(LCPLL_CTL),
2411 DEFINEREG(WRPLL_CTL1),
2412 DEFINEREG(WRPLL_CTL2),
2413
2414 /* DDI port clock control */
2415 DEFINEREG2(PORT_CLK_SEL_A, hsw_debug_port_clk_sel),
2416 DEFINEREG2(PORT_CLK_SEL_B, hsw_debug_port_clk_sel),
2417 DEFINEREG2(PORT_CLK_SEL_C, hsw_debug_port_clk_sel),
2418 DEFINEREG2(PORT_CLK_SEL_D, hsw_debug_port_clk_sel),
2419 DEFINEREG2(PORT_CLK_SEL_E, hsw_debug_port_clk_sel),
2420
2421 /* Pipe clock control */
2422 DEFINEREG2(PIPE_CLK_SEL_A, hsw_debug_pipe_clk_sel),
2423 DEFINEREG2(PIPE_CLK_SEL_B, hsw_debug_pipe_clk_sel),
2424 DEFINEREG2(PIPE_CLK_SEL_C, hsw_debug_pipe_clk_sel),
2425
2426 /* Watermarks */
2427 DEFINEREG2(WM_PIPE_A, hsw_debug_wm_pipe),
2428 DEFINEREG2(WM_PIPE_B, hsw_debug_wm_pipe),
2429 DEFINEREG2(WM_PIPE_C, hsw_debug_wm_pipe),
2430 DEFINEREG2(WM_LP1, hsw_debug_lp_wm),
2431 DEFINEREG2(WM_LP2, hsw_debug_lp_wm),
2432 DEFINEREG2(WM_LP3, hsw_debug_lp_wm),
2433 DEFINEREG(WM_LP1_SPR),
2434 DEFINEREG(WM_LP2_SPR),
2435 DEFINEREG(WM_LP3_SPR),
2436 DEFINEREG(WM_MISC),
2437 DEFINEREG(WM_SR_CNT),
2438 DEFINEREG(PIPE_WM_LINETIME_A),
2439 DEFINEREG(PIPE_WM_LINETIME_B),
2440 DEFINEREG(PIPE_WM_LINETIME_C),
2441 DEFINEREG(WM_DBG),
2442
2443 /* Fuses */
2444 DEFINEREG2(SFUSE_STRAP, hsw_debug_sfuse_strap),
2445
2446 /* Pipe A */
2447 DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
2448 DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
2449 DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
2450 DEFINEREG(DSPASURF),
2451 DEFINEREG2(DSPATILEOFF, i830_debug_xy),
2452
2453 /* Pipe B */
2454 DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
2455 DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
2456 DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
2457 DEFINEREG(DSPBSURF),
2458 DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
2459
2460 /* Pipe C */
2461 DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
2462 DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
2463 DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
2464 DEFINEREG(DSPCSURF),
2465 DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
2466
2467 /* Transcoder A */
2468 DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
2469 DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
2470 DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
2471 DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
2472 DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
2473 DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
2474 DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
2475 DEFINEREG(VSYNCSHIFT_A),
2476 DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
2477 DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
2478 DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
2479 DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
2480
2481 /* Transcoder B */
2482 DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
2483 DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
2484 DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
2485 DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
2486 DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
2487 DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
2488 DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
2489 DEFINEREG(VSYNCSHIFT_B),
2490 DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
2491 DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
2492 DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
2493 DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
2494
2495 /* Transcoder C */
2496 DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
2497 DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
2498 DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
2499 DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
2500 DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
2501 DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
2502 DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
2503 DEFINEREG(VSYNCSHIFT_C),
2504 DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
2505 DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
2506 DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
2507 DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
2508
2509 /* Transcoder EDP */
2510 DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
2511 DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
2512 DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
2513 DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
2514 DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
2515 DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
2516 DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
2517 DEFINEREG(VSYNCSHIFT_EDP),
2518 DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
2519 DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
2520 DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
2521 DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
2522
2523 /* Panel fitter */
2524 DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
2525 DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
2526 DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
2527
2528 DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
2529 DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
2530 DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
2531
2532 DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
2533 DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
2534 DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
2535
2536 /* LPT */
2537
2538 DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
2539 DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
2540 DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
2541 DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
2542 DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
2543 DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
2544 DEFINEREG(TRANS_VSYNCSHIFT_A),
2545
2546 DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
2547
2548 DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
2549 DEFINEREG(FDI_RXA_TUSIZE1),
2550 DEFINEREG(FDI_RXA_IIR),
2551 DEFINEREG(FDI_RXA_IMR),
2552
2553 DEFINEREG2(BLC_PWM_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2554 DEFINEREG2(BLC_PWM_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2555 DEFINEREG2(BLC_PWM2_CPU_CTL2, ilk_debug_blc_pwm_cpu_ctl2),
2556 DEFINEREG2(BLC_PWM2_CPU_CTL, ilk_debug_blc_pwm_cpu_ctl),
2557 DEFINEREG2(BLC_MISC_CTL, hsw_debug_blc_misc_ctl),
2558 DEFINEREG2(BLC_PWM_PCH_CTL1, ibx_debug_blc_pwm_ctl1),
2559 DEFINEREG2(BLC_PWM_PCH_CTL2, ibx_debug_blc_pwm_ctl2),
2560
2561 DEFINEREG2(UTIL_PIN_CTL, hsw_debug_util_pin_ctl),
2562
2563 DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
2564 DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
2565 DEFINEREG(PCH_PP_ON_DELAYS),
2566 DEFINEREG(PCH_PP_OFF_DELAYS),
2567 DEFINEREG(PCH_PP_DIVISOR),
2568
2569 DEFINEREG(PIXCLK_GATE),
2570
2571 DEFINEREG2(SDEISR, hsw_debug_sinterrupt),
2572
2573 DEFINEREG(RC6_RESIDENCY_TIME),
2574 };
2575
2576 static const struct reg_debug i945gm_mi_regs[] = {
2577 DEFINEREG(PGETBL_CTL),
2578 DEFINEREG(PGTBL_ER),
2579 DEFINEREG(EXCC),
2580 DEFINEREG(HWS_PGA),
2581 DEFINEREG(IPEIR),
2582 DEFINEREG(IPEHR),
2583 DEFINEREG(INSTDONE),
2584 DEFINEREG(NOP_ID),
2585 DEFINEREG(HWSTAM),
2586 DEFINEREG(SCPD0),
2587 DEFINEREG(IER),
2588 DEFINEREG(IIR),
2589 DEFINEREG(IMR),
2590 DEFINEREG(ISR),
2591 DEFINEREG(EIR),
2592 DEFINEREG(EMR),
2593 DEFINEREG(ESR),
2594 DEFINEREG(INST_PM),
2595 DEFINEREG(ECOSKPD),
2596 };
2597
DEBUGSTRING(gen6_rp_control)2598 DEBUGSTRING(gen6_rp_control)
2599 {
2600 return z_snprintf(result, len, "%s",
2601 (val & (1 << 7)) ? "enabled" : "disabled");
2602 }
2603
2604 static const struct reg_debug gen6_rp_debug_regs[] = {
2605 DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),
2606 DEFINEREG(GEN6_RPNSWREQ),
2607 DEFINEREG(GEN6_RP_DOWN_TIMEOUT),
2608 DEFINEREG(GEN6_RP_INTERRUPT_LIMITS),
2609 DEFINEREG(GEN6_RP_UP_THRESHOLD),
2610 DEFINEREG(GEN6_RP_UP_EI),
2611 DEFINEREG(GEN6_RP_DOWN_EI),
2612 DEFINEREG(GEN6_RP_IDLE_HYSTERSIS),
2613 DEFINEREG(GEN6_RC_STATE),
2614 DEFINEREG(GEN6_RC_CONTROL),
2615 DEFINEREG(GEN6_RC1_WAKE_RATE_LIMIT),
2616 DEFINEREG(GEN6_RC6_WAKE_RATE_LIMIT),
2617 DEFINEREG(GEN6_RC_EVALUATION_INTERVAL),
2618 DEFINEREG(GEN6_RC_IDLE_HYSTERSIS),
2619 DEFINEREG(GEN6_RC_SLEEP),
2620 DEFINEREG(GEN6_RC1e_THRESHOLD),
2621 DEFINEREG(GEN6_RC6_THRESHOLD),
2622 DEFINEREG(GEN6_RC_VIDEO_FREQ),
2623 DEFINEREG(GEN6_PMIER),
2624 DEFINEREG(GEN6_PMIMR),
2625 DEFINEREG(GEN6_PMINTRMSK),
2626 };
2627
is_hsw_plus(uint32_t devid,uint32_t pch)2628 static bool is_hsw_plus(uint32_t devid, uint32_t pch)
2629 {
2630 return IS_HASWELL(devid) || intel_gen(devid) >= 8;
2631 }
2632
is_gen6_plus(uint32_t devid,uint32_t pch)2633 static bool is_gen6_plus(uint32_t devid, uint32_t pch)
2634 {
2635 return intel_gen(devid) >= 6;
2636 }
2637
is_gen56ivb(uint32_t devid,uint32_t pch)2638 static bool is_gen56ivb(uint32_t devid, uint32_t pch)
2639 {
2640 return IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid);
2641 }
2642
is_gen45(uint32_t devid,uint32_t pch)2643 static bool is_gen45(uint32_t devid, uint32_t pch)
2644 {
2645 return IS_GEN4(devid) || IS_GEN5(devid);
2646 }
2647
is_945gm(uint32_t devid,uint32_t pch)2648 static bool is_945gm(uint32_t devid, uint32_t pch)
2649 {
2650 return IS_945GM(devid);
2651 }
2652
is_gen234(uint32_t devid,uint32_t pch)2653 static bool is_gen234(uint32_t devid, uint32_t pch)
2654 {
2655 return IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid);
2656 }
2657
2658 #define DECLARE_REGS(d,r,m) \
2659 { .description = d, .regs = r, .count = ARRAY_SIZE(r), .match = m }
2660 static struct {
2661 const char *description;
2662 const struct reg_debug *regs;
2663 bool (*match)(uint32_t devid, uint32_t pch);
2664 int count;
2665 } known_registers[] = {
2666 DECLARE_REGS("Gen2", intel_debug_regs, is_gen234),
2667 DECLARE_REGS("i945GM", i945gm_mi_regs, is_945gm),
2668 DECLARE_REGS("Gen4", i965_fences, is_gen45),
2669 DECLARE_REGS("Gen5", ironlake_debug_regs, is_gen56ivb),
2670 DECLARE_REGS("Gen6", gen6_rp_debug_regs, is_gen6_plus),
2671 DECLARE_REGS("Gen6+", gen6_fences, is_gen6_plus),
2672 DECLARE_REGS("Gen7.5", haswell_debug_regs, is_hsw_plus),
2673 };
2674 #undef DECLARE_REGS
2675
2676 /*
2677 * Decode register value into buffer for devid.
2678 *
2679 * If devid is 0, decode for all known platforms, with newline after each
2680 * decode.
2681 */
intel_reg_spec_decode(char * buf,size_t bufsize,const struct reg * reg,uint32_t val,uint32_t devid)2682 int intel_reg_spec_decode(char *buf, size_t bufsize, const struct reg *reg,
2683 uint32_t val, uint32_t devid)
2684 {
2685 char tmp[1024];
2686 int i, j;
2687
2688 if (!bufsize)
2689 return -1;
2690
2691 *buf = 0;
2692
2693 for (i = 0; i < ARRAY_SIZE(known_registers); i++) {
2694 const struct reg_debug *regs = known_registers[i].regs;
2695
2696 if (devid) {
2697 if (known_registers[i].match &&
2698 !known_registers[i].match(devid, 0))
2699 continue;
2700 }
2701
2702 for (j = 0; j < known_registers[i].count; j++) {
2703 const struct reg_debug *r = ®s[j];
2704 if (reg->addr != r->reg)
2705 continue;
2706
2707 if (r->debug_output) {
2708 if (r->debug_output(tmp, sizeof(tmp), r->reg,
2709 val, devid) == 0)
2710 continue;
2711 } else if (devid) {
2712 return 0;
2713 } else {
2714 continue;
2715 }
2716
2717 if (devid) {
2718 strncpy(buf, tmp, bufsize);
2719 return 0;
2720 }
2721
2722 strncat(buf, known_registers[i].description, bufsize);
2723 strncat(buf, "\t", bufsize);
2724 strncat(buf, tmp, bufsize);
2725 strncat(buf, "\n", bufsize);
2726 }
2727 }
2728
2729 return 0;
2730 }
2731
get_regs(struct reg ** regs,size_t * nregs,ssize_t index,uint32_t devid)2732 static ssize_t get_regs(struct reg **regs, size_t *nregs, ssize_t index,
2733 uint32_t devid)
2734 {
2735 ssize_t ret = -1;
2736 int i, j;
2737
2738 if (!devid)
2739 return 0;
2740
2741 for (i = 0; i < ARRAY_SIZE(known_registers); i++) {
2742 if (known_registers[i].match &&
2743 !known_registers[i].match(devid, 0))
2744 continue;
2745
2746 for (j = 0; j < known_registers[i].count; j++) {
2747 const struct reg_debug *reg_in =
2748 &known_registers[i].regs[j];
2749 struct reg reg = {};
2750
2751 /* XXX: Could be optimized. */
2752 parse_port_desc(®, NULL);
2753
2754 reg.name = strdup(reg_in->name);
2755 reg.addr = reg_in->reg;
2756
2757 if (!*regs || index >= *nregs) {
2758 if (!*regs)
2759 *nregs = 64;
2760 else
2761 *nregs *= 2;
2762
2763 *regs = recalloc(*regs, *nregs, sizeof(**regs));
2764 if (!*regs) {
2765 fprintf(stderr, "Error: %s\n", strerror(ENOMEM));
2766 goto out;
2767 }
2768 }
2769
2770 (*regs)[index++] = reg;
2771 }
2772 }
2773
2774 ret = index;
2775
2776 out:
2777 return ret;
2778 }
2779
2780 /*
2781 * Get builtin register definitions for devid.
2782 */
intel_reg_spec_builtin(struct reg ** regs,uint32_t devid)2783 ssize_t intel_reg_spec_builtin(struct reg **regs, uint32_t devid)
2784 {
2785 size_t nregs = 0;
2786 *regs = NULL;
2787
2788 return get_regs(regs, &nregs, 0, devid);
2789 }
2790