1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static const nir_shader_compiler_options options = {
36 .lower_fpow = true,
37 .lower_scmp = true,
38 .lower_flrp16 = true,
39 .lower_flrp32 = true,
40 .lower_flrp64 = true,
41 .lower_ffract = true,
42 .lower_fmod = true,
43 .lower_fdiv = true,
44 .lower_isign = true,
45 .lower_ldexp = true,
46 .lower_uadd_carry = true,
47 .lower_usub_borrow = true,
48 .lower_mul_high = true,
49 .lower_mul_2x32_64 = true,
50 .fuse_ffma16 = true,
51 .fuse_ffma32 = true,
52 .fuse_ffma64 = true,
53 .vertex_id_zero_based = true,
54 .lower_extract_byte = true,
55 .lower_extract_word = true,
56 .lower_all_io_to_elements = true,
57 .lower_helper_invocation = true,
58 .lower_bitfield_insert_to_shifts = true,
59 .lower_bitfield_extract_to_shifts = true,
60 .lower_pack_half_2x16 = true,
61 .lower_pack_snorm_4x8 = true,
62 .lower_pack_snorm_2x16 = true,
63 .lower_pack_unorm_4x8 = true,
64 .lower_pack_unorm_2x16 = true,
65 .lower_unpack_half_2x16 = true,
66 .lower_unpack_snorm_4x8 = true,
67 .lower_unpack_snorm_2x16 = true,
68 .lower_unpack_unorm_4x8 = true,
69 .lower_unpack_unorm_2x16 = true,
70 .lower_pack_split = true,
71 .use_interpolated_input_intrinsics = true,
72 .lower_rotate = true,
73 .lower_to_scalar = true,
74 .has_imul24 = true,
75 .lower_wpos_pntc = true,
76 .lower_cs_local_index_from_id = true,
77
78 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
79 * but that should be harmless for GL since 64b is not
80 * supported there.
81 */
82 .lower_int64_options = (nir_lower_int64_options)~0,
83 .lower_uniforms_to_ubo = true,
84 };
85
86 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
87 static const nir_shader_compiler_options options_a6xx = {
88 .lower_fpow = true,
89 .lower_scmp = true,
90 .lower_flrp16 = true,
91 .lower_flrp32 = true,
92 .lower_flrp64 = true,
93 .lower_ffract = true,
94 .lower_fmod = true,
95 .lower_fdiv = true,
96 .lower_isign = true,
97 .lower_ldexp = true,
98 .lower_uadd_carry = true,
99 .lower_usub_borrow = true,
100 .lower_mul_high = true,
101 .lower_mul_2x32_64 = true,
102 .fuse_ffma16 = true,
103 .fuse_ffma32 = true,
104 .fuse_ffma64 = true,
105 .vertex_id_zero_based = false,
106 .lower_extract_byte = true,
107 .lower_extract_word = true,
108 .lower_all_io_to_elements = true,
109 .lower_helper_invocation = true,
110 .lower_bitfield_insert_to_shifts = true,
111 .lower_bitfield_extract_to_shifts = true,
112 .lower_pack_half_2x16 = true,
113 .lower_pack_snorm_4x8 = true,
114 .lower_pack_snorm_2x16 = true,
115 .lower_pack_unorm_4x8 = true,
116 .lower_pack_unorm_2x16 = true,
117 .lower_unpack_half_2x16 = true,
118 .lower_unpack_snorm_4x8 = true,
119 .lower_unpack_snorm_2x16 = true,
120 .lower_unpack_unorm_4x8 = true,
121 .lower_unpack_unorm_2x16 = true,
122 .lower_pack_split = true,
123 .use_interpolated_input_intrinsics = true,
124 .lower_rotate = true,
125 .vectorize_io = true,
126 .lower_to_scalar = true,
127 .has_imul24 = true,
128 .max_unroll_iterations = 32,
129 .lower_wpos_pntc = true,
130 .lower_cs_local_index_from_id = true,
131
132 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
133 * but that should be harmless for GL since 64b is not
134 * supported there.
135 */
136 .lower_int64_options = (nir_lower_int64_options)~0,
137 .lower_uniforms_to_ubo = true,
138 };
139
140 const nir_shader_compiler_options *
ir3_get_compiler_options(struct ir3_compiler * compiler)141 ir3_get_compiler_options(struct ir3_compiler *compiler)
142 {
143 if (compiler->gpu_id >= 600)
144 return &options_a6xx;
145 return &options;
146 }
147
148 static bool
ir3_nir_should_vectorize_mem(unsigned align_mul,unsigned align_offset,unsigned bit_size,unsigned num_components,nir_intrinsic_instr * low,nir_intrinsic_instr * high)149 ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
150 unsigned bit_size,
151 unsigned num_components,
152 nir_intrinsic_instr *low,
153 nir_intrinsic_instr *high)
154 {
155 assert(bit_size >= 8);
156 if (bit_size != 32)
157 return false;
158 unsigned byte_size = bit_size / 8;
159
160 int size = num_components * byte_size;
161
162 /* Don't care about alignment past vec4. */
163 assert(util_is_power_of_two_nonzero(align_mul));
164 align_mul = MIN2(align_mul, 16);
165 align_offset &= 15;
166
167 /* Our offset alignment should aways be at least 4 bytes */
168 if (align_mul < 4)
169 return false;
170
171 unsigned worst_start_offset = 16 - align_mul + align_offset;
172 if (worst_start_offset + size > 16)
173 return false;
174
175 return true;
176 }
177
178 #define OPT(nir, pass, ...) ({ \
179 bool this_progress = false; \
180 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
181 this_progress; \
182 })
183
184 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
185
186 void
ir3_optimize_loop(nir_shader * s)187 ir3_optimize_loop(nir_shader *s)
188 {
189 bool progress;
190 unsigned lower_flrp =
191 (s->options->lower_flrp16 ? 16 : 0) |
192 (s->options->lower_flrp32 ? 32 : 0) |
193 (s->options->lower_flrp64 ? 64 : 0);
194
195 do {
196 progress = false;
197
198 OPT_V(s, nir_lower_vars_to_ssa);
199 progress |= OPT(s, nir_opt_copy_prop_vars);
200 progress |= OPT(s, nir_opt_dead_write_vars);
201 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
202 progress |= OPT(s, nir_lower_phis_to_scalar);
203
204 progress |= OPT(s, nir_copy_prop);
205 progress |= OPT(s, nir_opt_dce);
206 progress |= OPT(s, nir_opt_cse);
207 static int gcm = -1;
208 if (gcm == -1)
209 gcm = env_var_as_unsigned("GCM", 0);
210 if (gcm == 1)
211 progress |= OPT(s, nir_opt_gcm, true);
212 else if (gcm == 2)
213 progress |= OPT(s, nir_opt_gcm, false);
214 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
215 progress |= OPT(s, nir_opt_intrinsics);
216 progress |= OPT(s, nir_opt_algebraic);
217 progress |= OPT(s, nir_lower_alu);
218 progress |= OPT(s, nir_lower_pack);
219 progress |= OPT(s, nir_opt_constant_folding);
220
221 progress |= OPT(s, nir_opt_load_store_vectorize, nir_var_mem_ubo,
222 ir3_nir_should_vectorize_mem, 0);
223
224 if (lower_flrp != 0) {
225 if (OPT(s, nir_lower_flrp,
226 lower_flrp,
227 false /* always_precise */)) {
228 OPT(s, nir_opt_constant_folding);
229 progress = true;
230 }
231
232 /* Nothing should rematerialize any flrps, so we only
233 * need to do this lowering once.
234 */
235 lower_flrp = 0;
236 }
237
238 progress |= OPT(s, nir_opt_dead_cf);
239 if (OPT(s, nir_opt_trivial_continues)) {
240 progress |= true;
241 /* If nir_opt_trivial_continues makes progress, then we need to clean
242 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
243 * to make progress.
244 */
245 OPT(s, nir_copy_prop);
246 OPT(s, nir_opt_dce);
247 }
248 progress |= OPT(s, nir_opt_if, false);
249 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
250 progress |= OPT(s, nir_opt_remove_phis);
251 progress |= OPT(s, nir_opt_undef);
252 } while (progress);
253 }
254
255 static bool
should_split_wrmask(const nir_instr * instr,const void * data)256 should_split_wrmask(const nir_instr *instr, const void *data)
257 {
258 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
259
260 switch (intr->intrinsic) {
261 case nir_intrinsic_store_ssbo:
262 case nir_intrinsic_store_shared:
263 case nir_intrinsic_store_global:
264 return true;
265 default:
266 return false;
267 }
268 }
269
270 void
ir3_finalize_nir(struct ir3_compiler * compiler,nir_shader * s)271 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
272 {
273 struct nir_lower_tex_options tex_options = {
274 .lower_rect = 0,
275 .lower_tg4_offsets = true,
276 };
277
278 if (compiler->gpu_id >= 400) {
279 /* a4xx seems to have *no* sam.p */
280 tex_options.lower_txp = ~0; /* lower all txp */
281 } else {
282 /* a3xx just needs to avoid sam.p for 3d tex */
283 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
284 }
285
286 if (ir3_shader_debug & IR3_DBG_DISASM) {
287 debug_printf("----------------------\n");
288 nir_print_shader(s, stdout);
289 debug_printf("----------------------\n");
290 }
291
292 if (s->info.stage == MESA_SHADER_GEOMETRY)
293 NIR_PASS_V(s, ir3_nir_lower_gs);
294
295 NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
296
297 NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
298
299 OPT_V(s, nir_lower_regs_to_ssa);
300 OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
301
302 OPT_V(s, nir_lower_tex, &tex_options);
303 OPT_V(s, nir_lower_load_const_to_scalar);
304 if (compiler->gpu_id < 500)
305 OPT_V(s, ir3_nir_lower_tg4_to_tex);
306
307 ir3_optimize_loop(s);
308
309 /* do idiv lowering after first opt loop to get a chance to propagate
310 * constants for divide by immed power-of-two:
311 */
312 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
313
314 if (idiv_progress)
315 ir3_optimize_loop(s);
316
317 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
318
319 if (ir3_shader_debug & IR3_DBG_DISASM) {
320 debug_printf("----------------------\n");
321 nir_print_shader(s, stdout);
322 debug_printf("----------------------\n");
323 }
324
325 nir_sweep(s);
326 }
327
328 /**
329 * Late passes that need to be done after pscreen->finalize_nir()
330 */
331 void
ir3_nir_post_finalize(struct ir3_compiler * compiler,nir_shader * s)332 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
333 {
334 NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
335 ir3_glsl_type_size, (nir_lower_io_options)0);
336
337 if (s->info.stage == MESA_SHADER_FRAGMENT) {
338 /* NOTE: lower load_barycentric_at_sample first, since it
339 * produces load_barycentric_at_offset:
340 */
341 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
342 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
343 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
344 NIR_PASS_V(s, nir_lower_fb_read);
345 }
346
347 if (compiler->gpu_id >= 600 &&
348 s->info.stage == MESA_SHADER_FRAGMENT &&
349 !(ir3_shader_debug & IR3_DBG_NOFP16)) {
350 NIR_PASS_V(s, nir_lower_mediump_outputs);
351 }
352
353 /* we cannot ensure that ir3_finalize_nir() is only called once, so
354 * we also need to do trig workarounds here:
355 */
356 OPT_V(s, ir3_nir_apply_trig_workarounds);
357
358 ir3_optimize_loop(s);
359 }
360
361 static bool
ir3_nir_lower_view_layer_id(nir_shader * nir,bool layer_zero,bool view_zero)362 ir3_nir_lower_view_layer_id(nir_shader *nir, bool layer_zero, bool view_zero)
363 {
364 unsigned layer_id_loc = ~0, view_id_loc = ~0;
365 nir_foreach_shader_in_variable(var, nir) {
366 if (var->data.location == VARYING_SLOT_LAYER)
367 layer_id_loc = var->data.driver_location;
368 if (var->data.location == VARYING_SLOT_VIEWPORT)
369 view_id_loc = var->data.driver_location;
370 }
371
372 assert(!layer_zero || layer_id_loc != ~0);
373 assert(!view_zero || view_id_loc != ~0);
374
375 bool progress = false;
376 nir_builder b;
377
378 nir_foreach_function(func, nir) {
379 nir_builder_init(&b, func->impl);
380
381 nir_foreach_block(block, func->impl) {
382 nir_foreach_instr_safe(instr, block) {
383 if (instr->type != nir_instr_type_intrinsic)
384 continue;
385
386 nir_intrinsic_instr *intrin =
387 nir_instr_as_intrinsic(instr);
388
389 if (intrin->intrinsic != nir_intrinsic_load_input)
390 continue;
391
392 unsigned base = nir_intrinsic_base(intrin);
393 if (base != layer_id_loc && base != view_id_loc)
394 continue;
395
396 b.cursor = nir_before_instr(&intrin->instr);
397 nir_ssa_def *zero = nir_imm_int(&b, 0);
398 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
399 nir_src_for_ssa(zero));
400 nir_instr_remove(&intrin->instr);
401 progress = true;
402 }
403 }
404
405 if (progress) {
406 nir_metadata_preserve(func->impl,
407 nir_metadata_block_index |
408 nir_metadata_dominance);
409 } else {
410 nir_metadata_preserve(func->impl, nir_metadata_all);
411 }
412 }
413
414 return progress;
415 }
416
417 void
ir3_nir_lower_variant(struct ir3_shader_variant * so,nir_shader * s)418 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
419 {
420 if (ir3_shader_debug & IR3_DBG_DISASM) {
421 debug_printf("----------------------\n");
422 nir_print_shader(s, stdout);
423 debug_printf("----------------------\n");
424 }
425
426 bool progress = false;
427
428 if (so->key.has_gs || so->key.tessellation) {
429 switch (so->shader->type) {
430 case MESA_SHADER_VERTEX:
431 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
432 progress = true;
433 break;
434 case MESA_SHADER_TESS_CTRL:
435 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
436 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so);
437 progress = true;
438 break;
439 case MESA_SHADER_TESS_EVAL:
440 NIR_PASS_V(s, ir3_nir_lower_tess_eval, so, so->key.tessellation);
441 if (so->key.has_gs)
442 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
443 progress = true;
444 break;
445 case MESA_SHADER_GEOMETRY:
446 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so);
447 progress = true;
448 break;
449 default:
450 break;
451 }
452 }
453
454 if (s->info.stage == MESA_SHADER_VERTEX) {
455 if (so->key.ucp_enables)
456 progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
457 if (so->key.vclamp_color)
458 progress |= OPT(s, nir_lower_clamp_color_outputs);
459 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
460 bool layer_zero = so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER);
461 bool view_zero = so->key.view_zero && (s->info.inputs_read & VARYING_BIT_VIEWPORT);
462
463 if (so->key.ucp_enables && !so->shader->compiler->has_clip_cull)
464 progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
465 if (so->key.fclamp_color)
466 progress |= OPT(s, nir_lower_clamp_color_outputs);
467 if (layer_zero || view_zero)
468 progress |= OPT(s, ir3_nir_lower_view_layer_id, layer_zero, view_zero);
469 }
470 if (so->key.color_two_side) {
471 OPT_V(s, nir_lower_two_sided_color, true);
472 progress = true;
473 }
474
475 struct nir_lower_tex_options tex_options = { };
476
477 switch (so->shader->type) {
478 case MESA_SHADER_FRAGMENT:
479 tex_options.saturate_s = so->key.fsaturate_s;
480 tex_options.saturate_t = so->key.fsaturate_t;
481 tex_options.saturate_r = so->key.fsaturate_r;
482 break;
483 case MESA_SHADER_VERTEX:
484 tex_options.saturate_s = so->key.vsaturate_s;
485 tex_options.saturate_t = so->key.vsaturate_t;
486 tex_options.saturate_r = so->key.vsaturate_r;
487 break;
488 default:
489 /* TODO */
490 break;
491 }
492
493 if (tex_options.saturate_s || tex_options.saturate_t ||
494 tex_options.saturate_r) {
495 progress |= OPT(s, nir_lower_tex, &tex_options);
496 }
497
498 if (!so->binning_pass)
499 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
500
501 progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
502
503 /* UBO offset lowering has to come after we've decided what will
504 * be left as load_ubo
505 */
506 if (so->shader->compiler->gpu_id >= 600)
507 progress |= OPT(s, nir_lower_ubo_vec4);
508
509 OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
510
511 if (progress)
512 ir3_optimize_loop(s);
513
514 /* Do late algebraic optimization to turn add(a, neg(b)) back into
515 * subs, then the mandatory cleanup after algebraic. Note that it may
516 * produce fnegs, and if so then we need to keep running to squash
517 * fneg(fneg(a)).
518 */
519 bool more_late_algebraic = true;
520 while (more_late_algebraic) {
521 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
522 OPT_V(s, nir_opt_constant_folding);
523 OPT_V(s, nir_copy_prop);
524 OPT_V(s, nir_opt_dce);
525 OPT_V(s, nir_opt_cse);
526 }
527
528 OPT_V(s, nir_opt_sink, nir_move_const_undef);
529
530 if (ir3_shader_debug & IR3_DBG_DISASM) {
531 debug_printf("----------------------\n");
532 nir_print_shader(s, stdout);
533 debug_printf("----------------------\n");
534 }
535
536 nir_sweep(s);
537
538 /* Binning pass variants re-use the const_state of the corresponding
539 * draw pass shader, so that same const emit can be re-used for both
540 * passes:
541 */
542 if (!so->binning_pass)
543 ir3_setup_const_state(s, so, ir3_const_state(so));
544 }
545
546 static void
ir3_nir_scan_driver_consts(nir_shader * shader,struct ir3_const_state * layout)547 ir3_nir_scan_driver_consts(nir_shader *shader,
548 struct ir3_const_state *layout)
549 {
550 nir_foreach_function (function, shader) {
551 if (!function->impl)
552 continue;
553
554 nir_foreach_block (block, function->impl) {
555 nir_foreach_instr (instr, block) {
556 if (instr->type != nir_instr_type_intrinsic)
557 continue;
558
559 nir_intrinsic_instr *intr =
560 nir_instr_as_intrinsic(instr);
561 unsigned idx;
562
563 switch (intr->intrinsic) {
564 case nir_intrinsic_get_ssbo_size:
565 if (ir3_bindless_resource(intr->src[0]))
566 break;
567 idx = nir_src_as_uint(intr->src[0]);
568 if (layout->ssbo_size.mask & (1 << idx))
569 break;
570 layout->ssbo_size.mask |= (1 << idx);
571 layout->ssbo_size.off[idx] =
572 layout->ssbo_size.count;
573 layout->ssbo_size.count += 1; /* one const per */
574 break;
575 case nir_intrinsic_image_atomic_add:
576 case nir_intrinsic_image_atomic_imin:
577 case nir_intrinsic_image_atomic_umin:
578 case nir_intrinsic_image_atomic_imax:
579 case nir_intrinsic_image_atomic_umax:
580 case nir_intrinsic_image_atomic_and:
581 case nir_intrinsic_image_atomic_or:
582 case nir_intrinsic_image_atomic_xor:
583 case nir_intrinsic_image_atomic_exchange:
584 case nir_intrinsic_image_atomic_comp_swap:
585 case nir_intrinsic_image_store:
586 case nir_intrinsic_image_size:
587 idx = nir_src_as_uint(intr->src[0]);
588 if (layout->image_dims.mask & (1 << idx))
589 break;
590 layout->image_dims.mask |= (1 << idx);
591 layout->image_dims.off[idx] =
592 layout->image_dims.count;
593 layout->image_dims.count += 3; /* three const per */
594 break;
595 case nir_intrinsic_load_base_vertex:
596 case nir_intrinsic_load_first_vertex:
597 layout->num_driver_params =
598 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
599 break;
600 case nir_intrinsic_load_base_instance:
601 layout->num_driver_params =
602 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
603 break;
604 case nir_intrinsic_load_user_clip_plane:
605 idx = nir_intrinsic_ucp_id(intr);
606 layout->num_driver_params =
607 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
608 break;
609 case nir_intrinsic_load_num_work_groups:
610 layout->num_driver_params =
611 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
612 break;
613 case nir_intrinsic_load_local_group_size:
614 layout->num_driver_params =
615 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
616 break;
617 default:
618 break;
619 }
620 }
621 }
622 }
623 }
624
625 /* Sets up the variant-dependent constant state for the ir3_shader. Note
626 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
627 * maximum number of driver params that would eventually be used, to leave
628 * space for this function to allocate the driver params.
629 */
630 void
ir3_setup_const_state(nir_shader * nir,struct ir3_shader_variant * v,struct ir3_const_state * const_state)631 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
632 struct ir3_const_state *const_state)
633 {
634 struct ir3_compiler *compiler = v->shader->compiler;
635
636 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
637
638 ir3_nir_scan_driver_consts(nir, const_state);
639
640 if ((compiler->gpu_id < 500) &&
641 (v->shader->stream_output.num_outputs > 0)) {
642 const_state->num_driver_params =
643 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
644 }
645
646 const_state->num_ubos = nir->info.num_ubos;
647
648 /* num_driver_params is scalar, align to vec4: */
649 const_state->num_driver_params = align(const_state->num_driver_params, 4);
650
651 debug_assert((const_state->ubo_state.size % 16) == 0);
652 unsigned constoff = const_state->ubo_state.size / 16;
653 unsigned ptrsz = ir3_pointer_size(compiler);
654
655 if (const_state->num_ubos > 0) {
656 const_state->offsets.ubo = constoff;
657 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
658 }
659
660 if (const_state->ssbo_size.count > 0) {
661 unsigned cnt = const_state->ssbo_size.count;
662 const_state->offsets.ssbo_sizes = constoff;
663 constoff += align(cnt, 4) / 4;
664 }
665
666 if (const_state->image_dims.count > 0) {
667 unsigned cnt = const_state->image_dims.count;
668 const_state->offsets.image_dims = constoff;
669 constoff += align(cnt, 4) / 4;
670 }
671
672 if (const_state->num_driver_params > 0) {
673 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
674 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
675 constoff = MAX2(constoff, 1);
676 const_state->offsets.driver_param = constoff;
677 }
678 constoff += const_state->num_driver_params / 4;
679
680 if ((v->type == MESA_SHADER_VERTEX) &&
681 (compiler->gpu_id < 500) &&
682 v->shader->stream_output.num_outputs > 0) {
683 const_state->offsets.tfbo = constoff;
684 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
685 }
686
687 switch (v->type) {
688 case MESA_SHADER_VERTEX:
689 const_state->offsets.primitive_param = constoff;
690 constoff += 1;
691 break;
692 case MESA_SHADER_TESS_CTRL:
693 case MESA_SHADER_TESS_EVAL:
694 constoff = align(constoff - 1, 4) + 3;
695 const_state->offsets.primitive_param = constoff;
696 const_state->offsets.primitive_map = constoff + 5;
697 constoff += 5 + DIV_ROUND_UP(v->input_size, 4);
698 break;
699 case MESA_SHADER_GEOMETRY:
700 const_state->offsets.primitive_param = constoff;
701 const_state->offsets.primitive_map = constoff + 1;
702 constoff += 1 + DIV_ROUND_UP(v->input_size, 4);
703 break;
704 default:
705 break;
706 }
707
708 const_state->offsets.immediate = constoff;
709
710 assert(constoff <= ir3_max_const(v));
711 }
712