1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_resource.c
25 *
26 * Resources are images, buffers, and other objects used by the GPU.
27 *
28 * XXX: explain resources
29 */
30
31 #include <stdio.h>
32 #include <errno.h>
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "util/os_memory.h"
38 #include "util/u_cpu_detect.h"
39 #include "util/u_inlines.h"
40 #include "util/format/u_format.h"
41 #include "util/u_threaded_context.h"
42 #include "util/u_transfer.h"
43 #include "util/u_transfer_helper.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/ralloc.h"
46 #include "iris_batch.h"
47 #include "iris_context.h"
48 #include "iris_resource.h"
49 #include "iris_screen.h"
50 #include "intel/common/gen_aux_map.h"
51 #include "intel/dev/gen_debug.h"
52 #include "isl/isl.h"
53 #include "drm-uapi/drm_fourcc.h"
54 #include "drm-uapi/i915_drm.h"
55
56 enum modifier_priority {
57 MODIFIER_PRIORITY_INVALID = 0,
58 MODIFIER_PRIORITY_LINEAR,
59 MODIFIER_PRIORITY_X,
60 MODIFIER_PRIORITY_Y,
61 MODIFIER_PRIORITY_Y_CCS,
62 MODIFIER_PRIORITY_Y_GEN12_RC_CCS,
63 };
64
65 static const uint64_t priority_to_modifier[] = {
66 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
67 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
68 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
69 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
70 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
71 [MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
72 };
73
74 static bool
modifier_is_supported(const struct gen_device_info * devinfo,enum pipe_format pfmt,uint64_t modifier)75 modifier_is_supported(const struct gen_device_info *devinfo,
76 enum pipe_format pfmt, uint64_t modifier)
77 {
78 /* Check for basic device support. */
79 switch (modifier) {
80 case DRM_FORMAT_MOD_LINEAR:
81 case I915_FORMAT_MOD_X_TILED:
82 case I915_FORMAT_MOD_Y_TILED:
83 break;
84 case I915_FORMAT_MOD_Y_TILED_CCS:
85 if (devinfo->gen <= 8 || devinfo->gen >= 12)
86 return false;
87 break;
88 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
89 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
90 if (devinfo->gen != 12)
91 return false;
92 break;
93 case DRM_FORMAT_MOD_INVALID:
94 default:
95 return false;
96 }
97
98 /* Check remaining requirements. */
99 switch (modifier) {
100 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
101 if (pfmt != PIPE_FORMAT_BGRA8888_UNORM &&
102 pfmt != PIPE_FORMAT_RGBA8888_UNORM &&
103 pfmt != PIPE_FORMAT_BGRX8888_UNORM &&
104 pfmt != PIPE_FORMAT_RGBX8888_UNORM &&
105 pfmt != PIPE_FORMAT_NV12 &&
106 pfmt != PIPE_FORMAT_P010 &&
107 pfmt != PIPE_FORMAT_P012 &&
108 pfmt != PIPE_FORMAT_P016 &&
109 pfmt != PIPE_FORMAT_YUYV &&
110 pfmt != PIPE_FORMAT_UYVY) {
111 return false;
112 }
113 break;
114 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
115 case I915_FORMAT_MOD_Y_TILED_CCS: {
116 if (INTEL_DEBUG & DEBUG_NO_RBC)
117 return false;
118
119 enum isl_format rt_format =
120 iris_format_for_usage(devinfo, pfmt,
121 ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt;
122
123 if (rt_format == ISL_FORMAT_UNSUPPORTED ||
124 !isl_format_supports_ccs_e(devinfo, rt_format))
125 return false;
126 break;
127 }
128 default:
129 break;
130 }
131
132 return true;
133 }
134
135 static uint64_t
select_best_modifier(struct gen_device_info * devinfo,enum pipe_format pfmt,const uint64_t * modifiers,int count)136 select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
137 const uint64_t *modifiers,
138 int count)
139 {
140 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
141
142 for (int i = 0; i < count; i++) {
143 if (!modifier_is_supported(devinfo, pfmt, modifiers[i]))
144 continue;
145
146 switch (modifiers[i]) {
147 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
148 prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS);
149 break;
150 case I915_FORMAT_MOD_Y_TILED_CCS:
151 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
152 break;
153 case I915_FORMAT_MOD_Y_TILED:
154 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
155 break;
156 case I915_FORMAT_MOD_X_TILED:
157 prio = MAX2(prio, MODIFIER_PRIORITY_X);
158 break;
159 case DRM_FORMAT_MOD_LINEAR:
160 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
161 break;
162 case DRM_FORMAT_MOD_INVALID:
163 default:
164 break;
165 }
166 }
167
168 return priority_to_modifier[prio];
169 }
170
171 enum isl_surf_dim
target_to_isl_surf_dim(enum pipe_texture_target target)172 target_to_isl_surf_dim(enum pipe_texture_target target)
173 {
174 switch (target) {
175 case PIPE_BUFFER:
176 case PIPE_TEXTURE_1D:
177 case PIPE_TEXTURE_1D_ARRAY:
178 return ISL_SURF_DIM_1D;
179 case PIPE_TEXTURE_2D:
180 case PIPE_TEXTURE_CUBE:
181 case PIPE_TEXTURE_RECT:
182 case PIPE_TEXTURE_2D_ARRAY:
183 case PIPE_TEXTURE_CUBE_ARRAY:
184 return ISL_SURF_DIM_2D;
185 case PIPE_TEXTURE_3D:
186 return ISL_SURF_DIM_3D;
187 case PIPE_MAX_TEXTURE_TYPES:
188 break;
189 }
190 unreachable("invalid texture type");
191 }
192
193 static void
iris_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format pfmt,int max,uint64_t * modifiers,unsigned int * external_only,int * count)194 iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
195 enum pipe_format pfmt,
196 int max,
197 uint64_t *modifiers,
198 unsigned int *external_only,
199 int *count)
200 {
201 struct iris_screen *screen = (void *) pscreen;
202 const struct gen_device_info *devinfo = &screen->devinfo;
203
204 uint64_t all_modifiers[] = {
205 DRM_FORMAT_MOD_LINEAR,
206 I915_FORMAT_MOD_X_TILED,
207 I915_FORMAT_MOD_Y_TILED,
208 I915_FORMAT_MOD_Y_TILED_CCS,
209 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
210 I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
211 };
212
213 int supported_mods = 0;
214
215 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
216 if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i]))
217 continue;
218
219 if (supported_mods < max) {
220 if (modifiers)
221 modifiers[supported_mods] = all_modifiers[i];
222
223 if (external_only) {
224 /* Only allow external usage for the following cases: YUV formats
225 * and the media-compression modifier. The render engine lacks
226 * support for rendering to a media-compressed surface if the
227 * compression ratio is large enough. By requiring external usage
228 * of media-compressed surfaces, resolves are avoided.
229 */
230 external_only[supported_mods] =
231 util_format_is_yuv(pfmt) ||
232 all_modifiers[i] == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
233 }
234 }
235
236 supported_mods++;
237 }
238
239 *count = supported_mods;
240 }
241
242 enum isl_format
iris_image_view_get_format(struct iris_context * ice,const struct pipe_image_view * img)243 iris_image_view_get_format(struct iris_context *ice,
244 const struct pipe_image_view *img)
245 {
246 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
247 const struct gen_device_info *devinfo = &screen->devinfo;
248
249 isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
250 enum isl_format isl_fmt =
251 iris_format_for_usage(devinfo, img->format, usage).fmt;
252
253 if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
254 /* On Gen8, try to use typed surfaces reads (which support a
255 * limited number of formats), and if not possible, fall back
256 * to untyped reads.
257 */
258 if (devinfo->gen == 8 &&
259 !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt))
260 return ISL_FORMAT_RAW;
261 else
262 return isl_lower_storage_image_format(devinfo, isl_fmt);
263 }
264
265 return isl_fmt;
266 }
267
268 struct pipe_resource *
iris_resource_get_separate_stencil(struct pipe_resource * p_res)269 iris_resource_get_separate_stencil(struct pipe_resource *p_res)
270 {
271 /* For packed depth-stencil, we treat depth as the primary resource
272 * and store S8 as the "second plane" resource.
273 */
274 if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT)
275 return p_res->next;
276
277 return NULL;
278
279 }
280
281 static void
iris_resource_set_separate_stencil(struct pipe_resource * p_res,struct pipe_resource * stencil)282 iris_resource_set_separate_stencil(struct pipe_resource *p_res,
283 struct pipe_resource *stencil)
284 {
285 assert(util_format_has_depth(util_format_description(p_res->format)));
286 pipe_resource_reference(&p_res->next, stencil);
287 }
288
289 void
iris_get_depth_stencil_resources(struct pipe_resource * res,struct iris_resource ** out_z,struct iris_resource ** out_s)290 iris_get_depth_stencil_resources(struct pipe_resource *res,
291 struct iris_resource **out_z,
292 struct iris_resource **out_s)
293 {
294 if (!res) {
295 *out_z = NULL;
296 *out_s = NULL;
297 return;
298 }
299
300 if (res->format != PIPE_FORMAT_S8_UINT) {
301 *out_z = (void *) res;
302 *out_s = (void *) iris_resource_get_separate_stencil(res);
303 } else {
304 *out_z = NULL;
305 *out_s = (void *) res;
306 }
307 }
308
309 enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info * devinfo,enum isl_tiling tiling,enum pipe_texture_target target)310 iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
311 enum isl_tiling tiling,
312 enum pipe_texture_target target)
313 {
314 switch (target) {
315 case PIPE_TEXTURE_1D:
316 case PIPE_TEXTURE_1D_ARRAY:
317 return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ?
318 ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D);
319
320 case PIPE_TEXTURE_2D:
321 case PIPE_TEXTURE_2D_ARRAY:
322 case PIPE_TEXTURE_RECT:
323 case PIPE_TEXTURE_CUBE:
324 case PIPE_TEXTURE_CUBE_ARRAY:
325 return ISL_DIM_LAYOUT_GEN4_2D;
326
327 case PIPE_TEXTURE_3D:
328 return (devinfo->gen >= 9 ?
329 ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D);
330
331 case PIPE_MAX_TEXTURE_TYPES:
332 case PIPE_BUFFER:
333 break;
334 }
335 unreachable("invalid texture type");
336 }
337
338 void
iris_resource_disable_aux(struct iris_resource * res)339 iris_resource_disable_aux(struct iris_resource *res)
340 {
341 iris_bo_unreference(res->aux.bo);
342 iris_bo_unreference(res->aux.clear_color_bo);
343 free(res->aux.state);
344
345 res->aux.usage = ISL_AUX_USAGE_NONE;
346 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
347 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
348 res->aux.has_hiz = 0;
349 res->aux.surf.size_B = 0;
350 res->aux.bo = NULL;
351 res->aux.extra_aux.surf.size_B = 0;
352 res->aux.clear_color_bo = NULL;
353 res->aux.state = NULL;
354 }
355
356 static void
iris_resource_destroy(struct pipe_screen * screen,struct pipe_resource * resource)357 iris_resource_destroy(struct pipe_screen *screen,
358 struct pipe_resource *resource)
359 {
360 struct iris_resource *res = (struct iris_resource *)resource;
361
362 if (resource->target == PIPE_BUFFER)
363 util_range_destroy(&res->valid_buffer_range);
364
365 iris_resource_disable_aux(res);
366
367 iris_bo_unreference(res->bo);
368 iris_pscreen_unref(res->base.screen);
369
370 free(res);
371 }
372
373 static struct iris_resource *
iris_alloc_resource(struct pipe_screen * pscreen,const struct pipe_resource * templ)374 iris_alloc_resource(struct pipe_screen *pscreen,
375 const struct pipe_resource *templ)
376 {
377 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
378 if (!res)
379 return NULL;
380
381 res->base = *templ;
382 res->base.screen = iris_pscreen_ref(pscreen);
383 pipe_reference_init(&res->base.reference, 1);
384
385 res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
386 res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
387
388 if (templ->target == PIPE_BUFFER)
389 util_range_init(&res->valid_buffer_range);
390
391 return res;
392 }
393
394 unsigned
iris_get_num_logical_layers(const struct iris_resource * res,unsigned level)395 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
396 {
397 if (res->surf.dim == ISL_SURF_DIM_3D)
398 return minify(res->surf.logical_level0_px.depth, level);
399 else
400 return res->surf.logical_level0_px.array_len;
401 }
402
403 static enum isl_aux_state **
create_aux_state_map(struct iris_resource * res,enum isl_aux_state initial)404 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
405 {
406 assert(res->aux.state == NULL);
407
408 uint32_t total_slices = 0;
409 for (uint32_t level = 0; level < res->surf.levels; level++)
410 total_slices += iris_get_num_logical_layers(res, level);
411
412 const size_t per_level_array_size =
413 res->surf.levels * sizeof(enum isl_aux_state *);
414
415 /* We're going to allocate a single chunk of data for both the per-level
416 * reference array and the arrays of aux_state. This makes cleanup
417 * significantly easier.
418 */
419 const size_t total_size =
420 per_level_array_size + total_slices * sizeof(enum isl_aux_state);
421
422 void *data = malloc(total_size);
423 if (!data)
424 return NULL;
425
426 enum isl_aux_state **per_level_arr = data;
427 enum isl_aux_state *s = data + per_level_array_size;
428 for (uint32_t level = 0; level < res->surf.levels; level++) {
429 per_level_arr[level] = s;
430 const unsigned level_layers = iris_get_num_logical_layers(res, level);
431 for (uint32_t a = 0; a < level_layers; a++)
432 *(s++) = initial;
433 }
434 assert((void *)s == data + total_size);
435
436 return per_level_arr;
437 }
438
439 static unsigned
iris_get_aux_clear_color_state_size(struct iris_screen * screen)440 iris_get_aux_clear_color_state_size(struct iris_screen *screen)
441 {
442 const struct gen_device_info *devinfo = &screen->devinfo;
443 return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
444 }
445
446 static void
map_aux_addresses(struct iris_screen * screen,struct iris_resource * res,enum isl_format format,unsigned plane)447 map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
448 enum isl_format format, unsigned plane)
449 {
450 const struct gen_device_info *devinfo = &screen->devinfo;
451 if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
452 void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
453 assert(aux_map_ctx);
454 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
455 res->aux.extra_aux.offset : res->aux.offset;
456 const uint64_t format_bits =
457 gen_aux_map_format_bits(res->surf.tiling, format, plane);
458 gen_aux_map_add_mapping(aux_map_ctx, res->bo->gtt_offset + res->offset,
459 res->aux.bo->gtt_offset + aux_offset,
460 res->surf.size_B, format_bits);
461 res->bo->aux_map_address = res->aux.bo->gtt_offset;
462 }
463 }
464
465 static bool
want_ccs_e_for_format(const struct gen_device_info * devinfo,enum isl_format format)466 want_ccs_e_for_format(const struct gen_device_info *devinfo,
467 enum isl_format format)
468 {
469 if (!isl_format_supports_ccs_e(devinfo, format))
470 return false;
471
472 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
473
474 /* CCS_E seems to significantly hurt performance with 32-bit floating
475 * point formats. For example, Paraview's "Wavelet Volume" case uses
476 * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those
477 * formats causes a 62% FPS drop.
478 *
479 * However, many benchmarks seem to use 16-bit float with no issues.
480 */
481 if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT)
482 return false;
483
484 return true;
485 }
486
487 static bool
iris_resource_configure_main(const struct iris_screen * screen,struct iris_resource * res,const struct pipe_resource * templ,uint64_t modifier,uint32_t row_pitch_B)488 iris_resource_configure_main(const struct iris_screen *screen,
489 struct iris_resource *res,
490 const struct pipe_resource *templ,
491 uint64_t modifier, uint32_t row_pitch_B)
492 {
493 res->mod_info = isl_drm_modifier_get_info(modifier);
494
495 if (modifier != DRM_FORMAT_MOD_INVALID && res->mod_info == NULL)
496 return false;
497
498 isl_tiling_flags_t tiling_flags = 0;
499
500 if (res->mod_info != NULL) {
501 tiling_flags = 1 << res->mod_info->tiling;
502 } else if (templ->usage == PIPE_USAGE_STAGING ||
503 templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) {
504 tiling_flags = ISL_TILING_LINEAR_BIT;
505 } else if (templ->bind & PIPE_BIND_SCANOUT) {
506 tiling_flags = screen->devinfo.has_tiling_uapi ?
507 ISL_TILING_X_BIT : ISL_TILING_LINEAR_BIT;
508 } else {
509 tiling_flags = ISL_TILING_ANY_MASK;
510 }
511
512 isl_surf_usage_flags_t usage = 0;
513
514 if (templ->usage == PIPE_USAGE_STAGING)
515 usage |= ISL_SURF_USAGE_STAGING_BIT;
516
517 if (templ->bind & PIPE_BIND_RENDER_TARGET)
518 usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
519
520 if (templ->bind & PIPE_BIND_SAMPLER_VIEW)
521 usage |= ISL_SURF_USAGE_TEXTURE_BIT;
522
523 if (templ->bind & PIPE_BIND_SHADER_IMAGE)
524 usage |= ISL_SURF_USAGE_STORAGE_BIT;
525
526 if (templ->bind & PIPE_BIND_SCANOUT)
527 usage |= ISL_SURF_USAGE_DISPLAY_BIT;
528
529 if (templ->target == PIPE_TEXTURE_CUBE ||
530 templ->target == PIPE_TEXTURE_CUBE_ARRAY) {
531 usage |= ISL_SURF_USAGE_CUBE_BIT;
532 }
533
534 if (templ->usage != PIPE_USAGE_STAGING &&
535 util_format_is_depth_or_stencil(templ->format)) {
536
537 /* Should be handled by u_transfer_helper */
538 assert(!util_format_is_depth_and_stencil(templ->format));
539
540 usage |= templ->format == PIPE_FORMAT_S8_UINT ?
541 ISL_SURF_USAGE_STENCIL_BIT : ISL_SURF_USAGE_DEPTH_BIT;
542 }
543
544 const enum isl_format format =
545 iris_format_for_usage(&screen->devinfo, templ->format, usage).fmt;
546
547 const struct isl_surf_init_info init_info = {
548 .dim = target_to_isl_surf_dim(templ->target),
549 .format = format,
550 .width = templ->width0,
551 .height = templ->height0,
552 .depth = templ->depth0,
553 .levels = templ->last_level + 1,
554 .array_len = templ->array_size,
555 .samples = MAX2(templ->nr_samples, 1),
556 .min_alignment_B = 0,
557 .row_pitch_B = row_pitch_B,
558 .usage = usage,
559 .tiling_flags = tiling_flags
560 };
561
562 if (!isl_surf_init_s(&screen->isl_dev, &res->surf, &init_info))
563 return false;
564
565 res->internal_format = templ->format;
566
567 return true;
568 }
569
570 /**
571 * Configure aux for the resource, but don't allocate it. For images which
572 * might be shared with modifiers, we must allocate the image and aux data in
573 * a single bo.
574 *
575 * Returns false on unexpected error (e.g. allocation failed, or invalid
576 * configuration result).
577 */
578 static bool
iris_resource_configure_aux(struct iris_screen * screen,struct iris_resource * res,bool imported)579 iris_resource_configure_aux(struct iris_screen *screen,
580 struct iris_resource *res, bool imported)
581 {
582 const struct gen_device_info *devinfo = &screen->devinfo;
583
584 /* Try to create the auxiliary surfaces allowed by the modifier or by
585 * the user if no modifier is specified.
586 */
587 assert(!res->mod_info ||
588 res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
589 res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
590 res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E ||
591 res->mod_info->aux_usage == ISL_AUX_USAGE_MC);
592
593 const bool has_mcs = !res->mod_info &&
594 isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
595
596 const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) &&
597 isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
598
599 const bool has_ccs =
600 ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) ||
601 (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) &&
602 isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf,
603 &res->aux.extra_aux.surf, 0);
604
605 /* Having both HIZ and MCS is impossible. */
606 assert(!has_mcs || !has_hiz);
607
608 /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */
609 if (has_ccs && (has_mcs || has_hiz)) {
610 assert(res->aux.extra_aux.surf.size_B > 0 &&
611 res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT);
612 assert(res->aux.surf.size_B > 0 &&
613 res->aux.surf.usage &
614 (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT));
615 }
616
617 if (res->mod_info && has_ccs) {
618 /* Only allow a CCS modifier if the aux was created successfully. */
619 res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
620 } else if (has_mcs) {
621 res->aux.possible_usages |=
622 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS);
623 } else if (has_hiz) {
624 if (!has_ccs) {
625 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
626 } else if (res->surf.samples == 1 &&
627 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
628 /* If this resource is single-sampled and will be used as a texture,
629 * put the HiZ surface in write-through mode so that we can sample
630 * from it.
631 */
632 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
633 } else {
634 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS;
635 }
636 } else if (has_ccs && isl_surf_usage_is_stencil(res->surf.usage)) {
637 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_STC_CCS;
638 } else if (has_ccs) {
639 if (want_ccs_e_for_format(devinfo, res->surf.format)) {
640 res->aux.possible_usages |= devinfo->gen < 12 ?
641 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E;
642 } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
643 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
644 }
645 }
646
647 res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
648
649 res->aux.sampler_usages = res->aux.possible_usages;
650
651 /* We don't always support sampling with hiz. But when we do, it must be
652 * single sampled.
653 */
654 if (!devinfo->has_sample_with_hiz || res->surf.samples > 1)
655 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
656
657 /* ISL_AUX_USAGE_HIZ_CCS doesn't support sampling at all */
658 res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS);
659
660 enum isl_aux_state initial_state;
661 assert(!res->aux.bo);
662
663 switch (res->aux.usage) {
664 case ISL_AUX_USAGE_NONE:
665 /* Update relevant fields to indicate that aux is disabled. */
666 iris_resource_disable_aux(res);
667
668 /* Having no aux buffer is only okay if there's no modifier with aux. */
669 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
670 case ISL_AUX_USAGE_HIZ:
671 case ISL_AUX_USAGE_HIZ_CCS:
672 case ISL_AUX_USAGE_HIZ_CCS_WT:
673 initial_state = ISL_AUX_STATE_AUX_INVALID;
674 break;
675 case ISL_AUX_USAGE_MCS:
676 case ISL_AUX_USAGE_MCS_CCS:
677 /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
678 *
679 * "When MCS buffer is enabled and bound to MSRT, it is required
680 * that it is cleared prior to any rendering."
681 *
682 * Since we only use the MCS buffer for rendering, we just clear it
683 * immediately on allocation. The clear value for MCS buffers is all
684 * 1's, so we simply memset it to 0xff.
685 */
686 initial_state = ISL_AUX_STATE_CLEAR;
687 break;
688 case ISL_AUX_USAGE_CCS_D:
689 case ISL_AUX_USAGE_CCS_E:
690 case ISL_AUX_USAGE_GEN12_CCS_E:
691 case ISL_AUX_USAGE_STC_CCS:
692 case ISL_AUX_USAGE_MC:
693 /* When CCS_E is used, we need to ensure that the CCS starts off in
694 * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
695 * Target(s)":
696 *
697 * "If Software wants to enable Color Compression without Fast
698 * clear, Software needs to initialize MCS with zeros."
699 *
700 * A CCS value of 0 indicates that the corresponding block is in the
701 * pass-through state which is what we want.
702 *
703 * For CCS_D, do the same thing. On Gen9+, this avoids having any
704 * undefined bits in the aux buffer.
705 */
706 if (imported) {
707 assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
708 initial_state =
709 isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
710 } else {
711 initial_state = ISL_AUX_STATE_PASS_THROUGH;
712 }
713 break;
714 default:
715 unreachable("Unsupported aux mode");
716 }
717
718 /* Create the aux_state for the auxiliary buffer. */
719 res->aux.state = create_aux_state_map(res, initial_state);
720 if (!res->aux.state)
721 return false;
722
723 if (isl_aux_usage_has_hiz(res->aux.usage)) {
724 for (unsigned level = 0; level < res->surf.levels; ++level) {
725 uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
726 uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
727
728 /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
729 * For LOD == 0, we can grow the dimensions to make it work.
730 */
731 if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
732 res->aux.has_hiz |= 1 << level;
733 }
734 }
735
736 return true;
737 }
738
739 /**
740 * Initialize the aux buffer contents.
741 *
742 * Returns false on unexpected error (e.g. mapping a BO failed).
743 */
744 static bool
iris_resource_init_aux_buf(struct iris_resource * res,unsigned clear_color_state_size)745 iris_resource_init_aux_buf(struct iris_resource *res,
746 unsigned clear_color_state_size)
747 {
748 void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
749
750 if (!map)
751 return false;
752
753 if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) {
754 /* See iris_resource_configure_aux for the memset_value rationale. */
755 uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
756 memset((char*)map + res->aux.offset, memset_value,
757 res->aux.surf.size_B);
758 }
759
760 memset((char*)map + res->aux.extra_aux.offset,
761 0, res->aux.extra_aux.surf.size_B);
762
763 /* Zero the indirect clear color to match ::fast_clear_color. */
764 memset((char *)map + res->aux.clear_color_offset, 0,
765 clear_color_state_size);
766
767 iris_bo_unmap(res->aux.bo);
768
769 if (clear_color_state_size > 0) {
770 res->aux.clear_color_bo = res->aux.bo;
771 iris_bo_reference(res->aux.clear_color_bo);
772 }
773
774 return true;
775 }
776
777 static void
import_aux_info(struct iris_resource * res,const struct iris_resource * aux_res)778 import_aux_info(struct iris_resource *res,
779 const struct iris_resource *aux_res)
780 {
781 assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset);
782 assert(res->bo == aux_res->aux.bo);
783 assert(res->aux.surf.row_pitch_B == aux_res->aux.surf.row_pitch_B);
784 assert(res->bo->size >= aux_res->aux.offset + res->aux.surf.size_B);
785
786 iris_bo_reference(aux_res->aux.bo);
787 res->aux.bo = aux_res->aux.bo;
788 res->aux.offset = aux_res->aux.offset;
789 }
790
791 void
iris_resource_finish_aux_import(struct pipe_screen * pscreen,struct iris_resource * res)792 iris_resource_finish_aux_import(struct pipe_screen *pscreen,
793 struct iris_resource *res)
794 {
795 struct iris_screen *screen = (struct iris_screen *)pscreen;
796 assert(iris_resource_unfinished_aux_import(res));
797 assert(!res->mod_info->supports_clear_color);
798
799 /* Create an array of resources. Combining main and aux planes is easier
800 * with indexing as opposed to scanning the linked list.
801 */
802 struct iris_resource *r[4] = { NULL, };
803 unsigned num_planes = 0;
804 unsigned num_main_planes = 0;
805 for (struct pipe_resource *p_res = &res->base; p_res; p_res = p_res->next) {
806 r[num_planes] = (struct iris_resource *)p_res;
807 num_main_planes += r[num_planes++]->bo != NULL;
808 }
809
810 /* Get an ISL format to use with the aux-map. */
811 enum isl_format format;
812 switch (res->external_format) {
813 case PIPE_FORMAT_NV12: format = ISL_FORMAT_PLANAR_420_8; break;
814 case PIPE_FORMAT_P010: format = ISL_FORMAT_PLANAR_420_10; break;
815 case PIPE_FORMAT_P012: format = ISL_FORMAT_PLANAR_420_12; break;
816 case PIPE_FORMAT_P016: format = ISL_FORMAT_PLANAR_420_16; break;
817 case PIPE_FORMAT_YUYV: format = ISL_FORMAT_YCRCB_NORMAL; break;
818 case PIPE_FORMAT_UYVY: format = ISL_FORMAT_YCRCB_SWAPY; break;
819 default: format = res->surf.format; break;
820 }
821
822 /* Combine main and aux plane information. */
823 if (num_main_planes == 1 && num_planes == 2) {
824 import_aux_info(r[0], r[1]);
825 map_aux_addresses(screen, r[0], format, 0);
826 } else if (num_main_planes == 2 && num_planes == 4) {
827 import_aux_info(r[0], r[2]);
828 import_aux_info(r[1], r[3]);
829 map_aux_addresses(screen, r[0], format, 0);
830 map_aux_addresses(screen, r[1], format, 1);
831 } else {
832 /* Gallium has lowered a single main plane into two. */
833 assert(num_main_planes == 2 && num_planes == 3);
834 assert(isl_format_is_yuv(format) && !isl_format_is_planar(format));
835 import_aux_info(r[0], r[2]);
836 import_aux_info(r[1], r[2]);
837 map_aux_addresses(screen, r[0], format, 0);
838 }
839
840 /* Add on a clear color BO. */
841 assert(res->aux.clear_color_bo == NULL);
842 unsigned clear_color_state_size =
843 iris_get_aux_clear_color_state_size(screen);
844
845 if (clear_color_state_size > 0) {
846 res->aux.clear_color_bo =
847 iris_bo_alloc_tiled(screen->bufmgr, "clear color_buffer",
848 clear_color_state_size, 1, IRIS_MEMZONE_OTHER,
849 I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
850 }
851 }
852
853 static struct pipe_resource *
iris_resource_create_for_buffer(struct pipe_screen * pscreen,const struct pipe_resource * templ)854 iris_resource_create_for_buffer(struct pipe_screen *pscreen,
855 const struct pipe_resource *templ)
856 {
857 struct iris_screen *screen = (struct iris_screen *)pscreen;
858 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
859
860 assert(templ->target == PIPE_BUFFER);
861 assert(templ->height0 <= 1);
862 assert(templ->depth0 <= 1);
863 assert(templ->format == PIPE_FORMAT_NONE ||
864 util_format_get_blocksize(templ->format) == 1);
865
866 res->internal_format = templ->format;
867 res->surf.tiling = ISL_TILING_LINEAR;
868
869 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
870 const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
871 if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
872 memzone = IRIS_MEMZONE_SHADER;
873 name = "shader kernels";
874 } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
875 memzone = IRIS_MEMZONE_SURFACE;
876 name = "surface state";
877 } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
878 memzone = IRIS_MEMZONE_DYNAMIC;
879 name = "dynamic state";
880 }
881
882 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
883 if (!res->bo) {
884 iris_resource_destroy(pscreen, &res->base);
885 return NULL;
886 }
887
888 if (templ->bind & PIPE_BIND_SHARED)
889 iris_bo_make_external(res->bo);
890
891 return &res->base;
892 }
893
894 static struct pipe_resource *
iris_resource_create_with_modifiers(struct pipe_screen * pscreen,const struct pipe_resource * templ,const uint64_t * modifiers,int modifiers_count)895 iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
896 const struct pipe_resource *templ,
897 const uint64_t *modifiers,
898 int modifiers_count)
899 {
900 struct iris_screen *screen = (struct iris_screen *)pscreen;
901 struct gen_device_info *devinfo = &screen->devinfo;
902 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
903
904 if (!res)
905 return NULL;
906
907 uint64_t modifier =
908 select_best_modifier(devinfo, templ->format, modifiers, modifiers_count);
909
910 if (modifier == DRM_FORMAT_MOD_INVALID && modifiers_count > 0) {
911 fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
912 goto fail;
913 }
914
915 UNUSED const bool isl_surf_created_successfully =
916 iris_resource_configure_main(screen, res, templ, modifier, 0);
917 assert(isl_surf_created_successfully);
918
919 const char *name = "miptree";
920 enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
921
922 unsigned int flags = 0;
923 if (templ->usage == PIPE_USAGE_STAGING)
924 flags |= BO_ALLOC_COHERENT;
925
926 /* These are for u_upload_mgr buffers only */
927 assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
928 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
929 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
930
931 if (!iris_resource_configure_aux(screen, res, false))
932 goto fail;
933
934 /* Modifiers require the aux data to be in the same buffer as the main
935 * surface, but we combine them even when a modifier is not being used.
936 */
937 uint64_t bo_size = res->surf.size_B;
938
939 /* Allocate space for the aux buffer. */
940 if (res->aux.surf.size_B > 0) {
941 res->aux.offset = ALIGN(bo_size, res->aux.surf.alignment_B);
942 bo_size = res->aux.offset + res->aux.surf.size_B;
943 }
944
945 /* Allocate space for the extra aux buffer. */
946 if (res->aux.extra_aux.surf.size_B > 0) {
947 res->aux.extra_aux.offset =
948 ALIGN(bo_size, res->aux.extra_aux.surf.alignment_B);
949 bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
950 }
951
952 /* Allocate space for the indirect clear color.
953 *
954 * Also add some padding to make sure the fast clear color state buffer
955 * starts at a 4K alignment. We believe that 256B might be enough, but due
956 * to lack of testing we will leave this as 4K for now.
957 */
958 if (res->aux.surf.size_B > 0) {
959 res->aux.clear_color_offset = ALIGN(bo_size, 4096);
960 bo_size = res->aux.clear_color_offset +
961 iris_get_aux_clear_color_state_size(screen);
962 }
963
964 uint32_t alignment = MAX2(4096, res->surf.alignment_B);
965 res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment,
966 memzone,
967 isl_tiling_to_i915_tiling(res->surf.tiling),
968 res->surf.row_pitch_B, flags);
969
970 if (!res->bo)
971 goto fail;
972
973 if (res->aux.surf.size_B > 0) {
974 res->aux.bo = res->bo;
975 iris_bo_reference(res->aux.bo);
976 unsigned clear_color_state_size =
977 iris_get_aux_clear_color_state_size(screen);
978 if (!iris_resource_init_aux_buf(res, clear_color_state_size))
979 goto fail;
980 map_aux_addresses(screen, res, res->surf.format, 0);
981 }
982
983 if (templ->bind & PIPE_BIND_SHARED)
984 iris_bo_make_external(res->bo);
985
986 return &res->base;
987
988 fail:
989 fprintf(stderr, "XXX: resource creation failed\n");
990 iris_resource_destroy(pscreen, &res->base);
991 return NULL;
992
993 }
994
995 static struct pipe_resource *
iris_resource_create(struct pipe_screen * pscreen,const struct pipe_resource * templ)996 iris_resource_create(struct pipe_screen *pscreen,
997 const struct pipe_resource *templ)
998 {
999 if (templ->target == PIPE_BUFFER)
1000 return iris_resource_create_for_buffer(pscreen, templ);
1001 else
1002 return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
1003 }
1004
1005 static uint64_t
tiling_to_modifier(uint32_t tiling)1006 tiling_to_modifier(uint32_t tiling)
1007 {
1008 static const uint64_t map[] = {
1009 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
1010 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
1011 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
1012 };
1013
1014 assert(tiling < ARRAY_SIZE(map));
1015
1016 return map[tiling];
1017 }
1018
1019 static struct pipe_resource *
iris_resource_from_user_memory(struct pipe_screen * pscreen,const struct pipe_resource * templ,void * user_memory)1020 iris_resource_from_user_memory(struct pipe_screen *pscreen,
1021 const struct pipe_resource *templ,
1022 void *user_memory)
1023 {
1024 struct iris_screen *screen = (struct iris_screen *)pscreen;
1025 struct iris_bufmgr *bufmgr = screen->bufmgr;
1026 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1027 if (!res)
1028 return NULL;
1029
1030 assert(templ->target == PIPE_BUFFER);
1031
1032 res->internal_format = templ->format;
1033 res->bo = iris_bo_create_userptr(bufmgr, "user",
1034 user_memory, templ->width0,
1035 IRIS_MEMZONE_OTHER);
1036 if (!res->bo) {
1037 iris_resource_destroy(pscreen, &res->base);
1038 return NULL;
1039 }
1040
1041 util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0);
1042
1043 return &res->base;
1044 }
1045
1046 static struct pipe_resource *
iris_resource_from_handle(struct pipe_screen * pscreen,const struct pipe_resource * templ,struct winsys_handle * whandle,unsigned usage)1047 iris_resource_from_handle(struct pipe_screen *pscreen,
1048 const struct pipe_resource *templ,
1049 struct winsys_handle *whandle,
1050 unsigned usage)
1051 {
1052 assert(templ->target != PIPE_BUFFER);
1053
1054 struct iris_screen *screen = (struct iris_screen *)pscreen;
1055 struct iris_bufmgr *bufmgr = screen->bufmgr;
1056 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1057 if (!res)
1058 return NULL;
1059
1060 switch (whandle->type) {
1061 case WINSYS_HANDLE_TYPE_FD:
1062 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle,
1063 whandle->modifier);
1064 break;
1065 case WINSYS_HANDLE_TYPE_SHARED:
1066 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
1067 whandle->handle);
1068 break;
1069 default:
1070 unreachable("invalid winsys handle type");
1071 }
1072 if (!res->bo)
1073 goto fail;
1074
1075 res->offset = whandle->offset;
1076 res->external_format = whandle->format;
1077
1078 /* Create a surface for each plane specified by the external format. */
1079 if (whandle->plane < util_format_get_num_planes(whandle->format)) {
1080
1081 const uint64_t modifier =
1082 whandle->modifier != DRM_FORMAT_MOD_INVALID ?
1083 whandle->modifier : tiling_to_modifier(res->bo->tiling_mode);
1084
1085 UNUSED const bool isl_surf_created_successfully =
1086 iris_resource_configure_main(screen, res, templ, modifier,
1087 whandle->stride);
1088 assert(isl_surf_created_successfully);
1089 assert(res->bo->tiling_mode ==
1090 isl_tiling_to_i915_tiling(res->surf.tiling));
1091
1092 UNUSED const bool ok = iris_resource_configure_aux(screen, res, true);
1093 assert(ok);
1094 /* The gallium dri layer will create a separate plane resource for the
1095 * aux image. iris_resource_finish_aux_import will merge the separate aux
1096 * parameters back into a single iris_resource.
1097 */
1098 } else {
1099 /* Save modifier import information to reconstruct later. After import,
1100 * this will be available under a second image accessible from the main
1101 * image with res->base.next. See iris_resource_finish_aux_import.
1102 */
1103 res->aux.surf.row_pitch_B = whandle->stride;
1104 res->aux.offset = whandle->offset;
1105 res->aux.bo = res->bo;
1106 res->bo = NULL;
1107 }
1108
1109 return &res->base;
1110
1111 fail:
1112 iris_resource_destroy(pscreen, &res->base);
1113 return NULL;
1114 }
1115
1116 static void
iris_flush_resource(struct pipe_context * ctx,struct pipe_resource * resource)1117 iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
1118 {
1119 struct iris_context *ice = (struct iris_context *)ctx;
1120 struct iris_resource *res = (void *) resource;
1121 const struct isl_drm_modifier_info *mod = res->mod_info;
1122
1123 iris_resource_prepare_access(ice, res,
1124 0, INTEL_REMAINING_LEVELS,
1125 0, INTEL_REMAINING_LAYERS,
1126 mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
1127 mod ? mod->supports_clear_color : false);
1128 }
1129
1130 static void
iris_resource_disable_aux_on_first_query(struct pipe_resource * resource,unsigned usage)1131 iris_resource_disable_aux_on_first_query(struct pipe_resource *resource,
1132 unsigned usage)
1133 {
1134 struct iris_resource *res = (struct iris_resource *)resource;
1135 bool mod_with_aux =
1136 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1137
1138 /* Disable aux usage if explicit flush not set and this is the first time
1139 * we are dealing with this resource and the resource was not created with
1140 * a modifier with aux.
1141 */
1142 if (!mod_with_aux &&
1143 (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
1144 p_atomic_read(&resource->reference.count) == 1) {
1145 iris_resource_disable_aux(res);
1146 }
1147 }
1148
1149 static bool
iris_resource_get_param(struct pipe_screen * pscreen,struct pipe_context * context,struct pipe_resource * resource,unsigned plane,unsigned layer,unsigned level,enum pipe_resource_param param,unsigned handle_usage,uint64_t * value)1150 iris_resource_get_param(struct pipe_screen *pscreen,
1151 struct pipe_context *context,
1152 struct pipe_resource *resource,
1153 unsigned plane,
1154 unsigned layer,
1155 unsigned level,
1156 enum pipe_resource_param param,
1157 unsigned handle_usage,
1158 uint64_t *value)
1159 {
1160 struct iris_screen *screen = (struct iris_screen *)pscreen;
1161 struct iris_resource *res = (struct iris_resource *)resource;
1162 bool mod_with_aux =
1163 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1164 bool wants_aux = mod_with_aux && plane > 0;
1165 bool result;
1166 unsigned handle;
1167
1168 if (iris_resource_unfinished_aux_import(res))
1169 iris_resource_finish_aux_import(pscreen, res);
1170
1171 struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo;
1172
1173 iris_resource_disable_aux_on_first_query(resource, handle_usage);
1174
1175 switch (param) {
1176 case PIPE_RESOURCE_PARAM_NPLANES:
1177 if (mod_with_aux) {
1178 *value = 2 * util_format_get_num_planes(res->external_format);
1179 } else {
1180 unsigned count = 0;
1181 for (struct pipe_resource *cur = resource; cur; cur = cur->next)
1182 count++;
1183 *value = count;
1184 }
1185 return true;
1186 case PIPE_RESOURCE_PARAM_STRIDE:
1187 *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
1188 return true;
1189 case PIPE_RESOURCE_PARAM_OFFSET:
1190 *value = wants_aux ? res->aux.offset : 0;
1191 return true;
1192 case PIPE_RESOURCE_PARAM_MODIFIER:
1193 *value = res->mod_info ? res->mod_info->modifier :
1194 tiling_to_modifier(res->bo->tiling_mode);
1195 return true;
1196 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
1197 result = iris_bo_flink(bo, &handle) == 0;
1198 if (result)
1199 *value = handle;
1200 return result;
1201 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: {
1202 /* Because we share the same drm file across multiple iris_screen, when
1203 * we export a GEM handle we must make sure it is valid in the DRM file
1204 * descriptor the caller is using (this is the FD given at screen
1205 * creation).
1206 */
1207 uint32_t handle;
1208 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1209 return false;
1210 *value = handle;
1211 return true;
1212 }
1213
1214 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
1215 result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0;
1216 if (result)
1217 *value = handle;
1218 return result;
1219 default:
1220 return false;
1221 }
1222 }
1223
1224 static bool
iris_resource_get_handle(struct pipe_screen * pscreen,struct pipe_context * ctx,struct pipe_resource * resource,struct winsys_handle * whandle,unsigned usage)1225 iris_resource_get_handle(struct pipe_screen *pscreen,
1226 struct pipe_context *ctx,
1227 struct pipe_resource *resource,
1228 struct winsys_handle *whandle,
1229 unsigned usage)
1230 {
1231 struct iris_screen *screen = (struct iris_screen *) pscreen;
1232 struct iris_resource *res = (struct iris_resource *)resource;
1233 bool mod_with_aux =
1234 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1235
1236 iris_resource_disable_aux_on_first_query(resource, usage);
1237
1238 struct iris_bo *bo;
1239 if (mod_with_aux && whandle->plane > 0) {
1240 assert(res->aux.bo);
1241 bo = res->aux.bo;
1242 whandle->stride = res->aux.surf.row_pitch_B;
1243 whandle->offset = res->aux.offset;
1244 } else {
1245 /* If this is a buffer, stride should be 0 - no need to special case */
1246 whandle->stride = res->surf.row_pitch_B;
1247 bo = res->bo;
1248 }
1249
1250 whandle->format = res->external_format;
1251 whandle->modifier =
1252 res->mod_info ? res->mod_info->modifier
1253 : tiling_to_modifier(res->bo->tiling_mode);
1254
1255 #ifndef NDEBUG
1256 enum isl_aux_usage allowed_usage =
1257 usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH ? res->aux.usage :
1258 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
1259
1260 if (res->aux.usage != allowed_usage) {
1261 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
1262 assert(aux_state == ISL_AUX_STATE_RESOLVED ||
1263 aux_state == ISL_AUX_STATE_PASS_THROUGH);
1264 }
1265 #endif
1266
1267 switch (whandle->type) {
1268 case WINSYS_HANDLE_TYPE_SHARED:
1269 return iris_bo_flink(bo, &whandle->handle) == 0;
1270 case WINSYS_HANDLE_TYPE_KMS: {
1271 /* Because we share the same drm file across multiple iris_screen, when
1272 * we export a GEM handle we must make sure it is valid in the DRM file
1273 * descriptor the caller is using (this is the FD given at screen
1274 * creation).
1275 */
1276 uint32_t handle;
1277 if (iris_bo_export_gem_handle_for_device(bo, screen->winsys_fd, &handle))
1278 return false;
1279 whandle->handle = handle;
1280 return true;
1281 }
1282 case WINSYS_HANDLE_TYPE_FD:
1283 return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0;
1284 }
1285
1286 return false;
1287 }
1288
1289 static bool
resource_is_busy(struct iris_context * ice,struct iris_resource * res)1290 resource_is_busy(struct iris_context *ice,
1291 struct iris_resource *res)
1292 {
1293 bool busy = iris_bo_busy(res->bo);
1294
1295 for (int i = 0; i < IRIS_BATCH_COUNT; i++)
1296 busy |= iris_batch_references(&ice->batches[i], res->bo);
1297
1298 return busy;
1299 }
1300
1301 static void
iris_invalidate_resource(struct pipe_context * ctx,struct pipe_resource * resource)1302 iris_invalidate_resource(struct pipe_context *ctx,
1303 struct pipe_resource *resource)
1304 {
1305 struct iris_screen *screen = (void *) ctx->screen;
1306 struct iris_context *ice = (void *) ctx;
1307 struct iris_resource *res = (void *) resource;
1308
1309 if (resource->target != PIPE_BUFFER)
1310 return;
1311
1312 /* If it's already invalidated, don't bother doing anything. */
1313 if (res->valid_buffer_range.start > res->valid_buffer_range.end)
1314 return;
1315
1316 if (!resource_is_busy(ice, res)) {
1317 /* The resource is idle, so just mark that it contains no data and
1318 * keep using the same underlying buffer object.
1319 */
1320 util_range_set_empty(&res->valid_buffer_range);
1321 return;
1322 }
1323
1324 /* Otherwise, try and replace the backing storage with a new BO. */
1325
1326 /* We can't reallocate memory we didn't allocate in the first place. */
1327 if (res->bo->userptr)
1328 return;
1329
1330 // XXX: We should support this.
1331 if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
1332 return;
1333
1334 struct iris_bo *old_bo = res->bo;
1335 struct iris_bo *new_bo =
1336 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
1337 iris_memzone_for_address(old_bo->gtt_offset));
1338 if (!new_bo)
1339 return;
1340
1341 /* Swap out the backing storage */
1342 res->bo = new_bo;
1343
1344 /* Rebind the buffer, replacing any state referring to the old BO's
1345 * address, and marking state dirty so it's reemitted.
1346 */
1347 screen->vtbl.rebind_buffer(ice, res);
1348
1349 util_range_set_empty(&res->valid_buffer_range);
1350
1351 iris_bo_unreference(old_bo);
1352 }
1353
1354 static void
iris_flush_staging_region(struct pipe_transfer * xfer,const struct pipe_box * flush_box)1355 iris_flush_staging_region(struct pipe_transfer *xfer,
1356 const struct pipe_box *flush_box)
1357 {
1358 if (!(xfer->usage & PIPE_MAP_WRITE))
1359 return;
1360
1361 struct iris_transfer *map = (void *) xfer;
1362
1363 struct pipe_box src_box = *flush_box;
1364
1365 /* Account for extra alignment padding in staging buffer */
1366 if (xfer->resource->target == PIPE_BUFFER)
1367 src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
1368
1369 struct pipe_box dst_box = (struct pipe_box) {
1370 .x = xfer->box.x + flush_box->x,
1371 .y = xfer->box.y + flush_box->y,
1372 .z = xfer->box.z + flush_box->z,
1373 .width = flush_box->width,
1374 .height = flush_box->height,
1375 .depth = flush_box->depth,
1376 };
1377
1378 iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
1379 dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
1380 &src_box);
1381 }
1382
1383 static void
iris_unmap_copy_region(struct iris_transfer * map)1384 iris_unmap_copy_region(struct iris_transfer *map)
1385 {
1386 iris_resource_destroy(map->staging->screen, map->staging);
1387
1388 map->ptr = NULL;
1389 }
1390
1391 static void
iris_map_copy_region(struct iris_transfer * map)1392 iris_map_copy_region(struct iris_transfer *map)
1393 {
1394 struct pipe_screen *pscreen = &map->batch->screen->base;
1395 struct pipe_transfer *xfer = &map->base;
1396 struct pipe_box *box = &xfer->box;
1397 struct iris_resource *res = (void *) xfer->resource;
1398
1399 unsigned extra = xfer->resource->target == PIPE_BUFFER ?
1400 box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
1401
1402 struct pipe_resource templ = (struct pipe_resource) {
1403 .usage = PIPE_USAGE_STAGING,
1404 .width0 = box->width + extra,
1405 .height0 = box->height,
1406 .depth0 = 1,
1407 .nr_samples = xfer->resource->nr_samples,
1408 .nr_storage_samples = xfer->resource->nr_storage_samples,
1409 .array_size = box->depth,
1410 .format = res->internal_format,
1411 };
1412
1413 if (xfer->resource->target == PIPE_BUFFER)
1414 templ.target = PIPE_BUFFER;
1415 else if (templ.array_size > 1)
1416 templ.target = PIPE_TEXTURE_2D_ARRAY;
1417 else
1418 templ.target = PIPE_TEXTURE_2D;
1419
1420 map->staging = iris_resource_create(pscreen, &templ);
1421 assert(map->staging);
1422
1423 if (templ.target != PIPE_BUFFER) {
1424 struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
1425 xfer->stride = isl_surf_get_row_pitch_B(surf);
1426 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1427 }
1428
1429 if (!(xfer->usage & PIPE_MAP_DISCARD_RANGE)) {
1430 iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
1431 xfer->resource, xfer->level, box);
1432 /* Ensure writes to the staging BO land before we map it below. */
1433 iris_emit_pipe_control_flush(map->batch,
1434 "transfer read: flush before mapping",
1435 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1436 PIPE_CONTROL_CS_STALL);
1437 }
1438
1439 struct iris_bo *staging_bo = iris_resource_bo(map->staging);
1440
1441 if (iris_batch_references(map->batch, staging_bo))
1442 iris_batch_flush(map->batch);
1443
1444 map->ptr =
1445 iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
1446
1447 map->unmap = iris_unmap_copy_region;
1448 }
1449
1450 static void
get_image_offset_el(const struct isl_surf * surf,unsigned level,unsigned z,unsigned * out_x0_el,unsigned * out_y0_el)1451 get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z,
1452 unsigned *out_x0_el, unsigned *out_y0_el)
1453 {
1454 if (surf->dim == ISL_SURF_DIM_3D) {
1455 isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
1456 } else {
1457 isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
1458 }
1459 }
1460
1461 /**
1462 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1463 * different tiling patterns.
1464 */
1465 static void
iris_resource_get_tile_dims(enum isl_tiling tiling,uint32_t cpp,uint32_t * tile_w,uint32_t * tile_h)1466 iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
1467 uint32_t *tile_w, uint32_t *tile_h)
1468 {
1469 switch (tiling) {
1470 case ISL_TILING_X:
1471 *tile_w = 512;
1472 *tile_h = 8;
1473 break;
1474 case ISL_TILING_Y0:
1475 *tile_w = 128;
1476 *tile_h = 32;
1477 break;
1478 case ISL_TILING_LINEAR:
1479 *tile_w = cpp;
1480 *tile_h = 1;
1481 break;
1482 default:
1483 unreachable("not reached");
1484 }
1485
1486 }
1487
1488 /**
1489 * This function computes masks that may be used to select the bits of the X
1490 * and Y coordinates that indicate the offset within a tile. If the BO is
1491 * untiled, the masks are set to 0.
1492 */
1493 static void
iris_resource_get_tile_masks(enum isl_tiling tiling,uint32_t cpp,uint32_t * mask_x,uint32_t * mask_y)1494 iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
1495 uint32_t *mask_x, uint32_t *mask_y)
1496 {
1497 uint32_t tile_w_bytes, tile_h;
1498
1499 iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
1500
1501 *mask_x = tile_w_bytes / cpp - 1;
1502 *mask_y = tile_h - 1;
1503 }
1504
1505 /**
1506 * Compute the offset (in bytes) from the start of the BO to the given x
1507 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1508 * multiples of the tile size.
1509 */
1510 static uint32_t
iris_resource_get_aligned_offset(const struct iris_resource * res,uint32_t x,uint32_t y)1511 iris_resource_get_aligned_offset(const struct iris_resource *res,
1512 uint32_t x, uint32_t y)
1513 {
1514 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1515 unsigned cpp = fmtl->bpb / 8;
1516 uint32_t pitch = res->surf.row_pitch_B;
1517
1518 switch (res->surf.tiling) {
1519 default:
1520 unreachable("not reached");
1521 case ISL_TILING_LINEAR:
1522 return y * pitch + x * cpp;
1523 case ISL_TILING_X:
1524 assert((x % (512 / cpp)) == 0);
1525 assert((y % 8) == 0);
1526 return y * pitch + x / (512 / cpp) * 4096;
1527 case ISL_TILING_Y0:
1528 assert((x % (128 / cpp)) == 0);
1529 assert((y % 32) == 0);
1530 return y * pitch + x / (128 / cpp) * 4096;
1531 }
1532 }
1533
1534 /**
1535 * Rendering with tiled buffers requires that the base address of the buffer
1536 * be aligned to a page boundary. For renderbuffers, and sometimes with
1537 * textures, we may want the surface to point at a texture image level that
1538 * isn't at a page boundary.
1539 *
1540 * This function returns an appropriately-aligned base offset
1541 * according to the tiling restrictions, plus any required x/y offset
1542 * from there.
1543 */
1544 uint32_t
iris_resource_get_tile_offsets(const struct iris_resource * res,uint32_t level,uint32_t z,uint32_t * tile_x,uint32_t * tile_y)1545 iris_resource_get_tile_offsets(const struct iris_resource *res,
1546 uint32_t level, uint32_t z,
1547 uint32_t *tile_x, uint32_t *tile_y)
1548 {
1549 uint32_t x, y;
1550 uint32_t mask_x, mask_y;
1551
1552 const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format);
1553 const unsigned cpp = fmtl->bpb / 8;
1554
1555 iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y);
1556 get_image_offset_el(&res->surf, level, z, &x, &y);
1557
1558 *tile_x = x & mask_x;
1559 *tile_y = y & mask_y;
1560
1561 return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y);
1562 }
1563
1564 /**
1565 * Get pointer offset into stencil buffer.
1566 *
1567 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1568 * must decode the tile's layout in software.
1569 *
1570 * See
1571 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1572 * Format.
1573 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1574 *
1575 * Even though the returned offset is always positive, the return type is
1576 * signed due to
1577 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1578 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1579 */
1580 static intptr_t
s8_offset(uint32_t stride,uint32_t x,uint32_t y)1581 s8_offset(uint32_t stride, uint32_t x, uint32_t y)
1582 {
1583 uint32_t tile_size = 4096;
1584 uint32_t tile_width = 64;
1585 uint32_t tile_height = 64;
1586 uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
1587
1588 uint32_t tile_x = x / tile_width;
1589 uint32_t tile_y = y / tile_height;
1590
1591 /* The byte's address relative to the tile's base addres. */
1592 uint32_t byte_x = x % tile_width;
1593 uint32_t byte_y = y % tile_height;
1594
1595 uintptr_t u = tile_y * row_size
1596 + tile_x * tile_size
1597 + 512 * (byte_x / 8)
1598 + 64 * (byte_y / 8)
1599 + 32 * ((byte_y / 4) % 2)
1600 + 16 * ((byte_x / 4) % 2)
1601 + 8 * ((byte_y / 2) % 2)
1602 + 4 * ((byte_x / 2) % 2)
1603 + 2 * (byte_y % 2)
1604 + 1 * (byte_x % 2);
1605
1606 return u;
1607 }
1608
1609 static void
iris_unmap_s8(struct iris_transfer * map)1610 iris_unmap_s8(struct iris_transfer *map)
1611 {
1612 struct pipe_transfer *xfer = &map->base;
1613 const struct pipe_box *box = &xfer->box;
1614 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1615 struct isl_surf *surf = &res->surf;
1616
1617 if (xfer->usage & PIPE_MAP_WRITE) {
1618 uint8_t *untiled_s8_map = map->ptr;
1619 uint8_t *tiled_s8_map =
1620 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1621
1622 for (int s = 0; s < box->depth; s++) {
1623 unsigned x0_el, y0_el;
1624 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1625
1626 for (uint32_t y = 0; y < box->height; y++) {
1627 for (uint32_t x = 0; x < box->width; x++) {
1628 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1629 x0_el + box->x + x,
1630 y0_el + box->y + y);
1631 tiled_s8_map[offset] =
1632 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
1633 }
1634 }
1635 }
1636 }
1637
1638 free(map->buffer);
1639 }
1640
1641 static void
iris_map_s8(struct iris_transfer * map)1642 iris_map_s8(struct iris_transfer *map)
1643 {
1644 struct pipe_transfer *xfer = &map->base;
1645 const struct pipe_box *box = &xfer->box;
1646 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1647 struct isl_surf *surf = &res->surf;
1648
1649 xfer->stride = surf->row_pitch_B;
1650 xfer->layer_stride = xfer->stride * box->height;
1651
1652 /* The tiling and detiling functions require that the linear buffer has
1653 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1654 * over-allocate the linear buffer to get the proper alignment.
1655 */
1656 map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
1657 assert(map->buffer);
1658
1659 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1660 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1661 * invalidate is set, since we'll be writing the whole rectangle from our
1662 * temporary buffer back out.
1663 */
1664 if (!(xfer->usage & PIPE_MAP_DISCARD_RANGE)) {
1665 uint8_t *untiled_s8_map = map->ptr;
1666 uint8_t *tiled_s8_map =
1667 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1668
1669 for (int s = 0; s < box->depth; s++) {
1670 unsigned x0_el, y0_el;
1671 get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
1672
1673 for (uint32_t y = 0; y < box->height; y++) {
1674 for (uint32_t x = 0; x < box->width; x++) {
1675 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
1676 x0_el + box->x + x,
1677 y0_el + box->y + y);
1678 untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
1679 tiled_s8_map[offset];
1680 }
1681 }
1682 }
1683 }
1684
1685 map->unmap = iris_unmap_s8;
1686 }
1687
1688 /* Compute extent parameters for use with tiled_memcpy functions.
1689 * xs are in units of bytes and ys are in units of strides.
1690 */
1691 static inline void
tile_extents(const struct isl_surf * surf,const struct pipe_box * box,unsigned level,int z,unsigned * x1_B,unsigned * x2_B,unsigned * y1_el,unsigned * y2_el)1692 tile_extents(const struct isl_surf *surf,
1693 const struct pipe_box *box,
1694 unsigned level, int z,
1695 unsigned *x1_B, unsigned *x2_B,
1696 unsigned *y1_el, unsigned *y2_el)
1697 {
1698 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1699 const unsigned cpp = fmtl->bpb / 8;
1700
1701 assert(box->x % fmtl->bw == 0);
1702 assert(box->y % fmtl->bh == 0);
1703
1704 unsigned x0_el, y0_el;
1705 get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
1706
1707 *x1_B = (box->x / fmtl->bw + x0_el) * cpp;
1708 *y1_el = box->y / fmtl->bh + y0_el;
1709 *x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
1710 *y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
1711 }
1712
1713 static void
iris_unmap_tiled_memcpy(struct iris_transfer * map)1714 iris_unmap_tiled_memcpy(struct iris_transfer *map)
1715 {
1716 struct pipe_transfer *xfer = &map->base;
1717 const struct pipe_box *box = &xfer->box;
1718 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1719 struct isl_surf *surf = &res->surf;
1720
1721 const bool has_swizzling = false;
1722
1723 if (xfer->usage & PIPE_MAP_WRITE) {
1724 char *dst =
1725 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1726
1727 for (int s = 0; s < box->depth; s++) {
1728 unsigned x1, x2, y1, y2;
1729 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1730
1731 void *ptr = map->ptr + s * xfer->layer_stride;
1732
1733 isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
1734 surf->row_pitch_B, xfer->stride,
1735 has_swizzling, surf->tiling, ISL_MEMCPY);
1736 }
1737 }
1738 os_free_aligned(map->buffer);
1739 map->buffer = map->ptr = NULL;
1740 }
1741
1742 static void
iris_map_tiled_memcpy(struct iris_transfer * map)1743 iris_map_tiled_memcpy(struct iris_transfer *map)
1744 {
1745 struct pipe_transfer *xfer = &map->base;
1746 const struct pipe_box *box = &xfer->box;
1747 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1748 struct isl_surf *surf = &res->surf;
1749
1750 xfer->stride = ALIGN(surf->row_pitch_B, 16);
1751 xfer->layer_stride = xfer->stride * box->height;
1752
1753 unsigned x1, x2, y1, y2;
1754 tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
1755
1756 /* The tiling and detiling functions require that the linear buffer has
1757 * a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
1758 * over-allocate the linear buffer to get the proper alignment.
1759 */
1760 map->buffer =
1761 os_malloc_aligned(xfer->layer_stride * box->depth, 16);
1762 assert(map->buffer);
1763 map->ptr = (char *)map->buffer + (x1 & 0xf);
1764
1765 const bool has_swizzling = false;
1766
1767 if (!(xfer->usage & PIPE_MAP_DISCARD_RANGE)) {
1768 char *src =
1769 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
1770
1771 for (int s = 0; s < box->depth; s++) {
1772 unsigned x1, x2, y1, y2;
1773 tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
1774
1775 /* Use 's' rather than 'box->z' to rebase the first slice to 0. */
1776 void *ptr = map->ptr + s * xfer->layer_stride;
1777
1778 isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
1779 surf->row_pitch_B, has_swizzling,
1780 surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
1781 }
1782 }
1783
1784 map->unmap = iris_unmap_tiled_memcpy;
1785 }
1786
1787 static void
iris_map_direct(struct iris_transfer * map)1788 iris_map_direct(struct iris_transfer *map)
1789 {
1790 struct pipe_transfer *xfer = &map->base;
1791 struct pipe_box *box = &xfer->box;
1792 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1793
1794 void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
1795
1796 if (res->base.target == PIPE_BUFFER) {
1797 xfer->stride = 0;
1798 xfer->layer_stride = 0;
1799
1800 map->ptr = ptr + box->x;
1801 } else {
1802 struct isl_surf *surf = &res->surf;
1803 const struct isl_format_layout *fmtl =
1804 isl_format_get_layout(surf->format);
1805 const unsigned cpp = fmtl->bpb / 8;
1806 unsigned x0_el, y0_el;
1807
1808 get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
1809
1810 xfer->stride = isl_surf_get_row_pitch_B(surf);
1811 xfer->layer_stride = isl_surf_get_array_pitch(surf);
1812
1813 map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
1814 }
1815 }
1816
1817 static bool
can_promote_to_async(const struct iris_resource * res,const struct pipe_box * box,enum pipe_map_flags usage)1818 can_promote_to_async(const struct iris_resource *res,
1819 const struct pipe_box *box,
1820 enum pipe_map_flags usage)
1821 {
1822 /* If we're writing to a section of the buffer that hasn't even been
1823 * initialized with useful data, then we can safely promote this write
1824 * to be unsynchronized. This helps the common pattern of appending data.
1825 */
1826 return res->base.target == PIPE_BUFFER && (usage & PIPE_MAP_WRITE) &&
1827 !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) &&
1828 !util_ranges_intersect(&res->valid_buffer_range, box->x,
1829 box->x + box->width);
1830 }
1831
1832 static void *
iris_transfer_map(struct pipe_context * ctx,struct pipe_resource * resource,unsigned level,enum pipe_map_flags usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer)1833 iris_transfer_map(struct pipe_context *ctx,
1834 struct pipe_resource *resource,
1835 unsigned level,
1836 enum pipe_map_flags usage,
1837 const struct pipe_box *box,
1838 struct pipe_transfer **ptransfer)
1839 {
1840 struct iris_context *ice = (struct iris_context *)ctx;
1841 struct iris_resource *res = (struct iris_resource *)resource;
1842 struct isl_surf *surf = &res->surf;
1843
1844 if (iris_resource_unfinished_aux_import(res))
1845 iris_resource_finish_aux_import(ctx->screen, res);
1846
1847 if (usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE) {
1848 /* Replace the backing storage with a fresh buffer for non-async maps */
1849 if (!(usage & (PIPE_MAP_UNSYNCHRONIZED |
1850 TC_TRANSFER_MAP_NO_INVALIDATE)))
1851 iris_invalidate_resource(ctx, resource);
1852
1853 /* If we can discard the whole resource, we can discard the range. */
1854 usage |= PIPE_MAP_DISCARD_RANGE;
1855 }
1856
1857 if (!(usage & PIPE_MAP_UNSYNCHRONIZED) &&
1858 can_promote_to_async(res, box, usage)) {
1859 usage |= PIPE_MAP_UNSYNCHRONIZED;
1860 }
1861
1862 bool map_would_stall = false;
1863
1864 if (!(usage & PIPE_MAP_UNSYNCHRONIZED)) {
1865 map_would_stall =
1866 resource_is_busy(ice, res) ||
1867 iris_has_invalid_primary(res, level, 1, box->z, box->depth);
1868
1869 if (map_would_stall && (usage & PIPE_MAP_DONTBLOCK) &&
1870 (usage & PIPE_MAP_DIRECTLY))
1871 return NULL;
1872 }
1873
1874 if (surf->tiling != ISL_TILING_LINEAR &&
1875 (usage & PIPE_MAP_DIRECTLY))
1876 return NULL;
1877
1878 struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
1879 struct pipe_transfer *xfer = &map->base;
1880
1881 if (!map)
1882 return NULL;
1883
1884 memset(map, 0, sizeof(*map));
1885 map->dbg = &ice->dbg;
1886
1887 pipe_resource_reference(&xfer->resource, resource);
1888 xfer->level = level;
1889 xfer->usage = usage;
1890 xfer->box = *box;
1891 *ptransfer = xfer;
1892
1893 map->dest_had_defined_contents =
1894 util_ranges_intersect(&res->valid_buffer_range, box->x,
1895 box->x + box->width);
1896
1897 if (usage & PIPE_MAP_WRITE)
1898 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1899
1900 /* Avoid using GPU copies for persistent/coherent buffers, as the idea
1901 * there is to access them simultaneously on the CPU & GPU. This also
1902 * avoids trying to use GPU copies for our u_upload_mgr buffers which
1903 * contain state we're constructing for a GPU draw call, which would
1904 * kill us with infinite stack recursion.
1905 */
1906 bool no_gpu = usage & (PIPE_MAP_PERSISTENT |
1907 PIPE_MAP_COHERENT |
1908 PIPE_MAP_DIRECTLY);
1909
1910 /* GPU copies are not useful for buffer reads. Instead of stalling to
1911 * read from the original buffer, we'd simply copy it to a temporary...
1912 * then stall (a bit longer) to read from that buffer.
1913 *
1914 * Images are less clear-cut. Resolves can be destructive, removing some
1915 * of the underlying compression, so we'd rather blit the data to a linear
1916 * temporary and map that, to avoid the resolve. (It might be better to
1917 * a tiled temporary and use the tiled_memcpy paths...)
1918 */
1919 if (!(usage & PIPE_MAP_DISCARD_RANGE) &&
1920 !iris_has_invalid_primary(res, level, 1, box->z, box->depth)) {
1921 no_gpu = true;
1922 }
1923
1924 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1925 if (fmtl->txc == ISL_TXC_ASTC)
1926 no_gpu = true;
1927
1928 if (!map_would_stall &&
1929 res->aux.usage != ISL_AUX_USAGE_CCS_E &&
1930 res->aux.usage != ISL_AUX_USAGE_GEN12_CCS_E) {
1931 no_gpu = true;
1932 }
1933
1934 if (!no_gpu) {
1935 /* If we need a synchronous mapping and the resource is busy, or needs
1936 * resolving, we copy to/from a linear temporary buffer using the GPU.
1937 */
1938 map->batch = &ice->batches[IRIS_BATCH_RENDER];
1939 map->blorp = &ice->blorp;
1940 iris_map_copy_region(map);
1941 } else {
1942 /* Otherwise we're free to map on the CPU. */
1943
1944 if (resource->target != PIPE_BUFFER) {
1945 iris_resource_access_raw(ice, res, level, box->z, box->depth,
1946 usage & PIPE_MAP_WRITE);
1947 }
1948
1949 if (!(usage & PIPE_MAP_UNSYNCHRONIZED)) {
1950 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1951 if (iris_batch_references(&ice->batches[i], res->bo))
1952 iris_batch_flush(&ice->batches[i]);
1953 }
1954 }
1955
1956 if (surf->tiling == ISL_TILING_W) {
1957 /* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
1958 iris_map_s8(map);
1959 } else if (surf->tiling != ISL_TILING_LINEAR) {
1960 iris_map_tiled_memcpy(map);
1961 } else {
1962 iris_map_direct(map);
1963 }
1964 }
1965
1966 return map->ptr;
1967 }
1968
1969 static void
iris_transfer_flush_region(struct pipe_context * ctx,struct pipe_transfer * xfer,const struct pipe_box * box)1970 iris_transfer_flush_region(struct pipe_context *ctx,
1971 struct pipe_transfer *xfer,
1972 const struct pipe_box *box)
1973 {
1974 struct iris_context *ice = (struct iris_context *)ctx;
1975 struct iris_resource *res = (struct iris_resource *) xfer->resource;
1976 struct iris_transfer *map = (void *) xfer;
1977
1978 if (map->staging)
1979 iris_flush_staging_region(xfer, box);
1980
1981 uint32_t history_flush = 0;
1982
1983 if (res->base.target == PIPE_BUFFER) {
1984 if (map->staging)
1985 history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
1986
1987 if (map->dest_had_defined_contents)
1988 history_flush |= iris_flush_bits_for_history(ice, res);
1989
1990 util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width);
1991 }
1992
1993 if (history_flush & ~PIPE_CONTROL_CS_STALL) {
1994 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
1995 struct iris_batch *batch = &ice->batches[i];
1996 if (batch->contains_draw || batch->cache.render->entries) {
1997 iris_batch_maybe_flush(batch, 24);
1998 iris_emit_pipe_control_flush(batch,
1999 "cache history: transfer flush",
2000 history_flush);
2001 }
2002 }
2003 }
2004
2005 /* Make sure we flag constants dirty even if there's no need to emit
2006 * any PIPE_CONTROLs to a batch.
2007 */
2008 iris_dirty_for_history(ice, res);
2009 }
2010
2011 static void
iris_transfer_unmap(struct pipe_context * ctx,struct pipe_transfer * xfer)2012 iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
2013 {
2014 struct iris_context *ice = (struct iris_context *)ctx;
2015 struct iris_transfer *map = (void *) xfer;
2016
2017 if (!(xfer->usage & (PIPE_MAP_FLUSH_EXPLICIT |
2018 PIPE_MAP_COHERENT))) {
2019 struct pipe_box flush_box = {
2020 .x = 0, .y = 0, .z = 0,
2021 .width = xfer->box.width,
2022 .height = xfer->box.height,
2023 .depth = xfer->box.depth,
2024 };
2025 iris_transfer_flush_region(ctx, xfer, &flush_box);
2026 }
2027
2028 if (map->unmap)
2029 map->unmap(map);
2030
2031 pipe_resource_reference(&xfer->resource, NULL);
2032 slab_free(&ice->transfer_pool, map);
2033 }
2034
2035 /**
2036 * The pipe->texture_subdata() driver hook.
2037 *
2038 * Mesa's state tracker takes this path whenever possible, even with
2039 * PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER set.
2040 */
2041 static void
iris_texture_subdata(struct pipe_context * ctx,struct pipe_resource * resource,unsigned level,unsigned usage,const struct pipe_box * box,const void * data,unsigned stride,unsigned layer_stride)2042 iris_texture_subdata(struct pipe_context *ctx,
2043 struct pipe_resource *resource,
2044 unsigned level,
2045 unsigned usage,
2046 const struct pipe_box *box,
2047 const void *data,
2048 unsigned stride,
2049 unsigned layer_stride)
2050 {
2051 struct iris_context *ice = (struct iris_context *)ctx;
2052 struct iris_resource *res = (struct iris_resource *)resource;
2053 const struct isl_surf *surf = &res->surf;
2054
2055 assert(resource->target != PIPE_BUFFER);
2056
2057 if (iris_resource_unfinished_aux_import(res))
2058 iris_resource_finish_aux_import(ctx->screen, res);
2059
2060 /* Just use the transfer-based path for linear buffers - it will already
2061 * do a direct mapping, or a simple linear staging buffer.
2062 *
2063 * Linear staging buffers appear to be better than tiled ones, too, so
2064 * take that path if we need the GPU to perform color compression, or
2065 * stall-avoidance blits.
2066 */
2067 if (surf->tiling == ISL_TILING_LINEAR ||
2068 (isl_aux_usage_has_ccs(res->aux.usage) &&
2069 res->aux.usage != ISL_AUX_USAGE_CCS_D) ||
2070 resource_is_busy(ice, res)) {
2071 return u_default_texture_subdata(ctx, resource, level, usage, box,
2072 data, stride, layer_stride);
2073 }
2074
2075 /* No state trackers pass any flags other than PIPE_MAP_WRITE */
2076
2077 iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
2078
2079 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
2080 if (iris_batch_references(&ice->batches[i], res->bo))
2081 iris_batch_flush(&ice->batches[i]);
2082 }
2083
2084 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
2085
2086 for (int s = 0; s < box->depth; s++) {
2087 const uint8_t *src = data + s * layer_stride;
2088
2089 if (surf->tiling == ISL_TILING_W) {
2090 unsigned x0_el, y0_el;
2091 get_image_offset_el(surf, level, box->z + s, &x0_el, &y0_el);
2092
2093 for (unsigned y = 0; y < box->height; y++) {
2094 for (unsigned x = 0; x < box->width; x++) {
2095 ptrdiff_t offset = s8_offset(surf->row_pitch_B,
2096 x0_el + box->x + x,
2097 y0_el + box->y + y);
2098 dst[offset] = src[y * stride + x];
2099 }
2100 }
2101 } else {
2102 unsigned x1, x2, y1, y2;
2103
2104 tile_extents(surf, box, level, s, &x1, &x2, &y1, &y2);
2105
2106 isl_memcpy_linear_to_tiled(x1, x2, y1, y2,
2107 (void *)dst, (void *)src,
2108 surf->row_pitch_B, stride,
2109 false, surf->tiling, ISL_MEMCPY);
2110 }
2111 }
2112 }
2113
2114 /**
2115 * Mark state dirty that needs to be re-emitted when a resource is written.
2116 */
2117 void
iris_dirty_for_history(struct iris_context * ice,struct iris_resource * res)2118 iris_dirty_for_history(struct iris_context *ice,
2119 struct iris_resource *res)
2120 {
2121 uint64_t stage_dirty = 0ull;
2122
2123 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2124 stage_dirty |= ((uint64_t)res->bind_stages)
2125 << IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS;
2126 }
2127
2128 ice->state.stage_dirty |= stage_dirty;
2129 }
2130
2131 /**
2132 * Produce a set of PIPE_CONTROL bits which ensure data written to a
2133 * resource becomes visible, and any stale read cache data is invalidated.
2134 */
2135 uint32_t
iris_flush_bits_for_history(struct iris_context * ice,struct iris_resource * res)2136 iris_flush_bits_for_history(struct iris_context *ice,
2137 struct iris_resource *res)
2138 {
2139 struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
2140
2141 uint32_t flush = PIPE_CONTROL_CS_STALL;
2142
2143 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2144 flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2145 flush |= screen->compiler->indirect_ubos_use_sampler ?
2146 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
2147 PIPE_CONTROL_DATA_CACHE_FLUSH;
2148 }
2149
2150 if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
2151 flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2152
2153 if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
2154 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2155
2156 if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
2157 flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
2158
2159 return flush;
2160 }
2161
2162 void
iris_flush_and_dirty_for_history(struct iris_context * ice,struct iris_batch * batch,struct iris_resource * res,uint32_t extra_flags,const char * reason)2163 iris_flush_and_dirty_for_history(struct iris_context *ice,
2164 struct iris_batch *batch,
2165 struct iris_resource *res,
2166 uint32_t extra_flags,
2167 const char *reason)
2168 {
2169 if (res->base.target != PIPE_BUFFER)
2170 return;
2171
2172 uint32_t flush = iris_flush_bits_for_history(ice, res) | extra_flags;
2173
2174 iris_emit_pipe_control_flush(batch, reason, flush);
2175
2176 iris_dirty_for_history(ice, res);
2177 }
2178
2179 bool
iris_resource_set_clear_color(struct iris_context * ice,struct iris_resource * res,union isl_color_value color)2180 iris_resource_set_clear_color(struct iris_context *ice,
2181 struct iris_resource *res,
2182 union isl_color_value color)
2183 {
2184 if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
2185 res->aux.clear_color = color;
2186 return true;
2187 }
2188
2189 return false;
2190 }
2191
2192 union isl_color_value
iris_resource_get_clear_color(const struct iris_resource * res,struct iris_bo ** clear_color_bo,uint64_t * clear_color_offset)2193 iris_resource_get_clear_color(const struct iris_resource *res,
2194 struct iris_bo **clear_color_bo,
2195 uint64_t *clear_color_offset)
2196 {
2197 assert(res->aux.bo);
2198
2199 if (clear_color_bo)
2200 *clear_color_bo = res->aux.clear_color_bo;
2201 if (clear_color_offset)
2202 *clear_color_offset = res->aux.clear_color_offset;
2203 return res->aux.clear_color;
2204 }
2205
2206 static enum pipe_format
iris_resource_get_internal_format(struct pipe_resource * p_res)2207 iris_resource_get_internal_format(struct pipe_resource *p_res)
2208 {
2209 struct iris_resource *res = (void *) p_res;
2210 return res->internal_format;
2211 }
2212
2213 static const struct u_transfer_vtbl transfer_vtbl = {
2214 .resource_create = iris_resource_create,
2215 .resource_destroy = iris_resource_destroy,
2216 .transfer_map = iris_transfer_map,
2217 .transfer_unmap = iris_transfer_unmap,
2218 .transfer_flush_region = iris_transfer_flush_region,
2219 .get_internal_format = iris_resource_get_internal_format,
2220 .set_stencil = iris_resource_set_separate_stencil,
2221 .get_stencil = iris_resource_get_separate_stencil,
2222 };
2223
2224 void
iris_init_screen_resource_functions(struct pipe_screen * pscreen)2225 iris_init_screen_resource_functions(struct pipe_screen *pscreen)
2226 {
2227 pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
2228 pscreen->resource_create_with_modifiers =
2229 iris_resource_create_with_modifiers;
2230 pscreen->resource_create = u_transfer_helper_resource_create;
2231 pscreen->resource_from_user_memory = iris_resource_from_user_memory;
2232 pscreen->resource_from_handle = iris_resource_from_handle;
2233 pscreen->resource_get_handle = iris_resource_get_handle;
2234 pscreen->resource_get_param = iris_resource_get_param;
2235 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
2236 pscreen->transfer_helper =
2237 u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
2238 }
2239
2240 void
iris_init_resource_functions(struct pipe_context * ctx)2241 iris_init_resource_functions(struct pipe_context *ctx)
2242 {
2243 ctx->flush_resource = iris_flush_resource;
2244 ctx->invalidate_resource = iris_invalidate_resource;
2245 ctx->transfer_map = u_transfer_helper_transfer_map;
2246 ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
2247 ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
2248 ctx->buffer_subdata = u_default_buffer_subdata;
2249 ctx->texture_subdata = iris_texture_subdata;
2250 }
2251