1 // Copyright 2021 The Pigweed Authors 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not 4 // use this file except in compliance with the License. You may obtain a copy of 5 // the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 12 // License for the specific language governing permissions and limitations under 13 // the License. 14 15 #pragma once 16 17 #include <cstdint> 18 19 namespace pw::cpu_exception { 20 21 // CMSIS/Cortex-M/ARMv7 related constants. 22 // These values are from the ARMv7-M Architecture Reference Manual DDI 0403E.b. 23 // https://static.docs.arm.com/ddi0403/e/DDI0403E_B_armv7m_arm.pdf 24 25 constexpr uint32_t kThreadModeIsrNum = 0x0; 26 constexpr uint32_t kNmiIsrNum = 0x2; 27 constexpr uint32_t kHardFaultIsrNum = 0x3; 28 constexpr uint32_t kMemFaultIsrNum = 0x4; 29 constexpr uint32_t kBusFaultIsrNum = 0x5; 30 constexpr uint32_t kUsageFaultIsrNum = 0x6; 31 32 // Masks for Interrupt Control and State Register ICSR (ARMv7-M Section B3.2.4) 33 constexpr uint32_t kIcsrVectactiveMask = (1 << 9) - 1; 34 35 // Masks for individual bits of HFSR. (ARMv7-M Section B3.2.16) 36 constexpr uint32_t kHfsrForcedMask = (0x1 << 30); 37 38 // Masks for different sections of CFSR. (ARMv7-M Section B3.2.15) 39 constexpr uint32_t kCfsrMemFaultMask = 0x000000ff; 40 constexpr uint32_t kCfsrBusFaultMask = 0x0000ff00; 41 constexpr uint32_t kCfsrUsageFaultMask = 0xffff0000; 42 43 // Masks for individual bits of CFSR. (ARMv7-M Section B3.2.15) 44 // Memory faults (MemManage Status Register) 45 constexpr uint32_t kCfsrMemFaultStart = (0x1); 46 constexpr uint32_t kCfsrIaccviolMask = (kCfsrMemFaultStart << 0); 47 constexpr uint32_t kCfsrDaccviolMask = (kCfsrMemFaultStart << 1); 48 constexpr uint32_t kCfsrMunstkerrMask = (kCfsrMemFaultStart << 3); 49 constexpr uint32_t kCfsrMstkerrMask = (kCfsrMemFaultStart << 4); 50 constexpr uint32_t kCfsrMlsperrMask = (kCfsrMemFaultStart << 5); 51 constexpr uint32_t kCfsrMmarvalidMask = (kCfsrMemFaultStart << 7); 52 // Bus faults (BusFault Status Register) 53 constexpr uint32_t kCfsrBusFaultStart = (0x1 << 8); 54 constexpr uint32_t kCfsrIbuserrMask = (kCfsrBusFaultStart << 0); 55 constexpr uint32_t kCfsrPreciserrMask = (kCfsrBusFaultStart << 1); 56 constexpr uint32_t kCfsrImpreciserrMask = (kCfsrBusFaultStart << 2); 57 constexpr uint32_t kCfsrUnstkerrMask = (kCfsrBusFaultStart << 3); 58 constexpr uint32_t kCfsrStkerrMask = (kCfsrBusFaultStart << 4); 59 constexpr uint32_t kCfsrLsperrMask = (kCfsrBusFaultStart << 5); 60 constexpr uint32_t kCfsrBfarvalidMask = (kCfsrBusFaultStart << 7); 61 // Usage faults (UsageFault Status Register) 62 constexpr uint32_t kCfsrUsageFaultStart = (0x1 << 16); 63 constexpr uint32_t kCfsrUndefinstrMask = (kCfsrUsageFaultStart << 0); 64 constexpr uint32_t kCfsrInvstateMask = (kCfsrUsageFaultStart << 1); 65 constexpr uint32_t kCfsrInvpcMask = (kCfsrUsageFaultStart << 2); 66 constexpr uint32_t kCfsrNocpMask = (kCfsrUsageFaultStart << 3); 67 constexpr uint32_t kCfsrStkofMask = (kCfsrUsageFaultStart << 4); 68 constexpr uint32_t kCfsrUnalignedMask = (kCfsrUsageFaultStart << 8); 69 constexpr uint32_t kCfsrDivbyzeroMask = (kCfsrUsageFaultStart << 9); 70 71 // Bit masks for an exception return value. (ARMv7-M Section B1.5.8) 72 constexpr uint32_t kExcReturnStackMask = 0x1u << 2; 73 constexpr uint32_t kExcReturnBasicFrameMask = 0x1u << 4; 74 75 // Memory mapped registers. (ARMv7-M Section B3.2.2, Table B3-4) 76 // TODO(pwbug/316): Only some of these are supported on ARMv6-M. 77 inline volatile uint32_t& cortex_m_cfsr = 78 *reinterpret_cast<volatile uint32_t*>(0xE000ED28u); 79 inline volatile uint32_t& cortex_m_mmfar = 80 *reinterpret_cast<volatile uint32_t*>(0xE000ED34u); 81 inline volatile uint32_t& cortex_m_bfar = 82 *reinterpret_cast<volatile uint32_t*>(0xE000ED38u); 83 inline volatile uint32_t& cortex_m_icsr = 84 *reinterpret_cast<volatile uint32_t*>(0xE000ED04u); 85 inline volatile uint32_t& cortex_m_hfsr = 86 *reinterpret_cast<volatile uint32_t*>(0xE000ED2Cu); 87 inline volatile uint32_t& cortex_m_shcsr = 88 *reinterpret_cast<volatile uint32_t*>(0xE000ED24u); 89 90 } // namespace pw::cpu_exception 91