1 // Copyright 2019 The Pigweed Authors 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not 4 // use this file except in compliance with the License. You may obtain a copy of 5 // the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 12 // License for the specific language governing permissions and limitations under 13 // the License. 14 #pragma once 15 16 #include <cstdint> 17 18 #include "pw_preprocessor/compiler.h" 19 20 namespace pw::cpu_exception { 21 22 // This is dictated by ARMv7-M architecture. Do not change. PW_PACKED(struct)23PW_PACKED(struct) CortexMExceptionRegisters { 24 uint32_t r0; 25 uint32_t r1; 26 uint32_t r2; 27 uint32_t r3; 28 uint32_t r12; 29 uint32_t lr; // Link register. 30 uint32_t pc; // Program counter. 31 uint32_t psr; // Program status register. 32 }; 33 34 // This is dictated by ARMv7-M architecture. Do not change. PW_PACKED(struct)35PW_PACKED(struct) CortexMExceptionRegistersFpu { 36 uint32_t s0; 37 uint32_t s1; 38 uint32_t s2; 39 uint32_t s3; 40 uint32_t s4; 41 uint32_t s5; 42 uint32_t s6; 43 uint32_t s7; 44 uint32_t s8; 45 uint32_t s9; 46 uint32_t s10; 47 uint32_t s11; 48 uint32_t s12; 49 uint32_t s13; 50 uint32_t s14; 51 uint32_t s15; 52 uint32_t fpscr; 53 uint32_t reserved; 54 }; 55 56 // Bit in the PSR that indicates CPU added an extra word on the stack to 57 // align it during context save for an exception. 58 inline constexpr uint32_t kPsrExtraStackAlignBit = (1 << 9); 59 60 // This is dictated by this module, and shouldn't change often. 61 // Note that the order of entries in this struct is very important (as the 62 // values are populated in assembly). 63 // 64 // NOTE: Memory mapped registers are NOT restored upon fault return! PW_PACKED(struct)65PW_PACKED(struct) CortexMExtraRegisters { 66 // Memory mapped registers. 67 uint32_t cfsr; 68 uint32_t mmfar; 69 uint32_t bfar; 70 uint32_t icsr; 71 uint32_t hfsr; 72 uint32_t shcsr; 73 // Special registers. 74 uint32_t exc_return; 75 uint32_t msp; 76 uint32_t psp; 77 uint32_t control; 78 // General purpose registers. 79 uint32_t r4; 80 uint32_t r5; 81 uint32_t r6; 82 uint32_t r7; 83 uint32_t r8; 84 uint32_t r9; 85 uint32_t r10; 86 uint32_t r11; 87 }; 88 89 } // namespace pw::cpu_exception 90 PW_PACKED(struct)91PW_PACKED(struct) pw_cpu_exception_State { 92 pw::cpu_exception::CortexMExtraRegisters extended; 93 pw::cpu_exception::CortexMExceptionRegisters base; 94 // TODO(amontanez): FPU registers may or may not be here as well. Make the 95 // availability of the FPU registers a compile-time configuration when FPU 96 // register support is added. 97 }; 98