1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include <stdbool.h>
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "main/errors.h"
40 #include "brw_structs.h"
41 #include "brw_pipe_control.h"
42 #include "compiler/brw_compiler.h"
43
44 #include "isl/isl.h"
45 #include "blorp/blorp.h"
46
47 #include <brw_bufmgr.h>
48
49 #include "dev/gen_debug.h"
50 #include "common/gen_decoder.h"
51 #include "intel_screen.h"
52 #include "intel_tex_obj.h"
53 #include "perf/gen_perf.h"
54 #include "perf/gen_perf_query.h"
55
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 /* Glossary:
60 *
61 * URB - uniform resource buffer. A mid-sized buffer which is
62 * partitioned between the fixed function units and used for passing
63 * values (vertices, primitives, constants) between them.
64 *
65 * CURBE - constant URB entry. An urb region (entry) used to hold
66 * constant values which the fixed function units can be instructed to
67 * preload into the GRF when spawning a thread.
68 *
69 * VUE - vertex URB entry. An urb entry holding a vertex and usually
70 * a vertex header. The header contains control information and
71 * things like primitive type, Begin/end flags and clip codes.
72 *
73 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
74 * unit holding rasterization and interpolation parameters.
75 *
76 * GRF - general register file. One of several register files
77 * addressable by programmed threads. The inputs (r0, payload, curbe,
78 * urb) of the thread are preloaded to this area before the thread is
79 * spawned. The registers are individually 8 dwords wide and suitable
80 * for general usage. Registers holding thread input values are not
81 * special and may be overwritten.
82 *
83 * MRF - message register file. Threads communicate (and terminate)
84 * by sending messages. Message parameters are placed in contiguous
85 * MRF registers. All program output is via these messages. URB
86 * entries are populated by sending a message to the shared URB
87 * function containing the new data, together with a control word,
88 * often an unmodified copy of R0.
89 *
90 * R0 - GRF register 0. Typically holds control information used when
91 * sending messages to other threads.
92 *
93 * EU or GEN4 EU: The name of the programmable subsystem of the
94 * i965 hardware. Threads are executed by the EU, the registers
95 * described above are part of the EU architecture.
96 *
97 * Fixed function units:
98 *
99 * CS - Command streamer. Notional first unit, little software
100 * interaction. Holds the URB entries used for constant data, ie the
101 * CURBEs.
102 *
103 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
104 * this unit is responsible for pulling vertices out of vertex buffers
105 * in vram and injecting them into the processing pipe as VUEs. If
106 * enabled, it first passes them to a VS thread which is a good place
107 * for the driver to implement any active vertex shader.
108 *
109 * HS - Hull Shader (Tessellation Control Shader)
110 *
111 * TE - Tessellation Engine (Tessellation Primitive Generation)
112 *
113 * DS - Domain Shader (Tessellation Evaluation Shader)
114 *
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
123 *
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
129 *
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
133 *
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
137 *
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
140 */
141
142 struct brw_context;
143 struct brw_inst;
144 struct brw_vs_prog_key;
145 struct brw_vue_prog_key;
146 struct brw_wm_prog_key;
147 struct brw_wm_prog_data;
148 struct brw_cs_prog_key;
149 struct brw_cs_prog_data;
150 struct brw_label;
151
152 enum brw_pipeline {
153 BRW_RENDER_PIPELINE,
154 BRW_COMPUTE_PIPELINE,
155
156 BRW_NUM_PIPELINES
157 };
158
159 enum brw_cache_id {
160 BRW_CACHE_FS_PROG,
161 BRW_CACHE_BLORP_PROG,
162 BRW_CACHE_SF_PROG,
163 BRW_CACHE_VS_PROG,
164 BRW_CACHE_FF_GS_PROG,
165 BRW_CACHE_GS_PROG,
166 BRW_CACHE_TCS_PROG,
167 BRW_CACHE_TES_PROG,
168 BRW_CACHE_CLIP_PROG,
169 BRW_CACHE_CS_PROG,
170
171 BRW_MAX_CACHE
172 };
173
174 enum gen9_astc5x5_wa_tex_type {
175 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
176 GEN9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1,
177 };
178
179 enum brw_state_id {
180 /* brw_cache_ids must come first - see brw_program_cache.c */
181 BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
182 BRW_STATE_FRAGMENT_PROGRAM,
183 BRW_STATE_GEOMETRY_PROGRAM,
184 BRW_STATE_TESS_PROGRAMS,
185 BRW_STATE_VERTEX_PROGRAM,
186 BRW_STATE_REDUCED_PRIMITIVE,
187 BRW_STATE_PATCH_PRIMITIVE,
188 BRW_STATE_PRIMITIVE,
189 BRW_STATE_CONTEXT,
190 BRW_STATE_PSP,
191 BRW_STATE_SURFACES,
192 BRW_STATE_BINDING_TABLE_POINTERS,
193 BRW_STATE_INDICES,
194 BRW_STATE_VERTICES,
195 BRW_STATE_DEFAULT_TESS_LEVELS,
196 BRW_STATE_BATCH,
197 BRW_STATE_INDEX_BUFFER,
198 BRW_STATE_VS_CONSTBUF,
199 BRW_STATE_TCS_CONSTBUF,
200 BRW_STATE_TES_CONSTBUF,
201 BRW_STATE_GS_CONSTBUF,
202 BRW_STATE_PROGRAM_CACHE,
203 BRW_STATE_STATE_BASE_ADDRESS,
204 BRW_STATE_VUE_MAP_GEOM_OUT,
205 BRW_STATE_TRANSFORM_FEEDBACK,
206 BRW_STATE_RASTERIZER_DISCARD,
207 BRW_STATE_STATS_WM,
208 BRW_STATE_UNIFORM_BUFFER,
209 BRW_STATE_IMAGE_UNITS,
210 BRW_STATE_META_IN_PROGRESS,
211 BRW_STATE_PUSH_CONSTANT_ALLOCATION,
212 BRW_STATE_NUM_SAMPLES,
213 BRW_STATE_TEXTURE_BUFFER,
214 BRW_STATE_GEN4_UNIT_STATE,
215 BRW_STATE_CC_VP,
216 BRW_STATE_SF_VP,
217 BRW_STATE_CLIP_VP,
218 BRW_STATE_SAMPLER_STATE_TABLE,
219 BRW_STATE_VS_ATTRIB_WORKAROUNDS,
220 BRW_STATE_COMPUTE_PROGRAM,
221 BRW_STATE_CS_WORK_GROUPS,
222 BRW_STATE_URB_SIZE,
223 BRW_STATE_CC_STATE,
224 BRW_STATE_BLORP,
225 BRW_STATE_VIEWPORT_COUNT,
226 BRW_STATE_CONSERVATIVE_RASTERIZATION,
227 BRW_STATE_DRAW_CALL,
228 BRW_STATE_AUX,
229 BRW_NUM_STATE_BITS
230 };
231
232 /**
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
234 *
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
239 *
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
244 *
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
248 *
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
251 */
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_program_cache code with special cases, we retain the
256 * dirty bit for now. It should eventually be removed.
257 */
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
273 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
274 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
275 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
276 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
277 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
278 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
279 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
280 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
281 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
282 /**
283 * Used for any batch entry with a relocated pointer that will be used
284 * by any 3D rendering.
285 */
286 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
287 /** \see brw.state.depth_region */
288 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
289 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
290 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
291 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
292 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
293 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
294 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
295 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
296 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
297 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
298 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
299 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
300 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
301 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
302 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
303 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
304 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
305 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
306 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
307 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
308 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
309 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
310 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
311 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
312 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
313 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
314 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
315 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
316 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
317 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
318 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
319 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
320
321 struct brw_state_flags {
322 /** State update flags signalled by mesa internals */
323 GLuint mesa;
324 /**
325 * State update flags signalled as the result of brw_tracked_state updates
326 */
327 uint64_t brw;
328 };
329
330
331 /** Subclass of Mesa program */
332 struct brw_program {
333 struct gl_program program;
334 GLuint id;
335
336 bool compiled_once;
337 };
338
339
340 struct brw_ff_gs_prog_data {
341 GLuint urb_read_length;
342 GLuint total_grf;
343
344 /**
345 * Gen6 transform feedback: Amount by which the streaming vertex buffer
346 * indices should be incremented each time the GS is invoked.
347 */
348 unsigned svbi_postincrement_value;
349 };
350
351 /** Number of texture sampler units */
352 #define BRW_MAX_TEX_UNIT 32
353
354 /** Max number of UBOs in a shader */
355 #define BRW_MAX_UBO 14
356
357 /** Max number of SSBOs in a shader */
358 #define BRW_MAX_SSBO 12
359
360 /** Max number of atomic counter buffer objects in a shader */
361 #define BRW_MAX_ABO 16
362
363 /** Max number of image uniforms in a shader */
364 #define BRW_MAX_IMAGES 32
365
366 /** Maximum number of actual buffers used for stream output */
367 #define BRW_MAX_SOL_BUFFERS 4
368
369 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
370 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
371 BRW_MAX_UBO + \
372 BRW_MAX_SSBO + \
373 BRW_MAX_ABO + \
374 BRW_MAX_IMAGES + \
375 2 + /* shader time, pull constants */ \
376 1 /* cs num work groups */)
377
378 struct brw_cache {
379 struct brw_context *brw;
380
381 struct brw_cache_item **items;
382 struct brw_bo *bo;
383 void *map;
384 GLuint size, n_items;
385
386 uint32_t next_offset;
387 };
388
389 #define perf_debug(...) do { \
390 static GLuint msg_id = 0; \
391 if (INTEL_DEBUG & DEBUG_PERF) \
392 dbg_printf(__VA_ARGS__); \
393 if (brw->perf_debug) \
394 _mesa_gl_debugf(&brw->ctx, &msg_id, \
395 MESA_DEBUG_SOURCE_API, \
396 MESA_DEBUG_TYPE_PERFORMANCE, \
397 MESA_DEBUG_SEVERITY_MEDIUM, \
398 __VA_ARGS__); \
399 } while(0)
400
401 #define WARN_ONCE(cond, fmt...) do { \
402 if (unlikely(cond)) { \
403 static bool _warned = false; \
404 static GLuint msg_id = 0; \
405 if (!_warned) { \
406 fprintf(stderr, "WARNING: "); \
407 fprintf(stderr, fmt); \
408 _warned = true; \
409 \
410 _mesa_gl_debugf(ctx, &msg_id, \
411 MESA_DEBUG_SOURCE_API, \
412 MESA_DEBUG_TYPE_OTHER, \
413 MESA_DEBUG_SEVERITY_HIGH, fmt); \
414 } \
415 } \
416 } while (0)
417
418 /* Considered adding a member to this struct to document which flags
419 * an update might raise so that ordering of the state atoms can be
420 * checked or derived at runtime. Dropped the idea in favor of having
421 * a debug mode where the state is monitored for flags which are
422 * raised that have already been tested against.
423 */
424 struct brw_tracked_state {
425 struct brw_state_flags dirty;
426 void (*emit)( struct brw_context *brw );
427 };
428
429 enum shader_time_shader_type {
430 ST_NONE,
431 ST_VS,
432 ST_TCS,
433 ST_TES,
434 ST_GS,
435 ST_FS8,
436 ST_FS16,
437 ST_FS32,
438 ST_CS,
439 };
440
441 struct brw_vertex_buffer {
442 /** Buffer object containing the uploaded vertex data */
443 struct brw_bo *bo;
444 uint32_t offset;
445 uint32_t size;
446 /** Byte stride between elements in the uploaded array */
447 GLuint stride;
448 GLuint step_rate;
449 };
450 struct brw_vertex_element {
451 const struct gl_vertex_format *glformat;
452
453 int buffer;
454 bool is_dual_slot;
455 /** Offset of the first element within the buffer object */
456 unsigned int offset;
457 };
458
459 struct brw_query_object {
460 struct gl_query_object Base;
461
462 /** Last query BO associated with this query. */
463 struct brw_bo *bo;
464
465 /** Last index in bo with query data for this object. */
466 int last_index;
467
468 /** True if we know the batch has been flushed since we ended the query. */
469 bool flushed;
470 };
471
472 struct brw_reloc_list {
473 struct drm_i915_gem_relocation_entry *relocs;
474 int reloc_count;
475 int reloc_array_size;
476 };
477
478 struct brw_growing_bo {
479 struct brw_bo *bo;
480 uint32_t *map;
481 struct brw_bo *partial_bo;
482 uint32_t *partial_bo_map;
483 unsigned partial_bytes;
484 enum brw_memory_zone memzone;
485 };
486
487 struct intel_batchbuffer {
488 /** Current batchbuffer being queued up. */
489 struct brw_growing_bo batch;
490 /** Current statebuffer being queued up. */
491 struct brw_growing_bo state;
492
493 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
494 struct brw_bo *last_bo;
495
496 #ifdef DEBUG
497 uint16_t emit, total;
498 #endif
499 uint32_t *map_next;
500 uint32_t state_used;
501
502 bool use_shadow_copy;
503 bool use_batch_first;
504 bool needs_sol_reset;
505 bool state_base_address_emitted;
506 bool no_wrap;
507
508 struct brw_reloc_list batch_relocs;
509 struct brw_reloc_list state_relocs;
510 unsigned int valid_reloc_flags;
511
512 /** The validation list */
513 struct drm_i915_gem_exec_object2 *validation_list;
514 struct brw_bo **exec_bos;
515 int exec_count;
516 int exec_array_size;
517
518 /** The amount of aperture space (in bytes) used by all exec_bos */
519 uint64_t aperture_space;
520
521 struct {
522 uint32_t *map_next;
523 int batch_reloc_count;
524 int state_reloc_count;
525 int exec_count;
526 } saved;
527
528 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
529 struct hash_table_u64 *state_batch_sizes;
530
531 struct gen_batch_decode_ctx decoder;
532 };
533
534 #define BRW_MAX_XFB_STREAMS 4
535
536 struct brw_transform_feedback_counter {
537 /**
538 * Index of the first entry of this counter within the primitive count BO.
539 * An entry is considered to be an N-tuple of 64bit values, where N is the
540 * number of vertex streams supported by the platform.
541 */
542 unsigned bo_start;
543
544 /**
545 * Index one past the last entry of this counter within the primitive
546 * count BO.
547 */
548 unsigned bo_end;
549
550 /**
551 * Primitive count values accumulated while this counter was active,
552 * excluding any entries buffered between \c bo_start and \c bo_end, which
553 * haven't been accounted for yet.
554 */
555 uint64_t accum[BRW_MAX_XFB_STREAMS];
556 };
557
558 static inline void
brw_reset_transform_feedback_counter(struct brw_transform_feedback_counter * counter)559 brw_reset_transform_feedback_counter(
560 struct brw_transform_feedback_counter *counter)
561 {
562 counter->bo_start = counter->bo_end;
563 memset(&counter->accum, 0, sizeof(counter->accum));
564 }
565
566 struct brw_transform_feedback_object {
567 struct gl_transform_feedback_object base;
568
569 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
570 struct brw_bo *offset_bo;
571
572 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
573 bool zero_offsets;
574
575 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
576 GLenum primitive_mode;
577
578 /**
579 * The maximum number of vertices that we can write without overflowing
580 * any of the buffers currently being used for transform feedback.
581 */
582 unsigned max_index;
583
584 struct brw_bo *prim_count_bo;
585
586 /**
587 * Count of primitives generated during this transform feedback operation.
588 */
589 struct brw_transform_feedback_counter counter;
590
591 /**
592 * Count of primitives generated during the previous transform feedback
593 * operation. Used to implement DrawTransformFeedback().
594 */
595 struct brw_transform_feedback_counter previous_counter;
596
597 /**
598 * Number of vertices written between last Begin/EndTransformFeedback().
599 *
600 * Used to implement DrawTransformFeedback().
601 */
602 uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
603 bool vertices_written_valid;
604 };
605
606 /**
607 * Data shared between each programmable stage in the pipeline (vs, gs, and
608 * wm).
609 */
610 struct brw_stage_state
611 {
612 gl_shader_stage stage;
613 struct brw_stage_prog_data *prog_data;
614
615 /**
616 * Optional scratch buffer used to store spilled register values and
617 * variably-indexed GRF arrays.
618 *
619 * The contents of this buffer are short-lived so the same memory can be
620 * re-used at will for multiple shader programs (executed by the same fixed
621 * function). However reusing a scratch BO for which shader invocations
622 * are still in flight with a per-thread scratch slot size other than the
623 * original can cause threads with different scratch slot size and FFTID
624 * (which may be executed in parallel depending on the shader stage and
625 * hardware generation) to map to an overlapping region of the scratch
626 * space, which can potentially lead to mutual scratch space corruption.
627 * For that reason if you borrow this scratch buffer you should only be
628 * using the slot size given by the \c per_thread_scratch member below,
629 * unless you're taking additional measures to synchronize thread execution
630 * across slot size changes.
631 */
632 struct brw_bo *scratch_bo;
633
634 /**
635 * Scratch slot size allocated for each thread in the buffer object given
636 * by \c scratch_bo.
637 */
638 uint32_t per_thread_scratch;
639
640 /** Offset in the program cache to the program */
641 uint32_t prog_offset;
642
643 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
644 uint32_t state_offset;
645
646 struct brw_bo *push_const_bo; /* NULL if using the batchbuffer */
647 uint32_t push_const_offset; /* Offset in the push constant BO or batch */
648 int push_const_size; /* in 256-bit register increments */
649
650 /* Binding table: pointers to SURFACE_STATE entries. */
651 uint32_t bind_bo_offset;
652 uint32_t surf_offset[BRW_MAX_SURFACES];
653
654 /** SAMPLER_STATE count and table offset */
655 uint32_t sampler_count;
656 uint32_t sampler_offset;
657
658 struct brw_image_param image_param[BRW_MAX_IMAGES];
659
660 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
661 bool push_constants_dirty;
662 };
663
664 enum brw_predicate_state {
665 /* The first two states are used if we can determine whether to draw
666 * without having to look at the values in the query object buffer. This
667 * will happen if there is no conditional render in progress, if the query
668 * object is already completed or if something else has already added
669 * samples to the preliminary result such as via a BLT command.
670 */
671 BRW_PREDICATE_STATE_RENDER,
672 BRW_PREDICATE_STATE_DONT_RENDER,
673 /* In this case whether to draw or not depends on the result of an
674 * MI_PREDICATE command so the predicate enable bit needs to be checked.
675 */
676 BRW_PREDICATE_STATE_USE_BIT,
677 /* In this case, either MI_PREDICATE doesn't exist or we lack the
678 * necessary kernel features to use it. Stall for the query result.
679 */
680 BRW_PREDICATE_STATE_STALL_FOR_QUERY,
681 };
682
683 struct shader_times;
684
685 struct gen_l3_config;
686 struct gen_perf;
687
688 struct brw_uploader {
689 struct brw_bufmgr *bufmgr;
690 struct brw_bo *bo;
691 void *map;
692 uint32_t next_offset;
693 unsigned default_size;
694 };
695
696 /**
697 * brw_context is derived from gl_context.
698 */
699 struct brw_context
700 {
701 struct gl_context ctx; /**< base class, must be first field */
702
703 struct
704 {
705 /**
706 * Emit an MI_REPORT_PERF_COUNT command packet.
707 *
708 * This asks the GPU to write a report of the current OA counter values
709 * into @bo at the given offset and containing the given @report_id
710 * which we can cross-reference when parsing the report (gen7+ only).
711 */
712 void (*emit_mi_report_perf_count)(struct brw_context *brw,
713 struct brw_bo *bo,
714 uint32_t offset_in_bytes,
715 uint32_t report_id);
716
717 void (*emit_compute_walker)(struct brw_context *brw);
718 void (*emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
719 struct brw_bo *bo, uint32_t offset,
720 uint64_t imm);
721 } vtbl;
722
723 struct brw_bufmgr *bufmgr;
724
725 uint32_t hw_ctx;
726
727 /**
728 * BO for post-sync nonzero writes for gen6 workaround.
729 *
730 * This buffer also contains a marker + description of the driver. This
731 * buffer is added to all execbufs syscalls so that we can identify the
732 * driver that generated a hang by looking at the content of the buffer in
733 * the error state.
734 *
735 * Read/write should go at workaround_bo_offset in that buffer to avoid
736 * overriding the debug data.
737 */
738 struct brw_bo *workaround_bo;
739 uint32_t workaround_bo_offset;
740 uint8_t pipe_controls_since_last_cs_stall;
741
742 /**
743 * Set of struct brw_bo * that have been rendered to within this batchbuffer
744 * and would need flushing before being used from another cache domain that
745 * isn't coherent with it (i.e. the sampler).
746 */
747 struct hash_table *render_cache;
748
749 /**
750 * Set of struct brw_bo * that have been used as a depth buffer within this
751 * batchbuffer and would need flushing before being used from another cache
752 * domain that isn't coherent with it (i.e. the sampler).
753 */
754 struct set *depth_cache;
755
756 /**
757 * Number of resets observed in the system at context creation.
758 *
759 * This is tracked in the context so that we can determine that another
760 * reset has occurred.
761 */
762 uint32_t reset_count;
763
764 struct intel_batchbuffer batch;
765
766 struct brw_uploader upload;
767
768 /**
769 * Set if rendering has occurred to the drawable's front buffer.
770 *
771 * This is used in the DRI2 case to detect that glFlush should also copy
772 * the contents of the fake front buffer to the real front buffer.
773 */
774 bool front_buffer_dirty;
775
776 /**
777 * True if the __DRIdrawable's current __DRIimageBufferMask is
778 * __DRI_IMAGE_BUFFER_SHARED.
779 */
780 bool is_shared_buffer_bound;
781
782 /**
783 * True if a shared buffer is bound and it has received any rendering since
784 * the previous __DRImutableRenderBufferLoaderExtension::displaySharedBuffer().
785 */
786 bool is_shared_buffer_dirty;
787
788 /** Framerate throttling: @{ */
789 struct brw_bo *throttle_batch[2];
790
791 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
792 * frame of rendering to complete. This gives a very precise cap to the
793 * latency between input and output such that rendering never gets more
794 * than a frame behind the user. (With the caveat that we technically are
795 * not using the SwapBuffers itself as a barrier but the first batch
796 * submitted afterwards, which may be immediately prior to the next
797 * SwapBuffers.)
798 */
799 bool need_swap_throttle;
800
801 /** General throttling, not caught by throttling between SwapBuffers */
802 bool need_flush_throttle;
803 /** @} */
804
805 GLuint stats_wm;
806
807 /**
808 * drirc options:
809 * @{
810 */
811 bool always_flush_batch;
812 bool always_flush_cache;
813 bool disable_throttling;
814 bool precompile;
815 bool dual_color_blend_by_location;
816
817 driOptionCache optionCache;
818 /** @} */
819
820 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
821
822 bool object_preemption; /**< Object level preemption enabled. */
823
824 GLenum reduced_primitive;
825
826 /**
827 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
828 * variable is set, this is the flag indicating to do expensive work that
829 * might lead to a perf_debug() call.
830 */
831 bool perf_debug;
832
833 uint64_t max_gtt_map_object_size;
834
835 bool has_hiz;
836 bool has_separate_stencil;
837 bool has_swizzling;
838
839 /** Derived stencil states. */
840 bool stencil_enabled;
841 bool stencil_two_sided;
842 bool stencil_write_enabled;
843 /** Derived polygon state. */
844 bool polygon_front_bit; /**< 0=GL_CCW, 1=GL_CW */
845
846 struct isl_device isl_dev;
847
848 struct blorp_context blorp;
849
850 GLuint NewGLState;
851 struct {
852 struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
853 } state;
854
855 enum brw_pipeline last_pipeline;
856
857 struct brw_cache cache;
858
859 /* Whether a meta-operation is in progress. */
860 bool meta_in_progress;
861
862 /* Whether the last depth/stencil packets were both NULL. */
863 bool no_depth_or_stencil;
864
865 /* The last PMA stall bits programmed. */
866 uint32_t pma_stall_bits;
867
868 /* Whether INTEL_black_render is active. */
869 bool frontend_noop;
870
871 struct {
872 struct {
873 /**
874 * Either the value of gl_BaseVertex for indexed draw calls or the
875 * value of the argument <first> for non-indexed draw calls for the
876 * current _mesa_prim.
877 */
878 int firstvertex;
879
880 /** The value of gl_BaseInstance for the current _mesa_prim. */
881 int gl_baseinstance;
882 } params;
883
884 /**
885 * Buffer and offset used for GL_ARB_shader_draw_parameters which will
886 * point to the indirect buffer for indirect draw calls.
887 */
888 struct brw_bo *draw_params_bo;
889 uint32_t draw_params_offset;
890
891 struct {
892 /**
893 * The value of gl_DrawID for the current _mesa_prim. This always comes
894 * in from it's own vertex buffer since it's not part of the indirect
895 * draw parameters.
896 */
897 int gl_drawid;
898
899 /**
900 * Stores if the current _mesa_prim is an indexed or non-indexed draw
901 * (~0/0). Useful to calculate gl_BaseVertex as an AND of firstvertex
902 * and is_indexed_draw.
903 */
904 int is_indexed_draw;
905 } derived_params;
906
907 /**
908 * Buffer and offset used for GL_ARB_shader_draw_parameters which contains
909 * parameters that are not present in the indirect buffer. They will go in
910 * their own vertex element.
911 */
912 struct brw_bo *derived_draw_params_bo;
913 uint32_t derived_draw_params_offset;
914
915 /**
916 * Pointer to the the buffer storing the indirect draw parameters. It
917 * currently only stores the number of requested draw calls but more
918 * parameters could potentially be added.
919 */
920 struct brw_bo *draw_params_count_bo;
921 uint32_t draw_params_count_offset;
922
923 /**
924 * Draw indirect buffer.
925 */
926 unsigned draw_indirect_stride;
927 GLsizeiptr draw_indirect_offset;
928 struct gl_buffer_object *draw_indirect_data;
929 } draw;
930
931 struct {
932 /**
933 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
934 * an indirect call, and num_work_groups_offset is valid. Otherwise,
935 * num_work_groups is set based on glDispatchCompute.
936 */
937 struct brw_bo *num_work_groups_bo;
938 GLintptr num_work_groups_offset;
939 const GLuint *num_work_groups;
940 /**
941 * This is only used alongside ARB_compute_variable_group_size when the
942 * local work group size is variable, otherwise it's NULL.
943 */
944 const GLuint *group_size;
945 } compute;
946
947 struct {
948 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
949 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
950
951 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
952 GLuint nr_enabled;
953 GLuint nr_buffers;
954
955 /* Summary of size and varying of active arrays, so we can check
956 * for changes to this state:
957 */
958 bool index_bounds_valid;
959 unsigned int min_index, max_index;
960
961 /* Offset from start of vertex buffer so we can avoid redefining
962 * the same VB packed over and over again.
963 */
964 unsigned int start_vertex_bias;
965
966 /**
967 * Certain vertex attribute formats aren't natively handled by the
968 * hardware and require special VS code to fix up their values.
969 *
970 * These bitfields indicate which workarounds are needed.
971 */
972 uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
973
974 /* High bits of the last seen vertex buffer address (for workarounds). */
975 uint16_t last_bo_high_bits[33];
976 } vb;
977
978 struct {
979 /**
980 * Index buffer for this draw_prims call.
981 *
982 * Updates are signaled by BRW_NEW_INDICES.
983 */
984 const struct _mesa_index_buffer *ib;
985
986 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
987 struct brw_bo *bo;
988 uint32_t size;
989 unsigned index_size;
990
991 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
992 * avoid re-uploading the IB packet over and over if we're actually
993 * referencing the same index buffer.
994 */
995 unsigned int start_vertex_offset;
996
997 /* High bits of the last seen index buffer address (for workarounds). */
998 uint16_t last_bo_high_bits;
999
1000 /* Used to understand is GPU state of primitive restart is up to date */
1001 bool enable_cut_index;
1002 } ib;
1003
1004 /* Active vertex program:
1005 */
1006 struct gl_program *programs[MESA_SHADER_STAGES];
1007
1008 /**
1009 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1010 * that we don't have to reemit that state every time we change FBOs.
1011 */
1012 unsigned int num_samples;
1013
1014 /* BRW_NEW_URB_ALLOCATIONS:
1015 */
1016 struct {
1017 GLuint vsize; /* vertex size plus header in urb registers */
1018 GLuint gsize; /* GS output size in urb registers */
1019 GLuint hsize; /* Tessellation control output size in urb registers */
1020 GLuint dsize; /* Tessellation evaluation output size in urb registers */
1021 GLuint csize; /* constant buffer size in urb registers */
1022 GLuint sfsize; /* setup data size in urb registers */
1023
1024 bool constrained;
1025
1026 GLuint nr_vs_entries;
1027 GLuint nr_hs_entries;
1028 GLuint nr_ds_entries;
1029 GLuint nr_gs_entries;
1030 GLuint nr_clip_entries;
1031 GLuint nr_sf_entries;
1032 GLuint nr_cs_entries;
1033
1034 GLuint vs_start;
1035 GLuint hs_start;
1036 GLuint ds_start;
1037 GLuint gs_start;
1038 GLuint clip_start;
1039 GLuint sf_start;
1040 GLuint cs_start;
1041 /**
1042 * URB size in the current configuration. The units this is expressed
1043 * in are somewhat inconsistent, see gen_device_info::urb::size.
1044 *
1045 * FINISHME: Represent the URB size consistently in KB on all platforms.
1046 */
1047 GLuint size;
1048
1049 /* True if the most recently sent _3DSTATE_URB message allocated
1050 * URB space for the GS.
1051 */
1052 bool gs_present;
1053
1054 /* True if the most recently sent _3DSTATE_URB message allocated
1055 * URB space for the HS and DS.
1056 */
1057 bool tess_present;
1058 } urb;
1059
1060
1061 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1062 struct {
1063 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
1064 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
1065 GLuint clip_start;
1066 GLuint clip_size;
1067 GLuint vs_start;
1068 GLuint vs_size;
1069 GLuint total_size;
1070
1071 /**
1072 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1073 * for upload to the CURBE.
1074 */
1075 struct brw_bo *curbe_bo;
1076 /** Offset within curbe_bo of space for current curbe entry */
1077 GLuint curbe_offset;
1078 } curbe;
1079
1080 /**
1081 * Layout of vertex data exiting the geometry portion of the pipleine.
1082 * This comes from the last enabled shader stage (GS, DS, or VS).
1083 *
1084 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1085 */
1086 struct brw_vue_map vue_map_geom_out;
1087
1088 struct {
1089 struct brw_stage_state base;
1090 } vs;
1091
1092 struct {
1093 struct brw_stage_state base;
1094 } tcs;
1095
1096 struct {
1097 struct brw_stage_state base;
1098 } tes;
1099
1100 struct {
1101 struct brw_stage_state base;
1102
1103 /**
1104 * True if the 3DSTATE_GS command most recently emitted to the 3D
1105 * pipeline enabled the GS; false otherwise.
1106 */
1107 bool enabled;
1108 } gs;
1109
1110 struct {
1111 struct brw_ff_gs_prog_data *prog_data;
1112
1113 bool prog_active;
1114 /** Offset in the program cache to the CLIP program pre-gen6 */
1115 uint32_t prog_offset;
1116 uint32_t state_offset;
1117
1118 uint32_t bind_bo_offset;
1119 /**
1120 * Surface offsets for the binding table. We only need surfaces to
1121 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1122 * need in this case.
1123 */
1124 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS];
1125 } ff_gs;
1126
1127 struct {
1128 struct brw_clip_prog_data *prog_data;
1129
1130 /** Offset in the program cache to the CLIP program pre-gen6 */
1131 uint32_t prog_offset;
1132
1133 /* Offset in the batch to the CLIP state on pre-gen6. */
1134 uint32_t state_offset;
1135
1136 /* As of gen6, this is the offset in the batch to the CLIP VP,
1137 * instead of vp_bo.
1138 */
1139 uint32_t vp_offset;
1140
1141 /**
1142 * The number of viewports to use. If gl_ViewportIndex is written,
1143 * we can have up to ctx->Const.MaxViewports viewports. If not,
1144 * the viewport index is always 0, so we can only emit one.
1145 */
1146 uint8_t viewport_count;
1147 } clip;
1148
1149
1150 struct {
1151 struct brw_sf_prog_data *prog_data;
1152
1153 /** Offset in the program cache to the CLIP program pre-gen6 */
1154 uint32_t prog_offset;
1155 uint32_t state_offset;
1156 uint32_t vp_offset;
1157 } sf;
1158
1159 struct {
1160 struct brw_stage_state base;
1161
1162 /**
1163 * Buffer object used in place of multisampled null render targets on
1164 * Gen6. See brw_emit_null_surface_state().
1165 */
1166 struct brw_bo *multisampled_null_render_target_bo;
1167
1168 float offset_clamp;
1169 } wm;
1170
1171 struct {
1172 struct brw_stage_state base;
1173 } cs;
1174
1175 struct {
1176 uint32_t state_offset;
1177 uint32_t blend_state_offset;
1178 uint32_t depth_stencil_state_offset;
1179 uint32_t vp_offset;
1180 } cc;
1181
1182 struct {
1183 struct brw_query_object *obj;
1184 bool begin_emitted;
1185 } query;
1186
1187 struct {
1188 enum brw_predicate_state state;
1189 bool supported;
1190 } predicate;
1191
1192 struct gen_perf_context *perf_ctx;
1193
1194 int num_atoms[BRW_NUM_PIPELINES];
1195 const struct brw_tracked_state render_atoms[76];
1196 const struct brw_tracked_state compute_atoms[11];
1197
1198 const enum isl_format *mesa_to_isl_render_format;
1199 const bool *mesa_format_supports_render;
1200
1201 /* PrimitiveRestart */
1202 struct {
1203 bool in_progress;
1204 bool enable_cut_index;
1205 } prim_restart;
1206
1207 /** Computed depth/stencil/hiz state from the current attached
1208 * renderbuffers, valid only during the drawing state upload loop after
1209 * brw_workaround_depthstencil_alignment().
1210 */
1211 struct {
1212 /* Inter-tile (page-aligned) byte offsets. */
1213 uint32_t depth_offset;
1214 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1215 * used for Gen < 6.
1216 */
1217 uint32_t tile_x, tile_y;
1218 } depthstencil;
1219
1220 uint32_t num_instances;
1221 int basevertex;
1222 int baseinstance;
1223
1224 struct {
1225 const struct gen_l3_config *config;
1226 } l3;
1227
1228 struct {
1229 struct brw_bo *bo;
1230 const char **names;
1231 int *ids;
1232 enum shader_time_shader_type *types;
1233 struct shader_times *cumulative;
1234 int num_entries;
1235 int max_entries;
1236 double report_time;
1237 } shader_time;
1238
1239 struct brw_fast_clear_state *fast_clear_state;
1240
1241 /* Array of aux usages to use for drawing. Aux usage for render targets is
1242 * a bit more complex than simply calling a single function so we need some
1243 * way of passing it form brw_draw.c to surface state setup.
1244 */
1245 enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS];
1246
1247 enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask;
1248
1249 /** Last rendering scale argument provided to brw_emit_hashing_mode(). */
1250 unsigned current_hash_scale;
1251
1252 __DRIcontext *driContext;
1253 struct intel_screen *screen;
1254 };
1255
1256 /* brw_clear.c */
1257 extern void intelInitClearFuncs(struct dd_function_table *functions);
1258
1259 /*======================================================================
1260 * brw_context.c
1261 */
1262 extern const char *const brw_vendor_string;
1263
1264 extern const char *
1265 brw_get_renderer_string(const struct intel_screen *screen);
1266
1267 enum {
1268 DRI_CONF_BO_REUSE_DISABLED,
1269 DRI_CONF_BO_REUSE_ALL
1270 };
1271
1272 void intel_update_renderbuffers(__DRIcontext *context,
1273 __DRIdrawable *drawable);
1274 void intel_prepare_render(struct brw_context *brw);
1275
1276 void gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
1277 mesa_format format,
1278 enum isl_aux_usage aux_usage);
1279
1280 void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
1281 bool *draw_aux_buffer_disabled);
1282
1283 void intel_resolve_for_dri2_flush(struct brw_context *brw,
1284 __DRIdrawable *drawable);
1285
1286 GLboolean brwCreateContext(gl_api api,
1287 const struct gl_config *mesaVis,
1288 __DRIcontext *driContextPriv,
1289 const struct __DriverContextConfig *ctx_config,
1290 unsigned *error,
1291 void *sharedContextPrivate);
1292
1293 /*======================================================================
1294 * brw_misc_state.c
1295 */
1296 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1297 GLbitfield clear_mask);
1298 void brw_emit_hashing_mode(struct brw_context *brw, unsigned width,
1299 unsigned height, unsigned scale);
1300
1301 /* brw_object_purgeable.c */
1302 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1303
1304 /*======================================================================
1305 * brw_queryobj.c
1306 */
1307 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1308 void gen4_init_queryobj_functions(struct dd_function_table *functions);
1309 void brw_emit_query_begin(struct brw_context *brw);
1310 void brw_emit_query_end(struct brw_context *brw);
1311 void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q);
1312 bool brw_is_query_pipelined(struct brw_query_object *query);
1313 uint64_t brw_raw_timestamp_delta(struct brw_context *brw,
1314 uint64_t time0, uint64_t time1);
1315
1316 /** gen6_queryobj.c */
1317 void gen6_init_queryobj_functions(struct dd_function_table *functions);
1318 void brw_write_timestamp(struct brw_context *brw, struct brw_bo *bo, int idx);
1319 void brw_write_depth_count(struct brw_context *brw, struct brw_bo *bo, int idx);
1320
1321 /** hsw_queryobj.c */
1322 void hsw_overflow_result_to_gpr0(struct brw_context *brw,
1323 struct brw_query_object *query,
1324 int count);
1325 void hsw_init_queryobj_functions(struct dd_function_table *functions);
1326
1327 /** brw_conditional_render.c */
1328 void brw_init_conditional_render_functions(struct dd_function_table *functions);
1329 bool brw_check_conditional_render(struct brw_context *brw);
1330
1331 /** intel_batchbuffer.c */
1332 void brw_load_register_mem(struct brw_context *brw,
1333 uint32_t reg,
1334 struct brw_bo *bo,
1335 uint32_t offset);
1336 void brw_load_register_mem64(struct brw_context *brw,
1337 uint32_t reg,
1338 struct brw_bo *bo,
1339 uint32_t offset);
1340 void brw_store_register_mem32(struct brw_context *brw,
1341 struct brw_bo *bo, uint32_t reg, uint32_t offset);
1342 void brw_store_register_mem64(struct brw_context *brw,
1343 struct brw_bo *bo, uint32_t reg, uint32_t offset);
1344 void brw_load_register_imm32(struct brw_context *brw,
1345 uint32_t reg, uint32_t imm);
1346 void brw_load_register_imm64(struct brw_context *brw,
1347 uint32_t reg, uint64_t imm);
1348 void brw_load_register_reg(struct brw_context *brw, uint32_t dst,
1349 uint32_t src);
1350 void brw_load_register_reg64(struct brw_context *brw, uint32_t dst,
1351 uint32_t src);
1352 void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo,
1353 uint32_t offset, uint32_t imm);
1354 void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo,
1355 uint32_t offset, uint64_t imm);
1356
1357 /*======================================================================
1358 * intel_tex_validate.c
1359 */
1360 void brw_validate_textures( struct brw_context *brw );
1361
1362
1363 /*======================================================================
1364 * brw_program.c
1365 */
1366 void brwInitFragProgFuncs( struct dd_function_table *functions );
1367
1368 void brw_get_scratch_bo(struct brw_context *brw,
1369 struct brw_bo **scratch_bo, int size);
1370 void brw_alloc_stage_scratch(struct brw_context *brw,
1371 struct brw_stage_state *stage_state,
1372 unsigned per_thread_size);
1373 void brw_init_shader_time(struct brw_context *brw);
1374 int brw_get_shader_time_index(struct brw_context *brw,
1375 struct gl_program *prog,
1376 enum shader_time_shader_type type,
1377 bool is_glsl_sh);
1378 void brw_collect_and_report_shader_time(struct brw_context *brw);
1379 void brw_destroy_shader_time(struct brw_context *brw);
1380
1381 /* brw_urb.c
1382 */
1383 void brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
1384 unsigned vsize, unsigned sfsize);
1385 void brw_upload_urb_fence(struct brw_context *brw);
1386
1387 /* brw_curbe.c
1388 */
1389 void brw_upload_cs_urb_state(struct brw_context *brw);
1390
1391 /* brw_vs.c */
1392 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1393
1394 /* brw_draw_upload.c */
1395 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1396 const struct gl_vertex_format *glformat);
1397
1398 static inline unsigned
brw_get_index_type(unsigned index_size)1399 brw_get_index_type(unsigned index_size)
1400 {
1401 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1402 * respectively.
1403 */
1404 return index_size >> 1;
1405 }
1406
1407 void brw_prepare_vertices(struct brw_context *brw);
1408
1409 /* brw_wm_surface_state.c */
1410 void brw_update_buffer_texture_surface(struct gl_context *ctx,
1411 unsigned unit,
1412 uint32_t *surf_offset);
1413 void
1414 brw_update_sol_surface(struct brw_context *brw,
1415 struct gl_buffer_object *buffer_obj,
1416 uint32_t *out_offset, unsigned num_vector_components,
1417 unsigned stride_dwords, unsigned offset_dwords);
1418 void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
1419 struct brw_stage_state *stage_state,
1420 struct brw_stage_prog_data *prog_data);
1421 void brw_upload_image_surfaces(struct brw_context *brw,
1422 const struct gl_program *prog,
1423 struct brw_stage_state *stage_state,
1424 struct brw_stage_prog_data *prog_data);
1425
1426 /* brw_surface_formats.c */
1427 void intel_screen_init_surface_formats(struct intel_screen *screen);
1428 void brw_init_surface_formats(struct brw_context *brw);
1429 bool brw_render_target_supported(struct brw_context *brw,
1430 struct gl_renderbuffer *rb);
1431 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
1432
1433 /* brw_performance_query.c */
1434 void brw_init_performance_queries(struct brw_context *brw);
1435
1436 /* intel_extensions.c */
1437 extern void intelInitExtensions(struct gl_context *ctx);
1438
1439 /* intel_state.c */
1440 extern int intel_translate_shadow_compare_func(GLenum func);
1441 extern int intel_translate_compare_func(GLenum func);
1442 extern int intel_translate_stencil_op(GLenum op);
1443
1444 /* brw_sync.c */
1445 void brw_init_syncobj_functions(struct dd_function_table *functions);
1446
1447 /* gen6_sol.c */
1448 struct gl_transform_feedback_object *
1449 brw_new_transform_feedback(struct gl_context *ctx, GLuint name);
1450 void
1451 brw_delete_transform_feedback(struct gl_context *ctx,
1452 struct gl_transform_feedback_object *obj);
1453 void
1454 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1455 struct gl_transform_feedback_object *obj);
1456 void
1457 brw_end_transform_feedback(struct gl_context *ctx,
1458 struct gl_transform_feedback_object *obj);
1459 void
1460 brw_pause_transform_feedback(struct gl_context *ctx,
1461 struct gl_transform_feedback_object *obj);
1462 void
1463 brw_resume_transform_feedback(struct gl_context *ctx,
1464 struct gl_transform_feedback_object *obj);
1465 void
1466 brw_save_primitives_written_counters(struct brw_context *brw,
1467 struct brw_transform_feedback_object *obj);
1468 GLsizei
1469 brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
1470 struct gl_transform_feedback_object *obj,
1471 GLuint stream);
1472
1473 /* gen7_sol_state.c */
1474 void
1475 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1476 struct gl_transform_feedback_object *obj);
1477 void
1478 gen7_end_transform_feedback(struct gl_context *ctx,
1479 struct gl_transform_feedback_object *obj);
1480 void
1481 gen7_pause_transform_feedback(struct gl_context *ctx,
1482 struct gl_transform_feedback_object *obj);
1483 void
1484 gen7_resume_transform_feedback(struct gl_context *ctx,
1485 struct gl_transform_feedback_object *obj);
1486
1487 /* hsw_sol.c */
1488 void
1489 hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1490 struct gl_transform_feedback_object *obj);
1491 void
1492 hsw_end_transform_feedback(struct gl_context *ctx,
1493 struct gl_transform_feedback_object *obj);
1494 void
1495 hsw_pause_transform_feedback(struct gl_context *ctx,
1496 struct gl_transform_feedback_object *obj);
1497 void
1498 hsw_resume_transform_feedback(struct gl_context *ctx,
1499 struct gl_transform_feedback_object *obj);
1500
1501 /* brw_blorp_blit.cpp */
1502 GLbitfield
1503 brw_blorp_framebuffer(struct brw_context *brw,
1504 struct gl_framebuffer *readFb,
1505 struct gl_framebuffer *drawFb,
1506 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1507 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1508 GLbitfield mask, GLenum filter);
1509
1510 bool
1511 brw_blorp_copytexsubimage(struct brw_context *brw,
1512 struct gl_renderbuffer *src_rb,
1513 struct gl_texture_image *dst_image,
1514 int slice,
1515 int srcX0, int srcY0,
1516 int dstX0, int dstY0,
1517 int width, int height);
1518
1519 /* brw_generate_mipmap.c */
1520 void brw_generate_mipmap(struct gl_context *ctx, GLenum target,
1521 struct gl_texture_object *tex_obj);
1522
1523 void
1524 gen6_get_sample_position(struct gl_context *ctx,
1525 struct gl_framebuffer *fb,
1526 GLuint index,
1527 GLfloat *result);
1528
1529 /* gen8_multisample_state.c */
1530 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
1531
1532 /* gen7_l3_state.c */
1533 void brw_emit_l3_state(struct brw_context *brw);
1534
1535 /* gen7_urb.c */
1536 void
1537 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
1538 unsigned hs_size, unsigned ds_size,
1539 unsigned gs_size, unsigned fs_size);
1540
1541 void
1542 gen6_upload_urb(struct brw_context *brw, unsigned vs_size,
1543 bool gs_present, unsigned gs_size);
1544 void
1545 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
1546 bool gs_present, bool tess_present);
1547
1548 /* brw_reset.c */
1549 extern GLenum
1550 brw_get_graphics_reset_status(struct gl_context *ctx);
1551 void
1552 brw_check_for_reset(struct brw_context *brw);
1553
1554 /* brw_compute.c */
1555 extern void
1556 brw_init_compute_functions(struct dd_function_table *functions);
1557
1558 /* brw_program_binary.c */
1559 extern void
1560 brw_program_binary_init(unsigned device_id);
1561 extern void
1562 brw_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1);
1563 void brw_serialize_program_binary(struct gl_context *ctx,
1564 struct gl_shader_program *sh_prog,
1565 struct gl_program *prog);
1566 extern void
1567 brw_deserialize_program_binary(struct gl_context *ctx,
1568 struct gl_shader_program *shProg,
1569 struct gl_program *prog);
1570 void
1571 brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog);
1572 void
1573 brw_program_deserialize_driver_blob(struct gl_context *ctx,
1574 struct gl_program *prog,
1575 gl_shader_stage stage);
1576
1577 /*======================================================================
1578 * Inline conversion functions. These are better-typed than the
1579 * macros used previously:
1580 */
1581 static inline struct brw_context *
brw_context(struct gl_context * ctx)1582 brw_context( struct gl_context *ctx )
1583 {
1584 return (struct brw_context *)ctx;
1585 }
1586
1587 static inline struct brw_program *
brw_program(struct gl_program * p)1588 brw_program(struct gl_program *p)
1589 {
1590 return (struct brw_program *) p;
1591 }
1592
1593 static inline const struct brw_program *
brw_program_const(const struct gl_program * p)1594 brw_program_const(const struct gl_program *p)
1595 {
1596 return (const struct brw_program *) p;
1597 }
1598
1599 static inline bool
brw_depth_writes_enabled(const struct brw_context * brw)1600 brw_depth_writes_enabled(const struct brw_context *brw)
1601 {
1602 const struct gl_context *ctx = &brw->ctx;
1603
1604 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1605 * because it would just overwrite the existing depth value with itself.
1606 *
1607 * These bonus depth writes not only use bandwidth, but they also can
1608 * prevent early depth processing. For example, if the pixel shader
1609 * discards, the hardware must invoke the to determine whether or not
1610 * to do the depth write. If writes are disabled, we may still be able
1611 * to do the depth test before the shader, and skip the shader execution.
1612 *
1613 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1614 * a programming note saying to disable depth writes for EQUAL.
1615 */
1616 return ctx->Depth.Test && ctx->Depth.Mask && ctx->Depth.Func != GL_EQUAL;
1617 }
1618
1619 void
1620 brw_emit_depthbuffer(struct brw_context *brw);
1621
1622 uint32_t get_hw_prim_for_gl_prim(int mode);
1623
1624 void
1625 gen6_upload_push_constants(struct brw_context *brw,
1626 const struct gl_program *prog,
1627 const struct brw_stage_prog_data *prog_data,
1628 struct brw_stage_state *stage_state);
1629
1630 bool
1631 gen9_use_linear_1d_layout(const struct brw_context *brw,
1632 const struct intel_mipmap_tree *mt);
1633
1634 /* brw_queryformat.c */
1635 void brw_query_internal_format(struct gl_context *ctx, GLenum target,
1636 GLenum internalFormat, GLenum pname,
1637 GLint *params);
1638
1639 #ifdef __cplusplus
1640 }
1641 #endif
1642
1643 #endif
1644