1 /*
2 * \file trc_cmp_cfg_etmv4.cpp
3 * \brief OpenCSD :
4 *
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include "opencsd/etmv4/trc_cmp_cfg_etmv4.h"
36
EtmV4Config()37 EtmV4Config::EtmV4Config()
38 {
39 m_cfg.reg_idr0 = 0x28000EA1;
40 m_cfg.reg_idr1 = 0x4100F403;
41 m_cfg.reg_idr2 = 0x00000488;
42 m_cfg.reg_idr8 = 0;
43 m_cfg.reg_idr9 = 0;
44 m_cfg.reg_idr10 = 0;
45 m_cfg.reg_idr11 = 0;
46 m_cfg.reg_idr12 = 0;
47 m_cfg.reg_idr13 = 0;
48 m_cfg.reg_configr = 0xC1;
49 m_cfg.reg_traceidr = 0;
50 m_cfg.arch_ver = ARCH_V7;
51 m_cfg.core_prof = profile_CortexA;
52
53 PrivateInit();
54 }
55
EtmV4Config(const ocsd_etmv4_cfg * cfg_regs)56 EtmV4Config::EtmV4Config(const ocsd_etmv4_cfg *cfg_regs)
57 {
58 m_cfg = *cfg_regs;
59 PrivateInit();
60 }
61
operator =(const ocsd_etmv4_cfg * p_cfg)62 EtmV4Config & EtmV4Config::operator=(const ocsd_etmv4_cfg *p_cfg)
63 {
64 m_cfg = *p_cfg;
65 PrivateInit();
66 return *this;
67 }
68
PrivateInit()69 void EtmV4Config::PrivateInit()
70 {
71 m_QSuppCalc = false;
72 m_QSuppFilter = false;
73 m_QSuppType = Q_NONE;
74 m_VMIDSzCalc = false;
75 m_VMIDSize = 0;
76 m_condTraceCalc = false;
77 m_CondTrace = COND_TR_DIS;
78 m_MajVer = (uint8_t)((m_cfg.reg_idr1 >> 8) & 0xF);
79 m_MinVer = (uint8_t)((m_cfg.reg_idr1 >> 4) & 0xF);
80 }
81
CalcQSupp()82 void EtmV4Config::CalcQSupp()
83 {
84 QSuppType qtypes[] = {
85 Q_NONE,
86 Q_ICOUNT_ONLY,
87 Q_NO_ICOUNT_ONLY,
88 Q_FULL
89 };
90 uint8_t Qsupp = (m_cfg.reg_idr0 >> 15) & 0x3;
91 m_QSuppType = qtypes[Qsupp];
92 m_QSuppFilter = (bool)((m_cfg.reg_idr0 & 0x4000) == 0x4000) && (m_QSuppType != Q_NONE);
93 m_QSuppCalc = true;
94 }
95
CalcVMIDSize()96 void EtmV4Config::CalcVMIDSize()
97 {
98 uint32_t vmidszF = (m_cfg.reg_idr2 >> 10) & 0x1F;
99 if(vmidszF == 1)
100 m_VMIDSize = 8;
101 else if(FullVersion() > 0x40)
102 {
103 if(vmidszF == 2)
104 m_VMIDSize = 16;
105 else if(vmidszF == 4)
106 m_VMIDSize = 32;
107 }
108 m_VMIDSzCalc = true;
109 }
110
111 /* End of File trc_cmp_cfg_etmv4.cpp */
112