1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_pack_color.h"
29 #include "util/u_memory.h"
30 #include "util/u_framebuffer.h"
31 #include "util/u_dual_blend.h"
32
r600_translate_blend_function(int blend_func)33 static uint32_t r600_translate_blend_function(int blend_func)
34 {
35 switch (blend_func) {
36 case PIPE_BLEND_ADD:
37 return V_028804_COMB_DST_PLUS_SRC;
38 case PIPE_BLEND_SUBTRACT:
39 return V_028804_COMB_SRC_MINUS_DST;
40 case PIPE_BLEND_REVERSE_SUBTRACT:
41 return V_028804_COMB_DST_MINUS_SRC;
42 case PIPE_BLEND_MIN:
43 return V_028804_COMB_MIN_DST_SRC;
44 case PIPE_BLEND_MAX:
45 return V_028804_COMB_MAX_DST_SRC;
46 default:
47 R600_ERR("Unknown blend function %d\n", blend_func);
48 assert(0);
49 break;
50 }
51 return 0;
52 }
53
r600_translate_blend_factor(int blend_fact)54 static uint32_t r600_translate_blend_factor(int blend_fact)
55 {
56 switch (blend_fact) {
57 case PIPE_BLENDFACTOR_ONE:
58 return V_028804_BLEND_ONE;
59 case PIPE_BLENDFACTOR_SRC_COLOR:
60 return V_028804_BLEND_SRC_COLOR;
61 case PIPE_BLENDFACTOR_SRC_ALPHA:
62 return V_028804_BLEND_SRC_ALPHA;
63 case PIPE_BLENDFACTOR_DST_ALPHA:
64 return V_028804_BLEND_DST_ALPHA;
65 case PIPE_BLENDFACTOR_DST_COLOR:
66 return V_028804_BLEND_DST_COLOR;
67 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
68 return V_028804_BLEND_SRC_ALPHA_SATURATE;
69 case PIPE_BLENDFACTOR_CONST_COLOR:
70 return V_028804_BLEND_CONST_COLOR;
71 case PIPE_BLENDFACTOR_CONST_ALPHA:
72 return V_028804_BLEND_CONST_ALPHA;
73 case PIPE_BLENDFACTOR_ZERO:
74 return V_028804_BLEND_ZERO;
75 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
76 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
77 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
78 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
79 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
80 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
81 case PIPE_BLENDFACTOR_INV_DST_COLOR:
82 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
83 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
84 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
85 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
86 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
87 case PIPE_BLENDFACTOR_SRC1_COLOR:
88 return V_028804_BLEND_SRC1_COLOR;
89 case PIPE_BLENDFACTOR_SRC1_ALPHA:
90 return V_028804_BLEND_SRC1_ALPHA;
91 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
92 return V_028804_BLEND_INV_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
94 return V_028804_BLEND_INV_SRC1_ALPHA;
95 default:
96 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
97 assert(0);
98 break;
99 }
100 return 0;
101 }
102
r600_tex_dim(unsigned dim,unsigned nr_samples)103 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
104 {
105 switch (dim) {
106 default:
107 case PIPE_TEXTURE_1D:
108 return V_038000_SQ_TEX_DIM_1D;
109 case PIPE_TEXTURE_1D_ARRAY:
110 return V_038000_SQ_TEX_DIM_1D_ARRAY;
111 case PIPE_TEXTURE_2D:
112 case PIPE_TEXTURE_RECT:
113 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
114 V_038000_SQ_TEX_DIM_2D;
115 case PIPE_TEXTURE_2D_ARRAY:
116 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
117 V_038000_SQ_TEX_DIM_2D_ARRAY;
118 case PIPE_TEXTURE_3D:
119 return V_038000_SQ_TEX_DIM_3D;
120 case PIPE_TEXTURE_CUBE:
121 case PIPE_TEXTURE_CUBE_ARRAY:
122 return V_038000_SQ_TEX_DIM_CUBEMAP;
123 }
124 }
125
r600_translate_dbformat(enum pipe_format format)126 static uint32_t r600_translate_dbformat(enum pipe_format format)
127 {
128 switch (format) {
129 case PIPE_FORMAT_Z16_UNORM:
130 return V_028010_DEPTH_16;
131 case PIPE_FORMAT_Z24X8_UNORM:
132 return V_028010_DEPTH_X8_24;
133 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
134 return V_028010_DEPTH_8_24;
135 case PIPE_FORMAT_Z32_FLOAT:
136 return V_028010_DEPTH_32_FLOAT;
137 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
138 return V_028010_DEPTH_X24_8_32_FLOAT;
139 default:
140 return ~0U;
141 }
142 }
143
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)144 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
145 {
146 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
147 FALSE) != ~0U;
148 }
149
r600_is_colorbuffer_format_supported(enum chip_class chip,enum pipe_format format)150 static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
151 {
152 return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
153 r600_translate_colorswap(format, FALSE) != ~0U;
154 }
155
r600_is_zs_format_supported(enum pipe_format format)156 static bool r600_is_zs_format_supported(enum pipe_format format)
157 {
158 return r600_translate_dbformat(format) != ~0U;
159 }
160
r600_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)161 bool r600_is_format_supported(struct pipe_screen *screen,
162 enum pipe_format format,
163 enum pipe_texture_target target,
164 unsigned sample_count,
165 unsigned storage_sample_count,
166 unsigned usage)
167 {
168 struct r600_screen *rscreen = (struct r600_screen*)screen;
169 unsigned retval = 0;
170
171 if (target >= PIPE_MAX_TEXTURE_TYPES) {
172 R600_ERR("r600: unsupported texture type %d\n", target);
173 return false;
174 }
175
176 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
177 return false;
178
179 if (sample_count > 1) {
180 if (!rscreen->has_msaa)
181 return false;
182
183 /* R11G11B10 is broken on R6xx. */
184 if (rscreen->b.chip_class == R600 &&
185 format == PIPE_FORMAT_R11G11B10_FLOAT)
186 return false;
187
188 /* MSAA integer colorbuffers hang. */
189 if (util_format_is_pure_integer(format) &&
190 !util_format_is_depth_or_stencil(format))
191 return false;
192
193 switch (sample_count) {
194 case 2:
195 case 4:
196 case 8:
197 break;
198 default:
199 return false;
200 }
201 }
202
203 if (usage & PIPE_BIND_SAMPLER_VIEW) {
204 if (target == PIPE_BUFFER) {
205 if (r600_is_vertex_format_supported(format))
206 retval |= PIPE_BIND_SAMPLER_VIEW;
207 } else {
208 if (r600_is_sampler_format_supported(screen, format))
209 retval |= PIPE_BIND_SAMPLER_VIEW;
210 }
211 }
212
213 if ((usage & (PIPE_BIND_RENDER_TARGET |
214 PIPE_BIND_DISPLAY_TARGET |
215 PIPE_BIND_SCANOUT |
216 PIPE_BIND_SHARED |
217 PIPE_BIND_BLENDABLE)) &&
218 r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
219 retval |= usage &
220 (PIPE_BIND_RENDER_TARGET |
221 PIPE_BIND_DISPLAY_TARGET |
222 PIPE_BIND_SCANOUT |
223 PIPE_BIND_SHARED);
224 if (!util_format_is_pure_integer(format) &&
225 !util_format_is_depth_or_stencil(format))
226 retval |= usage & PIPE_BIND_BLENDABLE;
227 }
228
229 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
230 r600_is_zs_format_supported(format)) {
231 retval |= PIPE_BIND_DEPTH_STENCIL;
232 }
233
234 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
235 r600_is_vertex_format_supported(format)) {
236 retval |= PIPE_BIND_VERTEX_BUFFER;
237 }
238
239 if ((usage & PIPE_BIND_LINEAR) &&
240 !util_format_is_compressed(format) &&
241 !(usage & PIPE_BIND_DEPTH_STENCIL))
242 retval |= PIPE_BIND_LINEAR;
243
244 return retval == usage;
245 }
246
r600_emit_polygon_offset(struct r600_context * rctx,struct r600_atom * a)247 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
248 {
249 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
250 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
251 float offset_units = state->offset_units;
252 float offset_scale = state->offset_scale;
253 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
254
255 if (!state->offset_units_unscaled) {
256 switch (state->zs_format) {
257 case PIPE_FORMAT_Z24X8_UNORM:
258 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
259 offset_units *= 2.0f;
260 pa_su_poly_offset_db_fmt_cntl =
261 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
262 break;
263 case PIPE_FORMAT_Z16_UNORM:
264 offset_units *= 4.0f;
265 pa_su_poly_offset_db_fmt_cntl =
266 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
267 break;
268 default:
269 pa_su_poly_offset_db_fmt_cntl =
270 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
271 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
272 }
273 }
274
275 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
276 radeon_emit(cs, fui(offset_scale));
277 radeon_emit(cs, fui(offset_units));
278 radeon_emit(cs, fui(offset_scale));
279 radeon_emit(cs, fui(offset_units));
280
281 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
282 pa_su_poly_offset_db_fmt_cntl);
283 }
284
r600_get_blend_control(const struct pipe_blend_state * state,unsigned i)285 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
286 {
287 int j = state->independent_blend_enable ? i : 0;
288
289 unsigned eqRGB = state->rt[j].rgb_func;
290 unsigned srcRGB = state->rt[j].rgb_src_factor;
291 unsigned dstRGB = state->rt[j].rgb_dst_factor;
292
293 unsigned eqA = state->rt[j].alpha_func;
294 unsigned srcA = state->rt[j].alpha_src_factor;
295 unsigned dstA = state->rt[j].alpha_dst_factor;
296 uint32_t bc = 0;
297
298 if (!state->rt[j].blend_enable)
299 return 0;
300
301 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
302 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
303 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
304
305 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
306 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
307 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
308 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
309 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
310 }
311 return bc;
312 }
313
r600_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)314 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
315 const struct pipe_blend_state *state,
316 int mode)
317 {
318 struct r600_context *rctx = (struct r600_context *)ctx;
319 uint32_t color_control = 0, target_mask = 0;
320 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
321
322 if (!blend) {
323 return NULL;
324 }
325
326 r600_init_command_buffer(&blend->buffer, 20);
327 r600_init_command_buffer(&blend->buffer_no_blend, 20);
328
329 /* R600 does not support per-MRT blends */
330 if (rctx->b.family > CHIP_R600)
331 color_control |= S_028808_PER_MRT_BLEND(1);
332
333 if (state->logicop_enable) {
334 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
335 } else {
336 color_control |= (0xcc << 16);
337 }
338 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
339 if (state->independent_blend_enable) {
340 for (int i = 0; i < 8; i++) {
341 if (state->rt[i].blend_enable) {
342 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
343 }
344 target_mask |= (state->rt[i].colormask << (4 * i));
345 }
346 } else {
347 for (int i = 0; i < 8; i++) {
348 if (state->rt[0].blend_enable) {
349 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
350 }
351 target_mask |= (state->rt[0].colormask << (4 * i));
352 }
353 }
354
355 if (target_mask)
356 color_control |= S_028808_SPECIAL_OP(mode);
357 else
358 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
359
360 /* only MRT0 has dual src blend */
361 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
362 blend->cb_target_mask = target_mask;
363 blend->cb_color_control = color_control;
364 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
365 blend->alpha_to_one = state->alpha_to_one;
366
367 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
368 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
369 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
370 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
371 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
372 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
373
374 /* Copy over the registers set so far into buffer_no_blend. */
375 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
376 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
377
378 /* Only add blend registers if blending is enabled. */
379 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
380 return blend;
381 }
382
383 /* The first R600 does not support per-MRT blends */
384 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
385 r600_get_blend_control(state, 0));
386
387 if (rctx->b.family > CHIP_R600) {
388 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
389 for (int i = 0; i < 8; i++) {
390 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
391 }
392 }
393 return blend;
394 }
395
r600_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)396 static void *r600_create_blend_state(struct pipe_context *ctx,
397 const struct pipe_blend_state *state)
398 {
399 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
400 }
401
r600_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)402 static void *r600_create_dsa_state(struct pipe_context *ctx,
403 const struct pipe_depth_stencil_alpha_state *state)
404 {
405 unsigned db_depth_control, alpha_test_control, alpha_ref;
406 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
407
408 if (!dsa) {
409 return NULL;
410 }
411
412 r600_init_command_buffer(&dsa->buffer, 3);
413
414 dsa->valuemask[0] = state->stencil[0].valuemask;
415 dsa->valuemask[1] = state->stencil[1].valuemask;
416 dsa->writemask[0] = state->stencil[0].writemask;
417 dsa->writemask[1] = state->stencil[1].writemask;
418 dsa->zwritemask = state->depth.writemask;
419
420 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
421 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
422 S_028800_ZFUNC(state->depth.func);
423
424 /* stencil */
425 if (state->stencil[0].enabled) {
426 db_depth_control |= S_028800_STENCIL_ENABLE(1);
427 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
428 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
429 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
430 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
431
432 if (state->stencil[1].enabled) {
433 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
434 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
435 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
436 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
437 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
438 }
439 }
440
441 /* alpha */
442 alpha_test_control = 0;
443 alpha_ref = 0;
444 if (state->alpha.enabled) {
445 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
446 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
447 alpha_ref = fui(state->alpha.ref_value);
448 }
449 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
450 dsa->alpha_ref = alpha_ref;
451
452 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
453 return dsa;
454 }
455
r600_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)456 static void *r600_create_rs_state(struct pipe_context *ctx,
457 const struct pipe_rasterizer_state *state)
458 {
459 struct r600_context *rctx = (struct r600_context *)ctx;
460 unsigned tmp, sc_mode_cntl, spi_interp;
461 float psize_min, psize_max;
462 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
463
464 if (!rs) {
465 return NULL;
466 }
467
468 r600_init_command_buffer(&rs->buffer, 30);
469
470 rs->scissor_enable = state->scissor;
471 rs->clip_halfz = state->clip_halfz;
472 rs->flatshade = state->flatshade;
473 rs->sprite_coord_enable = state->sprite_coord_enable;
474 rs->rasterizer_discard = state->rasterizer_discard;
475 rs->two_side = state->light_twoside;
476 rs->clip_plane_enable = state->clip_plane_enable;
477 rs->pa_sc_line_stipple = state->line_stipple_enable ?
478 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
479 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
480 rs->pa_cl_clip_cntl =
481 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
482 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
483 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
484 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
485 if (rctx->b.chip_class == R700) {
486 rs->pa_cl_clip_cntl |=
487 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
488 }
489 rs->multisample_enable = state->multisample;
490
491 /* offset */
492 rs->offset_units = state->offset_units;
493 rs->offset_scale = state->offset_scale * 16.0f;
494 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
495 rs->offset_units_unscaled = state->offset_units_unscaled;
496
497 if (state->point_size_per_vertex) {
498 psize_min = util_get_min_point_size(state);
499 psize_max = 8192;
500 } else {
501 /* Force the point size to be as if the vertex output was disabled. */
502 psize_min = state->point_size;
503 psize_max = state->point_size;
504 }
505
506 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
507 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
508 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
509 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
510 if (rctx->b.family == CHIP_RV770) {
511 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
512 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
513 }
514 if (rctx->b.chip_class >= R700) {
515 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
516 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
517 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
518 } else {
519 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
520 }
521
522 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
523 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
524 S_0286D4_PNT_SPRITE_OVRD_X(2) |
525 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
526 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
527 S_0286D4_PNT_SPRITE_OVRD_W(1);
528 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
529 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
530 }
531
532 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
533 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
534 tmp = r600_pack_float_12p4(state->point_size/2);
535 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
536 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
537 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
538 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
539 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
540 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
541 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
542
543 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
544 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
545 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
546 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
547 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
548 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
549
550 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
551 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
552 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
553 S_028814_FACE(!state->front_ccw) |
554 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
555 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
556 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
557 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
558 state->fill_back != PIPE_POLYGON_MODE_FILL) |
559 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
560 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
561 if (rctx->b.chip_class == R700) {
562 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
563 }
564 if (rctx->b.chip_class == R600) {
565 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
566 S_028350_MULTIPASS(state->rasterizer_discard));
567 }
568 return rs;
569 }
570
r600_tex_filter(unsigned filter,unsigned max_aniso)571 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
572 {
573 if (filter == PIPE_TEX_FILTER_LINEAR)
574 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
575 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
576 else
577 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
578 : V_03C000_SQ_TEX_XY_FILTER_POINT;
579 }
580
r600_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)581 static void *r600_create_sampler_state(struct pipe_context *ctx,
582 const struct pipe_sampler_state *state)
583 {
584 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
585 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
586 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
587 : state->max_anisotropy;
588 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
589
590 if (!ss) {
591 return NULL;
592 }
593
594 ss->seamless_cube_map = state->seamless_cube_map;
595 ss->border_color_use = sampler_state_needs_border_color(state);
596
597 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
598 ss->tex_sampler_words[0] =
599 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
600 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
601 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
602 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
603 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
604 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
605 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
606 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
607 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
608 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
609 ss->tex_sampler_words[1] =
610 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
611 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
612 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
613 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
614 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
615
616 if (ss->border_color_use) {
617 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
618 }
619 return ss;
620 }
621
622 static struct pipe_sampler_view *
texture_buffer_sampler_view(struct r600_pipe_sampler_view * view,unsigned width0,unsigned height0)623 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
624 unsigned width0, unsigned height0)
625
626 {
627 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
628 int stride = util_format_get_blocksize(view->base.format);
629 unsigned format, num_format, format_comp, endian;
630 uint64_t offset = view->base.u.buf.offset;
631 unsigned size = view->base.u.buf.size;
632
633 r600_vertex_data_type(view->base.format,
634 &format, &num_format, &format_comp,
635 &endian);
636
637 view->tex_resource = &tmp->resource;
638 view->skip_mip_address_reloc = true;
639
640 view->tex_resource_words[0] = offset;
641 view->tex_resource_words[1] = size - 1;
642 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
643 S_038008_STRIDE(stride) |
644 S_038008_DATA_FORMAT(format) |
645 S_038008_NUM_FORMAT_ALL(num_format) |
646 S_038008_FORMAT_COMP_ALL(format_comp) |
647 S_038008_ENDIAN_SWAP(endian);
648 view->tex_resource_words[3] = 0;
649 /*
650 * in theory dword 4 is for number of elements, for use with resinfo,
651 * but it seems to utterly fail to work, the amd gpu shader analyser
652 * uses a const buffer to store the element sizes for buffer txq
653 */
654 view->tex_resource_words[4] = 0;
655 view->tex_resource_words[5] = 0;
656 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
657 return &view->base;
658 }
659
660 struct pipe_sampler_view *
r600_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width_first_level,unsigned height_first_level)661 r600_create_sampler_view_custom(struct pipe_context *ctx,
662 struct pipe_resource *texture,
663 const struct pipe_sampler_view *state,
664 unsigned width_first_level, unsigned height_first_level)
665 {
666 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
667 struct r600_texture *tmp = (struct r600_texture*)texture;
668 unsigned format, endian;
669 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
670 unsigned char swizzle[4], array_mode = 0;
671 unsigned width, height, depth, offset_level, last_level;
672 bool do_endian_swap = FALSE;
673
674 if (!view)
675 return NULL;
676
677 /* initialize base object */
678 view->base = *state;
679 view->base.texture = NULL;
680 pipe_reference(NULL, &texture->reference);
681 view->base.texture = texture;
682 view->base.reference.count = 1;
683 view->base.context = ctx;
684
685 if (texture->target == PIPE_BUFFER)
686 return texture_buffer_sampler_view(view, texture->width0, 1);
687
688 swizzle[0] = state->swizzle_r;
689 swizzle[1] = state->swizzle_g;
690 swizzle[2] = state->swizzle_b;
691 swizzle[3] = state->swizzle_a;
692
693 if (R600_BIG_ENDIAN)
694 do_endian_swap = !tmp->db_compatible;
695
696 format = r600_translate_texformat(ctx->screen, state->format,
697 swizzle,
698 &word4, &yuv_format, do_endian_swap);
699 assert(format != ~0);
700 if (format == ~0) {
701 FREE(view);
702 return NULL;
703 }
704
705 if (state->format == PIPE_FORMAT_X24S8_UINT ||
706 state->format == PIPE_FORMAT_S8X24_UINT ||
707 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
708 state->format == PIPE_FORMAT_S8_UINT)
709 view->is_stencil_sampler = true;
710
711 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
712 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
713 FREE(view);
714 return NULL;
715 }
716 tmp = tmp->flushed_depth_texture;
717 }
718
719 endian = r600_colorformat_endian_swap(format, do_endian_swap);
720
721 offset_level = state->u.tex.first_level;
722 last_level = state->u.tex.last_level - offset_level;
723 width = width_first_level;
724 height = height_first_level;
725 depth = u_minify(texture->depth0, offset_level);
726 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
727
728 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
729 height = 1;
730 depth = texture->array_size;
731 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
732 depth = texture->array_size;
733 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
734 depth = texture->array_size / 6;
735
736 switch (tmp->surface.u.legacy.level[offset_level].mode) {
737 default:
738 case RADEON_SURF_MODE_LINEAR_ALIGNED:
739 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
740 break;
741 case RADEON_SURF_MODE_1D:
742 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
743 break;
744 case RADEON_SURF_MODE_2D:
745 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
746 break;
747 }
748
749 view->tex_resource = &tmp->resource;
750 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
751 S_038000_TILE_MODE(array_mode) |
752 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
753 S_038000_PITCH((pitch / 8) - 1) |
754 S_038000_TEX_WIDTH(width - 1));
755 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
756 S_038004_TEX_DEPTH(depth - 1) |
757 S_038004_DATA_FORMAT(format));
758 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
759 if (offset_level >= tmp->resource.b.b.last_level) {
760 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
761 } else {
762 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
763 }
764 view->tex_resource_words[4] = (word4 |
765 S_038010_REQUEST_SIZE(1) |
766 S_038010_ENDIAN_SWAP(endian) |
767 S_038010_BASE_LEVEL(0));
768 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
769 S_038014_LAST_ARRAY(state->u.tex.last_layer));
770 if (texture->nr_samples > 1) {
771 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
772 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
773 } else {
774 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
775 }
776 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
777 S_038018_MAX_ANISO(4 /* max 16 samples */));
778 return &view->base;
779 }
780
781 static struct pipe_sampler_view *
r600_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * tex,const struct pipe_sampler_view * state)782 r600_create_sampler_view(struct pipe_context *ctx,
783 struct pipe_resource *tex,
784 const struct pipe_sampler_view *state)
785 {
786 return r600_create_sampler_view_custom(ctx, tex, state,
787 u_minify(tex->width0, state->u.tex.first_level),
788 u_minify(tex->height0, state->u.tex.first_level));
789 }
790
r600_emit_clip_state(struct r600_context * rctx,struct r600_atom * atom)791 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
792 {
793 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
794 struct pipe_clip_state *state = &rctx->clip_state.state;
795
796 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
797 radeon_emit_array(cs, (unsigned*)state, 6*4);
798 }
799
r600_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)800 static void r600_set_polygon_stipple(struct pipe_context *ctx,
801 const struct pipe_poly_stipple *state)
802 {
803 }
804
r600_init_color_surface(struct r600_context * rctx,struct r600_surface * surf,bool force_cmask_fmask)805 static void r600_init_color_surface(struct r600_context *rctx,
806 struct r600_surface *surf,
807 bool force_cmask_fmask)
808 {
809 struct r600_screen *rscreen = rctx->screen;
810 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
811 unsigned level = surf->base.u.tex.level;
812 unsigned pitch, slice;
813 unsigned color_info;
814 unsigned color_view;
815 unsigned format, swap, ntype, endian;
816 unsigned offset;
817 const struct util_format_description *desc;
818 int i;
819 bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = FALSE;
820
821 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
822 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
823 rtex = rtex->flushed_depth_texture;
824 assert(rtex);
825 }
826
827 offset = rtex->surface.u.legacy.level[level].offset;
828 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
829 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
830
831 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
832 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
833 if (slice) {
834 slice = slice - 1;
835 }
836 color_info = 0;
837 switch (rtex->surface.u.legacy.level[level].mode) {
838 default:
839 case RADEON_SURF_MODE_LINEAR_ALIGNED:
840 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
841 break;
842 case RADEON_SURF_MODE_1D:
843 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
844 break;
845 case RADEON_SURF_MODE_2D:
846 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
847 break;
848 }
849
850 desc = util_format_description(surf->base.format);
851
852 for (i = 0; i < 4; i++) {
853 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
854 break;
855 }
856 }
857
858 ntype = V_0280A0_NUMBER_UNORM;
859 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
860 ntype = V_0280A0_NUMBER_SRGB;
861 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
862 if (desc->channel[i].normalized)
863 ntype = V_0280A0_NUMBER_SNORM;
864 else if (desc->channel[i].pure_integer)
865 ntype = V_0280A0_NUMBER_SINT;
866 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
867 if (desc->channel[i].normalized)
868 ntype = V_0280A0_NUMBER_UNORM;
869 else if (desc->channel[i].pure_integer)
870 ntype = V_0280A0_NUMBER_UINT;
871 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
872 ntype = V_0280A0_NUMBER_FLOAT;
873 }
874
875 if (R600_BIG_ENDIAN)
876 do_endian_swap = !rtex->db_compatible;
877
878 format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
879 do_endian_swap);
880 assert(format != ~0);
881
882 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
883 assert(swap != ~0);
884
885 endian = r600_colorformat_endian_swap(format, do_endian_swap);
886
887 /* blend clamp should be set for all NORM/SRGB types */
888 if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM ||
889 ntype == V_0280A0_NUMBER_SRGB)
890 blend_clamp = 1;
891
892 /* set blend bypass according to docs if SINT/UINT or
893 8/24 COLOR variants */
894 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
895 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
896 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
897 blend_clamp = 0;
898 blend_bypass = 1;
899 }
900
901 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
902
903 color_info |= S_0280A0_FORMAT(format) |
904 S_0280A0_COMP_SWAP(swap) |
905 S_0280A0_BLEND_BYPASS(blend_bypass) |
906 S_0280A0_BLEND_CLAMP(blend_clamp) |
907 S_0280A0_SIMPLE_FLOAT(1) |
908 S_0280A0_NUMBER_TYPE(ntype) |
909 S_0280A0_ENDIAN(endian);
910
911 /* EXPORT_NORM is an optimzation that can be enabled for better
912 * performance in certain cases
913 */
914 if (rctx->b.chip_class == R600) {
915 /* EXPORT_NORM can be enabled if:
916 * - 11-bit or smaller UNORM/SNORM/SRGB
917 * - BLEND_CLAMP is enabled
918 * - BLEND_FLOAT32 is disabled
919 */
920 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
921 (desc->channel[i].size < 12 &&
922 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
923 ntype != V_0280A0_NUMBER_UINT &&
924 ntype != V_0280A0_NUMBER_SINT) &&
925 G_0280A0_BLEND_CLAMP(color_info) &&
926 /* XXX this condition is always true since BLEND_FLOAT32 is never set (bug?). */
927 !G_0280A0_BLEND_FLOAT32(color_info)) {
928 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
929 surf->export_16bpc = true;
930 }
931 } else {
932 /* EXPORT_NORM can be enabled if:
933 * - 11-bit or smaller UNORM/SNORM/SRGB
934 * - 16-bit or smaller FLOAT
935 */
936 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
937 ((desc->channel[i].size < 12 &&
938 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
939 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
940 (desc->channel[i].size < 17 &&
941 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
942 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
943 surf->export_16bpc = true;
944 }
945 }
946
947 /* These might not always be initialized to zero. */
948 surf->cb_color_base = offset >> 8;
949 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
950 S_028060_SLICE_TILE_MAX(slice);
951 surf->cb_color_fmask = surf->cb_color_base;
952 surf->cb_color_cmask = surf->cb_color_base;
953 surf->cb_color_mask = 0;
954
955 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
956 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
957
958 if (rtex->cmask.size) {
959 surf->cb_color_cmask = rtex->cmask.offset >> 8;
960 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
961
962 if (rtex->fmask.size) {
963 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
964 surf->cb_color_fmask = rtex->fmask.offset >> 8;
965 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
966 } else { /* cmask only */
967 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
968 }
969 } else if (force_cmask_fmask) {
970 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
971 *
972 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
973 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
974 * because it's not an MSAA buffer.
975 */
976 struct r600_cmask_info cmask;
977 struct r600_fmask_info fmask;
978
979 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
980 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
981
982 /* CMASK. */
983 if (!rctx->dummy_cmask ||
984 rctx->dummy_cmask->b.b.width0 < cmask.size ||
985 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
986 struct pipe_transfer *transfer;
987 void *ptr;
988
989 r600_resource_reference(&rctx->dummy_cmask, NULL);
990 rctx->dummy_cmask = (struct r600_resource*)
991 r600_aligned_buffer_create(&rscreen->b.b, 0,
992 PIPE_USAGE_DEFAULT,
993 cmask.size, cmask.alignment);
994
995 if (unlikely(!rctx->dummy_cmask)) {
996 surf->color_initialized = false;
997 return;
998 }
999
1000 /* Set the contents to 0xCC. */
1001 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_MAP_WRITE, &transfer);
1002 memset(ptr, 0xCC, cmask.size);
1003 pipe_buffer_unmap(&rctx->b.b, transfer);
1004 }
1005 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1006
1007 /* FMASK. */
1008 if (!rctx->dummy_fmask ||
1009 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1010 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1011 r600_resource_reference(&rctx->dummy_fmask, NULL);
1012 rctx->dummy_fmask = (struct r600_resource*)
1013 r600_aligned_buffer_create(&rscreen->b.b, 0,
1014 PIPE_USAGE_DEFAULT,
1015 fmask.size, fmask.alignment);
1016
1017 if (unlikely(!rctx->dummy_fmask)) {
1018 surf->color_initialized = false;
1019 return;
1020 }
1021 }
1022 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1023
1024 /* Init the registers. */
1025 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1026 surf->cb_color_cmask = 0;
1027 surf->cb_color_fmask = 0;
1028 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1029 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1030 }
1031
1032 surf->cb_color_info = color_info;
1033 surf->cb_color_view = color_view;
1034 surf->color_initialized = true;
1035 }
1036
r600_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1037 static void r600_init_depth_surface(struct r600_context *rctx,
1038 struct r600_surface *surf)
1039 {
1040 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1041 unsigned level, pitch, slice, format, offset, array_mode;
1042
1043 level = surf->base.u.tex.level;
1044 offset = rtex->surface.u.legacy.level[level].offset;
1045 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
1046 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1047 if (slice) {
1048 slice = slice - 1;
1049 }
1050 switch (rtex->surface.u.legacy.level[level].mode) {
1051 case RADEON_SURF_MODE_2D:
1052 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1053 break;
1054 case RADEON_SURF_MODE_1D:
1055 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1056 default:
1057 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1058 break;
1059 }
1060
1061 format = r600_translate_dbformat(surf->base.format);
1062 assert(format != ~0);
1063
1064 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1065 surf->db_depth_base = offset >> 8;
1066 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1067 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1068 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1069 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1070
1071 if (r600_htile_enabled(rtex, level)) {
1072 surf->db_htile_data_base = rtex->htile_offset >> 8;
1073 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1074 S_028D24_HTILE_HEIGHT(1) |
1075 S_028D24_FULL_CACHE(1);
1076 /* preload is not working properly on r6xx/r7xx */
1077 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1078 }
1079
1080 surf->depth_initialized = true;
1081 }
1082
r600_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1083 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1084 const struct pipe_framebuffer_state *state)
1085 {
1086 struct r600_context *rctx = (struct r600_context *)ctx;
1087 struct r600_surface *surf;
1088 struct r600_texture *rtex;
1089 unsigned i;
1090 uint32_t target_mask = 0;
1091
1092 /* Flush TC when changing the framebuffer state, because the only
1093 * client not using TC that can change textures is the framebuffer.
1094 * Other places don't typically have to flush TC.
1095 */
1096 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1097 R600_CONTEXT_FLUSH_AND_INV |
1098 R600_CONTEXT_FLUSH_AND_INV_CB |
1099 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1100 R600_CONTEXT_FLUSH_AND_INV_DB |
1101 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1102 R600_CONTEXT_INV_TEX_CACHE;
1103
1104 /* Set the new state. */
1105 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1106
1107 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1108 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1109 util_format_is_pure_integer(state->cbufs[0]->format);
1110 rctx->framebuffer.compressed_cb_mask = 0;
1111 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1112 state->cbufs[0] && state->cbufs[1] &&
1113 state->cbufs[0]->texture->nr_samples > 1 &&
1114 state->cbufs[1]->texture->nr_samples <= 1;
1115 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1116
1117 /* Colorbuffers. */
1118 for (i = 0; i < state->nr_cbufs; i++) {
1119 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1120 bool force_cmask_fmask = rctx->b.chip_class == R600 &&
1121 rctx->framebuffer.is_msaa_resolve &&
1122 i == 1;
1123
1124 surf = (struct r600_surface*)state->cbufs[i];
1125 if (!surf)
1126 continue;
1127
1128 rtex = (struct r600_texture*)surf->base.texture;
1129 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1130
1131 target_mask |= (0xf << (i * 4));
1132
1133 if (!surf->color_initialized || force_cmask_fmask) {
1134 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1135 if (force_cmask_fmask) {
1136 /* re-initialize later without compression */
1137 surf->color_initialized = false;
1138 }
1139 }
1140
1141 if (!surf->export_16bpc) {
1142 rctx->framebuffer.export_16bpc = false;
1143 }
1144
1145 if (rtex->fmask.size) {
1146 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1147 }
1148 }
1149
1150 /* Update alpha-test state dependencies.
1151 * Alpha-test is done on the first colorbuffer only. */
1152 if (state->nr_cbufs) {
1153 bool alphatest_bypass = false;
1154
1155 surf = (struct r600_surface*)state->cbufs[0];
1156 if (surf) {
1157 alphatest_bypass = surf->alphatest_bypass;
1158 }
1159
1160 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1161 rctx->alphatest_state.bypass = alphatest_bypass;
1162 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1163 }
1164 }
1165
1166 /* ZS buffer. */
1167 if (state->zsbuf) {
1168 surf = (struct r600_surface*)state->zsbuf;
1169
1170 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1171
1172 if (!surf->depth_initialized) {
1173 r600_init_depth_surface(rctx, surf);
1174 }
1175
1176 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1177 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1178 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1179 }
1180
1181 if (rctx->db_state.rsurf != surf) {
1182 rctx->db_state.rsurf = surf;
1183 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1184 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1185 }
1186 } else if (rctx->db_state.rsurf) {
1187 rctx->db_state.rsurf = NULL;
1188 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1189 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1190 }
1191
1192 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1193 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1194 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1195 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1196 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1197 }
1198
1199 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1200 rctx->alphatest_state.bypass = false;
1201 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1202 }
1203
1204 /* Calculate the CS size. */
1205 rctx->framebuffer.atom.num_dw =
1206 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1207
1208 if (rctx->framebuffer.state.nr_cbufs) {
1209 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1210 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1211 }
1212 if (rctx->framebuffer.state.zsbuf) {
1213 rctx->framebuffer.atom.num_dw += 16;
1214 } else if (rctx->screen->b.info.drm_minor >= 18) {
1215 rctx->framebuffer.atom.num_dw += 3;
1216 }
1217 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1218 rctx->framebuffer.atom.num_dw += 2;
1219 }
1220
1221 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1222
1223 r600_set_sample_locations_constant_buffer(rctx);
1224 rctx->framebuffer.do_update_surf_dirtiness = true;
1225 }
1226
1227 static const uint32_t sample_locs_2x[] = {
1228 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1229 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1230 };
1231 static const unsigned max_dist_2x = 4;
1232
1233 static const uint32_t sample_locs_4x[] = {
1234 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1235 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1236 };
1237 static const unsigned max_dist_4x = 6;
1238 static const uint32_t sample_locs_8x[] = {
1239 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1240 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1241 };
1242 static const unsigned max_dist_8x = 7;
1243
r600_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)1244 static void r600_get_sample_position(struct pipe_context *ctx,
1245 unsigned sample_count,
1246 unsigned sample_index,
1247 float *out_value)
1248 {
1249 int offset, index;
1250 struct {
1251 int idx:4;
1252 } val;
1253 switch (sample_count) {
1254 case 1:
1255 default:
1256 out_value[0] = out_value[1] = 0.5;
1257 break;
1258 case 2:
1259 offset = 4 * (sample_index * 2);
1260 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1261 out_value[0] = (float)(val.idx + 8) / 16.0f;
1262 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1263 out_value[1] = (float)(val.idx + 8) / 16.0f;
1264 break;
1265 case 4:
1266 offset = 4 * (sample_index * 2);
1267 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1268 out_value[0] = (float)(val.idx + 8) / 16.0f;
1269 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1270 out_value[1] = (float)(val.idx + 8) / 16.0f;
1271 break;
1272 case 8:
1273 offset = 4 * (sample_index % 4 * 2);
1274 index = (sample_index / 4);
1275 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1276 out_value[0] = (float)(val.idx + 8) / 16.0f;
1277 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1278 out_value[1] = (float)(val.idx + 8) / 16.0f;
1279 break;
1280 }
1281 }
1282
r600_emit_msaa_state(struct r600_context * rctx,int nr_samples)1283 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1284 {
1285 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1286 unsigned max_dist = 0;
1287
1288 if (rctx->b.family == CHIP_R600) {
1289 switch (nr_samples) {
1290 default:
1291 nr_samples = 0;
1292 break;
1293 case 2:
1294 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1295 max_dist = max_dist_2x;
1296 break;
1297 case 4:
1298 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1299 max_dist = max_dist_4x;
1300 break;
1301 case 8:
1302 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1303 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1304 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1305 max_dist = max_dist_8x;
1306 break;
1307 }
1308 } else {
1309 switch (nr_samples) {
1310 default:
1311 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1312 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1313 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1314 nr_samples = 0;
1315 break;
1316 case 2:
1317 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1318 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1319 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1320 max_dist = max_dist_2x;
1321 break;
1322 case 4:
1323 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1324 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1325 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1326 max_dist = max_dist_4x;
1327 break;
1328 case 8:
1329 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1330 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1331 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1332 max_dist = max_dist_8x;
1333 break;
1334 }
1335 }
1336
1337 if (nr_samples > 1) {
1338 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1339 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1340 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1341 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1342 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1343 } else {
1344 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1345 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1346 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1347 }
1348 }
1349
r600_emit_framebuffer_state(struct r600_context * rctx,struct r600_atom * atom)1350 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1351 {
1352 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1353 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1354 unsigned nr_cbufs = state->nr_cbufs;
1355 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1356 unsigned i, sbu = 0;
1357
1358 /* Colorbuffers. */
1359 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1360 for (i = 0; i < nr_cbufs; i++) {
1361 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1362 }
1363 /* set CB_COLOR1_INFO for possible dual-src blending */
1364 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1365 radeon_emit(cs, cb[0]->cb_color_info);
1366 i++;
1367 }
1368 for (; i < 8; i++) {
1369 radeon_emit(cs, 0);
1370 }
1371
1372 if (nr_cbufs) {
1373 for (i = 0; i < nr_cbufs; i++) {
1374 unsigned reloc;
1375
1376 if (!cb[i])
1377 continue;
1378
1379 /* COLOR_BASE */
1380 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1381
1382 reloc = radeon_add_to_buffer_list(&rctx->b,
1383 &rctx->b.gfx,
1384 (struct r600_resource*)cb[i]->base.texture,
1385 RADEON_USAGE_READWRITE,
1386 cb[i]->base.texture->nr_samples > 1 ?
1387 RADEON_PRIO_COLOR_BUFFER_MSAA :
1388 RADEON_PRIO_COLOR_BUFFER);
1389 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1390 radeon_emit(cs, reloc);
1391
1392 /* FMASK */
1393 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1394
1395 reloc = radeon_add_to_buffer_list(&rctx->b,
1396 &rctx->b.gfx,
1397 cb[i]->cb_buffer_fmask,
1398 RADEON_USAGE_READWRITE,
1399 cb[i]->base.texture->nr_samples > 1 ?
1400 RADEON_PRIO_COLOR_BUFFER_MSAA :
1401 RADEON_PRIO_COLOR_BUFFER);
1402 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1403 radeon_emit(cs, reloc);
1404
1405 /* CMASK */
1406 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1407
1408 reloc = radeon_add_to_buffer_list(&rctx->b,
1409 &rctx->b.gfx,
1410 cb[i]->cb_buffer_cmask,
1411 RADEON_USAGE_READWRITE,
1412 cb[i]->base.texture->nr_samples > 1 ?
1413 RADEON_PRIO_COLOR_BUFFER_MSAA :
1414 RADEON_PRIO_COLOR_BUFFER);
1415 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1416 radeon_emit(cs, reloc);
1417 }
1418
1419 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1420 for (i = 0; i < nr_cbufs; i++) {
1421 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1422 }
1423
1424 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1425 for (i = 0; i < nr_cbufs; i++) {
1426 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1427 }
1428
1429 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1430 for (i = 0; i < nr_cbufs; i++) {
1431 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1432 }
1433
1434 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1435 }
1436
1437 /* SURFACE_BASE_UPDATE */
1438 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1439 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1440 radeon_emit(cs, sbu);
1441 sbu = 0;
1442 }
1443
1444 /* Zbuffer. */
1445 if (state->zsbuf) {
1446 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1447 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1448 &rctx->b.gfx,
1449 (struct r600_resource*)state->zsbuf->texture,
1450 RADEON_USAGE_READWRITE,
1451 surf->base.texture->nr_samples > 1 ?
1452 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1453 RADEON_PRIO_DEPTH_BUFFER);
1454
1455 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1456 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1457 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1458 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1459 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1460 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1461
1462 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1463 radeon_emit(cs, reloc);
1464
1465 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1466
1467 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1468 } else if (rctx->screen->b.info.drm_minor >= 18) {
1469 /* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
1470 * Older kernels are out of luck. */
1471 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1472 }
1473
1474 /* SURFACE_BASE_UPDATE */
1475 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1476 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1477 radeon_emit(cs, sbu);
1478 sbu = 0;
1479 }
1480
1481 /* Framebuffer dimensions. */
1482 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1483 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1484 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1485 radeon_emit(cs, S_028244_BR_X(state->width) |
1486 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1487
1488 if (rctx->framebuffer.is_msaa_resolve) {
1489 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1490 } else {
1491 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1492 * will assure that the alpha-test will work even if there is
1493 * no colorbuffer bound. */
1494 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1495 (1ull << MAX2(nr_cbufs, 1)) - 1);
1496 }
1497
1498 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1499 }
1500
r600_set_min_samples(struct pipe_context * ctx,unsigned min_samples)1501 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1502 {
1503 struct r600_context *rctx = (struct r600_context *)ctx;
1504
1505 if (rctx->ps_iter_samples == min_samples)
1506 return;
1507
1508 rctx->ps_iter_samples = min_samples;
1509 if (rctx->framebuffer.nr_samples > 1) {
1510 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1511 if (rctx->b.chip_class == R600)
1512 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1513 }
1514 }
1515
r600_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)1516 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1517 {
1518 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1519 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1520
1521 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1522 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1523 if (rctx->b.chip_class == R600) {
1524 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1525 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1526 } else {
1527 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1528 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1529 }
1530 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1531 } else {
1532 unsigned fb_colormask = a->bound_cbufs_target_mask;
1533 unsigned ps_colormask = a->ps_color_export_mask;
1534 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1535
1536 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1537 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1538 /* Always enable the first color output to make sure alpha-test works even without one. */
1539 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1540 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1541 a->cb_color_control |
1542 S_028808_MULTIWRITE_ENABLE(multiwrite));
1543 }
1544 }
1545
r600_emit_db_state(struct r600_context * rctx,struct r600_atom * atom)1546 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1547 {
1548 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1549 struct r600_db_state *a = (struct r600_db_state*)atom;
1550
1551 if (a->rsurf && a->rsurf->db_htile_surface) {
1552 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1553 unsigned reloc_idx;
1554
1555 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1556 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1557 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1558 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1559 RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
1560 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1561 radeon_emit(cs, reloc_idx);
1562 } else {
1563 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1564 }
1565 }
1566
r600_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)1567 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1568 {
1569 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1570 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1571 unsigned db_render_control = 0;
1572 unsigned db_render_override =
1573 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1574 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1575
1576 if (rctx->b.chip_class >= R700) {
1577 switch (a->ps_conservative_z) {
1578 default: /* fall through */
1579 case TGSI_FS_DEPTH_LAYOUT_ANY:
1580 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1581 break;
1582 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1583 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1584 break;
1585 case TGSI_FS_DEPTH_LAYOUT_LESS:
1586 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1587 break;
1588 }
1589 }
1590
1591 if (rctx->b.num_occlusion_queries > 0 &&
1592 !a->occlusion_queries_disabled) {
1593 if (rctx->b.chip_class >= R700) {
1594 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1595 }
1596 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1597 } else {
1598 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1599 }
1600
1601 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1602 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1603 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1604 /* This is to fix a lockup when hyperz and alpha test are enabled at
1605 * the same time somehow GPU get confuse on which order to pick for
1606 * z test
1607 */
1608 if (rctx->alphatest_state.sx_alpha_test_control) {
1609 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1610 }
1611 } else {
1612 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1613 }
1614 if (rctx->b.chip_class == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1615 /* sample shading and hyperz causes lockups on R6xx chips */
1616 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1617 }
1618 if (a->flush_depthstencil_through_cb) {
1619 assert(a->copy_depth || a->copy_stencil);
1620
1621 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1622 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1623 S_028D0C_COPY_CENTROID(1) |
1624 S_028D0C_COPY_SAMPLE(a->copy_sample);
1625
1626 if (rctx->b.chip_class == R600)
1627 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1628
1629 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1630 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1631 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1632 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1633 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1634 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1635 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1636 }
1637 if (a->htile_clear) {
1638 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1639 }
1640
1641 /* RV770 workaround for a hang with 8x MSAA. */
1642 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1643 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1644 }
1645
1646 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1647 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1648 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1649 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1650 }
1651
r600_emit_config_state(struct r600_context * rctx,struct r600_atom * atom)1652 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1653 {
1654 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1655 struct r600_config_state *a = (struct r600_config_state*)atom;
1656
1657 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1658 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1659 }
1660
r600_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1661 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1662 {
1663 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1664 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1665
1666 while (dirty_mask) {
1667 struct pipe_vertex_buffer *vb;
1668 struct r600_resource *rbuffer;
1669 unsigned offset;
1670 unsigned buffer_index = u_bit_scan(&dirty_mask);
1671
1672 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1673 rbuffer = (struct r600_resource*)vb->buffer.resource;
1674 assert(rbuffer);
1675
1676 offset = vb->buffer_offset;
1677
1678 /* fetch resources start at index 320 (OFFSET_FS) */
1679 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1680 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1681 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1682 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1683 radeon_emit(cs, /* RESOURCEi_WORD2 */
1684 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1685 S_038008_STRIDE(vb->stride));
1686 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1687 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1688 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1689 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1690
1691 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1692 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1693 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER));
1694 }
1695 }
1696
r600_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache)1697 static void r600_emit_constant_buffers(struct r600_context *rctx,
1698 struct r600_constbuf_state *state,
1699 unsigned buffer_id_base,
1700 unsigned reg_alu_constbuf_size,
1701 unsigned reg_alu_const_cache)
1702 {
1703 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1704 uint32_t dirty_mask = state->dirty_mask;
1705
1706 while (dirty_mask) {
1707 struct pipe_constant_buffer *cb;
1708 struct r600_resource *rbuffer;
1709 unsigned offset;
1710 unsigned buffer_index = ffs(dirty_mask) - 1;
1711 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1712 cb = &state->cb[buffer_index];
1713 rbuffer = (struct r600_resource*)cb->buffer;
1714 assert(rbuffer);
1715
1716 offset = cb->buffer_offset;
1717
1718 if (!gs_ring_buffer) {
1719 assert(buffer_index < R600_MAX_HW_CONST_BUFFERS);
1720 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1721 DIV_ROUND_UP(cb->buffer_size, 256));
1722 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1723 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1724 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1725 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1726 }
1727
1728 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1729 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1730 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1731 radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
1732 radeon_emit(cs, /* RESOURCEi_WORD2 */
1733 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1734 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1735 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1736 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1737 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1738 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1739
1740 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1741 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1742 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER));
1743
1744 dirty_mask &= ~(1 << buffer_index);
1745 }
1746 state->dirty_mask = 0;
1747 }
1748
r600_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1749 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1750 {
1751 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1752 R600_FETCH_CONSTANTS_OFFSET_VS,
1753 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1754 R_028980_ALU_CONST_CACHE_VS_0);
1755 }
1756
r600_emit_gs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1757 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1758 {
1759 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1760 R600_FETCH_CONSTANTS_OFFSET_GS,
1761 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1762 R_0289C0_ALU_CONST_CACHE_GS_0);
1763 }
1764
r600_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1765 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1766 {
1767 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1768 R600_FETCH_CONSTANTS_OFFSET_PS,
1769 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1770 R_028940_ALU_CONST_CACHE_PS_0);
1771 }
1772
r600_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base)1773 static void r600_emit_sampler_views(struct r600_context *rctx,
1774 struct r600_samplerview_state *state,
1775 unsigned resource_id_base)
1776 {
1777 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1778 uint32_t dirty_mask = state->dirty_mask;
1779
1780 while (dirty_mask) {
1781 struct r600_pipe_sampler_view *rview;
1782 unsigned resource_index = u_bit_scan(&dirty_mask);
1783 unsigned reloc;
1784
1785 rview = state->views[resource_index];
1786 assert(rview);
1787
1788 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1789 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1790 radeon_emit_array(cs, rview->tex_resource_words, 7);
1791
1792 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1793 RADEON_USAGE_READ,
1794 r600_get_sampler_view_priority(rview->tex_resource));
1795 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1796 radeon_emit(cs, reloc);
1797 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1798 radeon_emit(cs, reloc);
1799 }
1800 state->dirty_mask = 0;
1801 }
1802
1803
r600_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1804 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1805 {
1806 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1807 }
1808
r600_emit_gs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1809 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1810 {
1811 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1812 }
1813
r600_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1814 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1815 {
1816 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1817 }
1818
r600_emit_sampler_states(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_color_reg)1819 static void r600_emit_sampler_states(struct r600_context *rctx,
1820 struct r600_textures_info *texinfo,
1821 unsigned resource_id_base,
1822 unsigned border_color_reg)
1823 {
1824 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1825 uint32_t dirty_mask = texinfo->states.dirty_mask;
1826
1827 while (dirty_mask) {
1828 struct r600_pipe_sampler_state *rstate;
1829 struct r600_pipe_sampler_view *rview;
1830 unsigned i = u_bit_scan(&dirty_mask);
1831
1832 rstate = texinfo->states.states[i];
1833 assert(rstate);
1834 rview = texinfo->views.views[i];
1835
1836 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1837 * filtering between layers.
1838 */
1839 enum pipe_texture_target target = PIPE_BUFFER;
1840 if (rview)
1841 target = rview->base.texture->target;
1842 if (target == PIPE_TEXTURE_1D_ARRAY ||
1843 target == PIPE_TEXTURE_2D_ARRAY) {
1844 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1845 texinfo->is_array_sampler[i] = true;
1846 } else {
1847 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1848 texinfo->is_array_sampler[i] = false;
1849 }
1850
1851 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1852 radeon_emit(cs, (resource_id_base + i) * 3);
1853 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1854
1855 if (rstate->border_color_use) {
1856 unsigned offset;
1857
1858 offset = border_color_reg;
1859 offset += i * 16;
1860 radeon_set_config_reg_seq(cs, offset, 4);
1861 radeon_emit_array(cs, rstate->border_color.ui, 4);
1862 }
1863 }
1864 texinfo->states.dirty_mask = 0;
1865 }
1866
r600_emit_vs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1867 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1868 {
1869 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1870 }
1871
r600_emit_gs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1872 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1873 {
1874 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1875 }
1876
r600_emit_ps_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1877 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1878 {
1879 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1880 }
1881
r600_emit_seamless_cube_map(struct r600_context * rctx,struct r600_atom * atom)1882 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1883 {
1884 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1885 unsigned tmp;
1886
1887 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1888 S_009508_SYNC_GRADIENT(1) |
1889 S_009508_SYNC_WALKER(1) |
1890 S_009508_SYNC_ALIGNER(1);
1891 if (!rctx->seamless_cube_map.enabled) {
1892 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1893 }
1894 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1895 }
1896
r600_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)1897 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1898 {
1899 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1900 uint8_t mask = s->sample_mask;
1901
1902 radeon_set_context_reg(rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1903 mask | (mask << 8) | (mask << 16) | (mask << 24));
1904 }
1905
r600_emit_vertex_fetch_shader(struct r600_context * rctx,struct r600_atom * a)1906 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1907 {
1908 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1909 struct r600_cso_state *state = (struct r600_cso_state*)a;
1910 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1911
1912 if (!shader)
1913 return;
1914
1915 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1916 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1917 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1918 RADEON_USAGE_READ,
1919 RADEON_PRIO_SHADER_BINARY));
1920 }
1921
r600_emit_shader_stages(struct r600_context * rctx,struct r600_atom * a)1922 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1923 {
1924 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1925 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1926
1927 uint32_t v2 = 0, primid = 0;
1928
1929 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1930 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1931 primid = 1;
1932 }
1933
1934 if (state->geom_enable) {
1935 uint32_t cut_val;
1936
1937 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1938 cut_val = V_028A40_GS_CUT_128;
1939 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1940 cut_val = V_028A40_GS_CUT_256;
1941 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1942 cut_val = V_028A40_GS_CUT_512;
1943 else
1944 cut_val = V_028A40_GS_CUT_1024;
1945
1946 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1947 S_028A40_CUT_MODE(cut_val);
1948
1949 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1950 primid = 1;
1951 }
1952
1953 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1954 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1955 }
1956
r600_emit_gs_rings(struct r600_context * rctx,struct r600_atom * a)1957 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1958 {
1959 struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
1960 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1961 struct r600_resource *rbuffer;
1962
1963 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1964 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1965 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1966
1967 if (state->enable) {
1968 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1969 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1970 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1971 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1972 RADEON_USAGE_READWRITE,
1973 RADEON_PRIO_SHADER_RINGS));
1974 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1975 state->esgs_ring.buffer_size >> 8);
1976
1977 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
1978 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
1979 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1980 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1981 RADEON_USAGE_READWRITE,
1982 RADEON_PRIO_SHADER_RINGS));
1983 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
1984 state->gsvs_ring.buffer_size >> 8);
1985 } else {
1986 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
1987 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
1988 }
1989
1990 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1991 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1992 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1993 }
1994
1995 /* Adjust GPR allocation on R6xx/R7xx */
r600_adjust_gprs(struct r600_context * rctx)1996 bool r600_adjust_gprs(struct r600_context *rctx)
1997 {
1998 unsigned num_gprs[R600_NUM_HW_STAGES];
1999 unsigned new_gprs[R600_NUM_HW_STAGES];
2000 unsigned cur_gprs[R600_NUM_HW_STAGES];
2001 unsigned def_gprs[R600_NUM_HW_STAGES];
2002 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2003 unsigned max_gprs;
2004 unsigned tmp, tmp2;
2005 unsigned i;
2006 bool need_recalc = false, use_default = true;
2007
2008 /* hardware will reserve twice num_clause_temp_gprs */
2009 max_gprs = def_num_clause_temp_gprs * 2;
2010 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2011 def_gprs[i] = rctx->default_gprs[i];
2012 max_gprs += def_gprs[i];
2013 }
2014
2015 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2016 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2017 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2018 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2019
2020 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2021 if (rctx->gs_shader) {
2022 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2023 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2024 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2025 } else {
2026 num_gprs[R600_HW_STAGE_ES] = 0;
2027 num_gprs[R600_HW_STAGE_GS] = 0;
2028 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2029 }
2030
2031 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2032 new_gprs[i] = num_gprs[i];
2033 if (new_gprs[i] > cur_gprs[i])
2034 need_recalc = true;
2035 if (new_gprs[i] > def_gprs[i])
2036 use_default = false;
2037 }
2038
2039 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2040 if (!need_recalc)
2041 return true;
2042
2043 /* try to use switch back to default */
2044 if (!use_default) {
2045 /* always privilege vs stage so that at worst we have the
2046 * pixel stage producing wrong output (not the vertex
2047 * stage) */
2048 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2049 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2050 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2051 } else {
2052 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2053 new_gprs[i] = def_gprs[i];
2054 }
2055
2056 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2057 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2058 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2059 * it will lockup. So in this case just discard the draw command
2060 * and don't change the current gprs repartitions.
2061 */
2062 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2063 if (num_gprs[i] > new_gprs[i]) {
2064 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2065 "for a combined maximum of %d\n",
2066 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2067 return false;
2068 }
2069 }
2070
2071 /* in some case we endup recomputing the current value */
2072 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2073 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2074 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2075
2076 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2077 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2078 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2079 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2080 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2081 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2082 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2083 }
2084 return true;
2085 }
2086
r600_init_atom_start_cs(struct r600_context * rctx)2087 void r600_init_atom_start_cs(struct r600_context *rctx)
2088 {
2089 int ps_prio;
2090 int vs_prio;
2091 int gs_prio;
2092 int es_prio;
2093 int num_ps_gprs;
2094 int num_vs_gprs;
2095 int num_gs_gprs;
2096 int num_es_gprs;
2097 int num_temp_gprs;
2098 int num_ps_threads;
2099 int num_vs_threads;
2100 int num_gs_threads;
2101 int num_es_threads;
2102 int num_ps_stack_entries;
2103 int num_vs_stack_entries;
2104 int num_gs_stack_entries;
2105 int num_es_stack_entries;
2106 enum radeon_family family;
2107 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2108 uint32_t tmp, i;
2109
2110 r600_init_command_buffer(cb, 256);
2111
2112 /* R6xx requires this packet at the start of each command buffer */
2113 if (rctx->b.chip_class == R600) {
2114 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2115 r600_store_value(cb, 0);
2116 }
2117 /* All asics require this one */
2118 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2119 r600_store_value(cb, 0x80000000);
2120 r600_store_value(cb, 0x80000000);
2121
2122 /* We're setting config registers here. */
2123 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2124 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2125
2126 /* This enables pipeline stat & streamout queries.
2127 * They are only disabled by blits.
2128 */
2129 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2130 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2131
2132 family = rctx->b.family;
2133 ps_prio = 0;
2134 vs_prio = 1;
2135 gs_prio = 2;
2136 es_prio = 3;
2137 switch (family) {
2138 case CHIP_R600:
2139 num_ps_gprs = 192;
2140 num_vs_gprs = 56;
2141 num_temp_gprs = 4;
2142 num_gs_gprs = 0;
2143 num_es_gprs = 0;
2144 num_ps_threads = 136;
2145 num_vs_threads = 48;
2146 num_gs_threads = 4;
2147 num_es_threads = 4;
2148 num_ps_stack_entries = 128;
2149 num_vs_stack_entries = 128;
2150 num_gs_stack_entries = 0;
2151 num_es_stack_entries = 0;
2152 break;
2153 case CHIP_RV630:
2154 case CHIP_RV635:
2155 num_ps_gprs = 84;
2156 num_vs_gprs = 36;
2157 num_temp_gprs = 4;
2158 num_gs_gprs = 0;
2159 num_es_gprs = 0;
2160 num_ps_threads = 144;
2161 num_vs_threads = 40;
2162 num_gs_threads = 4;
2163 num_es_threads = 4;
2164 num_ps_stack_entries = 40;
2165 num_vs_stack_entries = 40;
2166 num_gs_stack_entries = 32;
2167 num_es_stack_entries = 16;
2168 break;
2169 case CHIP_RV610:
2170 case CHIP_RV620:
2171 case CHIP_RS780:
2172 case CHIP_RS880:
2173 default:
2174 num_ps_gprs = 84;
2175 num_vs_gprs = 36;
2176 num_temp_gprs = 4;
2177 num_gs_gprs = 0;
2178 num_es_gprs = 0;
2179 /* use limits 40 VS and at least 16 ES/GS */
2180 num_ps_threads = 120;
2181 num_vs_threads = 40;
2182 num_gs_threads = 16;
2183 num_es_threads = 16;
2184 num_ps_stack_entries = 40;
2185 num_vs_stack_entries = 40;
2186 num_gs_stack_entries = 32;
2187 num_es_stack_entries = 16;
2188 break;
2189 case CHIP_RV670:
2190 num_ps_gprs = 144;
2191 num_vs_gprs = 40;
2192 num_temp_gprs = 4;
2193 num_gs_gprs = 0;
2194 num_es_gprs = 0;
2195 num_ps_threads = 136;
2196 num_vs_threads = 48;
2197 num_gs_threads = 4;
2198 num_es_threads = 4;
2199 num_ps_stack_entries = 40;
2200 num_vs_stack_entries = 40;
2201 num_gs_stack_entries = 32;
2202 num_es_stack_entries = 16;
2203 break;
2204 case CHIP_RV770:
2205 num_ps_gprs = 130;
2206 num_vs_gprs = 56;
2207 num_temp_gprs = 4;
2208 num_gs_gprs = 31;
2209 num_es_gprs = 31;
2210 num_ps_threads = 180;
2211 num_vs_threads = 60;
2212 num_gs_threads = 4;
2213 num_es_threads = 4;
2214 num_ps_stack_entries = 128;
2215 num_vs_stack_entries = 128;
2216 num_gs_stack_entries = 128;
2217 num_es_stack_entries = 128;
2218 break;
2219 case CHIP_RV730:
2220 case CHIP_RV740:
2221 num_ps_gprs = 84;
2222 num_vs_gprs = 36;
2223 num_temp_gprs = 4;
2224 num_gs_gprs = 0;
2225 num_es_gprs = 0;
2226 num_ps_threads = 180;
2227 num_vs_threads = 60;
2228 num_gs_threads = 4;
2229 num_es_threads = 4;
2230 num_ps_stack_entries = 128;
2231 num_vs_stack_entries = 128;
2232 num_gs_stack_entries = 0;
2233 num_es_stack_entries = 0;
2234 break;
2235 case CHIP_RV710:
2236 num_ps_gprs = 192;
2237 num_vs_gprs = 56;
2238 num_temp_gprs = 4;
2239 num_gs_gprs = 0;
2240 num_es_gprs = 0;
2241 num_ps_threads = 136;
2242 num_vs_threads = 48;
2243 num_gs_threads = 4;
2244 num_es_threads = 4;
2245 num_ps_stack_entries = 128;
2246 num_vs_stack_entries = 128;
2247 num_gs_stack_entries = 0;
2248 num_es_stack_entries = 0;
2249 break;
2250 }
2251
2252 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2253 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2254 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2255 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2256
2257 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2258
2259 /* SQ_CONFIG */
2260 tmp = 0;
2261 switch (family) {
2262 case CHIP_RV610:
2263 case CHIP_RV620:
2264 case CHIP_RS780:
2265 case CHIP_RS880:
2266 case CHIP_RV710:
2267 break;
2268 default:
2269 tmp |= S_008C00_VC_ENABLE(1);
2270 break;
2271 }
2272 tmp |= S_008C00_DX9_CONSTS(0);
2273 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2274 tmp |= S_008C00_PS_PRIO(ps_prio);
2275 tmp |= S_008C00_VS_PRIO(vs_prio);
2276 tmp |= S_008C00_GS_PRIO(gs_prio);
2277 tmp |= S_008C00_ES_PRIO(es_prio);
2278 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2279
2280 /* SQ_GPR_RESOURCE_MGMT_2 */
2281 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2282 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2283 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2284 r600_store_value(cb, tmp);
2285
2286 /* SQ_THREAD_RESOURCE_MGMT */
2287 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2288 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2289 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2290 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2291 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2292
2293 /* SQ_STACK_RESOURCE_MGMT_1 */
2294 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2295 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2296 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2297
2298 /* SQ_STACK_RESOURCE_MGMT_2 */
2299 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2300 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2301 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2302
2303 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2304
2305 if (rctx->b.chip_class >= R700) {
2306 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2307 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2308 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2309 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2310 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2311 } else {
2312 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2313 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2314 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2315 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2316 }
2317 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2318 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2319 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2320 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2321 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2322 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2323 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2324 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2325 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2326 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2327
2328 /* to avoid GPU doing any preloading of constant from random address */
2329 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2330 for (i = 0; i < 16; i++)
2331 r600_store_value(cb, 0);
2332
2333 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2334 for (i = 0; i < 16; i++)
2335 r600_store_value(cb, 0);
2336
2337 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2338 for (i = 0; i < 16; i++)
2339 r600_store_value(cb, 0);
2340
2341 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2342 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2343 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2344 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2345 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2346 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2347 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2348 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2349 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2350 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2351 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2352 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2353 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2354 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2355
2356 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2357 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2358 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2359
2360 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2361 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2362 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2363
2364 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2365
2366 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2367
2368 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2369
2370 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2371 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2372 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2373 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2374
2375 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2376 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2377 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2378 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2379
2380 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2381 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2382
2383 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2384 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2385
2386 if (rctx->b.chip_class >= R700) {
2387 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2388 }
2389
2390 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2391 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2392 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2393 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2394 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2395
2396 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2397 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2398 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2399
2400 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2401 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2402 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2403
2404 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2405 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2406 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2407 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2408 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2409 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2410
2411 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2412
2413 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2414 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2415 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2416
2417 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2418
2419 if (rctx->b.chip_class == R700)
2420 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2421 if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
2422 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2423
2424 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2425 if (rctx->screen->b.has_streamout) {
2426 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2427 }
2428
2429 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2430 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2431 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2432 }
2433
r600_update_ps_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2434 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2435 {
2436 struct r600_context *rctx = (struct r600_context *)ctx;
2437 struct r600_command_buffer *cb = &shader->command_buffer;
2438 struct r600_shader *rshader = &shader->shader;
2439 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2440 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2441 unsigned tmp, sid, ufi = 0;
2442 int need_linear = 0;
2443 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2444 unsigned sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2445
2446 if (!cb->buf) {
2447 r600_init_command_buffer(cb, 64);
2448 } else {
2449 cb->num_dw = 0;
2450 }
2451
2452 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2453 for (i = 0; i < rshader->ninput; i++) {
2454 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2455 pos_index = i;
2456 if (rshader->input[i].name == TGSI_SEMANTIC_FACE && face_index == -1)
2457 face_index = i;
2458 if (rshader->input[i].name == TGSI_SEMANTIC_SAMPLEID)
2459 fixed_pt_position_index = i;
2460
2461 sid = rshader->input[i].spi_sid;
2462
2463 tmp = S_028644_SEMANTIC(sid);
2464
2465 /* D3D 9 behaviour. GL is undefined */
2466 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0)
2467 tmp |= S_028644_DEFAULT_VAL(3);
2468
2469 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2470 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2471 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2472 rctx->rasterizer && rctx->rasterizer->flatshade))
2473 tmp |= S_028644_FLAT_SHADE(1);
2474
2475 if (rshader->input[i].name == TGSI_SEMANTIC_PCOORD ||
2476 (rshader->input[i].name == TGSI_SEMANTIC_TEXCOORD &&
2477 sprite_coord_enable & (1 << rshader->input[i].sid))) {
2478 tmp |= S_028644_PT_SPRITE_TEX(1);
2479 }
2480
2481 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2482 tmp |= S_028644_SEL_CENTROID(1);
2483
2484 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2485 tmp |= S_028644_SEL_SAMPLE(1);
2486
2487 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2488 need_linear = 1;
2489 tmp |= S_028644_SEL_LINEAR(1);
2490 }
2491
2492 r600_store_value(cb, tmp);
2493 }
2494
2495 db_shader_control = 0;
2496 for (i = 0; i < rshader->noutput; i++) {
2497 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2498 z_export = 1;
2499 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2500 stencil_export = 1;
2501 if (rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK &&
2502 rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0)
2503 mask_export = 1;
2504 }
2505 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2506 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2507 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2508 if (rshader->uses_kill)
2509 db_shader_control |= S_02880C_KILL_ENABLE(1);
2510
2511 exports_ps = 0;
2512 for (i = 0; i < rshader->noutput; i++) {
2513 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2514 rshader->output[i].name == TGSI_SEMANTIC_STENCIL ||
2515 rshader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2516 exports_ps |= 1;
2517 }
2518 }
2519 num_cout = rshader->nr_ps_color_exports;
2520 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2521 if (!exports_ps) {
2522 /* always at least export 1 component per pixel */
2523 exports_ps = 2;
2524 }
2525
2526 shader->nr_ps_color_outputs = num_cout;
2527 shader->ps_color_export_mask = rshader->ps_color_export_mask;
2528
2529 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2530 S_0286CC_PERSP_GRADIENT_ENA(1)|
2531 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2532 spi_input_z = 0;
2533 if (pos_index != -1) {
2534 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2535 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2536 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2537 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2538 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2539 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2540 }
2541
2542 spi_ps_in_control_1 = 0;
2543 if (face_index != -1) {
2544 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2545 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2546 }
2547 if (fixed_pt_position_index != -1) {
2548 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2549 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2550 }
2551
2552 /* HW bug in original R600 */
2553 if (rctx->b.family == CHIP_R600)
2554 ufi = 1;
2555
2556 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2557 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2558 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2559
2560 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2561
2562 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2563 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2564 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2565 /*
2566 * docs are misleading about the dx10_clamp bit. This only affects
2567 * instructions using CLAMP dst modifier, in which case they will
2568 * return 0 with this set for a NaN (otherwise NaN).
2569 */
2570 S_028850_DX10_CLAMP(1) |
2571 S_028850_STACK_SIZE(rshader->bc.nstack) |
2572 S_028850_UNCACHED_FIRST_INST(ufi));
2573 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2574
2575 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2576 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2577
2578 /* only set some bits here, the other bits are set in the dsa state */
2579 shader->db_shader_control = db_shader_control;
2580 shader->ps_depth_export = z_export | stencil_export | mask_export;
2581
2582 shader->sprite_coord_enable = sprite_coord_enable;
2583 if (rctx->rasterizer)
2584 shader->flatshade = rctx->rasterizer->flatshade;
2585 }
2586
r600_update_vs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2587 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2588 {
2589 struct r600_command_buffer *cb = &shader->command_buffer;
2590 struct r600_shader *rshader = &shader->shader;
2591 unsigned spi_vs_out_id[10] = {};
2592 unsigned i, tmp, nparams = 0;
2593
2594 for (i = 0; i < rshader->noutput; i++) {
2595 if (rshader->output[i].spi_sid) {
2596 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2597 spi_vs_out_id[nparams / 4] |= tmp;
2598 nparams++;
2599 }
2600 }
2601
2602 r600_init_command_buffer(cb, 32);
2603
2604 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2605 for (i = 0; i < 10; i++) {
2606 r600_store_value(cb, spi_vs_out_id[i]);
2607 }
2608
2609 /* Certain attributes (position, psize, etc.) don't count as params.
2610 * VS is required to export at least one param and r600_shader_from_tgsi()
2611 * takes care of adding a dummy export.
2612 */
2613 if (nparams < 1)
2614 nparams = 1;
2615
2616 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2617 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2618 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2619 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2620 S_028868_DX10_CLAMP(1) |
2621 S_028868_STACK_SIZE(rshader->bc.nstack));
2622 if (rshader->vs_position_window_space) {
2623 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2624 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2625 } else {
2626 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2627 S_028818_VTX_W0_FMT(1) |
2628 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2629 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2630 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2631
2632 }
2633 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2634 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2635
2636 shader->pa_cl_vs_out_cntl =
2637 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2638 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2639 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2640 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2641 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2642 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2643 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2644 }
2645
2646 #define RV610_GSVS_ALIGN 32
2647 #define R600_GSVS_ALIGN 16
2648
r600_update_gs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2649 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2650 {
2651 struct r600_context *rctx = (struct r600_context *)ctx;
2652 struct r600_command_buffer *cb = &shader->command_buffer;
2653 struct r600_shader *rshader = &shader->shader;
2654 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2655 unsigned gsvs_itemsize =
2656 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2657
2658 /* some r600s needs gsvs itemsize aligned to cacheline size
2659 this was fixed in rs780 and above. */
2660 switch (rctx->b.family) {
2661 case CHIP_RV610:
2662 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2663 break;
2664 case CHIP_R600:
2665 case CHIP_RV630:
2666 case CHIP_RV670:
2667 case CHIP_RV620:
2668 case CHIP_RV635:
2669 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2670 break;
2671 default:
2672 break;
2673 }
2674
2675 r600_init_command_buffer(cb, 64);
2676
2677 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2678 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2679
2680 if (rctx->b.chip_class >= R700) {
2681 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2682 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2683 }
2684 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2685 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2686
2687 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2688 cp_shader->ring_item_sizes[0] >> 2);
2689
2690 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2691 (rshader->ring_item_sizes[0]) >> 2);
2692
2693 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2694 gsvs_itemsize);
2695
2696 /* FIXME calculate these values somehow ??? */
2697 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2698 r600_store_value(cb, 0x80); /* GS_PER_ES */
2699 r600_store_value(cb, 0x100); /* ES_PER_GS */
2700 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2701 r600_store_value(cb, 0x2); /* GS_PER_VS */
2702
2703 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2704 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2705 S_02887C_DX10_CLAMP(1) |
2706 S_02887C_STACK_SIZE(rshader->bc.nstack));
2707 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2708 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2709 }
2710
r600_update_es_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2711 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2712 {
2713 struct r600_command_buffer *cb = &shader->command_buffer;
2714 struct r600_shader *rshader = &shader->shader;
2715
2716 r600_init_command_buffer(cb, 32);
2717
2718 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2719 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2720 S_028890_DX10_CLAMP(1) |
2721 S_028890_STACK_SIZE(rshader->bc.nstack));
2722 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2723 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2724 }
2725
2726
r600_create_resolve_blend(struct r600_context * rctx)2727 void *r600_create_resolve_blend(struct r600_context *rctx)
2728 {
2729 struct pipe_blend_state blend;
2730 unsigned i;
2731
2732 memset(&blend, 0, sizeof(blend));
2733 blend.independent_blend_enable = true;
2734 for (i = 0; i < 2; i++) {
2735 blend.rt[i].colormask = 0xf;
2736 blend.rt[i].blend_enable = 1;
2737 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2738 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2739 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2740 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2741 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2742 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2743 }
2744 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2745 }
2746
r700_create_resolve_blend(struct r600_context * rctx)2747 void *r700_create_resolve_blend(struct r600_context *rctx)
2748 {
2749 struct pipe_blend_state blend;
2750
2751 memset(&blend, 0, sizeof(blend));
2752 blend.independent_blend_enable = true;
2753 blend.rt[0].colormask = 0xf;
2754 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2755 }
2756
r600_create_decompress_blend(struct r600_context * rctx)2757 void *r600_create_decompress_blend(struct r600_context *rctx)
2758 {
2759 struct pipe_blend_state blend;
2760
2761 memset(&blend, 0, sizeof(blend));
2762 blend.independent_blend_enable = true;
2763 blend.rt[0].colormask = 0xf;
2764 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2765 }
2766
r600_create_db_flush_dsa(struct r600_context * rctx)2767 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2768 {
2769 struct pipe_depth_stencil_alpha_state dsa;
2770 boolean quirk = false;
2771
2772 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2773 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2774 quirk = true;
2775
2776 memset(&dsa, 0, sizeof(dsa));
2777
2778 if (quirk) {
2779 dsa.depth.enabled = 1;
2780 dsa.depth.func = PIPE_FUNC_LEQUAL;
2781 dsa.stencil[0].enabled = 1;
2782 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2783 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2784 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2785 dsa.stencil[0].writemask = 0xff;
2786 }
2787
2788 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2789 }
2790
r600_update_db_shader_control(struct r600_context * rctx)2791 void r600_update_db_shader_control(struct r600_context * rctx)
2792 {
2793 bool dual_export;
2794 unsigned db_shader_control;
2795 uint8_t ps_conservative_z;
2796
2797 if (!rctx->ps_shader) {
2798 return;
2799 }
2800
2801 dual_export = rctx->framebuffer.export_16bpc &&
2802 !rctx->ps_shader->current->ps_depth_export;
2803
2804 db_shader_control = rctx->ps_shader->current->db_shader_control |
2805 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2806
2807 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2808
2809 /* When alpha test is enabled we can't trust the hw to make the proper
2810 * decision on the order in which ztest should be run related to fragment
2811 * shader execution.
2812 *
2813 * If alpha test is enabled perform z test after fragment. RE_Z (early
2814 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2815 */
2816 if (rctx->alphatest_state.sx_alpha_test_control) {
2817 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2818 } else {
2819 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2820 }
2821
2822 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2823 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2824 rctx->db_misc_state.db_shader_control = db_shader_control;
2825 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2826 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2827 }
2828 }
2829
r600_array_mode(unsigned mode)2830 static inline unsigned r600_array_mode(unsigned mode)
2831 {
2832 switch (mode) {
2833 default:
2834 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2835 break;
2836 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2837 break;
2838 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2839 }
2840 }
2841
r600_dma_copy_tile(struct r600_context * rctx,struct pipe_resource * dst,unsigned dst_level,unsigned dst_x,unsigned dst_y,unsigned dst_z,struct pipe_resource * src,unsigned src_level,unsigned src_x,unsigned src_y,unsigned src_z,unsigned copy_height,unsigned pitch,unsigned bpp)2842 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2843 struct pipe_resource *dst,
2844 unsigned dst_level,
2845 unsigned dst_x,
2846 unsigned dst_y,
2847 unsigned dst_z,
2848 struct pipe_resource *src,
2849 unsigned src_level,
2850 unsigned src_x,
2851 unsigned src_y,
2852 unsigned src_z,
2853 unsigned copy_height,
2854 unsigned pitch,
2855 unsigned bpp)
2856 {
2857 struct radeon_cmdbuf *cs = rctx->b.dma.cs;
2858 struct r600_texture *rsrc = (struct r600_texture*)src;
2859 struct r600_texture *rdst = (struct r600_texture*)dst;
2860 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2861 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2862 uint64_t base, addr;
2863
2864 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2865 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2866 assert(dst_mode != src_mode);
2867
2868 y = 0;
2869 lbpp = util_logbase2(bpp);
2870 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2871
2872 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2873 /* T2L */
2874 array_mode = r600_array_mode(src_mode);
2875 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2876 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2877 /* linear height must be the same as the slice tile max height, it's ok even
2878 * if the linear destination/source have smaller heigh as the size of the
2879 * dma packet will be using the copy_height which is always smaller or equal
2880 * to the linear height
2881 */
2882 height = u_minify(rsrc->resource.b.b.height0, src_level);
2883 detile = 1;
2884 x = src_x;
2885 y = src_y;
2886 z = src_z;
2887 base = rsrc->surface.u.legacy.level[src_level].offset;
2888 addr = rdst->surface.u.legacy.level[dst_level].offset;
2889 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2890 addr += dst_y * pitch + dst_x * bpp;
2891 } else {
2892 /* L2T */
2893 array_mode = r600_array_mode(dst_mode);
2894 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2895 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2896 /* linear height must be the same as the slice tile max height, it's ok even
2897 * if the linear destination/source have smaller heigh as the size of the
2898 * dma packet will be using the copy_height which is always smaller or equal
2899 * to the linear height
2900 */
2901 height = u_minify(rdst->resource.b.b.height0, dst_level);
2902 detile = 0;
2903 x = dst_x;
2904 y = dst_y;
2905 z = dst_z;
2906 base = rdst->surface.u.legacy.level[dst_level].offset;
2907 addr = rsrc->surface.u.legacy.level[src_level].offset;
2908 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
2909 addr += src_y * pitch + src_x * bpp;
2910 }
2911 /* check that we are in dw/base alignment constraint */
2912 if (addr % 4 || base % 256) {
2913 return FALSE;
2914 }
2915
2916 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2917 * line in the blit. Compute max 8 line we can copy in the size limit
2918 */
2919 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2920 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2921 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2922
2923 for (i = 0; i < ncopy; i++) {
2924 cheight = cheight > copy_height ? copy_height : cheight;
2925 size = (cheight * pitch) / 4;
2926 /* emit reloc before writing cs so that cs is always in consistent state */
2927 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ, 0);
2928 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, 0);
2929 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2930 radeon_emit(cs, base >> 8);
2931 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2932 (lbpp << 24) | ((height - 1) << 10) |
2933 pitch_tile_max);
2934 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2935 radeon_emit(cs, (x << 3) | (y << 17));
2936 radeon_emit(cs, addr & 0xfffffffc);
2937 radeon_emit(cs, (addr >> 32UL) & 0xff);
2938 copy_height -= cheight;
2939 addr += cheight * pitch;
2940 y += cheight;
2941 }
2942 return TRUE;
2943 }
2944
r600_dma_copy(struct pipe_context * ctx,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)2945 static void r600_dma_copy(struct pipe_context *ctx,
2946 struct pipe_resource *dst,
2947 unsigned dst_level,
2948 unsigned dstx, unsigned dsty, unsigned dstz,
2949 struct pipe_resource *src,
2950 unsigned src_level,
2951 const struct pipe_box *src_box)
2952 {
2953 struct r600_context *rctx = (struct r600_context *)ctx;
2954 struct r600_texture *rsrc = (struct r600_texture*)src;
2955 struct r600_texture *rdst = (struct r600_texture*)dst;
2956 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2957 unsigned src_w, dst_w;
2958 unsigned src_x, src_y;
2959 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2960
2961 if (rctx->b.dma.cs == NULL) {
2962 goto fallback;
2963 }
2964
2965 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2966 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2967 goto fallback;
2968
2969 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2970 return;
2971 }
2972
2973 if (src_box->depth > 1 ||
2974 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2975 dstz, rsrc, src_level, src_box))
2976 goto fallback;
2977
2978 src_x = util_format_get_nblocksx(src->format, src_box->x);
2979 dst_x = util_format_get_nblocksx(src->format, dst_x);
2980 src_y = util_format_get_nblocksy(src->format, src_box->y);
2981 dst_y = util_format_get_nblocksy(src->format, dst_y);
2982
2983 bpp = rdst->surface.bpe;
2984 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
2985 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
2986 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2987 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
2988 copy_height = src_box->height / rsrc->surface.blk_h;
2989
2990 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2991 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2992
2993 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
2994 /* strict requirement on r6xx/r7xx */
2995 goto fallback;
2996 }
2997 /* lot of constraint on alignment this should capture them all */
2998 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
2999 goto fallback;
3000 }
3001
3002 if (src_mode == dst_mode) {
3003 uint64_t dst_offset, src_offset, size;
3004
3005 /* simple dma blit would do NOTE code here assume :
3006 * src_box.x/y == 0
3007 * dst_x/y == 0
3008 * dst_pitch == src_pitch
3009 */
3010 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
3011 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3012 src_offset += src_y * src_pitch + src_x * bpp;
3013 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
3014 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3015 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3016 size = src_box->height * src_pitch;
3017 /* must be dw aligned */
3018 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3019 goto fallback;
3020 }
3021 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3022 } else {
3023 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3024 src, src_level, src_x, src_y, src_box->z,
3025 copy_height, dst_pitch, bpp)) {
3026 goto fallback;
3027 }
3028 }
3029 return;
3030
3031 fallback:
3032 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3033 src, src_level, src_box);
3034 }
3035
r600_init_state_functions(struct r600_context * rctx)3036 void r600_init_state_functions(struct r600_context *rctx)
3037 {
3038 unsigned id = 1;
3039 unsigned i;
3040 /* !!!
3041 * To avoid GPU lockup registers must be emited in a specific order
3042 * (no kidding ...). The order below is important and have been
3043 * partialy infered from analyzing fglrx command stream.
3044 *
3045 * Don't reorder atom without carefully checking the effect (GPU lockup
3046 * or piglit regression).
3047 * !!!
3048 */
3049
3050 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3051
3052 /* shader const */
3053 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3054 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3055 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3056
3057 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3058 * does not take effect (TA_CNTL_AUX emited by r600_emit_seamless_cube_map)
3059 */
3060 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3061 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3062 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3063 /* resource */
3064 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3065 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3066 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3067 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3068
3069 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3070
3071 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3072 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3073 rctx->sample_mask.sample_mask = ~0;
3074
3075 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3076 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3077 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3078 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3079 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3080 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3081 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3082 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3083 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3084 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3085 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3086 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3087 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3088 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3089 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3090 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3091 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3092 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3093 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3094 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3095 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3096 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3097 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3098
3099 rctx->b.b.create_blend_state = r600_create_blend_state;
3100 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3101 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3102 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3103 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3104 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3105 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3106 rctx->b.b.set_min_samples = r600_set_min_samples;
3107 rctx->b.b.get_sample_position = r600_get_sample_position;
3108 rctx->b.dma_copy = r600_dma_copy;
3109 }
3110 /* this function must be last */
3111