1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "ac_shader_util.h"
25 
26 #include "sid.h"
27 
28 #include <assert.h>
29 #include <stdlib.h>
30 #include <string.h>
31 
ac_get_spi_shader_z_format(bool writes_z,bool writes_stencil,bool writes_samplemask)32 unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask)
33 {
34    if (writes_z) {
35       /* Z needs 32 bits. */
36       if (writes_samplemask)
37          return V_028710_SPI_SHADER_32_ABGR;
38       else if (writes_stencil)
39          return V_028710_SPI_SHADER_32_GR;
40       else
41          return V_028710_SPI_SHADER_32_R;
42    } else if (writes_stencil || writes_samplemask) {
43       /* Both stencil and sample mask need only 16 bits. */
44       return V_028710_SPI_SHADER_UINT16_ABGR;
45    } else {
46       return V_028710_SPI_SHADER_ZERO;
47    }
48 }
49 
ac_get_cb_shader_mask(unsigned spi_shader_col_format)50 unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format)
51 {
52    unsigned i, cb_shader_mask = 0;
53 
54    for (i = 0; i < 8; i++) {
55       switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
56       case V_028714_SPI_SHADER_ZERO:
57          break;
58       case V_028714_SPI_SHADER_32_R:
59          cb_shader_mask |= 0x1 << (i * 4);
60          break;
61       case V_028714_SPI_SHADER_32_GR:
62          cb_shader_mask |= 0x3 << (i * 4);
63          break;
64       case V_028714_SPI_SHADER_32_AR:
65          cb_shader_mask |= 0x9u << (i * 4);
66          break;
67       case V_028714_SPI_SHADER_FP16_ABGR:
68       case V_028714_SPI_SHADER_UNORM16_ABGR:
69       case V_028714_SPI_SHADER_SNORM16_ABGR:
70       case V_028714_SPI_SHADER_UINT16_ABGR:
71       case V_028714_SPI_SHADER_SINT16_ABGR:
72       case V_028714_SPI_SHADER_32_ABGR:
73          cb_shader_mask |= 0xfu << (i * 4);
74          break;
75       default:
76          assert(0);
77       }
78    }
79    return cb_shader_mask;
80 }
81 
82 /**
83  * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
84  * geometry shader.
85  */
ac_vgt_gs_mode(unsigned gs_max_vert_out,enum chip_class chip_class)86 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
87 {
88    unsigned cut_mode;
89 
90    if (gs_max_vert_out <= 128) {
91       cut_mode = V_028A40_GS_CUT_128;
92    } else if (gs_max_vert_out <= 256) {
93       cut_mode = V_028A40_GS_CUT_256;
94    } else if (gs_max_vert_out <= 512) {
95       cut_mode = V_028A40_GS_CUT_512;
96    } else {
97       assert(gs_max_vert_out <= 1024);
98       cut_mode = V_028A40_GS_CUT_1024;
99    }
100 
101    return S_028A40_MODE(V_028A40_GS_SCENARIO_G) | S_028A40_CUT_MODE(cut_mode) |
102           S_028A40_ES_WRITE_OPTIMIZE(chip_class <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) |
103           S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
104 }
105 
106 /// Translate a (dfmt, nfmt) pair into a chip-appropriate combined format
107 /// value for LLVM8+ tbuffer intrinsics.
ac_get_tbuffer_format(enum chip_class chip_class,unsigned dfmt,unsigned nfmt)108 unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt)
109 {
110    // Some games try to access vertex buffers without a valid format.
111    // This is a game bug, but we should still handle it gracefully.
112    if (dfmt == V_008F0C_IMG_FORMAT_INVALID)
113       return V_008F0C_IMG_FORMAT_INVALID;
114 
115    if (chip_class >= GFX10) {
116       unsigned format;
117       switch (dfmt) {
118       default:
119          unreachable("bad dfmt");
120       case V_008F0C_BUF_DATA_FORMAT_INVALID:
121          format = V_008F0C_IMG_FORMAT_INVALID;
122          break;
123       case V_008F0C_BUF_DATA_FORMAT_8:
124          format = V_008F0C_IMG_FORMAT_8_UINT;
125          break;
126       case V_008F0C_BUF_DATA_FORMAT_8_8:
127          format = V_008F0C_IMG_FORMAT_8_8_UINT;
128          break;
129       case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
130          format = V_008F0C_IMG_FORMAT_8_8_8_8_UINT;
131          break;
132       case V_008F0C_BUF_DATA_FORMAT_16:
133          format = V_008F0C_IMG_FORMAT_16_UINT;
134          break;
135       case V_008F0C_BUF_DATA_FORMAT_16_16:
136          format = V_008F0C_IMG_FORMAT_16_16_UINT;
137          break;
138       case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
139          format = V_008F0C_IMG_FORMAT_16_16_16_16_UINT;
140          break;
141       case V_008F0C_BUF_DATA_FORMAT_32:
142          format = V_008F0C_IMG_FORMAT_32_UINT;
143          break;
144       case V_008F0C_BUF_DATA_FORMAT_32_32:
145          format = V_008F0C_IMG_FORMAT_32_32_UINT;
146          break;
147       case V_008F0C_BUF_DATA_FORMAT_32_32_32:
148          format = V_008F0C_IMG_FORMAT_32_32_32_UINT;
149          break;
150       case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
151          format = V_008F0C_IMG_FORMAT_32_32_32_32_UINT;
152          break;
153       case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
154          format = V_008F0C_IMG_FORMAT_2_10_10_10_UINT;
155          break;
156       }
157 
158       // Use the regularity properties of the combined format enum.
159       //
160       // Note: float is incompatible with 8-bit data formats,
161       //       [us]{norm,scaled} are incomparible with 32-bit data formats.
162       //       [us]scaled are not writable.
163       switch (nfmt) {
164       case V_008F0C_BUF_NUM_FORMAT_UNORM:
165          format -= 4;
166          break;
167       case V_008F0C_BUF_NUM_FORMAT_SNORM:
168          format -= 3;
169          break;
170       case V_008F0C_BUF_NUM_FORMAT_USCALED:
171          format -= 2;
172          break;
173       case V_008F0C_BUF_NUM_FORMAT_SSCALED:
174          format -= 1;
175          break;
176       default:
177          unreachable("bad nfmt");
178       case V_008F0C_BUF_NUM_FORMAT_UINT:
179          break;
180       case V_008F0C_BUF_NUM_FORMAT_SINT:
181          format += 1;
182          break;
183       case V_008F0C_BUF_NUM_FORMAT_FLOAT:
184          format += 2;
185          break;
186       }
187 
188       return format;
189    } else {
190       return dfmt | (nfmt << 4);
191    }
192 }
193 
194 static const struct ac_data_format_info data_format_table[] = {
195    [V_008F0C_BUF_DATA_FORMAT_INVALID] = {0, 4, 0, V_008F0C_BUF_DATA_FORMAT_INVALID},
196    [V_008F0C_BUF_DATA_FORMAT_8] = {1, 1, 1, V_008F0C_BUF_DATA_FORMAT_8},
197    [V_008F0C_BUF_DATA_FORMAT_16] = {2, 1, 2, V_008F0C_BUF_DATA_FORMAT_16},
198    [V_008F0C_BUF_DATA_FORMAT_8_8] = {2, 2, 1, V_008F0C_BUF_DATA_FORMAT_8},
199    [V_008F0C_BUF_DATA_FORMAT_32] = {4, 1, 4, V_008F0C_BUF_DATA_FORMAT_32},
200    [V_008F0C_BUF_DATA_FORMAT_16_16] = {4, 2, 2, V_008F0C_BUF_DATA_FORMAT_16},
201    [V_008F0C_BUF_DATA_FORMAT_10_11_11] = {4, 3, 0, V_008F0C_BUF_DATA_FORMAT_10_11_11},
202    [V_008F0C_BUF_DATA_FORMAT_11_11_10] = {4, 3, 0, V_008F0C_BUF_DATA_FORMAT_11_11_10},
203    [V_008F0C_BUF_DATA_FORMAT_10_10_10_2] = {4, 4, 0, V_008F0C_BUF_DATA_FORMAT_10_10_10_2},
204    [V_008F0C_BUF_DATA_FORMAT_2_10_10_10] = {4, 4, 0, V_008F0C_BUF_DATA_FORMAT_2_10_10_10},
205    [V_008F0C_BUF_DATA_FORMAT_8_8_8_8] = {4, 4, 1, V_008F0C_BUF_DATA_FORMAT_8},
206    [V_008F0C_BUF_DATA_FORMAT_32_32] = {8, 2, 4, V_008F0C_BUF_DATA_FORMAT_32},
207    [V_008F0C_BUF_DATA_FORMAT_16_16_16_16] = {8, 4, 2, V_008F0C_BUF_DATA_FORMAT_16},
208    [V_008F0C_BUF_DATA_FORMAT_32_32_32] = {12, 3, 4, V_008F0C_BUF_DATA_FORMAT_32},
209    [V_008F0C_BUF_DATA_FORMAT_32_32_32_32] = {16, 4, 4, V_008F0C_BUF_DATA_FORMAT_32},
210 };
211 
ac_get_data_format_info(unsigned dfmt)212 const struct ac_data_format_info *ac_get_data_format_info(unsigned dfmt)
213 {
214    assert(dfmt < ARRAY_SIZE(data_format_table));
215    return &data_format_table[dfmt];
216 }
217 
ac_get_sampler_dim(enum chip_class chip_class,enum glsl_sampler_dim dim,bool is_array)218 enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim,
219                                      bool is_array)
220 {
221    switch (dim) {
222    case GLSL_SAMPLER_DIM_1D:
223       if (chip_class == GFX9)
224          return is_array ? ac_image_2darray : ac_image_2d;
225       return is_array ? ac_image_1darray : ac_image_1d;
226    case GLSL_SAMPLER_DIM_2D:
227    case GLSL_SAMPLER_DIM_RECT:
228    case GLSL_SAMPLER_DIM_EXTERNAL:
229       return is_array ? ac_image_2darray : ac_image_2d;
230    case GLSL_SAMPLER_DIM_3D:
231       return ac_image_3d;
232    case GLSL_SAMPLER_DIM_CUBE:
233       return ac_image_cube;
234    case GLSL_SAMPLER_DIM_MS:
235       return is_array ? ac_image_2darraymsaa : ac_image_2dmsaa;
236    case GLSL_SAMPLER_DIM_SUBPASS:
237       return ac_image_2darray;
238    case GLSL_SAMPLER_DIM_SUBPASS_MS:
239       return ac_image_2darraymsaa;
240    default:
241       unreachable("bad sampler dim");
242    }
243 }
244 
ac_get_image_dim(enum chip_class chip_class,enum glsl_sampler_dim sdim,bool is_array)245 enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim,
246                                    bool is_array)
247 {
248    enum ac_image_dim dim = ac_get_sampler_dim(chip_class, sdim, is_array);
249 
250    /* Match the resource type set in the descriptor. */
251    if (dim == ac_image_cube || (chip_class <= GFX8 && dim == ac_image_3d))
252       dim = ac_image_2darray;
253    else if (sdim == GLSL_SAMPLER_DIM_2D && !is_array && chip_class == GFX9) {
254       /* When a single layer of a 3D texture is bound, the shader
255        * will refer to a 2D target, but the descriptor has a 3D type.
256        * Since the HW ignores BASE_ARRAY in this case, we need to
257        * send 3 coordinates. This doesn't hurt when the underlying
258        * texture is non-3D.
259        */
260       dim = ac_image_3d;
261    }
262 
263    return dim;
264 }
265 
ac_get_fs_input_vgpr_cnt(const struct ac_shader_config * config,signed char * face_vgpr_index_ptr,signed char * ancillary_vgpr_index_ptr)266 unsigned ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config,
267                                   signed char *face_vgpr_index_ptr,
268                                   signed char *ancillary_vgpr_index_ptr)
269 {
270    unsigned num_input_vgprs = 0;
271    signed char face_vgpr_index = -1;
272    signed char ancillary_vgpr_index = -1;
273 
274    if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
275       num_input_vgprs += 2;
276    if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
277       num_input_vgprs += 2;
278    if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
279       num_input_vgprs += 2;
280    if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
281       num_input_vgprs += 3;
282    if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
283       num_input_vgprs += 2;
284    if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
285       num_input_vgprs += 2;
286    if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
287       num_input_vgprs += 2;
288    if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
289       num_input_vgprs += 1;
290    if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
291       num_input_vgprs += 1;
292    if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
293       num_input_vgprs += 1;
294    if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
295       num_input_vgprs += 1;
296    if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
297       num_input_vgprs += 1;
298    if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr)) {
299       face_vgpr_index = num_input_vgprs;
300       num_input_vgprs += 1;
301    }
302    if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr)) {
303       ancillary_vgpr_index = num_input_vgprs;
304       num_input_vgprs += 1;
305    }
306    if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
307       num_input_vgprs += 1;
308    if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
309       num_input_vgprs += 1;
310 
311    if (face_vgpr_index_ptr)
312       *face_vgpr_index_ptr = face_vgpr_index;
313    if (ancillary_vgpr_index_ptr)
314       *ancillary_vgpr_index_ptr = ancillary_vgpr_index;
315 
316    return num_input_vgprs;
317 }
318 
ac_choose_spi_color_formats(unsigned format,unsigned swap,unsigned ntype,bool is_depth,struct ac_spi_color_formats * formats)319 void ac_choose_spi_color_formats(unsigned format, unsigned swap, unsigned ntype, bool is_depth,
320                                  struct ac_spi_color_formats *formats)
321 {
322    /* Alpha is needed for alpha-to-coverage.
323     * Blending may be with or without alpha.
324     */
325    unsigned normal = 0;      /* most optimal, may not support blending or export alpha */
326    unsigned alpha = 0;       /* exports alpha, but may not support blending */
327    unsigned blend = 0;       /* supports blending, but may not export alpha */
328    unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
329 
330    /* Choose the SPI color formats. These are required values for RB+.
331     * Other chips have multiple choices, though they are not necessarily better.
332     */
333    switch (format) {
334    case V_028C70_COLOR_5_6_5:
335    case V_028C70_COLOR_1_5_5_5:
336    case V_028C70_COLOR_5_5_5_1:
337    case V_028C70_COLOR_4_4_4_4:
338    case V_028C70_COLOR_10_11_11:
339    case V_028C70_COLOR_11_11_10:
340    case V_028C70_COLOR_5_9_9_9:
341    case V_028C70_COLOR_8:
342    case V_028C70_COLOR_8_8:
343    case V_028C70_COLOR_8_8_8_8:
344    case V_028C70_COLOR_10_10_10_2:
345    case V_028C70_COLOR_2_10_10_10:
346       if (ntype == V_028C70_NUMBER_UINT)
347          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
348       else if (ntype == V_028C70_NUMBER_SINT)
349          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
350       else
351          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
352       break;
353 
354    case V_028C70_COLOR_16:
355    case V_028C70_COLOR_16_16:
356    case V_028C70_COLOR_16_16_16_16:
357       if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) {
358          /* UNORM16 and SNORM16 don't support blending */
359          if (ntype == V_028C70_NUMBER_UNORM)
360             normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
361          else
362             normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
363 
364          /* Use 32 bits per channel for blending. */
365          if (format == V_028C70_COLOR_16) {
366             if (swap == V_028C70_SWAP_STD) { /* R */
367                blend = V_028714_SPI_SHADER_32_R;
368                blend_alpha = V_028714_SPI_SHADER_32_AR;
369             } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
370                blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
371             else
372                assert(0);
373          } else if (format == V_028C70_COLOR_16_16) {
374             if (swap == V_028C70_SWAP_STD) { /* RG */
375                blend = V_028714_SPI_SHADER_32_GR;
376                blend_alpha = V_028714_SPI_SHADER_32_ABGR;
377             } else if (swap == V_028C70_SWAP_ALT) /* RA */
378                blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
379             else
380                assert(0);
381          } else /* 16_16_16_16 */
382             blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
383       } else if (ntype == V_028C70_NUMBER_UINT)
384          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
385       else if (ntype == V_028C70_NUMBER_SINT)
386          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
387       else if (ntype == V_028C70_NUMBER_FLOAT)
388          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
389       else
390          assert(0);
391       break;
392 
393    case V_028C70_COLOR_32:
394       if (swap == V_028C70_SWAP_STD) { /* R */
395          blend = normal = V_028714_SPI_SHADER_32_R;
396          alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
397       } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
398          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
399       else
400          assert(0);
401       break;
402 
403    case V_028C70_COLOR_32_32:
404       if (swap == V_028C70_SWAP_STD) { /* RG */
405          blend = normal = V_028714_SPI_SHADER_32_GR;
406          alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
407       } else if (swap == V_028C70_SWAP_ALT) /* RA */
408          alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
409       else
410          assert(0);
411       break;
412 
413    case V_028C70_COLOR_32_32_32_32:
414    case V_028C70_COLOR_8_24:
415    case V_028C70_COLOR_24_8:
416    case V_028C70_COLOR_X24_8_32_FLOAT:
417       alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
418       break;
419 
420    default:
421       assert(0);
422       return;
423    }
424 
425    /* The DB->CB copy needs 32_ABGR. */
426    if (is_depth)
427       alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
428 
429    formats->normal = normal;
430    formats->alpha = alpha;
431    formats->blend = blend;
432    formats->blend_alpha = blend_alpha;
433 }
434