1 /* -*- c++ -*- */ 2 /* 3 * Copyright © 2010-2016 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 */ 24 25 #ifndef BRW_IR_H 26 #define BRW_IR_H 27 28 #include <assert.h> 29 #include "brw_reg.h" 30 #include "compiler/glsl/list.h" 31 32 #define MAX_SAMPLER_MESSAGE_SIZE 11 33 #define MAX_VGRF_SIZE 16 34 35 #ifdef __cplusplus 36 struct backend_reg : private brw_reg 37 { backend_regbackend_reg38 backend_reg() {} backend_regbackend_reg39 backend_reg(const struct brw_reg ®) : brw_reg(reg), offset(0) {} 40 as_brw_regbackend_reg41 const brw_reg &as_brw_reg() const 42 { 43 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); 44 assert(offset == 0); 45 return static_cast<const brw_reg &>(*this); 46 } 47 as_brw_regbackend_reg48 brw_reg &as_brw_reg() 49 { 50 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); 51 assert(offset == 0); 52 return static_cast<brw_reg &>(*this); 53 } 54 55 bool equals(const backend_reg &r) const; 56 bool negative_equals(const backend_reg &r) const; 57 58 bool is_zero() const; 59 bool is_one() const; 60 bool is_negative_one() const; 61 bool is_null() const; 62 bool is_accumulator() const; 63 64 /** Offset from the start of the (virtual) register in bytes. */ 65 uint16_t offset; 66 67 using brw_reg::type; 68 using brw_reg::file; 69 using brw_reg::negate; 70 using brw_reg::abs; 71 using brw_reg::address_mode; 72 using brw_reg::subnr; 73 using brw_reg::nr; 74 75 using brw_reg::swizzle; 76 using brw_reg::writemask; 77 using brw_reg::indirect_offset; 78 using brw_reg::vstride; 79 using brw_reg::width; 80 using brw_reg::hstride; 81 82 using brw_reg::df; 83 using brw_reg::f; 84 using brw_reg::d; 85 using brw_reg::ud; 86 using brw_reg::d64; 87 using brw_reg::u64; 88 }; 89 90 struct bblock_t; 91 92 struct backend_instruction : public exec_node { 93 bool is_3src(const struct gen_device_info *devinfo) const; 94 bool is_tex() const; 95 bool is_math() const; 96 bool is_control_flow() const; 97 bool is_commutative() const; 98 bool can_do_source_mods() const; 99 bool can_do_saturate() const; 100 bool can_do_cmod() const; 101 bool reads_accumulator_implicitly() const; 102 bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const; 103 104 void remove(bblock_t *block); 105 void insert_after(bblock_t *block, backend_instruction *inst); 106 void insert_before(bblock_t *block, backend_instruction *inst); 107 void insert_before(bblock_t *block, exec_list *list); 108 109 /** 110 * True if the instruction has side effects other than writing to 111 * its destination registers. You are expected not to reorder or 112 * optimize these out unless you know what you are doing. 113 */ 114 bool has_side_effects() const; 115 116 /** 117 * True if the instruction might be affected by side effects of other 118 * instructions. 119 */ 120 bool is_volatile() const; 121 #else 122 struct backend_instruction { 123 struct exec_node link; 124 #endif 125 /** @{ 126 * Annotation for the generated IR. One of the two can be set. 127 */ 128 const void *ir; 129 const char *annotation; 130 /** @} */ 131 132 /** 133 * Execution size of the instruction. This is used by the generator to 134 * generate the correct binary for the given instruction. Current valid 135 * values are 1, 4, 8, 16, 32. 136 */ 137 uint8_t exec_size; 138 139 /** 140 * Channel group from the hardware execution and predication mask that 141 * should be applied to the instruction. The subset of channel enable 142 * signals (calculated from the EU control flow and predication state) 143 * given by [group, group + exec_size) will be used to mask GRF writes and 144 * any other side effects of the instruction. 145 */ 146 uint8_t group; 147 148 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */ 149 uint8_t mlen; /**< SEND message length */ 150 uint8_t ex_mlen; /**< SENDS extended message length */ 151 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ 152 uint8_t target; /**< MRT target. */ 153 uint8_t sfid; /**< SFID for SEND instructions */ 154 uint32_t desc; /**< SEND[S] message descriptor immediate */ 155 unsigned size_written; /**< Data written to the destination register in bytes. */ 156 157 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ 158 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */ 159 enum brw_predicate predicate; 160 bool predicate_inverse:1; 161 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */ 162 bool force_writemask_all:1; 163 bool no_dd_clear:1; 164 bool no_dd_check:1; 165 bool saturate:1; 166 bool shadow_compare:1; 167 bool check_tdr:1; /**< Only valid for SEND; turns it into a SENDC */ 168 bool send_has_side_effects:1; /**< Only valid for SHADER_OPCODE_SEND */ 169 bool send_is_volatile:1; /**< Only valid for SHADER_OPCODE_SEND */ 170 bool eot:1; 171 172 /* Chooses which flag subregister (f0.0 to f1.1) is used for conditional 173 * mod and predication. 174 */ 175 unsigned flag_subreg:2; 176 177 /** The number of hardware registers used for a message header. */ 178 uint8_t header_size; 179 }; 180 181 #endif 182