1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "si_build_pm4.h"
27 #include "sid.h"
28 #include "util/u_memory.h"
29
si_pm4_cmd_begin(struct si_pm4_state * state,unsigned opcode)30 static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
31 {
32 assert(state->ndw < SI_PM4_MAX_DW);
33 state->last_opcode = opcode;
34 state->last_pm4 = state->ndw++;
35 }
36
si_pm4_cmd_add(struct si_pm4_state * state,uint32_t dw)37 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
38 {
39 assert(state->ndw < SI_PM4_MAX_DW);
40 state->pm4[state->ndw++] = dw;
41 state->last_opcode = -1;
42 }
43
si_pm4_cmd_end(struct si_pm4_state * state,bool predicate)44 static void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
45 {
46 unsigned count;
47 count = state->ndw - state->last_pm4 - 2;
48 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate);
49 }
50
si_pm4_set_reg(struct si_pm4_state * state,unsigned reg,uint32_t val)51 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
52 {
53 unsigned opcode;
54
55 SI_CHECK_SHADOWED_REGS(reg, 1);
56
57 if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
58 opcode = PKT3_SET_CONFIG_REG;
59 reg -= SI_CONFIG_REG_OFFSET;
60
61 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
62 opcode = PKT3_SET_SH_REG;
63 reg -= SI_SH_REG_OFFSET;
64
65 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
66 opcode = PKT3_SET_CONTEXT_REG;
67 reg -= SI_CONTEXT_REG_OFFSET;
68
69 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
70 opcode = PKT3_SET_UCONFIG_REG;
71 reg -= CIK_UCONFIG_REG_OFFSET;
72
73 } else {
74 PRINT_ERR("Invalid register offset %08x!\n", reg);
75 return;
76 }
77
78 reg >>= 2;
79
80 assert(state->ndw + 2 <= SI_PM4_MAX_DW);
81
82 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
83 si_pm4_cmd_begin(state, opcode);
84 state->pm4[state->ndw++] = reg;
85 }
86
87 state->last_reg = reg;
88 state->pm4[state->ndw++] = val;
89 si_pm4_cmd_end(state, false);
90 }
91
si_pm4_clear_state(struct si_pm4_state * state)92 void si_pm4_clear_state(struct si_pm4_state *state)
93 {
94 state->ndw = 0;
95 }
96
si_pm4_free_state(struct si_context * sctx,struct si_pm4_state * state,unsigned idx)97 void si_pm4_free_state(struct si_context *sctx, struct si_pm4_state *state, unsigned idx)
98 {
99 if (!state)
100 return;
101
102 if (idx != ~0 && sctx->emitted.array[idx] == state) {
103 sctx->emitted.array[idx] = NULL;
104 }
105
106 si_pm4_clear_state(state);
107 FREE(state);
108 }
109
si_pm4_emit(struct si_context * sctx,struct si_pm4_state * state)110 void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
111 {
112 struct radeon_cmdbuf *cs = sctx->gfx_cs;
113
114 if (state->shader) {
115 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, state->shader->bo,
116 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
117 }
118
119 radeon_emit_array(cs, state->pm4, state->ndw);
120
121 if (state->atom.emit)
122 state->atom.emit(sctx);
123 }
124
si_pm4_reset_emitted(struct si_context * sctx,bool first_cs)125 void si_pm4_reset_emitted(struct si_context *sctx, bool first_cs)
126 {
127 if (!first_cs && sctx->shadowed_regs) {
128 /* Only dirty states that contain buffers, so that they are
129 * added to the buffer list on the next draw call.
130 */
131 for (unsigned i = 0; i < SI_NUM_STATES; i++) {
132 struct si_pm4_state *state = sctx->emitted.array[i];
133
134 if (state && state->shader) {
135 sctx->emitted.array[i] = NULL;
136 sctx->dirty_states |= 1 << i;
137 }
138 }
139 return;
140 }
141
142 memset(&sctx->emitted, 0, sizeof(sctx->emitted));
143 sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES);
144 }
145