| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | srsra-diagnostics.s | 3 srsra z30.b, z10.b, #0 label
8 srsra z18.b, z27.b, #9 label
13 srsra z26.h, z4.h, #0 label
18 srsra z25.h, z10.h, #17 label
23 srsra z17.s, z0.s, #0 label
28 srsra z0.s, z15.s, #33 label
33 srsra z4.d, z13.d, #0 label
38 srsra z26.d, z26.d, #65 label
47 srsra z0.b, z0.d, #1 label
57 srsra z0.d, z1.d, #64 label
|
| D | srsra.s | 10 srsra z0.b, z0.b, #1 label
16 srsra z31.b, z31.b, #8 label
22 srsra z0.h, z0.h, #1 label
28 srsra z31.h, z31.h, #16 label
34 srsra z0.s, z0.s, #1 label
40 srsra z31.s, z31.s, #32 label
46 srsra z0.d, z0.d, #1 label
52 srsra z31.d, z31.d, #64 label
68 srsra z0.d, z1.d, #1 label
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1376 srsra d0, d0, #1 define
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 1376 srsra d0, d0, #1 define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 1746 __ srsra(d21, d30, 63); in GenerateTestSequenceNEON() local
1747 __ srsra(v27.V16B(), v30.V16B(), 6); in GenerateTestSequenceNEON() local
1748 __ srsra(v20.V2D(), v12.V2D(), 27); in GenerateTestSequenceNEON() local
1749 __ srsra(v0.V2S(), v17.V2S(), 5); in GenerateTestSequenceNEON() local
1750 __ srsra(v14.V4H(), v16.V4H(), 15); in GenerateTestSequenceNEON() local
1751 __ srsra(v18.V4S(), v3.V4S(), 20); in GenerateTestSequenceNEON() local
1752 __ srsra(v21.V8B(), v1.V8B(), 1); in GenerateTestSequenceNEON() local
1753 __ srsra(v31.V8H(), v25.V8H(), 2); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5102 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) { in srsra() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 1969 LogicVRegister Simulator::srsra(VectorFormat vform, in srsra() function in vixl::aarch64::Simulator
|