/external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
D | usra-diagnostics.s | 3 usra z30.b, z10.b, #0 label 8 usra z18.b, z27.b, #9 label 13 usra z26.h, z4.h, #0 label 18 usra z25.h, z10.h, #17 label 23 usra z17.s, z0.s, #0 label 28 usra z0.s, z15.s, #33 label 33 usra z4.d, z13.d, #0 label 38 usra z26.d, z26.d, #65 label 47 usra z0.b, z0.d, #1 label 57 usra z0.d, z1.d, #64 label
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D | usra.s | 10 usra z0.b, z0.b, #1 label 16 usra z31.b, z31.b, #8 label 22 usra z0.h, z0.h, #1 label 28 usra z31.h, z31.h, #16 label 34 usra z0.s, z0.s, #1 label 40 usra z31.s, z31.s, #32 label 46 usra z0.d, z0.d, #1 label 52 usra z31.d, z31.d, #64 label 68 usra z0.d, z1.d, #1 label
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/external/llvm/test/MC/AArch64/ |
D | arm64-advsimd.s | 1395 usra d0, d0, #1 define
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/external/llvm-project/llvm/test/MC/AArch64/ |
D | arm64-advsimd.s | 1395 usra d0, d0, #1 define
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/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 2452 __ usra(d28, d27, 37); in GenerateTestSequenceNEON() local 2453 __ usra(v5.V16B(), v22.V16B(), 5); in GenerateTestSequenceNEON() local 2454 __ usra(v2.V2D(), v19.V2D(), 33); in GenerateTestSequenceNEON() local 2455 __ usra(v0.V2S(), v0.V2S(), 21); in GenerateTestSequenceNEON() local 2456 __ usra(v7.V4H(), v6.V4H(), 12); in GenerateTestSequenceNEON() local 2457 __ usra(v4.V4S(), v17.V4S(), 9); in GenerateTestSequenceNEON() local 2458 __ usra(v9.V8B(), v12.V8B(), 7); in GenerateTestSequenceNEON() local 2459 __ usra(v3.V8H(), v27.V8H(), 14); in GenerateTestSequenceNEON() local
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.cc | 5095 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) { in usra() function in vixl::aarch64::Assembler
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D | logic-aarch64.cc | 1959 LogicVRegister Simulator::usra(VectorFormat vform, in usra() function in vixl::aarch64::Simulator
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