1 // Copyright (c) Facebook, Inc. and its affiliates.
2 // All rights reserved.
3 //
4 // Copyright 2019 Google LLC
5 //
6 // This source code is licensed under the BSD-style license found in the
7 // LICENSE file in the root directory of this source tree.
8
9 #include <assert.h>
10 #include <stdint.h>
11 #include <stddef.h>
12
13 #include <arm_neon.h>
14
15 #include <xnnpack/requantization-stubs.h>
16
17
xnn_qs8_requantize_fp32__neon(size_t n,const int32_t * input,float scale,int8_t zero_point,int8_t qmin,int8_t qmax,int8_t * output)18 void xnn_qs8_requantize_fp32__neon(
19 size_t n,
20 const int32_t* input,
21 float scale,
22 int8_t zero_point,
23 int8_t qmin,
24 int8_t qmax,
25 int8_t* output)
26 {
27 assert(n % 16 == 0);
28 assert(scale < 1.0f);
29 assert(scale >= 0x1.0p-32f);
30
31 const float32x4_t vscale = vdupq_n_f32(scale);
32 #ifdef __aarch64__
33 const int16x8_t vzero_point = vdupq_n_s16((int16_t) zero_point);
34 const int8x16_t vqmin = vdupq_n_s8(qmin);
35 const int8x16_t vqmax = vdupq_n_s8(qmax);
36 #else
37 const float32x4_t vfmin = vdupq_n_f32((float) ((int32_t) qmin - (int32_t) zero_point));
38 const float32x4_t vfmax = vdupq_n_f32((float) ((int32_t) qmax - (int32_t) zero_point));
39 const float32x4_t vfmagic = vdupq_n_f32(12582912.0f);
40 const int32x4_t vimagic = vdupq_n_s32(INT32_C(0x4B400000) - (int32_t) zero_point);
41 #endif
42 for (; n != 0; n -= 16) {
43 const int32x4_t x = vld1q_s32(input);
44 const int32x4_t y = vld1q_s32(input + 4);
45 const int32x4_t z = vld1q_s32(input + 8);
46 const int32x4_t w = vld1q_s32(input + 12);
47 input += 16;
48
49 // Convert int32_t input to FP32 and multiply by FP32 scale.
50 // Both operations involve statistically unbiased roundings:
51 // - Large int32_t values can't be exactly represented as FP32. The conversion instruction in ARM NEON would
52 // round it to nearest FP32 value with ties to even.
53 // - Product of two FP32 values is generally not exactly representation as an FP32 value, and will be rounded
54 // to nearest FP32 value with ties to even.
55 const float32x4_t x_scaled = vmulq_f32(vcvtq_f32_s32(x), vscale);
56 const float32x4_t y_scaled = vmulq_f32(vcvtq_f32_s32(y), vscale);
57 const float32x4_t z_scaled = vmulq_f32(vcvtq_f32_s32(z), vscale);
58 const float32x4_t w_scaled = vmulq_f32(vcvtq_f32_s32(w), vscale);
59
60 #ifdef __aarch64__
61 // Leverage "Floating-point Convert to Signed integer, rouding to nearest with ties to even" instruction.
62 // This is an ARMv8 instruction (always available in AArch64), which saturates result on overflow.
63 // We don't need to specifically consider saturated results, they will be clamped at the last stage.
64 const int32x4_t x_rounded = vcvtnq_s32_f32(x_scaled);
65 const int32x4_t y_rounded = vcvtnq_s32_f32(y_scaled);
66 const int32x4_t z_rounded = vcvtnq_s32_f32(z_scaled);
67 const int32x4_t w_rounded = vcvtnq_s32_f32(w_scaled);
68
69 // Standard final sequence on ARM NEON:
70 // - Pack to int16_t and saturate
71 // - Add zero point
72 // - Pack to uint8_t and saturate
73 // - Clamp between qmin and qmax
74 const int16x8_t xy_packed = vqaddq_s16(vqmovn_high_s32(vqmovn_s32(x_rounded), y_rounded), vzero_point);
75 const int16x8_t zw_packed = vqaddq_s16(vqmovn_high_s32(vqmovn_s32(z_rounded), w_rounded), vzero_point);
76 const int8x16_t xyzw_packed = vqmovn_high_s16(vqmovn_s16(xy_packed), zw_packed);
77 const int8x16_t xyzw_clamped = vmaxq_s8(vminq_s8(xyzw_packed, vqmax), vqmin);
78
79 // AArch32 version:
80 // 4x VCVT.F32.S32 Qd, Qm
81 // 4x VMUL.F32 Qd, Qm, Qn
82 // 4x VMIN.F32 Qd, Qm, Qn
83 // 4x VMAX.F32 Qd, Qm, Qn
84 // 4x VADD.F32 Qd, Qm, Qn
85 // 4x VSUB.S32 Qd, Qm, Qn
86 // 4x VMOVN.I32 Dd, Qm
87 // 2x VMOVN.I16 Dd, Qm
88 // ---------------------
89 // 30 instructions total
90 vst1q_s8(output, xyzw_clamped); output += 16;
91 #else
92 // AArch64 version:
93 // 4x SCVTF Vd.4S, Vn.4S
94 // 4x FMUL Vd.4S, Vn.4S, Vm.4S
95 // 4x FCVTNS Vd.4S, Vn.4S
96 // 2x SQXTN Vd.4H, Vn.4S
97 // 2x SQXTN2 Vd.8H, Vn.4S
98 // 2x SQADD Vd.8H, Vn.8H, Vm.8H
99 // 1x SQXTN Vd.8B, Vn.8H
100 // 1x SQXTN2 Vd.16B, Vn.8H
101 // 1x SMIN Vd.16B, Vn.16B, Vm.16B
102 // 1x SMAX Vd.16B, Vn.16B, Vm.16B
103 // ---------------------
104 // 22 instructions total
105
106 // ARMv7 NEON offers only a floating-point to integer conversion instruction with rounding towards zero.
107 // In lieu of conversion instruction with rounding-to-nearest-even, we use a magic trick of adding a large
108 // number (1.5 * 2**23) to scaled value to cause rounding to integer, and then substracing this magic number as
109 // integer. This trick works only in a limited range (absolute value of input must be less than 2**22), so
110 // generally we have to clamp input to this range before using the magic. However, clamping to any smaller range
111 // works just as well, and thus we clamp to [qmin - zero point, qmax - zero point] range so that after we add
112 // zero point to the result, it gets into target [qmin, qmax] range.
113 const float32x4_t x_clamped = vminq_f32(vmaxq_f32(x_scaled, vfmin), vfmax);
114 const float32x4_t y_clamped = vminq_f32(vmaxq_f32(y_scaled, vfmin), vfmax);
115 const float32x4_t z_clamped = vminq_f32(vmaxq_f32(z_scaled, vfmin), vfmax);
116 const float32x4_t w_clamped = vminq_f32(vmaxq_f32(w_scaled, vfmin), vfmax);
117
118 // Conversion to integer using the "magic trick". Rounding is performed in the output of addition operation,
119 // and result is rounded to nearest even integer with ties to even.
120 const int32x4_t x_biased = vsubq_s32(vreinterpretq_s32_f32(vaddq_f32(x_clamped, vfmagic)), vimagic);
121 const int32x4_t y_biased = vsubq_s32(vreinterpretq_s32_f32(vaddq_f32(y_clamped, vfmagic)), vimagic);
122 const int32x4_t z_biased = vsubq_s32(vreinterpretq_s32_f32(vaddq_f32(z_clamped, vfmagic)), vimagic);
123 const int32x4_t w_biased = vsubq_s32(vreinterpretq_s32_f32(vaddq_f32(w_clamped, vfmagic)), vimagic);
124
125 // Select low 8 bits of each 32-bit integer in the vectors for the output.
126 // Since result is already clamped to [qmin, qmax] subrange of [0, 255], saturation is not needed.
127 const int16x8_t xy_packed = vcombine_s16(vmovn_s32(x_biased), vmovn_s32(y_biased));
128 const int16x8_t zw_packed = vcombine_s16(vmovn_s32(z_biased), vmovn_s32(w_biased));
129 const int8x16_t xyzw_packed = vcombine_s8(vmovn_s16(xy_packed), vmovn_s16(zw_packed));
130
131 vst1q_s8(output, xyzw_packed); output += 16;
132 #endif
133 }
134 }
135