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/external/vixl/test/aarch32/traces/
Dassembler-cond-rdlow-operand-imm8-mov-t32.h38 0x4f, 0xf0, 0x00, 0x00 // mov al r0 0
41 0x4f, 0xf0, 0x01, 0x00 // mov al r0 1
44 0x4f, 0xf0, 0x02, 0x00 // mov al r0 2
47 0x4f, 0xf0, 0x03, 0x00 // mov al r0 3
50 0x4f, 0xf0, 0x04, 0x00 // mov al r0 4
53 0x4f, 0xf0, 0x05, 0x00 // mov al r0 5
56 0x4f, 0xf0, 0x06, 0x00 // mov al r0 6
59 0x4f, 0xf0, 0x07, 0x00 // mov al r0 7
62 0x4f, 0xf0, 0x08, 0x00 // mov al r0 8
65 0x4f, 0xf0, 0x09, 0x00 // mov al r0 9
[all …]
Dassembler-cond-rd-operand-const-mov-t32.h38 0x4f, 0xf4, 0xff, 0x70 // mov al r0 0x000001fe
41 0x4f, 0xf4, 0x7f, 0x70 // mov al r0 0x000003fc
44 0x4f, 0xf4, 0xff, 0x60 // mov al r0 0x000007f8
47 0x4f, 0xf4, 0x7f, 0x60 // mov al r0 0x00000ff0
50 0x4f, 0xf4, 0xff, 0x50 // mov al r0 0x00001fe0
53 0x4f, 0xf4, 0x7f, 0x50 // mov al r0 0x00003fc0
56 0x4f, 0xf4, 0xff, 0x40 // mov al r0 0x00007f80
59 0x4f, 0xf4, 0x7f, 0x40 // mov al r0 0x0000ff00
62 0x4f, 0xf4, 0xff, 0x30 // mov al r0 0x0001fe00
65 0x4f, 0xf4, 0x7f, 0x30 // mov al r0 0x0003fc00
[all …]
Dassembler-cond-rd-operand-rn-shift-amount-1to31-mov-t32.h38 0x4f, 0xea, 0x78, 0x5e // mov al r14 r8 ROR 21
41 0x4f, 0xea, 0x3d, 0x15 // mov al r5 r13 ROR 4
44 0x4f, 0xea, 0x33, 0x10 // mov al r0 r3 ROR 4
47 0x4f, 0xea, 0xfe, 0x13 // mov al r3 r14 ROR 7
50 0x4f, 0xea, 0x86, 0x72 // mov al r2 r6 LSL 30
53 0x4f, 0xea, 0x84, 0x6b // mov al r11 r4 LSL 26
56 0x4f, 0xea, 0x80, 0x77 // mov al r7 r0 LSL 30
59 0x4f, 0xea, 0x79, 0x40 // mov al r0 r9 ROR 17
62 0x4f, 0xea, 0xf3, 0x7b // mov al r11 r3 ROR 31
65 0x4f, 0xea, 0x38, 0x58 // mov al r8 r8 ROR 20
[all …]
Dassembler-cond-rd-operand-rn-shift-amount-1to32-mov-t32.h38 0x4f, 0xea, 0x57, 0x17 // mov al r7 r7 LSR 5
41 0x4f, 0xea, 0xa3, 0x70 // mov al r0 r3 ASR 30
44 0x4f, 0xea, 0xe5, 0x7a // mov al r10 r5 ASR 31
47 0x4f, 0xea, 0x29, 0x4c // mov al r12 r9 ASR 16
50 0x4f, 0xea, 0xe3, 0x75 // mov al r5 r3 ASR 31
53 0x4f, 0xea, 0xa8, 0x2a // mov al r10 r8 ASR 10
56 0x4f, 0xea, 0xd7, 0x26 // mov al r6 r7 LSR 11
59 0x4f, 0xea, 0xec, 0x7d // mov al r13 r12 ASR 31
62 0x4f, 0xea, 0xa0, 0x54 // mov al r4 r0 ASR 22
65 0x4f, 0xea, 0xea, 0x53 // mov al r3 r10 ASR 23
[all …]
Dassembler-cond-rd-operand-rn-ror-amount-sxtb-t32.h38 0x40, 0xb2 // sxtb al r0 r0 ROR 0
41 0x4f, 0xfa, 0x90, 0xf0 // sxtb al r0 r0 ROR 8
44 0x4f, 0xfa, 0xa0, 0xf0 // sxtb al r0 r0 ROR 16
47 0x4f, 0xfa, 0xb0, 0xf0 // sxtb al r0 r0 ROR 24
50 0x48, 0xb2 // sxtb al r0 r1 ROR 0
53 0x4f, 0xfa, 0x91, 0xf0 // sxtb al r0 r1 ROR 8
56 0x4f, 0xfa, 0xa1, 0xf0 // sxtb al r0 r1 ROR 16
59 0x4f, 0xfa, 0xb1, 0xf0 // sxtb al r0 r1 ROR 24
62 0x50, 0xb2 // sxtb al r0 r2 ROR 0
65 0x4f, 0xfa, 0x92, 0xf0 // sxtb al r0 r2 ROR 8
[all …]
Dassembler-cond-rd-rn-rrx-t32.h38 0x4f, 0xea, 0x30, 0x00 // rrx al r0 r0
41 0x4f, 0xea, 0x31, 0x00 // rrx al r0 r1
44 0x4f, 0xea, 0x32, 0x00 // rrx al r0 r2
47 0x4f, 0xea, 0x33, 0x00 // rrx al r0 r3
50 0x4f, 0xea, 0x34, 0x00 // rrx al r0 r4
53 0x4f, 0xea, 0x35, 0x00 // rrx al r0 r5
56 0x4f, 0xea, 0x36, 0x00 // rrx al r0 r6
59 0x4f, 0xea, 0x37, 0x00 // rrx al r0 r7
62 0x4f, 0xea, 0x38, 0x00 // rrx al r0 r8
65 0x4f, 0xea, 0x39, 0x00 // rrx al r0 r9
[all …]
Dassembler-cond-rd-operand-rn-sxtb-t32.h38 0x40, 0xb2 // sxtb al r0 r0
41 0x48, 0xb2 // sxtb al r0 r1
44 0x50, 0xb2 // sxtb al r0 r2
47 0x58, 0xb2 // sxtb al r0 r3
50 0x60, 0xb2 // sxtb al r0 r4
53 0x68, 0xb2 // sxtb al r0 r5
56 0x70, 0xb2 // sxtb al r0 r6
59 0x78, 0xb2 // sxtb al r0 r7
62 0x4f, 0xfa, 0x88, 0xf0 // sxtb al r0 r8
65 0x4f, 0xfa, 0x89, 0xf0 // sxtb al r0 r9
[all …]
Dassembler-cond-rd-operand-imm16-mov-t32.h38 0x4f, 0xf0, 0x00, 0x00 // mov al r0 0x0000
41 0x4f, 0xf0, 0x01, 0x00 // mov al r0 0x0001
44 0x4f, 0xf0, 0x02, 0x00 // mov al r0 0x0002
47 0x4f, 0xf0, 0x20, 0x00 // mov al r0 0x0020
50 0x4f, 0xf0, 0x7d, 0x00 // mov al r0 0x007d
53 0x4f, 0xf0, 0x7e, 0x00 // mov al r0 0x007e
56 0x4f, 0xf0, 0x7f, 0x00 // mov al r0 0x007f
59 0x47, 0xf6, 0xfd, 0x70 // mov al r0 0x7ffd
62 0x47, 0xf6, 0xfe, 0x70 // mov al r0 0x7ffe
65 0x47, 0xf6, 0xff, 0x70 // mov al r0 0x7fff
[all …]
Dassembler-cond-rd-operand-imm16-movw-t32.h38 0x40, 0xf2, 0x00, 0x00 // movw al r0 0x0000
41 0x40, 0xf2, 0x01, 0x00 // movw al r0 0x0001
44 0x40, 0xf2, 0x02, 0x00 // movw al r0 0x0002
47 0x40, 0xf2, 0x20, 0x00 // movw al r0 0x0020
50 0x40, 0xf2, 0x7d, 0x00 // movw al r0 0x007d
53 0x40, 0xf2, 0x7e, 0x00 // movw al r0 0x007e
56 0x40, 0xf2, 0x7f, 0x00 // movw al r0 0x007f
59 0x47, 0xf6, 0xfd, 0x70 // movw al r0 0x7ffd
62 0x47, 0xf6, 0xfe, 0x70 // movw al r0 0x7ffe
65 0x47, 0xf6, 0xff, 0x70 // movw al r0 0x7fff
[all …]
Dassembler-cond-rd-operand-const-cmn-t32.h38 0x10, 0xf5, 0xff, 0x7f // cmn al r0 0x000001fe
41 0x10, 0xf5, 0x7f, 0x7f // cmn al r0 0x000003fc
44 0x10, 0xf5, 0xff, 0x6f // cmn al r0 0x000007f8
47 0x10, 0xf5, 0x7f, 0x6f // cmn al r0 0x00000ff0
50 0x10, 0xf5, 0xff, 0x5f // cmn al r0 0x00001fe0
53 0x10, 0xf5, 0x7f, 0x5f // cmn al r0 0x00003fc0
56 0x10, 0xf5, 0xff, 0x4f // cmn al r0 0x00007f80
59 0x10, 0xf5, 0x7f, 0x4f // cmn al r0 0x0000ff00
62 0x10, 0xf5, 0xff, 0x3f // cmn al r0 0x0001fe00
65 0x10, 0xf5, 0x7f, 0x3f // cmn al r0 0x0003fc00
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-2velem.s.cs1 # CS_ARCH_ARM64, 0, None
2 0x20,0x08,0x82,0x2f = mla v0.2s, v1.2s, v2.s[2]
3 0x20,0x08,0x96,0x2f = mla v0.2s, v1.2s, v22.s[2]
4 0x03,0x01,0xa2,0x6f = mla v3.4s, v8.4s, v2.s[1]
5 0x03,0x09,0xb6,0x6f = mla v3.4s, v8.4s, v22.s[3]
6 0x20,0x00,0x62,0x2f = mla v0.4h, v1.4h, v2.h[2]
7 0x20,0x00,0x6f,0x2f = mla v0.4h, v1.4h, v15.h[2]
8 0x20,0x08,0x72,0x6f = mla v0.8h, v1.8h, v2.h[7]
9 0x20,0x08,0x6e,0x6f = mla v0.8h, v1.8h, v14.h[6]
10 0x20,0x48,0x82,0x2f = mls v0.2s, v1.2s, v2.s[2]
[all …]
Dneon-simd-shift.s.cs1 # CS_ARCH_ARM64, 0, None
2 0x20,0x04,0x0d,0x0f = sshr v0.8b, v1.8b, #3
3 0x20,0x04,0x1d,0x0f = sshr v0.4h, v1.4h, #3
4 0x20,0x04,0x3d,0x0f = sshr v0.2s, v1.2s, #3
5 0x20,0x04,0x0d,0x4f = sshr v0.16b, v1.16b, #3
6 0x20,0x04,0x1d,0x4f = sshr v0.8h, v1.8h, #3
7 0x20,0x04,0x3d,0x4f = sshr v0.4s, v1.4s, #3
8 0x20,0x04,0x7d,0x4f = sshr v0.2d, v1.2d, #3
9 0x20,0x04,0x0d,0x2f = ushr v0.8b, v1.8b, #3
10 0x20,0x04,0x1d,0x2f = ushr v0.4h, v1.4h, #3
[all …]
Dneon-mov.s.cs1 # CS_ARCH_ARM64, 0, None
2 0x20,0x04,0x00,0x0f = movi v0.2s, #0x1
3 0x01,0x04,0x00,0x0f = movi v1.2s, #0x0
4 0x2f,0x24,0x00,0x0f = movi v15.2s, #0x1, lsl #8
5 0x30,0x44,0x00,0x0f = movi v16.2s, #0x1, lsl #16
6 0x3f,0x64,0x00,0x0f = movi v31.2s, #0x1, lsl #24
7 0x20,0x04,0x00,0x4f = movi v0.4s, #0x1
8 0x20,0x24,0x00,0x4f = movi v0.4s, #0x1, lsl #8
9 0x20,0x44,0x00,0x4f = movi v0.4s, #0x1, lsl #16
10 0x20,0x64,0x00,0x4f = movi v0.4s, #0x1, lsl #24
[all …]
/external/llvm/test/MC/X86/
Dintel-syntax-x86-64-avx.s4 // CHECK: encoding: [0xc4,0xe2,0xf9,0x92,0x14,0x4f]
8 // CHECK: encoding: [0xc4,0xe2,0xf9,0x93,0x14,0x4f]
12 // CHECK: encoding: [0xc4,0xe2,0xfd,0x92,0x14,0x4f]
16 // CHECK: encoding: [0xc4,0xe2,0xfd,0x93,0x14,0x4f]
20 // CHECK: encoding: [0xc4,0x02,0x39,0x92,0x14,0x4f]
24 // CHECK: encoding: [0xc4,0x02,0x39,0x93,0x14,0x4f]
28 // CHECK: encoding: [0xc4,0x02,0x3d,0x92,0x14,0x4f]
32 // CHECK: encoding: [0xc4,0x02,0x3d,0x93,0x14,0x4f]
36 // CHECK: encoding: [0xc4,0xe2,0xf9,0x90,0x14,0x4f]
40 // CHECK: encoding: [0xc4,0xe2,0xf9,0x91,0x14,0x4f]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dflat_gfx10.txt7 …ch_load_dword v1, v255, off offset:-1 glc dlc ; encoding: [0xff,0x5f,0x31,0xdc,0xff,0x00,0x7d,0x01]
8 0xff 0x5f 0x31 0xdc 0xff 0x00 0x7d 0x01
10 …ch_load_dword v5, v255, off offset:-1 glc slc ; encoding: [0xff,0x4f,0x33,0xdc,0xff,0x00,0x7d,0x05]
11 0xff 0x4f 0x33 0xdc 0xff 0x00 0x7d 0x05
13 …ad_dword v0, v1, off offset:-2048 glc slc dlc ; encoding: [0x00,0x58,0x33,0xdc,0x01,0x00,0x7d,0x00]
14 0x00 0x58 0x33 0xdc 0x01 0x00 0x7d 0x00
16 …ch_load_dword v255, off, s105 offset:2047 dlc ; encoding: [0xff,0x57,0x30,0xdc,0x00,0x00,0x69,0xff]
17 0xff 0x57 0x30 0xdc 0x00 0x00 0x69 0xff
19 # CHECK: scratch_load_dword v255, v2, off ; encoding: [0x00,0x40,0x30,0xdc,0x02,0x00,0x7d,0xff]
20 0x00 0x40 0x30 0xdc 0x02 0x00 0x7d 0xff
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-2velem.s14 // CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f]
15 // CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f]
16 // CHECK: mla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x01,0xa2,0x6f]
17 // CHECK: mla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x09,0xb6,0x6f]
24 // CHECK: mla v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x00,0x62,0x2f]
25 // CHECK: mla v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x00,0x6f,0x2f]
26 // CHECK: mla v0.8h, v1.8h, v2.h[7] // encoding: [0x20,0x08,0x72,0x6f]
27 // CHECK: mla v0.8h, v1.8h, v14.h[6] // encoding: [0x20,0x08,0x6e,0x6f]
34 // CHECK: mls v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x48,0x82,0x2f]
35 // CHECK: mls v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x48,0x96,0x2f]
[all …]
/external/llvm/test/MC/AArch64/
Dneon-2velem.s14 // CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f]
15 // CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f]
16 // CHECK: mla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x01,0xa2,0x6f]
17 // CHECK: mla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x09,0xb6,0x6f]
24 // CHECK: mla v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x00,0x62,0x2f]
25 // CHECK: mla v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x00,0x6f,0x2f]
26 // CHECK: mla v0.8h, v1.8h, v2.h[7] // encoding: [0x20,0x08,0x72,0x6f]
27 // CHECK: mla v0.8h, v1.8h, v14.h[6] // encoding: [0x20,0x08,0x6e,0x6f]
34 // CHECK: mls v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x48,0x82,0x2f]
35 // CHECK: mls v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x48,0x96,0x2f]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dvstrldr_sys.txt17 # CHECK-NOSEC: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
18 # CHECK-NOMVE: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
19 # CHECK-NOVFP: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
20 # CHECK: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
21 [0x80,0xed,0x80,0x2f]
23 # CHECK-NOSEC: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
24 # CHECK-NOMVE: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
25 # CHECK-NOVFP: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
26 # CHECK: vstr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x09,0xed,0x86,0x4f]
27 [0x09,0xed,0x86,0x4f]
[all …]
Dthumb2-bit-15.txt4 [0x09,0xea,0x08,0x04]
7 [0x09,0xea,0x08,0x84]
11 [0x04,0xea,0xe8,0x01]
14 [0x04,0xea,0xe8,0x81]
18 [0x11,0xea,0x47,0x02]
21 [0x11,0xea,0x47,0x82]
25 [0x45,0xea,0x06,0x04]
28 [0x45,0xea,0x06,0x84]
31 [0x45,0xea,0x46,0x14]
34 [0x45,0xea,0x46,0x94]
[all …]
/external/llvm-project/llvm/test/MC/X86/
Dintel-syntax-x86-64-avx.s4 // CHECK: encoding: [0xc4,0xe2,0xf9,0x92,0x14,0x4f]
8 // CHECK: encoding: [0xc4,0xe2,0xf9,0x93,0x14,0x4f]
12 // CHECK: encoding: [0xc4,0xe2,0xfd,0x92,0x14,0x4f]
16 // CHECK: encoding: [0xc4,0xe2,0xfd,0x93,0x14,0x4f]
20 // CHECK: encoding: [0xc4,0x02,0x39,0x92,0x14,0x4f]
24 // CHECK: encoding: [0xc4,0x02,0x39,0x93,0x14,0x4f]
28 // CHECK: encoding: [0xc4,0x02,0x3d,0x92,0x14,0x4f]
32 // CHECK: encoding: [0xc4,0x02,0x3d,0x93,0x14,0x4f]
36 // CHECK: encoding: [0xc4,0xe2,0xf9,0x90,0x14,0x4f]
40 // CHECK: encoding: [0xc4,0xe2,0xf9,0x91,0x14,0x4f]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darmv8.6a-bf16.txt7 [0x62,0xfc,0x44,0x2e]
8 [0x62,0xfc,0x44,0x6e]
12 # NOBF16-NEXT: [0x62,0xfc,0x44,0x2e]
14 # NOBF16-NEXT: [0x62,0xfc,0x44,0x6e]
16 [0x62,0xf0,0x44,0x4f]
17 [0x62,0xf0,0x64,0x4f]
18 [0x62,0xf8,0x44,0x4f]
19 [0x62,0xf8,0x64,0x4f]
20 # CHECK: bfdot v2.4s, v3.8h, v4.2h[0]
25 # NOBF-NEXT: [0x62,0xf0,0x44,0x4f]
[all …]
Darm64-advsimd.txt3 0x00 0xb8 0x20 0x0e
4 0x00 0xb8 0x20 0x4e
5 0x00 0xb8 0x60 0x0e
6 0x00 0xb8 0x60 0x4e
7 0x00 0xb8 0xa0 0x0e
8 0x00 0xb8 0xa0 0x4e
17 0x00 0x84 0x20 0x0e
18 0x00 0x84 0x20 0x4e
19 0x00 0x84 0x60 0x0e
20 0x00 0x84 0x60 0x4e
[all …]
/external/llvm-project/llvm/test/MC/VE/
DCVTLD.s7 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8c,0x0b,0x4f]
11 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x08,0x3f,0x0b,0x4f]
15 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x09,0x40,0x0b,0x4f]
19 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0a,0x7f,0x0b,0x4f]
23 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0b,0x07,0x0b,0x4f]
27 # CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x0c,0xbf,0x0b,0x4f]
/external/icu/icu4c/source/data/mappings/
Djisx-212.ucm30 <icu:state> 0-20:2, 21-7e:1, 7f-ff:2
40 <U007E> \x22\x37 |0
41 <U00A1> \x22\x42 |0
42 <U00A4> \x22\x70 |0
43 <U00A6> \x22\x43 |0
44 <U00A9> \x22\x6D |0
45 <U00AA> \x22\x6C |0
46 <U00AE> \x22\x6E |0
47 <U00AF> \x22\x34 |0
48 <U00B8> \x22\x31 |0
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt3 0x00 0xb8 0x20 0x0e
4 0x00 0xb8 0x20 0x4e
5 0x00 0xb8 0x60 0x0e
6 0x00 0xb8 0x60 0x4e
7 0x00 0xb8 0xa0 0x0e
8 0x00 0xb8 0xa0 0x4e
17 0x00 0x84 0x20 0x0e
18 0x00 0x84 0x20 0x4e
19 0x00 0x84 0x60 0x0e
20 0x00 0x84 0x60 0x4e
[all …]

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