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/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsopp_vi.txt3 # GCN: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
4 0x00 0x00 0x80 0xbf
6 # GCN: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf]
7 0xff 0xff 0x80 0xbf
9 # GCN: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]
10 0x01 0x00 0x80 0xbf
12 # GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
13 0x00 0x00 0x81 0xbf
15 # GCN: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf]
16 0x02 0x00 0x82 0xbf
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsopp_vi.txt3 # GCN: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
4 0x00 0x00 0x80 0xbf
6 # GCN: s_nop 0xffff ; encoding: [0xff,0xff,0x80,0xbf]
7 0xff 0xff 0x80 0xbf
9 # GCN: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]
10 0x01 0x00 0x80 0xbf
12 # GCN: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
13 0x00 0x00 0x81 0xbf
15 # GCN: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf]
16 0x02 0x00 0x82 0xbf
[all …]
/external/vixl/test/aarch32/traces/
Dassembler-cond-rd-operand-rn-sxth-a32.h38 0x72, 0xd0, 0xbf, 0xb6 // sxth lt r13 r2
41 0x79, 0x20, 0xbf, 0x26 // sxth cs r2 r9
44 0x71, 0xc0, 0xbf, 0x16 // sxth ne r12 r1
47 0x71, 0x00, 0xbf, 0x36 // sxth cc r0 r1
50 0x70, 0x60, 0xbf, 0x56 // sxth pl r6 r0
53 0x76, 0x10, 0xbf, 0x56 // sxth pl r1 r6
56 0x74, 0xa0, 0xbf, 0x66 // sxth vs r10 r4
59 0x74, 0xa0, 0xbf, 0x46 // sxth mi r10 r4
62 0x73, 0xc0, 0xbf, 0xa6 // sxth ge r12 r3
65 0x70, 0x20, 0xbf, 0xb6 // sxth lt r2 r0
[all …]
Dassembler-cond-rd-rn-rev16-a32.h38 0xb1, 0xcf, 0xbf, 0x26 // rev16 cs r12 r1
41 0xbc, 0x6f, 0xbf, 0x86 // rev16 hi r6 r12
44 0xba, 0xbf, 0xbf, 0xb6 // rev16 lt r11 r10
47 0xb8, 0xaf, 0xbf, 0x66 // rev16 vs r10 r8
50 0xb8, 0x5f, 0xbf, 0x56 // rev16 pl r5 r8
53 0xbe, 0xef, 0xbf, 0x96 // rev16 ls r14 r14
56 0xb6, 0x8f, 0xbf, 0xc6 // rev16 gt r8 r6
59 0xbb, 0x7f, 0xbf, 0x76 // rev16 vc r7 r11
62 0xbc, 0x4f, 0xbf, 0x56 // rev16 pl r4 r12
65 0xbc, 0xcf, 0xbf, 0xc6 // rev16 gt r12 r12
[all …]
Dassembler-cond-rd-rn-rev-a32.h38 0x31, 0xcf, 0xbf, 0x26 // rev cs r12 r1
41 0x3c, 0x6f, 0xbf, 0x86 // rev hi r6 r12
44 0x3a, 0xbf, 0xbf, 0xb6 // rev lt r11 r10
47 0x38, 0xaf, 0xbf, 0x66 // rev vs r10 r8
50 0x38, 0x5f, 0xbf, 0x56 // rev pl r5 r8
53 0x3e, 0xef, 0xbf, 0x96 // rev ls r14 r14
56 0x36, 0x8f, 0xbf, 0xc6 // rev gt r8 r6
59 0x3b, 0x7f, 0xbf, 0x76 // rev vc r7 r11
62 0x3c, 0x4f, 0xbf, 0x56 // rev pl r4 r12
65 0x3c, 0xcf, 0xbf, 0xc6 // rev gt r12 r12
[all …]
Dassembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-rsb-t32.h38 0x08, 0xbf, 0x40, 0x42 // It eq; rsb eq r0 r0 0
41 0x08, 0xbf, 0x48, 0x42 // It eq; rsb eq r0 r1 0
44 0x08, 0xbf, 0x50, 0x42 // It eq; rsb eq r0 r2 0
47 0x08, 0xbf, 0x58, 0x42 // It eq; rsb eq r0 r3 0
50 0x08, 0xbf, 0x60, 0x42 // It eq; rsb eq r0 r4 0
53 0x08, 0xbf, 0x68, 0x42 // It eq; rsb eq r0 r5 0
56 0x08, 0xbf, 0x70, 0x42 // It eq; rsb eq r0 r6 0
59 0x08, 0xbf, 0x78, 0x42 // It eq; rsb eq r0 r7 0
62 0x08, 0xbf, 0x41, 0x42 // It eq; rsb eq r1 r0 0
65 0x08, 0xbf, 0x49, 0x42 // It eq; rsb eq r1 r1 0
[all …]
Dassembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-sub-t32.h38 0x48, 0xbf, 0x5a, 0x3b // It mi; sub mi r3 r3 90
41 0x78, 0xbf, 0x8a, 0x3e // It vc; sub vc r6 r6 138
44 0x38, 0xbf, 0x48, 0x3d // It cc; sub cc r5 r5 72
47 0xa8, 0xbf, 0xb5, 0x3e // It ge; sub ge r6 r6 181
50 0x38, 0xbf, 0x8f, 0x39 // It cc; sub cc r1 r1 143
53 0x78, 0xbf, 0x72, 0x3d // It vc; sub vc r5 r5 114
56 0xa8, 0xbf, 0xc3, 0x3c // It ge; sub ge r4 r4 195
59 0xb8, 0xbf, 0xcb, 0x38 // It lt; sub lt r0 r0 203
62 0x88, 0xbf, 0x62, 0x39 // It hi; sub hi r1 r1 98
65 0xc8, 0xbf, 0x1b, 0x1e // It gt; sub gt r3 r3 0
[all …]
Dassembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-add-t32.h38 0x48, 0xbf, 0x5a, 0x33 // It mi; add mi r3 r3 90
41 0x78, 0xbf, 0x8a, 0x36 // It vc; add vc r6 r6 138
44 0x38, 0xbf, 0x48, 0x35 // It cc; add cc r5 r5 72
47 0xa8, 0xbf, 0xb5, 0x36 // It ge; add ge r6 r6 181
50 0x38, 0xbf, 0x8f, 0x31 // It cc; add cc r1 r1 143
53 0x78, 0xbf, 0x72, 0x35 // It vc; add vc r5 r5 114
56 0xa8, 0xbf, 0xc3, 0x34 // It ge; add ge r4 r4 195
59 0xb8, 0xbf, 0xcb, 0x30 // It lt; add lt r0 r0 203
62 0x88, 0xbf, 0x62, 0x31 // It hi; add hi r1 r1 98
65 0xc8, 0xbf, 0x1b, 0x1c // It gt; add gt r3 r3 0
[all …]
Dassembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-sub-t32.h38 0x58, 0xbf, 0xc0, 0x1f // It pl; sub pl r0 r0 7
41 0x28, 0xbf, 0x50, 0x1f // It cs; sub cs r0 r2 5
44 0x98, 0xbf, 0x31, 0x1e // It ls; sub ls r1 r6 0
47 0x38, 0xbf, 0x8d, 0x1f // It cc; sub cc r5 r1 6
50 0x28, 0xbf, 0x15, 0x1e // It cs; sub cs r5 r2 0
53 0x68, 0xbf, 0xf5, 0x1f // It vs; sub vs r5 r6 7
56 0x98, 0xbf, 0x42, 0x1f // It ls; sub ls r2 r0 5
59 0x08, 0xbf, 0x63, 0x1f // It eq; sub eq r3 r4 5
62 0xb8, 0xbf, 0xec, 0x1f // It lt; sub lt r4 r5 7
65 0xb8, 0xbf, 0x7e, 0x1e // It lt; sub lt r6 r7 1
[all …]
Dassembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-add-t32.h38 0x58, 0xbf, 0xc0, 0x1d // It pl; add pl r0 r0 7
41 0x28, 0xbf, 0x50, 0x1d // It cs; add cs r0 r2 5
44 0x98, 0xbf, 0x31, 0x1c // It ls; add ls r1 r6 0
47 0x38, 0xbf, 0x8d, 0x1d // It cc; add cc r5 r1 6
50 0x28, 0xbf, 0x15, 0x1c // It cs; add cs r5 r2 0
53 0x68, 0xbf, 0xf5, 0x1d // It vs; add vs r5 r6 7
56 0x98, 0xbf, 0x42, 0x1d // It ls; add ls r2 r0 5
59 0x08, 0xbf, 0x63, 0x1d // It eq; add eq r3 r4 5
62 0xb8, 0xbf, 0xec, 0x1d // It lt; add lt r4 r5 7
65 0xb8, 0xbf, 0x7e, 0x1c // It lt; add lt r6 r7 1
[all …]
Dassembler-cond-rd-operand-rn-low-registers-in-it-block-tst-t32.h38 0x08, 0xbf, 0x00, 0x42 // It eq; tst eq r0 r0
41 0x08, 0xbf, 0x08, 0x42 // It eq; tst eq r0 r1
44 0x08, 0xbf, 0x10, 0x42 // It eq; tst eq r0 r2
47 0x08, 0xbf, 0x18, 0x42 // It eq; tst eq r0 r3
50 0x08, 0xbf, 0x20, 0x42 // It eq; tst eq r0 r4
53 0x08, 0xbf, 0x28, 0x42 // It eq; tst eq r0 r5
56 0x08, 0xbf, 0x30, 0x42 // It eq; tst eq r0 r6
59 0x08, 0xbf, 0x38, 0x42 // It eq; tst eq r0 r7
62 0x08, 0xbf, 0x01, 0x42 // It eq; tst eq r1 r0
65 0x08, 0xbf, 0x09, 0x42 // It eq; tst eq r1 r1
[all …]
Dassembler-cond-rdlow-rnlow-rmlow-in-it-block-mul-t32.h38 0x08, 0xbf, 0x40, 0x43 // It eq; mul eq r0 r0 r0
41 0x08, 0xbf, 0x48, 0x43 // It eq; mul eq r0 r1 r0
44 0x08, 0xbf, 0x50, 0x43 // It eq; mul eq r0 r2 r0
47 0x08, 0xbf, 0x58, 0x43 // It eq; mul eq r0 r3 r0
50 0x08, 0xbf, 0x60, 0x43 // It eq; mul eq r0 r4 r0
53 0x08, 0xbf, 0x68, 0x43 // It eq; mul eq r0 r5 r0
56 0x08, 0xbf, 0x70, 0x43 // It eq; mul eq r0 r6 r0
59 0x08, 0xbf, 0x78, 0x43 // It eq; mul eq r0 r7 r0
62 0x08, 0xbf, 0x41, 0x43 // It eq; mul eq r1 r0 r1
65 0x08, 0xbf, 0x49, 0x43 // It eq; mul eq r1 r1 r1
[all …]
Dassembler-cond-rd-operand-rn-low-registers-in-it-block-cmn-t32.h38 0x08, 0xbf, 0xc0, 0x42 // It eq; cmn eq r0 r0
41 0x08, 0xbf, 0xc8, 0x42 // It eq; cmn eq r0 r1
44 0x08, 0xbf, 0xd0, 0x42 // It eq; cmn eq r0 r2
47 0x08, 0xbf, 0xd8, 0x42 // It eq; cmn eq r0 r3
50 0x08, 0xbf, 0xe0, 0x42 // It eq; cmn eq r0 r4
53 0x08, 0xbf, 0xe8, 0x42 // It eq; cmn eq r0 r5
56 0x08, 0xbf, 0xf0, 0x42 // It eq; cmn eq r0 r6
59 0x08, 0xbf, 0xf8, 0x42 // It eq; cmn eq r0 r7
62 0x08, 0xbf, 0xc1, 0x42 // It eq; cmn eq r1 r0
65 0x08, 0xbf, 0xc9, 0x42 // It eq; cmn eq r1 r1
[all …]
Dassembler-cond-rdlow-operand-imm8-in-it-block-cmp-t32.h38 0x78, 0xbf, 0x6f, 0x29 // It vc; cmp vc r1 111
41 0x18, 0xbf, 0x86, 0x29 // It ne; cmp ne r1 134
44 0x18, 0xbf, 0x15, 0x2d // It ne; cmp ne r5 21
47 0x28, 0xbf, 0xdd, 0x2e // It cs; cmp cs r6 221
50 0x28, 0xbf, 0x64, 0x2b // It cs; cmp cs r3 100
53 0xd8, 0xbf, 0xd1, 0x2a // It le; cmp le r2 209
56 0x98, 0xbf, 0x08, 0x2f // It ls; cmp ls r7 8
59 0x28, 0xbf, 0xc9, 0x2f // It cs; cmp cs r7 201
62 0x18, 0xbf, 0x70, 0x2b // It ne; cmp ne r3 112
65 0xb8, 0xbf, 0x98, 0x2c // It lt; cmp lt r4 152
[all …]
Dassembler-cond-rdlow-operand-imm8-in-it-block-mov-t32.h38 0x78, 0xbf, 0x6f, 0x21 // It vc; mov vc r1 111
41 0x18, 0xbf, 0x86, 0x21 // It ne; mov ne r1 134
44 0x18, 0xbf, 0x15, 0x25 // It ne; mov ne r5 21
47 0x28, 0xbf, 0xdd, 0x26 // It cs; mov cs r6 221
50 0x28, 0xbf, 0x64, 0x23 // It cs; mov cs r3 100
53 0xd8, 0xbf, 0xd1, 0x22 // It le; mov le r2 209
56 0x98, 0xbf, 0x08, 0x27 // It ls; mov ls r7 8
59 0x28, 0xbf, 0xc9, 0x27 // It cs; mov cs r7 201
62 0x18, 0xbf, 0x70, 0x23 // It ne; mov ne r3 112
65 0xb8, 0xbf, 0x98, 0x24 // It lt; mov lt r4 152
[all …]
Dassembler-cond-rd-operand-rn-ror-amount-sxth-a32.h38 0x75, 0x20, 0xbf, 0x76 // sxth vc r2 r5 ROR 0
41 0x77, 0x50, 0xbf, 0x06 // sxth eq r5 r7 ROR 0
44 0x72, 0x34, 0xbf, 0xa6 // sxth ge r3 r2 ROR 8
47 0x73, 0xb8, 0xbf, 0x36 // sxth cc r11 r3 ROR 16
50 0x76, 0xd0, 0xbf, 0x26 // sxth cs r13 r6 ROR 0
53 0x77, 0x68, 0xbf, 0xe6 // sxth al r6 r7 ROR 16
56 0x7c, 0xc0, 0xbf, 0xd6 // sxth le r12 r12 ROR 0
59 0x75, 0x48, 0xbf, 0x46 // sxth mi r4 r5 ROR 16
62 0x72, 0x98, 0xbf, 0x56 // sxth pl r9 r2 ROR 16
65 0x7b, 0x54, 0xbf, 0x66 // sxth vs r5 r11 ROR 8
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-lsl-t32.h38 0xc8, 0xbf, 0x83, 0x40 // It gt; lsl gt r3 r3 r0
41 0xa8, 0xbf, 0x8e, 0x40 // It ge; lsl ge r6 r6 r1
44 0xc8, 0xbf, 0x8f, 0x40 // It gt; lsl gt r7 r7 r1
47 0xc8, 0xbf, 0x82, 0x40 // It gt; lsl gt r2 r2 r0
50 0x08, 0xbf, 0x95, 0x40 // It eq; lsl eq r5 r5 r2
53 0xc8, 0xbf, 0x80, 0x40 // It gt; lsl gt r0 r0 r0
56 0xb8, 0xbf, 0xa0, 0x40 // It lt; lsl lt r0 r0 r4
59 0x88, 0xbf, 0x9e, 0x40 // It hi; lsl hi r6 r6 r3
62 0xa8, 0xbf, 0xb7, 0x40 // It ge; lsl ge r7 r7 r6
65 0x08, 0xbf, 0xad, 0x40 // It eq; lsl eq r5 r5 r5
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-sbc-t32.h38 0xc8, 0xbf, 0x83, 0x41 // It gt; sbc gt r3 r3 r0
41 0xa8, 0xbf, 0x8e, 0x41 // It ge; sbc ge r6 r6 r1
44 0xc8, 0xbf, 0x8f, 0x41 // It gt; sbc gt r7 r7 r1
47 0xc8, 0xbf, 0x82, 0x41 // It gt; sbc gt r2 r2 r0
50 0x08, 0xbf, 0x95, 0x41 // It eq; sbc eq r5 r5 r2
53 0xc8, 0xbf, 0x80, 0x41 // It gt; sbc gt r0 r0 r0
56 0xb8, 0xbf, 0xa0, 0x41 // It lt; sbc lt r0 r0 r4
59 0x88, 0xbf, 0x9e, 0x41 // It hi; sbc hi r6 r6 r3
62 0xa8, 0xbf, 0xb7, 0x41 // It ge; sbc ge r7 r7 r6
65 0x08, 0xbf, 0xad, 0x41 // It eq; sbc eq r5 r5 r5
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-bic-t32.h38 0xc8, 0xbf, 0x83, 0x43 // It gt; bic gt r3 r3 r0
41 0xa8, 0xbf, 0x8e, 0x43 // It ge; bic ge r6 r6 r1
44 0xc8, 0xbf, 0x8f, 0x43 // It gt; bic gt r7 r7 r1
47 0xc8, 0xbf, 0x82, 0x43 // It gt; bic gt r2 r2 r0
50 0x08, 0xbf, 0x95, 0x43 // It eq; bic eq r5 r5 r2
53 0xc8, 0xbf, 0x80, 0x43 // It gt; bic gt r0 r0 r0
56 0xb8, 0xbf, 0xa0, 0x43 // It lt; bic lt r0 r0 r4
59 0x88, 0xbf, 0x9e, 0x43 // It hi; bic hi r6 r6 r3
62 0xa8, 0xbf, 0xb7, 0x43 // It ge; bic ge r7 r7 r6
65 0x08, 0xbf, 0xad, 0x43 // It eq; bic eq r5 r5 r5
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-in-it-block-sub-t32.h38 0x28, 0xbf, 0x4f, 0x1b // It cs; sub cs r7 r1 r5
41 0xc8, 0xbf, 0x0b, 0x1a // It gt; sub gt r3 r1 r0
44 0x98, 0xbf, 0x9c, 0x1b // It ls; sub ls r4 r3 r6
47 0x58, 0xbf, 0x1d, 0x1b // It pl; sub pl r5 r3 r4
50 0x88, 0xbf, 0x01, 0x1a // It hi; sub hi r1 r0 r0
53 0x98, 0xbf, 0xd1, 0x1a // It ls; sub ls r1 r2 r3
56 0x78, 0xbf, 0x1c, 0x1b // It vc; sub vc r4 r3 r4
59 0x18, 0xbf, 0x39, 0x1a // It ne; sub ne r1 r7 r0
62 0x98, 0xbf, 0x23, 0x1a // It ls; sub ls r3 r4 r0
65 0xc8, 0xbf, 0xe6, 0x1a // It gt; sub gt r6 r4 r3
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-in-it-block-add-t32.h38 0x28, 0xbf, 0x4f, 0x19 // It cs; add cs r7 r1 r5
41 0xc8, 0xbf, 0x0b, 0x18 // It gt; add gt r3 r1 r0
44 0x98, 0xbf, 0x9c, 0x19 // It ls; add ls r4 r3 r6
47 0x58, 0xbf, 0x1d, 0x19 // It pl; add pl r5 r3 r4
50 0x88, 0xbf, 0x01, 0x18 // It hi; add hi r1 r0 r0
53 0x98, 0xbf, 0xd1, 0x18 // It ls; add ls r1 r2 r3
56 0x78, 0xbf, 0x1c, 0x19 // It vc; add vc r4 r3 r4
59 0x18, 0xbf, 0x39, 0x18 // It ne; add ne r1 r7 r0
62 0x98, 0xbf, 0x23, 0x18 // It ls; add ls r3 r4 r0
65 0xc8, 0xbf, 0xe6, 0x18 // It gt; add gt r6 r4 r3
[all …]
Dassembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-add-t32.h38 0x58, 0xbf, 0x8d, 0x44 // It pl; add pl r13 r13 r1
41 0x48, 0xbf, 0xa3, 0x44 // It mi; add mi r11 r11 r4
44 0x68, 0xbf, 0xa4, 0x18 // It vs; add vs r4 r4 r2
47 0x98, 0xbf, 0xbf, 0x19 // It ls; add ls r7 r7 r6
50 0xd8, 0xbf, 0xa4, 0x18 // It le; add le r4 r4 r2
53 0x78, 0xbf, 0x83, 0x44 // It vc; add vc r11 r11 r0
56 0xd8, 0xbf, 0x5e, 0x44 // It le; add le r6 r6 r11
59 0x08, 0xbf, 0x4c, 0x44 // It eq; add eq r4 r4 r9
62 0x88, 0xbf, 0x94, 0x44 // It hi; add hi r12 r12 r2
65 0x88, 0xbf, 0x8b, 0x44 // It hi; add hi r11 r11 r1
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-orr-t32.h38 0xc8, 0xbf, 0x03, 0x43 // It gt; orr gt r3 r3 r0
41 0xa8, 0xbf, 0x0e, 0x43 // It ge; orr ge r6 r6 r1
44 0xc8, 0xbf, 0x0f, 0x43 // It gt; orr gt r7 r7 r1
47 0xc8, 0xbf, 0x02, 0x43 // It gt; orr gt r2 r2 r0
50 0x08, 0xbf, 0x15, 0x43 // It eq; orr eq r5 r5 r2
53 0xc8, 0xbf, 0x00, 0x43 // It gt; orr gt r0 r0 r0
56 0xb8, 0xbf, 0x20, 0x43 // It lt; orr lt r0 r0 r4
59 0x88, 0xbf, 0x1e, 0x43 // It hi; orr hi r6 r6 r3
62 0xa8, 0xbf, 0x37, 0x43 // It ge; orr ge r7 r7 r6
65 0x08, 0xbf, 0x2d, 0x43 // It eq; orr eq r5 r5 r5
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-eor-t32.h38 0xc8, 0xbf, 0x43, 0x40 // It gt; eor gt r3 r3 r0
41 0xa8, 0xbf, 0x4e, 0x40 // It ge; eor ge r6 r6 r1
44 0xc8, 0xbf, 0x4f, 0x40 // It gt; eor gt r7 r7 r1
47 0xc8, 0xbf, 0x42, 0x40 // It gt; eor gt r2 r2 r0
50 0x08, 0xbf, 0x55, 0x40 // It eq; eor eq r5 r5 r2
53 0xc8, 0xbf, 0x40, 0x40 // It gt; eor gt r0 r0 r0
56 0xb8, 0xbf, 0x60, 0x40 // It lt; eor lt r0 r0 r4
59 0x88, 0xbf, 0x5e, 0x40 // It hi; eor hi r6 r6 r3
62 0xa8, 0xbf, 0x77, 0x40 // It ge; eor ge r7 r7 r6
65 0x08, 0xbf, 0x6d, 0x40 // It eq; eor eq r5 r5 r5
[all …]
Dassembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-ror-t32.h38 0xc8, 0xbf, 0xc3, 0x41 // It gt; ror gt r3 r3 r0
41 0xa8, 0xbf, 0xce, 0x41 // It ge; ror ge r6 r6 r1
44 0xc8, 0xbf, 0xcf, 0x41 // It gt; ror gt r7 r7 r1
47 0xc8, 0xbf, 0xc2, 0x41 // It gt; ror gt r2 r2 r0
50 0x08, 0xbf, 0xd5, 0x41 // It eq; ror eq r5 r5 r2
53 0xc8, 0xbf, 0xc0, 0x41 // It gt; ror gt r0 r0 r0
56 0xb8, 0xbf, 0xe0, 0x41 // It lt; ror lt r0 r0 r4
59 0x88, 0xbf, 0xde, 0x41 // It hi; ror hi r6 r6 r3
62 0xa8, 0xbf, 0xf7, 0x41 // It ge; ror ge r7 r7 r6
65 0x08, 0xbf, 0xed, 0x41 // It eq; ror eq r5 r5 r5
[all …]

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