Home
last modified time | relevance | path

Searched +full:0 +full:xc8 (Results 1 – 25 of 1066) sorted by relevance

12345678910>>...43

/external/llvm-project/llvm/test/MC/AMDGPU/
Dvintrp.s5 // SI: v_interp_p1_f32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xc8]
6 // VI: v_interp_p1_f32_e32 v1, v0, attr0.x ; encoding: [0x00,0x00,0x04,0xd4]
9 // SI: v_interp_p1_f32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xc8]
10 // VI: v_interp_p1_f32_e32 v2, v0, attr0.y ; encoding: [0x00,0x01,0x08,0xd4]
13 // SI: v_interp_p1_f32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xc8]
14 // VI: v_interp_p1_f32_e32 v3, v0, attr0.z ; encoding: [0x00,0x02,0x0c,0xd4]
17 // SI: v_interp_p1_f32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xc8]
18 // VI: v_interp_p1_f32_e32 v4, v0, attr0.w ; encoding: [0x00,0x03,0x10,0xd4]
21 // SI: v_interp_p1_f32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xc8]
22 // VI: v_interp_p1_f32_e32 v5, v0, attr0.x ; encoding: [0x00,0x00,0x14,0xd4]
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-fpu-instructions.s12 # CHECK-EL: add.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x20]
13 # CHECK-EL: add.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x21]
14 # CHECK-EL: div.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x20]
15 # CHECK-EL: div.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x21]
16 # CHECK-EL: mul.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x20]
17 # CHECK-EL: mul.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x21]
18 # CHECK-EL: sub.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x20]
19 # CHECK-EL: sub.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x21]
20 # CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00]
21 # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
[all …]
/external/capstone/suite/MC/AArch64/
Dgicv3-regs.s.cs1 # CS_ARCH_ARM64, 0, None
2 0x08,0xcc,0x38,0xd5 = mrs x8, icc_iar1_el1
3 0x1a,0xc8,0x38,0xd5 = mrs x26, icc_iar0_el1
4 0x42,0xcc,0x38,0xd5 = mrs x2, icc_hppir1_el1
5 0x51,0xc8,0x38,0xd5 = mrs x17, icc_hppir0_el1
6 0x7d,0xcb,0x38,0xd5 = mrs x29, icc_rpr_el1
7 0x24,0xcb,0x3c,0xd5 = mrs x4, ich_vtr_el2
8 0x78,0xcb,0x3c,0xd5 = mrs x24, ich_eisr_el2
9 0xa9,0xcb,0x3c,0xd5 = mrs x9, ich_elsr_el2
10 0x78,0xcc,0x38,0xd5 = mrs x24, icc_bpr1_el1
[all …]
/external/llvm-project/llvm/test/MC/RISCV/
Drv32-user-csr-names.s14 # CHECK-ENC: encoding: [0x73,0x23,0x00,0xc8]
18 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0xc8]
23 csrrs t2, 0xC80, zero
28 # CHECK-ENC: encoding: [0x73,0x23,0x10,0xc8]
32 # CHECK-ENC: encoding: [0xf3,0x23,0x10,0xc8]
37 csrrs t2, 0xC81, zero
42 # CHECK-ENC: encoding: [0x73,0x23,0x20,0xc8]
46 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0xc8]
51 csrrs t2, 0xC82, zero
56 # CHECK-ENC: encoding: [0x73,0x23,0x30,0xc8]
[all …]
Drv64-user-csr-names.s17 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0xc8]
19 csrrs t2, 0xC80, zero
24 # CHECK-ENC: encoding: [0xf3,0x23,0x10,0xc8]
26 csrrs t2, 0xC81, zero
31 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0xc8]
33 csrrs t2, 0xC82, zero
38 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0xc8]
40 csrrs t2, 0xC83, zero
45 # CHECK-ENC: encoding: [0xf3,0x23,0x40,0xc8]
47 csrrs t2, 0xC84, zero
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dgicv3-regs.txt4 0x8 0xcc 0x38 0xd5
6 0x1a 0xc8 0x38 0xd5
8 0x42 0xcc 0x38 0xd5
10 0x51 0xc8 0x38 0xd5
12 0x7d 0xcb 0x38 0xd5
14 0x24 0xcb 0x3c 0xd5
16 0x78 0xcb 0x3c 0xd5
18 0xa9 0xcb 0x3c 0xd5
20 0x78 0xcc 0x38 0xd5
22 0x6e 0xc8 0x38 0xd5
[all …]
Darmv8a-fpmul-err.txt8 [0x20,0xec,0x22,0x0e]
9 [0x20,0xec,0xa2,0x0e]
10 [0x20,0xec,0x22,0x4e]
11 [0x20,0xec,0xa2,0x4e]
12 [0x20,0xcc,0x22,0x2e]
13 [0x20,0xcc,0xa2,0x2e]
14 [0x20,0xcc,0x22,0x6e]
15 [0x20,0xcc,0xa2,0x6e]
19 [0x20,0x08,0xb2,0x0f]
20 [0x20,0x48,0xb2,0x0f]
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dgicv3-regs.txt4 0x8 0xcc 0x38 0xd5
6 0x1a 0xc8 0x38 0xd5
8 0x42 0xcc 0x38 0xd5
10 0x51 0xc8 0x38 0xd5
12 0x7d 0xcb 0x38 0xd5
14 0x24 0xcb 0x3c 0xd5
16 0x78 0xcb 0x3c 0xd5
18 0xa9 0xcb 0x3c 0xd5
20 0x78 0xcc 0x38 0xd5
22 0x6e 0xc8 0x38 0xd5
[all …]
/external/icu/icu4c/source/data/mappings/
Dicu-internal-compound-d3.ucm24 <U2074> \xA9\xF9 |0
25 <U207F> \xA9\xFA |0
26 <U2081> \xA9\xFB |0
27 <U2082> \xA9\xFC |0
28 <U2083> \xA9\xFD |0
29 <U2084> \xA9\xFE |0
30 <U20A9> \x80\xDC |0
31 <U2109> \xA2\xB5 |0
32 <U2113> \xA7\xA4 |0
33 <U2121> \xA2\xE5 |0
[all …]
Dicu-internal-compound-d2.ucm24 <U2010> \xA1\xBE |0
25 <U2014> \xA1\xBD |0
26 <U2016> \xA1\xC2 |0
27 <U2018> \xA1\xC6 |0
28 <U2019> \xA1\xC7 |0
29 <U201C> \xA1\xC8 |0
30 <U201D> \xA1\xC9 |0
31 <U2020> \xA2\xF7 |0
32 <U2021> \xA2\xF8 |0
33 <U2025> \xA1\xC5 |0
[all …]
Dicu-internal-compound-d4.ucm24 <U4E02> \xB0\xA1 |0
25 <U4E04> \xB0\xA2 |0
26 <U4E05> \xB0\xA3 |0
27 <U4E12> \xB0\xA5 |0
28 <U4E1F> \xB0\xA6 |0
29 <U4E23> \xB0\xA7 |0
30 <U4E2E> \xB0\xAB |0
31 <U4E2F> \xB0\xAC |0
32 <U4E35> \xB0\xAE |0
33 <U4E40> \xB0\xAF |0
[all …]
Deuc-jp-2007.ucm22 <icu:state> 0-8d, 8e:2, 8f:3, 90-9f, a1-fe:1
29 <U0000> \x00 |0
30 <U0001> \x01 |0
31 <U0002> \x02 |0
32 <U0003> \x03 |0
33 <U0004> \x04 |0
34 <U0005> \x05 |0
35 <U0006> \x06 |0
36 <U0007> \x07 |0
37 <U0008> \x08 |0
[all …]
Dicu-internal-compound-d6.ucm31 <U4EF4> \xF9\xA1 |0
32 <U4F04> \xF8\xA1 |0
33 <U4F05> \xF5\xA1 |0
34 <U4F13> \xF7\xA1 |0
41 <U4F62> \xFC\xA2 |0
54 <U4FF7> \xF6\xAD |0
56 <U5020> \xF9\xAD |0
57 <U502F> \xFC\xAD |0
58 <U5031> \xFD\xAD |0
59 <U5037> \xF3\xAD |0
[all …]
Dibm-954_P101-2007.ucm23 <icu:state> 0-8d, 8e:2, 8f:3, 90-9f, a1-fe:1
30 <U0000> \x00 |0
31 <U0001> \x01 |0
32 <U0002> \x02 |0
33 <U0003> \x03 |0
34 <U0004> \x04 |0
35 <U0005> \x05 |0
36 <U0006> \x06 |0
37 <U0007> \x07 |0
38 <U0008> \x08 |0
[all …]
Dicu-internal-compound-d7.ucm26 <U4E81> \xEE\xB9 |0
34 <U4EE6> \xF2\xA1 |0
35 <U4EE7> \xF0\xA1 |0
36 <U4EF8> \xEB\xA2 |0
38 <U4EFA> \xF6\xA2 |0
39 <U4EFC> \xEE\xA2 |0
40 <U4F06> \xEC\xA2 |0
41 <U4F07> \xF4\xA2 |0
42 <U4F28> \xF2\xA2 |0
46 <U4F66> \xC8\xE4 |1
[all …]
Dibm-970_P110_P110-2006_U2.ucm23 <icu:state> 0-9f, a1-fe:1
27 <U0000> \x00 |0
28 <U0001> \x01 |0
29 <U0002> \x02 |0
30 <U0003> \x03 |0
31 <U0004> \x04 |0
32 <U0005> \x05 |0
33 <U0006> \x06 |0
34 <U0007> \x07 |0
35 <U0008> \x08 |0
[all …]
Dibm-971_P100-1995.ucm27 <U00A1> \xA2\xAE |0
28 <U00A4> \xA2\xB4 |0
29 <U00A7> \xA1\xD7 |0
30 <U00A8> \xA1\xA7 |0
31 <U00AA> \xA8\xA3 |0
32 <U00B0> \xA1\xC6 |0
33 <U00B1> \xA1\xBE |0
34 <U00B2> \xA9\xF7 |0
35 <U00B3> \xA9\xF8 |0
36 <U00B4> \xA2\xA5 |0
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-fpu-instructions.s12 # CHECK-EL: add.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x20]
13 # CHECK-EL: add.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x30,0x21]
14 # CHECK-EL: div.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x20]
15 # CHECK-EL: div.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xf0,0x21]
16 # CHECK-EL: mul.s $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x20]
17 # CHECK-EL: mul.d $f4, $f6, $f8 # encoding: [0x06,0x55,0xb0,0x21]
18 # CHECK-EL: sub.s $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x20]
19 # CHECK-EL: sub.d $f4, $f6, $f8 # encoding: [0x06,0x55,0x70,0x21]
20 # CHECK-EL: lwc1 $f2, 4($6) # encoding: [0x46,0x9c,0x04,0x00]
21 # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dgicv3-regs.s57 // CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} // encoding: [0x08,0xcc,0x38,0xd5]
58 // CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} // encoding: [0x1a,0xc8,0x38,0xd5]
59 // CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} // encoding: [0x42,0xcc,0x38,0xd5]
60 // CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} // encoding: [0x51,0xc8,0x38,0xd5]
61 // CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} // encoding: [0x7d,0xcb,0x38,0xd5]
62 // CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} // encoding: [0x24,0xcb,0x3c,0xd5]
63 // CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} // encoding: [0x78,0xcb,0x3c,0xd5]
64 // CHECK: mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5]
65 // CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} // encoding: [0x78,0xcc,0x38,0xd5]
66 // CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} // encoding: [0x6e,0xc8,0x38,0xd5]
[all …]
/external/llvm/test/MC/AArch64/
Dgicv3-regs.s59 // CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} // encoding: [0x08,0xcc,0x38,0xd5]
60 // CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} // encoding: [0x1a,0xc8,0x38,0xd5]
61 // CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} // encoding: [0x42,0xcc,0x38,0xd5]
62 // CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} // encoding: [0x51,0xc8,0x38,0xd5]
63 // CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} // encoding: [0x7d,0xcb,0x38,0xd5]
64 // CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} // encoding: [0x24,0xcb,0x3c,0xd5]
65 // CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} // encoding: [0x78,0xcb,0x3c,0xd5]
66 // CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5]
67 // CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} // encoding: [0x78,0xcc,0x38,0xd5]
68 // CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} // encoding: [0x6e,0xc8,0x38,0xd5]
[all …]
/external/vixl/test/aarch32/traces/
Dassembler-cond-rd-operand-imm16-movt-t32.h38 0xc0, 0xf2, 0x00, 0x00 // movt al r0 0x0000
41 0xc0, 0xf2, 0x01, 0x00 // movt al r0 0x0001
44 0xc0, 0xf2, 0x02, 0x00 // movt al r0 0x0002
47 0xc0, 0xf2, 0x20, 0x00 // movt al r0 0x0020
50 0xc0, 0xf2, 0x7d, 0x00 // movt al r0 0x007d
53 0xc0, 0xf2, 0x7e, 0x00 // movt al r0 0x007e
56 0xc0, 0xf2, 0x7f, 0x00 // movt al r0 0x007f
59 0xc7, 0xf6, 0xfd, 0x70 // movt al r0 0x7ffd
62 0xc7, 0xf6, 0xfe, 0x70 // movt al r0 0x7ffe
65 0xc7, 0xf6, 0xff, 0x70 // movt al r0 0x7fff
[all …]
/external/llvm-project/llvm/test/MC/VE/
DVADD.s7 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xc8]
11 # CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xc8]
15 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xc8]
19 # CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x6b,0xc8]
23 # CHECK-ENCODING: encoding: [0x00,0x16,0xff,0x0b,0x00,0x00,0x8b,0xc8]
27 # CHECK-ENCODING: encoding: [0x00,0x16,0x14,0x0c,0x00,0x00,0xcc,0xc8]
/external/capstone/suite/MC/ARM/
Dneont2-shift-encoding.s.cs2 0x40,0xff,0xa1,0x04 = vshl.u8 d16, d17, d16
3 0x50,0xff,0xa1,0x04 = vshl.u16 d16, d17, d16
4 0x60,0xff,0xa1,0x04 = vshl.u32 d16, d17, d16
5 0x70,0xff,0xa1,0x04 = vshl.u64 d16, d17, d16
6 0xcf,0xef,0x30,0x05 = vshl.i8 d16, d16, #7
7 0xdf,0xef,0x30,0x05 = vshl.i16 d16, d16, #15
8 0xff,0xef,0x30,0x05 = vshl.i32 d16, d16, #31
9 0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #63
10 0x40,0xff,0xe2,0x04 = vshl.u8 q8, q9, q8
11 0x50,0xff,0xe2,0x04 = vshl.u16 q8, q9, q8
[all …]
/external/vixl/test/aarch64/traces/
Dsim-usra-16b-2opimm-trace-aarch64.h38 0x19, 0x2a, 0x3e, 0x3f, 0x3f, 0x40, 0x40, 0x41, 0x41, 0x55, 0x66, 0x7c, 0x7e, 0x7f, 0x7f, 0x00,
39 0x25, 0x3f, 0x5d, 0x5e, 0x5e, 0x60, 0x60, 0x61, 0x61, 0x7f, 0x99, 0xba, 0xbd, 0xbe, 0xbe, 0x00,
40 0x2b, 0x49, 0x6c, 0x6d, 0x6d, 0x70, 0x70, 0x71, 0x71, 0x94, 0xb2, 0xd9, 0xdc, 0xdd, 0xdd, 0x00,
41 0x2e, 0x4e, 0x73, 0x74, 0x74, 0x78, 0x78, 0x79, 0x79, 0x9e, 0xbe, 0xe8, 0xeb, 0xec, 0xec, 0x00,
42 0x2f, 0x50, 0x76, 0x77, 0x77, 0x7c, 0x7c, 0x7d, 0x7d, 0xa3, 0xc4, 0xef, 0xf2, 0xf3, 0xf3, 0x00,
43 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7e, 0x7e, 0x7f, 0x7f, 0xa5, 0xc7, 0xf2, 0xf5, 0xf6, 0xf6, 0x00,
44 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7f, 0x7f, 0x80, 0x80, 0xa6, 0xc8, 0xf3, 0xf6, 0xf7, 0xf7, 0x00,
45 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7f, 0x7f, 0x80, 0x80, 0xa6, 0xc8, 0xf3, 0xf6, 0xf7, 0xf7, 0x00,
46 0x2a, 0x3e, 0x3f, 0x3f, 0x40, 0x40, 0x41, 0x41, 0x55, 0x66, 0x7c, 0x7e, 0x7f, 0x7f, 0x00, 0x00,
47 0x3f, 0x5d, 0x5e, 0x5e, 0x60, 0x60, 0x61, 0x61, 0x7f, 0x99, 0xba, 0xbd, 0xbe, 0xbe, 0x00, 0x00,
[all …]
Dsim-usra-8b-2opimm-trace-aarch64.h38 0x19, 0x2a, 0x3e, 0x3f, 0x3f, 0x40, 0x40, 0x41,
39 0x25, 0x3f, 0x5d, 0x5e, 0x5e, 0x60, 0x60, 0x61,
40 0x2b, 0x49, 0x6c, 0x6d, 0x6d, 0x70, 0x70, 0x71,
41 0x2e, 0x4e, 0x73, 0x74, 0x74, 0x78, 0x78, 0x79,
42 0x2f, 0x50, 0x76, 0x77, 0x77, 0x7c, 0x7c, 0x7d,
43 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7e, 0x7e, 0x7f,
44 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7f, 0x7f, 0x80,
45 0x2f, 0x51, 0x77, 0x78, 0x78, 0x7f, 0x7f, 0x80,
46 0x2a, 0x3e, 0x3f, 0x3f, 0x40, 0x40, 0x41, 0x41,
47 0x3f, 0x5d, 0x5e, 0x5e, 0x60, 0x60, 0x61, 0x61,
[all …]

12345678910>>...43