| /external/vixl/test/aarch32/traces/ |
| D | assembler-cond-rd-operand-rn-mvn-a32.h | 38 0x02, 0xd0, 0xe0, 0xb1 // mvn lt r13 r2
41 0x09, 0x20, 0xe0, 0x21 // mvn cs r2 r9
44 0x01, 0xc0, 0xe0, 0x11 // mvn ne r12 r1
47 0x01, 0x00, 0xe0, 0x31 // mvn cc r0 r1
50 0x00, 0x60, 0xe0, 0x51 // mvn pl r6 r0
53 0x06, 0x10, 0xe0, 0x51 // mvn pl r1 r6
56 0x04, 0xa0, 0xe0, 0x61 // mvn vs r10 r4
59 0x04, 0xa0, 0xe0, 0x41 // mvn mi r10 r4
62 0x03, 0xc0, 0xe0, 0xa1 // mvn ge r12 r3
65 0x00, 0x20, 0xe0, 0xb1 // mvn lt r2 r0
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to31-mvn-a32.h | 38 0x65, 0x55, 0xe0, 0x71 // mvn vc r5 r5 ROR 10
41 0xe4, 0x38, 0xe0, 0x11 // mvn ne r3 r4 ROR 17
44 0x6a, 0x98, 0xe0, 0x21 // mvn cs r9 r10 ROR 16
47 0xe2, 0x0e, 0xe0, 0xb1 // mvn lt r0 r2 ROR 29
50 0xe2, 0xbb, 0xe0, 0xe1 // mvn al r11 r2 ROR 23
53 0x81, 0x7e, 0xe0, 0x81 // mvn hi r7 r1 LSL 29
56 0xe3, 0x5a, 0xe0, 0x01 // mvn eq r5 r3 ROR 21
59 0xea, 0x26, 0xe0, 0x51 // mvn pl r2 r10 ROR 13
62 0x81, 0x1b, 0xe0, 0xb1 // mvn lt r1 r1 LSL 23
65 0xea, 0xbf, 0xe0, 0x41 // mvn mi r11 r10 ROR 31
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-rs-mvn-a32.h | 38 0x1b, 0xdc, 0xe0, 0xc1 // mvn gt r13 r11 LSL r12
41 0x34, 0xc6, 0xe0, 0xc1 // mvn gt r12 r4 LSR r6
44 0x7d, 0xb2, 0xe0, 0xa1 // mvn ge r11 r13 ROR r2
47 0x58, 0x9a, 0xe0, 0x81 // mvn hi r9 r8 ASR r10
50 0x1a, 0x94, 0xe0, 0xe1 // mvn al r9 r10 LSL r4
53 0x3b, 0x44, 0xe0, 0xc1 // mvn gt r4 r11 LSR r4
56 0x56, 0x4b, 0xe0, 0x71 // mvn vc r4 r6 ASR r11
59 0x3e, 0x99, 0xe0, 0x41 // mvn mi r9 r14 LSR r9
62 0x3a, 0x58, 0xe0, 0x11 // mvn ne r5 r10 LSR r8
65 0x70, 0x3b, 0xe0, 0x01 // mvn eq r3 r0 ROR r11
[all …]
|
| D | assembler-cond-rd-operand-const-cannot-use-pc-mvn-a32.h | 38 0xff, 0x09, 0xe0, 0x93 // mvn ls r0 0x003fc000
41 0xff, 0xd4, 0xe0, 0x03 // mvn eq r13 0xff000000
44 0xab, 0x0b, 0xe0, 0xe3 // mvn al r0 0x0002ac00
47 0xab, 0xd9, 0xe0, 0xc3 // mvn gt r13 0x002ac000
50 0xab, 0x3f, 0xe0, 0x43 // mvn mi r3 0x000002ac
53 0xff, 0x00, 0xe0, 0x93 // mvn ls r0 0x000000ff
56 0xab, 0x7c, 0xe0, 0x93 // mvn ls r7 0x0000ab00
59 0xff, 0xb6, 0xe0, 0x33 // mvn cc r11 0x0ff00000
62 0xff, 0x51, 0xe0, 0x63 // mvn vs r5 0xc000003f
65 0xab, 0x38, 0xe0, 0xc3 // mvn gt r3 0x00ab0000
[all …]
|
| D | assembler-cond-rd-operand-rn-shift-amount-1to32-mvn-a32.h | 38 0xad, 0xab, 0xe0, 0x01 // mvn eq r10 r13 LSR 23
41 0xad, 0xc6, 0xe0, 0x01 // mvn eq r12 r13 LSR 13
44 0x25, 0xd6, 0xe0, 0x51 // mvn pl r13 r5 LSR 12
47 0xcb, 0x86, 0xe0, 0x71 // mvn vc r8 r11 ASR 13
50 0xcc, 0x90, 0xe0, 0xe1 // mvn al r9 r12 ASR 1
53 0xc3, 0xaf, 0xe0, 0x61 // mvn vs r10 r3 ASR 31
56 0x4b, 0x27, 0xe0, 0x51 // mvn pl r2 r11 ASR 14
59 0xaa, 0xbd, 0xe0, 0xe1 // mvn al r11 r10 LSR 27
62 0xa8, 0xa9, 0xe0, 0xd1 // mvn le r10 r8 LSR 19
65 0xc2, 0x64, 0xe0, 0x71 // mvn vc r6 r2 ASR 9
[all …]
|
| D | assembler-cond-rd-memop-immediate-512-strh-a32.h | 38 0xb0, 0xd0, 0xc0, 0x51 // strh pl r13 r0 plus 0 Offset
41 0xb0, 0x50, 0xc3, 0xa1 // strh ge r5 r3 plus 0 Offset
44 0xb0, 0x00, 0xc4, 0x31 // strh cc r0 r4 plus 0 Offset
47 0xb0, 0x00, 0xc0, 0xa1 // strh ge r0 r0 plus 0 Offset
50 0xb0, 0xc0, 0xc3, 0x01 // strh eq r12 r3 plus 0 Offset
53 0xb0, 0x40, 0xcd, 0xe1 // strh al r4 r13 plus 0 Offset
56 0xb0, 0x80, 0xc2, 0x41 // strh mi r8 r2 plus 0 Offset
59 0xb0, 0x60, 0xc9, 0x41 // strh mi r6 r9 plus 0 Offset
62 0xb0, 0xd0, 0xcb, 0xc1 // strh gt r13 r11 plus 0 Offset
65 0xb0, 0x00, 0xc7, 0x21 // strh cs r0 r7 plus 0 Offset
[all …]
|
| D | assembler-cond-rd-memop-immediate-512-ldrsh-a32.h | 38 0xf0, 0xd0, 0xd0, 0x51 // ldrsh pl r13 r0 plus 0 Offset
41 0xf0, 0x50, 0xd3, 0xa1 // ldrsh ge r5 r3 plus 0 Offset
44 0xf0, 0x00, 0xd4, 0x31 // ldrsh cc r0 r4 plus 0 Offset
47 0xf0, 0x00, 0xd0, 0xa1 // ldrsh ge r0 r0 plus 0 Offset
50 0xf0, 0xc0, 0xd3, 0x01 // ldrsh eq r12 r3 plus 0 Offset
53 0xf0, 0x40, 0xdd, 0xe1 // ldrsh al r4 r13 plus 0 Offset
56 0xf0, 0x80, 0xd2, 0x41 // ldrsh mi r8 r2 plus 0 Offset
59 0xf0, 0x60, 0xd9, 0x41 // ldrsh mi r6 r9 plus 0 Offset
62 0xf0, 0xd0, 0xdb, 0xc1 // ldrsh gt r13 r11 plus 0 Offset
65 0xf0, 0x00, 0xd7, 0x21 // ldrsh cs r0 r7 plus 0 Offset
[all …]
|
| D | assembler-cond-rd-memop-immediate-512-ldrh-a32.h | 38 0xb0, 0xd0, 0xd0, 0x51 // ldrh pl r13 r0 plus 0 Offset
41 0xb0, 0x50, 0xd3, 0xa1 // ldrh ge r5 r3 plus 0 Offset
44 0xb0, 0x00, 0xd4, 0x31 // ldrh cc r0 r4 plus 0 Offset
47 0xb0, 0x00, 0xd0, 0xa1 // ldrh ge r0 r0 plus 0 Offset
50 0xb0, 0xc0, 0xd3, 0x01 // ldrh eq r12 r3 plus 0 Offset
53 0xb0, 0x40, 0xdd, 0xe1 // ldrh al r4 r13 plus 0 Offset
56 0xb0, 0x80, 0xd2, 0x41 // ldrh mi r8 r2 plus 0 Offset
59 0xb0, 0x60, 0xd9, 0x41 // ldrh mi r6 r9 plus 0 Offset
62 0xb0, 0xd0, 0xdb, 0xc1 // ldrh gt r13 r11 plus 0 Offset
65 0xb0, 0x00, 0xd7, 0x21 // ldrh cs r0 r7 plus 0 Offset
[all …]
|
| D | assembler-cond-rd-memop-immediate-512-ldrsb-a32.h | 38 0xd0, 0xd0, 0xd0, 0x51 // ldrsb pl r13 r0 plus 0 Offset
41 0xd0, 0x50, 0xd3, 0xa1 // ldrsb ge r5 r3 plus 0 Offset
44 0xd0, 0x00, 0xd4, 0x31 // ldrsb cc r0 r4 plus 0 Offset
47 0xd0, 0x00, 0xd0, 0xa1 // ldrsb ge r0 r0 plus 0 Offset
50 0xd0, 0xc0, 0xd3, 0x01 // ldrsb eq r12 r3 plus 0 Offset
53 0xd0, 0x40, 0xdd, 0xe1 // ldrsb al r4 r13 plus 0 Offset
56 0xd0, 0x80, 0xd2, 0x41 // ldrsb mi r8 r2 plus 0 Offset
59 0xd0, 0x60, 0xd9, 0x41 // ldrsb mi r6 r9 plus 0 Offset
62 0xd0, 0xd0, 0xdb, 0xc1 // ldrsb gt r13 r11 plus 0 Offset
65 0xd0, 0x00, 0xd7, 0x21 // ldrsb cs r0 r7 plus 0 Offset
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
| D | mubuf_vi.txt | 3 # VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
4 0x00 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
6 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
7 0x04 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
9 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
10 0x04 0x40 0x50 0xe0 0x00 0x01 0x01 0x01
12 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x01,0x01,0x01]
13 0x04 0x00 0x52 0xe0 0x00 0x01 0x01 0x01
15 …r_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x81,0x01]
16 0x04 0x00 0x50 0xe0 0x00 0x01 0x81 0x01
[all …]
|
| D | mubuf_gfx9.txt | 3 …hi_x v5, off, s[8:11], s3 offset:4095 glc slc ; encoding: [0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03]
4 0xff,0x4f,0x9a,0xe0,0x00,0x05,0x02,0x03
6 …16_hi_x v5, v0, s[8:11], s3 idxen offset:4095 ; encoding: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
7 0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03
9 …16_hi_x v5, v0, s[8:11], s3 offen offset:4095 ; encoding: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
10 0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03
12 …6_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
13 0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04
15 …6_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
16 0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04
[all …]
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | mubuf_vi.txt | 3 # VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
4 0x00 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
6 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
7 0x04 0x00 0x50 0xe0 0x00 0x01 0x01 0x01
9 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
10 0x04 0x40 0x50 0xe0 0x00 0x01 0x01 0x01
12 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x01,0x01,0x01]
13 0x04 0x00 0x52 0xe0 0x00 0x01 0x01 0x01
15 …r_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x81,0x01]
16 0x04 0x00 0x50 0xe0 0x00 0x01 0x81 0x01
[all …]
|
| /external/freetype/src/autofit/ |
| D | afblue.c | 30 '\0',
32 '\0',
34 '\0',
36 '\0',
38 '\0',
40 '\0',
42 '\0',
44 '\0',
46 '\0',
48 '\0',
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2-v8.1m.txt | 5 0x40 0xf6 0x17 0xe8
6 0xb8 0xbf
9 0xc0 0xf4 0x15 0xe0
12 0x84 0xf3 0x13 0xe0
15 0xe2 0xf2 0x01 0xe0
18 0xf3 0xf1 0x01 0xe0
21 0x87 0xf0 0x61 0xcb
24 0x48 0xf0 0x13 0xc0
27 0x4a 0xf0 0x01 0xe0
30 0x2f 0xf0 0x0d 0xc0
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/PowerPC/ |
| D | vsx.txt | 4 0x7c 0xe5 0xfc 0x98
7 0x7c 0xe5 0xf8 0x98
10 0x7c 0xe5 0xf8 0x18
13 0x7c 0xe5 0xfc 0x18
16 0x7c 0xe5 0xfe 0x98
19 0x7c 0xe5 0xfa 0x98
22 0x7c 0xe5 0xfe 0x18
25 0x7d 0x05 0xfd 0x98
28 0x7d 0x05 0xf9 0x18
31 0x7d 0x05 0xfd 0x18
[all …]
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | vsx.txt | 4 0x7c 0xe5 0xfc 0x98
7 0x7c 0xe5 0xf8 0x98
10 0x7c 0xe5 0xf8 0x18
13 0x7c 0xe5 0xfc 0x18
16 0x7c 0xe5 0xfe 0x98
19 0x7c 0xe5 0xfa 0x98
22 0x7c 0xe5 0xfe 0x18
25 0x7d 0x05 0xfd 0x98
28 0x7d 0x05 0xf9 0x18
31 0x7d 0x05 0xfd 0x18
[all …]
|
| /external/llvm/test/MC/AMDGPU/ |
| D | mubuf.s | 18 // SICI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
19 // VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
22 // SICI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0…
23 // VI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0…
26 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
27 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
30 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01]
31 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
34 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x41,0x01]
35 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x01,0x01,0x01]
[all …]
|
| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | mubuf.s | 18 // SICI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
19 // VI: buffer_load_dword v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
22 // SICI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x30,0xe0,0x00,0x01,0x1d,0…
23 // VI: buffer_load_dword v1, off, ttmp[4:7], s1 ; encoding: [0x00,0x00,0x50,0xe0,0x00,0x01,0x1d,0…
26 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x01,0x01]
27 …uffer_load_dword v1, off, s[4:7], s1 offset:4 ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x01,0x01]
30 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x30,0xe0,0x00,0x01,0x01,0x01]
31 …r_load_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x50,0xe0,0x00,0x01,0x01,0x01]
34 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x30,0xe0,0x00,0x01,0x41,0x01]
35 …r_load_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x52,0xe0,0x00,0x01,0x01,0x01]
[all …]
|
| /external/llvm-project/llvm/test/MC/AVR/ |
| D | modifiers.s | 4 ; FIXME: most of these tests use values (i.e. 0x0815) that are out of bounds.
8 ldi r24, lo8(0x42)
9 ldi r24, lo8(0x2342)
11 ldi r24, lo8(0x23)
12 ldi r24, hi8(0x2342)
14 ; CHECK: ldi r24, lo8(66) ; encoding: [0x82,0xe4]
15 ; CHECK: ldi r24, lo8(9026) ; encoding: [0x82,0xe4]
17 ; CHECK: ldi r24, lo8(35) ; encoding: [0x83,0xe2]
18 ; CHECK: ldi r24, hi8(9026) ; encoding: [0x83,0xe2]
26 ; CHECK: ldi r24, lo8(bar) ; encoding: [0x80'A',0xe0]
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 2 0x0f,0x10,0xa2,0xe2 = adc r1, r2, #15
3 0xf0,0x10,0xa2,0xe2 = adc r1, r2, #240
4 0x0f,0x1c,0xa2,0xe2 = adc r1, r2, #3840
5 0x0f,0x1a,0xa2,0xe2 = adc r1, r2, #61440
6 0x0f,0x18,0xa2,0xe2 = adc r1, r2, #983040
7 0x0f,0x16,0xa2,0xe2 = adc r1, r2, #15728640
8 0x0f,0x14,0xa2,0xe2 = adc r1, r2, #251658240
9 0x0f,0x12,0xa2,0xe2 = adc r1, r2, #4026531840
10 0xff,0x12,0xa2,0xe2 = adc r1, r2, #4026531855
11 0x0f,0x1c,0xb2,0xe2 = adcs r1, r2, #3840
[all …]
|
| D | arm-memory-instructions.s.cs | 2 0x00,0x50,0x97,0xe5 = ldr r5, [r7]
3 0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63]
4 0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #4095]!
5 0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #30
6 0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30
7 0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0
8 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1]
9 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3]
10 0x09,0x10,0xb5,0xe7 = ldr r1, [r5, r9]!
11 0x08,0x60,0x37,0xe7 = ldr r6, [r7, -r8]!
[all …]
|
| /external/vixl/test/aarch64/traces/ |
| D | sim-shl-16b-2opimm-trace-aarch64.h | 38 0x33, 0x55, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0xaa, 0xcc, 0xf8, 0xfd, 0xfe, 0xff, 0x00,
39 0x66, 0xaa, 0xfa, 0xfc, 0xfe, 0x00, 0x02, 0x04, 0x06, 0x54, 0x98, 0xf0, 0xfa, 0xfc, 0xfe, 0x00,
40 0xcc, 0x54, 0xf4, 0xf8, 0xfc, 0x00, 0x04, 0x08, 0x0c, 0xa8, 0x30, 0xe0, 0xf4, 0xf8, 0xfc, 0x00,
41 0x98, 0xa8, 0xe8, 0xf0, 0xf8, 0x00, 0x08, 0x10, 0x18, 0x50, 0x60, 0xc0, 0xe8, 0xf0, 0xf8, 0x00,
42 0x30, 0x50, 0xd0, 0xe0, 0xf0, 0x00, 0x10, 0x20, 0x30, 0xa0, 0xc0, 0x80, 0xd0, 0xe0, 0xf0, 0x00,
43 0x60, 0xa0, 0xa0, 0xc0, 0xe0, 0x00, 0x20, 0x40, 0x60, 0x40, 0x80, 0x00, 0xa0, 0xc0, 0xe0, 0x00,
44 0xc0, 0x40, 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0, 0x80, 0x00, 0x00, 0x40, 0x80, 0xc0, 0x00,
45 0x80, 0x80, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00,
46 0x55, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0xaa, 0xcc, 0xf8, 0xfd, 0xfe, 0xff, 0x00, 0x01,
47 0xaa, 0xfa, 0xfc, 0xfe, 0x00, 0x02, 0x04, 0x06, 0x54, 0x98, 0xf0, 0xfa, 0xfc, 0xfe, 0x00, 0x02,
[all …]
|
| /external/llvm-project/llvm/test/MC/PowerPC/ |
| D | vsx.s | 4 # CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56]
5 # CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
8 # CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
9 # CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
11 # CHECK-BE: lxsiwax 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x99]
12 # CHECK-LE: lxsiwax 39, 5, 31 # encoding: [0x99,0xf8,0xe5,0x7c]
14 # CHECK-BE: lxsiwzx 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x19]
15 # CHECK-LE: lxsiwzx 39, 5, 31 # encoding: [0x19,0xf8,0xe5,0x7c]
17 # CHECK-BE: lxsspx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x19]
18 # CHECK-LE: lxsspx 39, 5, 31 # encoding: [0x19,0xfc,0xe5,0x7c]
[all …]
|
| /external/llvm/test/MC/PowerPC/ |
| D | vsx.s | 4 # CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56]
5 # CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
8 # CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
9 # CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
11 # CHECK-BE: lxsiwax 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x99]
12 # CHECK-LE: lxsiwax 39, 5, 31 # encoding: [0x99,0xf8,0xe5,0x7c]
14 # CHECK-BE: lxsiwzx 39, 5, 31 # encoding: [0x7c,0xe5,0xf8,0x19]
15 # CHECK-LE: lxsiwzx 39, 5, 31 # encoding: [0x19,0xf8,0xe5,0x7c]
17 # CHECK-BE: lxsspx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x19]
18 # CHECK-LE: lxsspx 39, 5, 31 # encoding: [0x19,0xfc,0xe5,0x7c]
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.6a-ecv.txt | 4 [0x81,0xe0,0x1c,0xd5]
5 [0xab,0xe0,0x1c,0xd5]
6 [0xd6,0xe0,0x1c,0xd5]
7 [0xe3,0xe0,0x1c,0xd5]
8 [0xad,0xe0,0x1b,0xd5]
9 [0xd7,0xe0,0x1b,0xd5]
23 [0x80,0xe0,0x3c,0xd5]
24 [0xa5,0xe0,0x3c,0xd5]
25 [0xca,0xe0,0x3c,0xd5]
26 [0xef,0xe0,0x3c,0xd5]
[all …]
|