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/external/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z13.txt5 #CHECK: lcbb %r0, 0, 0
6 0xe7 0x00 0x00 0x00 0x00 0x27
9 0xe7 0x17 0x89 0xab 0xc0 0x27
12 0xe7 0xff 0xff 0xff 0xf0 0x27
15 0xe7 0x00 0x00 0x00 0x00 0xf3
18 0xe7 0x23 0x40 0x00 0x0a 0xf3
21 0xe7 0xff 0xf0 0x00 0x0e 0xf3
24 0xe7 0x00 0x00 0x00 0x00 0xf1
27 0xe7 0x23 0x40 0x00 0x0a 0xf1
30 0xe7 0xff 0xf0 0x00 0x0e 0xf1
[all …]
Dinsns-z13-bad.txt5 # This would be "vlef %v0, 0, 4", but element 4 is invalid.
8 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x40 0x03
9 0xe7 0x00 0x00 0x00 0x40 0x03
14 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03
15 0xe7 0x00 0x00 0x00 0xf0 0x03
17 # This would be "vleg %v0, 0, 2", but element 2 is invalid.
20 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x20 0x02
21 0xe7 0x00 0x00 0x00 0x20 0x02
26 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02
27 0xe7 0x00 0x00 0x00 0xf0 0x02
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z13.txt5 # CHECK: cdpt %f0, 0(1), 0
6 0xed 0x00 0x00 0x00 0x00 0xae
8 # CHECK: cdpt %f15, 0(1), 0
9 0xed 0x00 0x00 0x00 0xf0 0xae
11 # CHECK: cdpt %f0, 0(1), 15
12 0xed 0x00 0x00 0x00 0x0f 0xae
14 # CHECK: cdpt %f0, 0(1,%r1), 0
15 0xed 0x00 0x10 0x00 0x00 0xae
17 # CHECK: cdpt %f0, 0(1,%r15), 0
18 0xed 0x00 0xf0 0x00 0x00 0xae
[all …]
Dinsns-z14.txt6 0xe3 0x00 0x00 0x00 0x80 0x38
9 0xe3 0x00 0x0f 0xff 0xff 0x38
11 # CHECK: agh %r0, 0
12 0xe3 0x00 0x00 0x00 0x00 0x38
15 0xe3 0x00 0x00 0x01 0x00 0x38
18 0xe3 0x00 0x0f 0xff 0x7f 0x38
20 # CHECK: agh %r0, 0(%r1)
21 0xe3 0x00 0x10 0x00 0x00 0x38
23 # CHECK: agh %r0, 0(%r15)
24 0xe3 0x00 0xf0 0x00 0x00 0x38
[all …]
Dinsns-z15.txt6 0xb9 0x39 0x20 0x22
9 0xb9 0x39 0xf0 0x28
12 0xb9 0x39 0x20 0xe8
15 0xb9 0x39 0xa0 0x68
18 0xb9 0x3a 0x00 0x02
21 0xb9 0x3a 0x00 0x0e
24 0xb9 0x3a 0x00 0xf2
27 0xb9 0x3a 0x00 0x7a
29 # CHECK: mvcrl 0, 0
30 0xe5 0x0a 0x00 0x00 0x00 0x00
[all …]
Dinsns-z13-bad.txt5 # This would be "vlef %v0, 0, 4", but element 4 is invalid.
8 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x40 0x03
9 0xe7 0x00 0x00 0x00 0x40 0x03
14 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x03
15 0xe7 0x00 0x00 0x00 0xf0 0x03
17 # This would be "vleg %v0, 0, 2", but element 2 is invalid.
20 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0x20 0x02
21 0xe7 0x00 0x00 0x00 0x20 0x02
26 #CHECK-NEXT: 0xe7 0x00 0x00 0x00 0xf0 0x02
27 0xe7 0x00 0x00 0x00 0xf0 0x02
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-good-z13.s5 #CHECK: lcbb %r0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x27]
6 #CHECK: lcbb %r0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x27]
7 #CHECK: lcbb %r0, 4095, 0 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x27]
8 #CHECK: lcbb %r0, 0(%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x27]
9 #CHECK: lcbb %r0, 0(%r15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x27]
10 #CHECK: lcbb %r15, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x27]
11 #CHECK: lcbb %r2, 1383(%r3,%r4), 8 # encoding: [0xe7,0x23,0x45,0x67,0x80,0x27]
13 lcbb %r0, 0, 0
14 lcbb %r0, 0, 15
15 lcbb %r0, 4095, 0
[all …]
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-good-z13.s7 #CHECK: cdpt %f0, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0xae]
8 #CHECK: cdpt %f15, 0(1), 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0xae]
9 #CHECK: cdpt %f0, 0(1), 15 # encoding: [0xed,0x00,0x00,0x00,0x0f,0xae]
10 #CHECK: cdpt %f0, 0(1,%r1), 0 # encoding: [0xed,0x00,0x10,0x00,0x00,0xae]
11 #CHECK: cdpt %f0, 0(1,%r15), 0 # encoding: [0xed,0x00,0xf0,0x00,0x00,0xae]
12 #CHECK: cdpt %f0, 4095(1,%r1), 0 # encoding: [0xed,0x00,0x1f,0xff,0x00,0xae]
13 #CHECK: cdpt %f0, 4095(1,%r15), 0 # encoding: [0xed,0x00,0xff,0xff,0x00,0xae]
14 #CHECK: cdpt %f0, 0(256,%r1), 0 # encoding: [0xed,0xff,0x10,0x00,0x00,0xae]
15 #CHECK: cdpt %f0, 0(256,%r15), 0 # encoding: [0xed,0xff,0xf0,0x00,0x00,0xae]
17 cdpt %f0, 0(1), 0
[all …]
Dinsn-good-z14.s7 #CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
8 #CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
9 #CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
10 #CHECK: agh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38]
11 #CHECK: agh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38]
12 #CHECK: agh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38]
13 #CHECK: agh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38]
14 #CHECK: agh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38]
15 #CHECK: agh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38]
16 #CHECK: agh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38]
[all …]
Dinsn-good-z15.s7 #CHECK: dfltcc %r2, %r2, %r2 # encoding: [0xb9,0x39,0x20,0x22]
8 #CHECK: dfltcc %r2, %r8, %r15 # encoding: [0xb9,0x39,0xf0,0x28]
9 #CHECK: dfltcc %r14, %r8, %r2 # encoding: [0xb9,0x39,0x20,0xe8]
10 #CHECK: dfltcc %r6, %r8, %r10 # encoding: [0xb9,0x39,0xa0,0x68]
17 #CHECK: kdsa %r0, %r2 # encoding: [0xb9,0x3a,0x00,0x02]
18 #CHECK: kdsa %r0, %r14 # encoding: [0xb9,0x3a,0x00,0x0e]
19 #CHECK: kdsa %r15, %r2 # encoding: [0xb9,0x3a,0x00,0xf2]
20 #CHECK: kdsa %r7, %r10 # encoding: [0xb9,0x3a,0x00,0x7a]
27 #CHECK: vllebrzg %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
28 #CHECK: vllebrzg %v0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
[all …]
/external/vixl/test/aarch32/traces/
Dassembler-cond-rd-memop-rs-strb-a32.h38 0x06, 0x80, 0xcb, 0x57 // strb pl r8 r11 plus r6 Offset
41 0x05, 0x40, 0xc8, 0xd7 // strb le r4 r8 plus r5 Offset
44 0x0e, 0x20, 0xc6, 0x67 // strb vs r2 r6 plus r14 Offset
47 0x08, 0x10, 0xc7, 0x97 // strb ls r1 r7 plus r8 Offset
50 0x0e, 0xe0, 0xc6, 0xa7 // strb ge r14 r6 plus r14 Offset
53 0x07, 0x70, 0xc0, 0x27 // strb cs r7 r0 plus r7 Offset
56 0x09, 0xb0, 0xc0, 0xa7 // strb ge r11 r0 plus r9 Offset
59 0x04, 0x70, 0xca, 0x07 // strb eq r7 r10 plus r4 Offset
62 0x03, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 Offset
65 0x06, 0xb0, 0xca, 0x37 // strb cc r11 r10 plus r6 Offset
[all …]
Dassembler-cond-rd-memop-rs-ldr-a32.h38 0x06, 0x80, 0x9b, 0x57 // ldr pl r8 r11 plus r6 Offset
41 0x05, 0x40, 0x98, 0xd7 // ldr le r4 r8 plus r5 Offset
44 0x0e, 0x20, 0x96, 0x67 // ldr vs r2 r6 plus r14 Offset
47 0x08, 0x10, 0x97, 0x97 // ldr ls r1 r7 plus r8 Offset
50 0x0e, 0xe0, 0x96, 0xa7 // ldr ge r14 r6 plus r14 Offset
53 0x07, 0x70, 0x90, 0x27 // ldr cs r7 r0 plus r7 Offset
56 0x09, 0xb0, 0x90, 0xa7 // ldr ge r11 r0 plus r9 Offset
59 0x04, 0x70, 0x9a, 0x07 // ldr eq r7 r10 plus r4 Offset
62 0x03, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 Offset
65 0x06, 0xb0, 0x9a, 0x37 // ldr cc r11 r10 plus r6 Offset
[all …]
Dassembler-cond-rd-memop-rs-str-a32.h38 0x06, 0x80, 0x8b, 0x57 // str pl r8 r11 plus r6 Offset
41 0x05, 0x40, 0x88, 0xd7 // str le r4 r8 plus r5 Offset
44 0x0e, 0x20, 0x86, 0x67 // str vs r2 r6 plus r14 Offset
47 0x08, 0x10, 0x87, 0x97 // str ls r1 r7 plus r8 Offset
50 0x0e, 0xe0, 0x86, 0xa7 // str ge r14 r6 plus r14 Offset
53 0x07, 0x70, 0x80, 0x27 // str cs r7 r0 plus r7 Offset
56 0x09, 0xb0, 0x80, 0xa7 // str ge r11 r0 plus r9 Offset
59 0x04, 0x70, 0x8a, 0x07 // str eq r7 r10 plus r4 Offset
62 0x03, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 Offset
65 0x06, 0xb0, 0x8a, 0x37 // str cc r11 r10 plus r6 Offset
[all …]
Dassembler-cond-rd-memop-rs-ldrb-a32.h38 0x06, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 Offset
41 0x05, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 Offset
44 0x0e, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 Offset
47 0x08, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 Offset
50 0x0e, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 Offset
53 0x07, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 Offset
56 0x09, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 Offset
59 0x04, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 Offset
62 0x03, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 Offset
65 0x06, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to31-strb-a32.h38 0x86, 0x80, 0xcb, 0x57 // strb pl r8 r11 plus r6 LSL 1 Offset
41 0x85, 0x40, 0xc8, 0xd7 // strb le r4 r8 plus r5 LSL 1 Offset
44 0x8e, 0x20, 0xc6, 0x67 // strb vs r2 r6 plus r14 LSL 1 Offset
47 0x88, 0x10, 0xc7, 0x97 // strb ls r1 r7 plus r8 LSL 1 Offset
50 0x8e, 0xe0, 0xc6, 0xa7 // strb ge r14 r6 plus r14 LSL 1 Offset
53 0x87, 0x70, 0xc0, 0x27 // strb cs r7 r0 plus r7 LSL 1 Offset
56 0x89, 0xb0, 0xc0, 0xa7 // strb ge r11 r0 plus r9 LSL 1 Offset
59 0x84, 0x70, 0xca, 0x07 // strb eq r7 r10 plus r4 LSL 1 Offset
62 0x83, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 LSL 1 Offset
65 0x86, 0xb0, 0xca, 0x37 // strb cc r11 r10 plus r6 LSL 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to32-strb-a32.h38 0xa6, 0x80, 0xcb, 0x57 // strb pl r8 r11 plus r6 LSR 1 Offset
41 0xa5, 0x40, 0xc8, 0xd7 // strb le r4 r8 plus r5 LSR 1 Offset
44 0xae, 0x20, 0xc6, 0x67 // strb vs r2 r6 plus r14 LSR 1 Offset
47 0xa8, 0x10, 0xc7, 0x97 // strb ls r1 r7 plus r8 LSR 1 Offset
50 0xae, 0xe0, 0xc6, 0xa7 // strb ge r14 r6 plus r14 LSR 1 Offset
53 0xa7, 0x70, 0xc0, 0x27 // strb cs r7 r0 plus r7 LSR 1 Offset
56 0xa9, 0xb0, 0xc0, 0xa7 // strb ge r11 r0 plus r9 LSR 1 Offset
59 0xa4, 0x70, 0xca, 0x07 // strb eq r7 r10 plus r4 LSR 1 Offset
62 0xa3, 0x90, 0xc2, 0xe7 // strb al r9 r2 plus r3 LSR 1 Offset
65 0xa6, 0xb0, 0xca, 0x37 // strb cc r11 r10 plus r6 LSR 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to31-str-a32.h38 0x86, 0x80, 0x8b, 0x57 // str pl r8 r11 plus r6 LSL 1 Offset
41 0x85, 0x40, 0x88, 0xd7 // str le r4 r8 plus r5 LSL 1 Offset
44 0x8e, 0x20, 0x86, 0x67 // str vs r2 r6 plus r14 LSL 1 Offset
47 0x88, 0x10, 0x87, 0x97 // str ls r1 r7 plus r8 LSL 1 Offset
50 0x8e, 0xe0, 0x86, 0xa7 // str ge r14 r6 plus r14 LSL 1 Offset
53 0x87, 0x70, 0x80, 0x27 // str cs r7 r0 plus r7 LSL 1 Offset
56 0x89, 0xb0, 0x80, 0xa7 // str ge r11 r0 plus r9 LSL 1 Offset
59 0x84, 0x70, 0x8a, 0x07 // str eq r7 r10 plus r4 LSL 1 Offset
62 0x83, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 LSL 1 Offset
65 0x86, 0xb0, 0x8a, 0x37 // str cc r11 r10 plus r6 LSL 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to31-ldrb-a32.h38 0x86, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 LSL 1 Offset
41 0x85, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 LSL 1 Offset
44 0x8e, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 LSL 1 Offset
47 0x88, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 LSL 1 Offset
50 0x8e, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 LSL 1 Offset
53 0x87, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 LSL 1 Offset
56 0x89, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 LSL 1 Offset
59 0x84, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 LSL 1 Offset
62 0x83, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSL 1 Offset
65 0x86, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 LSL 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to31-ldr-a32.h38 0x86, 0x80, 0x9b, 0x57 // ldr pl r8 r11 plus r6 LSL 1 Offset
41 0x85, 0x40, 0x98, 0xd7 // ldr le r4 r8 plus r5 LSL 1 Offset
44 0x8e, 0x20, 0x96, 0x67 // ldr vs r2 r6 plus r14 LSL 1 Offset
47 0x88, 0x10, 0x97, 0x97 // ldr ls r1 r7 plus r8 LSL 1 Offset
50 0x8e, 0xe0, 0x96, 0xa7 // ldr ge r14 r6 plus r14 LSL 1 Offset
53 0x87, 0x70, 0x90, 0x27 // ldr cs r7 r0 plus r7 LSL 1 Offset
56 0x89, 0xb0, 0x90, 0xa7 // ldr ge r11 r0 plus r9 LSL 1 Offset
59 0x84, 0x70, 0x9a, 0x07 // ldr eq r7 r10 plus r4 LSL 1 Offset
62 0x83, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 LSL 1 Offset
65 0x86, 0xb0, 0x9a, 0x37 // ldr cc r11 r10 plus r6 LSL 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to32-ldr-a32.h38 0xa6, 0x80, 0x9b, 0x57 // ldr pl r8 r11 plus r6 LSR 1 Offset
41 0xa5, 0x40, 0x98, 0xd7 // ldr le r4 r8 plus r5 LSR 1 Offset
44 0xae, 0x20, 0x96, 0x67 // ldr vs r2 r6 plus r14 LSR 1 Offset
47 0xa8, 0x10, 0x97, 0x97 // ldr ls r1 r7 plus r8 LSR 1 Offset
50 0xae, 0xe0, 0x96, 0xa7 // ldr ge r14 r6 plus r14 LSR 1 Offset
53 0xa7, 0x70, 0x90, 0x27 // ldr cs r7 r0 plus r7 LSR 1 Offset
56 0xa9, 0xb0, 0x90, 0xa7 // ldr ge r11 r0 plus r9 LSR 1 Offset
59 0xa4, 0x70, 0x9a, 0x07 // ldr eq r7 r10 plus r4 LSR 1 Offset
62 0xa3, 0x90, 0x92, 0xe7 // ldr al r9 r2 plus r3 LSR 1 Offset
65 0xa6, 0xb0, 0x9a, 0x37 // ldr cc r11 r10 plus r6 LSR 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to32-ldrb-a32.h38 0xa6, 0x80, 0xdb, 0x57 // ldrb pl r8 r11 plus r6 LSR 1 Offset
41 0xa5, 0x40, 0xd8, 0xd7 // ldrb le r4 r8 plus r5 LSR 1 Offset
44 0xae, 0x20, 0xd6, 0x67 // ldrb vs r2 r6 plus r14 LSR 1 Offset
47 0xa8, 0x10, 0xd7, 0x97 // ldrb ls r1 r7 plus r8 LSR 1 Offset
50 0xae, 0xe0, 0xd6, 0xa7 // ldrb ge r14 r6 plus r14 LSR 1 Offset
53 0xa7, 0x70, 0xd0, 0x27 // ldrb cs r7 r0 plus r7 LSR 1 Offset
56 0xa9, 0xb0, 0xd0, 0xa7 // ldrb ge r11 r0 plus r9 LSR 1 Offset
59 0xa4, 0x70, 0xda, 0x07 // ldrb eq r7 r10 plus r4 LSR 1 Offset
62 0xa3, 0x90, 0xd2, 0xe7 // ldrb al r9 r2 plus r3 LSR 1 Offset
65 0xa6, 0xb0, 0xda, 0x37 // ldrb cc r11 r10 plus r6 LSR 1 Offset
[all …]
Dassembler-cond-rd-memop-rs-shift-amount-1to32-str-a32.h38 0xa6, 0x80, 0x8b, 0x57 // str pl r8 r11 plus r6 LSR 1 Offset
41 0xa5, 0x40, 0x88, 0xd7 // str le r4 r8 plus r5 LSR 1 Offset
44 0xae, 0x20, 0x86, 0x67 // str vs r2 r6 plus r14 LSR 1 Offset
47 0xa8, 0x10, 0x87, 0x97 // str ls r1 r7 plus r8 LSR 1 Offset
50 0xae, 0xe0, 0x86, 0xa7 // str ge r14 r6 plus r14 LSR 1 Offset
53 0xa7, 0x70, 0x80, 0x27 // str cs r7 r0 plus r7 LSR 1 Offset
56 0xa9, 0xb0, 0x80, 0xa7 // str ge r11 r0 plus r9 LSR 1 Offset
59 0xa4, 0x70, 0x8a, 0x07 // str eq r7 r10 plus r4 LSR 1 Offset
62 0xa3, 0x90, 0x82, 0xe7 // str al r9 r2 plus r3 LSR 1 Offset
65 0xa6, 0xb0, 0x8a, 0x37 // str cc r11 r10 plus r6 LSR 1 Offset
[all …]
/external/capstone/suite/MC/ARM/
Darm-shift-encoding.s.cs2 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
3 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
4 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
5 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
6 0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
7 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
8 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
9 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
10 0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
11 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
[all …]
/external/tensorflow/tensorflow/core/kernels/
Dsubstr_op_test.cc68 "TensorFlow\xe6\x98\xaf\xe4\xb8\x80\xe4\xb8\xaa\xe4\xbd\xbf\xe7\x94\xa8\xe6"
70 "\x95\xb0\xe5\x80\xbc\xe8\xae\xa1\xe7\xae\x97\xe7\x9a\x84\xe5\xbc\x80\xe6"
72 "\xe5\x9b\xbe\xe5\xbd\xa2\xe8\x8a\x82\xe7\x82\xb9\xe8\xa1\xa8\xe7\xa4\xba"
73 "\xe6\x95\xb0\xe5\xad\xa6\xe8\xbf\x90\xe7\xae\x97\xef\xbc\x8c\xe8\x80\x8c"
74 "\xe5\x9b\xbe\xe5\xbd\xa2\xe8\xbe\xb9\xe7\xbc\x98\xe8\xa1\xa8\xe7\xa4\xba"
76 "\xe5\x8a\xa8\xe7\x9a\x84\xe5\xa4\x9a\xe7\xbb\xb4\xe6\x95\xb0\xe6\x8d\xae"
79 "\xe8\xbf\x99\xe7\xa7\x8d\xe7\x81\xb5\xe6\xb4\xbb\xe7\x9a\x84\xe4\xbd\x93"
80 "\xe7\xb3\xbb\xe7\xbb\x93\xe6\x9e\x84\xe4\xbd\xbf\xe6\x82\xa8\xe5\x8f\xaf"
81 "\xe4\xbb\xa5\xe5\xb0\x86\xe8\xae\xa1\xe7\xae\x97\xe9\x83\xa8\xe7\xbd\xb2"
83 "\xe5\x99\xa8\xe6\x88\x96\xe7\xa7\xbb\xe5\x8a\xa8\xe8\xae\xbe\xe5\xa4\x87"
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Darm-shift-encoding.s6 ldr r0, [r0, r0, lsl #0]
13 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
14 @ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15 @ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
16 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
17 @ CHECK: ldr r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x90,0xe7]
18 @ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
19 @ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
20 @ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
21 @ CHECK: ldr r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x90,0xe7]
[all …]

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