| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | csr-split.ll | 2 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-linux < %s | FileCheck %s
3 ; RUN: llc -verify-machineinstrs -mtriple=i386-unknown-linux < %s | FileCheck %s --check-prefix=CHE…
10 ; CHECK-LABEL: test1:
12 ; CHECK-NEXT: pushq %rbx
13 ; CHECK-NEXT: .cfi_def_cfa_offset 16
14 ; CHECK-NEXT: .cfi_offset %rbx, -16
15 ; CHECK-NEXT: movslq {{.*}}(%rip), %rax
16 ; CHECK-NEXT: cmpq %rdi, %rax
17 ; CHECK-NEXT: je .LBB0_2
18 ; CHECK-NEXT: # %bb.1: # %if.end
[all …]
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | aix32-cc-abi-vaarg.ll | 1 ; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
2 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
4 ; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
5 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
6 ; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
44 ; 32BIT-LABEL: name: int_va_arg
45 ; 32BIT-LABEL; liveins:
46 ; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
47 ; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
48 ; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
[all …]
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| D | aix-cc-byval-mem.ll | 1 ; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy \
2 ; RUN: -mcpu=pwr4 -mattr=-altivec \
3 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
4 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
6 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
7 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
8 ; RUN: FileCheck --check-prefixes=CHECKASM,ASM32BIT %s
10 ; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy \
11 ; RUN: -mcpu=pwr4 -mattr=-altivec \
12 ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
[all …]
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| D | aix-crspill.ll | 1 ; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
2 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
4 ; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
5 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
23 ; 64BIT-LABEL: .killOne:
25 ; 64BIT: mflr 0
26 ; 64BIT-NEXT: std 0, 16(1)
27 ; 64BIT-NEXT: mfcr 12
28 ; 64BIT-NEXT: stw 12, 8(1)
29 ; 64BIT: stdu 1, -112(1)
[all …]
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| D | aix-cc-abi.ll | 1 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
2 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
4 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
5 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
6 ; RUN: FileCheck --check-prefixes=CHECKASM,ASM32PWR4 %s
8 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
9 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
11 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
12 ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
13 ; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
[all …]
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| D | aix-cc-byval.ll | 1 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
2 ; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
3 ; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
5 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
6 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
7 ; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
9 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
10 ; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
11 ; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
13 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
[all …]
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| D | aix-base-pointer.ll | 1 ; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
2 ; RUN: -mtriple=powerpc-unknown-aix < %s | FileCheck %s --check-prefix 32BIT
4 ; RUN: llc -mcpu=pwr7 -mattr=-altivec -verify-machineinstrs \
5 ; RUN: -mtriple=powerpc64-unknown-aix < %s | FileCheck %s --check-prefix 64BIT
7 ; Use an overaligned buffer to force base-pointer usage. Test verifies:
8 ; - base pointer register (r30) is saved/defined/restored.
9 ; - stack frame is allocated with correct alignment.
10 ; - Address of %AlignedBuffer is calculated based off offset from the stack
14 %AlignedBuffer = alloca [32 x i32], align 32
15 %Pointer = getelementptr inbounds [32 x i32], [32 x i32]* %AlignedBuffer, i64 0, i64 0
[all …]
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| /external/rust/crates/ahash/smhasher/ |
| D | ahashOutput.txt | 1 -------------------------------------------------------------------------------
2 --- Testing ahash64 "ahash 64bit" GOOD
6 Verification value 0x84A46E17 ....... SKIP (self- or unseeded)
12 Bulk speed test - 262144-byte keys
13 Alignment 7 - 8.351 bytes/cycle - 23891.85 MiB/sec @ 3 ghz
14 Alignment 6 - 8.327 bytes/cycle - 23823.64 MiB/sec @ 3 ghz
15 Alignment 5 - 8.312 bytes/cycle - 23780.76 MiB/sec @ 3 ghz
16 Alignment 4 - 8.309 bytes/cycle - 23772.79 MiB/sec @ 3 ghz
17 Alignment 3 - 8.315 bytes/cycle - 23790.37 MiB/sec @ 3 ghz
18 Alignment 2 - 8.339 bytes/cycle - 23858.92 MiB/sec @ 3 ghz
[all …]
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| D | fallbackOutput.txt | 1 -------------------------------------------------------------------------------
2 --- Testing ahash64 "ahash 64bit" GOOD
6 Verification value 0x52EC0BA4 ....... SKIP (self- or unseeded)
12 Bulk speed test - 262144-byte keys
13 Alignment 7 - 8.506 bytes/cycle - 24336.28 MiB/sec @ 3 ghz
14 Alignment 6 - 8.505 bytes/cycle - 24333.38 MiB/sec @ 3 ghz
15 Alignment 5 - 8.500 bytes/cycle - 24317.30 MiB/sec @ 3 ghz
16 Alignment 4 - 8.491 bytes/cycle - 24294.09 MiB/sec @ 3 ghz
17 Alignment 3 - 8.491 bytes/cycle - 24293.90 MiB/sec @ 3 ghz
18 Alignment 2 - 8.492 bytes/cycle - 24296.22 MiB/sec @ 3 ghz
[all …]
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVSchedule.td | 1 //===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVSchedule.td | 1 //===-- RISCVSchedule.td - RISCV Scheduling Definitions -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShift32 : SchedWrite; // 32-bit shift operations on RV64Ix
13 def WriteShift : SchedWrite; // 32 or 64-bit shift operations
14 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
15 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
[all …]
|
| /external/llvm-project/llvm/test/MC/X86/ |
| D | x86_errors.s | 1 // RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
2 // RUN: FileCheck --check-prefix=64 < %t.err %s
4 // RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
5 // RUN: FileCheck --check-prefix=32 < %t.err %s
11 // 32: error: register %rax is only available in 64-bit mode
14 // 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
21 // 32: error: instruction requires: 64-bit mode
29 // 64: error: base register is 64-bit, but index register is not
32 // 64: error: invalid 16-bit base register
35 // 32: error: scale factor in 16-bit address must be 1
[all …]
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| /external/oboe/samples/RhythmGame/third_party/glm/gtx/ |
| D | type_aligned.hpp | 33 /// Low precision 8 bit signed integer aligned scalar type.
37 /// Low precision 16 bit signed integer aligned scalar type.
41 /// Low precision 32 bit signed integer aligned scalar type.
45 /// Low precision 64 bit signed integer aligned scalar type.
50 /// Low precision 8 bit signed integer aligned scalar type.
54 /// Low precision 16 bit signed integer aligned scalar type.
58 /// Low precision 32 bit signed integer aligned scalar type.
62 /// Low precision 64 bit signed integer aligned scalar type.
67 /// Low precision 8 bit signed integer aligned scalar type.
71 /// Low precision 16 bit signed integer aligned scalar type.
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | 3addr-16bit.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
4 ; In 32-bit the partial register stall would degrade performance.
8 ; 32BIT-LABEL: t1:
9 ; 32BIT: movw 20(%esp), %ax
10 ; 32BIT-NOT: movw %ax, %cx
11 ; 32BIT: leal 1(%eax), %ecx
13 ; 64BIT-LABEL: t1:
14 ; 64BIT-NOT: movw %si, %ax
15 ; 64BIT: movl %esi, %eax
30 ; 32BIT-LABEL: t2:
[all …]
|
| /external/llvm-project/clang/lib/Headers/ |
| D | mmintrin.h | 1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
37 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
44 /// A 32-bit integer value.
45 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
46 /// parameter. The upper 32 bits are set to 0.
53 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
61 /// A 64-bit integer vector.
[all …]
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| D | xmmintrin.h | 1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
34 /// Adds the 32-bit float values in the low-order bits of the operands.
41 /// A 128-bit vector of [4 x float] containing one of the source operands.
42 /// The lower 32 bits of this operand are used in the calculation.
44 /// A 128-bit vector of [4 x float] containing one of the source operands.
45 /// The lower 32 bits of this operand are used in the calculation.
46 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
47 /// of the lower 32 bits of both operands. The upper 96 bits are copied from
[all …]
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| /external/clang/lib/Headers/ |
| D | mmintrin.h | 1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
21 *===-----------------------------------------------------------------------===
50 /// \brief Constructs a 64-bit integer vector, setting the lower 32 bits to the
51 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
58 /// A 32-bit integer value.
59 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
60 /// parameter. The upper 32 bits are set to 0.
67 /// \brief Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
75 /// A 64-bit integer vector.
76 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
[all …]
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| D | xmmintrin.h | 1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
21 *===-----------------------------------------------------------------------===
45 /// \brief Adds the 32-bit float values in the low-order bits of the operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
53 /// The lower 32 bits of this operand are used in the calculation.
55 /// A 128-bit vector of [4 x float] containing one of the source operands.
56 /// The lower 32 bits of this operand are used in the calculation.
57 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
58 /// of the lower 32 bits of both operands. The upper 96 bits are copied from
67 /// \brief Adds two 128-bit vectors of [4 x float], and returns the results of
[all …]
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| /external/llvm-project/llvm/test/MC/Mips/mips64r2/ |
| D | invalid.s | 4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1
9 andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
10 andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
11 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
12 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
13 dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
14 dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
15 dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
16 dext $2, $3, 32, 33 # CHECK: :[[@LINE]]:26: error: expected immediate in range 1 .. 32
17 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
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| /external/llvm/test/MC/Mips/mips64r2/ |
| D | invalid.s | 4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1
9 andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
10 andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
11 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
12 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
14 dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
15 dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
16 dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
17 dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
18 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
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| /external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmSignedOpTests.cpp | 1 /*------------------------------------------------------------------------
3 * ------------------------
12 * http://www.apache.org/licenses/LICENSE-2.0
22 * \brief SPIR-V signed instruction tests
23 *//*--------------------------------------------------------------------*/
40 tcu::TestContext& testCtx = tests->getTestContext(); in createSignedOpTests()
49 { "glsl_int_findumsb", "32bit signed int with FindUMsb" }, in createSignedOpTests()
50 { "glsl_int_uclamp", "32bit signed int with UClamp" }, in createSignedOpTests()
51 { "glsl_int_umax", "32bit signed int with UMax" }, in createSignedOpTests()
52 { "glsl_int_umin", "32bit signed int with UMin" }, in createSignedOpTests()
[all …]
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| /external/llvm/test/MC/Mips/mips64r5/ |
| D | invalid.s | 4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1
9 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
10 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
11 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
12 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
13 …jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be differe…
14 …jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be differe…
15 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
16 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
17 dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
[all …]
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| /external/llvm/test/MC/Mips/ |
| D | mips-expansions-bad.s | 1 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
2 # RUN: FileCheck %s < %t1 --check-prefix=32-BIT
3 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
4 # RUN: FileCheck %s --check-prefixes=64-BIT,N32-ONLY
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
6 # RUN: FileCheck %s --check-prefixes=64-BIT,N64-ONLY
10 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
12 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
17 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
[all …]
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| /external/llvm-project/llvm/test/MC/Mips/ |
| D | mips-expansions-bad.s | 1 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
2 # RUN: FileCheck %s < %t1 --check-prefix=32-BIT
3 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
4 # RUN: FileCheck %s --check-prefix=64-BIT
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
6 # RUN: FileCheck %s --check-prefix=64-BIT
10 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
12 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
17 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
[all …]
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| /external/oboe/samples/RhythmGame/third_party/glm/ |
| D | fwd.hpp | 17 /// Quaternion of low single-precision floating-point numbers.
22 /// Quaternion of medium single-precision floating-point numbers.
27 /// Quaternion of high single-precision floating-point numbers.
39 /// Quaternion of default single-precision floating-point numbers.
43 /// Quaternion of low single-precision floating-point numbers.
48 /// Quaternion of medium single-precision floating-point numbers.
53 /// Quaternion of high single-precision floating-point numbers.
58 /// Quaternion of default single-precision floating-point numbers.
64 /// Quaternion of low double-precision floating-point numbers.
69 /// Quaternion of medium double-precision floating-point numbers.
[all …]
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