Home
last modified time | relevance | path

Searched full:d6 (Results 1 – 25 of 1441) sorted by relevance

12345678910>>...58

/external/boringssl/linux-arm/crypto/fipsmodule/
Dghash-armv4.S45 vld1.64 d6,[r1]
49 vshr.u64 d26,d6,#63
66 vld1.64 d6,[r0]!
97 vld1.64 d6,[r2]!
104 vmull.p8 q8, d16, d6 @ F = A1*B
105 vext.8 d0, d6, d6, #1 @ B1
108 vmull.p8 q9, d18, d6 @ H = A2*B
109 vext.8 d22, d6, d6, #2 @ B2
113 vmull.p8 q10, d20, d6 @ J = A3*B
114 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/rust/crates/ring/pregenerated/
Dghash-armv4-linux32.S42 vld1.64 d6,[r1]
46 vshr.u64 d26,d6,#63
63 vld1.64 d6,[r0]!
94 vld1.64 d6,[r2]!
101 vmull.p8 q8, d16, d6 @ F = A1*B
102 vext.8 d0, d6, d6, #1 @ B1
105 vmull.p8 q9, d18, d6 @ H = A2*B
106 vext.8 d22, d6, d6, #2 @ B2
110 vmull.p8 q10, d20, d6 @ J = A3*B
111 vext.8 d0, d6, d6, #3 @ B3
[all …]
Dghash-armv4-ios32.S43 vld1.64 d6,[r1]
47 vshr.u64 d26,d6,#63
66 vld1.64 d6,[r0]!
99 vld1.64 d6,[r2]!
106 vmull.p8 q8, d16, d6 @ F = A1*B
107 vext.8 d0, d6, d6, #1 @ B1
110 vmull.p8 q9, d18, d6 @ H = A2*B
111 vext.8 d22, d6, d6, #2 @ B2
115 vmull.p8 q10, d20, d6 @ J = A3*B
116 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/
Dghash-armv4.S46 vld1.64 d6,[r1]
50 vshr.u64 d26,d6,#63
69 vld1.64 d6,[r0]!
102 vld1.64 d6,[r2]!
109 vmull.p8 q8, d16, d6 @ F = A1*B
110 vext.8 d0, d6, d6, #1 @ B1
113 vmull.p8 q9, d18, d6 @ H = A2*B
114 vext.8 d22, d6, d6, #2 @ B2
118 vmull.p8 q10, d20, d6 @ J = A3*B
119 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/
Dghash-armv4.S45 vld1.64 d6,[r1]
49 vshr.u64 d26,d6,#63
66 vld1.64 d6,[r0]!
97 vld1.64 d6,[r2]!
104 vmull.p8 q8, d16, d6 @ F = A1*B
105 vext.8 d0, d6, d6, #1 @ B1
108 vmull.p8 q9, d18, d6 @ H = A2*B
109 vext.8 d22, d6, d6, #2 @ B2
113 vmull.p8 q10, d20, d6 @ J = A3*B
114 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/
Dghash-armv4.S45 vld1.64 d6,[r1]
49 vshr.u64 d26,d6,#63
66 vld1.64 d6,[r0]!
97 vld1.64 d6,[r2]!
104 vmull.p8 q8, d16, d6 @ F = A1*B
105 vext.8 d0, d6, d6, #1 @ B1
108 vmull.p8 q9, d18, d6 @ H = A2*B
109 vext.8 d22, d6, d6, #2 @ B2
113 vmull.p8 q10, d20, d6 @ J = A3*B
114 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/boringssl/ios-arm/crypto/fipsmodule/
Dghash-armv4.S46 vld1.64 d6,[r1]
50 vshr.u64 d26,d6,#63
69 vld1.64 d6,[r0]!
102 vld1.64 d6,[r2]!
109 vmull.p8 q8, d16, d6 @ F = A1*B
110 vext.8 d0, d6, d6, #1 @ B1
113 vmull.p8 q9, d18, d6 @ H = A2*B
114 vext.8 d22, d6, d6, #2 @ B2
118 vmull.p8 q10, d20, d6 @ J = A3*B
119 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/
Dghash-armv4.S46 vld1.64 d6,[r1]
50 vshr.u64 d26,d6,#63
69 vld1.64 d6,[r0]!
102 vld1.64 d6,[r2]!
109 vmull.p8 q8, d16, d6 @ F = A1*B
110 vext.8 d0, d6, d6, #1 @ B1
113 vmull.p8 q9, d18, d6 @ H = A2*B
114 vext.8 d22, d6, d6, #2 @ B2
118 vmull.p8 q10, d20, d6 @ J = A3*B
119 vext.8 d0, d6, d6, #3 @ B3
[all …]
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_planar.s153 vdup.s8 d6, r9 @nt - 1 - row
196 vmlal.u8 q6, d6, d3 @(1)(nt-1-row) * src[2nt+1+col]
204 vsub.s8 d6, d6, d7 @(1)
212 vmlal.u8 q15, d6, d3 @(2)
218 vsub.s8 d6, d6, d7 @(2)
227 vmlal.u8 q14, d6, d3 @(3)
235 vsub.s8 d6, d6, d7 @(3)
244 vmlal.u8 q5, d6, d3 @(4)
252 vsub.s8 d6, d6, d7 @(4)
261 vmlal.u8 q8, d6, d3 @(5)
[all …]
Dihevc_itrans_recon_32x32.s118 @d4[0]= 64 d6[0]=36
119 @d4[1]= 61 d6[1]=31
120 @d4[2]= 57 d6[2]=25
121 @d4[3]= 54 d6[3]=22
178 vld1.16 {d4,d5,d6,d7},[r14]!
259 vmlal.s16 q14,d14,d6[1]
288 vmlal.s16 q13,d8,d6[3] @// y1 * cos3(part of b1)
305 vmlal.s16 q11,d10,d6[0]
308 vmlsl.s16 q8,d10,d6[0]
332 vmlsl.s16 q13,d14,d6[1]
[all …]
Dihevc_intra_pred_luma_mode_3_to_9.s180 vmovn.s16 d6, q11
195 vand d6, d6, d29 @fract values in d1/ idx values in d0
206 vsub.s8 d7, d28, d6 @32-fract
214 vmlal.u8 q12, d13, d6 @mul (row 0)
224 vmlal.u8 q11, d17, d6 @mul (row 1)
235 vmlal.u8 q10, d15, d6 @mul (row 2)
246 vmlal.u8 q9, d11, d6 @mul (row 3)
257 vmlal.u8 q12, d13, d6 @mul (row 4)
268 vmlal.u8 q11, d17, d6 @mul (row 5)
279 vmlal.u8 q10, d15, d6 @mul (row 6)
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_tns_ar_filter_fixed.s149 VADD.I64 D6, D2, D3
151 …VSHR.S64 D6, #32 @acc1=acc>>32 @acc = mac32_tns_neon(state[j - 1],lpc[j],acc, t…
152 @VMOV R11,D6[0]
153 VST1.32 D6[0], [SP]
189 VADD.I64 D6, D2, D3
190 VSHR.S64 D6, #32 @acc = mac32_tns_neon(state[j - 1],lpc[j],acc, temp_lo)@
192 @VMOV R11,D6[0]
193 VST1.32 D6[0], [SP]
233 VADD.I64 D6, D2, D3
235 VSHR.S64 D6, #32
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfcmp.mir605 liveins: $d6, $d7
608 ; FP32: liveins: $d6, $d7
613 ; FP64: liveins: $d6, $d7
631 liveins: $d6, $d7
634 ; FP32: liveins: $d6, $d7
639 ; FP64: liveins: $d6, $d7
657 liveins: $d6, $d7
660 ; FP32: liveins: $d6, $d7
661 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
669 ; FP64: liveins: $d6, $d7
[all …]
Dfloat_arithmetic_operations.mir148 liveins: $d6, $d7
151 ; FP32: liveins: $d6, $d7
152 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
158 ; FP64: liveins: $d6, $d7
159 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
164 %0:fprb(s64) = COPY $d6
179 liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
183 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
189 ; FP64: liveins: $d6, $d7
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dfloat_arithmetic_operations.mir139 liveins: $d6, $d7
142 ; FP32: liveins: $d6, $d7
143 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
149 ; FP64: liveins: $d6, $d7
150 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
155 %0:_(s64) = COPY $d6
168 liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
172 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
178 ; FP64: liveins: $d6, $d7
[all …]
Dceil_and_floor.mir52 liveins: $d6
55 ; FP32: liveins: $d6
56 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
58 ; FP32: $d6 = COPY [[COPY]](s64)
59 ; FP32: JAL &ceil, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
65 ; FP64: liveins: $d6
66 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
74 %0:_(s64) = COPY $d6
120 liveins: $d6
123 ; FP32: liveins: $d6
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc111 {{F32, d17, d8, d6}, false, al, "F32 d17 d8 d6", "F32_d17_d8_d6"},
113 {{F32, d17, d6, d28}, false, al, "F32 d17 d6 d28", "F32_d17_d6_d28"},
114 {{F32, d30, d6, d27}, false, al, "F32 d30 d6 d27", "F32_d30_d6_d27"},
115 {{F32, d6, d13, d11}, false, al, "F32 d6 d13 d11", "F32_d6_d13_d11"},
123 {{F32, d6, d26, d20}, false, al, "F32 d6 d26 d20", "F32_d6_d26_d20"},
124 {{F32, d2, d7, d6}, false, al, "F32 d2 d7 d6", "F32_d2_d7_d6"},
126 {{F32, d6, d12, d13}, false, al, "F32 d6 d12 d13", "F32_d6_d12_d13"},
127 {{F32, d6, d17, d17}, false, al, "F32 d6 d17 d17", "F32_d6_d17_d17"},
128 {{F32, d18, d7, d6}, false, al, "F32 d18 d7 d6", "F32_d18_d7_d6"},
140 {{F32, d16, d15, d6}, false, al, "F32 d16 d15 d6", "F32_d16_d15_d6"},
[all …]
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc111 {{F32, d17, d8, d6}, false, al, "F32 d17 d8 d6", "F32_d17_d8_d6"},
113 {{F32, d17, d6, d28}, false, al, "F32 d17 d6 d28", "F32_d17_d6_d28"},
114 {{F32, d30, d6, d27}, false, al, "F32 d30 d6 d27", "F32_d30_d6_d27"},
115 {{F32, d6, d13, d11}, false, al, "F32 d6 d13 d11", "F32_d6_d13_d11"},
123 {{F32, d6, d26, d20}, false, al, "F32 d6 d26 d20", "F32_d6_d26_d20"},
124 {{F32, d2, d7, d6}, false, al, "F32 d2 d7 d6", "F32_d2_d7_d6"},
126 {{F32, d6, d12, d13}, false, al, "F32 d6 d12 d13", "F32_d6_d12_d13"},
127 {{F32, d6, d17, d17}, false, al, "F32 d6 d17 d17", "F32_d6_d17_d17"},
128 {{F32, d18, d7, d6}, false, al, "F32 d18 d7 d6", "F32_d18_d7_d6"},
140 {{F32, d16, d15, d6}, false, al, "F32 d16 d15 d6", "F32_d16_d15_d6"},
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dfloat_arithmetic_operations.mir144 liveins: $d6, $d7
147 ; FP32: liveins: $d6, $d7
148 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
154 ; FP64: liveins: $d6, $d7
155 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
160 %0:_(s64) = COPY $d6
174 liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
178 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
184 ; FP64: liveins: $d6, $d7
[all …]
/external/llvm/test/MC/ARM/
Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
26 vfms.f64 d4, d5, d6
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
60 vcmp.f64 d6, #0
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
[all …]
/external/libopus/win32/VS2015/
Dopus.sln13 …0A0C91BC942}") = "test_opus_api", "test_opus_api.vcxproj", "{1D257A17-D254-42E5-82D6-1C87A6EC775A}"
92 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.Debug|Win32.ActiveCfg = Debug|Win32
93 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.Debug|Win32.Build.0 = Debug|Win32
94 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.Debug|x64.ActiveCfg = Debug|x64
95 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.Debug|x64.Build.0 = Debug|x64
96 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.DebugDLL_fixed|Win32.ActiveCfg = DebugDLL_fixed|Win32
97 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.DebugDLL_fixed|Win32.Build.0 = DebugDLL_fixed|Win32
98 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.DebugDLL_fixed|x64.ActiveCfg = DebugDLL_fixed|x64
99 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.DebugDLL_fixed|x64.Build.0 = DebugDLL_fixed|x64
100 {1D257A17-D254-42E5-82D6-1C87A6EC775A}.DebugDLL|Win32.ActiveCfg = DebugDLL|Win32
[all …]
/external/gemmlowp/meta/
Dquantized_mul_kernels_arm_32.h131 "vld1.32 {d5, d6}, [%[rhs]:64]!\n" in Multiply()
135 "vmull.u8 q5, d6, d4\n" in Multiply()
174 : "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d8", "d9", "d10", "d11", in Multiply()
209 "vld1.32 {d6}, [%[lhs]:64]!\n" in Multiply()
213 "vmull.u8 q5, d7, d6\n" in Multiply()
214 "vmull.u8 q6, d8, d6\n" in Multiply()
215 "vmull.u8 q7, d9, d6\n" in Multiply()
258 : "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", in Multiply()
324 "vpadd.u32 d6, d6, d7\n" in Multiply()
326 "vpadd.u32 d1, d4, d6\n" in Multiply()
[all …]
/external/libavc/common/arm/
Dih264_inter_pred_chroma_a9q.s144 vld1.8 {d5, d6, d7}, [r0], r2 @ Load row1
146 vext.8 d8, d5, d6, #2
152 vext.8 d9, d6, d7, #2
156 vmull.u8 q6, d6, d30
164 vmov d1, d6
167 vld1.8 {d5, d6, d7}, [r0], r2 @ Load row1
170 vext.8 d8, d5, d6, #2
172 vext.8 d9, d6, d7, #2
181 vmull.u8 q6, d6, d30
211 vqrshrun.s16 d6, q2, #6
[all …]
Dih264_inter_pred_filters_luma_horz_a9q.s125 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
128 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
130 vext.8 d27, d6, d7, #5 @//extract a[5] (column2,row1)
133 vaddl.u8 q8, d27, d6 @// a0 + a5 (column2,row1)
136 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
138 vext.8 d27, d6, d7, #2 @//extract a[2] (column2,row1)
144 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
146 vext.8 d27, d6, d7, #3 @//extract a[3] (column2,row1)
152 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
154 vext.8 d27, d6, d7, #1 @//extract a[1] (column2,row1)
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
26 vfms.f64 d4, d5, d6
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
60 vcmp.f64 d6, #0
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #0
[all …]

12345678910>>...58