| /external/google-breakpad/src/common/dwarf/ |
| D | dwarf2reader_cfi_unittest.cc | 257 .D8(0xd7).D8(0xe5).D8(0xf1) // incomplete id in TEST_F()
766 .D8(dwarf2reader::DW_CFA_def_cfa) in StockCIEAndFDE()
826 .D8(dwarf2reader::DW_CFA_set_loc).D32(0xb1ee3e7a) in TEST_F()
829 .D8(dwarf2reader::DW_CFA_def_cfa).ULEB128(0x4defb431).ULEB128(0x6d17b0ee) in TEST_F()
847 .D8(dwarf2reader::DW_CFA_advance_loc | 0x2a) in TEST_F()
850 .D8(dwarf2reader::DW_CFA_def_cfa).ULEB128(0x5bbb3715).ULEB128(0x0186c7bf) in TEST_F()
869 .D8(dwarf2reader::DW_CFA_advance_loc1).D8(0xd8) in TEST_F()
870 .D8(dwarf2reader::DW_CFA_def_cfa).ULEB128(0x69d5696a).ULEB128(0x1eb7fc93) in TEST_F()
889 .D8(dwarf2reader::DW_CFA_advance_loc2).D16(0x3adb) in TEST_F()
890 .D8(dwarf2reader::DW_CFA_def_cfa).ULEB128(0x3a368bed).ULEB128(0x3194ee37) in TEST_F()
[all …]
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_pre_twiddle_compute.s | 29 VPUSH {d8 - d15}
106 VLD2.16 {D8[0], D9[0]}, [R3], R6
107 VLD2.16 {D8[1], D9[1]}, [R3], R6
108 VLD2.16 {D8[2], D9[2]}, [R3], R6
109 VLD2.16 {D8[3], D9[3]}, [R3], R6
126 VMULL.U16 Q13, D2, D8
127 VMULL.U16 Q12, D4, D8
136 VMLAL.S16 Q13, D3, D8
137 VMLAL.S16 Q12, D5, D8
154 VLD2.16 {D8[0], D9[0]}, [R3], R6
[all …]
|
| D | ixheaacd_post_twiddle.s | 29 VPUSH {d8 - d15}
105 VLD2.16 {D8[0], D9[0]}, [R2], R6
106 VLD2.16 {D8[1], D9[1]}, [R2], R6
107 VLD2.16 {D8[2], D9[2]}, [R2], R6
108 VLD2.16 {D8[3], D9[3]}, [R2], R6
135 VMULL.U16 Q9, D6, D8
136 VMULL.U16 Q8, D4, D8
153 VMLAL.S16 Q9, D7, D8
154 VMLAL.S16 Q8, D5, D8
156 VLD2.16 {D8[0], D9[0]}, [R2], R6
[all …]
|
| D | ixheaacd_post_twiddle_overlap.s | 29 VPUSH {d8 - d15}
142 VQMOVN.S64 D8, Q0
149 VQSUB.S32 D8, D0, D8
152 VQSHL.S32 D8, D8, #2
154 VQADD.S32 D8, D8, D0
155 VSHR.S32 D8, D8, #16
169 VST1.16 D8[2], [R0], R9
170 VST1.16 D8[0], [R5], R10
197 VLD2.16 {D8, D9}, [R2]!
203 VMULL.U16 Q14, D2, D8
[all …]
|
| D | ixheaacd_dct3_32.s | 35 VPUSH {D8 - D15}
78 VSWP D8, D9
122 VSWP D8, D9
156 VSWP D8, D9
199 VLD1.32 D8[0], [R5], R11
206 VLD1.32 D8[1], [R5], R11
305 VLD2.16 {D8, D9}, [R10], R5
308 VREV64.16 D8, D8
327 VMULL.U16 Q15, D12, D8
330 VMLSL.U16 Q14, D16, D8
[all …]
|
| /external/libdrm/data/ |
| D | amdgpu.ids | 10 15DD, D8, AMD Radeon(TM) Vega 3 Graphics
31 15D8, 93, AMD Radeon(TM) Vega 1 Graphics
32 15D8, C4, AMD Radeon(TM) Vega 3 Graphics
33 15D8, C5, AMD Radeon(TM) Vega 3 Graphics
34 15D8, CC, AMD Radeon(TM) Vega 3 Graphics
35 15D8, CE, AMD Radeon(TM) Vega 3 Graphics
36 15D8, CF, AMD Radeon(TM) Vega 3 Graphics
37 15D8, D4, AMD Radeon(TM) Vega 3 Graphics
38 15D8, DC, AMD Radeon(TM) Vega 3 Graphics
39 15D8, DD, AMD Radeon(TM) Vega 3 Graphics
[all …]
|
| /external/curl/tests/data/ |
| D | test1138 | 65 …e/all/moo.html/?name=%d8%a2%d8%ba%d8%a7%d8%b2-%d8%b3%d9%85-%d8%b2%d8%af%d8%a7%db%8c%db%8c-%d8%a7%d…
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | cortex-a57-neon-instructions.s | 919 vst1.8 {d8}, [r4]!
920 vst1.16 {d8}, [r4]!
921 vst1.32 {d8}, [r4]!
922 vst1.64 {d8}, [r4]!
923 vst1.8 {d8}, [r4], r6
924 vst1.16 {d8}, [r4], r6
925 vst1.32 {d8}, [r4], r6
926 vst1.64 {d8}, [r4], r6
927 vst1.8 {d8, d9}, [r4]!
928 vst1.16 {d8, d9}, [r4]!
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 1652 # CHECK: vst1.8 {d8}, [r4]!
1654 # CHECK: vst1.16 {d8}, [r4]!
1656 # CHECK: vst1.32 {d8}, [r4]!
1658 # CHECK: vst1.64 {d8}, [r4]!
1660 # CHECK: vst1.8 {d8}, [r4], r6
1662 # CHECK: vst1.16 {d8}, [r4], r6
1664 # CHECK: vst1.32 {d8}, [r4], r6
1666 # CHECK: vst1.64 {d8}, [r4], r6
1669 # CHECK: vst1.8 {d8, d9}, [r4]!
1671 # CHECK: vst1.16 {d8, d9}, [r4]!
[all …]
|
| D | neon.txt | 1945 # CHECK: vst1.8 {d8}, [r4]!
1947 # CHECK: vst1.16 {d8}, [r4]!
1949 # CHECK: vst1.32 {d8}, [r4]!
1951 # CHECK: vst1.64 {d8}, [r4]!
1953 # CHECK: vst1.8 {d8}, [r4], r6
1955 # CHECK: vst1.16 {d8}, [r4], r6
1957 # CHECK: vst1.32 {d8}, [r4], r6
1959 # CHECK: vst1.64 {d8}, [r4], r6
1962 # CHECK: vst1.8 {d8, d9}, [r4]!
1964 # CHECK: vst1.16 {d8, d9}, [r4]!
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 1642 # CHECK: vst1.8 {d8}, [r4]!
1644 # CHECK: vst1.16 {d8}, [r4]!
1646 # CHECK: vst1.32 {d8}, [r4]!
1648 # CHECK: vst1.64 {d8}, [r4]!
1650 # CHECK: vst1.8 {d8}, [r4], r6
1652 # CHECK: vst1.16 {d8}, [r4], r6
1654 # CHECK: vst1.32 {d8}, [r4], r6
1656 # CHECK: vst1.64 {d8}, [r4], r6
1659 # CHECK: vst1.8 {d8, d9}, [r4]!
1661 # CHECK: vst1.16 {d8, d9}, [r4]!
[all …]
|
| D | neon.txt | 1936 # CHECK: vst1.8 {d8}, [r4]!
1938 # CHECK: vst1.16 {d8}, [r4]!
1940 # CHECK: vst1.32 {d8}, [r4]!
1942 # CHECK: vst1.64 {d8}, [r4]!
1944 # CHECK: vst1.8 {d8}, [r4], r6
1946 # CHECK: vst1.16 {d8}, [r4], r6
1948 # CHECK: vst1.32 {d8}, [r4], r6
1950 # CHECK: vst1.64 {d8}, [r4], r6
1953 # CHECK: vst1.8 {d8, d9}, [r4]!
1955 # CHECK: vst1.16 {d8, d9}, [r4]!
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_mode_3_to_9.s | 132 vpush {d8 - d15}
193 vqmovn.s16 d8, q11
201 vsub.s8 d8, d8, d2 @ref_main_idx (sub row)
202 vsub.s8 d8, d26, d8 @ref_main_idx (row 0)
203 vadd.s8 d8, d8, d27 @t0 compensate the pu1_src idx incremented by 8
204 vsub.s8 d9, d8, d2 @ref_main_idx + 1 (row 0)
205 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
209 vsub.s8 d4, d8, d2 @ref_main_idx (row 1)
217 vsub.s8 d8, d8, d3 @ref_main_idx (row 2)
222 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
[all …]
|
| D | ihevc_itrans_recon_32x32.s | 163 vpush {d8 - d15}
213 vld1.16 d8,[r0],r6
217 vmull.s16 q12,d8,d0[1] @// y1 * cos1(part of b0)
218 vmull.s16 q13,d8,d0[3] @// y1 * cos3(part of b1)
219 vmull.s16 q14,d8,d1[1] @// y1 * sin3(part of b2)
220 vmull.s16 q15,d8,d1[3] @// y1 * sin1(part of b3)
282 vld1.16 d8,[r0],r6
287 vmlal.s16 q12,d8,d2[1] @// y1 * cos1(part of b0)
288 vmlal.s16 q13,d8,d6[3] @// y1 * cos3(part of b1)
289 vmlsl.s16 q14,d8,d4[3] @// y1 * sin3(part of b2)
[all …]
|
| D | ihevc_intra_pred_filters_luma_mode_11_to_17.s | 135 vpush {d8 - d15}
305 vqmovn.s16 d8, q11
312 vadd.s8 d8, d8, d27 @ref_main_idx (add row)
313 vsub.s8 d8, d8, d26 @ref_main_idx (row 0)
314 vadd.s8 d9, d8, d2 @ref_main_idx + 1 (row 0)
315 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
319 vadd.s8 d4, d8, d2 @ref_main_idx (row 1)
327 vadd.s8 d8, d8, d3 @ref_main_idx (row 2)
332 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
348 vadd.s8 d8, d8, d3 @ref_main_idx (row 4)
[all …]
|
| D | ihevc_intra_pred_chroma_mode_3_to_9.s | 129 vpush {d8 - d15}
185 vqmovn.s16 d8, q11
186 vshl.s8 d8, d8, #1 @ 2 * idx
197 vsub.s8 d8, d8, d27 @ref_main_idx (sub row)
198 vsub.s8 d8, d26, d8 @ref_main_idx (row 0)
199 vadd.s8 d8, d8, d9 @to compensate the pu1_src idx incremented by 8
200 vsub.s8 d9, d8, d29 @ref_main_idx + 1 (row 0)
201 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
205 vsub.s8 d4, d8, d29 @ref_main_idx (row 1)
215 vsub.s8 d8, d8, d29 @ref_main_idx (row 2)
[all …]
|
| D | ihevc_intra_pred_filters_chroma_mode_11_to_17.s | 129 vpush {d8 - d15}
298 vqmovn.s16 d8, q11
299 vshl.s8 d8, d8, #1 @ 2 * idx
311 vadd.s8 d8, d8, d27 @ref_main_idx (add row)
312 vsub.s8 d8, d8, d26 @ref_main_idx (row 0)
313 vadd.s8 d9, d8, d29 @ref_main_idx + 1 (row 0)
314 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
318 vadd.s8 d4, d8, d29 @ref_main_idx (row 1)
329 vadd.s8 d8, d8, d29 @ref_main_idx (row 2)
334 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | ifcvt-live-subreg.mir | 9 # CHECK: liveins: $r0, $r1, $p0, $d8
10 # CHECK: $d8 = A2_combinew killed $r0, killed $r1
11 # CHECK: $d8 = L2_ploadrdf_io $p0, $r29, 0, implicit killed $d8
12 # CHECK: J2_jumprf killed $p0, $r31, implicit-def $pc, implicit-def $pc, implicit $d8
29 - { reg: '$d8' }
33 liveins: $r0, $r1, $p0, $d8
34 $d8 = A2_combinew killed $r0, killed $r1
46 $d8 = L2_loadrd_io $r29, 0
47 J2_jumpr killed $r31, implicit-def dead $pc, implicit killed $d8
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | mve-fmath.ll | 62 ; CHECK-NEXT: .vsave {d8, d9}
63 ; CHECK-NEXT: vpush {d8, d9}
67 ; CHECK-NEXT: vmov r2, r3, d8
72 ; CHECK-NEXT: vmov d8, r0, r1
74 ; CHECK-NEXT: vpop {d8, d9}
86 ; CHECK-NEXT: .vsave {d8, d9}
87 ; CHECK-NEXT: vpush {d8, d9}
105 ; CHECK-NEXT: vpop {d8, d9}
117 ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
118 ; CHECK-NEXT: vpush {d8, d9, d10, d11}
[all …]
|
| /external/grpc-grpc/examples/csharp/HelloworldXamarin/ |
| D | HelloworldXamarin.sln | 8 … "HelloworldXamarin.iOS", "iOS\HelloworldXamarin.iOS.csproj", "{62336DF0-60D8-478F-8140-B3CB089B41…
32 {62336DF0-60D8-478F-8140-B3CB089B417E}.Debug|Any CPU.ActiveCfg = Debug|iPhoneSimulator
33 {62336DF0-60D8-478F-8140-B3CB089B417E}.Debug|Any CPU.Build.0 = Debug|iPhoneSimulator
34 {62336DF0-60D8-478F-8140-B3CB089B417E}.Release|Any CPU.ActiveCfg = Release|iPhone
35 {62336DF0-60D8-478F-8140-B3CB089B417E}.Release|Any CPU.Build.0 = Release|iPhone
36 {62336DF0-60D8-478F-8140-B3CB089B417E}.Debug|iPhoneSimulator.ActiveCfg = Debug|iPhoneSimulator
37 {62336DF0-60D8-478F-8140-B3CB089B417E}.Debug|iPhoneSimulator.Build.0 = Debug|iPhoneSimulator
38 {62336DF0-60D8-478F-8140-B3CB089B417E}.Release|iPhone.ActiveCfg = Release|iPhone
39 {62336DF0-60D8-478F-8140-B3CB089B417E}.Release|iPhone.Build.0 = Release|iPhone
40 {62336DF0-60D8-478F-8140-B3CB089B417E}.Release|iPhoneSimulator.ActiveCfg = Release|iPhoneSimulator
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | vpush-vpop.s | 6 vpush {d8, d9, d10, d11, d12}
8 vpop {d8, d9, d10, d11, d12}
11 vpush.s8 {d8, d9, d10, d11, d12}
13 vpop.f32 {d8, d9, d10, d11, d12}
16 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
18 @ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
21 @ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed]
23 @ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec]
26 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
28 @ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | vpush-vpop.s | 6 vpush {d8, d9, d10, d11, d12}
8 vpop {d8, d9, d10, d11, d12}
11 vpush.s8 {d8, d9, d10, d11, d12}
13 vpop.f32 {d8, d9, d10, d11, d12}
16 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
18 @ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
21 @ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed]
23 @ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec]
26 @ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
28 @ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
[all …]
|
| /external/gemmlowp/meta/ |
| D | quantized_mul_kernels_arm_32.h | 66 "vld1.32 {d8, d9}, [%[lhs]:64]!\n" in Multiply()
71 "vdup.32 q4, d8[0]\n" in Multiply()
96 : "d0", "d1", "d2", "d3", "d4", "d5", "d8", "d9", "d10", "d11", "d12", in Multiply()
143 "vld1.32 {d8, d9}, [%[lhs]:64]!\n" in Multiply()
148 "vdup.32 q4, d8[0]\n" in Multiply()
174 : "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d8", "d9", "d10", "d11", in Multiply()
210 "vld1.32 {d7, d8, d9}, [%[rhs]:64]!\n" in Multiply()
214 "vmull.u8 q6, d8, d6\n" in Multiply()
224 "vld1.32 {d8, d9}, [%[lhs]:64]!\n" in Multiply()
229 "vdup.32 q4, d8[0]\n" in Multiply()
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | arm-half-promote.ll | 5 ; CHECK: vpush {d8}
6 ; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
7 ; CHECK-NEXT: vmov.i32 d8, #0x0
24 ; CHECK-NEXT: vpop {d8}
31 ; CHECK: vpush {d8}
32 ; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
33 ; CHECK-NEXT: vmov.i32 d8, #0x0
50 ; CHECK-NEXT: vpop {d8}
57 ; CHECK: vpush {d8}
58 ; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
[all …]
|
| /external/libavc/encoder/arm/ |
| D | ime_distortion_metrics_a9q.s | 91 vpush {d8-d15}
101 vld1.8 {d8, d9}, [r0], r2
109 vabal.u8 q0, d10, d8
113 vld1.8 {d8, d9}, [r0], r2
120 vabal.u8 q0, d10, d8
125 vpop {d8-d15}
183 vpush {d8-d15}
184 vld1.8 {d8, d9}, [r0], r2
192 vabal.u8 q0, d10, d8
196 vld1.8 {d8, d9}, [r0], r2
[all …]
|