| /external/llvm-project/llvm/test/MC/SystemZ/ |
| D | insn-bad-z196.s | 8 #CHECK: adtra %f0, %f0, %f0, -1
10 #CHECK: adtra %f0, %f0, %f0, 16
12 adtra %f0, %f0, %f0, -1
13 adtra %f0, %f0, %f0, 16
62 #CHECK: axtra %f0, %f0, %f0, -1
64 #CHECK: axtra %f0, %f0, %f0, 16
66 #CHECK: axtra %f0, %f0, %f2, 0
68 #CHECK: axtra %f0, %f2, %f0, 0
70 #CHECK: axtra %f2, %f0, %f0, 0
72 axtra %f0, %f0, %f0, -1
[all …]
|
| D | insn-bad.s | 16 #CHECK: ad %f0, -1
18 #CHECK: ad %f0, 4096
20 ad %f0, -1
21 ad %f0, 4096
24 #CHECK: adb %f0, -1
26 #CHECK: adb %f0, 4096
28 adb %f0, -1
29 adb %f0, 4096
32 #CHECK: adtra %f0, %f0, %f0, 0
34 adtra %f0, %f0, %f0, 0
[all …]
|
| D | regs-bad.s | 7 #CHECK: lr %f0,%r1
23 lr %f0,%r1
35 #CHECK: lgr %f0,%r1
51 lgr %f0,%r1
79 #CHECK: dlr %f0,%r1
103 dlr %f0,%r1
121 #CHECK: ler %f0,%r1
123 #CHECK: ler %f0,%a1
125 #CHECK: ler %f0,%c1
127 #CHECK: ler %f0,16
[all …]
|
| /external/llvm/test/MC/Sparc/ |
| D | sparc-fp-instructions.s | 3 ! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
4 ! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
5 ! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80]
6 fitos %f0, %f4
7 fitod %f0, %f4
8 fitoq %f0, %f4
10 ! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20]
11 ! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40]
12 ! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60]
13 fstoi %f0, %f4
[all …]
|
| /external/llvm-project/llvm/test/MC/Sparc/ |
| D | sparc-fp-instructions.s | 3 ! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
4 ! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
5 ! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80]
6 fitos %f0, %f4
7 fitod %f0, %f4
8 fitoq %f0, %f4
10 ! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20]
11 ! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40]
12 ! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60]
13 fstoi %f0, %f4
[all …]
|
| /external/clang/test/CXX/over/over.over/ |
| D | p1.cpp | 3 template<typename T> T f0(T);
4 int f0(int);
8 int (*f0)(int); member
13 int (*f0a)(int) = f0; in test_init_f0()
14 int (*f0b)(int) = &f0; in test_init_f0()
15 int (*f0c)(int) = (f0); in test_init_f0()
16 float (*f0d)(float) = f0; in test_init_f0()
17 float (*f0e)(float) = &f0; in test_init_f0()
18 float (*f0f)(float) = (f0); in test_init_f0()
19 int (&f0g)(int) = f0; in test_init_f0()
[all …]
|
| /external/llvm/test/MC/SystemZ/ |
| D | insn-bad-z196.s | 36 #CHECK: cdlfbr %f0, 0, %r0, -1
38 #CHECK: cdlfbr %f0, 0, %r0, 16
40 #CHECK: cdlfbr %f0, -1, %r0, 0
42 #CHECK: cdlfbr %f0, 16, %r0, 0
44 cdlfbr %f0, 0, %r0, -1
45 cdlfbr %f0, 0, %r0, 16
46 cdlfbr %f0, -1, %r0, 0
47 cdlfbr %f0, 16, %r0, 0
50 #CHECK: cdlgbr %f0, 0, %r0, -1
52 #CHECK: cdlgbr %f0, 0, %r0, 16
[all …]
|
| /external/llvm-project/clang/test/CXX/over/over.over/ |
| D | p1.cpp | 5 template<typename T> T f0(T) NOEXCEPT;
6 int f0(int) NOEXCEPT;
10 int (*f0)(int); member
15 int (*f0a)(int) = f0; in test_init_f0()
16 int (*f0b)(int) = &f0; in test_init_f0()
17 int (*f0c)(int) = (f0); in test_init_f0()
18 float (*f0d)(float) = f0; in test_init_f0()
19 float (*f0e)(float) = &f0; in test_init_f0()
20 float (*f0f)(float) = (f0); in test_init_f0()
21 int (&f0g)(int) = f0; in test_init_f0()
[all …]
|
| /external/capstone/suite/MC/Sparc/ |
| D | sparc-fp-instructions.s.cs | 2 0x89,0xa0,0x18,0x80 = fitos %f0, %f4
3 0x89,0xa0,0x19,0x00 = fitod %f0, %f4
4 0x89,0xa0,0x19,0x80 = fitoq %f0, %f4
5 0x89,0xa0,0x1a,0x20 = fstoi %f0, %f4
6 0x89,0xa0,0x1a,0x40 = fdtoi %f0, %f4
7 0x89,0xa0,0x1a,0x60 = fqtoi %f0, %f4
8 0x89,0xa0,0x19,0x20 = fstod %f0, %f4
9 0x89,0xa0,0x19,0xa0 = fstoq %f0, %f4
10 0x89,0xa0,0x18,0xc0 = fdtos %f0, %f4
11 0x89,0xa0,0x19,0xc0 = fdtoq %f0, %f4
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen6/ |
| D | cmp.asm | 1 cmp.ge.f0.0(8) g38<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
2 cmp.l.f0.0(8) g39<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
5 cmp.ge.f0.0(8) null<1>F g38<4>.xF g36<4>.xF { align16 1Q };
6 cmp.g.f0.0(8) null<1>UD g17<4>.xUD 0x00000000UD { align16 1Q };
7 cmp.ge.f0.0(8) null<1>UD g18<4>.xUD g17<4>.xUD { align16 1Q };
8 cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q };
9 cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H };
10 cmp.z.f0.0(8) null<1>UD g9<4>.xUD 0x00000000UD { align16 1Q };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen7/ |
| D | cmp.asm | 1 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
2 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
3 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
4 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
5 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
6 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
7 cmp.z.f0.0(8) null<1>D g13<4>.xyyyD g6<0>.yzzzD { align16 1Q switch };
8 cmp.ge.f0.0(8) g33<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
9 cmp.l.f0.0(8) g34<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
10 cmp.ge.f0.0(8) g2<1>F g23<8,8,1>F g51<0,1,0>F { align1 1Q };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen7.5/ |
| D | cmp.asm | 1 cmp.z.f0.0(8) g7<1>D g6<8,8,1>D g2.5<0,1,0>D { align1 1Q };
2 cmp.z.f0.0(16) g11<1>D g9<8,8,1>D g2.5<0,1,0>D { align1 1H };
3 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
4 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
5 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
6 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
7 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
8 cmp.ge.f0.0(8) g15<1>D (abs)g14<4>D 1D { align16 1Q };
9 cmp.ge.f0.0(8) g16<1>F g15<4>F 0x3f800000F /* 1F */ { align16 1Q };
10 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Sparc/ |
| D | sparc-fp.txt | 4 # CHECK: fitos %f0, %f4
7 # CHECK: fitod %f0, %f4
10 # CHECK: fitoq %f0, %f4
13 # CHECK: fstoi %f0, %f4
16 # CHECK: fdtoi %f0, %f4
19 # CHECK: fqtoi %f0, %f4
22 # CHECK: fstod %f0, %f4
24 # CHECK: fstoq %f0, %f4
27 # CHECK: fdtos %f0, %f4
30 # CHECK: fdtoq %f0, %f4
[all …]
|
| /external/llvm/test/MC/Disassembler/Sparc/ |
| D | sparc-fp.txt | 4 # CHECK: fitos %f0, %f4
7 # CHECK: fitod %f0, %f4
10 # CHECK: fitoq %f0, %f4
13 # CHECK: fstoi %f0, %f4
16 # CHECK: fdtoi %f0, %f4
19 # CHECK: fqtoi %f0, %f4
22 # CHECK: fstod %f0, %f4
24 # CHECK: fstoq %f0, %f4
27 # CHECK: fdtos %f0, %f4
30 # CHECK: fdtoq %f0, %f4
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen4.5/ |
| D | cmp.asm | 1 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
2 cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
6 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
8 cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
9 cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
10 cmp.z.f0.0(8) null<1>F g3<0>.zwwwF g3<0>.xyyyF { align16 };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen4/ |
| D | cmp.asm | 1 cmp.l.f0.0(8) null<1>F g8<4>.wF 0x0F /* 0F */ { align16 };
2 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
3 cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
4 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
6 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
8 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
9 cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
10 cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen5/ |
| D | cmp.asm | 1 cmp.ge.f0.0(8) null<1>D g12<8,8,1>D 16D { align1 };
2 cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr };
3 cmp.ge.f0.0(8) null<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 };
4 cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
5 cmp.ge.f0.0(8) null<1>F g5<4>.xF 0x0F /* 0F */ { align16 };
6 cmp.l.f0.0(8) null<1>F g5<4>.wF 0x43000000F /* 128F */ { align16 };
7 cmp.le.f0.0(8) g5<1>.xF g5<4>.xF 0x0F /* 0F */ { align16 };
8 cmp.nz.f0.0(8) null<1>.zD -g5<4>.xD 0D { align16 };
9 cmp.ge.f0.0(8) g6<1>F g4<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 };
10 cmp.ge.f0.0(16) g12<1>F g8<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 compr };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen9/ |
| D | cmp.asm | 1 cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q };
2 cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q };
3 cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q };
4 cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q };
5 cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q };
6 cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H };
7 cmp.l.f0.0(16) g28<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H };
8 cmp.ge.f0.0(16) g30<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H };
9 cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q };
10 cmp.z.f0.0(8) g86<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
[all …]
|
| /external/mesa3d/src/intel/tools/tests/gen8/ |
| D | cmp.asm | 1 cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q };
2 cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q };
3 cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q };
4 cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q };
5 cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q };
6 cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H };
7 cmp.l.f0.0(16) g35<1>F g33<8,8,1>F g31<8,8,1>F { align1 1H };
8 cmp.ge.f0.0(16) g37<1>F g33<8,8,1>F g31<8,8,1>F { align1 1H };
9 cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q };
10 cmp.z.f0.0(8) g32<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select-dbl.ll | 41 ; M2-NEXT: ldc1 $f0, 16($sp)
45 ; M2-NEXT: mtc1 $7, $f0
54 ; CMOV32R1-NEXT: ldc1 $f0, 16($sp)
56 ; CMOV32R1-NEXT: movn.d $f0, $f2, $1
63 ; CMOV32R2-NEXT: ldc1 $f0, 16($sp)
65 ; CMOV32R2-NEXT: movn.d $f0, $f2, $1
71 ; 32R6-NEXT: mtc1 $4, $f0
74 ; 32R6-NEXT: sel.d $f0, $f2, $f1
80 ; M3-NEXT: mov.d $f0, $f13
82 ; M3-NEXT: mov.d $f0, $f14
[all …]
|
| D | select-flt.ll | 41 ; M2-NEXT: mtc1 $6, $f0
44 ; M2-NEXT: mtc1 $5, $f0
48 ; CMOV32R1-NEXT: mtc1 $6, $f0
52 ; CMOV32R1-NEXT: movn.s $f0, $f1, $1
56 ; CMOV32R2-NEXT: mtc1 $6, $f0
60 ; CMOV32R2-NEXT: movn.s $f0, $f1, $1
66 ; 32R6-NEXT: mtc1 $4, $f0
68 ; 32R6-NEXT: sel.s $f0, $f2, $f1
74 ; M3-NEXT: mov.s $f0, $f13
76 ; M3-NEXT: mov.s $f0, $f14
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/SystemZ/ |
| D | insns-z14.txt | 1886 # CHECK: wfasb %f0, %f0, %f0
1889 # CHECK: wfasb %f0, %f0, %f0
1892 # CHECK: wfasb %f0, %f0, %v31
1895 # CHECK: wfasb %f0, %v31, %f0
1898 # CHECK: wfasb %v31, %f0, %f0
1919 # CHECK: wfcsb %f0, %f0
1922 # CHECK: wfcsb %f0, %f0
1925 # CHECK: wfcsb %f0, %f15
1928 # CHECK: wfcsb %f0, %v31
1931 # CHECK: wfcsb %f15, %f0
[all …]
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/math/ |
| D | fpu_asm.S | 12 lfd f0,0(r4)
13 fcmpu cr1,f0,f14
15 lfd f0,8(r4)
16 fcmpu cr1,f0,f15
18 lfd f0,16(r4)
19 fcmpu cr1,f0,f16
21 lfd f0,24(r4)
22 fcmpu cr1,f0,f17
24 lfd f0,32(r4)
25 fcmpu cr1,f0,f18
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | scalar_cmp.ll | 23 ; FAST-P8-NEXT: xssubsp f0, f1, f2
25 ; FAST-P8-NEXT: fsel f0, f0, f3, f4
26 ; FAST-P8-NEXT: fsel f1, f1, f0, f4
31 ; FAST-P9-NEXT: xssubsp f0, f2, f1
34 ; FAST-P9-NEXT: fsel f1, f0, f1, f4
64 ; FAST-P8-NEXT: xssubdp f0, f1, f2
65 ; FAST-P8-NEXT: xsnegdp f1, f0
66 ; FAST-P8-NEXT: fsel f0, f0, f3, f4
67 ; FAST-P8-NEXT: fsel f1, f1, f0, f4
72 ; FAST-P9-NEXT: xssubdp f0, f1, f2
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | select.ll | 12 define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone…
52 %cond = select i1 %tobool, i32 %f1, i32 %f0
60 define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
114 %cond = select i1 %tobool, i64 %f1, i64 %f0
118 define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
174 %cond = select i1 %tobool, i64 %f1, i64 %f0
178 define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone {
181 ; 32-NEXT: mtc1 $6, $f0
184 ; 32-NEXT: movn.s $f0, $f1, $4
188 ; 32R2-NEXT: mtc1 $6, $f0
[all …]
|