| /external/rust/crates/ahash/smhasher/ |
| D | ahashOutput.txt | 87 Testing collisions (high 32-bit) - Expected 0.3, actual 1 (3.35x) (1) !
88 Testing collisions (high 19-25 bits) - Worst is 24 bits: 90/76 (1.18x)
89 Testing collisions (high 12-bit) - Expected 46547.0, actual 46547 (1.00x)
90 Testing collisions (high 8-bit) - Expected 50387.0, actual 50387 (1.00x)
99 Testing collisions (high 32-bit) - Expected 188.2, actual 174 (0.92x)
100 Testing collisions (high 24-35 bits) - Worst is 26 bits: 12182/12047 (1.01x)
101 Testing collisions (high 12-bit) - Expected 1267530.0, actual 1267530 (1.00x)
102 Testing collisions (high 8-bit) - Expected 1271370.0, actual 1271370 (1.00x)
111 Testing collisions (high 32-bit) - Expected 2373.0, actual 2366 (1.00x) (-7)
112 Testing collisions (high 25-38 bits) - Worst is 30 bits: 9627/9492 (1.01x)
[all …]
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| D | fallbackOutput.txt | 87 Testing collisions (high 32-bit) - Expected 0.6, actual 0 (0.00x)
88 Testing collisions (high 19-26 bits) - Worst is 22 bits: 320/611 (0.52x)
89 Testing collisions (high 12-bit) - Expected 50643.0, actual 46547 (0.92x)
90 Testing collisions (high 8-bit) - Expected 50643.0, actual 50387 (0.99x) (-256)
99 Testing collisions (high 32-bit) - Expected 376.5, actual 180 (0.48x)
100 Testing collisions (high 24-36 bits) - Worst is 35 bits: 26/47 (0.55x)
101 Testing collisions (high 12-bit) - Expected 1271626.0, actual 1267530 (1.00x) (-4096)
102 Testing collisions (high 8-bit) - Expected 1271626.0, actual 1271370 (1.00x) (-256)
111 Testing collisions (high 32-bit) - Expected 4746.0, actual 2412 (0.51x)
112 Testing collisions (high 26-39 bits) - Worst is 39 bits: 24/37 (0.65x)
[all …]
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| /external/clang/test/CodeGen/ |
| D | aarch64-neon-vcombine.c | 7 // CHECK-LABEL: define <16 x i8> @test_vcombine_s8(<8 x i8> %low, <8 x i8> %high) #0 {
8 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> <i32 0, i32…
10 int8x16_t test_vcombine_s8(int8x8_t low, int8x8_t high) { in test_vcombine_s8() argument
11 return vcombine_s8(low, high); in test_vcombine_s8()
14 // CHECK-LABEL: define <8 x i16> @test_vcombine_s16(<4 x i16> %low, <4 x i16> %high) #0 {
15 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i3…
17 int16x8_t test_vcombine_s16(int16x4_t low, int16x4_t high) { in test_vcombine_s16() argument
18 return vcombine_s16(low, high); in test_vcombine_s16()
21 // CHECK-LABEL: define <4 x i32> @test_vcombine_s32(<2 x i32> %low, <2 x i32> %high) #0 {
22 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> <i32 0, i3…
[all …]
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| /external/llvm-project/clang/test/CodeGen/ |
| D | aarch64-neon-vcombine.c | 7 // CHECK-LABEL: define <16 x i8> @test_vcombine_s8(<8 x i8> %low, <8 x i8> %high) #0 {
8 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> <i32 0, i32…
10 int8x16_t test_vcombine_s8(int8x8_t low, int8x8_t high) { in test_vcombine_s8() argument
11 return vcombine_s8(low, high); in test_vcombine_s8()
14 // CHECK-LABEL: define <8 x i16> @test_vcombine_s16(<4 x i16> %low, <4 x i16> %high) #0 {
15 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i3…
17 int16x8_t test_vcombine_s16(int16x4_t low, int16x4_t high) { in test_vcombine_s16() argument
18 return vcombine_s16(low, high); in test_vcombine_s16()
21 // CHECK-LABEL: define <4 x i32> @test_vcombine_s32(<2 x i32> %low, <2 x i32> %high) #0 {
22 // CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> <i32 0, i3…
[all …]
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| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| D | TensorUInt128.h | 31 template <typename HIGH = uint64_t, typename LOW = uint64_t>
34 HIGH high; member
39 …TensorUInt128(const TensorUInt128<OTHER_HIGH, OTHER_LOW>& other) : high(other.high), low(other.low… in TensorUInt128()
40 EIGEN_STATIC_ASSERT(sizeof(OTHER_HIGH) <= sizeof(HIGH), YOU_MADE_A_PROGRAMMING_MISTAKE); in TensorUInt128()
47 EIGEN_STATIC_ASSERT(sizeof(OTHER_HIGH) <= sizeof(HIGH), YOU_MADE_A_PROGRAMMING_MISTAKE);
49 high = other.high;
56 explicit TensorUInt128(const T& x) : high(0), low(x) { in TensorUInt128()
62 TensorUInt128(HIGH y, LOW x) : high(y), low(x) { } in TensorUInt128()
70 EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE HIGH upper() const { in upper()
71 return high; in upper()
[all …]
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| /external/compiler-rt/lib/builtins/ |
| D | udivmoddi4.c | 36 if (n.s.high == 0) in __udivmoddi4()
38 if (d.s.high == 0) in __udivmoddi4()
56 /* n.s.high != 0 */ in __udivmoddi4()
59 if (d.s.high == 0) in __udivmoddi4()
66 *rem = n.s.high % d.s.low; in __udivmoddi4()
67 return n.s.high / d.s.low; in __udivmoddi4()
69 /* d.s.high != 0 */ in __udivmoddi4()
78 r.s.high = n.s.high % d.s.high; in __udivmoddi4()
82 return n.s.high / d.s.high; in __udivmoddi4()
88 if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ in __udivmoddi4()
[all …]
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| D | udivmodti4.c | 38 if (n.s.high == 0) in __udivmodti4()
40 if (d.s.high == 0) in __udivmodti4()
58 /* n.s.high != 0 */ in __udivmodti4()
61 if (d.s.high == 0) in __udivmodti4()
68 *rem = n.s.high % d.s.low; in __udivmodti4()
69 return n.s.high / d.s.low; in __udivmodti4()
71 /* d.s.high != 0 */ in __udivmodti4()
80 r.s.high = n.s.high % d.s.high; in __udivmodti4()
84 return n.s.high / d.s.high; in __udivmodti4()
90 if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ in __udivmodti4()
[all …]
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| /external/llvm-project/compiler-rt/lib/builtins/ |
| D | udivmoddi4.c | 38 if (n.s.high == 0) { in __udivmoddi4()
39 if (d.s.high == 0) { in __udivmoddi4()
54 // n.s.high != 0 in __udivmoddi4()
56 if (d.s.high == 0) { in __udivmoddi4()
61 *rem = n.s.high % d.s.low; in __udivmoddi4()
62 return n.s.high / d.s.low; in __udivmoddi4()
64 // d.s.high != 0 in __udivmoddi4()
70 r.s.high = n.s.high % d.s.high; in __udivmoddi4()
74 return n.s.high / d.s.high; in __udivmoddi4()
79 if ((d.s.high & (d.s.high - 1)) == 0) /* if d is a power of 2 */ { in __udivmoddi4()
[all …]
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| /external/mesa3d/src/freedreno/registers/mdp/ |
| D | mdp5.xml | 14 <bitfield name="STEP" low="0" high="15" type="uint"/>
15 <bitfield name="MINOR" low="16" high="27" type="uint"/>
16 <bitfield name="MAJOR" low="28" high="31" type="uint"/>
142 <bitfield name="CLIENT0" low="0" high="7" type="uint"/>
143 <bitfield name="CLIENT1" low="8" high="15" type="uint"/>
144 <bitfield name="CLIENT2" low="16" high="23" type="uint"/>
148 <bitfield name="STEP" low="0" high="15" type="uint"/>
149 <bitfield name="MINOR" low="16" high="27" type="uint"/>
150 <bitfield name="MAJOR" low="28" high="31" type="uint"/>
154 <bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
[all …]
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| /external/selinux/libsepol/src/ |
| D | port_record.c | 9 /* Low - High range. Same for single ports. */
10 int low, high; member
20 /* Low - High range. Same for single ports. */
21 int low, high; member
29 int low, int high, int proto, in sepol_port_key_create() argument
42 tmp_key->high = high; in sepol_port_key_create()
52 int *low, int *high, int *proto) in hidden_def()
56 *high = key->high; in hidden_def()
68 (handle, port->low, port->high, port->proto, key_ptr) < 0) { in hidden_def()
72 port->low, port->high); in hidden_def()
[all …]
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| D | ibpkey_record.c | 16 /* Low - High range. Same for single ibpkeys. */
17 int low, high; member
27 /* Low - High range. Same for single ibpkeys. */
28 int low, high; member
101 int low, int high, in sepol_ibpkey_key_create() argument
116 tmp_key->high = high; in sepol_ibpkey_key_create()
127 subnet_prefix, low, high); in sepol_ibpkey_key_create()
134 uint64_t *subnet_prefix, int *low, int *high) in hidden_def()
138 *high = key->high; in hidden_def()
152 (handle, subnet_prefix_str, ibpkey->low, ibpkey->high, key_ptr) < 0) { in hidden_def()
[all …]
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| /external/llvm-project/llvm/test/Transforms/ConstraintElimination/ |
| D | sub-nuw.ll | 4 define void @test.not.uge.ult(i8 %start, i8 %low, i8 %high) {
8 ; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[SUB_PTR_I]], [[HIGH:%.*]]
13 ; CHECK-NEXT: [[T_0:%.*]] = icmp ult i8 [[START]], [[HIGH]]
16 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[START_1]], [[HIGH]]
19 ; CHECK-NEXT: [[T_2:%.*]] = icmp ult i8 [[START_2]], [[HIGH]]
22 ; CHECK-NEXT: [[T_3:%.*]] = icmp ult i8 [[START_3]], [[HIGH]]
25 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]]
31 %c.1 = icmp uge i8 %sub.ptr.i, %high
38 %t.0 = icmp ult i8 %start, %high
41 %t.1 = icmp ult i8 %start.1, %high
[all …]
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| D | sub.ll | 4 define void @test.not.uge.ult(i8 %start, i8 %low, i8 %high) {
8 ; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[SUB_PTR_I]], [[HIGH:%.*]]
13 ; CHECK-NEXT: [[T_0:%.*]] = icmp ult i8 [[START]], [[HIGH]]
16 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[START_1]], [[HIGH]]
19 ; CHECK-NEXT: [[T_2:%.*]] = icmp ult i8 [[START_2]], [[HIGH]]
22 ; CHECK-NEXT: [[T_3:%.*]] = icmp ult i8 [[START_3]], [[HIGH]]
25 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]]
31 %c.1 = icmp uge i8 %sub.ptr.i, %high
38 %t.0 = icmp ult i8 %start, %high
41 %t.1 = icmp ult i8 %start.1, %high
[all …]
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| D | add.ll | 4 define void @test.not.uge.ult(i8 %start, i8 %low, i8 %high) {
8 ; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[ADD_PTR_I]], [[HIGH:%.*]]
13 ; CHECK-NEXT: [[T_0:%.*]] = icmp ult i8 [[START]], [[HIGH]]
16 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[START_1]], [[HIGH]]
19 ; CHECK-NEXT: [[T_2:%.*]] = icmp ult i8 [[START_2]], [[HIGH]]
22 ; CHECK-NEXT: [[T_3:%.*]] = icmp ult i8 [[START_3]], [[HIGH]]
25 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]]
31 %c.1 = icmp uge i8 %add.ptr.i, %high
38 %t.0 = icmp ult i8 %start, %high
41 %t.1 = icmp ult i8 %start.1, %high
[all …]
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| D | add-nuw.ll | 4 define void @test.not.uge.ult(i8 %start, i8 %low, i8 %high) {
8 ; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[ADD_PTR_I]], [[HIGH:%.*]]
13 ; CHECK-NEXT: [[T_0:%.*]] = icmp ult i8 [[START]], [[HIGH]]
16 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[START_1]], [[HIGH]]
19 ; CHECK-NEXT: [[T_2:%.*]] = icmp ult i8 [[START_2]], [[HIGH]]
22 ; CHECK-NEXT: [[T_3:%.*]] = icmp ult i8 [[START_3]], [[HIGH]]
25 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8 [[START_4]], [[HIGH]]
31 %c.1 = icmp uge i8 %add.ptr.i, %high
38 %t.0 = icmp ult i8 %start, %high
41 %t.1 = icmp ult i8 %start.1, %high
[all …]
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| /external/ltp/testcases/open_posix_testsuite/Documentation/ |
| D | COVERAGE.threads | 21 pthread_attr_destroy YES HIGH
22 pthread_attr_getdetachstate YES HIGH
23 pthread_attr_init YES HIGH
24 pthread_attr_setdetachstate YES HIGH
25 pthread_cancel YES HIGH
36 pthread_create YES HIGH
37 pthread_detach YES HIGH
38 pthread_equal YES HIGH
39 pthread_exit YES HIGH
40 pthread_join YES HIGH
[all …]
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| /external/mesa3d/src/freedreno/registers/adreno/ |
| D | a3xx.xml | 799 <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
802 <bitfield name="HORZ" low="0" high="9" type="uint"/>
803 <bitfield name="VERT" low="10" high="19" type="uint"/>
812 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
813 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
817 <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
827 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
832 <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
833 <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
834 <bitfield name="RASTER_MODE" low="12" high="15"/>
[all …]
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| D | adreno_pm4.xml | 272 <doc>load high level sequencer command</doc>
513 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
514 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
515 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
516 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
519 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
520 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
593 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
594 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
595 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
[all …]
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| D | a6xx.xml | 176 <bitfield name="BASE_ADDR" low="0" high="17"/>
177 <bitfield name="MASK_LEN" low="18" high="30"/>
871 8b unorm: 10 (sometimes 0, is the high bit part of something else?)
990 and b8..15 is a high threshold?
996 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
997 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
998 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
999 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
1013 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
1015 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
[all …]
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| D | a4xx.xml | 879 <bitfield name="WIDTH" low="0" high="13" type="uint"/>
880 <bitfield name="HEIGHT" low="16" high="29" type="uint"/>
893 <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
894 <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
905 <bitfield name="SAMPLES" low="13" high="15" type="uint"/>
908 <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
912 <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
929 <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
930 <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
933 <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
[all …]
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| /external/icu/icu4c/source/data/translit/ |
| D | my_my_FONIPA.txt | 44 $high = \u0301;
46 $coda = [$creaky $high $low ɴ ʔ ə]; # TODO: remove if unused
76 ၎င\u103Aး → lə\.ɡa $high ʊ\u032Fɴ;
84 င\u103Aး → ɪ $high ɴ;
88 ဉ\u103Aး → ɪ $high ɴ;
91 ည\u103Aး → ɛ $high;
94 ဏ\u103Aး → a $high ɴ;
98 န\u103Aး → a $high ɴ;
102 မ\u103Aး → a $high ɴ;
105 ယ\u103Aး → ɛ $high;
[all …]
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| /external/cldr/common/transforms/ |
| D | my-my_FONIPA.xml | 53 $high = \u0301;
55 $coda = [$creaky $high $low ɴ ʔ ə]; # TODO: remove if unused
95 ၎င်း → lə\.ɡa $high ʊ̯ɴ;
108 င်း → ɪ $high ɴ;
114 ဉ်း → ɪ $high ɴ;
118 ည်း → ɛ $high;
122 ဏ်း → a $high ɴ;
128 န်း → a $high ɴ;
134 မ်း → a $high ɴ;
138 ယ်း → ɛ $high;
[all …]
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| /external/tensorflow/tensorflow/python/ops/distributions/ |
| D | uniform.py | 38 """Uniform distribution with `low` and `high` parameters.
52 - `high = b`,
57 The parameters `low` and `high` must be shaped in a way that supports
58 broadcasting (e.g., `high - low` is a valid operation).
64 u1 = Uniform(low=3.0, high=4.0) # a single uniform distribution [3, 4]
66 high=[3.0, 4.0]) # 2 distributions [1, 3], [2, 4]
69 high=[[1.5, 2.5],
75 u1 = Uniform(low=3.0, high=[5.0, 6.0, 7.0]) # 3 distributions
90 high=1., argument
98 have `low < high`.
[all …]
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-10.ll | 1 ; Test signed high-part i64->i128 multiplications on z14.
7 ; Check sign-extended multiplication in which only the high part is used.
17 %high = trunc i128 %highx to i64
18 ret i64 %high
21 ; Check sign-extended multiplication in which only part of the high half
33 %high = trunc i128 %highx to i64
34 ret i64 %high
38 ; high and low halves.
49 %high = trunc i128 %highx to i64
51 %or = or i64 %high, %low
[all …]
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| /external/rust/crates/rand/src/distributions/ |
| D | uniform.rs | 53 //! `low < high`). The example below merely wraps another back-end.
73 //! fn new<B1, B2>(low: B1, high: B2) -> Self
77 //! UniformMyF32(UniformFloat::<f32>::new(low.borrow().0, high.borrow().0))
79 //! fn new_inclusive<B1, B2>(low: B1, high: B2) -> Self
83 //! UniformSampler::new(low, high)
94 //! let (low, high) = (MyF32(17.0f32), MyF32(22.0f32));
95 //! let uniform = Uniform::new(low, high);
139 /// values. Further, the implementations here give more weight to the high-bits
141 /// are of lower quality than the high bits.
143 /// Implementations must sample in `[low, high)` range for
[all …]
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