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/external/llvm-project/llvm/test/MC/ARM/
Dfullfp16-neon-neg.s1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileC…
2 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileC…
3 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | Fil…
4 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | Fil…
8 @ CHECK: instruction requires: {{full half-float|NEON}}
9 @ CHECK: instruction requires: {{full half-float|NEON}}
13 @ CHECK: instruction requires: {{full half-float|NEON}}
14 @ CHECK: instruction requires: {{full half-float|NEON}}
18 @ CHECK: instruction requires: {{full half-float|NEON}}
19 @ CHECK: instruction requires: {{full half-float|NEON}}
[all …]
Darmv8a-fpmul.s1 // RUN: llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-prefix…
2 // RUN: llvm-mc -triple thumb -mattr=+fp16fml,+neon -show-encoding < %s | FileCheck %s --check-pref…
3 // RUN: llvm-mc -triple arm -mattr=-fullfp16,+fp16fml,+neon -show-encoding < %s | FileCheck %s --ch…
4 // RUN: llvm-mc -triple thumb -mattr=-fullfp16,+fp16fml,+neon -show-encoding < %s | FileCheck %s --…
7 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML-NOR-NEON < %t %s
9 // RUN: FileCheck --check-prefix=CHECK-NO-FP16FML-NOR-NEON < %t %s
11 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon -show-encoding < %s 2> %t
13 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon -show-encoding < %s 2> %t
16 // RUN: not llvm-mc -triple arm -mattr=+v8.2a,+neon,+fp16fml,-fp16fml -show-encoding < %s 2> %t
18 // RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+neon,+fp16fml,-fp16fml -show-encoding < %s 2> %t
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsARM.h164 arm_neon_aesd, // llvm.arm.neon.aesd
165 arm_neon_aese, // llvm.arm.neon.aese
166 arm_neon_aesimc, // llvm.arm.neon.aesimc
167 arm_neon_aesmc, // llvm.arm.neon.aesmc
168 arm_neon_sdot, // llvm.arm.neon.sdot
169 arm_neon_sha1c, // llvm.arm.neon.sha1c
170 arm_neon_sha1h, // llvm.arm.neon.sha1h
171 arm_neon_sha1m, // llvm.arm.neon.sha1m
172 arm_neon_sha1p, // llvm.arm.neon.sha1p
173 arm_neon_sha1su0, // llvm.arm.neon.sha1su0
[all …]
DIntrinsicsAArch64.h56 aarch64_neon_abs, // llvm.aarch64.neon.abs
57 aarch64_neon_addhn, // llvm.aarch64.neon.addhn
58 aarch64_neon_addp, // llvm.aarch64.neon.addp
59 aarch64_neon_cls, // llvm.aarch64.neon.cls
60 aarch64_neon_fabd, // llvm.aarch64.neon.fabd
61 aarch64_neon_facge, // llvm.aarch64.neon.facge
62 aarch64_neon_facgt, // llvm.aarch64.neon.facgt
63 aarch64_neon_faddp, // llvm.aarch64.neon.faddp
64 aarch64_neon_faddv, // llvm.aarch64.neon.faddv
65 aarch64_neon_fcvtas, // llvm.aarch64.neon.fcvtas
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darmv8a-fpmul.s6 …ne-linux-gnu -show-encoding -mattr=+v8.2a,-neon,+fp16fml < %s 2>&1 | FileCheck %s --check-prefix=C…
7 …-linux-gnu -show-encoding -mattr=+v8.2a,-neon < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-FP1…
40 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
41 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
42 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
43 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
44 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
45 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
46 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
47 //CHECK-NO-NEON: error: instruction requires: neon{{$}}
[all …]
/external/llvm-project/llvm/test/Transforms/InterleavedAccess/AArch64/
Dinterleaved-accesses.ll1 ; RUN: opt < %s -interleaved-access -S | FileCheck %s -check-prefix=NEON
2 ; RUN: opt < %s -mattr=-neon -interleaved-access -S | FileCheck %s -check-prefix=NO_NEON
8 ; NEON-LABEL: @load_factor2(
9 ; NEON-NEXT: [[TMP1:%.*]] = bitcast <16 x i8>* %ptr to <8 x i8>*
10 ; NEON-NEXT: [[LDN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 …
11 ; NEON-NEXT: [[TMP2:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 1
12 ; NEON-NEXT: [[TMP3:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[LDN]], 0
13 ; NEON-NEXT: ret void
15 ; NO_NEON-NOT: @llvm.aarch64.neon
25 ; NEON-LABEL: @load_factor3(
[all …]
/external/vixl/test/test-trace-reference/
Dlog-cpufeatures322 0x~~~~~~~~~~~~~~~~ 7ef3d44d fabd d13, d2, d19 // Needs: FP, NEON
323 0x~~~~~~~~~~~~~~~~ 7ebed548 fabd s8, s10, s30 // Needs: FP, NEON
326 0x~~~~~~~~~~~~~~~~ 7e70eee1 facge d1, d23, d16 // Needs: FP, NEON
327 0x~~~~~~~~~~~~~~~~ 7e21ee24 facge s4, s17, s1 // Needs: FP, NEON
328 0x~~~~~~~~~~~~~~~~ 7ef8eea2 facgt d2, d21, d24 // Needs: FP, NEON
329 0x~~~~~~~~~~~~~~~~ 7eacef4c facgt s12, s26, s12 // Needs: FP, NEON
336 0x~~~~~~~~~~~~~~~~ 5e6ae513 fcmeq d19, d8, d10 // Needs: FP, NEON
337 0x~~~~~~~~~~~~~~~~ 5ee0da40 fcmeq d0, d18, #0.0 // Needs: FP, NEON
338 0x~~~~~~~~~~~~~~~~ 5e3ee481 fcmeq s1, s4, s30 // Needs: FP, NEON
339 0x~~~~~~~~~~~~~~~~ 5ea0dbb6 fcmeq s22, s29, #0.0 // Needs: FP, NEON
[all …]
Dlog-cpufeatures-custom322 0x~~~~~~~~~~~~~~~~ 7ef3d44d fabd d13, d2, d19 ### {FP, NEON} ###
323 0x~~~~~~~~~~~~~~~~ 7ebed548 fabd s8, s10, s30 ### {FP, NEON} ###
326 0x~~~~~~~~~~~~~~~~ 7e70eee1 facge d1, d23, d16 ### {FP, NEON} ###
327 0x~~~~~~~~~~~~~~~~ 7e21ee24 facge s4, s17, s1 ### {FP, NEON} ###
328 0x~~~~~~~~~~~~~~~~ 7ef8eea2 facgt d2, d21, d24 ### {FP, NEON} ###
329 0x~~~~~~~~~~~~~~~~ 7eacef4c facgt s12, s26, s12 ### {FP, NEON} ###
336 0x~~~~~~~~~~~~~~~~ 5e6ae513 fcmeq d19, d8, d10 ### {FP, NEON} ###
337 0x~~~~~~~~~~~~~~~~ 5ee0da40 fcmeq d0, d18, #0.0 ### {FP, NEON} ###
338 0x~~~~~~~~~~~~~~~~ 5e3ee481 fcmeq s1, s4, s30 ### {FP, NEON} ###
339 0x~~~~~~~~~~~~~~~~ 5ea0dbb6 fcmeq s22, s29, #0.0 ### {FP, NEON} ###
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
23 ; NEON: f
24 ; NEON: push {r4, r7, lr}
25 ; NEON: sub.w r4, sp, #64
26 ; NEON: bfc r4, #0, #4
28 ; NEON: mov sp, r4
29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128]
36 ; NEON: sub sp, #16
[all …]
/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
23 ; NEON: f
24 ; NEON: push {r4, r7, lr}
25 ; NEON: sub.w r4, sp, #64
26 ; NEON: bfc r4, #0, #4
28 ; NEON: mov sp, r4
29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128]
36 ; NEON: sub sp, #16
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
[all …]
Darm64-neon-across.ll1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
[all …]
Darm64-vsqrt.ll1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone
41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
[all …]
Darm64-neon-across.ll1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
[all …]
Dfp16_intrinsic_scalar_1op.ll3 declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half)
4 declare i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half)
5 declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half)
6 declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half)
7 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half)
8 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half)
9 declare i64 @llvm.aarch64.neon.fcvtns.i64.f16(half)
10 declare i32 @llvm.aarch64.neon.fcvtns.i32.f16(half)
11 declare i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half)
12 declare i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half)
[all …]
Darm64-vsqrt.ll1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfunnel-shift-rot.ll3 …RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,NE…
98 ; NEON-LABEL: rotl_i64:
99 ; NEON: @ %bb.0:
100 ; NEON-NEXT: .save {r4, r5, r11, lr}
101 ; NEON-NEXT: push {r4, r5, r11, lr}
102 ; NEON-NEXT: and r12, r2, #63
103 ; NEON-NEXT: rsb r2, r2, #0
104 ; NEON-NEXT: rsb r3, r12, #32
105 ; NEON-NEXT: and r4, r2, #63
106 ; NEON-NEXT: subs lr, r12, #32
[all …]
Dmisched-fusion-aes.ll3 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
4 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
5 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
6 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
17 %e00 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d0, <16 x i8> %k0)
18 %f00 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e00)
19 %e01 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d1, <16 x i8> %k0)
20 %f01 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e01)
21 %e02 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d2, <16 x i8> %k0)
22 %f02 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %e02)
[all …]
/external/XNNPACK/scripts/
Dgenerate-qs8-igemm.sh17 ################################### ARM NEON ##################################
18 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=1 -D NR=8 -o src/qs8-igemm/gen/1x8-minmax-neon-…
19 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=2 -D NR=8 -o src/qs8-igemm/gen/2x8-minmax-neon-…
20 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=3 -D NR=8 -o src/qs8-igemm/gen/3x8-minmax-neon-…
21 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=4 -D NR=8 -o src/qs8-igemm/gen/4x8-minmax-neon-…
23 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=1 -D NR=16 -o src/qs8-igemm/gen/1x16-minmax-neo…
24 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=2 -D NR=16 -o src/qs8-igemm/gen/2x16-minmax-neo…
25 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=3 -D NR=16 -o src/qs8-igemm/gen/3x16-minmax-neo…
26 tools/xngen src/qs8-igemm/neon-mlal-lane.c.in -D MR=4 -D NR=16 -o src/qs8-igemm/gen/4x16-minmax-neo…
28 tools/xngen src/qs8-igemm/neon-mull-addw-dup.c.in -D MR=1 -D NR=8 -o src/qs8-igemm/gen/1x8-minmax-n…
[all …]
Dgenerate-qs8-gemm.sh21 ################################### ARM NEON ##################################
22 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=1 -D NR=8 -o src/qs8-gemm/gen/1x8-minmax-neon-ml…
23 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=2 -D NR=8 -o src/qs8-gemm/gen/2x8-minmax-neon-ml…
24 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=3 -D NR=8 -o src/qs8-gemm/gen/3x8-minmax-neon-ml…
25 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=4 -D NR=8 -o src/qs8-gemm/gen/4x8-minmax-neon-ml…
27 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=1 -D NR=16 -o src/qs8-gemm/gen/1x16-minmax-neon-…
28 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=2 -D NR=16 -o src/qs8-gemm/gen/2x16-minmax-neon-…
29 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=3 -D NR=16 -o src/qs8-gemm/gen/3x16-minmax-neon-…
30 tools/xngen src/qs8-gemm/neon-mlal-lane.c.in -D MR=4 -D NR=16 -o src/qs8-gemm/gen/4x16-minmax-neon-…
32 tools/xngen src/qs8-gemm/neon-mull-addw-dup.c.in -D MR=1 -D NR=8 -o src/qs8-gemm/gen/1x8-minmax-neo…
[all …]
/external/libvpx/libvpx/vpx_dsp/
Dvpx_dsp_rtcd_defs.pl44 specialize qw/vpx_d45_predictor_4x4 neon sse2/;
55 specialize qw/vpx_h_predictor_4x4 neon dspr2 msa sse2/;
62 specialize qw/vpx_d135_predictor_4x4 neon/;
68 specialize qw/vpx_v_predictor_4x4 neon msa sse2/;
74 specialize qw/vpx_tm_predictor_4x4 neon dspr2 msa sse2/;
77 specialize qw/vpx_dc_predictor_4x4 dspr2 msa neon sse2/;
80 specialize qw/vpx_dc_top_predictor_4x4 msa neon sse2/;
83 specialize qw/vpx_dc_left_predictor_4x4 msa neon sse2/;
86 specialize qw/vpx_dc_128_predictor_4x4 msa neon sse2/;
93 specialize qw/vpx_d45_predictor_8x8 neon sse2/;
[all …]
/external/llvm/test/MC/ARM/
Dvfp-aliases-diagnostics.s34 @ CHECK: error: VFP/Neon double precision register expected
37 @ CHECK: error: VFP/Neon double precision register expected
40 @ CHECK: error: VFP/Neon double precision register expected
43 @ CHECK: error: VFP/Neon double precision register expected
46 @ CHECK: error: VFP/Neon single precision register expected
49 @ CHECK: error: VFP/Neon single precision register expected
52 @ CHECK: error: VFP/Neon single precision register expected
55 @ CHECK: error: VFP/Neon single precision register expected
59 @ CHECK: error: VFP/Neon single precision register expected
62 @ CHECK: error: VFP/Neon single precision register expected
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/external/chromium-trace/catapult/third_party/polymer/components/neon-animation/guides/
Dneon-animation.md2 title: neon-animation
3 summary: "A short guide to neon-animation and neon-animated-pages"
5 elements: ['neon-animation','neon-animated-pages']
9 # neon-animation
11 `neon-animation` is a suite of elements and behaviors to implement pluggable animated transitions f…
42 // provided by neon-animation/animations/scale-down-animation.html
51 'neon-animation-finish': '_onNeonAnimationFinish'
63 [Live demo](http://morethanreal.github.io/neon-animation-demo/bower_components/neon-animation/demo/…
87 // provided by neon-animation/animations/scale-up-animation.html
92 // provided by neon-animation-animations/fade-out-animation.html
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/external/llvm-project/llvm/test/Transforms/CodeGenPrepare/ARM/
Dsink-free-instructions.ll2 ; RUN: opt -mtriple=armv7-apple-darwin < %s -codegenprepare -S | FileCheck -check-prefix=NEON %s
6 ; NEON-LABEL: @sink_zext(
7 ; NEON-NEXT: entry:
8 ; NEON-NEXT: br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
9 ; NEON: if.then:
10 ; NEON-NEXT: [[ZB_1:%.*]] = zext <8 x i8> [[B:%.*]] to <8 x i16>
11 ; NEON-NEXT: [[TMP0:%.*]] = zext <8 x i8> [[A:%.*]] to <8 x i16>
12 ; NEON-NEXT: [[RES_1:%.*]] = add <8 x i16> [[TMP0]], [[ZB_1]]
13 ; NEON-NEXT: ret <8 x i16> [[RES_1]]
14 ; NEON: if.else:
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