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/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsARM.h16 arm_cdp = 1498, // llvm.arm.cdp
17 arm_cdp2, // llvm.arm.cdp2
18 arm_clrex, // llvm.arm.clrex
19 arm_cls, // llvm.arm.cls
20 arm_cls64, // llvm.arm.cls64
21 arm_cmse_tt, // llvm.arm.cmse.tt
22 arm_cmse_tta, // llvm.arm.cmse.tta
23 arm_cmse_ttat, // llvm.arm.cmse.ttat
24 arm_cmse_ttt, // llvm.arm.cmse.ttt
25 arm_crc32b, // llvm.arm.crc32b
[all …]
/external/llvm-project/clang/test/Preprocessor/
Dinit-arm.c1 …ng -triple=thumbv7-windows-msvc < /dev/null | FileCheck -match-full-lines -check-prefix ARM-MSVC %s
3 // ARM-MSVC: #define _M_ARM_NT 1
4 // ARM-MSVC: #define _WIN32 1
5 // ARM-MSVC-NOT:#define __ARM_DWARF_EH__ 1
7 …clang_cc1 -E -dM -ffreestanding -triple=arm-none-none < /dev/null | FileCheck -match-full-lines -c…
8 … -E -dM -ffreestanding -triple=arm-none-none < /dev/null | FileCheck -match-full-lines -check-pref…
10 // ARM-NOT:#define _LP64
11 // ARM:#define __APCS_32__ 1
12 // ARM-NOT:#define __ARMEB__ 1
13 // ARM:#define __ARMEL__ 1
[all …]
/external/llvm-project/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 ; RUN: llc < %s -mtriple=arm-linux-androideabi -mattr=+v4t -verify-machineinstrs | FileCheck %s -ch…
2 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -mattr=+v4t -verify-machineinstrs | FileCheck %…
5 ; RUN: llc < %s -mtriple=arm-linux-androideabi -filetype=obj
6 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -filetype=obj
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
[all …]
Ddebug-frame-large-stack.ll1 … llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi -frame-pointer=all| FileCheck %s --check…
2 ; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK…
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
Dtwo-part-imm.ll2 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=CHECK-ARM
9 ; CHECK-ARM-LABEL: sub0:
10 ; CHECK-ARM: @ %bb.0:
11 ; CHECK-ARM: sub r0, r0, #23
12 ; CHECK-ARM: mov pc, lr
23 ; CHECK-ARM-LABEL: sub1:
24 ; CHECK-ARM: @ %bb.0:
25 ; CHECK-ARM: ldr r1, .LCPI1_0
26 ; CHECK-ARM: add r0, r0, r1
27 ; CHECK-ARM: mov pc, lr
[all …]
Darm-shrink-wrapping.ll3 ; RUN: | FileCheck %s --check-prefix=ARM-ENABLE
5 ; RUN: | FileCheck %s --check-prefix=ARM-DISABLE
64 ; ARM-ENABLE-LABEL: foo:
65 ; ARM-ENABLE: @ %bb.0:
66 ; ARM-ENABLE-NEXT: cmp r0, r1
67 ; ARM-ENABLE-NEXT: bge LBB0_2
68 ; ARM-ENABLE-NEXT: @ %bb.1: @ %true
69 ; ARM-ENABLE-NEXT: push {r7, lr}
70 ; ARM-ENABLE-NEXT: mov r7, sp
71 ; ARM-ENABLE-NEXT: push {r0}
[all …]
/external/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 ; RUN: llc < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=A…
2 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-pref…
5 ; RUN: llc < %s -mtriple=arm-linux-androideabi -filetype=obj
6 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -filetype=obj
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
[all …]
Ddebug-frame-large-stack.ll1 …: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-…
2 ; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK…
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp16 #include "ARM.h"
30 #define DEBUG_TYPE "arm-pseudo"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
[all …]
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp17 #include "ARM.h"
35 #define DEBUG_TYPE "arm-pseudo"
38 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
39 cl::desc("Verify machine code after expanding ARM pseudos"));
60 return "ARM pseudo instruction expansion pass"; in getPassName()
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
45 #define DEBUG_TYPE "arm-instrinfo"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp16 #include "ARM.h"
30 #define DEBUG_TYPE "arm-pseudo"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
DARMFeatures.h1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
[all …]
/external/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/llvm-project/llvm/unittests/Support/
DTargetParserTest.cpp37 ARM::ArchKind AK = ARM::parseCPUArch(CPUName); in testARMCPU()
38 bool pass = ARM::getArchName(AK).equals(ExpectedArch); in testARMCPU()
39 unsigned FPUKind = ARM::getDefaultFPU(CPUName, AK); in testARMCPU()
40 pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU); in testARMCPU()
42 uint64_t ExtKind = ARM::getDefaultExtensions(CPUName, AK); in testARMCPU()
43 if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE)) in testARMCPU()
44 pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags); in testARMCPU()
47 pass &= ARM::getCPUAttr(AK).equals(CPUAttr); in testARMCPU()
54 ARM::AEK_NONE, "")); in TEST()
56 ARM::AEK_NONE, "")); in TEST()
[all …]
/external/libhevc/
DAndroid.bp116 "decoder/arm",
117 "common/arm",
123 "decoder/arm/ihevcd_function_selector.c",
124 "decoder/arm/ihevcd_function_selector_noneon.c",
126 "common/arm/ihevc_intra_pred_filters_neon_intr.c",
127 "common/arm/ihevc_weighted_pred_neon_intr.c",
196 arm: {
198 "decoder/arm",
199 "common/arm",
203 "decoder/arm/ihevcd_function_selector.c",
[all …]
/external/compiler-rt/lib/builtins/
DCMakeLists.txt259 arm/adddf3vfp.S
260 arm/addsf3vfp.S
261 arm/aeabi_cdcmp.S
262 arm/aeabi_cdcmpeq_check_nan.c
263 arm/aeabi_cfcmp.S
264 arm/aeabi_cfcmpeq_check_nan.c
265 arm/aeabi_dcmp.S
266 arm/aeabi_div0.c
267 arm/aeabi_drsub.c
268 arm/aeabi_fcmp.S
[all …]
/external/llvm/unittests/Support/
DTargetParserTest.cpp47 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
51 ArchNames<ARM::ArchKind> kARMARCHNames[] = {
54 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, ARM::ID, ARCH_ATTR},
67 {NAME, AArch64::ArchKind::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
71 CpuNames<ARM::ArchKind> kARMCPUNames[] = {
73 {NAME, ARM::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
97 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
98 AK <= ARM::ArchKind::AK_LAST; in TEST()
99 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
100 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty() in TEST()
[all …]
/external/llvm-project/llvm/utils/gn/secondary/compiler-rt/lib/builtins/
DBUILD.gn304 if (current_cpu == "arm") {
321 "arm/aeabi_cdcmp.S",
322 "arm/aeabi_cdcmpeq_check_nan.c",
323 "arm/aeabi_cfcmp.S",
324 "arm/aeabi_cfcmpeq_check_nan.c",
325 "arm/aeabi_dcmp.S",
326 "arm/aeabi_div0.c",
327 "arm/aeabi_drsub.c",
328 "arm/aeabi_fcmp.S",
329 "arm/aeabi_frsub.c",
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc18 namespace ARM {
317 } // end namespace ARM
321 namespace ARM {
447 } // end namespace ARM
452 namespace ARM {
458 } // end namespace ARM
463 namespace ARM {
524 } // end namespace ARM
1479 { ARM::APSR },
1480 { ARM::APSR_NZCV },
[all …]

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