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/external/deqp-deps/glslang/Test/baseResults/
Dreflection.vert.out3 named.deadMember1: offset 0, type 8b51, size 1, index 0, binding -1, stages 1
4 anonDeadMember2: offset 64, type 8b52, size 1, index 1, binding -1, stages 1
5 ufDead4: offset -1, type 1406, size 1, index -1, binding -1, stages 1
6 anonMember1: offset 0, type 8b51, size 1, index 1, binding -1, stages 1
7 uf1: offset -1, type 1406, size 1, index -1, binding -1, stages 1
8 uf2: offset -1, type 1406, size 1, index -1, binding -1, stages 1
9 named.member3: offset 32, type 8b52, size 1, index 0, binding -1, stages 1
10 image_ui2D: offset -1, type 9063, size 1, index -1, binding -1, stages 1
11 sampler_2D: offset -1, type 8b5e, size 1, index -1, binding -1, stages 1
12 sampler_2DMSArray: offset -1, type 910b, size 1, index -1, binding -1, stages 1
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Dhlsl.reflection.vert.out3 anonDeadMember2: offset 64, type 8b52, size 1, index 0, binding -1, stages 1
4 ufDead4: offset 28, type 1406, size 1, index 1, binding -1, stages 1
5 anonMember1: offset 0, type 8b51, size 1, index 0, binding -1, stages 1
6 uf1: offset 16, type 1406, size 1, index 1, binding -1, stages 1
7 anonMember3: offset 80, type 8b52, size 1, index 0, binding -1, stages 1
8 s.a: offset 0, type 1404, size 1, index 1, binding -1, stages 1
9 m23: offset 16, type 8b67, size 1, index 0, binding -1, stages 1
10 scalarAfterm23: offset 48, type 1404, size 1, index 0, binding -1, stages 1
11 c_m23: offset 16, type 8b67, size 1, index 2, binding -1, stages 1
12 c_scalarAfterm23: offset 48, type 1404, size 1, index 2, binding -1, stages 1
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Dreflection.options.vert.out3 UBO.verts[0].position[0]: offset 0, type 1406, size 3, index 0, binding -1, stages 1, arrayStride 4…
4 UBO.verts[0].normal[0]: offset 12, type 1406, size 3, index 0, binding -1, stages 0, arrayStride 4,…
5 UBO.verts[1].position[0]: offset 24, type 1406, size 3, index 0, binding -1, stages 1, arrayStride …
6 UBO.verts[1].normal[0]: offset 36, type 1406, size 3, index 0, binding -1, stages 0, arrayStride 4,…
7 UBO.flt[0]: offset 48, type 1406, size 8, index 0, binding -1, stages 1, arrayStride 4, topLevelArr…
8 UBO.unused: offset 80, type 8dc8, size 1, index 0, binding -1, stages 0
9 UBO.uniform_multi[0][0][0]: offset 96, type 1406, size 2, index 0, binding -1, stages 1, arrayStrid…
10 UBO.uniform_multi[0][1][0]: offset 104, type 1406, size 2, index 0, binding -1, stages 0, arrayStri…
11 UBO.uniform_multi[0][2][0]: offset 112, type 1406, size 2, index 0, binding -1, stages 0, arrayStri…
12 UBO.uniform_multi[1][0][0]: offset 120, type 1406, size 2, index 0, binding -1, stages 0, arrayStri…
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Dhlsl.automap.frag.out3 t1: offset -1, type 8b5d, size 1, index -1, binding 11, stages 16
4 t2: offset -1, type 8b5e, size 1, index -1, binding 12, stages 16
5 t3: offset -1, type 8b5f, size 1, index -1, binding 13, stages 16
6 t4.@data: offset 0, type 8b52, size 1, index 0, binding -1, stages 16, arrayStride 16, topLevelArra…
7 t5.@data: offset 0, type 1405, size 0, index 1, binding -1, stages 16, arrayStride 4, topLevelArray…
8 t6: offset -1, type 8dc2, size 1, index -1, binding 16, stages 16
9 s1: offset -1, type 0, size 1, index -1, binding 31, stages 16
10 s2: offset -1, type 0, size 1, index -1, binding 32, stages 16
11 u1: offset -1, type 904c, size 1, index -1, binding 41, stages 16
12 u2: offset -1, type 904d, size 1, index -1, binding 42, stages 16
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Dhlsl.reflection.binding.frag.out3 t1: offset -1, type 8b5d, size 1, index -1, binding 15, stages 16
4 s1: offset -1, type 0, size 1, index -1, binding 5, stages 16
5 t1a: offset -1, type 8b5d, size 1, index -1, binding 16, stages 16, arrayStride 4, topLevelArrayStr…
6 s1a: offset -1, type 0, size 1, index -1, binding 6, stages 16, arrayStride 4, topLevelArrayStride 4
7 c1_a: offset 0, type 8b52, size 1, index 0, binding -1, stages 16
8 c1_b: offset 16, type 1404, size 1, index 0, binding -1, stages 16
9 c1_c: offset 20, type 1406, size 1, index 0, binding -1, stages 16
10 c2_a: offset 0, type 8b52, size 1, index 1, binding -1, stages 16
11 c2_b: offset 16, type 1404, size 1, index 1, binding -1, stages 16
12 c2_c: offset 20, type 1406, size 1, index 1, binding -1, stages 16
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Dreflection.options.geom.out11 gl_PerVertex.gl_Position: offset 0, type 8b52, size 1, index 0, binding -1, stages 8
12 gl_PerVertex.gl_PointSize: offset 0, type 1406, size 1, index 0, binding -1, stages 8
13 gl_PerVertex.gl_ClipDistance[0]: offset 0, type 1406, size 1, index 0, binding -1, stages 8
14 block.Color: offset 0, type 8b50, size 1, index 0, binding -1, stages 8
15 block.Texcoord: offset 0, type 8b50, size 1, index 0, binding -1, stages 8
16 block.in_a: offset 0, type 8b54, size 1, index 0, binding -1, stages 8
19 gl_Position: offset 0, type 8b52, size 1, index 0, binding -1, stages 8
20 gl_PointSize: offset 0, type 1406, size 1, index 0, binding -1, stages 8
21 gl_ClipDistance[0]: offset 0, type 1406, size 1, index 0, binding -1, stages 8
22 block.Color: offset 0, type 8b52, size 1, index 0, binding -1, stages 8
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Dreflection.linked.options.out4 ubo_block.unused_uniform: offset 0, type 1406, size 1, index 0, binding -1, stages 0
5 ubo_block.shared_uniform: offset 4, type 1406, size 1, index 0, binding -1, stages 17
6 ubo_block.vsonly_uniform: offset 8, type 1406, size 1, index 0, binding -1, stages 1
7 ubo_block.fsonly_uniform: offset 12, type 1406, size 1, index 0, binding -1, stages 16
10 ubo_block: offset -1, type ffffffff, size 16, index 0, binding 0, stages 17, numMembers 4
17 vertin: offset 0, type 1406, size 1, index 0, binding -1, stages 1
18 gl_VertexID: offset 0, type 1404, size 1, index 0, binding -1, stages 1
19 gl_InstanceID: offset 0, type 1404, size 1, index 0, binding -1, stages 1
22 fragout: offset 0, type 1406, size 1, index 0, binding -1, stages 16
Dhlsl.shift.per-set.frag.out203 t1: offset -1, type 8b5d, size 1, index -1, binding 21, stages 16
204 t2: offset -1, type 8b5e, size 1, index -1, binding 22, stages 16
205 t3: offset -1, type 8b5f, size 1, index -1, binding 26, stages 16
206 t4.@data: offset 0, type 8b52, size 1, index 0, binding -1, stages 16, arrayStride 16, topLevelArra…
207 t5.@data: offset 0, type 1405, size 0, index 1, binding -1, stages 16, arrayStride 4, topLevelArray…
208 t6: offset -1, type 8dc2, size 1, index -1, binding 23, stages 16
209 s1: offset -1, type 0, size 1, index -1, binding 11, stages 16
210 s2: offset -1, type 0, size 1, index -1, binding 17, stages 16
211 u1: offset -1, type 904c, size 1, index -1, binding 31, stages 16
212 u2: offset -1, type 904d, size 1, index -1, binding 42, stages 16
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Dreflection.linked.out4 ubo_block.shared_uniform: offset 4, type 1406, size 1, index 0, binding -1, stages 17
5 ubo_block.vsonly_uniform: offset 8, type 1406, size 1, index 0, binding -1, stages 17
6 ubo_block.fsonly_uniform: offset 12, type 1406, size 1, index 0, binding -1, stages 16
9 ubo_block: offset -1, type ffffffff, size 16, index 0, binding 0, stages 17, numMembers 4
16 vertin: offset 0, type 1406, size 1, index 0, binding -1, stages 1
19 fragout: offset 0, type 1406, size 1, index 0, binding -1, stages 16
/external/mesa3d/src/intel/tools/
Daubinator_viewer_urb.h27 const struct aub_decode_urb_stage_state *stages) { in DrawAllocation()
48 ImVec2 alloc_tl(x + stages[s].start * alloc_delta, y); in DrawAllocation()
49 ImVec2 alloc_br(x + (stages[s].start + in DrawAllocation()
50 stages[s].n_entries * stages[s].size) * alloc_delta, in DrawAllocation()
53 ImVec2 const_br(x + (const_idx + stages[s].const_rd_length) * alloc_delta, in DrawAllocation()
72 stages[s].start, in DrawAllocation()
73 stages[s].start + stages[s].n_entries * stages[s].size); in DrawAllocation()
85 stages[s].rd_offset, in DrawAllocation()
86 stages[s].rd_offset + stages[s].rd_length); in DrawAllocation()
89 const_idx += stages[s].const_rd_length; in DrawAllocation()
/external/deqp/external/openglcts/modules/gl/
Dgl4cEnhancedLayoutsTests.hpp290 enum STAGES enum in gl4cts::EnhancedLayouts::Utils::Shader
308 InvalidSourceException(const glw::GLchar* error_message, const std::string& source, STAGES stage);
320 STAGES m_stage;
329 void Init(STAGES stage, const std::string& source);
336 static void Create(const glw::Functions& gl, STAGES stage, glw::GLuint& out_id);
341 static glw::GLenum GetShaderStageGLenum(STAGES stage);
344 static const glw::GLchar* GetStageName(STAGES stage);
347 static void LogSource(deqp::Context& context, const std::string& source, STAGES stage);
492 static FLAVOUR GetFlavour(Shader::STAGES stage, VARYING_DIRECTION direction);
581 ShaderInterface(Shader::STAGES stage);
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
DPipeline.cpp10 /// This file implements an ordered container of stages that simulate the
27 for (auto &S : Stages) in addEventListener()
32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
38 assert(!Stages.empty() && "Unexpected empty pipeline found!"); in run()
53 // Update stages before we start processing new instructions. in runCycle()
54 for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) { in runCycle()
61 Stage &FirstStage = *Stages[0]; in runCycle()
65 // Update stages in preparation for a new cycle. in runCycle()
66 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
77 if (!Stages.empty()) { in appendStage()
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DCMakeLists.txt14 Stages/DispatchStage.cpp
15 Stages/EntryStage.cpp
16 Stages/ExecuteStage.cpp
17 Stages/InstructionTables.cpp
18 Stages/MicroOpQueueStage.cpp
19 Stages/RetireStage.cpp
20 Stages/Stage.cpp
/external/llvm-project/llvm/lib/MCA/
DPipeline.cpp10 /// This file implements an ordered container of stages that simulate the
27 for (auto &S : Stages) in addEventListener()
32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
38 assert(!Stages.empty() && "Unexpected empty pipeline found!"); in run()
53 // Update stages before we start processing new instructions. in runCycle()
54 for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) { in runCycle()
61 Stage &FirstStage = *Stages[0]; in runCycle()
65 // Update stages in preparation for a new cycle. in runCycle()
66 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
77 if (!Stages.empty()) { in appendStage()
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DCMakeLists.txt14 Stages/DispatchStage.cpp
15 Stages/EntryStage.cpp
16 Stages/ExecuteStage.cpp
17 Stages/InstructionTables.cpp
18 Stages/MicroOpQueueStage.cpp
19 Stages/RetireStage.cpp
20 Stages/Stage.cpp
/external/llvm-project/llvm/utils/gn/secondary/llvm/lib/MCA/
DBUILD.gn22 "Stages/DispatchStage.cpp",
23 "Stages/EntryStage.cpp",
24 "Stages/ExecuteStage.cpp",
25 "Stages/InstructionTables.cpp",
26 "Stages/MicroOpQueueStage.cpp",
27 "Stages/RetireStage.cpp",
28 "Stages/Stage.cpp",
/external/mesa3d/src/intel/vulkan/
Danv_pipeline.c650 struct anv_pipeline_stage *stages, in anv_pipeline_hash_graphics() argument
666 if (stages[s].entrypoint) { in anv_pipeline_hash_graphics()
667 _mesa_sha1_update(&ctx, stages[s].shader_sha1, in anv_pipeline_hash_graphics()
668 sizeof(stages[s].shader_sha1)); in anv_pipeline_hash_graphics()
669 _mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s)); in anv_pipeline_hash_graphics()
847 * shader stages." in merge_tess_info()
1019 * stages. in anv_pipeline_link_fs()
1279 struct anv_pipeline_stage stages[MESA_SHADER_STAGES] = {}; in anv_pipeline_compile_graphics() local
1292 stages[stage].stage = stage; in anv_pipeline_compile_graphics()
1293 stages[stage].module = anv_shader_module_from_handle(sinfo->module); in anv_pipeline_compile_graphics()
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/external/adhd/scripts/audio_tuning/
Dconf2ini2.py94 stages = []
96 stages.append(print_drc)
98 stages.append(print_eq)
100 if is_true(d, 'global.enable_swap') and len(stages) >= 2:
101 stages[0], stages[1] = stages[1], stages[0]
103 for i in range(len(stages)):
106 dst = 'dst' if i == len(stages) - 1 else intermediate_name(i + 1)
107 stages[i](d, src, dst)
/external/mesa3d/src/mesa/tnl/
Dt_pipeline.c39 const struct tnl_pipeline_stage **stages ) in _tnl_install_pipeline() argument
48 for (i = 0 ; i < MAX_PIPELINE_STAGES && stages[i] ; i++) { in _tnl_install_pipeline()
49 struct tnl_pipeline_stage *s = &tnl->pipeline.stages[i]; in _tnl_install_pipeline()
50 memcpy(s, stages[i], sizeof(*s)); in _tnl_install_pipeline()
64 struct tnl_pipeline_stage *s = &tnl->pipeline.stages[i]; in _tnl_destroy_pipeline()
211 struct tnl_pipeline_stage *s = &tnl->pipeline.stages[i]; in _tnl_run_pipeline()
240 struct tnl_pipeline_stage *s = &tnl->pipeline.stages[i]; in _tnl_run_pipeline()
254 * tampering with the internals of these stages in the way that
255 * drivers did in Mesa 3.4. These stages are basically black boxes,
260 * - removing redundant stages (making sure that the software rasterizer
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/external/mesa3d/src/mesa/main/
Dpipelineobj.c222 GLbitfield stages, struct gl_pipeline_object *pipe) { in use_program_stages() argument
224 /* Enable individual stages from the program as requested by the in use_program_stages()
234 * stages, it is as if the pipeline object has no programmable stage in use_program_stages()
235 * configured for the indicated shader stages." in use_program_stages()
237 if ((stages & GL_VERTEX_SHADER_BIT) != 0) in use_program_stages()
240 if ((stages & GL_FRAGMENT_SHADER_BIT) != 0) in use_program_stages()
243 if ((stages & GL_GEOMETRY_SHADER_BIT) != 0) in use_program_stages()
246 if ((stages & GL_TESS_CONTROL_SHADER_BIT) != 0) in use_program_stages()
249 if ((stages & GL_TESS_EVALUATION_SHADER_BIT) != 0) in use_program_stages()
252 if ((stages & GL_COMPUTE_SHADER_BIT) != 0) in use_program_stages()
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/external/webrtc/common_audio/signal_processing/
Dcomplex_bit_reverse.c19 /* Indexes for the case of stages == 7. */
30 /* Indexes for the case of stages == 8. */
49 void WebRtcSpl_ComplexBitReverse(int16_t* __restrict complex_data, int stages) { in WebRtcSpl_ComplexBitReverse() argument
50 /* For any specific value of stages, we know exactly the indexes that are in WebRtcSpl_ComplexBitReverse()
52 * stages are 7 and 8, so we use tables to save unnecessary iterations and in WebRtcSpl_ComplexBitReverse()
55 if (stages == 7 || stages == 8) { in WebRtcSpl_ComplexBitReverse()
60 if (stages == 8) { in WebRtcSpl_ComplexBitReverse()
81 int n = 1 << stages; in WebRtcSpl_ComplexBitReverse()
101 * This is similar to the loop in the stages == 7 or 8 cases. in WebRtcSpl_ComplexBitReverse()
/external/deqp-deps/glslang/glslang/MachineIndependent/
Dreflection.cpp160 EShLanguageMask& stages = ioItems.back().stages; in addPipeIOVariable() local
161 stages = static_cast<EShLanguageMask>(stages | 1 << intermediate.getStage()); in addPipeIOVariable()
163 EShLanguageMask& stages = ioItems[it->second].stages; in addPipeIOVariable() local
164 stages = static_cast<EShLanguageMask>(stages | 1 << intermediate.getStage()); in addPipeIOVariable()
467 EShLanguageMask& stages = variables.back().stages; in blowUpActiveAggregate() local
468 stages = static_cast<EShLanguageMask>(stages | 1 << intermediate.getStage()); in blowUpActiveAggregate()
477 EShLanguageMask& stages = variables[it->second].stages; in blowUpActiveAggregate() local
478 stages = static_cast<EShLanguageMask>(stages | 1 << intermediate.getStage()); in blowUpActiveAggregate()
536 EShLanguageMask& stages = ioItems.back().stages; in blowUpIOAggregate() local
537 stages = static_cast<EShLanguageMask>(stages | 1 << intermediate.getStage()); in blowUpIOAggregate()
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DModuloSchedule.h94 /// The number of stages in this schedule (Max(Stage) + 1).
120 /// Return the number of stages contained in this schedule, which is the
175 /// The first element in the pair is the max difference in stages. The
226 /// Return the max. number of stages/iterations that can occur between a
229 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForReg() local
230 if ((int)CurStage > Schedule.getNumStages() - 1 && Stages.first == 0 && in getStagesForReg()
231 Stages.second) in getStagesForReg()
233 return Stages.first; in getStagesForReg()
236 /// The number of stages for a Phi is a little different than other
240 /// Phi in the same stage. This function returns the number of stages
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/external/mesa3d/src/amd/compiler/
DREADME.md114 ## Supported shader stages
116 Hardware stages (as executed on the chip) don't exactly match software stages (as defined in OpenGL…
117 Which software stage gets executed on which hardware stage depends on what kind of software stages
123 #### Glossary of software stages argument
132 #### Glossary of hardware stages argument
157 The merged stages on GFX9 (and GFX10/legacy) are: LSHS and ESGS. On GFX10/NGG the ESGS is merged wi…
176 | GFX6-8 HW stages: | LS | HS | ES | GS | VS | PS | ACO terminology |
178 | SW stages: only VS+PS: | | | | | VS | FS | `vertex_vs`, `fragment_fs` |
185 * HW LS and HS stages are merged, and the merged shader still uses LDS in the same way as before
186 * HW ES and GS stages are merged, so ES outputs can go to LDS instead of VRAM
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/external/llvm-project/llvm/include/llvm/CodeGen/
DModuloSchedule.h94 /// The number of stages in this schedule (Max(Stage) + 1).
120 /// Return the number of stages contained in this schedule, which is the
181 /// The first element in the pair is the max difference in stages. The
232 /// Return the max. number of stages/iterations that can occur between a
235 std::pair<unsigned, bool> Stages = RegToStageDiff[Reg]; in getStagesForReg() local
236 if ((int)CurStage > Schedule.getNumStages() - 1 && Stages.first == 0 && in getStagesForReg()
237 Stages.second) in getStagesForReg()
239 return Stages.first; in getStagesForReg()
242 /// The number of stages for a Phi is a little different than other
246 /// Phi in the same stage. This function returns the number of stages
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