1{
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108    {"name": "CB_DCC_DECOMPRESS", "value": 6},
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121    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
122    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
123    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
124    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
125    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
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383    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
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403  },
404  "PkrYsel": {
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407    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
408    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
409    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
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415    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
416    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
417    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
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419    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
420    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
421    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
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423  },
424  "ROP3": {
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428    {"name": "X_0X0A", "value": 10},
429    {"name": "X_0X0F", "value": 15},
430    {"name": "ROP3_NOR", "value": 17},
431    {"name": "ROP3_AND_INVERTED", "value": 34},
432    {"name": "ROP3_COPY_INVERTED", "value": 51},
433    {"name": "ROP3_AND_REVERSE", "value": 68},
434    {"name": "X_0X50", "value": 80},
435    {"name": "ROP3_INVERT", "value": 85},
436    {"name": "X_0X5A", "value": 90},
437    {"name": "X_0X5F", "value": 95},
438    {"name": "ROP3_XOR", "value": 102},
439    {"name": "ROP3_NAND", "value": 119},
440    {"name": "ROP3_AND", "value": 136},
441    {"name": "ROP3_EQUIVALENT", "value": 153},
442    {"name": "X_0XA0", "value": 160},
443    {"name": "X_0XA5", "value": 165},
444    {"name": "ROP3_NO_OP", "value": 170},
445    {"name": "X_0XAF", "value": 175},
446    {"name": "ROP3_OR_INVERTED", "value": 187},
447    {"name": "ROP3_COPY", "value": 204},
448    {"name": "ROP3_OR_REVERSE", "value": 221},
449    {"name": "ROP3_OR", "value": 238},
450    {"name": "X_0XF0", "value": 240},
451    {"name": "X_0XF5", "value": 245},
452    {"name": "X_0XFA", "value": 250},
453    {"name": "ROP3_SET", "value": 255}
454   ]
455  },
456  "RbMap": {
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459    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
460    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
461    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
462   ]
463  },
464  "RbXsel": {
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467    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
468   ]
469  },
470  "RbXsel2": {
471   "entries": [
472    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
473    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
474    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
475    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
476   ]
477  },
478  "RbYsel": {
479   "entries": [
480    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
481    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
482   ]
483  },
484  "ReadPolicy": {
485   "entries": [
486    {"name": "CACHE_LRU_RD", "value": 0},
487    {"name": "CACHE_NOA", "value": 1},
488    {"name": "UNCACHED_RD", "value": 2},
489    {"name": "RESERVED_RDPOLICY", "value": 3}
490   ]
491  },
492  "SPI_PNT_SPRITE_OVERRIDE": {
493   "entries": [
494    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
495    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
496    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
497    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
498    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
499   ]
500  },
501  "SPI_SHADER_EX_FORMAT": {
502   "entries": [
503    {"name": "SPI_SHADER_ZERO", "value": 0},
504    {"name": "SPI_SHADER_32_R", "value": 1},
505    {"name": "SPI_SHADER_32_GR", "value": 2},
506    {"name": "SPI_SHADER_32_AR", "value": 3},
507    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
508    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
509    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
510    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
511    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
512    {"name": "SPI_SHADER_32_ABGR", "value": 9}
513   ]
514  },
515  "SPI_SHADER_FORMAT": {
516   "entries": [
517    {"name": "SPI_SHADER_NONE", "value": 0},
518    {"name": "SPI_SHADER_1COMP", "value": 1},
519    {"name": "SPI_SHADER_2COMP", "value": 2},
520    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
521    {"name": "SPI_SHADER_4COMP", "value": 4}
522   ]
523  },
524  "SPM_PERFMON_STATE": {
525   "entries": [
526    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
527    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
528    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
529    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
530    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
531    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
532   ]
533  },
534  "SX_BLEND_OPT": {
535   "entries": [
536    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
537    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
538    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
539    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
540    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
541    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
542    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
543    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
544   ]
545  },
546  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
547   "entries": [
548    {"name": "EXACT", "value": 0},
549    {"name": "11BIT_FORMAT", "value": 1},
550    {"name": "10BIT_FORMAT", "value": 3},
551    {"name": "8BIT_FORMAT", "value": 6},
552    {"name": "6BIT_FORMAT", "value": 11},
553    {"name": "5BIT_FORMAT", "value": 13},
554    {"name": "4BIT_FORMAT", "value": 15}
555   ]
556  },
557  "SX_DOWNCONVERT_FORMAT": {
558   "entries": [
559    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
560    {"name": "SX_RT_EXPORT_32_R", "value": 1},
561    {"name": "SX_RT_EXPORT_32_A", "value": 2},
562    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
563    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
564    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
565    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
566    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
567    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
568    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
569    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
570   ]
571  },
572  "SX_OPT_COMB_FCN": {
573   "entries": [
574    {"name": "OPT_COMB_NONE", "value": 0},
575    {"name": "OPT_COMB_ADD", "value": 1},
576    {"name": "OPT_COMB_SUBTRACT", "value": 2},
577    {"name": "OPT_COMB_MIN", "value": 3},
578    {"name": "OPT_COMB_MAX", "value": 4},
579    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
580    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
581    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
582   ]
583  },
584  "ScMap": {
585   "entries": [
586    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
587    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
588    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
589    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
590   ]
591  },
592  "ScUncertaintyRegionMode": {
593   "entries": [
594    {"name": "SC_HALF_LSB", "value": 0},
595    {"name": "SC_LSB_ONE_SIDED", "value": 1},
596    {"name": "SC_LSB_TWO_SIDED", "value": 2}
597   ]
598  },
599  "ScXsel": {
600   "entries": [
601    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
602    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
603    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
604    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
605   ]
606  },
607  "ScYsel": {
608   "entries": [
609    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
610    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
611    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
612    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
613   ]
614  },
615  "SeMap": {
616   "entries": [
617    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
618    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
619    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
620    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
621   ]
622  },
623  "SePairMap": {
624   "entries": [
625    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
626    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
627    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
628    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
629   ]
630  },
631  "SePairXsel": {
632   "entries": [
633    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
634    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
635    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
636    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
637   ]
638  },
639  "SePairYsel": {
640   "entries": [
641    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
642    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
643    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
644    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
645   ]
646  },
647  "SeXsel": {
648   "entries": [
649    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
650    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
651    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
652    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
653   ]
654  },
655  "SeYsel": {
656   "entries": [
657    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
658    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
659    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
660    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
661   ]
662  },
663  "StencilFormat": {
664   "entries": [
665    {"name": "STENCIL_INVALID", "value": 0},
666    {"name": "STENCIL_8", "value": 1}
667   ]
668  },
669  "StencilOp": {
670   "entries": [
671    {"name": "STENCIL_KEEP", "value": 0},
672    {"name": "STENCIL_ZERO", "value": 1},
673    {"name": "STENCIL_ONES", "value": 2},
674    {"name": "STENCIL_REPLACE_TEST", "value": 3},
675    {"name": "STENCIL_REPLACE_OP", "value": 4},
676    {"name": "STENCIL_ADD_CLAMP", "value": 5},
677    {"name": "STENCIL_SUB_CLAMP", "value": 6},
678    {"name": "STENCIL_INVERT", "value": 7},
679    {"name": "STENCIL_ADD_WRAP", "value": 8},
680    {"name": "STENCIL_SUB_WRAP", "value": 9},
681    {"name": "STENCIL_AND", "value": 10},
682    {"name": "STENCIL_OR", "value": 11},
683    {"name": "STENCIL_XOR", "value": 12},
684    {"name": "STENCIL_NAND", "value": 13},
685    {"name": "STENCIL_NOR", "value": 14},
686    {"name": "STENCIL_XNOR", "value": 15}
687   ]
688  },
689  "SurfaceEndian": {
690   "entries": [
691    {"name": "ENDIAN_NONE", "value": 0},
692    {"name": "ENDIAN_8IN16", "value": 1},
693    {"name": "ENDIAN_8IN32", "value": 2},
694    {"name": "ENDIAN_8IN64", "value": 3}
695   ]
696  },
697  "SurfaceNumber": {
698   "entries": [
699    {"name": "NUMBER_UNORM", "value": 0},
700    {"name": "NUMBER_SNORM", "value": 1},
701    {"name": "NUMBER_USCALED", "value": 2},
702    {"name": "NUMBER_SSCALED", "value": 3},
703    {"name": "NUMBER_UINT", "value": 4},
704    {"name": "NUMBER_SINT", "value": 5},
705    {"name": "NUMBER_SRGB", "value": 6},
706    {"name": "NUMBER_FLOAT", "value": 7}
707   ]
708  },
709  "SurfaceSwap": {
710   "entries": [
711    {"name": "SWAP_STD", "value": 0},
712    {"name": "SWAP_ALT", "value": 1},
713    {"name": "SWAP_STD_REV", "value": 2},
714    {"name": "SWAP_ALT_REV", "value": 3}
715   ]
716  },
717  "ThreadTraceRegInclude": {
718   "entries": [
719    {"name": "REG_INCLUDE_SQDEC", "value": 1},
720    {"name": "REG_INCLUDE_SHDEC", "value": 2},
721    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
722    {"name": "REG_INCLUDE_COMP", "value": 8},
723    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
724    {"name": "REG_INCLUDE_CONFIG", "value": 32},
725    {"name": "REG_INCLUDE_OTHER", "value": 64},
726    {"name": "REG_INCLUDE_READS", "value": 128}
727   ]
728  },
729  "ThreadTraceTokenExclude": {
730   "entries": [
731    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
732    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
733    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
734    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
735    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
736    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
737    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
738    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
739    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
740    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
741    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
742    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
743   ]
744  },
745  "TileSplit": {
746   "entries": [
747    {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
748    {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
749    {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
750    {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
751    {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
752    {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
753    {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
754   ]
755  },
756  "VGT_DETECT_ONE": {
757   "entries": [
758    {"name": "PRE_CLAMP_TF1", "value": 0},
759    {"name": "POST_CLAMP_TF1", "value": 1},
760    {"name": "DISABLE_TF1", "value": 2}
761   ]
762  },
763  "VGT_DETECT_ZERO": {
764   "entries": [
765    {"name": "PRE_CLAMP_TF0", "value": 0},
766    {"name": "POST_CLAMP_TF0", "value": 1},
767    {"name": "DISABLE_TF0", "value": 2}
768   ]
769  },
770  "VGT_DIST_MODE": {
771   "entries": [
772    {"name": "NO_DIST", "value": 0},
773    {"name": "PATCHES", "value": 1},
774    {"name": "DONUTS", "value": 2},
775    {"name": "TRAPEZOIDS", "value": 3}
776   ]
777  },
778  "VGT_DI_MAJOR_MODE_SELECT": {
779   "entries": [
780    {"name": "DI_MAJOR_MODE_0", "value": 0},
781    {"name": "DI_MAJOR_MODE_1", "value": 1}
782   ]
783  },
784  "VGT_DI_PRIM_TYPE": {
785   "entries": [
786    {"name": "DI_PT_NONE", "value": 0},
787    {"name": "DI_PT_POINTLIST", "value": 1},
788    {"name": "DI_PT_LINELIST", "value": 2},
789    {"name": "DI_PT_LINESTRIP", "value": 3},
790    {"name": "DI_PT_TRILIST", "value": 4},
791    {"name": "DI_PT_TRIFAN", "value": 5},
792    {"name": "DI_PT_TRISTRIP", "value": 6},
793    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
794    {"name": "DI_PT_UNUSED_1", "value": 8},
795    {"name": "DI_PT_PATCH", "value": 9},
796    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
797    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
798    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
799    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
800    {"name": "DI_PT_UNUSED_3", "value": 14},
801    {"name": "DI_PT_UNUSED_4", "value": 15},
802    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
803    {"name": "DI_PT_RECTLIST", "value": 17},
804    {"name": "DI_PT_LINELOOP", "value": 18},
805    {"name": "DI_PT_QUADLIST", "value": 19},
806    {"name": "DI_PT_QUADSTRIP", "value": 20},
807    {"name": "DI_PT_POLYGON", "value": 21}
808   ]
809  },
810  "VGT_DI_SOURCE_SELECT": {
811   "entries": [
812    {"name": "DI_SRC_SEL_DMA", "value": 0},
813    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
814    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
815    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
816   ]
817  },
818  "VGT_DMA_BUF_TYPE": {
819   "entries": [
820    {"name": "VGT_DMA_BUF_MEM", "value": 0},
821    {"name": "VGT_DMA_BUF_RING", "value": 1},
822    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
823    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
824   ]
825  },
826  "VGT_DMA_SWAP_MODE": {
827   "entries": [
828    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
829    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
830    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
831    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
832   ]
833  },
834  "VGT_EVENT_TYPE": {
835   "entries": [
836    {"name": "Reserved_0x00", "value": 0},
837    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
838    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
839    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
840    {"name": "CACHE_FLUSH_TS", "value": 4},
841    {"name": "CONTEXT_DONE", "value": 5},
842    {"name": "CACHE_FLUSH", "value": 6},
843    {"name": "CS_PARTIAL_FLUSH", "value": 7},
844    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
845    {"name": "SET_FE_ID", "value": 9},
846    {"name": "VGT_STREAMOUT_RESET", "value": 10},
847    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
848    {"name": "END_OF_PIPE_IB_END", "value": 12},
849    {"name": "RST_PIX_CNT", "value": 13},
850    {"name": "BREAK_BATCH", "value": 14},
851    {"name": "VS_PARTIAL_FLUSH", "value": 15},
852    {"name": "PS_PARTIAL_FLUSH", "value": 16},
853    {"name": "FLUSH_HS_OUTPUT", "value": 17},
854    {"name": "FLUSH_DFSM", "value": 18},
855    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
856    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
857    {"name": "ZPASS_DONE", "value": 21},
858    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
859    {"name": "PERFCOUNTER_START", "value": 23},
860    {"name": "PERFCOUNTER_STOP", "value": 24},
861    {"name": "PIPELINESTAT_START", "value": 25},
862    {"name": "PIPELINESTAT_STOP", "value": 26},
863    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
864    {"name": "FLUSH_ES_OUTPUT", "value": 28},
865    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
866    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
867    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
868    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
869    {"name": "RESET_VTX_CNT", "value": 33},
870    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
871    {"name": "CS_CONTEXT_DONE", "value": 35},
872    {"name": "VGT_FLUSH", "value": 36},
873    {"name": "TGID_ROLLOVER", "value": 37},
874    {"name": "SQ_NON_EVENT", "value": 38},
875    {"name": "SC_SEND_DB_VPZ", "value": 39},
876    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
877    {"name": "FLUSH_SX_TS", "value": 41},
878    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
879    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
880    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
881    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
882    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
883    {"name": "CS_DONE", "value": 47},
884    {"name": "PS_DONE", "value": 48},
885    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
886    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
887    {"name": "THREAD_TRACE_START", "value": 51},
888    {"name": "THREAD_TRACE_STOP", "value": 52},
889    {"name": "THREAD_TRACE_MARKER", "value": 53},
890    {"name": "THREAD_TRACE_DRAW", "value": 54},
891    {"name": "THREAD_TRACE_FINISH", "value": 55},
892    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
893    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
894    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
895    {"name": "CONTEXT_SUSPEND", "value": 59},
896    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
897    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
898    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
899    {"name": "DRAW_DONE", "value": 63}
900   ]
901  },
902  "VGT_GS_CUT_MODE": {
903   "entries": [
904    {"name": "GS_CUT_1024", "value": 0},
905    {"name": "GS_CUT_512", "value": 1},
906    {"name": "GS_CUT_256", "value": 2},
907    {"name": "GS_CUT_128", "value": 3}
908   ]
909  },
910  "VGT_GS_MODE_TYPE": {
911   "entries": [
912    {"name": "GS_OFF", "value": 0},
913    {"name": "GS_SCENARIO_A", "value": 1},
914    {"name": "GS_SCENARIO_B", "value": 2},
915    {"name": "GS_SCENARIO_G", "value": 3},
916    {"name": "GS_SCENARIO_C", "value": 4},
917    {"name": "SPRITE_EN", "value": 5}
918   ]
919  },
920  "VGT_GS_OUTPRIM_TYPE": {
921   "entries": [
922    {"name": "POINTLIST", "value": 0},
923    {"name": "LINESTRIP", "value": 1},
924    {"name": "TRISTRIP", "value": 2},
925    {"name": "RECTLIST", "value": 3}
926   ]
927  },
928  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
929   "entries": [
930    {"name": "X_8K_DWORDS", "value": 0},
931    {"name": "X_4K_DWORDS", "value": 1},
932    {"name": "X_2K_DWORDS", "value": 2},
933    {"name": "X_1K_DWORDS", "value": 3}
934   ]
935  },
936  "VGT_INDEX_TYPE_MODE": {
937   "entries": [
938    {"name": "VGT_INDEX_16", "value": 0},
939    {"name": "VGT_INDEX_32", "value": 1},
940    {"name": "VGT_INDEX_8", "value": 2}
941   ]
942  },
943  "VGT_RDREQ_POLICY": {
944   "entries": [
945    {"name": "VGT_POLICY_LRU", "value": 0},
946    {"name": "VGT_POLICY_STREAM", "value": 1},
947    {"name": "VGT_POLICY_BYPASS", "value": 2}
948   ]
949  },
950  "VGT_STAGES_ES_EN": {
951   "entries": [
952    {"name": "ES_STAGE_OFF", "value": 0},
953    {"name": "ES_STAGE_DS", "value": 1},
954    {"name": "ES_STAGE_REAL", "value": 2},
955    {"name": "RESERVED_ES", "value": 3}
956   ]
957  },
958  "VGT_STAGES_GS_EN": {
959   "entries": [
960    {"name": "GS_STAGE_OFF", "value": 0},
961    {"name": "GS_STAGE_ON", "value": 1}
962   ]
963  },
964  "VGT_STAGES_HS_EN": {
965   "entries": [
966    {"name": "HS_STAGE_OFF", "value": 0},
967    {"name": "HS_STAGE_ON", "value": 1}
968   ]
969  },
970  "VGT_STAGES_LS_EN": {
971   "entries": [
972    {"name": "LS_STAGE_OFF", "value": 0},
973    {"name": "LS_STAGE_ON", "value": 1},
974    {"name": "CS_STAGE_ON", "value": 2},
975    {"name": "RESERVED_LS", "value": 3}
976   ]
977  },
978  "VGT_STAGES_VS_EN": {
979   "entries": [
980    {"name": "VS_STAGE_REAL", "value": 0},
981    {"name": "VS_STAGE_DS", "value": 1},
982    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
983    {"name": "RESERVED_VS", "value": 3}
984   ]
985  },
986  "VGT_TESS_PARTITION": {
987   "entries": [
988    {"name": "PART_INTEGER", "value": 0},
989    {"name": "PART_POW2", "value": 1},
990    {"name": "PART_FRAC_ODD", "value": 2},
991    {"name": "PART_FRAC_EVEN", "value": 3}
992   ]
993  },
994  "VGT_TESS_TOPOLOGY": {
995   "entries": [
996    {"name": "OUTPUT_POINT", "value": 0},
997    {"name": "OUTPUT_LINE", "value": 1},
998    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
999    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1000   ]
1001  },
1002  "VGT_TESS_TYPE": {
1003   "entries": [
1004    {"name": "TESS_ISOLINE", "value": 0},
1005    {"name": "TESS_TRIANGLE", "value": 1},
1006    {"name": "TESS_QUAD", "value": 2}
1007   ]
1008  },
1009  "WritePolicy": {
1010   "entries": [
1011    {"name": "CACHE_LRU_WR", "value": 0},
1012    {"name": "CACHE_STREAM", "value": 1},
1013    {"name": "CACHE_BYPASS", "value": 2},
1014    {"name": "UNCACHED_WR", "value": 3}
1015   ]
1016  },
1017  "ZFormat": {
1018   "entries": [
1019    {"name": "Z_INVALID", "value": 0},
1020    {"name": "Z_16", "value": 1},
1021    {"name": "Z_24", "value": 2},
1022    {"name": "Z_32_FLOAT", "value": 3}
1023   ]
1024  },
1025  "ZLimitSumm": {
1026   "entries": [
1027    {"name": "FORCE_SUMM_OFF", "value": 0},
1028    {"name": "FORCE_SUMM_MINZ", "value": 1},
1029    {"name": "FORCE_SUMM_MAXZ", "value": 2},
1030    {"name": "FORCE_SUMM_BOTH", "value": 3}
1031   ]
1032  },
1033  "ZOrder": {
1034   "entries": [
1035    {"name": "LATE_Z", "value": 0},
1036    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1037    {"name": "RE_Z", "value": 2},
1038    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1039   ]
1040  }
1041 },
1042 "register_mappings": [
1043  {
1044   "chips": ["gfx10"],
1045   "map": {"at": 1028, "to": "mm"},
1046   "name": "SQ_WAVE_MODE",
1047   "type_ref": "SQ_WAVE_MODE"
1048  },
1049  {
1050   "chips": ["gfx10"],
1051   "map": {"at": 1032, "to": "mm"},
1052   "name": "SQ_WAVE_STATUS",
1053   "type_ref": "SQ_WAVE_STATUS"
1054  },
1055  {
1056   "chips": ["gfx10"],
1057   "map": {"at": 1036, "to": "mm"},
1058   "name": "SQ_WAVE_TRAPSTS",
1059   "type_ref": "SQ_WAVE_TRAPSTS"
1060  },
1061  {
1062   "chips": ["gfx10"],
1063   "map": {"at": 1040, "to": "mm"},
1064   "name": "SQ_WAVE_HW_ID_LEGACY",
1065   "type_ref": "SQ_WAVE_HW_ID_LEGACY"
1066  },
1067  {
1068   "chips": ["gfx10"],
1069   "map": {"at": 1044, "to": "mm"},
1070   "name": "SQ_WAVE_GPR_ALLOC",
1071   "type_ref": "SQ_WAVE_GPR_ALLOC"
1072  },
1073  {
1074   "chips": ["gfx10"],
1075   "map": {"at": 1048, "to": "mm"},
1076   "name": "SQ_WAVE_LDS_ALLOC",
1077   "type_ref": "SQ_WAVE_LDS_ALLOC"
1078  },
1079  {
1080   "chips": ["gfx10"],
1081   "map": {"at": 1052, "to": "mm"},
1082   "name": "SQ_WAVE_IB_STS",
1083   "type_ref": "SQ_WAVE_IB_STS"
1084  },
1085  {
1086   "chips": ["gfx10"],
1087   "map": {"at": 1056, "to": "mm"},
1088   "name": "SQ_WAVE_PC_LO",
1089   "type_ref": "SQ_WAVE_PC_LO"
1090  },
1091  {
1092   "chips": ["gfx10"],
1093   "map": {"at": 1060, "to": "mm"},
1094   "name": "SQ_WAVE_PC_HI",
1095   "type_ref": "SQ_WAVE_PC_HI"
1096  },
1097  {
1098   "chips": ["gfx10"],
1099   "map": {"at": 1064, "to": "mm"},
1100   "name": "SQ_WAVE_INST_DW0",
1101   "type_ref": "SQ_WAVE_INST_DW0"
1102  },
1103  {
1104   "chips": ["gfx10"],
1105   "map": {"at": 1076, "to": "mm"},
1106   "name": "SQ_WAVE_IB_DBG1",
1107   "type_ref": "SQ_WAVE_IB_DBG1"
1108  },
1109  {
1110   "chips": ["gfx10"],
1111   "map": {"at": 1080, "to": "mm"},
1112   "name": "SQ_WAVE_FLUSH_IB",
1113   "type_ref": "SQ_WAVE_FLUSH_IB"
1114  },
1115  {
1116   "chips": ["gfx10"],
1117   "map": {"at": 1116, "to": "mm"},
1118   "name": "SQ_WAVE_HW_ID1",
1119   "type_ref": "SQ_WAVE_HW_ID1"
1120  },
1121  {
1122   "chips": ["gfx10"],
1123   "map": {"at": 1120, "to": "mm"},
1124   "name": "SQ_WAVE_HW_ID2",
1125   "type_ref": "SQ_WAVE_HW_ID2"
1126  },
1127  {
1128   "chips": ["gfx10"],
1129   "map": {"at": 1124, "to": "mm"},
1130   "name": "SQ_WAVE_POPS_PACKER",
1131   "type_ref": "SQ_WAVE_POPS_PACKER"
1132  },
1133  {
1134   "chips": ["gfx10"],
1135   "map": {"at": 1128, "to": "mm"},
1136   "name": "SQ_WAVE_SCHED_MODE",
1137   "type_ref": "SQ_WAVE_SCHED_MODE"
1138  },
1139  {
1140   "chips": ["gfx10"],
1141   "map": {"at": 1132, "to": "mm"},
1142   "name": "SQ_WAVE_VGPR_OFFSET",
1143   "type_ref": "SQ_WAVE_VGPR_OFFSET"
1144  },
1145  {
1146   "chips": ["gfx10"],
1147   "map": {"at": 1136, "to": "mm"},
1148   "name": "SQ_WAVE_IB_STS2",
1149   "type_ref": "SQ_WAVE_IB_STS2"
1150  },
1151  {
1152   "chips": ["gfx10"],
1153   "map": {"at": 2480, "to": "mm"},
1154   "name": "SQ_WAVE_TTMP0",
1155   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1156  },
1157  {
1158   "chips": ["gfx10"],
1159   "map": {"at": 2484, "to": "mm"},
1160   "name": "SQ_WAVE_TTMP1",
1161   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1162  },
1163  {
1164   "chips": ["gfx10"],
1165   "map": {"at": 2488, "to": "mm"},
1166   "name": "SQ_WAVE_TTMP2",
1167   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1168  },
1169  {
1170   "chips": ["gfx10"],
1171   "map": {"at": 2492, "to": "mm"},
1172   "name": "SQ_WAVE_TTMP3",
1173   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1174  },
1175  {
1176   "chips": ["gfx10"],
1177   "map": {"at": 2496, "to": "mm"},
1178   "name": "SQ_WAVE_TTMP4",
1179   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1180  },
1181  {
1182   "chips": ["gfx10"],
1183   "map": {"at": 2500, "to": "mm"},
1184   "name": "SQ_WAVE_TTMP5",
1185   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1186  },
1187  {
1188   "chips": ["gfx10"],
1189   "map": {"at": 2504, "to": "mm"},
1190   "name": "SQ_WAVE_TTMP6",
1191   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1192  },
1193  {
1194   "chips": ["gfx10"],
1195   "map": {"at": 2508, "to": "mm"},
1196   "name": "SQ_WAVE_TTMP7",
1197   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1198  },
1199  {
1200   "chips": ["gfx10"],
1201   "map": {"at": 2512, "to": "mm"},
1202   "name": "SQ_WAVE_TTMP8",
1203   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1204  },
1205  {
1206   "chips": ["gfx10"],
1207   "map": {"at": 2516, "to": "mm"},
1208   "name": "SQ_WAVE_TTMP9",
1209   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1210  },
1211  {
1212   "chips": ["gfx10"],
1213   "map": {"at": 2520, "to": "mm"},
1214   "name": "SQ_WAVE_TTMP10",
1215   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1216  },
1217  {
1218   "chips": ["gfx10"],
1219   "map": {"at": 2524, "to": "mm"},
1220   "name": "SQ_WAVE_TTMP11",
1221   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1222  },
1223  {
1224   "chips": ["gfx10"],
1225   "map": {"at": 2528, "to": "mm"},
1226   "name": "SQ_WAVE_TTMP12",
1227   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1228  },
1229  {
1230   "chips": ["gfx10"],
1231   "map": {"at": 2532, "to": "mm"},
1232   "name": "SQ_WAVE_TTMP13",
1233   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1234  },
1235  {
1236   "chips": ["gfx10"],
1237   "map": {"at": 2536, "to": "mm"},
1238   "name": "SQ_WAVE_TTMP14",
1239   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1240  },
1241  {
1242   "chips": ["gfx10"],
1243   "map": {"at": 2540, "to": "mm"},
1244   "name": "SQ_WAVE_TTMP15",
1245   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1246  },
1247  {
1248   "chips": ["gfx10"],
1249   "map": {"at": 2544, "to": "mm"},
1250   "name": "SQ_WAVE_M0",
1251   "type_ref": "SQ_WAVE_M0"
1252  },
1253  {
1254   "chips": ["gfx10"],
1255   "map": {"at": 2552, "to": "mm"},
1256   "name": "SQ_WAVE_EXEC_LO",
1257   "type_ref": "SQ_WAVE_EXEC_LO"
1258  },
1259  {
1260   "chips": ["gfx10"],
1261   "map": {"at": 2556, "to": "mm"},
1262   "name": "SQ_WAVE_EXEC_HI",
1263   "type_ref": "SQ_WAVE_EXEC_HI"
1264  },
1265  {
1266   "chips": ["gfx10"],
1267   "map": {"at": 2560, "to": "mm"},
1268   "name": "SQ_WAVE_FLAT_SCRATCH_LO",
1269   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1270  },
1271  {
1272   "chips": ["gfx10"],
1273   "map": {"at": 2564, "to": "mm"},
1274   "name": "SQ_WAVE_FLAT_SCRATCH_HI",
1275   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1276  },
1277  {
1278   "chips": ["gfx10"],
1279   "map": {"at": 2568, "to": "mm"},
1280   "name": "SQ_WAVE_FLAT_XNACK_MASK",
1281   "type_ref": "SQ_WAVE_FLAT_XNACK_MASK"
1282  },
1283  {
1284   "chips": ["gfx10"],
1285   "map": {"at": 32776, "to": "mm"},
1286   "name": "GRBM_STATUS2",
1287   "type_ref": "GRBM_STATUS2"
1288  },
1289  {
1290   "chips": ["gfx10"],
1291   "map": {"at": 32784, "to": "mm"},
1292   "name": "GRBM_STATUS",
1293   "type_ref": "GRBM_STATUS"
1294  },
1295  {
1296   "chips": ["gfx10"],
1297   "map": {"at": 32788, "to": "mm"},
1298   "name": "GRBM_STATUS_SE0",
1299   "type_ref": "GRBM_STATUS_SE0"
1300  },
1301  {
1302   "chips": ["gfx10"],
1303   "map": {"at": 32792, "to": "mm"},
1304   "name": "GRBM_STATUS_SE1",
1305   "type_ref": "GRBM_STATUS_SE0"
1306  },
1307  {
1308   "chips": ["gfx10"],
1309   "map": {"at": 32796, "to": "mm"},
1310   "name": "GRBM_STATUS3",
1311   "type_ref": "GRBM_STATUS3"
1312  },
1313  {
1314   "chips": ["gfx10"],
1315   "map": {"at": 32824, "to": "mm"},
1316   "name": "GRBM_STATUS_SE2",
1317   "type_ref": "GRBM_STATUS_SE0"
1318  },
1319  {
1320   "chips": ["gfx10"],
1321   "map": {"at": 32828, "to": "mm"},
1322   "name": "GRBM_STATUS_SE3",
1323   "type_ref": "GRBM_STATUS_SE0"
1324  },
1325  {
1326   "chips": ["gfx10"],
1327   "map": {"at": 33296, "to": "mm"},
1328   "name": "CP_CPC_STATUS",
1329   "type_ref": "CP_CPC_STATUS"
1330  },
1331  {
1332   "chips": ["gfx10"],
1333   "map": {"at": 33300, "to": "mm"},
1334   "name": "CP_CPC_BUSY_STAT",
1335   "type_ref": "CP_CPC_BUSY_STAT"
1336  },
1337  {
1338   "chips": ["gfx10"],
1339   "map": {"at": 33304, "to": "mm"},
1340   "name": "CP_CPC_STALLED_STAT1",
1341   "type_ref": "CP_CPC_STALLED_STAT1"
1342  },
1343  {
1344   "chips": ["gfx10"],
1345   "map": {"at": 33308, "to": "mm"},
1346   "name": "CP_CPF_STATUS",
1347   "type_ref": "CP_CPF_STATUS"
1348  },
1349  {
1350   "chips": ["gfx10"],
1351   "map": {"at": 33312, "to": "mm"},
1352   "name": "CP_CPF_BUSY_STAT",
1353   "type_ref": "CP_CPF_BUSY_STAT"
1354  },
1355  {
1356   "chips": ["gfx10"],
1357   "map": {"at": 33316, "to": "mm"},
1358   "name": "CP_CPF_STALLED_STAT1",
1359   "type_ref": "CP_CPF_STALLED_STAT1"
1360  },
1361  {
1362   "chips": ["gfx10"],
1363   "map": {"at": 33320, "to": "mm"},
1364   "name": "CP_CPC_BUSY_STAT2",
1365   "type_ref": "CP_CPC_BUSY_STAT2"
1366  },
1367  {
1368   "chips": ["gfx10"],
1369   "map": {"at": 33324, "to": "mm"},
1370   "name": "CP_CPC_GRBM_FREE_COUNT",
1371   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1372  },
1373  {
1374   "chips": ["gfx10"],
1375   "map": {"at": 33344, "to": "mm"},
1376   "name": "CP_CPC_SCRATCH_INDEX",
1377   "type_ref": "CP_CPC_SCRATCH_INDEX"
1378  },
1379  {
1380   "chips": ["gfx10"],
1381   "map": {"at": 33348, "to": "mm"},
1382   "name": "CP_CPC_SCRATCH_DATA",
1383   "type_ref": "CP_CPC_SCRATCH_DATA"
1384  },
1385  {
1386   "chips": ["gfx10"],
1387   "map": {"at": 33352, "to": "mm"},
1388   "name": "CP_CPF_GRBM_FREE_COUNT",
1389   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1390  },
1391  {
1392   "chips": ["gfx10"],
1393   "map": {"at": 33356, "to": "mm"},
1394   "name": "CP_CPF_BUSY_STAT2",
1395   "type_ref": "CP_CPF_BUSY_STAT2"
1396  },
1397  {
1398   "chips": ["gfx10"],
1399   "map": {"at": 33436, "to": "mm"},
1400   "name": "CP_CPC_HALT_HYST_COUNT",
1401   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1402  },
1403  {
1404   "chips": ["gfx10"],
1405   "map": {"at": 36096, "to": "mm"},
1406   "name": "SQ_THREAD_TRACE_BUF0_BASE",
1407   "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1408  },
1409  {
1410   "chips": ["gfx10"],
1411   "map": {"at": 36100, "to": "mm"},
1412   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1413   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1414  },
1415  {
1416   "chips": ["gfx10"],
1417   "map": {"at": 36104, "to": "mm"},
1418   "name": "SQ_THREAD_TRACE_BUF1_BASE",
1419   "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1420  },
1421  {
1422   "chips": ["gfx10"],
1423   "map": {"at": 36108, "to": "mm"},
1424   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1425   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1426  },
1427  {
1428   "chips": ["gfx10"],
1429   "map": {"at": 36112, "to": "mm"},
1430   "name": "SQ_THREAD_TRACE_WPTR",
1431   "type_ref": "SQ_THREAD_TRACE_WPTR"
1432  },
1433  {
1434   "chips": ["gfx10"],
1435   "map": {"at": 36116, "to": "mm"},
1436   "name": "SQ_THREAD_TRACE_MASK",
1437   "type_ref": "SQ_THREAD_TRACE_MASK"
1438  },
1439  {
1440   "chips": ["gfx10"],
1441   "map": {"at": 36120, "to": "mm"},
1442   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1443   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1444  },
1445  {
1446   "chips": ["gfx10"],
1447   "map": {"at": 36124, "to": "mm"},
1448   "name": "SQ_THREAD_TRACE_CTRL",
1449   "type_ref": "SQ_THREAD_TRACE_CTRL"
1450  },
1451  {
1452   "chips": ["gfx10"],
1453   "map": {"at": 36128, "to": "mm"},
1454   "name": "SQ_THREAD_TRACE_STATUS",
1455   "type_ref": "SQ_THREAD_TRACE_STATUS"
1456  },
1457  {
1458   "chips": ["gfx10"],
1459   "map": {"at": 36132, "to": "mm"},
1460   "name": "SQ_THREAD_TRACE_DROPPED_CNTR",
1461   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1462  },
1463  {
1464   "chips": ["gfx10"],
1465   "map": {"at": 36140, "to": "mm"},
1466   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR",
1467   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1468  },
1469  {
1470   "chips": ["gfx10"],
1471   "map": {"at": 36144, "to": "mm"},
1472   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR",
1473   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1474  },
1475  {
1476   "chips": ["gfx10"],
1477   "map": {"at": 36148, "to": "mm"},
1478   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR",
1479   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1480  },
1481  {
1482   "chips": ["gfx10"],
1483   "map": {"at": 36152, "to": "mm"},
1484   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR",
1485   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1486  },
1487  {
1488   "chips": ["gfx10"],
1489   "map": {"at": 37120, "to": "mm"},
1490   "name": "SPI_CONFIG_CNTL",
1491   "type_ref": "SPI_CONFIG_CNTL"
1492  },
1493  {
1494   "chips": ["gfx10"],
1495   "map": {"at": 39160, "to": "mm"},
1496   "name": "GB_ADDR_CONFIG",
1497   "type_ref": "GB_ADDR_CONFIG"
1498  },
1499  {
1500   "chips": ["gfx10"],
1501   "map": {"at": 39184, "to": "mm"},
1502   "name": "GB_TILE_MODE0",
1503   "type_ref": "GB_TILE_MODE0"
1504  },
1505  {
1506   "chips": ["gfx10"],
1507   "map": {"at": 39188, "to": "mm"},
1508   "name": "GB_TILE_MODE1",
1509   "type_ref": "GB_TILE_MODE0"
1510  },
1511  {
1512   "chips": ["gfx10"],
1513   "map": {"at": 39192, "to": "mm"},
1514   "name": "GB_TILE_MODE2",
1515   "type_ref": "GB_TILE_MODE0"
1516  },
1517  {
1518   "chips": ["gfx10"],
1519   "map": {"at": 39196, "to": "mm"},
1520   "name": "GB_TILE_MODE3",
1521   "type_ref": "GB_TILE_MODE0"
1522  },
1523  {
1524   "chips": ["gfx10"],
1525   "map": {"at": 39200, "to": "mm"},
1526   "name": "GB_TILE_MODE4",
1527   "type_ref": "GB_TILE_MODE0"
1528  },
1529  {
1530   "chips": ["gfx10"],
1531   "map": {"at": 39204, "to": "mm"},
1532   "name": "GB_TILE_MODE5",
1533   "type_ref": "GB_TILE_MODE0"
1534  },
1535  {
1536   "chips": ["gfx10"],
1537   "map": {"at": 39208, "to": "mm"},
1538   "name": "GB_TILE_MODE6",
1539   "type_ref": "GB_TILE_MODE0"
1540  },
1541  {
1542   "chips": ["gfx10"],
1543   "map": {"at": 39212, "to": "mm"},
1544   "name": "GB_TILE_MODE7",
1545   "type_ref": "GB_TILE_MODE0"
1546  },
1547  {
1548   "chips": ["gfx10"],
1549   "map": {"at": 39216, "to": "mm"},
1550   "name": "GB_TILE_MODE8",
1551   "type_ref": "GB_TILE_MODE0"
1552  },
1553  {
1554   "chips": ["gfx10"],
1555   "map": {"at": 39220, "to": "mm"},
1556   "name": "GB_TILE_MODE9",
1557   "type_ref": "GB_TILE_MODE0"
1558  },
1559  {
1560   "chips": ["gfx10"],
1561   "map": {"at": 39224, "to": "mm"},
1562   "name": "GB_TILE_MODE10",
1563   "type_ref": "GB_TILE_MODE0"
1564  },
1565  {
1566   "chips": ["gfx10"],
1567   "map": {"at": 39228, "to": "mm"},
1568   "name": "GB_TILE_MODE11",
1569   "type_ref": "GB_TILE_MODE0"
1570  },
1571  {
1572   "chips": ["gfx10"],
1573   "map": {"at": 39232, "to": "mm"},
1574   "name": "GB_TILE_MODE12",
1575   "type_ref": "GB_TILE_MODE0"
1576  },
1577  {
1578   "chips": ["gfx10"],
1579   "map": {"at": 39236, "to": "mm"},
1580   "name": "GB_TILE_MODE13",
1581   "type_ref": "GB_TILE_MODE0"
1582  },
1583  {
1584   "chips": ["gfx10"],
1585   "map": {"at": 39240, "to": "mm"},
1586   "name": "GB_TILE_MODE14",
1587   "type_ref": "GB_TILE_MODE0"
1588  },
1589  {
1590   "chips": ["gfx10"],
1591   "map": {"at": 39244, "to": "mm"},
1592   "name": "GB_TILE_MODE15",
1593   "type_ref": "GB_TILE_MODE0"
1594  },
1595  {
1596   "chips": ["gfx10"],
1597   "map": {"at": 39248, "to": "mm"},
1598   "name": "GB_TILE_MODE16",
1599   "type_ref": "GB_TILE_MODE0"
1600  },
1601  {
1602   "chips": ["gfx10"],
1603   "map": {"at": 39252, "to": "mm"},
1604   "name": "GB_TILE_MODE17",
1605   "type_ref": "GB_TILE_MODE0"
1606  },
1607  {
1608   "chips": ["gfx10"],
1609   "map": {"at": 39256, "to": "mm"},
1610   "name": "GB_TILE_MODE18",
1611   "type_ref": "GB_TILE_MODE0"
1612  },
1613  {
1614   "chips": ["gfx10"],
1615   "map": {"at": 39260, "to": "mm"},
1616   "name": "GB_TILE_MODE19",
1617   "type_ref": "GB_TILE_MODE0"
1618  },
1619  {
1620   "chips": ["gfx10"],
1621   "map": {"at": 39264, "to": "mm"},
1622   "name": "GB_TILE_MODE20",
1623   "type_ref": "GB_TILE_MODE0"
1624  },
1625  {
1626   "chips": ["gfx10"],
1627   "map": {"at": 39268, "to": "mm"},
1628   "name": "GB_TILE_MODE21",
1629   "type_ref": "GB_TILE_MODE0"
1630  },
1631  {
1632   "chips": ["gfx10"],
1633   "map": {"at": 39272, "to": "mm"},
1634   "name": "GB_TILE_MODE22",
1635   "type_ref": "GB_TILE_MODE0"
1636  },
1637  {
1638   "chips": ["gfx10"],
1639   "map": {"at": 39276, "to": "mm"},
1640   "name": "GB_TILE_MODE23",
1641   "type_ref": "GB_TILE_MODE0"
1642  },
1643  {
1644   "chips": ["gfx10"],
1645   "map": {"at": 39280, "to": "mm"},
1646   "name": "GB_TILE_MODE24",
1647   "type_ref": "GB_TILE_MODE0"
1648  },
1649  {
1650   "chips": ["gfx10"],
1651   "map": {"at": 39284, "to": "mm"},
1652   "name": "GB_TILE_MODE25",
1653   "type_ref": "GB_TILE_MODE0"
1654  },
1655  {
1656   "chips": ["gfx10"],
1657   "map": {"at": 39288, "to": "mm"},
1658   "name": "GB_TILE_MODE26",
1659   "type_ref": "GB_TILE_MODE0"
1660  },
1661  {
1662   "chips": ["gfx10"],
1663   "map": {"at": 39292, "to": "mm"},
1664   "name": "GB_TILE_MODE27",
1665   "type_ref": "GB_TILE_MODE0"
1666  },
1667  {
1668   "chips": ["gfx10"],
1669   "map": {"at": 39296, "to": "mm"},
1670   "name": "GB_TILE_MODE28",
1671   "type_ref": "GB_TILE_MODE0"
1672  },
1673  {
1674   "chips": ["gfx10"],
1675   "map": {"at": 39300, "to": "mm"},
1676   "name": "GB_TILE_MODE29",
1677   "type_ref": "GB_TILE_MODE0"
1678  },
1679  {
1680   "chips": ["gfx10"],
1681   "map": {"at": 39304, "to": "mm"},
1682   "name": "GB_TILE_MODE30",
1683   "type_ref": "GB_TILE_MODE0"
1684  },
1685  {
1686   "chips": ["gfx10"],
1687   "map": {"at": 39308, "to": "mm"},
1688   "name": "GB_TILE_MODE31",
1689   "type_ref": "GB_TILE_MODE0"
1690  },
1691  {
1692   "chips": ["gfx10"],
1693   "map": {"at": 39312, "to": "mm"},
1694   "name": "GB_MACROTILE_MODE0",
1695   "type_ref": "GB_MACROTILE_MODE0"
1696  },
1697  {
1698   "chips": ["gfx10"],
1699   "map": {"at": 39316, "to": "mm"},
1700   "name": "GB_MACROTILE_MODE1",
1701   "type_ref": "GB_MACROTILE_MODE0"
1702  },
1703  {
1704   "chips": ["gfx10"],
1705   "map": {"at": 39320, "to": "mm"},
1706   "name": "GB_MACROTILE_MODE2",
1707   "type_ref": "GB_MACROTILE_MODE0"
1708  },
1709  {
1710   "chips": ["gfx10"],
1711   "map": {"at": 39324, "to": "mm"},
1712   "name": "GB_MACROTILE_MODE3",
1713   "type_ref": "GB_MACROTILE_MODE0"
1714  },
1715  {
1716   "chips": ["gfx10"],
1717   "map": {"at": 39328, "to": "mm"},
1718   "name": "GB_MACROTILE_MODE4",
1719   "type_ref": "GB_MACROTILE_MODE0"
1720  },
1721  {
1722   "chips": ["gfx10"],
1723   "map": {"at": 39332, "to": "mm"},
1724   "name": "GB_MACROTILE_MODE5",
1725   "type_ref": "GB_MACROTILE_MODE0"
1726  },
1727  {
1728   "chips": ["gfx10"],
1729   "map": {"at": 39336, "to": "mm"},
1730   "name": "GB_MACROTILE_MODE6",
1731   "type_ref": "GB_MACROTILE_MODE0"
1732  },
1733  {
1734   "chips": ["gfx10"],
1735   "map": {"at": 39340, "to": "mm"},
1736   "name": "GB_MACROTILE_MODE7",
1737   "type_ref": "GB_MACROTILE_MODE0"
1738  },
1739  {
1740   "chips": ["gfx10"],
1741   "map": {"at": 39344, "to": "mm"},
1742   "name": "GB_MACROTILE_MODE8",
1743   "type_ref": "GB_MACROTILE_MODE0"
1744  },
1745  {
1746   "chips": ["gfx10"],
1747   "map": {"at": 39348, "to": "mm"},
1748   "name": "GB_MACROTILE_MODE9",
1749   "type_ref": "GB_MACROTILE_MODE0"
1750  },
1751  {
1752   "chips": ["gfx10"],
1753   "map": {"at": 39352, "to": "mm"},
1754   "name": "GB_MACROTILE_MODE10",
1755   "type_ref": "GB_MACROTILE_MODE0"
1756  },
1757  {
1758   "chips": ["gfx10"],
1759   "map": {"at": 39356, "to": "mm"},
1760   "name": "GB_MACROTILE_MODE11",
1761   "type_ref": "GB_MACROTILE_MODE0"
1762  },
1763  {
1764   "chips": ["gfx10"],
1765   "map": {"at": 39360, "to": "mm"},
1766   "name": "GB_MACROTILE_MODE12",
1767   "type_ref": "GB_MACROTILE_MODE0"
1768  },
1769  {
1770   "chips": ["gfx10"],
1771   "map": {"at": 39364, "to": "mm"},
1772   "name": "GB_MACROTILE_MODE13",
1773   "type_ref": "GB_MACROTILE_MODE0"
1774  },
1775  {
1776   "chips": ["gfx10"],
1777   "map": {"at": 39368, "to": "mm"},
1778   "name": "GB_MACROTILE_MODE14",
1779   "type_ref": "GB_MACROTILE_MODE0"
1780  },
1781  {
1782   "chips": ["gfx10"],
1783   "map": {"at": 39372, "to": "mm"},
1784   "name": "GB_MACROTILE_MODE15",
1785   "type_ref": "GB_MACROTILE_MODE0"
1786  },
1787  {
1788   "chips": ["gfx10"],
1789   "map": {"at": 45060, "to": "mm"},
1790   "name": "SPI_SHADER_PGM_RSRC4_PS",
1791   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1792  },
1793  {
1794   "chips": ["gfx10"],
1795   "map": {"at": 45080, "to": "mm"},
1796   "name": "SPI_SHADER_PGM_CHKSUM_PS",
1797   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
1798  },
1799  {
1800   "chips": ["gfx10"],
1801   "map": {"at": 45084, "to": "mm"},
1802   "name": "SPI_SHADER_PGM_RSRC3_PS",
1803   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1804  },
1805  {
1806   "chips": ["gfx10"],
1807   "map": {"at": 45088, "to": "mm"},
1808   "name": "SPI_SHADER_PGM_LO_PS",
1809   "type_ref": "SPI_SHADER_PGM_LO_PS"
1810  },
1811  {
1812   "chips": ["gfx10"],
1813   "map": {"at": 45092, "to": "mm"},
1814   "name": "SPI_SHADER_PGM_HI_PS",
1815   "type_ref": "SPI_SHADER_PGM_HI_PS"
1816  },
1817  {
1818   "chips": ["gfx10"],
1819   "map": {"at": 45096, "to": "mm"},
1820   "name": "SPI_SHADER_PGM_RSRC1_PS",
1821   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1822  },
1823  {
1824   "chips": ["gfx10"],
1825   "map": {"at": 45100, "to": "mm"},
1826   "name": "SPI_SHADER_PGM_RSRC2_PS",
1827   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1828  },
1829  {
1830   "chips": ["gfx10"],
1831   "map": {"at": 45104, "to": "mm"},
1832   "name": "SPI_SHADER_USER_DATA_PS_0",
1833   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1834  },
1835  {
1836   "chips": ["gfx10"],
1837   "map": {"at": 45108, "to": "mm"},
1838   "name": "SPI_SHADER_USER_DATA_PS_1",
1839   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1840  },
1841  {
1842   "chips": ["gfx10"],
1843   "map": {"at": 45112, "to": "mm"},
1844   "name": "SPI_SHADER_USER_DATA_PS_2",
1845   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1846  },
1847  {
1848   "chips": ["gfx10"],
1849   "map": {"at": 45116, "to": "mm"},
1850   "name": "SPI_SHADER_USER_DATA_PS_3",
1851   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1852  },
1853  {
1854   "chips": ["gfx10"],
1855   "map": {"at": 45120, "to": "mm"},
1856   "name": "SPI_SHADER_USER_DATA_PS_4",
1857   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1858  },
1859  {
1860   "chips": ["gfx10"],
1861   "map": {"at": 45124, "to": "mm"},
1862   "name": "SPI_SHADER_USER_DATA_PS_5",
1863   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1864  },
1865  {
1866   "chips": ["gfx10"],
1867   "map": {"at": 45128, "to": "mm"},
1868   "name": "SPI_SHADER_USER_DATA_PS_6",
1869   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1870  },
1871  {
1872   "chips": ["gfx10"],
1873   "map": {"at": 45132, "to": "mm"},
1874   "name": "SPI_SHADER_USER_DATA_PS_7",
1875   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1876  },
1877  {
1878   "chips": ["gfx10"],
1879   "map": {"at": 45136, "to": "mm"},
1880   "name": "SPI_SHADER_USER_DATA_PS_8",
1881   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1882  },
1883  {
1884   "chips": ["gfx10"],
1885   "map": {"at": 45140, "to": "mm"},
1886   "name": "SPI_SHADER_USER_DATA_PS_9",
1887   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1888  },
1889  {
1890   "chips": ["gfx10"],
1891   "map": {"at": 45144, "to": "mm"},
1892   "name": "SPI_SHADER_USER_DATA_PS_10",
1893   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1894  },
1895  {
1896   "chips": ["gfx10"],
1897   "map": {"at": 45148, "to": "mm"},
1898   "name": "SPI_SHADER_USER_DATA_PS_11",
1899   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1900  },
1901  {
1902   "chips": ["gfx10"],
1903   "map": {"at": 45152, "to": "mm"},
1904   "name": "SPI_SHADER_USER_DATA_PS_12",
1905   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1906  },
1907  {
1908   "chips": ["gfx10"],
1909   "map": {"at": 45156, "to": "mm"},
1910   "name": "SPI_SHADER_USER_DATA_PS_13",
1911   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1912  },
1913  {
1914   "chips": ["gfx10"],
1915   "map": {"at": 45160, "to": "mm"},
1916   "name": "SPI_SHADER_USER_DATA_PS_14",
1917   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1918  },
1919  {
1920   "chips": ["gfx10"],
1921   "map": {"at": 45164, "to": "mm"},
1922   "name": "SPI_SHADER_USER_DATA_PS_15",
1923   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1924  },
1925  {
1926   "chips": ["gfx10"],
1927   "map": {"at": 45168, "to": "mm"},
1928   "name": "SPI_SHADER_USER_DATA_PS_16",
1929   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1930  },
1931  {
1932   "chips": ["gfx10"],
1933   "map": {"at": 45172, "to": "mm"},
1934   "name": "SPI_SHADER_USER_DATA_PS_17",
1935   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1936  },
1937  {
1938   "chips": ["gfx10"],
1939   "map": {"at": 45176, "to": "mm"},
1940   "name": "SPI_SHADER_USER_DATA_PS_18",
1941   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1942  },
1943  {
1944   "chips": ["gfx10"],
1945   "map": {"at": 45180, "to": "mm"},
1946   "name": "SPI_SHADER_USER_DATA_PS_19",
1947   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1948  },
1949  {
1950   "chips": ["gfx10"],
1951   "map": {"at": 45184, "to": "mm"},
1952   "name": "SPI_SHADER_USER_DATA_PS_20",
1953   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1954  },
1955  {
1956   "chips": ["gfx10"],
1957   "map": {"at": 45188, "to": "mm"},
1958   "name": "SPI_SHADER_USER_DATA_PS_21",
1959   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1960  },
1961  {
1962   "chips": ["gfx10"],
1963   "map": {"at": 45192, "to": "mm"},
1964   "name": "SPI_SHADER_USER_DATA_PS_22",
1965   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1966  },
1967  {
1968   "chips": ["gfx10"],
1969   "map": {"at": 45196, "to": "mm"},
1970   "name": "SPI_SHADER_USER_DATA_PS_23",
1971   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1972  },
1973  {
1974   "chips": ["gfx10"],
1975   "map": {"at": 45200, "to": "mm"},
1976   "name": "SPI_SHADER_USER_DATA_PS_24",
1977   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1978  },
1979  {
1980   "chips": ["gfx10"],
1981   "map": {"at": 45204, "to": "mm"},
1982   "name": "SPI_SHADER_USER_DATA_PS_25",
1983   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1984  },
1985  {
1986   "chips": ["gfx10"],
1987   "map": {"at": 45208, "to": "mm"},
1988   "name": "SPI_SHADER_USER_DATA_PS_26",
1989   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1990  },
1991  {
1992   "chips": ["gfx10"],
1993   "map": {"at": 45212, "to": "mm"},
1994   "name": "SPI_SHADER_USER_DATA_PS_27",
1995   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1996  },
1997  {
1998   "chips": ["gfx10"],
1999   "map": {"at": 45216, "to": "mm"},
2000   "name": "SPI_SHADER_USER_DATA_PS_28",
2001   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2002  },
2003  {
2004   "chips": ["gfx10"],
2005   "map": {"at": 45220, "to": "mm"},
2006   "name": "SPI_SHADER_USER_DATA_PS_29",
2007   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2008  },
2009  {
2010   "chips": ["gfx10"],
2011   "map": {"at": 45224, "to": "mm"},
2012   "name": "SPI_SHADER_USER_DATA_PS_30",
2013   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2014  },
2015  {
2016   "chips": ["gfx10"],
2017   "map": {"at": 45228, "to": "mm"},
2018   "name": "SPI_SHADER_USER_DATA_PS_31",
2019   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2020  },
2021  {
2022   "chips": ["gfx10"],
2023   "map": {"at": 45248, "to": "mm"},
2024   "name": "SPI_SHADER_REQ_CTRL_PS",
2025   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2026  },
2027  {
2028   "chips": ["gfx10"],
2029   "map": {"at": 45252, "to": "mm"},
2030   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS",
2031   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2032  },
2033  {
2034   "chips": ["gfx10"],
2035   "map": {"at": 45256, "to": "mm"},
2036   "name": "SPI_SHADER_USER_ACCUM_PS_0",
2037   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2038  },
2039  {
2040   "chips": ["gfx10"],
2041   "map": {"at": 45260, "to": "mm"},
2042   "name": "SPI_SHADER_USER_ACCUM_PS_1",
2043   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2044  },
2045  {
2046   "chips": ["gfx10"],
2047   "map": {"at": 45264, "to": "mm"},
2048   "name": "SPI_SHADER_USER_ACCUM_PS_2",
2049   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2050  },
2051  {
2052   "chips": ["gfx10"],
2053   "map": {"at": 45268, "to": "mm"},
2054   "name": "SPI_SHADER_USER_ACCUM_PS_3",
2055   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2056  },
2057  {
2058   "chips": ["gfx10"],
2059   "map": {"at": 45316, "to": "mm"},
2060   "name": "SPI_SHADER_PGM_RSRC4_VS",
2061   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2062  },
2063  {
2064   "chips": ["gfx10"],
2065   "map": {"at": 45332, "to": "mm"},
2066   "name": "SPI_SHADER_PGM_CHKSUM_VS",
2067   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2068  },
2069  {
2070   "chips": ["gfx10"],
2071   "map": {"at": 45336, "to": "mm"},
2072   "name": "SPI_SHADER_PGM_RSRC3_VS",
2073   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2074  },
2075  {
2076   "chips": ["gfx10"],
2077   "map": {"at": 45340, "to": "mm"},
2078   "name": "SPI_SHADER_LATE_ALLOC_VS",
2079   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
2080  },
2081  {
2082   "chips": ["gfx10"],
2083   "map": {"at": 45344, "to": "mm"},
2084   "name": "SPI_SHADER_PGM_LO_VS",
2085   "type_ref": "SPI_SHADER_PGM_LO_PS"
2086  },
2087  {
2088   "chips": ["gfx10"],
2089   "map": {"at": 45348, "to": "mm"},
2090   "name": "SPI_SHADER_PGM_HI_VS",
2091   "type_ref": "SPI_SHADER_PGM_HI_PS"
2092  },
2093  {
2094   "chips": ["gfx10"],
2095   "map": {"at": 45352, "to": "mm"},
2096   "name": "SPI_SHADER_PGM_RSRC1_VS",
2097   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2098  },
2099  {
2100   "chips": ["gfx10"],
2101   "map": {"at": 45356, "to": "mm"},
2102   "name": "SPI_SHADER_PGM_RSRC2_VS",
2103   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2104  },
2105  {
2106   "chips": ["gfx10"],
2107   "map": {"at": 45360, "to": "mm"},
2108   "name": "SPI_SHADER_USER_DATA_VS_0",
2109   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2110  },
2111  {
2112   "chips": ["gfx10"],
2113   "map": {"at": 45364, "to": "mm"},
2114   "name": "SPI_SHADER_USER_DATA_VS_1",
2115   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2116  },
2117  {
2118   "chips": ["gfx10"],
2119   "map": {"at": 45368, "to": "mm"},
2120   "name": "SPI_SHADER_USER_DATA_VS_2",
2121   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2122  },
2123  {
2124   "chips": ["gfx10"],
2125   "map": {"at": 45372, "to": "mm"},
2126   "name": "SPI_SHADER_USER_DATA_VS_3",
2127   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2128  },
2129  {
2130   "chips": ["gfx10"],
2131   "map": {"at": 45376, "to": "mm"},
2132   "name": "SPI_SHADER_USER_DATA_VS_4",
2133   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2134  },
2135  {
2136   "chips": ["gfx10"],
2137   "map": {"at": 45380, "to": "mm"},
2138   "name": "SPI_SHADER_USER_DATA_VS_5",
2139   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2140  },
2141  {
2142   "chips": ["gfx10"],
2143   "map": {"at": 45384, "to": "mm"},
2144   "name": "SPI_SHADER_USER_DATA_VS_6",
2145   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2146  },
2147  {
2148   "chips": ["gfx10"],
2149   "map": {"at": 45388, "to": "mm"},
2150   "name": "SPI_SHADER_USER_DATA_VS_7",
2151   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2152  },
2153  {
2154   "chips": ["gfx10"],
2155   "map": {"at": 45392, "to": "mm"},
2156   "name": "SPI_SHADER_USER_DATA_VS_8",
2157   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2158  },
2159  {
2160   "chips": ["gfx10"],
2161   "map": {"at": 45396, "to": "mm"},
2162   "name": "SPI_SHADER_USER_DATA_VS_9",
2163   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2164  },
2165  {
2166   "chips": ["gfx10"],
2167   "map": {"at": 45400, "to": "mm"},
2168   "name": "SPI_SHADER_USER_DATA_VS_10",
2169   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2170  },
2171  {
2172   "chips": ["gfx10"],
2173   "map": {"at": 45404, "to": "mm"},
2174   "name": "SPI_SHADER_USER_DATA_VS_11",
2175   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2176  },
2177  {
2178   "chips": ["gfx10"],
2179   "map": {"at": 45408, "to": "mm"},
2180   "name": "SPI_SHADER_USER_DATA_VS_12",
2181   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2182  },
2183  {
2184   "chips": ["gfx10"],
2185   "map": {"at": 45412, "to": "mm"},
2186   "name": "SPI_SHADER_USER_DATA_VS_13",
2187   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2188  },
2189  {
2190   "chips": ["gfx10"],
2191   "map": {"at": 45416, "to": "mm"},
2192   "name": "SPI_SHADER_USER_DATA_VS_14",
2193   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2194  },
2195  {
2196   "chips": ["gfx10"],
2197   "map": {"at": 45420, "to": "mm"},
2198   "name": "SPI_SHADER_USER_DATA_VS_15",
2199   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2200  },
2201  {
2202   "chips": ["gfx10"],
2203   "map": {"at": 45424, "to": "mm"},
2204   "name": "SPI_SHADER_USER_DATA_VS_16",
2205   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2206  },
2207  {
2208   "chips": ["gfx10"],
2209   "map": {"at": 45428, "to": "mm"},
2210   "name": "SPI_SHADER_USER_DATA_VS_17",
2211   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2212  },
2213  {
2214   "chips": ["gfx10"],
2215   "map": {"at": 45432, "to": "mm"},
2216   "name": "SPI_SHADER_USER_DATA_VS_18",
2217   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2218  },
2219  {
2220   "chips": ["gfx10"],
2221   "map": {"at": 45436, "to": "mm"},
2222   "name": "SPI_SHADER_USER_DATA_VS_19",
2223   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2224  },
2225  {
2226   "chips": ["gfx10"],
2227   "map": {"at": 45440, "to": "mm"},
2228   "name": "SPI_SHADER_USER_DATA_VS_20",
2229   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2230  },
2231  {
2232   "chips": ["gfx10"],
2233   "map": {"at": 45444, "to": "mm"},
2234   "name": "SPI_SHADER_USER_DATA_VS_21",
2235   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2236  },
2237  {
2238   "chips": ["gfx10"],
2239   "map": {"at": 45448, "to": "mm"},
2240   "name": "SPI_SHADER_USER_DATA_VS_22",
2241   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2242  },
2243  {
2244   "chips": ["gfx10"],
2245   "map": {"at": 45452, "to": "mm"},
2246   "name": "SPI_SHADER_USER_DATA_VS_23",
2247   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2248  },
2249  {
2250   "chips": ["gfx10"],
2251   "map": {"at": 45456, "to": "mm"},
2252   "name": "SPI_SHADER_USER_DATA_VS_24",
2253   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2254  },
2255  {
2256   "chips": ["gfx10"],
2257   "map": {"at": 45460, "to": "mm"},
2258   "name": "SPI_SHADER_USER_DATA_VS_25",
2259   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2260  },
2261  {
2262   "chips": ["gfx10"],
2263   "map": {"at": 45464, "to": "mm"},
2264   "name": "SPI_SHADER_USER_DATA_VS_26",
2265   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2266  },
2267  {
2268   "chips": ["gfx10"],
2269   "map": {"at": 45468, "to": "mm"},
2270   "name": "SPI_SHADER_USER_DATA_VS_27",
2271   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2272  },
2273  {
2274   "chips": ["gfx10"],
2275   "map": {"at": 45472, "to": "mm"},
2276   "name": "SPI_SHADER_USER_DATA_VS_28",
2277   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2278  },
2279  {
2280   "chips": ["gfx10"],
2281   "map": {"at": 45476, "to": "mm"},
2282   "name": "SPI_SHADER_USER_DATA_VS_29",
2283   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2284  },
2285  {
2286   "chips": ["gfx10"],
2287   "map": {"at": 45480, "to": "mm"},
2288   "name": "SPI_SHADER_USER_DATA_VS_30",
2289   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2290  },
2291  {
2292   "chips": ["gfx10"],
2293   "map": {"at": 45484, "to": "mm"},
2294   "name": "SPI_SHADER_USER_DATA_VS_31",
2295   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2296  },
2297  {
2298   "chips": ["gfx10"],
2299   "map": {"at": 45504, "to": "mm"},
2300   "name": "SPI_SHADER_REQ_CTRL_VS",
2301   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2302  },
2303  {
2304   "chips": ["gfx10"],
2305   "map": {"at": 45508, "to": "mm"},
2306   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_VS",
2307   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2308  },
2309  {
2310   "chips": ["gfx10"],
2311   "map": {"at": 45512, "to": "mm"},
2312   "name": "SPI_SHADER_USER_ACCUM_VS_0",
2313   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2314  },
2315  {
2316   "chips": ["gfx10"],
2317   "map": {"at": 45516, "to": "mm"},
2318   "name": "SPI_SHADER_USER_ACCUM_VS_1",
2319   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2320  },
2321  {
2322   "chips": ["gfx10"],
2323   "map": {"at": 45520, "to": "mm"},
2324   "name": "SPI_SHADER_USER_ACCUM_VS_2",
2325   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2326  },
2327  {
2328   "chips": ["gfx10"],
2329   "map": {"at": 45524, "to": "mm"},
2330   "name": "SPI_SHADER_USER_ACCUM_VS_3",
2331   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2332  },
2333  {
2334   "chips": ["gfx10"],
2335   "map": {"at": 45548, "to": "mm"},
2336   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
2337   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
2338  },
2339  {
2340   "chips": ["gfx10"],
2341   "map": {"at": 45552, "to": "mm"},
2342   "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2343   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2344  },
2345  {
2346   "chips": ["gfx10"],
2347   "map": {"at": 45556, "to": "mm"},
2348   "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2349   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2350  },
2351  {
2352   "chips": ["gfx10"],
2353   "map": {"at": 45568, "to": "mm"},
2354   "name": "SPI_SHADER_PGM_CHKSUM_GS",
2355   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2356  },
2357  {
2358   "chips": ["gfx10"],
2359   "map": {"at": 45572, "to": "mm"},
2360   "name": "SPI_SHADER_PGM_RSRC4_GS",
2361   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
2362  },
2363  {
2364   "chips": ["gfx10"],
2365   "map": {"at": 45576, "to": "mm"},
2366   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS",
2367   "type_ref": "SPI_SHADER_PGM_LO_PS"
2368  },
2369  {
2370   "chips": ["gfx10"],
2371   "map": {"at": 45580, "to": "mm"},
2372   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS",
2373   "type_ref": "SPI_SHADER_PGM_LO_PS"
2374  },
2375  {
2376   "chips": ["gfx10"],
2377   "map": {"at": 45584, "to": "mm"},
2378   "name": "SPI_SHADER_PGM_LO_ES_GS",
2379   "type_ref": "SPI_SHADER_PGM_LO_PS"
2380  },
2381  {
2382   "chips": ["gfx10"],
2383   "map": {"at": 45588, "to": "mm"},
2384   "name": "SPI_SHADER_PGM_HI_ES_GS",
2385   "type_ref": "SPI_SHADER_PGM_HI_PS"
2386  },
2387  {
2388   "chips": ["gfx10"],
2389   "map": {"at": 45596, "to": "mm"},
2390   "name": "SPI_SHADER_PGM_RSRC3_GS",
2391   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2392  },
2393  {
2394   "chips": ["gfx10"],
2395   "map": {"at": 45600, "to": "mm"},
2396   "name": "SPI_SHADER_PGM_LO_GS",
2397   "type_ref": "SPI_SHADER_PGM_LO_PS"
2398  },
2399  {
2400   "chips": ["gfx10"],
2401   "map": {"at": 45604, "to": "mm"},
2402   "name": "SPI_SHADER_PGM_HI_GS",
2403   "type_ref": "SPI_SHADER_PGM_HI_PS"
2404  },
2405  {
2406   "chips": ["gfx10"],
2407   "map": {"at": 45608, "to": "mm"},
2408   "name": "SPI_SHADER_PGM_RSRC1_GS",
2409   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2410  },
2411  {
2412   "chips": ["gfx10"],
2413   "map": {"at": 45612, "to": "mm"},
2414   "name": "SPI_SHADER_PGM_RSRC2_GS",
2415   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2416  },
2417  {
2418   "chips": ["gfx10"],
2419   "map": {"at": 45616, "to": "mm"},
2420   "name": "SPI_SHADER_USER_DATA_GS_0",
2421   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2422  },
2423  {
2424   "chips": ["gfx10"],
2425   "map": {"at": 45620, "to": "mm"},
2426   "name": "SPI_SHADER_USER_DATA_GS_1",
2427   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2428  },
2429  {
2430   "chips": ["gfx10"],
2431   "map": {"at": 45624, "to": "mm"},
2432   "name": "SPI_SHADER_USER_DATA_GS_2",
2433   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2434  },
2435  {
2436   "chips": ["gfx10"],
2437   "map": {"at": 45628, "to": "mm"},
2438   "name": "SPI_SHADER_USER_DATA_GS_3",
2439   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2440  },
2441  {
2442   "chips": ["gfx10"],
2443   "map": {"at": 45632, "to": "mm"},
2444   "name": "SPI_SHADER_USER_DATA_GS_4",
2445   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2446  },
2447  {
2448   "chips": ["gfx10"],
2449   "map": {"at": 45636, "to": "mm"},
2450   "name": "SPI_SHADER_USER_DATA_GS_5",
2451   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2452  },
2453  {
2454   "chips": ["gfx10"],
2455   "map": {"at": 45640, "to": "mm"},
2456   "name": "SPI_SHADER_USER_DATA_GS_6",
2457   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2458  },
2459  {
2460   "chips": ["gfx10"],
2461   "map": {"at": 45644, "to": "mm"},
2462   "name": "SPI_SHADER_USER_DATA_GS_7",
2463   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2464  },
2465  {
2466   "chips": ["gfx10"],
2467   "map": {"at": 45648, "to": "mm"},
2468   "name": "SPI_SHADER_USER_DATA_GS_8",
2469   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2470  },
2471  {
2472   "chips": ["gfx10"],
2473   "map": {"at": 45652, "to": "mm"},
2474   "name": "SPI_SHADER_USER_DATA_GS_9",
2475   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2476  },
2477  {
2478   "chips": ["gfx10"],
2479   "map": {"at": 45656, "to": "mm"},
2480   "name": "SPI_SHADER_USER_DATA_GS_10",
2481   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2482  },
2483  {
2484   "chips": ["gfx10"],
2485   "map": {"at": 45660, "to": "mm"},
2486   "name": "SPI_SHADER_USER_DATA_GS_11",
2487   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2488  },
2489  {
2490   "chips": ["gfx10"],
2491   "map": {"at": 45664, "to": "mm"},
2492   "name": "SPI_SHADER_USER_DATA_GS_12",
2493   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2494  },
2495  {
2496   "chips": ["gfx10"],
2497   "map": {"at": 45668, "to": "mm"},
2498   "name": "SPI_SHADER_USER_DATA_GS_13",
2499   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2500  },
2501  {
2502   "chips": ["gfx10"],
2503   "map": {"at": 45672, "to": "mm"},
2504   "name": "SPI_SHADER_USER_DATA_GS_14",
2505   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2506  },
2507  {
2508   "chips": ["gfx10"],
2509   "map": {"at": 45676, "to": "mm"},
2510   "name": "SPI_SHADER_USER_DATA_GS_15",
2511   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2512  },
2513  {
2514   "chips": ["gfx10"],
2515   "map": {"at": 45680, "to": "mm"},
2516   "name": "SPI_SHADER_USER_DATA_GS_16",
2517   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2518  },
2519  {
2520   "chips": ["gfx10"],
2521   "map": {"at": 45684, "to": "mm"},
2522   "name": "SPI_SHADER_USER_DATA_GS_17",
2523   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2524  },
2525  {
2526   "chips": ["gfx10"],
2527   "map": {"at": 45688, "to": "mm"},
2528   "name": "SPI_SHADER_USER_DATA_GS_18",
2529   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2530  },
2531  {
2532   "chips": ["gfx10"],
2533   "map": {"at": 45692, "to": "mm"},
2534   "name": "SPI_SHADER_USER_DATA_GS_19",
2535   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2536  },
2537  {
2538   "chips": ["gfx10"],
2539   "map": {"at": 45696, "to": "mm"},
2540   "name": "SPI_SHADER_USER_DATA_GS_20",
2541   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2542  },
2543  {
2544   "chips": ["gfx10"],
2545   "map": {"at": 45700, "to": "mm"},
2546   "name": "SPI_SHADER_USER_DATA_GS_21",
2547   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2548  },
2549  {
2550   "chips": ["gfx10"],
2551   "map": {"at": 45704, "to": "mm"},
2552   "name": "SPI_SHADER_USER_DATA_GS_22",
2553   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2554  },
2555  {
2556   "chips": ["gfx10"],
2557   "map": {"at": 45708, "to": "mm"},
2558   "name": "SPI_SHADER_USER_DATA_GS_23",
2559   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2560  },
2561  {
2562   "chips": ["gfx10"],
2563   "map": {"at": 45712, "to": "mm"},
2564   "name": "SPI_SHADER_USER_DATA_GS_24",
2565   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2566  },
2567  {
2568   "chips": ["gfx10"],
2569   "map": {"at": 45716, "to": "mm"},
2570   "name": "SPI_SHADER_USER_DATA_GS_25",
2571   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2572  },
2573  {
2574   "chips": ["gfx10"],
2575   "map": {"at": 45720, "to": "mm"},
2576   "name": "SPI_SHADER_USER_DATA_GS_26",
2577   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2578  },
2579  {
2580   "chips": ["gfx10"],
2581   "map": {"at": 45724, "to": "mm"},
2582   "name": "SPI_SHADER_USER_DATA_GS_27",
2583   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2584  },
2585  {
2586   "chips": ["gfx10"],
2587   "map": {"at": 45728, "to": "mm"},
2588   "name": "SPI_SHADER_USER_DATA_GS_28",
2589   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2590  },
2591  {
2592   "chips": ["gfx10"],
2593   "map": {"at": 45732, "to": "mm"},
2594   "name": "SPI_SHADER_USER_DATA_GS_29",
2595   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2596  },
2597  {
2598   "chips": ["gfx10"],
2599   "map": {"at": 45736, "to": "mm"},
2600   "name": "SPI_SHADER_USER_DATA_GS_30",
2601   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2602  },
2603  {
2604   "chips": ["gfx10"],
2605   "map": {"at": 45740, "to": "mm"},
2606   "name": "SPI_SHADER_USER_DATA_GS_31",
2607   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2608  },
2609  {
2610   "chips": ["gfx10"],
2611   "map": {"at": 45760, "to": "mm"},
2612   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2613   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2614  },
2615  {
2616   "chips": ["gfx10"],
2617   "map": {"at": 45764, "to": "mm"},
2618   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS",
2619   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
2620  },
2621  {
2622   "chips": ["gfx10"],
2623   "map": {"at": 45768, "to": "mm"},
2624   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2625   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2626  },
2627  {
2628   "chips": ["gfx10"],
2629   "map": {"at": 45772, "to": "mm"},
2630   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2631   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2632  },
2633  {
2634   "chips": ["gfx10"],
2635   "map": {"at": 45776, "to": "mm"},
2636   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2637   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2638  },
2639  {
2640   "chips": ["gfx10"],
2641   "map": {"at": 45780, "to": "mm"},
2642   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2643   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2644  },
2645  {
2646   "chips": ["gfx10"],
2647   "map": {"at": 45808, "to": "mm"},
2648   "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2649   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2650  },
2651  {
2652   "chips": ["gfx10"],
2653   "map": {"at": 45852, "to": "mm"},
2654   "name": "SPI_SHADER_PGM_RSRC3_ES",
2655   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2656  },
2657  {
2658   "chips": ["gfx10"],
2659   "map": {"at": 45856, "to": "mm"},
2660   "name": "SPI_SHADER_PGM_LO_ES",
2661   "type_ref": "SPI_SHADER_PGM_LO_PS"
2662  },
2663  {
2664   "chips": ["gfx10"],
2665   "map": {"at": 45860, "to": "mm"},
2666   "name": "SPI_SHADER_PGM_HI_ES",
2667   "type_ref": "SPI_SHADER_PGM_HI_PS"
2668  },
2669  {
2670   "chips": ["gfx10"],
2671   "map": {"at": 45864, "to": "mm"},
2672   "name": "SPI_SHADER_PGM_RSRC1_ES",
2673   "type_ref": "SPI_SHADER_PGM_RSRC1_ES"
2674  },
2675  {
2676   "chips": ["gfx10"],
2677   "map": {"at": 45868, "to": "mm"},
2678   "name": "SPI_SHADER_PGM_RSRC2_ES",
2679   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2680  },
2681  {
2682   "chips": ["gfx10"],
2683   "map": {"at": 45872, "to": "mm"},
2684   "name": "SPI_SHADER_USER_DATA_ES_0",
2685   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2686  },
2687  {
2688   "chips": ["gfx10"],
2689   "map": {"at": 45876, "to": "mm"},
2690   "name": "SPI_SHADER_USER_DATA_ES_1",
2691   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2692  },
2693  {
2694   "chips": ["gfx10"],
2695   "map": {"at": 45880, "to": "mm"},
2696   "name": "SPI_SHADER_USER_DATA_ES_2",
2697   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2698  },
2699  {
2700   "chips": ["gfx10"],
2701   "map": {"at": 45884, "to": "mm"},
2702   "name": "SPI_SHADER_USER_DATA_ES_3",
2703   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2704  },
2705  {
2706   "chips": ["gfx10"],
2707   "map": {"at": 45888, "to": "mm"},
2708   "name": "SPI_SHADER_USER_DATA_ES_4",
2709   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2710  },
2711  {
2712   "chips": ["gfx10"],
2713   "map": {"at": 45892, "to": "mm"},
2714   "name": "SPI_SHADER_USER_DATA_ES_5",
2715   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2716  },
2717  {
2718   "chips": ["gfx10"],
2719   "map": {"at": 45896, "to": "mm"},
2720   "name": "SPI_SHADER_USER_DATA_ES_6",
2721   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2722  },
2723  {
2724   "chips": ["gfx10"],
2725   "map": {"at": 45900, "to": "mm"},
2726   "name": "SPI_SHADER_USER_DATA_ES_7",
2727   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2728  },
2729  {
2730   "chips": ["gfx10"],
2731   "map": {"at": 45904, "to": "mm"},
2732   "name": "SPI_SHADER_USER_DATA_ES_8",
2733   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2734  },
2735  {
2736   "chips": ["gfx10"],
2737   "map": {"at": 45908, "to": "mm"},
2738   "name": "SPI_SHADER_USER_DATA_ES_9",
2739   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2740  },
2741  {
2742   "chips": ["gfx10"],
2743   "map": {"at": 45912, "to": "mm"},
2744   "name": "SPI_SHADER_USER_DATA_ES_10",
2745   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2746  },
2747  {
2748   "chips": ["gfx10"],
2749   "map": {"at": 45916, "to": "mm"},
2750   "name": "SPI_SHADER_USER_DATA_ES_11",
2751   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2752  },
2753  {
2754   "chips": ["gfx10"],
2755   "map": {"at": 45920, "to": "mm"},
2756   "name": "SPI_SHADER_USER_DATA_ES_12",
2757   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2758  },
2759  {
2760   "chips": ["gfx10"],
2761   "map": {"at": 45924, "to": "mm"},
2762   "name": "SPI_SHADER_USER_DATA_ES_13",
2763   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2764  },
2765  {
2766   "chips": ["gfx10"],
2767   "map": {"at": 45928, "to": "mm"},
2768   "name": "SPI_SHADER_USER_DATA_ES_14",
2769   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2770  },
2771  {
2772   "chips": ["gfx10"],
2773   "map": {"at": 45932, "to": "mm"},
2774   "name": "SPI_SHADER_USER_DATA_ES_15",
2775   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2776  },
2777  {
2778   "chips": ["gfx10"],
2779   "map": {"at": 46068, "to": "mm"},
2780   "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2781   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2782  },
2783  {
2784   "chips": ["gfx10"],
2785   "map": {"at": 46080, "to": "mm"},
2786   "name": "SPI_SHADER_PGM_CHKSUM_HS",
2787   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2788  },
2789  {
2790   "chips": ["gfx10"],
2791   "map": {"at": 46084, "to": "mm"},
2792   "name": "SPI_SHADER_PGM_RSRC4_HS",
2793   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2794  },
2795  {
2796   "chips": ["gfx10"],
2797   "map": {"at": 46088, "to": "mm"},
2798   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS",
2799   "type_ref": "SPI_SHADER_PGM_LO_PS"
2800  },
2801  {
2802   "chips": ["gfx10"],
2803   "map": {"at": 46092, "to": "mm"},
2804   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS",
2805   "type_ref": "SPI_SHADER_PGM_LO_PS"
2806  },
2807  {
2808   "chips": ["gfx10"],
2809   "map": {"at": 46096, "to": "mm"},
2810   "name": "SPI_SHADER_PGM_LO_LS_HS",
2811   "type_ref": "SPI_SHADER_PGM_LO_PS"
2812  },
2813  {
2814   "chips": ["gfx10"],
2815   "map": {"at": 46100, "to": "mm"},
2816   "name": "SPI_SHADER_PGM_HI_LS_HS",
2817   "type_ref": "SPI_SHADER_PGM_HI_PS"
2818  },
2819  {
2820   "chips": ["gfx10"],
2821   "map": {"at": 46108, "to": "mm"},
2822   "name": "SPI_SHADER_PGM_RSRC3_HS",
2823   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2824  },
2825  {
2826   "chips": ["gfx10"],
2827   "map": {"at": 46112, "to": "mm"},
2828   "name": "SPI_SHADER_PGM_LO_HS",
2829   "type_ref": "SPI_SHADER_PGM_LO_PS"
2830  },
2831  {
2832   "chips": ["gfx10"],
2833   "map": {"at": 46116, "to": "mm"},
2834   "name": "SPI_SHADER_PGM_HI_HS",
2835   "type_ref": "SPI_SHADER_PGM_HI_PS"
2836  },
2837  {
2838   "chips": ["gfx10"],
2839   "map": {"at": 46120, "to": "mm"},
2840   "name": "SPI_SHADER_PGM_RSRC1_HS",
2841   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2842  },
2843  {
2844   "chips": ["gfx10"],
2845   "map": {"at": 46124, "to": "mm"},
2846   "name": "SPI_SHADER_PGM_RSRC2_HS",
2847   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2848  },
2849  {
2850   "chips": ["gfx10"],
2851   "map": {"at": 46128, "to": "mm"},
2852   "name": "SPI_SHADER_USER_DATA_HS_0",
2853   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2854  },
2855  {
2856   "chips": ["gfx10"],
2857   "map": {"at": 46132, "to": "mm"},
2858   "name": "SPI_SHADER_USER_DATA_HS_1",
2859   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2860  },
2861  {
2862   "chips": ["gfx10"],
2863   "map": {"at": 46136, "to": "mm"},
2864   "name": "SPI_SHADER_USER_DATA_HS_2",
2865   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2866  },
2867  {
2868   "chips": ["gfx10"],
2869   "map": {"at": 46140, "to": "mm"},
2870   "name": "SPI_SHADER_USER_DATA_HS_3",
2871   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2872  },
2873  {
2874   "chips": ["gfx10"],
2875   "map": {"at": 46144, "to": "mm"},
2876   "name": "SPI_SHADER_USER_DATA_HS_4",
2877   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2878  },
2879  {
2880   "chips": ["gfx10"],
2881   "map": {"at": 46148, "to": "mm"},
2882   "name": "SPI_SHADER_USER_DATA_HS_5",
2883   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2884  },
2885  {
2886   "chips": ["gfx10"],
2887   "map": {"at": 46152, "to": "mm"},
2888   "name": "SPI_SHADER_USER_DATA_HS_6",
2889   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2890  },
2891  {
2892   "chips": ["gfx10"],
2893   "map": {"at": 46156, "to": "mm"},
2894   "name": "SPI_SHADER_USER_DATA_HS_7",
2895   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2896  },
2897  {
2898   "chips": ["gfx10"],
2899   "map": {"at": 46160, "to": "mm"},
2900   "name": "SPI_SHADER_USER_DATA_HS_8",
2901   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2902  },
2903  {
2904   "chips": ["gfx10"],
2905   "map": {"at": 46164, "to": "mm"},
2906   "name": "SPI_SHADER_USER_DATA_HS_9",
2907   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2908  },
2909  {
2910   "chips": ["gfx10"],
2911   "map": {"at": 46168, "to": "mm"},
2912   "name": "SPI_SHADER_USER_DATA_HS_10",
2913   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2914  },
2915  {
2916   "chips": ["gfx10"],
2917   "map": {"at": 46172, "to": "mm"},
2918   "name": "SPI_SHADER_USER_DATA_HS_11",
2919   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2920  },
2921  {
2922   "chips": ["gfx10"],
2923   "map": {"at": 46176, "to": "mm"},
2924   "name": "SPI_SHADER_USER_DATA_HS_12",
2925   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2926  },
2927  {
2928   "chips": ["gfx10"],
2929   "map": {"at": 46180, "to": "mm"},
2930   "name": "SPI_SHADER_USER_DATA_HS_13",
2931   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2932  },
2933  {
2934   "chips": ["gfx10"],
2935   "map": {"at": 46184, "to": "mm"},
2936   "name": "SPI_SHADER_USER_DATA_HS_14",
2937   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2938  },
2939  {
2940   "chips": ["gfx10"],
2941   "map": {"at": 46188, "to": "mm"},
2942   "name": "SPI_SHADER_USER_DATA_HS_15",
2943   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2944  },
2945  {
2946   "chips": ["gfx10"],
2947   "map": {"at": 46192, "to": "mm"},
2948   "name": "SPI_SHADER_USER_DATA_HS_16",
2949   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2950  },
2951  {
2952   "chips": ["gfx10"],
2953   "map": {"at": 46196, "to": "mm"},
2954   "name": "SPI_SHADER_USER_DATA_HS_17",
2955   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2956  },
2957  {
2958   "chips": ["gfx10"],
2959   "map": {"at": 46200, "to": "mm"},
2960   "name": "SPI_SHADER_USER_DATA_HS_18",
2961   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2962  },
2963  {
2964   "chips": ["gfx10"],
2965   "map": {"at": 46204, "to": "mm"},
2966   "name": "SPI_SHADER_USER_DATA_HS_19",
2967   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2968  },
2969  {
2970   "chips": ["gfx10"],
2971   "map": {"at": 46208, "to": "mm"},
2972   "name": "SPI_SHADER_USER_DATA_HS_20",
2973   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2974  },
2975  {
2976   "chips": ["gfx10"],
2977   "map": {"at": 46212, "to": "mm"},
2978   "name": "SPI_SHADER_USER_DATA_HS_21",
2979   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2980  },
2981  {
2982   "chips": ["gfx10"],
2983   "map": {"at": 46216, "to": "mm"},
2984   "name": "SPI_SHADER_USER_DATA_HS_22",
2985   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2986  },
2987  {
2988   "chips": ["gfx10"],
2989   "map": {"at": 46220, "to": "mm"},
2990   "name": "SPI_SHADER_USER_DATA_HS_23",
2991   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2992  },
2993  {
2994   "chips": ["gfx10"],
2995   "map": {"at": 46224, "to": "mm"},
2996   "name": "SPI_SHADER_USER_DATA_HS_24",
2997   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2998  },
2999  {
3000   "chips": ["gfx10"],
3001   "map": {"at": 46228, "to": "mm"},
3002   "name": "SPI_SHADER_USER_DATA_HS_25",
3003   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3004  },
3005  {
3006   "chips": ["gfx10"],
3007   "map": {"at": 46232, "to": "mm"},
3008   "name": "SPI_SHADER_USER_DATA_HS_26",
3009   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3010  },
3011  {
3012   "chips": ["gfx10"],
3013   "map": {"at": 46236, "to": "mm"},
3014   "name": "SPI_SHADER_USER_DATA_HS_27",
3015   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3016  },
3017  {
3018   "chips": ["gfx10"],
3019   "map": {"at": 46240, "to": "mm"},
3020   "name": "SPI_SHADER_USER_DATA_HS_28",
3021   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3022  },
3023  {
3024   "chips": ["gfx10"],
3025   "map": {"at": 46244, "to": "mm"},
3026   "name": "SPI_SHADER_USER_DATA_HS_29",
3027   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3028  },
3029  {
3030   "chips": ["gfx10"],
3031   "map": {"at": 46248, "to": "mm"},
3032   "name": "SPI_SHADER_USER_DATA_HS_30",
3033   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3034  },
3035  {
3036   "chips": ["gfx10"],
3037   "map": {"at": 46252, "to": "mm"},
3038   "name": "SPI_SHADER_USER_DATA_HS_31",
3039   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3040  },
3041  {
3042   "chips": ["gfx10"],
3043   "map": {"at": 46272, "to": "mm"},
3044   "name": "SPI_SHADER_REQ_CTRL_LSHS",
3045   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
3046  },
3047  {
3048   "chips": ["gfx10"],
3049   "map": {"at": 46276, "to": "mm"},
3050   "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS",
3051   "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS"
3052  },
3053  {
3054   "chips": ["gfx10"],
3055   "map": {"at": 46280, "to": "mm"},
3056   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
3057   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3058  },
3059  {
3060   "chips": ["gfx10"],
3061   "map": {"at": 46284, "to": "mm"},
3062   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
3063   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3064  },
3065  {
3066   "chips": ["gfx10"],
3067   "map": {"at": 46288, "to": "mm"},
3068   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
3069   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3070  },
3071  {
3072   "chips": ["gfx10"],
3073   "map": {"at": 46292, "to": "mm"},
3074   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
3075   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3076  },
3077  {
3078   "chips": ["gfx10"],
3079   "map": {"at": 46324, "to": "mm"},
3080   "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
3081   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
3082  },
3083  {
3084   "chips": ["gfx10"],
3085   "map": {"at": 46364, "to": "mm"},
3086   "name": "SPI_SHADER_PGM_RSRC3_LS",
3087   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
3088  },
3089  {
3090   "chips": ["gfx10"],
3091   "map": {"at": 46368, "to": "mm"},
3092   "name": "SPI_SHADER_PGM_LO_LS",
3093   "type_ref": "SPI_SHADER_PGM_LO_PS"
3094  },
3095  {
3096   "chips": ["gfx10"],
3097   "map": {"at": 46372, "to": "mm"},
3098   "name": "SPI_SHADER_PGM_HI_LS",
3099   "type_ref": "SPI_SHADER_PGM_HI_PS"
3100  },
3101  {
3102   "chips": ["gfx10"],
3103   "map": {"at": 46376, "to": "mm"},
3104   "name": "SPI_SHADER_PGM_RSRC1_LS",
3105   "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
3106  },
3107  {
3108   "chips": ["gfx10"],
3109   "map": {"at": 46380, "to": "mm"},
3110   "name": "SPI_SHADER_PGM_RSRC2_LS",
3111   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
3112  },
3113  {
3114   "chips": ["gfx10"],
3115   "map": {"at": 46384, "to": "mm"},
3116   "name": "SPI_SHADER_USER_DATA_LS_0",
3117   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3118  },
3119  {
3120   "chips": ["gfx10"],
3121   "map": {"at": 46388, "to": "mm"},
3122   "name": "SPI_SHADER_USER_DATA_LS_1",
3123   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3124  },
3125  {
3126   "chips": ["gfx10"],
3127   "map": {"at": 46392, "to": "mm"},
3128   "name": "SPI_SHADER_USER_DATA_LS_2",
3129   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3130  },
3131  {
3132   "chips": ["gfx10"],
3133   "map": {"at": 46396, "to": "mm"},
3134   "name": "SPI_SHADER_USER_DATA_LS_3",
3135   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3136  },
3137  {
3138   "chips": ["gfx10"],
3139   "map": {"at": 46400, "to": "mm"},
3140   "name": "SPI_SHADER_USER_DATA_LS_4",
3141   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3142  },
3143  {
3144   "chips": ["gfx10"],
3145   "map": {"at": 46404, "to": "mm"},
3146   "name": "SPI_SHADER_USER_DATA_LS_5",
3147   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3148  },
3149  {
3150   "chips": ["gfx10"],
3151   "map": {"at": 46408, "to": "mm"},
3152   "name": "SPI_SHADER_USER_DATA_LS_6",
3153   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3154  },
3155  {
3156   "chips": ["gfx10"],
3157   "map": {"at": 46412, "to": "mm"},
3158   "name": "SPI_SHADER_USER_DATA_LS_7",
3159   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3160  },
3161  {
3162   "chips": ["gfx10"],
3163   "map": {"at": 46416, "to": "mm"},
3164   "name": "SPI_SHADER_USER_DATA_LS_8",
3165   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3166  },
3167  {
3168   "chips": ["gfx10"],
3169   "map": {"at": 46420, "to": "mm"},
3170   "name": "SPI_SHADER_USER_DATA_LS_9",
3171   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3172  },
3173  {
3174   "chips": ["gfx10"],
3175   "map": {"at": 46424, "to": "mm"},
3176   "name": "SPI_SHADER_USER_DATA_LS_10",
3177   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3178  },
3179  {
3180   "chips": ["gfx10"],
3181   "map": {"at": 46428, "to": "mm"},
3182   "name": "SPI_SHADER_USER_DATA_LS_11",
3183   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3184  },
3185  {
3186   "chips": ["gfx10"],
3187   "map": {"at": 46432, "to": "mm"},
3188   "name": "SPI_SHADER_USER_DATA_LS_12",
3189   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3190  },
3191  {
3192   "chips": ["gfx10"],
3193   "map": {"at": 46436, "to": "mm"},
3194   "name": "SPI_SHADER_USER_DATA_LS_13",
3195   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3196  },
3197  {
3198   "chips": ["gfx10"],
3199   "map": {"at": 46440, "to": "mm"},
3200   "name": "SPI_SHADER_USER_DATA_LS_14",
3201   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3202  },
3203  {
3204   "chips": ["gfx10"],
3205   "map": {"at": 46444, "to": "mm"},
3206   "name": "SPI_SHADER_USER_DATA_LS_15",
3207   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3208  },
3209  {
3210   "chips": ["gfx10"],
3211   "map": {"at": 47104, "to": "mm"},
3212   "name": "COMPUTE_DISPATCH_INITIATOR",
3213   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
3214  },
3215  {
3216   "chips": ["gfx10"],
3217   "map": {"at": 47108, "to": "mm"},
3218   "name": "COMPUTE_DIM_X",
3219   "type_ref": "COMPUTE_DIM_X"
3220  },
3221  {
3222   "chips": ["gfx10"],
3223   "map": {"at": 47112, "to": "mm"},
3224   "name": "COMPUTE_DIM_Y",
3225   "type_ref": "COMPUTE_DIM_X"
3226  },
3227  {
3228   "chips": ["gfx10"],
3229   "map": {"at": 47116, "to": "mm"},
3230   "name": "COMPUTE_DIM_Z",
3231   "type_ref": "COMPUTE_DIM_X"
3232  },
3233  {
3234   "chips": ["gfx10"],
3235   "map": {"at": 47120, "to": "mm"},
3236   "name": "COMPUTE_START_X",
3237   "type_ref": "COMPUTE_START_X"
3238  },
3239  {
3240   "chips": ["gfx10"],
3241   "map": {"at": 47124, "to": "mm"},
3242   "name": "COMPUTE_START_Y",
3243   "type_ref": "COMPUTE_START_X"
3244  },
3245  {
3246   "chips": ["gfx10"],
3247   "map": {"at": 47128, "to": "mm"},
3248   "name": "COMPUTE_START_Z",
3249   "type_ref": "COMPUTE_START_X"
3250  },
3251  {
3252   "chips": ["gfx10"],
3253   "map": {"at": 47132, "to": "mm"},
3254   "name": "COMPUTE_NUM_THREAD_X",
3255   "type_ref": "COMPUTE_NUM_THREAD_X"
3256  },
3257  {
3258   "chips": ["gfx10"],
3259   "map": {"at": 47136, "to": "mm"},
3260   "name": "COMPUTE_NUM_THREAD_Y",
3261   "type_ref": "COMPUTE_NUM_THREAD_X"
3262  },
3263  {
3264   "chips": ["gfx10"],
3265   "map": {"at": 47140, "to": "mm"},
3266   "name": "COMPUTE_NUM_THREAD_Z",
3267   "type_ref": "COMPUTE_NUM_THREAD_X"
3268  },
3269  {
3270   "chips": ["gfx10"],
3271   "map": {"at": 47144, "to": "mm"},
3272   "name": "COMPUTE_PIPELINESTAT_ENABLE",
3273   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
3274  },
3275  {
3276   "chips": ["gfx10"],
3277   "map": {"at": 47148, "to": "mm"},
3278   "name": "COMPUTE_PERFCOUNT_ENABLE",
3279   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
3280  },
3281  {
3282   "chips": ["gfx10"],
3283   "map": {"at": 47152, "to": "mm"},
3284   "name": "COMPUTE_PGM_LO",
3285   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3286  },
3287  {
3288   "chips": ["gfx10"],
3289   "map": {"at": 47156, "to": "mm"},
3290   "name": "COMPUTE_PGM_HI",
3291   "type_ref": "COMPUTE_PGM_HI"
3292  },
3293  {
3294   "chips": ["gfx10"],
3295   "map": {"at": 47160, "to": "mm"},
3296   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO",
3297   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3298  },
3299  {
3300   "chips": ["gfx10"],
3301   "map": {"at": 47164, "to": "mm"},
3302   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
3303   "type_ref": "COMPUTE_PGM_HI"
3304  },
3305  {
3306   "chips": ["gfx10"],
3307   "map": {"at": 47168, "to": "mm"},
3308   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO",
3309   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3310  },
3311  {
3312   "chips": ["gfx10"],
3313   "map": {"at": 47172, "to": "mm"},
3314   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
3315   "type_ref": "COMPUTE_PGM_HI"
3316  },
3317  {
3318   "chips": ["gfx10"],
3319   "map": {"at": 47176, "to": "mm"},
3320   "name": "COMPUTE_PGM_RSRC1",
3321   "type_ref": "COMPUTE_PGM_RSRC1"
3322  },
3323  {
3324   "chips": ["gfx10"],
3325   "map": {"at": 47180, "to": "mm"},
3326   "name": "COMPUTE_PGM_RSRC2",
3327   "type_ref": "COMPUTE_PGM_RSRC2"
3328  },
3329  {
3330   "chips": ["gfx10"],
3331   "map": {"at": 47184, "to": "mm"},
3332   "name": "COMPUTE_VMID",
3333   "type_ref": "COMPUTE_VMID"
3334  },
3335  {
3336   "chips": ["gfx10"],
3337   "map": {"at": 47188, "to": "mm"},
3338   "name": "COMPUTE_RESOURCE_LIMITS",
3339   "type_ref": "COMPUTE_RESOURCE_LIMITS"
3340  },
3341  {
3342   "chips": ["gfx10"],
3343   "map": {"at": 47192, "to": "mm"},
3344   "name": "COMPUTE_DESTINATION_EN_SE0",
3345   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3346  },
3347  {
3348   "chips": ["gfx10"],
3349   "map": {"at": 47196, "to": "mm"},
3350   "name": "COMPUTE_DESTINATION_EN_SE1",
3351   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3352  },
3353  {
3354   "chips": ["gfx10"],
3355   "map": {"at": 47200, "to": "mm"},
3356   "name": "COMPUTE_TMPRING_SIZE",
3357   "type_ref": "COMPUTE_TMPRING_SIZE"
3358  },
3359  {
3360   "chips": ["gfx10"],
3361   "map": {"at": 47204, "to": "mm"},
3362   "name": "COMPUTE_DESTINATION_EN_SE2",
3363   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3364  },
3365  {
3366   "chips": ["gfx10"],
3367   "map": {"at": 47208, "to": "mm"},
3368   "name": "COMPUTE_DESTINATION_EN_SE3",
3369   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
3370  },
3371  {
3372   "chips": ["gfx10"],
3373   "map": {"at": 47212, "to": "mm"},
3374   "name": "COMPUTE_RESTART_X",
3375   "type_ref": "COMPUTE_RESTART_X"
3376  },
3377  {
3378   "chips": ["gfx10"],
3379   "map": {"at": 47216, "to": "mm"},
3380   "name": "COMPUTE_RESTART_Y",
3381   "type_ref": "COMPUTE_RESTART_X"
3382  },
3383  {
3384   "chips": ["gfx10"],
3385   "map": {"at": 47220, "to": "mm"},
3386   "name": "COMPUTE_RESTART_Z",
3387   "type_ref": "COMPUTE_RESTART_X"
3388  },
3389  {
3390   "chips": ["gfx10"],
3391   "map": {"at": 47224, "to": "mm"},
3392   "name": "COMPUTE_THREAD_TRACE_ENABLE",
3393   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
3394  },
3395  {
3396   "chips": ["gfx10"],
3397   "map": {"at": 47228, "to": "mm"},
3398   "name": "COMPUTE_MISC_RESERVED",
3399   "type_ref": "COMPUTE_MISC_RESERVED"
3400  },
3401  {
3402   "chips": ["gfx10"],
3403   "map": {"at": 47232, "to": "mm"},
3404   "name": "COMPUTE_DISPATCH_ID",
3405   "type_ref": "COMPUTE_DISPATCH_ID"
3406  },
3407  {
3408   "chips": ["gfx10"],
3409   "map": {"at": 47236, "to": "mm"},
3410   "name": "COMPUTE_THREADGROUP_ID",
3411   "type_ref": "COMPUTE_THREADGROUP_ID"
3412  },
3413  {
3414   "chips": ["gfx10"],
3415   "map": {"at": 47240, "to": "mm"},
3416   "name": "COMPUTE_REQ_CTRL",
3417   "type_ref": "COMPUTE_REQ_CTRL"
3418  },
3419  {
3420   "chips": ["gfx10"],
3421   "map": {"at": 47248, "to": "mm"},
3422   "name": "COMPUTE_USER_ACCUM_0",
3423   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3424  },
3425  {
3426   "chips": ["gfx10"],
3427   "map": {"at": 47252, "to": "mm"},
3428   "name": "COMPUTE_USER_ACCUM_1",
3429   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3430  },
3431  {
3432   "chips": ["gfx10"],
3433   "map": {"at": 47256, "to": "mm"},
3434   "name": "COMPUTE_USER_ACCUM_2",
3435   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3436  },
3437  {
3438   "chips": ["gfx10"],
3439   "map": {"at": 47260, "to": "mm"},
3440   "name": "COMPUTE_USER_ACCUM_3",
3441   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
3442  },
3443  {
3444   "chips": ["gfx10"],
3445   "map": {"at": 47264, "to": "mm"},
3446   "name": "COMPUTE_PGM_RSRC3",
3447   "type_ref": "COMPUTE_PGM_RSRC3"
3448  },
3449  {
3450   "chips": ["gfx10"],
3451   "map": {"at": 47268, "to": "mm"},
3452   "name": "COMPUTE_DDID_INDEX",
3453   "type_ref": "COMPUTE_DDID_INDEX"
3454  },
3455  {
3456   "chips": ["gfx10"],
3457   "map": {"at": 47272, "to": "mm"},
3458   "name": "COMPUTE_SHADER_CHKSUM",
3459   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
3460  },
3461  {
3462   "chips": ["gfx10"],
3463   "map": {"at": 47276, "to": "mm"},
3464   "name": "COMPUTE_RELAUNCH",
3465   "type_ref": "COMPUTE_RELAUNCH"
3466  },
3467  {
3468   "chips": ["gfx10"],
3469   "map": {"at": 47280, "to": "mm"},
3470   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO",
3471   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_LO"
3472  },
3473  {
3474   "chips": ["gfx10"],
3475   "map": {"at": 47284, "to": "mm"},
3476   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
3477   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
3478  },
3479  {
3480   "chips": ["gfx10"],
3481   "map": {"at": 47288, "to": "mm"},
3482   "name": "COMPUTE_RELAUNCH2",
3483   "type_ref": "COMPUTE_RELAUNCH"
3484  },
3485  {
3486   "chips": ["gfx10"],
3487   "map": {"at": 47360, "to": "mm"},
3488   "name": "COMPUTE_USER_DATA_0",
3489   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3490  },
3491  {
3492   "chips": ["gfx10"],
3493   "map": {"at": 47364, "to": "mm"},
3494   "name": "COMPUTE_USER_DATA_1",
3495   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3496  },
3497  {
3498   "chips": ["gfx10"],
3499   "map": {"at": 47368, "to": "mm"},
3500   "name": "COMPUTE_USER_DATA_2",
3501   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3502  },
3503  {
3504   "chips": ["gfx10"],
3505   "map": {"at": 47372, "to": "mm"},
3506   "name": "COMPUTE_USER_DATA_3",
3507   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3508  },
3509  {
3510   "chips": ["gfx10"],
3511   "map": {"at": 47376, "to": "mm"},
3512   "name": "COMPUTE_USER_DATA_4",
3513   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3514  },
3515  {
3516   "chips": ["gfx10"],
3517   "map": {"at": 47380, "to": "mm"},
3518   "name": "COMPUTE_USER_DATA_5",
3519   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3520  },
3521  {
3522   "chips": ["gfx10"],
3523   "map": {"at": 47384, "to": "mm"},
3524   "name": "COMPUTE_USER_DATA_6",
3525   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3526  },
3527  {
3528   "chips": ["gfx10"],
3529   "map": {"at": 47388, "to": "mm"},
3530   "name": "COMPUTE_USER_DATA_7",
3531   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3532  },
3533  {
3534   "chips": ["gfx10"],
3535   "map": {"at": 47392, "to": "mm"},
3536   "name": "COMPUTE_USER_DATA_8",
3537   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3538  },
3539  {
3540   "chips": ["gfx10"],
3541   "map": {"at": 47396, "to": "mm"},
3542   "name": "COMPUTE_USER_DATA_9",
3543   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3544  },
3545  {
3546   "chips": ["gfx10"],
3547   "map": {"at": 47400, "to": "mm"},
3548   "name": "COMPUTE_USER_DATA_10",
3549   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3550  },
3551  {
3552   "chips": ["gfx10"],
3553   "map": {"at": 47404, "to": "mm"},
3554   "name": "COMPUTE_USER_DATA_11",
3555   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3556  },
3557  {
3558   "chips": ["gfx10"],
3559   "map": {"at": 47408, "to": "mm"},
3560   "name": "COMPUTE_USER_DATA_12",
3561   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3562  },
3563  {
3564   "chips": ["gfx10"],
3565   "map": {"at": 47412, "to": "mm"},
3566   "name": "COMPUTE_USER_DATA_13",
3567   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3568  },
3569  {
3570   "chips": ["gfx10"],
3571   "map": {"at": 47416, "to": "mm"},
3572   "name": "COMPUTE_USER_DATA_14",
3573   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3574  },
3575  {
3576   "chips": ["gfx10"],
3577   "map": {"at": 47420, "to": "mm"},
3578   "name": "COMPUTE_USER_DATA_15",
3579   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3580  },
3581  {
3582   "chips": ["gfx10"],
3583   "map": {"at": 47604, "to": "mm"},
3584   "name": "COMPUTE_DISPATCH_TUNNEL",
3585   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
3586  },
3587  {
3588   "chips": ["gfx10"],
3589   "map": {"at": 47608, "to": "mm"},
3590   "name": "COMPUTE_DISPATCH_END",
3591   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3592  },
3593  {
3594   "chips": ["gfx10"],
3595   "map": {"at": 47612, "to": "mm"},
3596   "name": "COMPUTE_NOWHERE",
3597   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3598  },
3599  {
3600   "chips": ["gfx10"],
3601   "map": {"at": 163840, "to": "mm"},
3602   "name": "DB_RENDER_CONTROL",
3603   "type_ref": "DB_RENDER_CONTROL"
3604  },
3605  {
3606   "chips": ["gfx10"],
3607   "map": {"at": 163844, "to": "mm"},
3608   "name": "DB_COUNT_CONTROL",
3609   "type_ref": "DB_COUNT_CONTROL"
3610  },
3611  {
3612   "chips": ["gfx10"],
3613   "map": {"at": 163848, "to": "mm"},
3614   "name": "DB_DEPTH_VIEW",
3615   "type_ref": "DB_DEPTH_VIEW"
3616  },
3617  {
3618   "chips": ["gfx10"],
3619   "map": {"at": 163852, "to": "mm"},
3620   "name": "DB_RENDER_OVERRIDE",
3621   "type_ref": "DB_RENDER_OVERRIDE"
3622  },
3623  {
3624   "chips": ["gfx10"],
3625   "map": {"at": 163856, "to": "mm"},
3626   "name": "DB_RENDER_OVERRIDE2",
3627   "type_ref": "DB_RENDER_OVERRIDE2"
3628  },
3629  {
3630   "chips": ["gfx10"],
3631   "map": {"at": 163860, "to": "mm"},
3632   "name": "DB_HTILE_DATA_BASE",
3633   "type_ref": "DB_HTILE_DATA_BASE"
3634  },
3635  {
3636   "chips": ["gfx10"],
3637   "map": {"at": 163868, "to": "mm"},
3638   "name": "DB_DEPTH_SIZE_XY",
3639   "type_ref": "DB_DEPTH_SIZE_XY"
3640  },
3641  {
3642   "chips": ["gfx10"],
3643   "map": {"at": 163872, "to": "mm"},
3644   "name": "DB_DEPTH_BOUNDS_MIN",
3645   "type_ref": "DB_DEPTH_BOUNDS_MIN"
3646  },
3647  {
3648   "chips": ["gfx10"],
3649   "map": {"at": 163876, "to": "mm"},
3650   "name": "DB_DEPTH_BOUNDS_MAX",
3651   "type_ref": "DB_DEPTH_BOUNDS_MAX"
3652  },
3653  {
3654   "chips": ["gfx10"],
3655   "map": {"at": 163880, "to": "mm"},
3656   "name": "DB_STENCIL_CLEAR",
3657   "type_ref": "DB_STENCIL_CLEAR"
3658  },
3659  {
3660   "chips": ["gfx10"],
3661   "map": {"at": 163884, "to": "mm"},
3662   "name": "DB_DEPTH_CLEAR",
3663   "type_ref": "DB_DEPTH_CLEAR"
3664  },
3665  {
3666   "chips": ["gfx10"],
3667   "map": {"at": 163888, "to": "mm"},
3668   "name": "PA_SC_SCREEN_SCISSOR_TL",
3669   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3670  },
3671  {
3672   "chips": ["gfx10"],
3673   "map": {"at": 163892, "to": "mm"},
3674   "name": "PA_SC_SCREEN_SCISSOR_BR",
3675   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3676  },
3677  {
3678   "chips": ["gfx10"],
3679   "map": {"at": 163896, "to": "mm"},
3680   "name": "DB_DFSM_CONTROL",
3681   "type_ref": "DB_DFSM_CONTROL"
3682  },
3683  {
3684   "chips": ["gfx10"],
3685   "map": {"at": 163900, "to": "mm"},
3686   "name": "DB_RESERVED_REG_2",
3687   "type_ref": "DB_RESERVED_REG_2"
3688  },
3689  {
3690   "chips": ["gfx10"],
3691   "map": {"at": 163904, "to": "mm"},
3692   "name": "DB_Z_INFO",
3693   "type_ref": "DB_Z_INFO"
3694  },
3695  {
3696   "chips": ["gfx10"],
3697   "map": {"at": 163908, "to": "mm"},
3698   "name": "DB_STENCIL_INFO",
3699   "type_ref": "DB_STENCIL_INFO"
3700  },
3701  {
3702   "chips": ["gfx10"],
3703   "map": {"at": 163912, "to": "mm"},
3704   "name": "DB_Z_READ_BASE",
3705   "type_ref": "DB_HTILE_DATA_BASE"
3706  },
3707  {
3708   "chips": ["gfx10"],
3709   "map": {"at": 163916, "to": "mm"},
3710   "name": "DB_STENCIL_READ_BASE",
3711   "type_ref": "DB_HTILE_DATA_BASE"
3712  },
3713  {
3714   "chips": ["gfx10"],
3715   "map": {"at": 163920, "to": "mm"},
3716   "name": "DB_Z_WRITE_BASE",
3717   "type_ref": "DB_HTILE_DATA_BASE"
3718  },
3719  {
3720   "chips": ["gfx10"],
3721   "map": {"at": 163924, "to": "mm"},
3722   "name": "DB_STENCIL_WRITE_BASE",
3723   "type_ref": "DB_HTILE_DATA_BASE"
3724  },
3725  {
3726   "chips": ["gfx10"],
3727   "map": {"at": 163928, "to": "mm"},
3728   "name": "DB_RESERVED_REG_1",
3729   "type_ref": "DB_RESERVED_REG_1"
3730  },
3731  {
3732   "chips": ["gfx10"],
3733   "map": {"at": 163932, "to": "mm"},
3734   "name": "DB_RESERVED_REG_3",
3735   "type_ref": "DB_RESERVED_REG_3"
3736  },
3737  {
3738   "chips": ["gfx10"],
3739   "map": {"at": 163944, "to": "mm"},
3740   "name": "DB_Z_READ_BASE_HI",
3741   "type_ref": "DB_Z_READ_BASE_HI"
3742  },
3743  {
3744   "chips": ["gfx10"],
3745   "map": {"at": 163948, "to": "mm"},
3746   "name": "DB_STENCIL_READ_BASE_HI",
3747   "type_ref": "DB_Z_READ_BASE_HI"
3748  },
3749  {
3750   "chips": ["gfx10"],
3751   "map": {"at": 163952, "to": "mm"},
3752   "name": "DB_Z_WRITE_BASE_HI",
3753   "type_ref": "DB_Z_READ_BASE_HI"
3754  },
3755  {
3756   "chips": ["gfx10"],
3757   "map": {"at": 163956, "to": "mm"},
3758   "name": "DB_STENCIL_WRITE_BASE_HI",
3759   "type_ref": "DB_Z_READ_BASE_HI"
3760  },
3761  {
3762   "chips": ["gfx10"],
3763   "map": {"at": 163960, "to": "mm"},
3764   "name": "DB_HTILE_DATA_BASE_HI",
3765   "type_ref": "DB_Z_READ_BASE_HI"
3766  },
3767  {
3768   "chips": ["gfx10"],
3769   "map": {"at": 163964, "to": "mm"},
3770   "name": "DB_RMI_L2_CACHE_CONTROL",
3771   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
3772  },
3773  {
3774   "chips": ["gfx10"],
3775   "map": {"at": 163968, "to": "mm"},
3776   "name": "TA_BC_BASE_ADDR",
3777   "type_ref": "TA_BC_BASE_ADDR"
3778  },
3779  {
3780   "chips": ["gfx10"],
3781   "map": {"at": 163972, "to": "mm"},
3782   "name": "TA_BC_BASE_ADDR_HI",
3783   "type_ref": "TA_BC_BASE_ADDR_HI"
3784  },
3785  {
3786   "chips": ["gfx10"],
3787   "map": {"at": 164328, "to": "mm"},
3788   "name": "COHER_DEST_BASE_HI_0",
3789   "type_ref": "COHER_DEST_BASE_HI_0"
3790  },
3791  {
3792   "chips": ["gfx10"],
3793   "map": {"at": 164332, "to": "mm"},
3794   "name": "COHER_DEST_BASE_HI_1",
3795   "type_ref": "COHER_DEST_BASE_HI_0"
3796  },
3797  {
3798   "chips": ["gfx10"],
3799   "map": {"at": 164336, "to": "mm"},
3800   "name": "COHER_DEST_BASE_HI_2",
3801   "type_ref": "COHER_DEST_BASE_HI_0"
3802  },
3803  {
3804   "chips": ["gfx10"],
3805   "map": {"at": 164340, "to": "mm"},
3806   "name": "COHER_DEST_BASE_HI_3",
3807   "type_ref": "COHER_DEST_BASE_HI_0"
3808  },
3809  {
3810   "chips": ["gfx10"],
3811   "map": {"at": 164344, "to": "mm"},
3812   "name": "COHER_DEST_BASE_2",
3813   "type_ref": "COHER_DEST_BASE_2"
3814  },
3815  {
3816   "chips": ["gfx10"],
3817   "map": {"at": 164348, "to": "mm"},
3818   "name": "COHER_DEST_BASE_3",
3819   "type_ref": "COHER_DEST_BASE_2"
3820  },
3821  {
3822   "chips": ["gfx10"],
3823   "map": {"at": 164352, "to": "mm"},
3824   "name": "PA_SC_WINDOW_OFFSET",
3825   "type_ref": "PA_SC_WINDOW_OFFSET"
3826  },
3827  {
3828   "chips": ["gfx10"],
3829   "map": {"at": 164356, "to": "mm"},
3830   "name": "PA_SC_WINDOW_SCISSOR_TL",
3831   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3832  },
3833  {
3834   "chips": ["gfx10"],
3835   "map": {"at": 164360, "to": "mm"},
3836   "name": "PA_SC_WINDOW_SCISSOR_BR",
3837   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3838  },
3839  {
3840   "chips": ["gfx10"],
3841   "map": {"at": 164364, "to": "mm"},
3842   "name": "PA_SC_CLIPRECT_RULE",
3843   "type_ref": "PA_SC_CLIPRECT_RULE"
3844  },
3845  {
3846   "chips": ["gfx10"],
3847   "map": {"at": 164368, "to": "mm"},
3848   "name": "PA_SC_CLIPRECT_0_TL",
3849   "type_ref": "PA_SC_CLIPRECT_0_TL"
3850  },
3851  {
3852   "chips": ["gfx10"],
3853   "map": {"at": 164372, "to": "mm"},
3854   "name": "PA_SC_CLIPRECT_0_BR",
3855   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3856  },
3857  {
3858   "chips": ["gfx10"],
3859   "map": {"at": 164376, "to": "mm"},
3860   "name": "PA_SC_CLIPRECT_1_TL",
3861   "type_ref": "PA_SC_CLIPRECT_0_TL"
3862  },
3863  {
3864   "chips": ["gfx10"],
3865   "map": {"at": 164380, "to": "mm"},
3866   "name": "PA_SC_CLIPRECT_1_BR",
3867   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3868  },
3869  {
3870   "chips": ["gfx10"],
3871   "map": {"at": 164384, "to": "mm"},
3872   "name": "PA_SC_CLIPRECT_2_TL",
3873   "type_ref": "PA_SC_CLIPRECT_0_TL"
3874  },
3875  {
3876   "chips": ["gfx10"],
3877   "map": {"at": 164388, "to": "mm"},
3878   "name": "PA_SC_CLIPRECT_2_BR",
3879   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3880  },
3881  {
3882   "chips": ["gfx10"],
3883   "map": {"at": 164392, "to": "mm"},
3884   "name": "PA_SC_CLIPRECT_3_TL",
3885   "type_ref": "PA_SC_CLIPRECT_0_TL"
3886  },
3887  {
3888   "chips": ["gfx10"],
3889   "map": {"at": 164396, "to": "mm"},
3890   "name": "PA_SC_CLIPRECT_3_BR",
3891   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3892  },
3893  {
3894   "chips": ["gfx10"],
3895   "map": {"at": 164400, "to": "mm"},
3896   "name": "PA_SC_EDGERULE",
3897   "type_ref": "PA_SC_EDGERULE"
3898  },
3899  {
3900   "chips": ["gfx10"],
3901   "map": {"at": 164404, "to": "mm"},
3902   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3903   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3904  },
3905  {
3906   "chips": ["gfx10"],
3907   "map": {"at": 164408, "to": "mm"},
3908   "name": "CB_TARGET_MASK",
3909   "type_ref": "CB_TARGET_MASK"
3910  },
3911  {
3912   "chips": ["gfx10"],
3913   "map": {"at": 164412, "to": "mm"},
3914   "name": "CB_SHADER_MASK",
3915   "type_ref": "CB_SHADER_MASK"
3916  },
3917  {
3918   "chips": ["gfx10"],
3919   "map": {"at": 164416, "to": "mm"},
3920   "name": "PA_SC_GENERIC_SCISSOR_TL",
3921   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3922  },
3923  {
3924   "chips": ["gfx10"],
3925   "map": {"at": 164420, "to": "mm"},
3926   "name": "PA_SC_GENERIC_SCISSOR_BR",
3927   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3928  },
3929  {
3930   "chips": ["gfx10"],
3931   "map": {"at": 164424, "to": "mm"},
3932   "name": "COHER_DEST_BASE_0",
3933   "type_ref": "COHER_DEST_BASE_2"
3934  },
3935  {
3936   "chips": ["gfx10"],
3937   "map": {"at": 164428, "to": "mm"},
3938   "name": "COHER_DEST_BASE_1",
3939   "type_ref": "COHER_DEST_BASE_2"
3940  },
3941  {
3942   "chips": ["gfx10"],
3943   "map": {"at": 164432, "to": "mm"},
3944   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3945   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3946  },
3947  {
3948   "chips": ["gfx10"],
3949   "map": {"at": 164436, "to": "mm"},
3950   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3951   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3952  },
3953  {
3954   "chips": ["gfx10"],
3955   "map": {"at": 164440, "to": "mm"},
3956   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3957   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3958  },
3959  {
3960   "chips": ["gfx10"],
3961   "map": {"at": 164444, "to": "mm"},
3962   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3963   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3964  },
3965  {
3966   "chips": ["gfx10"],
3967   "map": {"at": 164448, "to": "mm"},
3968   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3969   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3970  },
3971  {
3972   "chips": ["gfx10"],
3973   "map": {"at": 164452, "to": "mm"},
3974   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3975   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3976  },
3977  {
3978   "chips": ["gfx10"],
3979   "map": {"at": 164456, "to": "mm"},
3980   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3981   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3982  },
3983  {
3984   "chips": ["gfx10"],
3985   "map": {"at": 164460, "to": "mm"},
3986   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3987   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3988  },
3989  {
3990   "chips": ["gfx10"],
3991   "map": {"at": 164464, "to": "mm"},
3992   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3993   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3994  },
3995  {
3996   "chips": ["gfx10"],
3997   "map": {"at": 164468, "to": "mm"},
3998   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3999   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4000  },
4001  {
4002   "chips": ["gfx10"],
4003   "map": {"at": 164472, "to": "mm"},
4004   "name": "PA_SC_VPORT_SCISSOR_5_TL",
4005   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4006  },
4007  {
4008   "chips": ["gfx10"],
4009   "map": {"at": 164476, "to": "mm"},
4010   "name": "PA_SC_VPORT_SCISSOR_5_BR",
4011   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4012  },
4013  {
4014   "chips": ["gfx10"],
4015   "map": {"at": 164480, "to": "mm"},
4016   "name": "PA_SC_VPORT_SCISSOR_6_TL",
4017   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4018  },
4019  {
4020   "chips": ["gfx10"],
4021   "map": {"at": 164484, "to": "mm"},
4022   "name": "PA_SC_VPORT_SCISSOR_6_BR",
4023   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4024  },
4025  {
4026   "chips": ["gfx10"],
4027   "map": {"at": 164488, "to": "mm"},
4028   "name": "PA_SC_VPORT_SCISSOR_7_TL",
4029   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4030  },
4031  {
4032   "chips": ["gfx10"],
4033   "map": {"at": 164492, "to": "mm"},
4034   "name": "PA_SC_VPORT_SCISSOR_7_BR",
4035   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4036  },
4037  {
4038   "chips": ["gfx10"],
4039   "map": {"at": 164496, "to": "mm"},
4040   "name": "PA_SC_VPORT_SCISSOR_8_TL",
4041   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4042  },
4043  {
4044   "chips": ["gfx10"],
4045   "map": {"at": 164500, "to": "mm"},
4046   "name": "PA_SC_VPORT_SCISSOR_8_BR",
4047   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4048  },
4049  {
4050   "chips": ["gfx10"],
4051   "map": {"at": 164504, "to": "mm"},
4052   "name": "PA_SC_VPORT_SCISSOR_9_TL",
4053   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4054  },
4055  {
4056   "chips": ["gfx10"],
4057   "map": {"at": 164508, "to": "mm"},
4058   "name": "PA_SC_VPORT_SCISSOR_9_BR",
4059   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4060  },
4061  {
4062   "chips": ["gfx10"],
4063   "map": {"at": 164512, "to": "mm"},
4064   "name": "PA_SC_VPORT_SCISSOR_10_TL",
4065   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4066  },
4067  {
4068   "chips": ["gfx10"],
4069   "map": {"at": 164516, "to": "mm"},
4070   "name": "PA_SC_VPORT_SCISSOR_10_BR",
4071   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4072  },
4073  {
4074   "chips": ["gfx10"],
4075   "map": {"at": 164520, "to": "mm"},
4076   "name": "PA_SC_VPORT_SCISSOR_11_TL",
4077   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4078  },
4079  {
4080   "chips": ["gfx10"],
4081   "map": {"at": 164524, "to": "mm"},
4082   "name": "PA_SC_VPORT_SCISSOR_11_BR",
4083   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4084  },
4085  {
4086   "chips": ["gfx10"],
4087   "map": {"at": 164528, "to": "mm"},
4088   "name": "PA_SC_VPORT_SCISSOR_12_TL",
4089   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4090  },
4091  {
4092   "chips": ["gfx10"],
4093   "map": {"at": 164532, "to": "mm"},
4094   "name": "PA_SC_VPORT_SCISSOR_12_BR",
4095   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4096  },
4097  {
4098   "chips": ["gfx10"],
4099   "map": {"at": 164536, "to": "mm"},
4100   "name": "PA_SC_VPORT_SCISSOR_13_TL",
4101   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4102  },
4103  {
4104   "chips": ["gfx10"],
4105   "map": {"at": 164540, "to": "mm"},
4106   "name": "PA_SC_VPORT_SCISSOR_13_BR",
4107   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4108  },
4109  {
4110   "chips": ["gfx10"],
4111   "map": {"at": 164544, "to": "mm"},
4112   "name": "PA_SC_VPORT_SCISSOR_14_TL",
4113   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4114  },
4115  {
4116   "chips": ["gfx10"],
4117   "map": {"at": 164548, "to": "mm"},
4118   "name": "PA_SC_VPORT_SCISSOR_14_BR",
4119   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4120  },
4121  {
4122   "chips": ["gfx10"],
4123   "map": {"at": 164552, "to": "mm"},
4124   "name": "PA_SC_VPORT_SCISSOR_15_TL",
4125   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
4126  },
4127  {
4128   "chips": ["gfx10"],
4129   "map": {"at": 164556, "to": "mm"},
4130   "name": "PA_SC_VPORT_SCISSOR_15_BR",
4131   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
4132  },
4133  {
4134   "chips": ["gfx10"],
4135   "map": {"at": 164560, "to": "mm"},
4136   "name": "PA_SC_VPORT_ZMIN_0",
4137   "type_ref": "PA_SC_VPORT_ZMIN_0"
4138  },
4139  {
4140   "chips": ["gfx10"],
4141   "map": {"at": 164564, "to": "mm"},
4142   "name": "PA_SC_VPORT_ZMAX_0",
4143   "type_ref": "PA_SC_VPORT_ZMAX_0"
4144  },
4145  {
4146   "chips": ["gfx10"],
4147   "map": {"at": 164568, "to": "mm"},
4148   "name": "PA_SC_VPORT_ZMIN_1",
4149   "type_ref": "PA_SC_VPORT_ZMIN_0"
4150  },
4151  {
4152   "chips": ["gfx10"],
4153   "map": {"at": 164572, "to": "mm"},
4154   "name": "PA_SC_VPORT_ZMAX_1",
4155   "type_ref": "PA_SC_VPORT_ZMAX_0"
4156  },
4157  {
4158   "chips": ["gfx10"],
4159   "map": {"at": 164576, "to": "mm"},
4160   "name": "PA_SC_VPORT_ZMIN_2",
4161   "type_ref": "PA_SC_VPORT_ZMIN_0"
4162  },
4163  {
4164   "chips": ["gfx10"],
4165   "map": {"at": 164580, "to": "mm"},
4166   "name": "PA_SC_VPORT_ZMAX_2",
4167   "type_ref": "PA_SC_VPORT_ZMAX_0"
4168  },
4169  {
4170   "chips": ["gfx10"],
4171   "map": {"at": 164584, "to": "mm"},
4172   "name": "PA_SC_VPORT_ZMIN_3",
4173   "type_ref": "PA_SC_VPORT_ZMIN_0"
4174  },
4175  {
4176   "chips": ["gfx10"],
4177   "map": {"at": 164588, "to": "mm"},
4178   "name": "PA_SC_VPORT_ZMAX_3",
4179   "type_ref": "PA_SC_VPORT_ZMAX_0"
4180  },
4181  {
4182   "chips": ["gfx10"],
4183   "map": {"at": 164592, "to": "mm"},
4184   "name": "PA_SC_VPORT_ZMIN_4",
4185   "type_ref": "PA_SC_VPORT_ZMIN_0"
4186  },
4187  {
4188   "chips": ["gfx10"],
4189   "map": {"at": 164596, "to": "mm"},
4190   "name": "PA_SC_VPORT_ZMAX_4",
4191   "type_ref": "PA_SC_VPORT_ZMAX_0"
4192  },
4193  {
4194   "chips": ["gfx10"],
4195   "map": {"at": 164600, "to": "mm"},
4196   "name": "PA_SC_VPORT_ZMIN_5",
4197   "type_ref": "PA_SC_VPORT_ZMIN_0"
4198  },
4199  {
4200   "chips": ["gfx10"],
4201   "map": {"at": 164604, "to": "mm"},
4202   "name": "PA_SC_VPORT_ZMAX_5",
4203   "type_ref": "PA_SC_VPORT_ZMAX_0"
4204  },
4205  {
4206   "chips": ["gfx10"],
4207   "map": {"at": 164608, "to": "mm"},
4208   "name": "PA_SC_VPORT_ZMIN_6",
4209   "type_ref": "PA_SC_VPORT_ZMIN_0"
4210  },
4211  {
4212   "chips": ["gfx10"],
4213   "map": {"at": 164612, "to": "mm"},
4214   "name": "PA_SC_VPORT_ZMAX_6",
4215   "type_ref": "PA_SC_VPORT_ZMAX_0"
4216  },
4217  {
4218   "chips": ["gfx10"],
4219   "map": {"at": 164616, "to": "mm"},
4220   "name": "PA_SC_VPORT_ZMIN_7",
4221   "type_ref": "PA_SC_VPORT_ZMIN_0"
4222  },
4223  {
4224   "chips": ["gfx10"],
4225   "map": {"at": 164620, "to": "mm"},
4226   "name": "PA_SC_VPORT_ZMAX_7",
4227   "type_ref": "PA_SC_VPORT_ZMAX_0"
4228  },
4229  {
4230   "chips": ["gfx10"],
4231   "map": {"at": 164624, "to": "mm"},
4232   "name": "PA_SC_VPORT_ZMIN_8",
4233   "type_ref": "PA_SC_VPORT_ZMIN_0"
4234  },
4235  {
4236   "chips": ["gfx10"],
4237   "map": {"at": 164628, "to": "mm"},
4238   "name": "PA_SC_VPORT_ZMAX_8",
4239   "type_ref": "PA_SC_VPORT_ZMAX_0"
4240  },
4241  {
4242   "chips": ["gfx10"],
4243   "map": {"at": 164632, "to": "mm"},
4244   "name": "PA_SC_VPORT_ZMIN_9",
4245   "type_ref": "PA_SC_VPORT_ZMIN_0"
4246  },
4247  {
4248   "chips": ["gfx10"],
4249   "map": {"at": 164636, "to": "mm"},
4250   "name": "PA_SC_VPORT_ZMAX_9",
4251   "type_ref": "PA_SC_VPORT_ZMAX_0"
4252  },
4253  {
4254   "chips": ["gfx10"],
4255   "map": {"at": 164640, "to": "mm"},
4256   "name": "PA_SC_VPORT_ZMIN_10",
4257   "type_ref": "PA_SC_VPORT_ZMIN_0"
4258  },
4259  {
4260   "chips": ["gfx10"],
4261   "map": {"at": 164644, "to": "mm"},
4262   "name": "PA_SC_VPORT_ZMAX_10",
4263   "type_ref": "PA_SC_VPORT_ZMAX_0"
4264  },
4265  {
4266   "chips": ["gfx10"],
4267   "map": {"at": 164648, "to": "mm"},
4268   "name": "PA_SC_VPORT_ZMIN_11",
4269   "type_ref": "PA_SC_VPORT_ZMIN_0"
4270  },
4271  {
4272   "chips": ["gfx10"],
4273   "map": {"at": 164652, "to": "mm"},
4274   "name": "PA_SC_VPORT_ZMAX_11",
4275   "type_ref": "PA_SC_VPORT_ZMAX_0"
4276  },
4277  {
4278   "chips": ["gfx10"],
4279   "map": {"at": 164656, "to": "mm"},
4280   "name": "PA_SC_VPORT_ZMIN_12",
4281   "type_ref": "PA_SC_VPORT_ZMIN_0"
4282  },
4283  {
4284   "chips": ["gfx10"],
4285   "map": {"at": 164660, "to": "mm"},
4286   "name": "PA_SC_VPORT_ZMAX_12",
4287   "type_ref": "PA_SC_VPORT_ZMAX_0"
4288  },
4289  {
4290   "chips": ["gfx10"],
4291   "map": {"at": 164664, "to": "mm"},
4292   "name": "PA_SC_VPORT_ZMIN_13",
4293   "type_ref": "PA_SC_VPORT_ZMIN_0"
4294  },
4295  {
4296   "chips": ["gfx10"],
4297   "map": {"at": 164668, "to": "mm"},
4298   "name": "PA_SC_VPORT_ZMAX_13",
4299   "type_ref": "PA_SC_VPORT_ZMAX_0"
4300  },
4301  {
4302   "chips": ["gfx10"],
4303   "map": {"at": 164672, "to": "mm"},
4304   "name": "PA_SC_VPORT_ZMIN_14",
4305   "type_ref": "PA_SC_VPORT_ZMIN_0"
4306  },
4307  {
4308   "chips": ["gfx10"],
4309   "map": {"at": 164676, "to": "mm"},
4310   "name": "PA_SC_VPORT_ZMAX_14",
4311   "type_ref": "PA_SC_VPORT_ZMAX_0"
4312  },
4313  {
4314   "chips": ["gfx10"],
4315   "map": {"at": 164680, "to": "mm"},
4316   "name": "PA_SC_VPORT_ZMIN_15",
4317   "type_ref": "PA_SC_VPORT_ZMIN_0"
4318  },
4319  {
4320   "chips": ["gfx10"],
4321   "map": {"at": 164684, "to": "mm"},
4322   "name": "PA_SC_VPORT_ZMAX_15",
4323   "type_ref": "PA_SC_VPORT_ZMAX_0"
4324  },
4325  {
4326   "chips": ["gfx10"],
4327   "map": {"at": 164688, "to": "mm"},
4328   "name": "PA_SC_RASTER_CONFIG",
4329   "type_ref": "PA_SC_RASTER_CONFIG"
4330  },
4331  {
4332   "chips": ["gfx10"],
4333   "map": {"at": 164692, "to": "mm"},
4334   "name": "PA_SC_RASTER_CONFIG_1",
4335   "type_ref": "PA_SC_RASTER_CONFIG_1"
4336  },
4337  {
4338   "chips": ["gfx10"],
4339   "map": {"at": 164696, "to": "mm"},
4340   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
4341   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
4342  },
4343  {
4344   "chips": ["gfx10"],
4345   "map": {"at": 164700, "to": "mm"},
4346   "name": "PA_SC_TILE_STEERING_OVERRIDE",
4347   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
4348  },
4349  {
4350   "chips": ["gfx10"],
4351   "map": {"at": 164704, "to": "mm"},
4352   "name": "CP_PERFMON_CNTX_CNTL",
4353   "type_ref": "CP_PERFMON_CNTX_CNTL"
4354  },
4355  {
4356   "chips": ["gfx10"],
4357   "map": {"at": 164708, "to": "mm"},
4358   "name": "CP_PIPEID",
4359   "type_ref": "CP_PIPEID"
4360  },
4361  {
4362   "chips": ["gfx10"],
4363   "map": {"at": 164712, "to": "mm"},
4364   "name": "CP_VMID",
4365   "type_ref": "CP_VMID"
4366  },
4367  {
4368   "chips": ["gfx10"],
4369   "map": {"at": 164768, "to": "mm"},
4370   "name": "PA_SC_RIGHT_VERT_GRID",
4371   "type_ref": "PA_SC_RIGHT_VERT_GRID"
4372  },
4373  {
4374   "chips": ["gfx10"],
4375   "map": {"at": 164772, "to": "mm"},
4376   "name": "PA_SC_LEFT_VERT_GRID",
4377   "type_ref": "PA_SC_RIGHT_VERT_GRID"
4378  },
4379  {
4380   "chips": ["gfx10"],
4381   "map": {"at": 164776, "to": "mm"},
4382   "name": "PA_SC_HORIZ_GRID",
4383   "type_ref": "PA_SC_HORIZ_GRID"
4384  },
4385  {
4386   "chips": ["gfx10"],
4387   "map": {"at": 164864, "to": "mm"},
4388   "name": "VGT_MAX_VTX_INDX",
4389   "type_ref": "VGT_MAX_VTX_INDX"
4390  },
4391  {
4392   "chips": ["gfx10"],
4393   "map": {"at": 164868, "to": "mm"},
4394   "name": "VGT_MIN_VTX_INDX",
4395   "type_ref": "VGT_MIN_VTX_INDX"
4396  },
4397  {
4398   "chips": ["gfx10"],
4399   "map": {"at": 164872, "to": "mm"},
4400   "name": "VGT_INDX_OFFSET",
4401   "type_ref": "VGT_INDX_OFFSET"
4402  },
4403  {
4404   "chips": ["gfx10"],
4405   "map": {"at": 164876, "to": "mm"},
4406   "name": "VGT_MULTI_PRIM_IB_RESET_INDX",
4407   "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX"
4408  },
4409  {
4410   "chips": ["gfx10"],
4411   "map": {"at": 164880, "to": "mm"},
4412   "name": "CB_RMI_GL2_CACHE_CONTROL",
4413   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
4414  },
4415  {
4416   "chips": ["gfx10"],
4417   "map": {"at": 164884, "to": "mm"},
4418   "name": "CB_BLEND_RED",
4419   "type_ref": "CB_BLEND_RED"
4420  },
4421  {
4422   "chips": ["gfx10"],
4423   "map": {"at": 164888, "to": "mm"},
4424   "name": "CB_BLEND_GREEN",
4425   "type_ref": "CB_BLEND_GREEN"
4426  },
4427  {
4428   "chips": ["gfx10"],
4429   "map": {"at": 164892, "to": "mm"},
4430   "name": "CB_BLEND_BLUE",
4431   "type_ref": "CB_BLEND_BLUE"
4432  },
4433  {
4434   "chips": ["gfx10"],
4435   "map": {"at": 164896, "to": "mm"},
4436   "name": "CB_BLEND_ALPHA",
4437   "type_ref": "CB_BLEND_ALPHA"
4438  },
4439  {
4440   "chips": ["gfx10"],
4441   "map": {"at": 164900, "to": "mm"},
4442   "name": "CB_DCC_CONTROL",
4443   "type_ref": "CB_DCC_CONTROL"
4444  },
4445  {
4446   "chips": ["gfx10"],
4447   "map": {"at": 164904, "to": "mm"},
4448   "name": "CB_COVERAGE_OUT_CONTROL",
4449   "type_ref": "CB_COVERAGE_OUT_CONTROL"
4450  },
4451  {
4452   "chips": ["gfx10"],
4453   "map": {"at": 164908, "to": "mm"},
4454   "name": "DB_STENCIL_CONTROL",
4455   "type_ref": "DB_STENCIL_CONTROL"
4456  },
4457  {
4458   "chips": ["gfx10"],
4459   "map": {"at": 164912, "to": "mm"},
4460   "name": "DB_STENCILREFMASK",
4461   "type_ref": "DB_STENCILREFMASK"
4462  },
4463  {
4464   "chips": ["gfx10"],
4465   "map": {"at": 164916, "to": "mm"},
4466   "name": "DB_STENCILREFMASK_BF",
4467   "type_ref": "DB_STENCILREFMASK_BF"
4468  },
4469  {
4470   "chips": ["gfx10"],
4471   "map": {"at": 164924, "to": "mm"},
4472   "name": "PA_CL_VPORT_XSCALE",
4473   "type_ref": "PA_CL_VPORT_XSCALE"
4474  },
4475  {
4476   "chips": ["gfx10"],
4477   "map": {"at": 164928, "to": "mm"},
4478   "name": "PA_CL_VPORT_XOFFSET",
4479   "type_ref": "PA_CL_VPORT_XOFFSET"
4480  },
4481  {
4482   "chips": ["gfx10"],
4483   "map": {"at": 164932, "to": "mm"},
4484   "name": "PA_CL_VPORT_YSCALE",
4485   "type_ref": "PA_CL_VPORT_YSCALE"
4486  },
4487  {
4488   "chips": ["gfx10"],
4489   "map": {"at": 164936, "to": "mm"},
4490   "name": "PA_CL_VPORT_YOFFSET",
4491   "type_ref": "PA_CL_VPORT_YOFFSET"
4492  },
4493  {
4494   "chips": ["gfx10"],
4495   "map": {"at": 164940, "to": "mm"},
4496   "name": "PA_CL_VPORT_ZSCALE",
4497   "type_ref": "PA_CL_VPORT_ZSCALE"
4498  },
4499  {
4500   "chips": ["gfx10"],
4501   "map": {"at": 164944, "to": "mm"},
4502   "name": "PA_CL_VPORT_ZOFFSET",
4503   "type_ref": "PA_CL_VPORT_ZOFFSET"
4504  },
4505  {
4506   "chips": ["gfx10"],
4507   "map": {"at": 164948, "to": "mm"},
4508   "name": "PA_CL_VPORT_XSCALE_1",
4509   "type_ref": "PA_CL_VPORT_XSCALE"
4510  },
4511  {
4512   "chips": ["gfx10"],
4513   "map": {"at": 164952, "to": "mm"},
4514   "name": "PA_CL_VPORT_XOFFSET_1",
4515   "type_ref": "PA_CL_VPORT_XOFFSET"
4516  },
4517  {
4518   "chips": ["gfx10"],
4519   "map": {"at": 164956, "to": "mm"},
4520   "name": "PA_CL_VPORT_YSCALE_1",
4521   "type_ref": "PA_CL_VPORT_YSCALE"
4522  },
4523  {
4524   "chips": ["gfx10"],
4525   "map": {"at": 164960, "to": "mm"},
4526   "name": "PA_CL_VPORT_YOFFSET_1",
4527   "type_ref": "PA_CL_VPORT_YOFFSET"
4528  },
4529  {
4530   "chips": ["gfx10"],
4531   "map": {"at": 164964, "to": "mm"},
4532   "name": "PA_CL_VPORT_ZSCALE_1",
4533   "type_ref": "PA_CL_VPORT_ZSCALE"
4534  },
4535  {
4536   "chips": ["gfx10"],
4537   "map": {"at": 164968, "to": "mm"},
4538   "name": "PA_CL_VPORT_ZOFFSET_1",
4539   "type_ref": "PA_CL_VPORT_ZOFFSET"
4540  },
4541  {
4542   "chips": ["gfx10"],
4543   "map": {"at": 164972, "to": "mm"},
4544   "name": "PA_CL_VPORT_XSCALE_2",
4545   "type_ref": "PA_CL_VPORT_XSCALE"
4546  },
4547  {
4548   "chips": ["gfx10"],
4549   "map": {"at": 164976, "to": "mm"},
4550   "name": "PA_CL_VPORT_XOFFSET_2",
4551   "type_ref": "PA_CL_VPORT_XOFFSET"
4552  },
4553  {
4554   "chips": ["gfx10"],
4555   "map": {"at": 164980, "to": "mm"},
4556   "name": "PA_CL_VPORT_YSCALE_2",
4557   "type_ref": "PA_CL_VPORT_YSCALE"
4558  },
4559  {
4560   "chips": ["gfx10"],
4561   "map": {"at": 164984, "to": "mm"},
4562   "name": "PA_CL_VPORT_YOFFSET_2",
4563   "type_ref": "PA_CL_VPORT_YOFFSET"
4564  },
4565  {
4566   "chips": ["gfx10"],
4567   "map": {"at": 164988, "to": "mm"},
4568   "name": "PA_CL_VPORT_ZSCALE_2",
4569   "type_ref": "PA_CL_VPORT_ZSCALE"
4570  },
4571  {
4572   "chips": ["gfx10"],
4573   "map": {"at": 164992, "to": "mm"},
4574   "name": "PA_CL_VPORT_ZOFFSET_2",
4575   "type_ref": "PA_CL_VPORT_ZOFFSET"
4576  },
4577  {
4578   "chips": ["gfx10"],
4579   "map": {"at": 164996, "to": "mm"},
4580   "name": "PA_CL_VPORT_XSCALE_3",
4581   "type_ref": "PA_CL_VPORT_XSCALE"
4582  },
4583  {
4584   "chips": ["gfx10"],
4585   "map": {"at": 165000, "to": "mm"},
4586   "name": "PA_CL_VPORT_XOFFSET_3",
4587   "type_ref": "PA_CL_VPORT_XOFFSET"
4588  },
4589  {
4590   "chips": ["gfx10"],
4591   "map": {"at": 165004, "to": "mm"},
4592   "name": "PA_CL_VPORT_YSCALE_3",
4593   "type_ref": "PA_CL_VPORT_YSCALE"
4594  },
4595  {
4596   "chips": ["gfx10"],
4597   "map": {"at": 165008, "to": "mm"},
4598   "name": "PA_CL_VPORT_YOFFSET_3",
4599   "type_ref": "PA_CL_VPORT_YOFFSET"
4600  },
4601  {
4602   "chips": ["gfx10"],
4603   "map": {"at": 165012, "to": "mm"},
4604   "name": "PA_CL_VPORT_ZSCALE_3",
4605   "type_ref": "PA_CL_VPORT_ZSCALE"
4606  },
4607  {
4608   "chips": ["gfx10"],
4609   "map": {"at": 165016, "to": "mm"},
4610   "name": "PA_CL_VPORT_ZOFFSET_3",
4611   "type_ref": "PA_CL_VPORT_ZOFFSET"
4612  },
4613  {
4614   "chips": ["gfx10"],
4615   "map": {"at": 165020, "to": "mm"},
4616   "name": "PA_CL_VPORT_XSCALE_4",
4617   "type_ref": "PA_CL_VPORT_XSCALE"
4618  },
4619  {
4620   "chips": ["gfx10"],
4621   "map": {"at": 165024, "to": "mm"},
4622   "name": "PA_CL_VPORT_XOFFSET_4",
4623   "type_ref": "PA_CL_VPORT_XOFFSET"
4624  },
4625  {
4626   "chips": ["gfx10"],
4627   "map": {"at": 165028, "to": "mm"},
4628   "name": "PA_CL_VPORT_YSCALE_4",
4629   "type_ref": "PA_CL_VPORT_YSCALE"
4630  },
4631  {
4632   "chips": ["gfx10"],
4633   "map": {"at": 165032, "to": "mm"},
4634   "name": "PA_CL_VPORT_YOFFSET_4",
4635   "type_ref": "PA_CL_VPORT_YOFFSET"
4636  },
4637  {
4638   "chips": ["gfx10"],
4639   "map": {"at": 165036, "to": "mm"},
4640   "name": "PA_CL_VPORT_ZSCALE_4",
4641   "type_ref": "PA_CL_VPORT_ZSCALE"
4642  },
4643  {
4644   "chips": ["gfx10"],
4645   "map": {"at": 165040, "to": "mm"},
4646   "name": "PA_CL_VPORT_ZOFFSET_4",
4647   "type_ref": "PA_CL_VPORT_ZOFFSET"
4648  },
4649  {
4650   "chips": ["gfx10"],
4651   "map": {"at": 165044, "to": "mm"},
4652   "name": "PA_CL_VPORT_XSCALE_5",
4653   "type_ref": "PA_CL_VPORT_XSCALE"
4654  },
4655  {
4656   "chips": ["gfx10"],
4657   "map": {"at": 165048, "to": "mm"},
4658   "name": "PA_CL_VPORT_XOFFSET_5",
4659   "type_ref": "PA_CL_VPORT_XOFFSET"
4660  },
4661  {
4662   "chips": ["gfx10"],
4663   "map": {"at": 165052, "to": "mm"},
4664   "name": "PA_CL_VPORT_YSCALE_5",
4665   "type_ref": "PA_CL_VPORT_YSCALE"
4666  },
4667  {
4668   "chips": ["gfx10"],
4669   "map": {"at": 165056, "to": "mm"},
4670   "name": "PA_CL_VPORT_YOFFSET_5",
4671   "type_ref": "PA_CL_VPORT_YOFFSET"
4672  },
4673  {
4674   "chips": ["gfx10"],
4675   "map": {"at": 165060, "to": "mm"},
4676   "name": "PA_CL_VPORT_ZSCALE_5",
4677   "type_ref": "PA_CL_VPORT_ZSCALE"
4678  },
4679  {
4680   "chips": ["gfx10"],
4681   "map": {"at": 165064, "to": "mm"},
4682   "name": "PA_CL_VPORT_ZOFFSET_5",
4683   "type_ref": "PA_CL_VPORT_ZOFFSET"
4684  },
4685  {
4686   "chips": ["gfx10"],
4687   "map": {"at": 165068, "to": "mm"},
4688   "name": "PA_CL_VPORT_XSCALE_6",
4689   "type_ref": "PA_CL_VPORT_XSCALE"
4690  },
4691  {
4692   "chips": ["gfx10"],
4693   "map": {"at": 165072, "to": "mm"},
4694   "name": "PA_CL_VPORT_XOFFSET_6",
4695   "type_ref": "PA_CL_VPORT_XOFFSET"
4696  },
4697  {
4698   "chips": ["gfx10"],
4699   "map": {"at": 165076, "to": "mm"},
4700   "name": "PA_CL_VPORT_YSCALE_6",
4701   "type_ref": "PA_CL_VPORT_YSCALE"
4702  },
4703  {
4704   "chips": ["gfx10"],
4705   "map": {"at": 165080, "to": "mm"},
4706   "name": "PA_CL_VPORT_YOFFSET_6",
4707   "type_ref": "PA_CL_VPORT_YOFFSET"
4708  },
4709  {
4710   "chips": ["gfx10"],
4711   "map": {"at": 165084, "to": "mm"},
4712   "name": "PA_CL_VPORT_ZSCALE_6",
4713   "type_ref": "PA_CL_VPORT_ZSCALE"
4714  },
4715  {
4716   "chips": ["gfx10"],
4717   "map": {"at": 165088, "to": "mm"},
4718   "name": "PA_CL_VPORT_ZOFFSET_6",
4719   "type_ref": "PA_CL_VPORT_ZOFFSET"
4720  },
4721  {
4722   "chips": ["gfx10"],
4723   "map": {"at": 165092, "to": "mm"},
4724   "name": "PA_CL_VPORT_XSCALE_7",
4725   "type_ref": "PA_CL_VPORT_XSCALE"
4726  },
4727  {
4728   "chips": ["gfx10"],
4729   "map": {"at": 165096, "to": "mm"},
4730   "name": "PA_CL_VPORT_XOFFSET_7",
4731   "type_ref": "PA_CL_VPORT_XOFFSET"
4732  },
4733  {
4734   "chips": ["gfx10"],
4735   "map": {"at": 165100, "to": "mm"},
4736   "name": "PA_CL_VPORT_YSCALE_7",
4737   "type_ref": "PA_CL_VPORT_YSCALE"
4738  },
4739  {
4740   "chips": ["gfx10"],
4741   "map": {"at": 165104, "to": "mm"},
4742   "name": "PA_CL_VPORT_YOFFSET_7",
4743   "type_ref": "PA_CL_VPORT_YOFFSET"
4744  },
4745  {
4746   "chips": ["gfx10"],
4747   "map": {"at": 165108, "to": "mm"},
4748   "name": "PA_CL_VPORT_ZSCALE_7",
4749   "type_ref": "PA_CL_VPORT_ZSCALE"
4750  },
4751  {
4752   "chips": ["gfx10"],
4753   "map": {"at": 165112, "to": "mm"},
4754   "name": "PA_CL_VPORT_ZOFFSET_7",
4755   "type_ref": "PA_CL_VPORT_ZOFFSET"
4756  },
4757  {
4758   "chips": ["gfx10"],
4759   "map": {"at": 165116, "to": "mm"},
4760   "name": "PA_CL_VPORT_XSCALE_8",
4761   "type_ref": "PA_CL_VPORT_XSCALE"
4762  },
4763  {
4764   "chips": ["gfx10"],
4765   "map": {"at": 165120, "to": "mm"},
4766   "name": "PA_CL_VPORT_XOFFSET_8",
4767   "type_ref": "PA_CL_VPORT_XOFFSET"
4768  },
4769  {
4770   "chips": ["gfx10"],
4771   "map": {"at": 165124, "to": "mm"},
4772   "name": "PA_CL_VPORT_YSCALE_8",
4773   "type_ref": "PA_CL_VPORT_YSCALE"
4774  },
4775  {
4776   "chips": ["gfx10"],
4777   "map": {"at": 165128, "to": "mm"},
4778   "name": "PA_CL_VPORT_YOFFSET_8",
4779   "type_ref": "PA_CL_VPORT_YOFFSET"
4780  },
4781  {
4782   "chips": ["gfx10"],
4783   "map": {"at": 165132, "to": "mm"},
4784   "name": "PA_CL_VPORT_ZSCALE_8",
4785   "type_ref": "PA_CL_VPORT_ZSCALE"
4786  },
4787  {
4788   "chips": ["gfx10"],
4789   "map": {"at": 165136, "to": "mm"},
4790   "name": "PA_CL_VPORT_ZOFFSET_8",
4791   "type_ref": "PA_CL_VPORT_ZOFFSET"
4792  },
4793  {
4794   "chips": ["gfx10"],
4795   "map": {"at": 165140, "to": "mm"},
4796   "name": "PA_CL_VPORT_XSCALE_9",
4797   "type_ref": "PA_CL_VPORT_XSCALE"
4798  },
4799  {
4800   "chips": ["gfx10"],
4801   "map": {"at": 165144, "to": "mm"},
4802   "name": "PA_CL_VPORT_XOFFSET_9",
4803   "type_ref": "PA_CL_VPORT_XOFFSET"
4804  },
4805  {
4806   "chips": ["gfx10"],
4807   "map": {"at": 165148, "to": "mm"},
4808   "name": "PA_CL_VPORT_YSCALE_9",
4809   "type_ref": "PA_CL_VPORT_YSCALE"
4810  },
4811  {
4812   "chips": ["gfx10"],
4813   "map": {"at": 165152, "to": "mm"},
4814   "name": "PA_CL_VPORT_YOFFSET_9",
4815   "type_ref": "PA_CL_VPORT_YOFFSET"
4816  },
4817  {
4818   "chips": ["gfx10"],
4819   "map": {"at": 165156, "to": "mm"},
4820   "name": "PA_CL_VPORT_ZSCALE_9",
4821   "type_ref": "PA_CL_VPORT_ZSCALE"
4822  },
4823  {
4824   "chips": ["gfx10"],
4825   "map": {"at": 165160, "to": "mm"},
4826   "name": "PA_CL_VPORT_ZOFFSET_9",
4827   "type_ref": "PA_CL_VPORT_ZOFFSET"
4828  },
4829  {
4830   "chips": ["gfx10"],
4831   "map": {"at": 165164, "to": "mm"},
4832   "name": "PA_CL_VPORT_XSCALE_10",
4833   "type_ref": "PA_CL_VPORT_XSCALE"
4834  },
4835  {
4836   "chips": ["gfx10"],
4837   "map": {"at": 165168, "to": "mm"},
4838   "name": "PA_CL_VPORT_XOFFSET_10",
4839   "type_ref": "PA_CL_VPORT_XOFFSET"
4840  },
4841  {
4842   "chips": ["gfx10"],
4843   "map": {"at": 165172, "to": "mm"},
4844   "name": "PA_CL_VPORT_YSCALE_10",
4845   "type_ref": "PA_CL_VPORT_YSCALE"
4846  },
4847  {
4848   "chips": ["gfx10"],
4849   "map": {"at": 165176, "to": "mm"},
4850   "name": "PA_CL_VPORT_YOFFSET_10",
4851   "type_ref": "PA_CL_VPORT_YOFFSET"
4852  },
4853  {
4854   "chips": ["gfx10"],
4855   "map": {"at": 165180, "to": "mm"},
4856   "name": "PA_CL_VPORT_ZSCALE_10",
4857   "type_ref": "PA_CL_VPORT_ZSCALE"
4858  },
4859  {
4860   "chips": ["gfx10"],
4861   "map": {"at": 165184, "to": "mm"},
4862   "name": "PA_CL_VPORT_ZOFFSET_10",
4863   "type_ref": "PA_CL_VPORT_ZOFFSET"
4864  },
4865  {
4866   "chips": ["gfx10"],
4867   "map": {"at": 165188, "to": "mm"},
4868   "name": "PA_CL_VPORT_XSCALE_11",
4869   "type_ref": "PA_CL_VPORT_XSCALE"
4870  },
4871  {
4872   "chips": ["gfx10"],
4873   "map": {"at": 165192, "to": "mm"},
4874   "name": "PA_CL_VPORT_XOFFSET_11",
4875   "type_ref": "PA_CL_VPORT_XOFFSET"
4876  },
4877  {
4878   "chips": ["gfx10"],
4879   "map": {"at": 165196, "to": "mm"},
4880   "name": "PA_CL_VPORT_YSCALE_11",
4881   "type_ref": "PA_CL_VPORT_YSCALE"
4882  },
4883  {
4884   "chips": ["gfx10"],
4885   "map": {"at": 165200, "to": "mm"},
4886   "name": "PA_CL_VPORT_YOFFSET_11",
4887   "type_ref": "PA_CL_VPORT_YOFFSET"
4888  },
4889  {
4890   "chips": ["gfx10"],
4891   "map": {"at": 165204, "to": "mm"},
4892   "name": "PA_CL_VPORT_ZSCALE_11",
4893   "type_ref": "PA_CL_VPORT_ZSCALE"
4894  },
4895  {
4896   "chips": ["gfx10"],
4897   "map": {"at": 165208, "to": "mm"},
4898   "name": "PA_CL_VPORT_ZOFFSET_11",
4899   "type_ref": "PA_CL_VPORT_ZOFFSET"
4900  },
4901  {
4902   "chips": ["gfx10"],
4903   "map": {"at": 165212, "to": "mm"},
4904   "name": "PA_CL_VPORT_XSCALE_12",
4905   "type_ref": "PA_CL_VPORT_XSCALE"
4906  },
4907  {
4908   "chips": ["gfx10"],
4909   "map": {"at": 165216, "to": "mm"},
4910   "name": "PA_CL_VPORT_XOFFSET_12",
4911   "type_ref": "PA_CL_VPORT_XOFFSET"
4912  },
4913  {
4914   "chips": ["gfx10"],
4915   "map": {"at": 165220, "to": "mm"},
4916   "name": "PA_CL_VPORT_YSCALE_12",
4917   "type_ref": "PA_CL_VPORT_YSCALE"
4918  },
4919  {
4920   "chips": ["gfx10"],
4921   "map": {"at": 165224, "to": "mm"},
4922   "name": "PA_CL_VPORT_YOFFSET_12",
4923   "type_ref": "PA_CL_VPORT_YOFFSET"
4924  },
4925  {
4926   "chips": ["gfx10"],
4927   "map": {"at": 165228, "to": "mm"},
4928   "name": "PA_CL_VPORT_ZSCALE_12",
4929   "type_ref": "PA_CL_VPORT_ZSCALE"
4930  },
4931  {
4932   "chips": ["gfx10"],
4933   "map": {"at": 165232, "to": "mm"},
4934   "name": "PA_CL_VPORT_ZOFFSET_12",
4935   "type_ref": "PA_CL_VPORT_ZOFFSET"
4936  },
4937  {
4938   "chips": ["gfx10"],
4939   "map": {"at": 165236, "to": "mm"},
4940   "name": "PA_CL_VPORT_XSCALE_13",
4941   "type_ref": "PA_CL_VPORT_XSCALE"
4942  },
4943  {
4944   "chips": ["gfx10"],
4945   "map": {"at": 165240, "to": "mm"},
4946   "name": "PA_CL_VPORT_XOFFSET_13",
4947   "type_ref": "PA_CL_VPORT_XOFFSET"
4948  },
4949  {
4950   "chips": ["gfx10"],
4951   "map": {"at": 165244, "to": "mm"},
4952   "name": "PA_CL_VPORT_YSCALE_13",
4953   "type_ref": "PA_CL_VPORT_YSCALE"
4954  },
4955  {
4956   "chips": ["gfx10"],
4957   "map": {"at": 165248, "to": "mm"},
4958   "name": "PA_CL_VPORT_YOFFSET_13",
4959   "type_ref": "PA_CL_VPORT_YOFFSET"
4960  },
4961  {
4962   "chips": ["gfx10"],
4963   "map": {"at": 165252, "to": "mm"},
4964   "name": "PA_CL_VPORT_ZSCALE_13",
4965   "type_ref": "PA_CL_VPORT_ZSCALE"
4966  },
4967  {
4968   "chips": ["gfx10"],
4969   "map": {"at": 165256, "to": "mm"},
4970   "name": "PA_CL_VPORT_ZOFFSET_13",
4971   "type_ref": "PA_CL_VPORT_ZOFFSET"
4972  },
4973  {
4974   "chips": ["gfx10"],
4975   "map": {"at": 165260, "to": "mm"},
4976   "name": "PA_CL_VPORT_XSCALE_14",
4977   "type_ref": "PA_CL_VPORT_XSCALE"
4978  },
4979  {
4980   "chips": ["gfx10"],
4981   "map": {"at": 165264, "to": "mm"},
4982   "name": "PA_CL_VPORT_XOFFSET_14",
4983   "type_ref": "PA_CL_VPORT_XOFFSET"
4984  },
4985  {
4986   "chips": ["gfx10"],
4987   "map": {"at": 165268, "to": "mm"},
4988   "name": "PA_CL_VPORT_YSCALE_14",
4989   "type_ref": "PA_CL_VPORT_YSCALE"
4990  },
4991  {
4992   "chips": ["gfx10"],
4993   "map": {"at": 165272, "to": "mm"},
4994   "name": "PA_CL_VPORT_YOFFSET_14",
4995   "type_ref": "PA_CL_VPORT_YOFFSET"
4996  },
4997  {
4998   "chips": ["gfx10"],
4999   "map": {"at": 165276, "to": "mm"},
5000   "name": "PA_CL_VPORT_ZSCALE_14",
5001   "type_ref": "PA_CL_VPORT_ZSCALE"
5002  },
5003  {
5004   "chips": ["gfx10"],
5005   "map": {"at": 165280, "to": "mm"},
5006   "name": "PA_CL_VPORT_ZOFFSET_14",
5007   "type_ref": "PA_CL_VPORT_ZOFFSET"
5008  },
5009  {
5010   "chips": ["gfx10"],
5011   "map": {"at": 165284, "to": "mm"},
5012   "name": "PA_CL_VPORT_XSCALE_15",
5013   "type_ref": "PA_CL_VPORT_XSCALE"
5014  },
5015  {
5016   "chips": ["gfx10"],
5017   "map": {"at": 165288, "to": "mm"},
5018   "name": "PA_CL_VPORT_XOFFSET_15",
5019   "type_ref": "PA_CL_VPORT_XOFFSET"
5020  },
5021  {
5022   "chips": ["gfx10"],
5023   "map": {"at": 165292, "to": "mm"},
5024   "name": "PA_CL_VPORT_YSCALE_15",
5025   "type_ref": "PA_CL_VPORT_YSCALE"
5026  },
5027  {
5028   "chips": ["gfx10"],
5029   "map": {"at": 165296, "to": "mm"},
5030   "name": "PA_CL_VPORT_YOFFSET_15",
5031   "type_ref": "PA_CL_VPORT_YOFFSET"
5032  },
5033  {
5034   "chips": ["gfx10"],
5035   "map": {"at": 165300, "to": "mm"},
5036   "name": "PA_CL_VPORT_ZSCALE_15",
5037   "type_ref": "PA_CL_VPORT_ZSCALE"
5038  },
5039  {
5040   "chips": ["gfx10"],
5041   "map": {"at": 165304, "to": "mm"},
5042   "name": "PA_CL_VPORT_ZOFFSET_15",
5043   "type_ref": "PA_CL_VPORT_ZOFFSET"
5044  },
5045  {
5046   "chips": ["gfx10"],
5047   "map": {"at": 165308, "to": "mm"},
5048   "name": "PA_CL_UCP_0_X",
5049   "type_ref": "PA_CL_UCP_0_X"
5050  },
5051  {
5052   "chips": ["gfx10"],
5053   "map": {"at": 165312, "to": "mm"},
5054   "name": "PA_CL_UCP_0_Y",
5055   "type_ref": "PA_CL_UCP_0_X"
5056  },
5057  {
5058   "chips": ["gfx10"],
5059   "map": {"at": 165316, "to": "mm"},
5060   "name": "PA_CL_UCP_0_Z",
5061   "type_ref": "PA_CL_UCP_0_X"
5062  },
5063  {
5064   "chips": ["gfx10"],
5065   "map": {"at": 165320, "to": "mm"},
5066   "name": "PA_CL_UCP_0_W",
5067   "type_ref": "PA_CL_UCP_0_X"
5068  },
5069  {
5070   "chips": ["gfx10"],
5071   "map": {"at": 165324, "to": "mm"},
5072   "name": "PA_CL_UCP_1_X",
5073   "type_ref": "PA_CL_UCP_0_X"
5074  },
5075  {
5076   "chips": ["gfx10"],
5077   "map": {"at": 165328, "to": "mm"},
5078   "name": "PA_CL_UCP_1_Y",
5079   "type_ref": "PA_CL_UCP_0_X"
5080  },
5081  {
5082   "chips": ["gfx10"],
5083   "map": {"at": 165332, "to": "mm"},
5084   "name": "PA_CL_UCP_1_Z",
5085   "type_ref": "PA_CL_UCP_0_X"
5086  },
5087  {
5088   "chips": ["gfx10"],
5089   "map": {"at": 165336, "to": "mm"},
5090   "name": "PA_CL_UCP_1_W",
5091   "type_ref": "PA_CL_UCP_0_X"
5092  },
5093  {
5094   "chips": ["gfx10"],
5095   "map": {"at": 165340, "to": "mm"},
5096   "name": "PA_CL_UCP_2_X",
5097   "type_ref": "PA_CL_UCP_0_X"
5098  },
5099  {
5100   "chips": ["gfx10"],
5101   "map": {"at": 165344, "to": "mm"},
5102   "name": "PA_CL_UCP_2_Y",
5103   "type_ref": "PA_CL_UCP_0_X"
5104  },
5105  {
5106   "chips": ["gfx10"],
5107   "map": {"at": 165348, "to": "mm"},
5108   "name": "PA_CL_UCP_2_Z",
5109   "type_ref": "PA_CL_UCP_0_X"
5110  },
5111  {
5112   "chips": ["gfx10"],
5113   "map": {"at": 165352, "to": "mm"},
5114   "name": "PA_CL_UCP_2_W",
5115   "type_ref": "PA_CL_UCP_0_X"
5116  },
5117  {
5118   "chips": ["gfx10"],
5119   "map": {"at": 165356, "to": "mm"},
5120   "name": "PA_CL_UCP_3_X",
5121   "type_ref": "PA_CL_UCP_0_X"
5122  },
5123  {
5124   "chips": ["gfx10"],
5125   "map": {"at": 165360, "to": "mm"},
5126   "name": "PA_CL_UCP_3_Y",
5127   "type_ref": "PA_CL_UCP_0_X"
5128  },
5129  {
5130   "chips": ["gfx10"],
5131   "map": {"at": 165364, "to": "mm"},
5132   "name": "PA_CL_UCP_3_Z",
5133   "type_ref": "PA_CL_UCP_0_X"
5134  },
5135  {
5136   "chips": ["gfx10"],
5137   "map": {"at": 165368, "to": "mm"},
5138   "name": "PA_CL_UCP_3_W",
5139   "type_ref": "PA_CL_UCP_0_X"
5140  },
5141  {
5142   "chips": ["gfx10"],
5143   "map": {"at": 165372, "to": "mm"},
5144   "name": "PA_CL_UCP_4_X",
5145   "type_ref": "PA_CL_UCP_0_X"
5146  },
5147  {
5148   "chips": ["gfx10"],
5149   "map": {"at": 165376, "to": "mm"},
5150   "name": "PA_CL_UCP_4_Y",
5151   "type_ref": "PA_CL_UCP_0_X"
5152  },
5153  {
5154   "chips": ["gfx10"],
5155   "map": {"at": 165380, "to": "mm"},
5156   "name": "PA_CL_UCP_4_Z",
5157   "type_ref": "PA_CL_UCP_0_X"
5158  },
5159  {
5160   "chips": ["gfx10"],
5161   "map": {"at": 165384, "to": "mm"},
5162   "name": "PA_CL_UCP_4_W",
5163   "type_ref": "PA_CL_UCP_0_X"
5164  },
5165  {
5166   "chips": ["gfx10"],
5167   "map": {"at": 165388, "to": "mm"},
5168   "name": "PA_CL_UCP_5_X",
5169   "type_ref": "PA_CL_UCP_0_X"
5170  },
5171  {
5172   "chips": ["gfx10"],
5173   "map": {"at": 165392, "to": "mm"},
5174   "name": "PA_CL_UCP_5_Y",
5175   "type_ref": "PA_CL_UCP_0_X"
5176  },
5177  {
5178   "chips": ["gfx10"],
5179   "map": {"at": 165396, "to": "mm"},
5180   "name": "PA_CL_UCP_5_Z",
5181   "type_ref": "PA_CL_UCP_0_X"
5182  },
5183  {
5184   "chips": ["gfx10"],
5185   "map": {"at": 165400, "to": "mm"},
5186   "name": "PA_CL_UCP_5_W",
5187   "type_ref": "PA_CL_UCP_0_X"
5188  },
5189  {
5190   "chips": ["gfx10"],
5191   "map": {"at": 165404, "to": "mm"},
5192   "name": "PA_CL_PROG_NEAR_CLIP_Z",
5193   "type_ref": "PA_CL_UCP_0_X"
5194  },
5195  {
5196   "chips": ["gfx10"],
5197   "map": {"at": 165444, "to": "mm"},
5198   "name": "SPI_PS_INPUT_CNTL_0",
5199   "type_ref": "SPI_PS_INPUT_CNTL_0"
5200  },
5201  {
5202   "chips": ["gfx10"],
5203   "map": {"at": 165448, "to": "mm"},
5204   "name": "SPI_PS_INPUT_CNTL_1",
5205   "type_ref": "SPI_PS_INPUT_CNTL_0"
5206  },
5207  {
5208   "chips": ["gfx10"],
5209   "map": {"at": 165452, "to": "mm"},
5210   "name": "SPI_PS_INPUT_CNTL_2",
5211   "type_ref": "SPI_PS_INPUT_CNTL_0"
5212  },
5213  {
5214   "chips": ["gfx10"],
5215   "map": {"at": 165456, "to": "mm"},
5216   "name": "SPI_PS_INPUT_CNTL_3",
5217   "type_ref": "SPI_PS_INPUT_CNTL_0"
5218  },
5219  {
5220   "chips": ["gfx10"],
5221   "map": {"at": 165460, "to": "mm"},
5222   "name": "SPI_PS_INPUT_CNTL_4",
5223   "type_ref": "SPI_PS_INPUT_CNTL_0"
5224  },
5225  {
5226   "chips": ["gfx10"],
5227   "map": {"at": 165464, "to": "mm"},
5228   "name": "SPI_PS_INPUT_CNTL_5",
5229   "type_ref": "SPI_PS_INPUT_CNTL_0"
5230  },
5231  {
5232   "chips": ["gfx10"],
5233   "map": {"at": 165468, "to": "mm"},
5234   "name": "SPI_PS_INPUT_CNTL_6",
5235   "type_ref": "SPI_PS_INPUT_CNTL_0"
5236  },
5237  {
5238   "chips": ["gfx10"],
5239   "map": {"at": 165472, "to": "mm"},
5240   "name": "SPI_PS_INPUT_CNTL_7",
5241   "type_ref": "SPI_PS_INPUT_CNTL_0"
5242  },
5243  {
5244   "chips": ["gfx10"],
5245   "map": {"at": 165476, "to": "mm"},
5246   "name": "SPI_PS_INPUT_CNTL_8",
5247   "type_ref": "SPI_PS_INPUT_CNTL_0"
5248  },
5249  {
5250   "chips": ["gfx10"],
5251   "map": {"at": 165480, "to": "mm"},
5252   "name": "SPI_PS_INPUT_CNTL_9",
5253   "type_ref": "SPI_PS_INPUT_CNTL_0"
5254  },
5255  {
5256   "chips": ["gfx10"],
5257   "map": {"at": 165484, "to": "mm"},
5258   "name": "SPI_PS_INPUT_CNTL_10",
5259   "type_ref": "SPI_PS_INPUT_CNTL_0"
5260  },
5261  {
5262   "chips": ["gfx10"],
5263   "map": {"at": 165488, "to": "mm"},
5264   "name": "SPI_PS_INPUT_CNTL_11",
5265   "type_ref": "SPI_PS_INPUT_CNTL_0"
5266  },
5267  {
5268   "chips": ["gfx10"],
5269   "map": {"at": 165492, "to": "mm"},
5270   "name": "SPI_PS_INPUT_CNTL_12",
5271   "type_ref": "SPI_PS_INPUT_CNTL_0"
5272  },
5273  {
5274   "chips": ["gfx10"],
5275   "map": {"at": 165496, "to": "mm"},
5276   "name": "SPI_PS_INPUT_CNTL_13",
5277   "type_ref": "SPI_PS_INPUT_CNTL_0"
5278  },
5279  {
5280   "chips": ["gfx10"],
5281   "map": {"at": 165500, "to": "mm"},
5282   "name": "SPI_PS_INPUT_CNTL_14",
5283   "type_ref": "SPI_PS_INPUT_CNTL_0"
5284  },
5285  {
5286   "chips": ["gfx10"],
5287   "map": {"at": 165504, "to": "mm"},
5288   "name": "SPI_PS_INPUT_CNTL_15",
5289   "type_ref": "SPI_PS_INPUT_CNTL_0"
5290  },
5291  {
5292   "chips": ["gfx10"],
5293   "map": {"at": 165508, "to": "mm"},
5294   "name": "SPI_PS_INPUT_CNTL_16",
5295   "type_ref": "SPI_PS_INPUT_CNTL_0"
5296  },
5297  {
5298   "chips": ["gfx10"],
5299   "map": {"at": 165512, "to": "mm"},
5300   "name": "SPI_PS_INPUT_CNTL_17",
5301   "type_ref": "SPI_PS_INPUT_CNTL_0"
5302  },
5303  {
5304   "chips": ["gfx10"],
5305   "map": {"at": 165516, "to": "mm"},
5306   "name": "SPI_PS_INPUT_CNTL_18",
5307   "type_ref": "SPI_PS_INPUT_CNTL_0"
5308  },
5309  {
5310   "chips": ["gfx10"],
5311   "map": {"at": 165520, "to": "mm"},
5312   "name": "SPI_PS_INPUT_CNTL_19",
5313   "type_ref": "SPI_PS_INPUT_CNTL_0"
5314  },
5315  {
5316   "chips": ["gfx10"],
5317   "map": {"at": 165524, "to": "mm"},
5318   "name": "SPI_PS_INPUT_CNTL_20",
5319   "type_ref": "SPI_PS_INPUT_CNTL_20"
5320  },
5321  {
5322   "chips": ["gfx10"],
5323   "map": {"at": 165528, "to": "mm"},
5324   "name": "SPI_PS_INPUT_CNTL_21",
5325   "type_ref": "SPI_PS_INPUT_CNTL_20"
5326  },
5327  {
5328   "chips": ["gfx10"],
5329   "map": {"at": 165532, "to": "mm"},
5330   "name": "SPI_PS_INPUT_CNTL_22",
5331   "type_ref": "SPI_PS_INPUT_CNTL_20"
5332  },
5333  {
5334   "chips": ["gfx10"],
5335   "map": {"at": 165536, "to": "mm"},
5336   "name": "SPI_PS_INPUT_CNTL_23",
5337   "type_ref": "SPI_PS_INPUT_CNTL_20"
5338  },
5339  {
5340   "chips": ["gfx10"],
5341   "map": {"at": 165540, "to": "mm"},
5342   "name": "SPI_PS_INPUT_CNTL_24",
5343   "type_ref": "SPI_PS_INPUT_CNTL_20"
5344  },
5345  {
5346   "chips": ["gfx10"],
5347   "map": {"at": 165544, "to": "mm"},
5348   "name": "SPI_PS_INPUT_CNTL_25",
5349   "type_ref": "SPI_PS_INPUT_CNTL_20"
5350  },
5351  {
5352   "chips": ["gfx10"],
5353   "map": {"at": 165548, "to": "mm"},
5354   "name": "SPI_PS_INPUT_CNTL_26",
5355   "type_ref": "SPI_PS_INPUT_CNTL_20"
5356  },
5357  {
5358   "chips": ["gfx10"],
5359   "map": {"at": 165552, "to": "mm"},
5360   "name": "SPI_PS_INPUT_CNTL_27",
5361   "type_ref": "SPI_PS_INPUT_CNTL_20"
5362  },
5363  {
5364   "chips": ["gfx10"],
5365   "map": {"at": 165556, "to": "mm"},
5366   "name": "SPI_PS_INPUT_CNTL_28",
5367   "type_ref": "SPI_PS_INPUT_CNTL_20"
5368  },
5369  {
5370   "chips": ["gfx10"],
5371   "map": {"at": 165560, "to": "mm"},
5372   "name": "SPI_PS_INPUT_CNTL_29",
5373   "type_ref": "SPI_PS_INPUT_CNTL_20"
5374  },
5375  {
5376   "chips": ["gfx10"],
5377   "map": {"at": 165564, "to": "mm"},
5378   "name": "SPI_PS_INPUT_CNTL_30",
5379   "type_ref": "SPI_PS_INPUT_CNTL_20"
5380  },
5381  {
5382   "chips": ["gfx10"],
5383   "map": {"at": 165568, "to": "mm"},
5384   "name": "SPI_PS_INPUT_CNTL_31",
5385   "type_ref": "SPI_PS_INPUT_CNTL_20"
5386  },
5387  {
5388   "chips": ["gfx10"],
5389   "map": {"at": 165572, "to": "mm"},
5390   "name": "SPI_VS_OUT_CONFIG",
5391   "type_ref": "SPI_VS_OUT_CONFIG"
5392  },
5393  {
5394   "chips": ["gfx10"],
5395   "map": {"at": 165580, "to": "mm"},
5396   "name": "SPI_PS_INPUT_ENA",
5397   "type_ref": "SPI_PS_INPUT_ENA"
5398  },
5399  {
5400   "chips": ["gfx10"],
5401   "map": {"at": 165584, "to": "mm"},
5402   "name": "SPI_PS_INPUT_ADDR",
5403   "type_ref": "SPI_PS_INPUT_ENA"
5404  },
5405  {
5406   "chips": ["gfx10"],
5407   "map": {"at": 165588, "to": "mm"},
5408   "name": "SPI_INTERP_CONTROL_0",
5409   "type_ref": "SPI_INTERP_CONTROL_0"
5410  },
5411  {
5412   "chips": ["gfx10"],
5413   "map": {"at": 165592, "to": "mm"},
5414   "name": "SPI_PS_IN_CONTROL",
5415   "type_ref": "SPI_PS_IN_CONTROL"
5416  },
5417  {
5418   "chips": ["gfx10"],
5419   "map": {"at": 165600, "to": "mm"},
5420   "name": "SPI_BARYC_CNTL",
5421   "type_ref": "SPI_BARYC_CNTL"
5422  },
5423  {
5424   "chips": ["gfx10"],
5425   "map": {"at": 165608, "to": "mm"},
5426   "name": "SPI_TMPRING_SIZE",
5427   "type_ref": "COMPUTE_TMPRING_SIZE"
5428  },
5429  {
5430   "chips": ["gfx10"],
5431   "map": {"at": 165640, "to": "mm"},
5432   "name": "SPI_SHADER_IDX_FORMAT",
5433   "type_ref": "SPI_SHADER_IDX_FORMAT"
5434  },
5435  {
5436   "chips": ["gfx10"],
5437   "map": {"at": 165644, "to": "mm"},
5438   "name": "SPI_SHADER_POS_FORMAT",
5439   "type_ref": "SPI_SHADER_POS_FORMAT"
5440  },
5441  {
5442   "chips": ["gfx10"],
5443   "map": {"at": 165648, "to": "mm"},
5444   "name": "SPI_SHADER_Z_FORMAT",
5445   "type_ref": "SPI_SHADER_Z_FORMAT"
5446  },
5447  {
5448   "chips": ["gfx10"],
5449   "map": {"at": 165652, "to": "mm"},
5450   "name": "SPI_SHADER_COL_FORMAT",
5451   "type_ref": "SPI_SHADER_COL_FORMAT"
5452  },
5453  {
5454   "chips": ["gfx10"],
5455   "map": {"at": 165716, "to": "mm"},
5456   "name": "SX_PS_DOWNCONVERT",
5457   "type_ref": "SX_PS_DOWNCONVERT"
5458  },
5459  {
5460   "chips": ["gfx10"],
5461   "map": {"at": 165720, "to": "mm"},
5462   "name": "SX_BLEND_OPT_EPSILON",
5463   "type_ref": "SX_BLEND_OPT_EPSILON"
5464  },
5465  {
5466   "chips": ["gfx10"],
5467   "map": {"at": 165724, "to": "mm"},
5468   "name": "SX_BLEND_OPT_CONTROL",
5469   "type_ref": "SX_BLEND_OPT_CONTROL"
5470  },
5471  {
5472   "chips": ["gfx10"],
5473   "map": {"at": 165728, "to": "mm"},
5474   "name": "SX_MRT0_BLEND_OPT",
5475   "type_ref": "SX_MRT0_BLEND_OPT"
5476  },
5477  {
5478   "chips": ["gfx10"],
5479   "map": {"at": 165732, "to": "mm"},
5480   "name": "SX_MRT1_BLEND_OPT",
5481   "type_ref": "SX_MRT0_BLEND_OPT"
5482  },
5483  {
5484   "chips": ["gfx10"],
5485   "map": {"at": 165736, "to": "mm"},
5486   "name": "SX_MRT2_BLEND_OPT",
5487   "type_ref": "SX_MRT0_BLEND_OPT"
5488  },
5489  {
5490   "chips": ["gfx10"],
5491   "map": {"at": 165740, "to": "mm"},
5492   "name": "SX_MRT3_BLEND_OPT",
5493   "type_ref": "SX_MRT0_BLEND_OPT"
5494  },
5495  {
5496   "chips": ["gfx10"],
5497   "map": {"at": 165744, "to": "mm"},
5498   "name": "SX_MRT4_BLEND_OPT",
5499   "type_ref": "SX_MRT0_BLEND_OPT"
5500  },
5501  {
5502   "chips": ["gfx10"],
5503   "map": {"at": 165748, "to": "mm"},
5504   "name": "SX_MRT5_BLEND_OPT",
5505   "type_ref": "SX_MRT0_BLEND_OPT"
5506  },
5507  {
5508   "chips": ["gfx10"],
5509   "map": {"at": 165752, "to": "mm"},
5510   "name": "SX_MRT6_BLEND_OPT",
5511   "type_ref": "SX_MRT0_BLEND_OPT"
5512  },
5513  {
5514   "chips": ["gfx10"],
5515   "map": {"at": 165756, "to": "mm"},
5516   "name": "SX_MRT7_BLEND_OPT",
5517   "type_ref": "SX_MRT0_BLEND_OPT"
5518  },
5519  {
5520   "chips": ["gfx10"],
5521   "map": {"at": 165760, "to": "mm"},
5522   "name": "CB_BLEND0_CONTROL",
5523   "type_ref": "CB_BLEND0_CONTROL"
5524  },
5525  {
5526   "chips": ["gfx10"],
5527   "map": {"at": 165764, "to": "mm"},
5528   "name": "CB_BLEND1_CONTROL",
5529   "type_ref": "CB_BLEND0_CONTROL"
5530  },
5531  {
5532   "chips": ["gfx10"],
5533   "map": {"at": 165768, "to": "mm"},
5534   "name": "CB_BLEND2_CONTROL",
5535   "type_ref": "CB_BLEND0_CONTROL"
5536  },
5537  {
5538   "chips": ["gfx10"],
5539   "map": {"at": 165772, "to": "mm"},
5540   "name": "CB_BLEND3_CONTROL",
5541   "type_ref": "CB_BLEND0_CONTROL"
5542  },
5543  {
5544   "chips": ["gfx10"],
5545   "map": {"at": 165776, "to": "mm"},
5546   "name": "CB_BLEND4_CONTROL",
5547   "type_ref": "CB_BLEND0_CONTROL"
5548  },
5549  {
5550   "chips": ["gfx10"],
5551   "map": {"at": 165780, "to": "mm"},
5552   "name": "CB_BLEND5_CONTROL",
5553   "type_ref": "CB_BLEND0_CONTROL"
5554  },
5555  {
5556   "chips": ["gfx10"],
5557   "map": {"at": 165784, "to": "mm"},
5558   "name": "CB_BLEND6_CONTROL",
5559   "type_ref": "CB_BLEND0_CONTROL"
5560  },
5561  {
5562   "chips": ["gfx10"],
5563   "map": {"at": 165788, "to": "mm"},
5564   "name": "CB_BLEND7_CONTROL",
5565   "type_ref": "CB_BLEND0_CONTROL"
5566  },
5567  {
5568   "chips": ["gfx10"],
5569   "map": {"at": 165836, "to": "mm"},
5570   "name": "CS_COPY_STATE",
5571   "type_ref": "CS_COPY_STATE"
5572  },
5573  {
5574   "chips": ["gfx10"],
5575   "map": {"at": 165840, "to": "mm"},
5576   "name": "GFX_COPY_STATE",
5577   "type_ref": "CS_COPY_STATE"
5578  },
5579  {
5580   "chips": ["gfx10"],
5581   "map": {"at": 165844, "to": "mm"},
5582   "name": "PA_CL_POINT_X_RAD",
5583   "type_ref": "PA_CL_UCP_0_X"
5584  },
5585  {
5586   "chips": ["gfx10"],
5587   "map": {"at": 165848, "to": "mm"},
5588   "name": "PA_CL_POINT_Y_RAD",
5589   "type_ref": "PA_CL_UCP_0_X"
5590  },
5591  {
5592   "chips": ["gfx10"],
5593   "map": {"at": 165852, "to": "mm"},
5594   "name": "PA_CL_POINT_SIZE",
5595   "type_ref": "PA_CL_UCP_0_X"
5596  },
5597  {
5598   "chips": ["gfx10"],
5599   "map": {"at": 165856, "to": "mm"},
5600   "name": "PA_CL_POINT_CULL_RAD",
5601   "type_ref": "PA_CL_UCP_0_X"
5602  },
5603  {
5604   "chips": ["gfx10"],
5605   "map": {"at": 165860, "to": "mm"},
5606   "name": "VGT_DMA_BASE_HI",
5607   "type_ref": "VGT_DMA_BASE_HI"
5608  },
5609  {
5610   "chips": ["gfx10"],
5611   "map": {"at": 165864, "to": "mm"},
5612   "name": "VGT_DMA_BASE",
5613   "type_ref": "VGT_DMA_BASE"
5614  },
5615  {
5616   "chips": ["gfx10"],
5617   "map": {"at": 165872, "to": "mm"},
5618   "name": "VGT_DRAW_INITIATOR",
5619   "type_ref": "VGT_DRAW_INITIATOR"
5620  },
5621  {
5622   "chips": ["gfx10"],
5623   "map": {"at": 165876, "to": "mm"},
5624   "name": "VGT_IMMED_DATA",
5625   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
5626  },
5627  {
5628   "chips": ["gfx10"],
5629   "map": {"at": 165880, "to": "mm"},
5630   "name": "VGT_EVENT_ADDRESS_REG",
5631   "type_ref": "VGT_EVENT_ADDRESS_REG"
5632  },
5633  {
5634   "chips": ["gfx10"],
5635   "map": {"at": 165884, "to": "mm"},
5636   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
5637   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
5638  },
5639  {
5640   "chips": ["gfx10"],
5641   "map": {"at": 165888, "to": "mm"},
5642   "name": "DB_DEPTH_CONTROL",
5643   "type_ref": "DB_DEPTH_CONTROL"
5644  },
5645  {
5646   "chips": ["gfx10"],
5647   "map": {"at": 165892, "to": "mm"},
5648   "name": "DB_EQAA",
5649   "type_ref": "DB_EQAA"
5650  },
5651  {
5652   "chips": ["gfx10"],
5653   "map": {"at": 165896, "to": "mm"},
5654   "name": "CB_COLOR_CONTROL",
5655   "type_ref": "CB_COLOR_CONTROL"
5656  },
5657  {
5658   "chips": ["gfx10"],
5659   "map": {"at": 165900, "to": "mm"},
5660   "name": "DB_SHADER_CONTROL",
5661   "type_ref": "DB_SHADER_CONTROL"
5662  },
5663  {
5664   "chips": ["gfx10"],
5665   "map": {"at": 165904, "to": "mm"},
5666   "name": "PA_CL_CLIP_CNTL",
5667   "type_ref": "PA_CL_CLIP_CNTL"
5668  },
5669  {
5670   "chips": ["gfx10"],
5671   "map": {"at": 165908, "to": "mm"},
5672   "name": "PA_SU_SC_MODE_CNTL",
5673   "type_ref": "PA_SU_SC_MODE_CNTL"
5674  },
5675  {
5676   "chips": ["gfx10"],
5677   "map": {"at": 165912, "to": "mm"},
5678   "name": "PA_CL_VTE_CNTL",
5679   "type_ref": "PA_CL_VTE_CNTL"
5680  },
5681  {
5682   "chips": ["gfx10"],
5683   "map": {"at": 165916, "to": "mm"},
5684   "name": "PA_CL_VS_OUT_CNTL",
5685   "type_ref": "PA_CL_VS_OUT_CNTL"
5686  },
5687  {
5688   "chips": ["gfx10"],
5689   "map": {"at": 165920, "to": "mm"},
5690   "name": "PA_CL_NANINF_CNTL",
5691   "type_ref": "PA_CL_NANINF_CNTL"
5692  },
5693  {
5694   "chips": ["gfx10"],
5695   "map": {"at": 165924, "to": "mm"},
5696   "name": "PA_SU_LINE_STIPPLE_CNTL",
5697   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5698  },
5699  {
5700   "chips": ["gfx10"],
5701   "map": {"at": 165928, "to": "mm"},
5702   "name": "PA_SU_LINE_STIPPLE_SCALE",
5703   "type_ref": "PA_SU_LINE_STIPPLE_SCALE"
5704  },
5705  {
5706   "chips": ["gfx10"],
5707   "map": {"at": 165932, "to": "mm"},
5708   "name": "PA_SU_PRIM_FILTER_CNTL",
5709   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5710  },
5711  {
5712   "chips": ["gfx10"],
5713   "map": {"at": 165936, "to": "mm"},
5714   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5715   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
5716  },
5717  {
5718   "chips": ["gfx10"],
5719   "map": {"at": 165940, "to": "mm"},
5720   "name": "PA_CL_OBJPRIM_ID_CNTL",
5721   "type_ref": "PA_CL_OBJPRIM_ID_CNTL"
5722  },
5723  {
5724   "chips": ["gfx10"],
5725   "map": {"at": 165944, "to": "mm"},
5726   "name": "PA_CL_NGG_CNTL",
5727   "type_ref": "PA_CL_NGG_CNTL"
5728  },
5729  {
5730   "chips": ["gfx10"],
5731   "map": {"at": 165948, "to": "mm"},
5732   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5733   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
5734  },
5735  {
5736   "chips": ["gfx10"],
5737   "map": {"at": 165952, "to": "mm"},
5738   "name": "PA_STEREO_CNTL",
5739   "type_ref": "PA_STEREO_CNTL"
5740  },
5741  {
5742   "chips": ["gfx10"],
5743   "map": {"at": 165956, "to": "mm"},
5744   "name": "PA_STATE_STEREO_X",
5745   "type_ref": "PA_STATE_STEREO_X"
5746  },
5747  {
5748   "chips": ["gfx10"],
5749   "map": {"at": 166400, "to": "mm"},
5750   "name": "PA_SU_POINT_SIZE",
5751   "type_ref": "PA_SU_POINT_SIZE"
5752  },
5753  {
5754   "chips": ["gfx10"],
5755   "map": {"at": 166404, "to": "mm"},
5756   "name": "PA_SU_POINT_MINMAX",
5757   "type_ref": "PA_SU_POINT_MINMAX"
5758  },
5759  {
5760   "chips": ["gfx10"],
5761   "map": {"at": 166408, "to": "mm"},
5762   "name": "PA_SU_LINE_CNTL",
5763   "type_ref": "PA_SU_LINE_CNTL"
5764  },
5765  {
5766   "chips": ["gfx10"],
5767   "map": {"at": 166412, "to": "mm"},
5768   "name": "PA_SC_LINE_STIPPLE",
5769   "type_ref": "PA_SC_LINE_STIPPLE"
5770  },
5771  {
5772   "chips": ["gfx10"],
5773   "map": {"at": 166416, "to": "mm"},
5774   "name": "VGT_OUTPUT_PATH_CNTL",
5775   "type_ref": "VGT_OUTPUT_PATH_CNTL"
5776  },
5777  {
5778   "chips": ["gfx10"],
5779   "map": {"at": 166420, "to": "mm"},
5780   "name": "VGT_HOS_CNTL",
5781   "type_ref": "VGT_HOS_CNTL"
5782  },
5783  {
5784   "chips": ["gfx10"],
5785   "map": {"at": 166424, "to": "mm"},
5786   "name": "VGT_HOS_MAX_TESS_LEVEL",
5787   "type_ref": "VGT_HOS_MAX_TESS_LEVEL"
5788  },
5789  {
5790   "chips": ["gfx10"],
5791   "map": {"at": 166428, "to": "mm"},
5792   "name": "VGT_HOS_MIN_TESS_LEVEL",
5793   "type_ref": "VGT_HOS_MIN_TESS_LEVEL"
5794  },
5795  {
5796   "chips": ["gfx10"],
5797   "map": {"at": 166432, "to": "mm"},
5798   "name": "VGT_HOS_REUSE_DEPTH",
5799   "type_ref": "VGT_HOS_REUSE_DEPTH"
5800  },
5801  {
5802   "chips": ["gfx10"],
5803   "map": {"at": 166436, "to": "mm"},
5804   "name": "VGT_GROUP_PRIM_TYPE",
5805   "type_ref": "VGT_GROUP_PRIM_TYPE"
5806  },
5807  {
5808   "chips": ["gfx10"],
5809   "map": {"at": 166440, "to": "mm"},
5810   "name": "VGT_GROUP_FIRST_DECR",
5811   "type_ref": "VGT_GROUP_FIRST_DECR"
5812  },
5813  {
5814   "chips": ["gfx10"],
5815   "map": {"at": 166444, "to": "mm"},
5816   "name": "VGT_GROUP_DECR",
5817   "type_ref": "VGT_GROUP_DECR"
5818  },
5819  {
5820   "chips": ["gfx10"],
5821   "map": {"at": 166448, "to": "mm"},
5822   "name": "VGT_GROUP_VECT_0_CNTL",
5823   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5824  },
5825  {
5826   "chips": ["gfx10"],
5827   "map": {"at": 166452, "to": "mm"},
5828   "name": "VGT_GROUP_VECT_1_CNTL",
5829   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5830  },
5831  {
5832   "chips": ["gfx10"],
5833   "map": {"at": 166456, "to": "mm"},
5834   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5835   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5836  },
5837  {
5838   "chips": ["gfx10"],
5839   "map": {"at": 166460, "to": "mm"},
5840   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5841   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5842  },
5843  {
5844   "chips": ["gfx10"],
5845   "map": {"at": 166464, "to": "mm"},
5846   "name": "VGT_GS_MODE",
5847   "type_ref": "VGT_GS_MODE"
5848  },
5849  {
5850   "chips": ["gfx10"],
5851   "map": {"at": 166468, "to": "mm"},
5852   "name": "VGT_GS_ONCHIP_CNTL",
5853   "type_ref": "VGT_GS_ONCHIP_CNTL"
5854  },
5855  {
5856   "chips": ["gfx10"],
5857   "map": {"at": 166472, "to": "mm"},
5858   "name": "PA_SC_MODE_CNTL_0",
5859   "type_ref": "PA_SC_MODE_CNTL_0"
5860  },
5861  {
5862   "chips": ["gfx10"],
5863   "map": {"at": 166476, "to": "mm"},
5864   "name": "PA_SC_MODE_CNTL_1",
5865   "type_ref": "PA_SC_MODE_CNTL_1"
5866  },
5867  {
5868   "chips": ["gfx10"],
5869   "map": {"at": 166480, "to": "mm"},
5870   "name": "VGT_ENHANCE",
5871   "type_ref": "VGT_ENHANCE"
5872  },
5873  {
5874   "chips": ["gfx10"],
5875   "map": {"at": 166484, "to": "mm"},
5876   "name": "VGT_GS_PER_ES",
5877   "type_ref": "VGT_GS_PER_ES"
5878  },
5879  {
5880   "chips": ["gfx10"],
5881   "map": {"at": 166488, "to": "mm"},
5882   "name": "VGT_ES_PER_GS",
5883   "type_ref": "VGT_ES_PER_GS"
5884  },
5885  {
5886   "chips": ["gfx10"],
5887   "map": {"at": 166492, "to": "mm"},
5888   "name": "VGT_GS_PER_VS",
5889   "type_ref": "VGT_GS_PER_VS"
5890  },
5891  {
5892   "chips": ["gfx10"],
5893   "map": {"at": 166496, "to": "mm"},
5894   "name": "VGT_GSVS_RING_OFFSET_1",
5895   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5896  },
5897  {
5898   "chips": ["gfx10"],
5899   "map": {"at": 166500, "to": "mm"},
5900   "name": "VGT_GSVS_RING_OFFSET_2",
5901   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5902  },
5903  {
5904   "chips": ["gfx10"],
5905   "map": {"at": 166504, "to": "mm"},
5906   "name": "VGT_GSVS_RING_OFFSET_3",
5907   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5908  },
5909  {
5910   "chips": ["gfx10"],
5911   "map": {"at": 166508, "to": "mm"},
5912   "name": "VGT_GS_OUT_PRIM_TYPE",
5913   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5914  },
5915  {
5916   "chips": ["gfx10"],
5917   "map": {"at": 166512, "to": "mm"},
5918   "name": "IA_ENHANCE",
5919   "type_ref": "VGT_ENHANCE"
5920  },
5921  {
5922   "chips": ["gfx10"],
5923   "map": {"at": 166516, "to": "mm"},
5924   "name": "VGT_DMA_SIZE",
5925   "type_ref": "VGT_DMA_SIZE"
5926  },
5927  {
5928   "chips": ["gfx10"],
5929   "map": {"at": 166520, "to": "mm"},
5930   "name": "VGT_DMA_MAX_SIZE",
5931   "type_ref": "VGT_DMA_MAX_SIZE"
5932  },
5933  {
5934   "chips": ["gfx10"],
5935   "map": {"at": 166524, "to": "mm"},
5936   "name": "VGT_DMA_INDEX_TYPE",
5937   "type_ref": "VGT_DMA_INDEX_TYPE"
5938  },
5939  {
5940   "chips": ["gfx10"],
5941   "map": {"at": 166528, "to": "mm"},
5942   "name": "WD_ENHANCE",
5943   "type_ref": "VGT_ENHANCE"
5944  },
5945  {
5946   "chips": ["gfx10"],
5947   "map": {"at": 166532, "to": "mm"},
5948   "name": "VGT_PRIMITIVEID_EN",
5949   "type_ref": "VGT_PRIMITIVEID_EN"
5950  },
5951  {
5952   "chips": ["gfx10"],
5953   "map": {"at": 166536, "to": "mm"},
5954   "name": "VGT_DMA_NUM_INSTANCES",
5955   "type_ref": "VGT_DMA_NUM_INSTANCES"
5956  },
5957  {
5958   "chips": ["gfx10"],
5959   "map": {"at": 166540, "to": "mm"},
5960   "name": "VGT_PRIMITIVEID_RESET",
5961   "type_ref": "VGT_PRIMITIVEID_RESET"
5962  },
5963  {
5964   "chips": ["gfx10"],
5965   "map": {"at": 166544, "to": "mm"},
5966   "name": "VGT_EVENT_INITIATOR",
5967   "type_ref": "VGT_EVENT_INITIATOR"
5968  },
5969  {
5970   "chips": ["gfx10"],
5971   "map": {"at": 166548, "to": "mm"},
5972   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5973   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
5974  },
5975  {
5976   "chips": ["gfx10"],
5977   "map": {"at": 166552, "to": "mm"},
5978   "name": "VGT_DRAW_PAYLOAD_CNTL",
5979   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
5980  },
5981  {
5982   "chips": ["gfx10"],
5983   "map": {"at": 166560, "to": "mm"},
5984   "name": "VGT_INSTANCE_STEP_RATE_0",
5985   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5986  },
5987  {
5988   "chips": ["gfx10"],
5989   "map": {"at": 166564, "to": "mm"},
5990   "name": "VGT_INSTANCE_STEP_RATE_1",
5991   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5992  },
5993  {
5994   "chips": ["gfx10"],
5995   "map": {"at": 166568, "to": "mm"},
5996   "name": "IA_MULTI_VGT_PARAM",
5997   "type_ref": "IA_MULTI_VGT_PARAM"
5998  },
5999  {
6000   "chips": ["gfx10"],
6001   "map": {"at": 166572, "to": "mm"},
6002   "name": "VGT_ESGS_RING_ITEMSIZE",
6003   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6004  },
6005  {
6006   "chips": ["gfx10"],
6007   "map": {"at": 166576, "to": "mm"},
6008   "name": "VGT_GSVS_RING_ITEMSIZE",
6009   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6010  },
6011  {
6012   "chips": ["gfx10"],
6013   "map": {"at": 166580, "to": "mm"},
6014   "name": "VGT_REUSE_OFF",
6015   "type_ref": "VGT_REUSE_OFF"
6016  },
6017  {
6018   "chips": ["gfx10"],
6019   "map": {"at": 166584, "to": "mm"},
6020   "name": "VGT_VTX_CNT_EN",
6021   "type_ref": "VGT_VTX_CNT_EN"
6022  },
6023  {
6024   "chips": ["gfx10"],
6025   "map": {"at": 166588, "to": "mm"},
6026   "name": "DB_HTILE_SURFACE",
6027   "type_ref": "DB_HTILE_SURFACE"
6028  },
6029  {
6030   "chips": ["gfx10"],
6031   "map": {"at": 166592, "to": "mm"},
6032   "name": "DB_SRESULTS_COMPARE_STATE0",
6033   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
6034  },
6035  {
6036   "chips": ["gfx10"],
6037   "map": {"at": 166596, "to": "mm"},
6038   "name": "DB_SRESULTS_COMPARE_STATE1",
6039   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
6040  },
6041  {
6042   "chips": ["gfx10"],
6043   "map": {"at": 166600, "to": "mm"},
6044   "name": "DB_PRELOAD_CONTROL",
6045   "type_ref": "DB_PRELOAD_CONTROL"
6046  },
6047  {
6048   "chips": ["gfx10"],
6049   "map": {"at": 166608, "to": "mm"},
6050   "name": "VGT_STRMOUT_BUFFER_SIZE_0",
6051   "type_ref": "COMPUTE_DIM_X"
6052  },
6053  {
6054   "chips": ["gfx10"],
6055   "map": {"at": 166612, "to": "mm"},
6056   "name": "VGT_STRMOUT_VTX_STRIDE_0",
6057   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6058  },
6059  {
6060   "chips": ["gfx10"],
6061   "map": {"at": 166620, "to": "mm"},
6062   "name": "VGT_STRMOUT_BUFFER_OFFSET_0",
6063   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6064  },
6065  {
6066   "chips": ["gfx10"],
6067   "map": {"at": 166624, "to": "mm"},
6068   "name": "VGT_STRMOUT_BUFFER_SIZE_1",
6069   "type_ref": "COMPUTE_DIM_X"
6070  },
6071  {
6072   "chips": ["gfx10"],
6073   "map": {"at": 166628, "to": "mm"},
6074   "name": "VGT_STRMOUT_VTX_STRIDE_1",
6075   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6076  },
6077  {
6078   "chips": ["gfx10"],
6079   "map": {"at": 166636, "to": "mm"},
6080   "name": "VGT_STRMOUT_BUFFER_OFFSET_1",
6081   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6082  },
6083  {
6084   "chips": ["gfx10"],
6085   "map": {"at": 166640, "to": "mm"},
6086   "name": "VGT_STRMOUT_BUFFER_SIZE_2",
6087   "type_ref": "COMPUTE_DIM_X"
6088  },
6089  {
6090   "chips": ["gfx10"],
6091   "map": {"at": 166644, "to": "mm"},
6092   "name": "VGT_STRMOUT_VTX_STRIDE_2",
6093   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6094  },
6095  {
6096   "chips": ["gfx10"],
6097   "map": {"at": 166652, "to": "mm"},
6098   "name": "VGT_STRMOUT_BUFFER_OFFSET_2",
6099   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6100  },
6101  {
6102   "chips": ["gfx10"],
6103   "map": {"at": 166656, "to": "mm"},
6104   "name": "VGT_STRMOUT_BUFFER_SIZE_3",
6105   "type_ref": "COMPUTE_DIM_X"
6106  },
6107  {
6108   "chips": ["gfx10"],
6109   "map": {"at": 166660, "to": "mm"},
6110   "name": "VGT_STRMOUT_VTX_STRIDE_3",
6111   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
6112  },
6113  {
6114   "chips": ["gfx10"],
6115   "map": {"at": 166668, "to": "mm"},
6116   "name": "VGT_STRMOUT_BUFFER_OFFSET_3",
6117   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6118  },
6119  {
6120   "chips": ["gfx10"],
6121   "map": {"at": 166696, "to": "mm"},
6122   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET",
6123   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6124  },
6125  {
6126   "chips": ["gfx10"],
6127   "map": {"at": 166700, "to": "mm"},
6128   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE",
6129   "type_ref": "COMPUTE_DIM_X"
6130  },
6131  {
6132   "chips": ["gfx10"],
6133   "map": {"at": 166704, "to": "mm"},
6134   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
6135   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
6136  },
6137  {
6138   "chips": ["gfx10"],
6139   "map": {"at": 166712, "to": "mm"},
6140   "name": "VGT_GS_MAX_VERT_OUT",
6141   "type_ref": "VGT_GS_MAX_VERT_OUT"
6142  },
6143  {
6144   "chips": ["gfx10"],
6145   "map": {"at": 166732, "to": "mm"},
6146   "name": "GE_NGG_SUBGRP_CNTL",
6147   "type_ref": "GE_NGG_SUBGRP_CNTL"
6148  },
6149  {
6150   "chips": ["gfx10"],
6151   "map": {"at": 166736, "to": "mm"},
6152   "name": "VGT_TESS_DISTRIBUTION",
6153   "type_ref": "VGT_TESS_DISTRIBUTION"
6154  },
6155  {
6156   "chips": ["gfx10"],
6157   "map": {"at": 166740, "to": "mm"},
6158   "name": "VGT_SHADER_STAGES_EN",
6159   "type_ref": "VGT_SHADER_STAGES_EN"
6160  },
6161  {
6162   "chips": ["gfx10"],
6163   "map": {"at": 166744, "to": "mm"},
6164   "name": "VGT_LS_HS_CONFIG",
6165   "type_ref": "VGT_LS_HS_CONFIG"
6166  },
6167  {
6168   "chips": ["gfx10"],
6169   "map": {"at": 166748, "to": "mm"},
6170   "name": "VGT_GS_VERT_ITEMSIZE",
6171   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6172  },
6173  {
6174   "chips": ["gfx10"],
6175   "map": {"at": 166752, "to": "mm"},
6176   "name": "VGT_GS_VERT_ITEMSIZE_1",
6177   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6178  },
6179  {
6180   "chips": ["gfx10"],
6181   "map": {"at": 166756, "to": "mm"},
6182   "name": "VGT_GS_VERT_ITEMSIZE_2",
6183   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6184  },
6185  {
6186   "chips": ["gfx10"],
6187   "map": {"at": 166760, "to": "mm"},
6188   "name": "VGT_GS_VERT_ITEMSIZE_3",
6189   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
6190  },
6191  {
6192   "chips": ["gfx10"],
6193   "map": {"at": 166764, "to": "mm"},
6194   "name": "VGT_TF_PARAM",
6195   "type_ref": "VGT_TF_PARAM"
6196  },
6197  {
6198   "chips": ["gfx10"],
6199   "map": {"at": 166768, "to": "mm"},
6200   "name": "DB_ALPHA_TO_MASK",
6201   "type_ref": "DB_ALPHA_TO_MASK"
6202  },
6203  {
6204   "chips": ["gfx10"],
6205   "map": {"at": 166772, "to": "mm"},
6206   "name": "VGT_DISPATCH_DRAW_INDEX",
6207   "type_ref": "VGT_DISPATCH_DRAW_INDEX"
6208  },
6209  {
6210   "chips": ["gfx10"],
6211   "map": {"at": 166776, "to": "mm"},
6212   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
6213   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
6214  },
6215  {
6216   "chips": ["gfx10"],
6217   "map": {"at": 166780, "to": "mm"},
6218   "name": "PA_SU_POLY_OFFSET_CLAMP",
6219   "type_ref": "PA_SU_POLY_OFFSET_CLAMP"
6220  },
6221  {
6222   "chips": ["gfx10"],
6223   "map": {"at": 166784, "to": "mm"},
6224   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE",
6225   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
6226  },
6227  {
6228   "chips": ["gfx10"],
6229   "map": {"at": 166788, "to": "mm"},
6230   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET",
6231   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6232  },
6233  {
6234   "chips": ["gfx10"],
6235   "map": {"at": 166792, "to": "mm"},
6236   "name": "PA_SU_POLY_OFFSET_BACK_SCALE",
6237   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
6238  },
6239  {
6240   "chips": ["gfx10"],
6241   "map": {"at": 166796, "to": "mm"},
6242   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET",
6243   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
6244  },
6245  {
6246   "chips": ["gfx10"],
6247   "map": {"at": 166800, "to": "mm"},
6248   "name": "VGT_GS_INSTANCE_CNT",
6249   "type_ref": "VGT_GS_INSTANCE_CNT"
6250  },
6251  {
6252   "chips": ["gfx10"],
6253   "map": {"at": 166804, "to": "mm"},
6254   "name": "VGT_STRMOUT_CONFIG",
6255   "type_ref": "VGT_STRMOUT_CONFIG"
6256  },
6257  {
6258   "chips": ["gfx10"],
6259   "map": {"at": 166808, "to": "mm"},
6260   "name": "VGT_STRMOUT_BUFFER_CONFIG",
6261   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
6262  },
6263  {
6264   "chips": ["gfx10"],
6265   "map": {"at": 166812, "to": "mm"},
6266   "name": "VGT_DMA_EVENT_INITIATOR",
6267   "type_ref": "VGT_EVENT_INITIATOR"
6268  },
6269  {
6270   "chips": ["gfx10"],
6271   "map": {"at": 166868, "to": "mm"},
6272   "name": "PA_SC_CENTROID_PRIORITY_0",
6273   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
6274  },
6275  {
6276   "chips": ["gfx10"],
6277   "map": {"at": 166872, "to": "mm"},
6278   "name": "PA_SC_CENTROID_PRIORITY_1",
6279   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
6280  },
6281  {
6282   "chips": ["gfx10"],
6283   "map": {"at": 166876, "to": "mm"},
6284   "name": "PA_SC_LINE_CNTL",
6285   "type_ref": "PA_SC_LINE_CNTL"
6286  },
6287  {
6288   "chips": ["gfx10"],
6289   "map": {"at": 166880, "to": "mm"},
6290   "name": "PA_SC_AA_CONFIG",
6291   "type_ref": "PA_SC_AA_CONFIG"
6292  },
6293  {
6294   "chips": ["gfx10"],
6295   "map": {"at": 166884, "to": "mm"},
6296   "name": "PA_SU_VTX_CNTL",
6297   "type_ref": "PA_SU_VTX_CNTL"
6298  },
6299  {
6300   "chips": ["gfx10"],
6301   "map": {"at": 166888, "to": "mm"},
6302   "name": "PA_CL_GB_VERT_CLIP_ADJ",
6303   "type_ref": "PA_CL_UCP_0_X"
6304  },
6305  {
6306   "chips": ["gfx10"],
6307   "map": {"at": 166892, "to": "mm"},
6308   "name": "PA_CL_GB_VERT_DISC_ADJ",
6309   "type_ref": "PA_CL_UCP_0_X"
6310  },
6311  {
6312   "chips": ["gfx10"],
6313   "map": {"at": 166896, "to": "mm"},
6314   "name": "PA_CL_GB_HORZ_CLIP_ADJ",
6315   "type_ref": "PA_CL_UCP_0_X"
6316  },
6317  {
6318   "chips": ["gfx10"],
6319   "map": {"at": 166900, "to": "mm"},
6320   "name": "PA_CL_GB_HORZ_DISC_ADJ",
6321   "type_ref": "PA_CL_UCP_0_X"
6322  },
6323  {
6324   "chips": ["gfx10"],
6325   "map": {"at": 166904, "to": "mm"},
6326   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
6327   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6328  },
6329  {
6330   "chips": ["gfx10"],
6331   "map": {"at": 166908, "to": "mm"},
6332   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
6333   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6334  },
6335  {
6336   "chips": ["gfx10"],
6337   "map": {"at": 166912, "to": "mm"},
6338   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
6339   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6340  },
6341  {
6342   "chips": ["gfx10"],
6343   "map": {"at": 166916, "to": "mm"},
6344   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
6345   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6346  },
6347  {
6348   "chips": ["gfx10"],
6349   "map": {"at": 166920, "to": "mm"},
6350   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
6351   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6352  },
6353  {
6354   "chips": ["gfx10"],
6355   "map": {"at": 166924, "to": "mm"},
6356   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
6357   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6358  },
6359  {
6360   "chips": ["gfx10"],
6361   "map": {"at": 166928, "to": "mm"},
6362   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
6363   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6364  },
6365  {
6366   "chips": ["gfx10"],
6367   "map": {"at": 166932, "to": "mm"},
6368   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
6369   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6370  },
6371  {
6372   "chips": ["gfx10"],
6373   "map": {"at": 166936, "to": "mm"},
6374   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
6375   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6376  },
6377  {
6378   "chips": ["gfx10"],
6379   "map": {"at": 166940, "to": "mm"},
6380   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
6381   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6382  },
6383  {
6384   "chips": ["gfx10"],
6385   "map": {"at": 166944, "to": "mm"},
6386   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
6387   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6388  },
6389  {
6390   "chips": ["gfx10"],
6391   "map": {"at": 166948, "to": "mm"},
6392   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
6393   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6394  },
6395  {
6396   "chips": ["gfx10"],
6397   "map": {"at": 166952, "to": "mm"},
6398   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
6399   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
6400  },
6401  {
6402   "chips": ["gfx10"],
6403   "map": {"at": 166956, "to": "mm"},
6404   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
6405   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
6406  },
6407  {
6408   "chips": ["gfx10"],
6409   "map": {"at": 166960, "to": "mm"},
6410   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
6411   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
6412  },
6413  {
6414   "chips": ["gfx10"],
6415   "map": {"at": 166964, "to": "mm"},
6416   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
6417   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
6418  },
6419  {
6420   "chips": ["gfx10"],
6421   "map": {"at": 166968, "to": "mm"},
6422   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
6423   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
6424  },
6425  {
6426   "chips": ["gfx10"],
6427   "map": {"at": 166972, "to": "mm"},
6428   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
6429   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
6430  },
6431  {
6432   "chips": ["gfx10"],
6433   "map": {"at": 166976, "to": "mm"},
6434   "name": "PA_SC_SHADER_CONTROL",
6435   "type_ref": "PA_SC_SHADER_CONTROL"
6436  },
6437  {
6438   "chips": ["gfx10"],
6439   "map": {"at": 166980, "to": "mm"},
6440   "name": "PA_SC_BINNER_CNTL_0",
6441   "type_ref": "PA_SC_BINNER_CNTL_0"
6442  },
6443  {
6444   "chips": ["gfx10"],
6445   "map": {"at": 166984, "to": "mm"},
6446   "name": "PA_SC_BINNER_CNTL_1",
6447   "type_ref": "PA_SC_BINNER_CNTL_1"
6448  },
6449  {
6450   "chips": ["gfx10"],
6451   "map": {"at": 166988, "to": "mm"},
6452   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
6453   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
6454  },
6455  {
6456   "chips": ["gfx10"],
6457   "map": {"at": 166992, "to": "mm"},
6458   "name": "PA_SC_NGG_MODE_CNTL",
6459   "type_ref": "PA_SC_NGG_MODE_CNTL"
6460  },
6461  {
6462   "chips": ["gfx10"],
6463   "map": {"at": 167000, "to": "mm"},
6464   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
6465   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
6466  },
6467  {
6468   "chips": ["gfx10"],
6469   "map": {"at": 167004, "to": "mm"},
6470   "name": "VGT_OUT_DEALLOC_CNTL",
6471   "type_ref": "VGT_OUT_DEALLOC_CNTL"
6472  },
6473  {
6474   "chips": ["gfx10"],
6475   "map": {"at": 167008, "to": "mm"},
6476   "name": "CB_COLOR0_BASE",
6477   "type_ref": "DB_HTILE_DATA_BASE"
6478  },
6479  {
6480   "chips": ["gfx10"],
6481   "map": {"at": 167012, "to": "mm"},
6482   "name": "CB_COLOR0_PITCH",
6483   "type_ref": "CB_COLOR0_PITCH"
6484  },
6485  {
6486   "chips": ["gfx10"],
6487   "map": {"at": 167016, "to": "mm"},
6488   "name": "CB_COLOR0_SLICE",
6489   "type_ref": "CB_COLOR0_SLICE"
6490  },
6491  {
6492   "chips": ["gfx10"],
6493   "map": {"at": 167020, "to": "mm"},
6494   "name": "CB_COLOR0_VIEW",
6495   "type_ref": "CB_COLOR0_VIEW"
6496  },
6497  {
6498   "chips": ["gfx10"],
6499   "map": {"at": 167024, "to": "mm"},
6500   "name": "CB_COLOR0_INFO",
6501   "type_ref": "CB_COLOR0_INFO"
6502  },
6503  {
6504   "chips": ["gfx10"],
6505   "map": {"at": 167028, "to": "mm"},
6506   "name": "CB_COLOR0_ATTRIB",
6507   "type_ref": "CB_COLOR0_ATTRIB"
6508  },
6509  {
6510   "chips": ["gfx10"],
6511   "map": {"at": 167032, "to": "mm"},
6512   "name": "CB_COLOR0_DCC_CONTROL",
6513   "type_ref": "CB_COLOR0_DCC_CONTROL"
6514  },
6515  {
6516   "chips": ["gfx10"],
6517   "map": {"at": 167036, "to": "mm"},
6518   "name": "CB_COLOR0_CMASK",
6519   "type_ref": "DB_HTILE_DATA_BASE"
6520  },
6521  {
6522   "chips": ["gfx10"],
6523   "map": {"at": 167040, "to": "mm"},
6524   "name": "CB_COLOR0_CMASK_SLICE",
6525   "type_ref": "CB_COLOR0_CMASK_SLICE"
6526  },
6527  {
6528   "chips": ["gfx10"],
6529   "map": {"at": 167044, "to": "mm"},
6530   "name": "CB_COLOR0_FMASK",
6531   "type_ref": "DB_HTILE_DATA_BASE"
6532  },
6533  {
6534   "chips": ["gfx10"],
6535   "map": {"at": 167048, "to": "mm"},
6536   "name": "CB_COLOR0_FMASK_SLICE",
6537   "type_ref": "CB_COLOR0_SLICE"
6538  },
6539  {
6540   "chips": ["gfx10"],
6541   "map": {"at": 167052, "to": "mm"},
6542   "name": "CB_COLOR0_CLEAR_WORD0",
6543   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6544  },
6545  {
6546   "chips": ["gfx10"],
6547   "map": {"at": 167056, "to": "mm"},
6548   "name": "CB_COLOR0_CLEAR_WORD1",
6549   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6550  },
6551  {
6552   "chips": ["gfx10"],
6553   "map": {"at": 167060, "to": "mm"},
6554   "name": "CB_COLOR0_DCC_BASE",
6555   "type_ref": "DB_HTILE_DATA_BASE"
6556  },
6557  {
6558   "chips": ["gfx10"],
6559   "map": {"at": 167068, "to": "mm"},
6560   "name": "CB_COLOR1_BASE",
6561   "type_ref": "DB_HTILE_DATA_BASE"
6562  },
6563  {
6564   "chips": ["gfx10"],
6565   "map": {"at": 167072, "to": "mm"},
6566   "name": "CB_COLOR1_PITCH",
6567   "type_ref": "CB_COLOR0_PITCH"
6568  },
6569  {
6570   "chips": ["gfx10"],
6571   "map": {"at": 167076, "to": "mm"},
6572   "name": "CB_COLOR1_SLICE",
6573   "type_ref": "CB_COLOR0_SLICE"
6574  },
6575  {
6576   "chips": ["gfx10"],
6577   "map": {"at": 167080, "to": "mm"},
6578   "name": "CB_COLOR1_VIEW",
6579   "type_ref": "CB_COLOR0_VIEW"
6580  },
6581  {
6582   "chips": ["gfx10"],
6583   "map": {"at": 167084, "to": "mm"},
6584   "name": "CB_COLOR1_INFO",
6585   "type_ref": "CB_COLOR0_INFO"
6586  },
6587  {
6588   "chips": ["gfx10"],
6589   "map": {"at": 167088, "to": "mm"},
6590   "name": "CB_COLOR1_ATTRIB",
6591   "type_ref": "CB_COLOR0_ATTRIB"
6592  },
6593  {
6594   "chips": ["gfx10"],
6595   "map": {"at": 167092, "to": "mm"},
6596   "name": "CB_COLOR1_DCC_CONTROL",
6597   "type_ref": "CB_COLOR0_DCC_CONTROL"
6598  },
6599  {
6600   "chips": ["gfx10"],
6601   "map": {"at": 167096, "to": "mm"},
6602   "name": "CB_COLOR1_CMASK",
6603   "type_ref": "DB_HTILE_DATA_BASE"
6604  },
6605  {
6606   "chips": ["gfx10"],
6607   "map": {"at": 167100, "to": "mm"},
6608   "name": "CB_COLOR1_CMASK_SLICE",
6609   "type_ref": "CB_COLOR0_CMASK_SLICE"
6610  },
6611  {
6612   "chips": ["gfx10"],
6613   "map": {"at": 167104, "to": "mm"},
6614   "name": "CB_COLOR1_FMASK",
6615   "type_ref": "DB_HTILE_DATA_BASE"
6616  },
6617  {
6618   "chips": ["gfx10"],
6619   "map": {"at": 167108, "to": "mm"},
6620   "name": "CB_COLOR1_FMASK_SLICE",
6621   "type_ref": "CB_COLOR0_SLICE"
6622  },
6623  {
6624   "chips": ["gfx10"],
6625   "map": {"at": 167112, "to": "mm"},
6626   "name": "CB_COLOR1_CLEAR_WORD0",
6627   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6628  },
6629  {
6630   "chips": ["gfx10"],
6631   "map": {"at": 167116, "to": "mm"},
6632   "name": "CB_COLOR1_CLEAR_WORD1",
6633   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6634  },
6635  {
6636   "chips": ["gfx10"],
6637   "map": {"at": 167120, "to": "mm"},
6638   "name": "CB_COLOR1_DCC_BASE",
6639   "type_ref": "DB_HTILE_DATA_BASE"
6640  },
6641  {
6642   "chips": ["gfx10"],
6643   "map": {"at": 167128, "to": "mm"},
6644   "name": "CB_COLOR2_BASE",
6645   "type_ref": "DB_HTILE_DATA_BASE"
6646  },
6647  {
6648   "chips": ["gfx10"],
6649   "map": {"at": 167132, "to": "mm"},
6650   "name": "CB_COLOR2_PITCH",
6651   "type_ref": "CB_COLOR0_PITCH"
6652  },
6653  {
6654   "chips": ["gfx10"],
6655   "map": {"at": 167136, "to": "mm"},
6656   "name": "CB_COLOR2_SLICE",
6657   "type_ref": "CB_COLOR0_SLICE"
6658  },
6659  {
6660   "chips": ["gfx10"],
6661   "map": {"at": 167140, "to": "mm"},
6662   "name": "CB_COLOR2_VIEW",
6663   "type_ref": "CB_COLOR0_VIEW"
6664  },
6665  {
6666   "chips": ["gfx10"],
6667   "map": {"at": 167144, "to": "mm"},
6668   "name": "CB_COLOR2_INFO",
6669   "type_ref": "CB_COLOR0_INFO"
6670  },
6671  {
6672   "chips": ["gfx10"],
6673   "map": {"at": 167148, "to": "mm"},
6674   "name": "CB_COLOR2_ATTRIB",
6675   "type_ref": "CB_COLOR0_ATTRIB"
6676  },
6677  {
6678   "chips": ["gfx10"],
6679   "map": {"at": 167152, "to": "mm"},
6680   "name": "CB_COLOR2_DCC_CONTROL",
6681   "type_ref": "CB_COLOR0_DCC_CONTROL"
6682  },
6683  {
6684   "chips": ["gfx10"],
6685   "map": {"at": 167156, "to": "mm"},
6686   "name": "CB_COLOR2_CMASK",
6687   "type_ref": "DB_HTILE_DATA_BASE"
6688  },
6689  {
6690   "chips": ["gfx10"],
6691   "map": {"at": 167160, "to": "mm"},
6692   "name": "CB_COLOR2_CMASK_SLICE",
6693   "type_ref": "CB_COLOR0_CMASK_SLICE"
6694  },
6695  {
6696   "chips": ["gfx10"],
6697   "map": {"at": 167164, "to": "mm"},
6698   "name": "CB_COLOR2_FMASK",
6699   "type_ref": "DB_HTILE_DATA_BASE"
6700  },
6701  {
6702   "chips": ["gfx10"],
6703   "map": {"at": 167168, "to": "mm"},
6704   "name": "CB_COLOR2_FMASK_SLICE",
6705   "type_ref": "CB_COLOR0_SLICE"
6706  },
6707  {
6708   "chips": ["gfx10"],
6709   "map": {"at": 167172, "to": "mm"},
6710   "name": "CB_COLOR2_CLEAR_WORD0",
6711   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6712  },
6713  {
6714   "chips": ["gfx10"],
6715   "map": {"at": 167176, "to": "mm"},
6716   "name": "CB_COLOR2_CLEAR_WORD1",
6717   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6718  },
6719  {
6720   "chips": ["gfx10"],
6721   "map": {"at": 167180, "to": "mm"},
6722   "name": "CB_COLOR2_DCC_BASE",
6723   "type_ref": "DB_HTILE_DATA_BASE"
6724  },
6725  {
6726   "chips": ["gfx10"],
6727   "map": {"at": 167188, "to": "mm"},
6728   "name": "CB_COLOR3_BASE",
6729   "type_ref": "DB_HTILE_DATA_BASE"
6730  },
6731  {
6732   "chips": ["gfx10"],
6733   "map": {"at": 167192, "to": "mm"},
6734   "name": "CB_COLOR3_PITCH",
6735   "type_ref": "CB_COLOR0_PITCH"
6736  },
6737  {
6738   "chips": ["gfx10"],
6739   "map": {"at": 167196, "to": "mm"},
6740   "name": "CB_COLOR3_SLICE",
6741   "type_ref": "CB_COLOR0_SLICE"
6742  },
6743  {
6744   "chips": ["gfx10"],
6745   "map": {"at": 167200, "to": "mm"},
6746   "name": "CB_COLOR3_VIEW",
6747   "type_ref": "CB_COLOR0_VIEW"
6748  },
6749  {
6750   "chips": ["gfx10"],
6751   "map": {"at": 167204, "to": "mm"},
6752   "name": "CB_COLOR3_INFO",
6753   "type_ref": "CB_COLOR0_INFO"
6754  },
6755  {
6756   "chips": ["gfx10"],
6757   "map": {"at": 167208, "to": "mm"},
6758   "name": "CB_COLOR3_ATTRIB",
6759   "type_ref": "CB_COLOR0_ATTRIB"
6760  },
6761  {
6762   "chips": ["gfx10"],
6763   "map": {"at": 167212, "to": "mm"},
6764   "name": "CB_COLOR3_DCC_CONTROL",
6765   "type_ref": "CB_COLOR0_DCC_CONTROL"
6766  },
6767  {
6768   "chips": ["gfx10"],
6769   "map": {"at": 167216, "to": "mm"},
6770   "name": "CB_COLOR3_CMASK",
6771   "type_ref": "DB_HTILE_DATA_BASE"
6772  },
6773  {
6774   "chips": ["gfx10"],
6775   "map": {"at": 167220, "to": "mm"},
6776   "name": "CB_COLOR3_CMASK_SLICE",
6777   "type_ref": "CB_COLOR0_CMASK_SLICE"
6778  },
6779  {
6780   "chips": ["gfx10"],
6781   "map": {"at": 167224, "to": "mm"},
6782   "name": "CB_COLOR3_FMASK",
6783   "type_ref": "DB_HTILE_DATA_BASE"
6784  },
6785  {
6786   "chips": ["gfx10"],
6787   "map": {"at": 167228, "to": "mm"},
6788   "name": "CB_COLOR3_FMASK_SLICE",
6789   "type_ref": "CB_COLOR0_SLICE"
6790  },
6791  {
6792   "chips": ["gfx10"],
6793   "map": {"at": 167232, "to": "mm"},
6794   "name": "CB_COLOR3_CLEAR_WORD0",
6795   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6796  },
6797  {
6798   "chips": ["gfx10"],
6799   "map": {"at": 167236, "to": "mm"},
6800   "name": "CB_COLOR3_CLEAR_WORD1",
6801   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6802  },
6803  {
6804   "chips": ["gfx10"],
6805   "map": {"at": 167240, "to": "mm"},
6806   "name": "CB_COLOR3_DCC_BASE",
6807   "type_ref": "DB_HTILE_DATA_BASE"
6808  },
6809  {
6810   "chips": ["gfx10"],
6811   "map": {"at": 167248, "to": "mm"},
6812   "name": "CB_COLOR4_BASE",
6813   "type_ref": "DB_HTILE_DATA_BASE"
6814  },
6815  {
6816   "chips": ["gfx10"],
6817   "map": {"at": 167252, "to": "mm"},
6818   "name": "CB_COLOR4_PITCH",
6819   "type_ref": "CB_COLOR0_PITCH"
6820  },
6821  {
6822   "chips": ["gfx10"],
6823   "map": {"at": 167256, "to": "mm"},
6824   "name": "CB_COLOR4_SLICE",
6825   "type_ref": "CB_COLOR0_SLICE"
6826  },
6827  {
6828   "chips": ["gfx10"],
6829   "map": {"at": 167260, "to": "mm"},
6830   "name": "CB_COLOR4_VIEW",
6831   "type_ref": "CB_COLOR0_VIEW"
6832  },
6833  {
6834   "chips": ["gfx10"],
6835   "map": {"at": 167264, "to": "mm"},
6836   "name": "CB_COLOR4_INFO",
6837   "type_ref": "CB_COLOR0_INFO"
6838  },
6839  {
6840   "chips": ["gfx10"],
6841   "map": {"at": 167268, "to": "mm"},
6842   "name": "CB_COLOR4_ATTRIB",
6843   "type_ref": "CB_COLOR0_ATTRIB"
6844  },
6845  {
6846   "chips": ["gfx10"],
6847   "map": {"at": 167272, "to": "mm"},
6848   "name": "CB_COLOR4_DCC_CONTROL",
6849   "type_ref": "CB_COLOR0_DCC_CONTROL"
6850  },
6851  {
6852   "chips": ["gfx10"],
6853   "map": {"at": 167276, "to": "mm"},
6854   "name": "CB_COLOR4_CMASK",
6855   "type_ref": "DB_HTILE_DATA_BASE"
6856  },
6857  {
6858   "chips": ["gfx10"],
6859   "map": {"at": 167280, "to": "mm"},
6860   "name": "CB_COLOR4_CMASK_SLICE",
6861   "type_ref": "CB_COLOR0_CMASK_SLICE"
6862  },
6863  {
6864   "chips": ["gfx10"],
6865   "map": {"at": 167284, "to": "mm"},
6866   "name": "CB_COLOR4_FMASK",
6867   "type_ref": "DB_HTILE_DATA_BASE"
6868  },
6869  {
6870   "chips": ["gfx10"],
6871   "map": {"at": 167288, "to": "mm"},
6872   "name": "CB_COLOR4_FMASK_SLICE",
6873   "type_ref": "CB_COLOR0_SLICE"
6874  },
6875  {
6876   "chips": ["gfx10"],
6877   "map": {"at": 167292, "to": "mm"},
6878   "name": "CB_COLOR4_CLEAR_WORD0",
6879   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6880  },
6881  {
6882   "chips": ["gfx10"],
6883   "map": {"at": 167296, "to": "mm"},
6884   "name": "CB_COLOR4_CLEAR_WORD1",
6885   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6886  },
6887  {
6888   "chips": ["gfx10"],
6889   "map": {"at": 167300, "to": "mm"},
6890   "name": "CB_COLOR4_DCC_BASE",
6891   "type_ref": "DB_HTILE_DATA_BASE"
6892  },
6893  {
6894   "chips": ["gfx10"],
6895   "map": {"at": 167308, "to": "mm"},
6896   "name": "CB_COLOR5_BASE",
6897   "type_ref": "DB_HTILE_DATA_BASE"
6898  },
6899  {
6900   "chips": ["gfx10"],
6901   "map": {"at": 167312, "to": "mm"},
6902   "name": "CB_COLOR5_PITCH",
6903   "type_ref": "CB_COLOR0_PITCH"
6904  },
6905  {
6906   "chips": ["gfx10"],
6907   "map": {"at": 167316, "to": "mm"},
6908   "name": "CB_COLOR5_SLICE",
6909   "type_ref": "CB_COLOR0_SLICE"
6910  },
6911  {
6912   "chips": ["gfx10"],
6913   "map": {"at": 167320, "to": "mm"},
6914   "name": "CB_COLOR5_VIEW",
6915   "type_ref": "CB_COLOR0_VIEW"
6916  },
6917  {
6918   "chips": ["gfx10"],
6919   "map": {"at": 167324, "to": "mm"},
6920   "name": "CB_COLOR5_INFO",
6921   "type_ref": "CB_COLOR0_INFO"
6922  },
6923  {
6924   "chips": ["gfx10"],
6925   "map": {"at": 167328, "to": "mm"},
6926   "name": "CB_COLOR5_ATTRIB",
6927   "type_ref": "CB_COLOR0_ATTRIB"
6928  },
6929  {
6930   "chips": ["gfx10"],
6931   "map": {"at": 167332, "to": "mm"},
6932   "name": "CB_COLOR5_DCC_CONTROL",
6933   "type_ref": "CB_COLOR0_DCC_CONTROL"
6934  },
6935  {
6936   "chips": ["gfx10"],
6937   "map": {"at": 167336, "to": "mm"},
6938   "name": "CB_COLOR5_CMASK",
6939   "type_ref": "DB_HTILE_DATA_BASE"
6940  },
6941  {
6942   "chips": ["gfx10"],
6943   "map": {"at": 167340, "to": "mm"},
6944   "name": "CB_COLOR5_CMASK_SLICE",
6945   "type_ref": "CB_COLOR0_CMASK_SLICE"
6946  },
6947  {
6948   "chips": ["gfx10"],
6949   "map": {"at": 167344, "to": "mm"},
6950   "name": "CB_COLOR5_FMASK",
6951   "type_ref": "DB_HTILE_DATA_BASE"
6952  },
6953  {
6954   "chips": ["gfx10"],
6955   "map": {"at": 167348, "to": "mm"},
6956   "name": "CB_COLOR5_FMASK_SLICE",
6957   "type_ref": "CB_COLOR0_SLICE"
6958  },
6959  {
6960   "chips": ["gfx10"],
6961   "map": {"at": 167352, "to": "mm"},
6962   "name": "CB_COLOR5_CLEAR_WORD0",
6963   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6964  },
6965  {
6966   "chips": ["gfx10"],
6967   "map": {"at": 167356, "to": "mm"},
6968   "name": "CB_COLOR5_CLEAR_WORD1",
6969   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6970  },
6971  {
6972   "chips": ["gfx10"],
6973   "map": {"at": 167360, "to": "mm"},
6974   "name": "CB_COLOR5_DCC_BASE",
6975   "type_ref": "DB_HTILE_DATA_BASE"
6976  },
6977  {
6978   "chips": ["gfx10"],
6979   "map": {"at": 167368, "to": "mm"},
6980   "name": "CB_COLOR6_BASE",
6981   "type_ref": "DB_HTILE_DATA_BASE"
6982  },
6983  {
6984   "chips": ["gfx10"],
6985   "map": {"at": 167372, "to": "mm"},
6986   "name": "CB_COLOR6_PITCH",
6987   "type_ref": "CB_COLOR0_PITCH"
6988  },
6989  {
6990   "chips": ["gfx10"],
6991   "map": {"at": 167376, "to": "mm"},
6992   "name": "CB_COLOR6_SLICE",
6993   "type_ref": "CB_COLOR0_SLICE"
6994  },
6995  {
6996   "chips": ["gfx10"],
6997   "map": {"at": 167380, "to": "mm"},
6998   "name": "CB_COLOR6_VIEW",
6999   "type_ref": "CB_COLOR0_VIEW"
7000  },
7001  {
7002   "chips": ["gfx10"],
7003   "map": {"at": 167384, "to": "mm"},
7004   "name": "CB_COLOR6_INFO",
7005   "type_ref": "CB_COLOR0_INFO"
7006  },
7007  {
7008   "chips": ["gfx10"],
7009   "map": {"at": 167388, "to": "mm"},
7010   "name": "CB_COLOR6_ATTRIB",
7011   "type_ref": "CB_COLOR0_ATTRIB"
7012  },
7013  {
7014   "chips": ["gfx10"],
7015   "map": {"at": 167392, "to": "mm"},
7016   "name": "CB_COLOR6_DCC_CONTROL",
7017   "type_ref": "CB_COLOR0_DCC_CONTROL"
7018  },
7019  {
7020   "chips": ["gfx10"],
7021   "map": {"at": 167396, "to": "mm"},
7022   "name": "CB_COLOR6_CMASK",
7023   "type_ref": "DB_HTILE_DATA_BASE"
7024  },
7025  {
7026   "chips": ["gfx10"],
7027   "map": {"at": 167400, "to": "mm"},
7028   "name": "CB_COLOR6_CMASK_SLICE",
7029   "type_ref": "CB_COLOR0_CMASK_SLICE"
7030  },
7031  {
7032   "chips": ["gfx10"],
7033   "map": {"at": 167404, "to": "mm"},
7034   "name": "CB_COLOR6_FMASK",
7035   "type_ref": "DB_HTILE_DATA_BASE"
7036  },
7037  {
7038   "chips": ["gfx10"],
7039   "map": {"at": 167408, "to": "mm"},
7040   "name": "CB_COLOR6_FMASK_SLICE",
7041   "type_ref": "CB_COLOR0_SLICE"
7042  },
7043  {
7044   "chips": ["gfx10"],
7045   "map": {"at": 167412, "to": "mm"},
7046   "name": "CB_COLOR6_CLEAR_WORD0",
7047   "type_ref": "CB_COLOR0_CLEAR_WORD0"
7048  },
7049  {
7050   "chips": ["gfx10"],
7051   "map": {"at": 167416, "to": "mm"},
7052   "name": "CB_COLOR6_CLEAR_WORD1",
7053   "type_ref": "CB_COLOR0_CLEAR_WORD1"
7054  },
7055  {
7056   "chips": ["gfx10"],
7057   "map": {"at": 167420, "to": "mm"},
7058   "name": "CB_COLOR6_DCC_BASE",
7059   "type_ref": "DB_HTILE_DATA_BASE"
7060  },
7061  {
7062   "chips": ["gfx10"],
7063   "map": {"at": 167428, "to": "mm"},
7064   "name": "CB_COLOR7_BASE",
7065   "type_ref": "DB_HTILE_DATA_BASE"
7066  },
7067  {
7068   "chips": ["gfx10"],
7069   "map": {"at": 167432, "to": "mm"},
7070   "name": "CB_COLOR7_PITCH",
7071   "type_ref": "CB_COLOR0_PITCH"
7072  },
7073  {
7074   "chips": ["gfx10"],
7075   "map": {"at": 167436, "to": "mm"},
7076   "name": "CB_COLOR7_SLICE",
7077   "type_ref": "CB_COLOR0_SLICE"
7078  },
7079  {
7080   "chips": ["gfx10"],
7081   "map": {"at": 167440, "to": "mm"},
7082   "name": "CB_COLOR7_VIEW",
7083   "type_ref": "CB_COLOR0_VIEW"
7084  },
7085  {
7086   "chips": ["gfx10"],
7087   "map": {"at": 167444, "to": "mm"},
7088   "name": "CB_COLOR7_INFO",
7089   "type_ref": "CB_COLOR0_INFO"
7090  },
7091  {
7092   "chips": ["gfx10"],
7093   "map": {"at": 167448, "to": "mm"},
7094   "name": "CB_COLOR7_ATTRIB",
7095   "type_ref": "CB_COLOR0_ATTRIB"
7096  },
7097  {
7098   "chips": ["gfx10"],
7099   "map": {"at": 167452, "to": "mm"},
7100   "name": "CB_COLOR7_DCC_CONTROL",
7101   "type_ref": "CB_COLOR0_DCC_CONTROL"
7102  },
7103  {
7104   "chips": ["gfx10"],
7105   "map": {"at": 167456, "to": "mm"},
7106   "name": "CB_COLOR7_CMASK",
7107   "type_ref": "DB_HTILE_DATA_BASE"
7108  },
7109  {
7110   "chips": ["gfx10"],
7111   "map": {"at": 167460, "to": "mm"},
7112   "name": "CB_COLOR7_CMASK_SLICE",
7113   "type_ref": "CB_COLOR0_CMASK_SLICE"
7114  },
7115  {
7116   "chips": ["gfx10"],
7117   "map": {"at": 167464, "to": "mm"},
7118   "name": "CB_COLOR7_FMASK",
7119   "type_ref": "DB_HTILE_DATA_BASE"
7120  },
7121  {
7122   "chips": ["gfx10"],
7123   "map": {"at": 167468, "to": "mm"},
7124   "name": "CB_COLOR7_FMASK_SLICE",
7125   "type_ref": "CB_COLOR0_SLICE"
7126  },
7127  {
7128   "chips": ["gfx10"],
7129   "map": {"at": 167472, "to": "mm"},
7130   "name": "CB_COLOR7_CLEAR_WORD0",
7131   "type_ref": "CB_COLOR0_CLEAR_WORD0"
7132  },
7133  {
7134   "chips": ["gfx10"],
7135   "map": {"at": 167476, "to": "mm"},
7136   "name": "CB_COLOR7_CLEAR_WORD1",
7137   "type_ref": "CB_COLOR0_CLEAR_WORD1"
7138  },
7139  {
7140   "chips": ["gfx10"],
7141   "map": {"at": 167480, "to": "mm"},
7142   "name": "CB_COLOR7_DCC_BASE",
7143   "type_ref": "DB_HTILE_DATA_BASE"
7144  },
7145  {
7146   "chips": ["gfx10"],
7147   "map": {"at": 167488, "to": "mm"},
7148   "name": "CB_COLOR0_BASE_EXT",
7149   "type_ref": "CB_COLOR0_BASE_EXT"
7150  },
7151  {
7152   "chips": ["gfx10"],
7153   "map": {"at": 167492, "to": "mm"},
7154   "name": "CB_COLOR1_BASE_EXT",
7155   "type_ref": "CB_COLOR0_BASE_EXT"
7156  },
7157  {
7158   "chips": ["gfx10"],
7159   "map": {"at": 167496, "to": "mm"},
7160   "name": "CB_COLOR2_BASE_EXT",
7161   "type_ref": "CB_COLOR0_BASE_EXT"
7162  },
7163  {
7164   "chips": ["gfx10"],
7165   "map": {"at": 167500, "to": "mm"},
7166   "name": "CB_COLOR3_BASE_EXT",
7167   "type_ref": "CB_COLOR0_BASE_EXT"
7168  },
7169  {
7170   "chips": ["gfx10"],
7171   "map": {"at": 167504, "to": "mm"},
7172   "name": "CB_COLOR4_BASE_EXT",
7173   "type_ref": "CB_COLOR0_BASE_EXT"
7174  },
7175  {
7176   "chips": ["gfx10"],
7177   "map": {"at": 167508, "to": "mm"},
7178   "name": "CB_COLOR5_BASE_EXT",
7179   "type_ref": "CB_COLOR0_BASE_EXT"
7180  },
7181  {
7182   "chips": ["gfx10"],
7183   "map": {"at": 167512, "to": "mm"},
7184   "name": "CB_COLOR6_BASE_EXT",
7185   "type_ref": "CB_COLOR0_BASE_EXT"
7186  },
7187  {
7188   "chips": ["gfx10"],
7189   "map": {"at": 167516, "to": "mm"},
7190   "name": "CB_COLOR7_BASE_EXT",
7191   "type_ref": "CB_COLOR0_BASE_EXT"
7192  },
7193  {
7194   "chips": ["gfx10"],
7195   "map": {"at": 167520, "to": "mm"},
7196   "name": "CB_COLOR0_CMASK_BASE_EXT",
7197   "type_ref": "CB_COLOR0_BASE_EXT"
7198  },
7199  {
7200   "chips": ["gfx10"],
7201   "map": {"at": 167524, "to": "mm"},
7202   "name": "CB_COLOR1_CMASK_BASE_EXT",
7203   "type_ref": "CB_COLOR0_BASE_EXT"
7204  },
7205  {
7206   "chips": ["gfx10"],
7207   "map": {"at": 167528, "to": "mm"},
7208   "name": "CB_COLOR2_CMASK_BASE_EXT",
7209   "type_ref": "CB_COLOR0_BASE_EXT"
7210  },
7211  {
7212   "chips": ["gfx10"],
7213   "map": {"at": 167532, "to": "mm"},
7214   "name": "CB_COLOR3_CMASK_BASE_EXT",
7215   "type_ref": "CB_COLOR0_BASE_EXT"
7216  },
7217  {
7218   "chips": ["gfx10"],
7219   "map": {"at": 167536, "to": "mm"},
7220   "name": "CB_COLOR4_CMASK_BASE_EXT",
7221   "type_ref": "CB_COLOR0_BASE_EXT"
7222  },
7223  {
7224   "chips": ["gfx10"],
7225   "map": {"at": 167540, "to": "mm"},
7226   "name": "CB_COLOR5_CMASK_BASE_EXT",
7227   "type_ref": "CB_COLOR0_BASE_EXT"
7228  },
7229  {
7230   "chips": ["gfx10"],
7231   "map": {"at": 167544, "to": "mm"},
7232   "name": "CB_COLOR6_CMASK_BASE_EXT",
7233   "type_ref": "CB_COLOR0_BASE_EXT"
7234  },
7235  {
7236   "chips": ["gfx10"],
7237   "map": {"at": 167548, "to": "mm"},
7238   "name": "CB_COLOR7_CMASK_BASE_EXT",
7239   "type_ref": "CB_COLOR0_BASE_EXT"
7240  },
7241  {
7242   "chips": ["gfx10"],
7243   "map": {"at": 167552, "to": "mm"},
7244   "name": "CB_COLOR0_FMASK_BASE_EXT",
7245   "type_ref": "CB_COLOR0_BASE_EXT"
7246  },
7247  {
7248   "chips": ["gfx10"],
7249   "map": {"at": 167556, "to": "mm"},
7250   "name": "CB_COLOR1_FMASK_BASE_EXT",
7251   "type_ref": "CB_COLOR0_BASE_EXT"
7252  },
7253  {
7254   "chips": ["gfx10"],
7255   "map": {"at": 167560, "to": "mm"},
7256   "name": "CB_COLOR2_FMASK_BASE_EXT",
7257   "type_ref": "CB_COLOR0_BASE_EXT"
7258  },
7259  {
7260   "chips": ["gfx10"],
7261   "map": {"at": 167564, "to": "mm"},
7262   "name": "CB_COLOR3_FMASK_BASE_EXT",
7263   "type_ref": "CB_COLOR0_BASE_EXT"
7264  },
7265  {
7266   "chips": ["gfx10"],
7267   "map": {"at": 167568, "to": "mm"},
7268   "name": "CB_COLOR4_FMASK_BASE_EXT",
7269   "type_ref": "CB_COLOR0_BASE_EXT"
7270  },
7271  {
7272   "chips": ["gfx10"],
7273   "map": {"at": 167572, "to": "mm"},
7274   "name": "CB_COLOR5_FMASK_BASE_EXT",
7275   "type_ref": "CB_COLOR0_BASE_EXT"
7276  },
7277  {
7278   "chips": ["gfx10"],
7279   "map": {"at": 167576, "to": "mm"},
7280   "name": "CB_COLOR6_FMASK_BASE_EXT",
7281   "type_ref": "CB_COLOR0_BASE_EXT"
7282  },
7283  {
7284   "chips": ["gfx10"],
7285   "map": {"at": 167580, "to": "mm"},
7286   "name": "CB_COLOR7_FMASK_BASE_EXT",
7287   "type_ref": "CB_COLOR0_BASE_EXT"
7288  },
7289  {
7290   "chips": ["gfx10"],
7291   "map": {"at": 167584, "to": "mm"},
7292   "name": "CB_COLOR0_DCC_BASE_EXT",
7293   "type_ref": "CB_COLOR0_BASE_EXT"
7294  },
7295  {
7296   "chips": ["gfx10"],
7297   "map": {"at": 167588, "to": "mm"},
7298   "name": "CB_COLOR1_DCC_BASE_EXT",
7299   "type_ref": "CB_COLOR0_BASE_EXT"
7300  },
7301  {
7302   "chips": ["gfx10"],
7303   "map": {"at": 167592, "to": "mm"},
7304   "name": "CB_COLOR2_DCC_BASE_EXT",
7305   "type_ref": "CB_COLOR0_BASE_EXT"
7306  },
7307  {
7308   "chips": ["gfx10"],
7309   "map": {"at": 167596, "to": "mm"},
7310   "name": "CB_COLOR3_DCC_BASE_EXT",
7311   "type_ref": "CB_COLOR0_BASE_EXT"
7312  },
7313  {
7314   "chips": ["gfx10"],
7315   "map": {"at": 167600, "to": "mm"},
7316   "name": "CB_COLOR4_DCC_BASE_EXT",
7317   "type_ref": "CB_COLOR0_BASE_EXT"
7318  },
7319  {
7320   "chips": ["gfx10"],
7321   "map": {"at": 167604, "to": "mm"},
7322   "name": "CB_COLOR5_DCC_BASE_EXT",
7323   "type_ref": "CB_COLOR0_BASE_EXT"
7324  },
7325  {
7326   "chips": ["gfx10"],
7327   "map": {"at": 167608, "to": "mm"},
7328   "name": "CB_COLOR6_DCC_BASE_EXT",
7329   "type_ref": "CB_COLOR0_BASE_EXT"
7330  },
7331  {
7332   "chips": ["gfx10"],
7333   "map": {"at": 167612, "to": "mm"},
7334   "name": "CB_COLOR7_DCC_BASE_EXT",
7335   "type_ref": "CB_COLOR0_BASE_EXT"
7336  },
7337  {
7338   "chips": ["gfx10"],
7339   "map": {"at": 167616, "to": "mm"},
7340   "name": "CB_COLOR0_ATTRIB2",
7341   "type_ref": "CB_COLOR0_ATTRIB2"
7342  },
7343  {
7344   "chips": ["gfx10"],
7345   "map": {"at": 167620, "to": "mm"},
7346   "name": "CB_COLOR1_ATTRIB2",
7347   "type_ref": "CB_COLOR0_ATTRIB2"
7348  },
7349  {
7350   "chips": ["gfx10"],
7351   "map": {"at": 167624, "to": "mm"},
7352   "name": "CB_COLOR2_ATTRIB2",
7353   "type_ref": "CB_COLOR0_ATTRIB2"
7354  },
7355  {
7356   "chips": ["gfx10"],
7357   "map": {"at": 167628, "to": "mm"},
7358   "name": "CB_COLOR3_ATTRIB2",
7359   "type_ref": "CB_COLOR0_ATTRIB2"
7360  },
7361  {
7362   "chips": ["gfx10"],
7363   "map": {"at": 167632, "to": "mm"},
7364   "name": "CB_COLOR4_ATTRIB2",
7365   "type_ref": "CB_COLOR0_ATTRIB2"
7366  },
7367  {
7368   "chips": ["gfx10"],
7369   "map": {"at": 167636, "to": "mm"},
7370   "name": "CB_COLOR5_ATTRIB2",
7371   "type_ref": "CB_COLOR0_ATTRIB2"
7372  },
7373  {
7374   "chips": ["gfx10"],
7375   "map": {"at": 167640, "to": "mm"},
7376   "name": "CB_COLOR6_ATTRIB2",
7377   "type_ref": "CB_COLOR0_ATTRIB2"
7378  },
7379  {
7380   "chips": ["gfx10"],
7381   "map": {"at": 167644, "to": "mm"},
7382   "name": "CB_COLOR7_ATTRIB2",
7383   "type_ref": "CB_COLOR0_ATTRIB2"
7384  },
7385  {
7386   "chips": ["gfx10"],
7387   "map": {"at": 167648, "to": "mm"},
7388   "name": "CB_COLOR0_ATTRIB3",
7389   "type_ref": "CB_COLOR0_ATTRIB3"
7390  },
7391  {
7392   "chips": ["gfx10"],
7393   "map": {"at": 167652, "to": "mm"},
7394   "name": "CB_COLOR1_ATTRIB3",
7395   "type_ref": "CB_COLOR0_ATTRIB3"
7396  },
7397  {
7398   "chips": ["gfx10"],
7399   "map": {"at": 167656, "to": "mm"},
7400   "name": "CB_COLOR2_ATTRIB3",
7401   "type_ref": "CB_COLOR0_ATTRIB3"
7402  },
7403  {
7404   "chips": ["gfx10"],
7405   "map": {"at": 167660, "to": "mm"},
7406   "name": "CB_COLOR3_ATTRIB3",
7407   "type_ref": "CB_COLOR0_ATTRIB3"
7408  },
7409  {
7410   "chips": ["gfx10"],
7411   "map": {"at": 167664, "to": "mm"},
7412   "name": "CB_COLOR4_ATTRIB3",
7413   "type_ref": "CB_COLOR0_ATTRIB3"
7414  },
7415  {
7416   "chips": ["gfx10"],
7417   "map": {"at": 167668, "to": "mm"},
7418   "name": "CB_COLOR5_ATTRIB3",
7419   "type_ref": "CB_COLOR0_ATTRIB3"
7420  },
7421  {
7422   "chips": ["gfx10"],
7423   "map": {"at": 167672, "to": "mm"},
7424   "name": "CB_COLOR6_ATTRIB3",
7425   "type_ref": "CB_COLOR0_ATTRIB3"
7426  },
7427  {
7428   "chips": ["gfx10"],
7429   "map": {"at": 167676, "to": "mm"},
7430   "name": "CB_COLOR7_ATTRIB3",
7431   "type_ref": "CB_COLOR0_ATTRIB3"
7432  },
7433  {
7434   "chips": ["gfx10"],
7435   "map": {"at": 196608, "to": "mm"},
7436   "name": "CP_EOP_DONE_ADDR_LO",
7437   "type_ref": "CP_EOP_DONE_ADDR_LO"
7438  },
7439  {
7440   "chips": ["gfx10"],
7441   "map": {"at": 196612, "to": "mm"},
7442   "name": "CP_EOP_DONE_ADDR_HI",
7443   "type_ref": "CP_EOP_DONE_ADDR_HI"
7444  },
7445  {
7446   "chips": ["gfx10"],
7447   "map": {"at": 196616, "to": "mm"},
7448   "name": "CP_EOP_DONE_DATA_LO",
7449   "type_ref": "CP_EOP_DONE_DATA_LO"
7450  },
7451  {
7452   "chips": ["gfx10"],
7453   "map": {"at": 196620, "to": "mm"},
7454   "name": "CP_EOP_DONE_DATA_HI",
7455   "type_ref": "CP_EOP_DONE_DATA_HI"
7456  },
7457  {
7458   "chips": ["gfx10"],
7459   "map": {"at": 196624, "to": "mm"},
7460   "name": "CP_EOP_LAST_FENCE_LO",
7461   "type_ref": "CP_EOP_LAST_FENCE_LO"
7462  },
7463  {
7464   "chips": ["gfx10"],
7465   "map": {"at": 196628, "to": "mm"},
7466   "name": "CP_EOP_LAST_FENCE_HI",
7467   "type_ref": "CP_EOP_LAST_FENCE_HI"
7468  },
7469  {
7470   "chips": ["gfx10"],
7471   "map": {"at": 196632, "to": "mm"},
7472   "name": "CP_STREAM_OUT_ADDR_LO",
7473   "type_ref": "CP_STREAM_OUT_ADDR_LO"
7474  },
7475  {
7476   "chips": ["gfx10"],
7477   "map": {"at": 196636, "to": "mm"},
7478   "name": "CP_STREAM_OUT_ADDR_HI",
7479   "type_ref": "CP_STREAM_OUT_ADDR_HI"
7480  },
7481  {
7482   "chips": ["gfx10"],
7483   "map": {"at": 196640, "to": "mm"},
7484   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO",
7485   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
7486  },
7487  {
7488   "chips": ["gfx10"],
7489   "map": {"at": 196644, "to": "mm"},
7490   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI",
7491   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
7492  },
7493  {
7494   "chips": ["gfx10"],
7495   "map": {"at": 196648, "to": "mm"},
7496   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO",
7497   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
7498  },
7499  {
7500   "chips": ["gfx10"],
7501   "map": {"at": 196652, "to": "mm"},
7502   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI",
7503   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
7504  },
7505  {
7506   "chips": ["gfx10"],
7507   "map": {"at": 196656, "to": "mm"},
7508   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO",
7509   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
7510  },
7511  {
7512   "chips": ["gfx10"],
7513   "map": {"at": 196660, "to": "mm"},
7514   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI",
7515   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
7516  },
7517  {
7518   "chips": ["gfx10"],
7519   "map": {"at": 196664, "to": "mm"},
7520   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO",
7521   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
7522  },
7523  {
7524   "chips": ["gfx10"],
7525   "map": {"at": 196668, "to": "mm"},
7526   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI",
7527   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
7528  },
7529  {
7530   "chips": ["gfx10"],
7531   "map": {"at": 196672, "to": "mm"},
7532   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO",
7533   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
7534  },
7535  {
7536   "chips": ["gfx10"],
7537   "map": {"at": 196676, "to": "mm"},
7538   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI",
7539   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
7540  },
7541  {
7542   "chips": ["gfx10"],
7543   "map": {"at": 196680, "to": "mm"},
7544   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO",
7545   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
7546  },
7547  {
7548   "chips": ["gfx10"],
7549   "map": {"at": 196684, "to": "mm"},
7550   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI",
7551   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
7552  },
7553  {
7554   "chips": ["gfx10"],
7555   "map": {"at": 196688, "to": "mm"},
7556   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO",
7557   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
7558  },
7559  {
7560   "chips": ["gfx10"],
7561   "map": {"at": 196692, "to": "mm"},
7562   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI",
7563   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
7564  },
7565  {
7566   "chips": ["gfx10"],
7567   "map": {"at": 196696, "to": "mm"},
7568   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO",
7569   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
7570  },
7571  {
7572   "chips": ["gfx10"],
7573   "map": {"at": 196700, "to": "mm"},
7574   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI",
7575   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
7576  },
7577  {
7578   "chips": ["gfx10"],
7579   "map": {"at": 196704, "to": "mm"},
7580   "name": "CP_PIPE_STATS_ADDR_LO",
7581   "type_ref": "CP_PIPE_STATS_ADDR_LO"
7582  },
7583  {
7584   "chips": ["gfx10"],
7585   "map": {"at": 196708, "to": "mm"},
7586   "name": "CP_PIPE_STATS_ADDR_HI",
7587   "type_ref": "CP_PIPE_STATS_ADDR_HI"
7588  },
7589  {
7590   "chips": ["gfx10"],
7591   "map": {"at": 196712, "to": "mm"},
7592   "name": "CP_VGT_IAVERT_COUNT_LO",
7593   "type_ref": "CP_VGT_IAVERT_COUNT_LO"
7594  },
7595  {
7596   "chips": ["gfx10"],
7597   "map": {"at": 196716, "to": "mm"},
7598   "name": "CP_VGT_IAVERT_COUNT_HI",
7599   "type_ref": "CP_VGT_IAVERT_COUNT_HI"
7600  },
7601  {
7602   "chips": ["gfx10"],
7603   "map": {"at": 196720, "to": "mm"},
7604   "name": "CP_VGT_IAPRIM_COUNT_LO",
7605   "type_ref": "CP_VGT_IAPRIM_COUNT_LO"
7606  },
7607  {
7608   "chips": ["gfx10"],
7609   "map": {"at": 196724, "to": "mm"},
7610   "name": "CP_VGT_IAPRIM_COUNT_HI",
7611   "type_ref": "CP_VGT_IAPRIM_COUNT_HI"
7612  },
7613  {
7614   "chips": ["gfx10"],
7615   "map": {"at": 196728, "to": "mm"},
7616   "name": "CP_VGT_GSPRIM_COUNT_LO",
7617   "type_ref": "CP_VGT_GSPRIM_COUNT_LO"
7618  },
7619  {
7620   "chips": ["gfx10"],
7621   "map": {"at": 196732, "to": "mm"},
7622   "name": "CP_VGT_GSPRIM_COUNT_HI",
7623   "type_ref": "CP_VGT_GSPRIM_COUNT_HI"
7624  },
7625  {
7626   "chips": ["gfx10"],
7627   "map": {"at": 196736, "to": "mm"},
7628   "name": "CP_VGT_VSINVOC_COUNT_LO",
7629   "type_ref": "CP_VGT_VSINVOC_COUNT_LO"
7630  },
7631  {
7632   "chips": ["gfx10"],
7633   "map": {"at": 196740, "to": "mm"},
7634   "name": "CP_VGT_VSINVOC_COUNT_HI",
7635   "type_ref": "CP_VGT_VSINVOC_COUNT_HI"
7636  },
7637  {
7638   "chips": ["gfx10"],
7639   "map": {"at": 196744, "to": "mm"},
7640   "name": "CP_VGT_GSINVOC_COUNT_LO",
7641   "type_ref": "CP_VGT_GSINVOC_COUNT_LO"
7642  },
7643  {
7644   "chips": ["gfx10"],
7645   "map": {"at": 196748, "to": "mm"},
7646   "name": "CP_VGT_GSINVOC_COUNT_HI",
7647   "type_ref": "CP_VGT_GSINVOC_COUNT_HI"
7648  },
7649  {
7650   "chips": ["gfx10"],
7651   "map": {"at": 196752, "to": "mm"},
7652   "name": "CP_VGT_HSINVOC_COUNT_LO",
7653   "type_ref": "CP_VGT_HSINVOC_COUNT_LO"
7654  },
7655  {
7656   "chips": ["gfx10"],
7657   "map": {"at": 196756, "to": "mm"},
7658   "name": "CP_VGT_HSINVOC_COUNT_HI",
7659   "type_ref": "CP_VGT_HSINVOC_COUNT_HI"
7660  },
7661  {
7662   "chips": ["gfx10"],
7663   "map": {"at": 196760, "to": "mm"},
7664   "name": "CP_VGT_DSINVOC_COUNT_LO",
7665   "type_ref": "CP_VGT_DSINVOC_COUNT_LO"
7666  },
7667  {
7668   "chips": ["gfx10"],
7669   "map": {"at": 196764, "to": "mm"},
7670   "name": "CP_VGT_DSINVOC_COUNT_HI",
7671   "type_ref": "CP_VGT_DSINVOC_COUNT_HI"
7672  },
7673  {
7674   "chips": ["gfx10"],
7675   "map": {"at": 196768, "to": "mm"},
7676   "name": "CP_PA_CINVOC_COUNT_LO",
7677   "type_ref": "CP_PA_CINVOC_COUNT_LO"
7678  },
7679  {
7680   "chips": ["gfx10"],
7681   "map": {"at": 196772, "to": "mm"},
7682   "name": "CP_PA_CINVOC_COUNT_HI",
7683   "type_ref": "CP_PA_CINVOC_COUNT_HI"
7684  },
7685  {
7686   "chips": ["gfx10"],
7687   "map": {"at": 196776, "to": "mm"},
7688   "name": "CP_PA_CPRIM_COUNT_LO",
7689   "type_ref": "CP_PA_CPRIM_COUNT_LO"
7690  },
7691  {
7692   "chips": ["gfx10"],
7693   "map": {"at": 196780, "to": "mm"},
7694   "name": "CP_PA_CPRIM_COUNT_HI",
7695   "type_ref": "CP_PA_CPRIM_COUNT_HI"
7696  },
7697  {
7698   "chips": ["gfx10"],
7699   "map": {"at": 196784, "to": "mm"},
7700   "name": "CP_SC_PSINVOC_COUNT0_LO",
7701   "type_ref": "CP_SC_PSINVOC_COUNT0_LO"
7702  },
7703  {
7704   "chips": ["gfx10"],
7705   "map": {"at": 196788, "to": "mm"},
7706   "name": "CP_SC_PSINVOC_COUNT0_HI",
7707   "type_ref": "CP_SC_PSINVOC_COUNT0_HI"
7708  },
7709  {
7710   "chips": ["gfx10"],
7711   "map": {"at": 196792, "to": "mm"},
7712   "name": "CP_SC_PSINVOC_COUNT1_LO",
7713   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7714  },
7715  {
7716   "chips": ["gfx10"],
7717   "map": {"at": 196796, "to": "mm"},
7718   "name": "CP_SC_PSINVOC_COUNT1_HI",
7719   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7720  },
7721  {
7722   "chips": ["gfx10"],
7723   "map": {"at": 196800, "to": "mm"},
7724   "name": "CP_VGT_CSINVOC_COUNT_LO",
7725   "type_ref": "CP_VGT_CSINVOC_COUNT_LO"
7726  },
7727  {
7728   "chips": ["gfx10"],
7729   "map": {"at": 196804, "to": "mm"},
7730   "name": "CP_VGT_CSINVOC_COUNT_HI",
7731   "type_ref": "CP_VGT_CSINVOC_COUNT_HI"
7732  },
7733  {
7734   "chips": ["gfx10"],
7735   "map": {"at": 196808, "to": "mm"},
7736   "name": "CP_EOP_DONE_DOORBELL",
7737   "type_ref": "CP_EOP_DONE_DOORBELL"
7738  },
7739  {
7740   "chips": ["gfx10"],
7741   "map": {"at": 196812, "to": "mm"},
7742   "name": "CP_STREAM_OUT_DOORBELL",
7743   "type_ref": "CP_EOP_DONE_DOORBELL"
7744  },
7745  {
7746   "chips": ["gfx10"],
7747   "map": {"at": 196816, "to": "mm"},
7748   "name": "CP_SEM_DOORBELL",
7749   "type_ref": "CP_EOP_DONE_DOORBELL"
7750  },
7751  {
7752   "chips": ["gfx10"],
7753   "map": {"at": 196852, "to": "mm"},
7754   "name": "CP_PIPE_STATS_CONTROL",
7755   "type_ref": "CP_PIPE_STATS_CONTROL"
7756  },
7757  {
7758   "chips": ["gfx10"],
7759   "map": {"at": 196856, "to": "mm"},
7760   "name": "CP_STREAM_OUT_CONTROL",
7761   "type_ref": "CP_PIPE_STATS_CONTROL"
7762  },
7763  {
7764   "chips": ["gfx10"],
7765   "map": {"at": 196860, "to": "mm"},
7766   "name": "CP_STRMOUT_CNTL",
7767   "type_ref": "CP_STRMOUT_CNTL"
7768  },
7769  {
7770   "chips": ["gfx10"],
7771   "map": {"at": 196864, "to": "mm"},
7772   "name": "SCRATCH_REG0",
7773   "type_ref": "SCRATCH_REG0"
7774  },
7775  {
7776   "chips": ["gfx10"],
7777   "map": {"at": 196868, "to": "mm"},
7778   "name": "SCRATCH_REG1",
7779   "type_ref": "SCRATCH_REG1"
7780  },
7781  {
7782   "chips": ["gfx10"],
7783   "map": {"at": 196872, "to": "mm"},
7784   "name": "SCRATCH_REG2",
7785   "type_ref": "SCRATCH_REG2"
7786  },
7787  {
7788   "chips": ["gfx10"],
7789   "map": {"at": 196876, "to": "mm"},
7790   "name": "SCRATCH_REG3",
7791   "type_ref": "SCRATCH_REG3"
7792  },
7793  {
7794   "chips": ["gfx10"],
7795   "map": {"at": 196880, "to": "mm"},
7796   "name": "SCRATCH_REG4",
7797   "type_ref": "SCRATCH_REG4"
7798  },
7799  {
7800   "chips": ["gfx10"],
7801   "map": {"at": 196884, "to": "mm"},
7802   "name": "SCRATCH_REG5",
7803   "type_ref": "SCRATCH_REG5"
7804  },
7805  {
7806   "chips": ["gfx10"],
7807   "map": {"at": 196888, "to": "mm"},
7808   "name": "SCRATCH_REG6",
7809   "type_ref": "SCRATCH_REG6"
7810  },
7811  {
7812   "chips": ["gfx10"],
7813   "map": {"at": 196892, "to": "mm"},
7814   "name": "SCRATCH_REG7",
7815   "type_ref": "SCRATCH_REG7"
7816  },
7817  {
7818   "chips": ["gfx10"],
7819   "map": {"at": 196896, "to": "mm"},
7820   "name": "CP_PIPE_STATS_DOORBELL",
7821   "type_ref": "CP_EOP_DONE_DOORBELL"
7822  },
7823  {
7824   "chips": ["gfx10"],
7825   "map": {"at": 196908, "to": "mm"},
7826   "name": "CP_APPEND_DDID_CNT",
7827   "type_ref": "COMPUTE_PGM_HI"
7828  },
7829  {
7830   "chips": ["gfx10"],
7831   "map": {"at": 196912, "to": "mm"},
7832   "name": "CP_APPEND_DATA_HI",
7833   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7834  },
7835  {
7836   "chips": ["gfx10"],
7837   "map": {"at": 196916, "to": "mm"},
7838   "name": "CP_APPEND_LAST_CS_FENCE_HI",
7839   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7840  },
7841  {
7842   "chips": ["gfx10"],
7843   "map": {"at": 196920, "to": "mm"},
7844   "name": "CP_APPEND_LAST_PS_FENCE_HI",
7845   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7846  },
7847  {
7848   "chips": ["gfx10"],
7849   "map": {"at": 196928, "to": "mm"},
7850   "name": "SCRATCH_UMSK",
7851   "type_ref": "SCRATCH_UMSK"
7852  },
7853  {
7854   "chips": ["gfx10"],
7855   "map": {"at": 196932, "to": "mm"},
7856   "name": "SCRATCH_ADDR",
7857   "type_ref": "SCRATCH_ADDR"
7858  },
7859  {
7860   "chips": ["gfx10"],
7861   "map": {"at": 196936, "to": "mm"},
7862   "name": "CP_PFP_ATOMIC_PREOP_LO",
7863   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7864  },
7865  {
7866   "chips": ["gfx10"],
7867   "map": {"at": 196940, "to": "mm"},
7868   "name": "CP_PFP_ATOMIC_PREOP_HI",
7869   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7870  },
7871  {
7872   "chips": ["gfx10"],
7873   "map": {"at": 196944, "to": "mm"},
7874   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO",
7875   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7876  },
7877  {
7878   "chips": ["gfx10"],
7879   "map": {"at": 196948, "to": "mm"},
7880   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI",
7881   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7882  },
7883  {
7884   "chips": ["gfx10"],
7885   "map": {"at": 196952, "to": "mm"},
7886   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO",
7887   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7888  },
7889  {
7890   "chips": ["gfx10"],
7891   "map": {"at": 196956, "to": "mm"},
7892   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI",
7893   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7894  },
7895  {
7896   "chips": ["gfx10"],
7897   "map": {"at": 196960, "to": "mm"},
7898   "name": "CP_APPEND_ADDR_LO",
7899   "type_ref": "CP_APPEND_ADDR_LO"
7900  },
7901  {
7902   "chips": ["gfx10"],
7903   "map": {"at": 196964, "to": "mm"},
7904   "name": "CP_APPEND_ADDR_HI",
7905   "type_ref": "CP_APPEND_ADDR_HI"
7906  },
7907  {
7908   "chips": ["gfx10"],
7909   "map": {"at": 196968, "to": "mm"},
7910   "name": "CP_APPEND_DATA",
7911   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7912  },
7913  {
7914   "chips": ["gfx10"],
7915   "map": {"at": 196972, "to": "mm"},
7916   "name": "CP_APPEND_LAST_CS_FENCE",
7917   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7918  },
7919  {
7920   "chips": ["gfx10"],
7921   "map": {"at": 196976, "to": "mm"},
7922   "name": "CP_APPEND_LAST_PS_FENCE",
7923   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7924  },
7925  {
7926   "chips": ["gfx10"],
7927   "map": {"at": 196980, "to": "mm"},
7928   "name": "CP_ATOMIC_PREOP_LO",
7929   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7930  },
7931  {
7932   "chips": ["gfx10"],
7933   "map": {"at": 196984, "to": "mm"},
7934   "name": "CP_ATOMIC_PREOP_HI",
7935   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7936  },
7937  {
7938   "chips": ["gfx10"],
7939   "map": {"at": 196988, "to": "mm"},
7940   "name": "CP_GDS_ATOMIC0_PREOP_LO",
7941   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7942  },
7943  {
7944   "chips": ["gfx10"],
7945   "map": {"at": 196992, "to": "mm"},
7946   "name": "CP_GDS_ATOMIC0_PREOP_HI",
7947   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7948  },
7949  {
7950   "chips": ["gfx10"],
7951   "map": {"at": 196996, "to": "mm"},
7952   "name": "CP_GDS_ATOMIC1_PREOP_LO",
7953   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7954  },
7955  {
7956   "chips": ["gfx10"],
7957   "map": {"at": 197000, "to": "mm"},
7958   "name": "CP_GDS_ATOMIC1_PREOP_HI",
7959   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7960  },
7961  {
7962   "chips": ["gfx10"],
7963   "map": {"at": 197028, "to": "mm"},
7964   "name": "CP_ME_MC_WADDR_LO",
7965   "type_ref": "CP_ME_MC_WADDR_LO"
7966  },
7967  {
7968   "chips": ["gfx10"],
7969   "map": {"at": 197032, "to": "mm"},
7970   "name": "CP_ME_MC_WADDR_HI",
7971   "type_ref": "CP_ME_MC_WADDR_HI"
7972  },
7973  {
7974   "chips": ["gfx10"],
7975   "map": {"at": 197036, "to": "mm"},
7976   "name": "CP_ME_MC_WDATA_LO",
7977   "type_ref": "CP_ME_MC_WDATA_LO"
7978  },
7979  {
7980   "chips": ["gfx10"],
7981   "map": {"at": 197040, "to": "mm"},
7982   "name": "CP_ME_MC_WDATA_HI",
7983   "type_ref": "CP_ME_MC_WDATA_HI"
7984  },
7985  {
7986   "chips": ["gfx10"],
7987   "map": {"at": 197044, "to": "mm"},
7988   "name": "CP_ME_MC_RADDR_LO",
7989   "type_ref": "CP_ME_MC_RADDR_LO"
7990  },
7991  {
7992   "chips": ["gfx10"],
7993   "map": {"at": 197048, "to": "mm"},
7994   "name": "CP_ME_MC_RADDR_HI",
7995   "type_ref": "CP_ME_MC_RADDR_HI"
7996  },
7997  {
7998   "chips": ["gfx10"],
7999   "map": {"at": 197052, "to": "mm"},
8000   "name": "CP_SEM_WAIT_TIMER",
8001   "type_ref": "CP_SEM_WAIT_TIMER"
8002  },
8003  {
8004   "chips": ["gfx10"],
8005   "map": {"at": 197056, "to": "mm"},
8006   "name": "CP_SIG_SEM_ADDR_LO",
8007   "type_ref": "CP_SIG_SEM_ADDR_LO"
8008  },
8009  {
8010   "chips": ["gfx10"],
8011   "map": {"at": 197060, "to": "mm"},
8012   "name": "CP_SIG_SEM_ADDR_HI",
8013   "type_ref": "CP_SIG_SEM_ADDR_HI"
8014  },
8015  {
8016   "chips": ["gfx10"],
8017   "map": {"at": 197072, "to": "mm"},
8018   "name": "CP_WAIT_REG_MEM_TIMEOUT",
8019   "type_ref": "CP_WAIT_REG_MEM_TIMEOUT"
8020  },
8021  {
8022   "chips": ["gfx10"],
8023   "map": {"at": 197076, "to": "mm"},
8024   "name": "CP_WAIT_SEM_ADDR_LO",
8025   "type_ref": "CP_SIG_SEM_ADDR_LO"
8026  },
8027  {
8028   "chips": ["gfx10"],
8029   "map": {"at": 197080, "to": "mm"},
8030   "name": "CP_WAIT_SEM_ADDR_HI",
8031   "type_ref": "CP_SIG_SEM_ADDR_HI"
8032  },
8033  {
8034   "chips": ["gfx10"],
8035   "map": {"at": 197084, "to": "mm"},
8036   "name": "CP_DMA_PFP_CONTROL",
8037   "type_ref": "CP_DMA_PFP_CONTROL"
8038  },
8039  {
8040   "chips": ["gfx10"],
8041   "map": {"at": 197088, "to": "mm"},
8042   "name": "CP_DMA_ME_CONTROL",
8043   "type_ref": "CP_DMA_PFP_CONTROL"
8044  },
8045  {
8046   "chips": ["gfx10"],
8047   "map": {"at": 197092, "to": "mm"},
8048   "name": "CP_COHER_BASE_HI",
8049   "type_ref": "CP_COHER_BASE_HI"
8050  },
8051  {
8052   "chips": ["gfx10"],
8053   "map": {"at": 197100, "to": "mm"},
8054   "name": "CP_COHER_START_DELAY",
8055   "type_ref": "CP_COHER_START_DELAY"
8056  },
8057  {
8058   "chips": ["gfx10"],
8059   "map": {"at": 197104, "to": "mm"},
8060   "name": "CP_COHER_CNTL",
8061   "type_ref": "CP_COHER_CNTL"
8062  },
8063  {
8064   "chips": ["gfx10"],
8065   "map": {"at": 197108, "to": "mm"},
8066   "name": "CP_COHER_SIZE",
8067   "type_ref": "CP_COHER_SIZE"
8068  },
8069  {
8070   "chips": ["gfx10"],
8071   "map": {"at": 197112, "to": "mm"},
8072   "name": "CP_COHER_BASE",
8073   "type_ref": "CP_COHER_BASE"
8074  },
8075  {
8076   "chips": ["gfx10"],
8077   "map": {"at": 197116, "to": "mm"},
8078   "name": "CP_COHER_STATUS",
8079   "type_ref": "CP_COHER_STATUS"
8080  },
8081  {
8082   "chips": ["gfx10"],
8083   "map": {"at": 197120, "to": "mm"},
8084   "name": "CP_DMA_ME_SRC_ADDR",
8085   "type_ref": "CP_DMA_ME_SRC_ADDR"
8086  },
8087  {
8088   "chips": ["gfx10"],
8089   "map": {"at": 197124, "to": "mm"},
8090   "name": "CP_DMA_ME_SRC_ADDR_HI",
8091   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
8092  },
8093  {
8094   "chips": ["gfx10"],
8095   "map": {"at": 197128, "to": "mm"},
8096   "name": "CP_DMA_ME_DST_ADDR",
8097   "type_ref": "CP_DMA_ME_DST_ADDR"
8098  },
8099  {
8100   "chips": ["gfx10"],
8101   "map": {"at": 197132, "to": "mm"},
8102   "name": "CP_DMA_ME_DST_ADDR_HI",
8103   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
8104  },
8105  {
8106   "chips": ["gfx10"],
8107   "map": {"at": 197136, "to": "mm"},
8108   "name": "CP_DMA_ME_COMMAND",
8109   "type_ref": "CP_DMA_ME_COMMAND"
8110  },
8111  {
8112   "chips": ["gfx10"],
8113   "map": {"at": 197140, "to": "mm"},
8114   "name": "CP_DMA_PFP_SRC_ADDR",
8115   "type_ref": "CP_DMA_ME_SRC_ADDR"
8116  },
8117  {
8118   "chips": ["gfx10"],
8119   "map": {"at": 197144, "to": "mm"},
8120   "name": "CP_DMA_PFP_SRC_ADDR_HI",
8121   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
8122  },
8123  {
8124   "chips": ["gfx10"],
8125   "map": {"at": 197148, "to": "mm"},
8126   "name": "CP_DMA_PFP_DST_ADDR",
8127   "type_ref": "CP_DMA_ME_DST_ADDR"
8128  },
8129  {
8130   "chips": ["gfx10"],
8131   "map": {"at": 197152, "to": "mm"},
8132   "name": "CP_DMA_PFP_DST_ADDR_HI",
8133   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
8134  },
8135  {
8136   "chips": ["gfx10"],
8137   "map": {"at": 197156, "to": "mm"},
8138   "name": "CP_DMA_PFP_COMMAND",
8139   "type_ref": "CP_DMA_ME_COMMAND"
8140  },
8141  {
8142   "chips": ["gfx10"],
8143   "map": {"at": 197160, "to": "mm"},
8144   "name": "CP_DMA_CNTL",
8145   "type_ref": "CP_DMA_CNTL"
8146  },
8147  {
8148   "chips": ["gfx10"],
8149   "map": {"at": 197164, "to": "mm"},
8150   "name": "CP_DMA_READ_TAGS",
8151   "type_ref": "CP_DMA_READ_TAGS"
8152  },
8153  {
8154   "chips": ["gfx10"],
8155   "map": {"at": 197168, "to": "mm"},
8156   "name": "CP_COHER_SIZE_HI",
8157   "type_ref": "CP_COHER_SIZE_HI"
8158  },
8159  {
8160   "chips": ["gfx10"],
8161   "map": {"at": 197172, "to": "mm"},
8162   "name": "CP_PFP_IB_CONTROL",
8163   "type_ref": "CP_PFP_IB_CONTROL"
8164  },
8165  {
8166   "chips": ["gfx10"],
8167   "map": {"at": 197176, "to": "mm"},
8168   "name": "CP_PFP_LOAD_CONTROL",
8169   "type_ref": "CP_PFP_LOAD_CONTROL"
8170  },
8171  {
8172   "chips": ["gfx10"],
8173   "map": {"at": 197180, "to": "mm"},
8174   "name": "CP_SCRATCH_INDEX",
8175   "type_ref": "CP_SCRATCH_INDEX"
8176  },
8177  {
8178   "chips": ["gfx10"],
8179   "map": {"at": 197184, "to": "mm"},
8180   "name": "CP_SCRATCH_DATA",
8181   "type_ref": "CP_CPC_SCRATCH_DATA"
8182  },
8183  {
8184   "chips": ["gfx10"],
8185   "map": {"at": 197188, "to": "mm"},
8186   "name": "CP_RB_OFFSET",
8187   "type_ref": "CP_RB_OFFSET"
8188  },
8189  {
8190   "chips": ["gfx10"],
8191   "map": {"at": 197192, "to": "mm"},
8192   "name": "CP_IB1_OFFSET",
8193   "type_ref": "CP_IB1_OFFSET"
8194  },
8195  {
8196   "chips": ["gfx10"],
8197   "map": {"at": 197196, "to": "mm"},
8198   "name": "CP_IB2_OFFSET",
8199   "type_ref": "CP_IB2_OFFSET"
8200  },
8201  {
8202   "chips": ["gfx10"],
8203   "map": {"at": 197200, "to": "mm"},
8204   "name": "CP_IB1_PREAMBLE_BEGIN",
8205   "type_ref": "CP_IB1_PREAMBLE_BEGIN"
8206  },
8207  {
8208   "chips": ["gfx10"],
8209   "map": {"at": 197204, "to": "mm"},
8210   "name": "CP_IB1_PREAMBLE_END",
8211   "type_ref": "CP_IB1_PREAMBLE_END"
8212  },
8213  {
8214   "chips": ["gfx10"],
8215   "map": {"at": 197208, "to": "mm"},
8216   "name": "CP_IB2_PREAMBLE_BEGIN",
8217   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
8218  },
8219  {
8220   "chips": ["gfx10"],
8221   "map": {"at": 197212, "to": "mm"},
8222   "name": "CP_IB2_PREAMBLE_END",
8223   "type_ref": "CP_IB2_PREAMBLE_END"
8224  },
8225  {
8226   "chips": ["gfx10"],
8227   "map": {"at": 197216, "to": "mm"},
8228   "name": "CP_CE_IB1_OFFSET",
8229   "type_ref": "CP_IB1_OFFSET"
8230  },
8231  {
8232   "chips": ["gfx10"],
8233   "map": {"at": 197220, "to": "mm"},
8234   "name": "CP_CE_IB2_OFFSET",
8235   "type_ref": "CP_IB2_OFFSET"
8236  },
8237  {
8238   "chips": ["gfx10"],
8239   "map": {"at": 197224, "to": "mm"},
8240   "name": "CP_CE_COUNTER",
8241   "type_ref": "CP_CE_COUNTER"
8242  },
8243  {
8244   "chips": ["gfx10"],
8245   "map": {"at": 197232, "to": "mm"},
8246   "name": "CP_DMA_ME_CMD_ADDR_LO",
8247   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8248  },
8249  {
8250   "chips": ["gfx10"],
8251   "map": {"at": 197236, "to": "mm"},
8252   "name": "CP_DMA_ME_CMD_ADDR_HI",
8253   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8254  },
8255  {
8256   "chips": ["gfx10"],
8257   "map": {"at": 197240, "to": "mm"},
8258   "name": "CP_DMA_PFP_CMD_ADDR_LO",
8259   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8260  },
8261  {
8262   "chips": ["gfx10"],
8263   "map": {"at": 197244, "to": "mm"},
8264   "name": "CP_DMA_PFP_CMD_ADDR_HI",
8265   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8266  },
8267  {
8268   "chips": ["gfx10"],
8269   "map": {"at": 197248, "to": "mm"},
8270   "name": "CP_APPEND_CMD_ADDR_LO",
8271   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
8272  },
8273  {
8274   "chips": ["gfx10"],
8275   "map": {"at": 197252, "to": "mm"},
8276   "name": "CP_APPEND_CMD_ADDR_HI",
8277   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
8278  },
8279  {
8280   "chips": ["gfx10"],
8281   "map": {"at": 197364, "to": "mm"},
8282   "name": "CP_CE_INIT_CMD_BUFSZ",
8283   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
8284  },
8285  {
8286   "chips": ["gfx10"],
8287   "map": {"at": 197368, "to": "mm"},
8288   "name": "CP_CE_IB1_CMD_BUFSZ",
8289   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
8290  },
8291  {
8292   "chips": ["gfx10"],
8293   "map": {"at": 197372, "to": "mm"},
8294   "name": "CP_CE_IB2_CMD_BUFSZ",
8295   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
8296  },
8297  {
8298   "chips": ["gfx10"],
8299   "map": {"at": 197376, "to": "mm"},
8300   "name": "CP_IB1_CMD_BUFSZ",
8301   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
8302  },
8303  {
8304   "chips": ["gfx10"],
8305   "map": {"at": 197380, "to": "mm"},
8306   "name": "CP_IB2_CMD_BUFSZ",
8307   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
8308  },
8309  {
8310   "chips": ["gfx10"],
8311   "map": {"at": 197384, "to": "mm"},
8312   "name": "CP_ST_CMD_BUFSZ",
8313   "type_ref": "CP_ST_CMD_BUFSZ"
8314  },
8315  {
8316   "chips": ["gfx10"],
8317   "map": {"at": 197388, "to": "mm"},
8318   "name": "CP_CE_INIT_BASE_LO",
8319   "type_ref": "CP_CE_INIT_BASE_LO"
8320  },
8321  {
8322   "chips": ["gfx10"],
8323   "map": {"at": 197392, "to": "mm"},
8324   "name": "CP_CE_INIT_BASE_HI",
8325   "type_ref": "CP_CE_INIT_BASE_HI"
8326  },
8327  {
8328   "chips": ["gfx10"],
8329   "map": {"at": 197396, "to": "mm"},
8330   "name": "CP_CE_INIT_BUFSZ",
8331   "type_ref": "CP_CE_INIT_BUFSZ"
8332  },
8333  {
8334   "chips": ["gfx10"],
8335   "map": {"at": 197400, "to": "mm"},
8336   "name": "CP_CE_IB1_BASE_LO",
8337   "type_ref": "CP_CE_IB1_BASE_LO"
8338  },
8339  {
8340   "chips": ["gfx10"],
8341   "map": {"at": 197404, "to": "mm"},
8342   "name": "CP_CE_IB1_BASE_HI",
8343   "type_ref": "CP_CE_IB1_BASE_HI"
8344  },
8345  {
8346   "chips": ["gfx10"],
8347   "map": {"at": 197408, "to": "mm"},
8348   "name": "CP_CE_IB1_BUFSZ",
8349   "type_ref": "CP_CE_IB1_BUFSZ"
8350  },
8351  {
8352   "chips": ["gfx10"],
8353   "map": {"at": 197412, "to": "mm"},
8354   "name": "CP_CE_IB2_BASE_LO",
8355   "type_ref": "CP_CE_IB2_BASE_LO"
8356  },
8357  {
8358   "chips": ["gfx10"],
8359   "map": {"at": 197416, "to": "mm"},
8360   "name": "CP_CE_IB2_BASE_HI",
8361   "type_ref": "CP_CE_IB2_BASE_HI"
8362  },
8363  {
8364   "chips": ["gfx10"],
8365   "map": {"at": 197420, "to": "mm"},
8366   "name": "CP_CE_IB2_BUFSZ",
8367   "type_ref": "CP_CE_IB2_BUFSZ"
8368  },
8369  {
8370   "chips": ["gfx10"],
8371   "map": {"at": 197424, "to": "mm"},
8372   "name": "CP_IB1_BASE_LO",
8373   "type_ref": "CP_CE_IB1_BASE_LO"
8374  },
8375  {
8376   "chips": ["gfx10"],
8377   "map": {"at": 197428, "to": "mm"},
8378   "name": "CP_IB1_BASE_HI",
8379   "type_ref": "CP_CE_IB1_BASE_HI"
8380  },
8381  {
8382   "chips": ["gfx10"],
8383   "map": {"at": 197432, "to": "mm"},
8384   "name": "CP_IB1_BUFSZ",
8385   "type_ref": "CP_CE_IB1_BUFSZ"
8386  },
8387  {
8388   "chips": ["gfx10"],
8389   "map": {"at": 197436, "to": "mm"},
8390   "name": "CP_IB2_BASE_LO",
8391   "type_ref": "CP_CE_IB2_BASE_LO"
8392  },
8393  {
8394   "chips": ["gfx10"],
8395   "map": {"at": 197440, "to": "mm"},
8396   "name": "CP_IB2_BASE_HI",
8397   "type_ref": "CP_CE_IB2_BASE_HI"
8398  },
8399  {
8400   "chips": ["gfx10"],
8401   "map": {"at": 197444, "to": "mm"},
8402   "name": "CP_IB2_BUFSZ",
8403   "type_ref": "CP_CE_IB2_BUFSZ"
8404  },
8405  {
8406   "chips": ["gfx10"],
8407   "map": {"at": 197448, "to": "mm"},
8408   "name": "CP_ST_BASE_LO",
8409   "type_ref": "CP_ST_BASE_LO"
8410  },
8411  {
8412   "chips": ["gfx10"],
8413   "map": {"at": 197452, "to": "mm"},
8414   "name": "CP_ST_BASE_HI",
8415   "type_ref": "CP_ST_BASE_HI"
8416  },
8417  {
8418   "chips": ["gfx10"],
8419   "map": {"at": 197456, "to": "mm"},
8420   "name": "CP_ST_BUFSZ",
8421   "type_ref": "CP_ST_BUFSZ"
8422  },
8423  {
8424   "chips": ["gfx10"],
8425   "map": {"at": 197460, "to": "mm"},
8426   "name": "CP_EOP_DONE_EVENT_CNTL",
8427   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
8428  },
8429  {
8430   "chips": ["gfx10"],
8431   "map": {"at": 197464, "to": "mm"},
8432   "name": "CP_EOP_DONE_DATA_CNTL",
8433   "type_ref": "CP_EOP_DONE_DATA_CNTL"
8434  },
8435  {
8436   "chips": ["gfx10"],
8437   "map": {"at": 197468, "to": "mm"},
8438   "name": "CP_EOP_DONE_CNTX_ID",
8439   "type_ref": "CP_EOP_DONE_CNTX_ID"
8440  },
8441  {
8442   "chips": ["gfx10"],
8443   "map": {"at": 197472, "to": "mm"},
8444   "name": "CP_DB_BASE_LO",
8445   "type_ref": "CP_DB_BASE_LO"
8446  },
8447  {
8448   "chips": ["gfx10"],
8449   "map": {"at": 197476, "to": "mm"},
8450   "name": "CP_DB_BASE_HI",
8451   "type_ref": "CP_DB_BASE_HI"
8452  },
8453  {
8454   "chips": ["gfx10"],
8455   "map": {"at": 197480, "to": "mm"},
8456   "name": "CP_DB_BUFSZ",
8457   "type_ref": "CP_DB_BUFSZ"
8458  },
8459  {
8460   "chips": ["gfx10"],
8461   "map": {"at": 197484, "to": "mm"},
8462   "name": "CP_DB_CMD_BUFSZ",
8463   "type_ref": "CP_DB_CMD_BUFSZ"
8464  },
8465  {
8466   "chips": ["gfx10"],
8467   "map": {"at": 197488, "to": "mm"},
8468   "name": "CP_CE_DB_BASE_LO",
8469   "type_ref": "CP_DB_BASE_LO"
8470  },
8471  {
8472   "chips": ["gfx10"],
8473   "map": {"at": 197492, "to": "mm"},
8474   "name": "CP_CE_DB_BASE_HI",
8475   "type_ref": "CP_DB_BASE_HI"
8476  },
8477  {
8478   "chips": ["gfx10"],
8479   "map": {"at": 197496, "to": "mm"},
8480   "name": "CP_CE_DB_BUFSZ",
8481   "type_ref": "CP_DB_BUFSZ"
8482  },
8483  {
8484   "chips": ["gfx10"],
8485   "map": {"at": 197500, "to": "mm"},
8486   "name": "CP_CE_DB_CMD_BUFSZ",
8487   "type_ref": "CP_DB_CMD_BUFSZ"
8488  },
8489  {
8490   "chips": ["gfx10"],
8491   "map": {"at": 197552, "to": "mm"},
8492   "name": "CP_PFP_COMPLETION_STATUS",
8493   "type_ref": "CP_PFP_COMPLETION_STATUS"
8494  },
8495  {
8496   "chips": ["gfx10"],
8497   "map": {"at": 197556, "to": "mm"},
8498   "name": "CP_CE_COMPLETION_STATUS",
8499   "type_ref": "CP_PFP_COMPLETION_STATUS"
8500  },
8501  {
8502   "chips": ["gfx10"],
8503   "map": {"at": 197560, "to": "mm"},
8504   "name": "CP_PRED_NOT_VISIBLE",
8505   "type_ref": "CP_PRED_NOT_VISIBLE"
8506  },
8507  {
8508   "chips": ["gfx10"],
8509   "map": {"at": 197568, "to": "mm"},
8510   "name": "CP_PFP_METADATA_BASE_ADDR",
8511   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8512  },
8513  {
8514   "chips": ["gfx10"],
8515   "map": {"at": 197572, "to": "mm"},
8516   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
8517   "type_ref": "CP_EOP_DONE_ADDR_HI"
8518  },
8519  {
8520   "chips": ["gfx10"],
8521   "map": {"at": 197576, "to": "mm"},
8522   "name": "CP_CE_METADATA_BASE_ADDR",
8523   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8524  },
8525  {
8526   "chips": ["gfx10"],
8527   "map": {"at": 197580, "to": "mm"},
8528   "name": "CP_CE_METADATA_BASE_ADDR_HI",
8529   "type_ref": "CP_EOP_DONE_ADDR_HI"
8530  },
8531  {
8532   "chips": ["gfx10"],
8533   "map": {"at": 197584, "to": "mm"},
8534   "name": "CP_DRAW_INDX_INDR_ADDR",
8535   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8536  },
8537  {
8538   "chips": ["gfx10"],
8539   "map": {"at": 197588, "to": "mm"},
8540   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
8541   "type_ref": "CP_EOP_DONE_ADDR_HI"
8542  },
8543  {
8544   "chips": ["gfx10"],
8545   "map": {"at": 197592, "to": "mm"},
8546   "name": "CP_DISPATCH_INDR_ADDR",
8547   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8548  },
8549  {
8550   "chips": ["gfx10"],
8551   "map": {"at": 197596, "to": "mm"},
8552   "name": "CP_DISPATCH_INDR_ADDR_HI",
8553   "type_ref": "CP_EOP_DONE_ADDR_HI"
8554  },
8555  {
8556   "chips": ["gfx10"],
8557   "map": {"at": 197600, "to": "mm"},
8558   "name": "CP_INDEX_BASE_ADDR",
8559   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8560  },
8561  {
8562   "chips": ["gfx10"],
8563   "map": {"at": 197604, "to": "mm"},
8564   "name": "CP_INDEX_BASE_ADDR_HI",
8565   "type_ref": "CP_EOP_DONE_ADDR_HI"
8566  },
8567  {
8568   "chips": ["gfx10"],
8569   "map": {"at": 197608, "to": "mm"},
8570   "name": "CP_INDEX_TYPE",
8571   "type_ref": "CP_INDEX_TYPE"
8572  },
8573  {
8574   "chips": ["gfx10"],
8575   "map": {"at": 197612, "to": "mm"},
8576   "name": "CP_GDS_BKUP_ADDR",
8577   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
8578  },
8579  {
8580   "chips": ["gfx10"],
8581   "map": {"at": 197616, "to": "mm"},
8582   "name": "CP_GDS_BKUP_ADDR_HI",
8583   "type_ref": "CP_EOP_DONE_ADDR_HI"
8584  },
8585  {
8586   "chips": ["gfx10"],
8587   "map": {"at": 197620, "to": "mm"},
8588   "name": "CP_SAMPLE_STATUS",
8589   "type_ref": "CP_SAMPLE_STATUS"
8590  },
8591  {
8592   "chips": ["gfx10"],
8593   "map": {"at": 197624, "to": "mm"},
8594   "name": "CP_ME_COHER_CNTL",
8595   "type_ref": "CP_ME_COHER_CNTL"
8596  },
8597  {
8598   "chips": ["gfx10"],
8599   "map": {"at": 197628, "to": "mm"},
8600   "name": "CP_ME_COHER_SIZE",
8601   "type_ref": "CP_COHER_SIZE"
8602  },
8603  {
8604   "chips": ["gfx10"],
8605   "map": {"at": 197632, "to": "mm"},
8606   "name": "CP_ME_COHER_SIZE_HI",
8607   "type_ref": "CP_COHER_SIZE_HI"
8608  },
8609  {
8610   "chips": ["gfx10"],
8611   "map": {"at": 197636, "to": "mm"},
8612   "name": "CP_ME_COHER_BASE",
8613   "type_ref": "CP_COHER_BASE"
8614  },
8615  {
8616   "chips": ["gfx10"],
8617   "map": {"at": 197640, "to": "mm"},
8618   "name": "CP_ME_COHER_BASE_HI",
8619   "type_ref": "CP_COHER_BASE_HI"
8620  },
8621  {
8622   "chips": ["gfx10"],
8623   "map": {"at": 197644, "to": "mm"},
8624   "name": "CP_ME_COHER_STATUS",
8625   "type_ref": "CP_ME_COHER_STATUS"
8626  },
8627  {
8628   "chips": ["gfx10"],
8629   "map": {"at": 197888, "to": "mm"},
8630   "name": "RLC_GPM_PERF_COUNT_0",
8631   "type_ref": "RLC_GPM_PERF_COUNT_0"
8632  },
8633  {
8634   "chips": ["gfx10"],
8635   "map": {"at": 197892, "to": "mm"},
8636   "name": "RLC_GPM_PERF_COUNT_1",
8637   "type_ref": "RLC_GPM_PERF_COUNT_0"
8638  },
8639  {
8640   "chips": ["gfx10"],
8641   "map": {"at": 198656, "to": "mm"},
8642   "name": "GRBM_GFX_INDEX",
8643   "type_ref": "GRBM_GFX_INDEX"
8644  },
8645  {
8646   "chips": ["gfx10"],
8647   "map": {"at": 198912, "to": "mm"},
8648   "name": "VGT_ESGS_RING_SIZE_UMD",
8649   "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8650  },
8651  {
8652   "chips": ["gfx10"],
8653   "map": {"at": 198916, "to": "mm"},
8654   "name": "VGT_GSVS_RING_SIZE_UMD",
8655   "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8656  },
8657  {
8658   "chips": ["gfx10"],
8659   "map": {"at": 198920, "to": "mm"},
8660   "name": "VGT_PRIMITIVE_TYPE",
8661   "type_ref": "VGT_PRIMITIVE_TYPE"
8662  },
8663  {
8664   "chips": ["gfx10"],
8665   "map": {"at": 198924, "to": "mm"},
8666   "name": "VGT_INDEX_TYPE",
8667   "type_ref": "CP_INDEX_TYPE"
8668  },
8669  {
8670   "chips": ["gfx10"],
8671   "map": {"at": 198928, "to": "mm"},
8672   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0",
8673   "type_ref": "COMPUTE_DIM_X"
8674  },
8675  {
8676   "chips": ["gfx10"],
8677   "map": {"at": 198932, "to": "mm"},
8678   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1",
8679   "type_ref": "COMPUTE_DIM_X"
8680  },
8681  {
8682   "chips": ["gfx10"],
8683   "map": {"at": 198936, "to": "mm"},
8684   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2",
8685   "type_ref": "COMPUTE_DIM_X"
8686  },
8687  {
8688   "chips": ["gfx10"],
8689   "map": {"at": 198940, "to": "mm"},
8690   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3",
8691   "type_ref": "COMPUTE_DIM_X"
8692  },
8693  {
8694   "chips": ["gfx10"],
8695   "map": {"at": 198948, "to": "mm"},
8696   "name": "GE_MIN_VTX_INDX",
8697   "type_ref": "VGT_MIN_VTX_INDX"
8698  },
8699  {
8700   "chips": ["gfx10"],
8701   "map": {"at": 198952, "to": "mm"},
8702   "name": "GE_INDX_OFFSET",
8703   "type_ref": "VGT_INDX_OFFSET"
8704  },
8705  {
8706   "chips": ["gfx10"],
8707   "map": {"at": 198956, "to": "mm"},
8708   "name": "GE_MULTI_PRIM_IB_RESET_EN",
8709   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
8710  },
8711  {
8712   "chips": ["gfx10"],
8713   "map": {"at": 198960, "to": "mm"},
8714   "name": "VGT_NUM_INDICES",
8715   "type_ref": "VGT_DMA_SIZE"
8716  },
8717  {
8718   "chips": ["gfx10"],
8719   "map": {"at": 198964, "to": "mm"},
8720   "name": "VGT_NUM_INSTANCES",
8721   "type_ref": "VGT_DMA_NUM_INSTANCES"
8722  },
8723  {
8724   "chips": ["gfx10"],
8725   "map": {"at": 198968, "to": "mm"},
8726   "name": "VGT_TF_RING_SIZE_UMD",
8727   "type_ref": "VGT_TF_RING_SIZE_UMD"
8728  },
8729  {
8730   "chips": ["gfx10"],
8731   "map": {"at": 198972, "to": "mm"},
8732   "name": "VGT_HS_OFFCHIP_PARAM_UMD",
8733   "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
8734  },
8735  {
8736   "chips": ["gfx10"],
8737   "map": {"at": 198976, "to": "mm"},
8738   "name": "VGT_TF_MEMORY_BASE_UMD",
8739   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8740  },
8741  {
8742   "chips": ["gfx10"],
8743   "map": {"at": 198980, "to": "mm"},
8744   "name": "GE_DMA_FIRST_INDEX",
8745   "type_ref": "GE_DMA_FIRST_INDEX"
8746  },
8747  {
8748   "chips": ["gfx10"],
8749   "map": {"at": 198984, "to": "mm"},
8750   "name": "WD_POS_BUF_BASE",
8751   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8752  },
8753  {
8754   "chips": ["gfx10"],
8755   "map": {"at": 198988, "to": "mm"},
8756   "name": "WD_POS_BUF_BASE_HI",
8757   "type_ref": "DB_Z_READ_BASE_HI"
8758  },
8759  {
8760   "chips": ["gfx10"],
8761   "map": {"at": 198992, "to": "mm"},
8762   "name": "WD_CNTL_SB_BUF_BASE",
8763   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8764  },
8765  {
8766   "chips": ["gfx10"],
8767   "map": {"at": 198996, "to": "mm"},
8768   "name": "WD_CNTL_SB_BUF_BASE_HI",
8769   "type_ref": "DB_Z_READ_BASE_HI"
8770  },
8771  {
8772   "chips": ["gfx10"],
8773   "map": {"at": 199000, "to": "mm"},
8774   "name": "WD_INDEX_BUF_BASE",
8775   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8776  },
8777  {
8778   "chips": ["gfx10"],
8779   "map": {"at": 199004, "to": "mm"},
8780   "name": "WD_INDEX_BUF_BASE_HI",
8781   "type_ref": "DB_Z_READ_BASE_HI"
8782  },
8783  {
8784   "chips": ["gfx10"],
8785   "map": {"at": 199008, "to": "mm"},
8786   "name": "IA_MULTI_VGT_PARAM_PIPED",
8787   "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
8788  },
8789  {
8790   "chips": ["gfx10"],
8791   "map": {"at": 199012, "to": "mm"},
8792   "name": "GE_MAX_VTX_INDX",
8793   "type_ref": "VGT_MAX_VTX_INDX"
8794  },
8795  {
8796   "chips": ["gfx10"],
8797   "map": {"at": 199016, "to": "mm"},
8798   "name": "VGT_INSTANCE_BASE_ID",
8799   "type_ref": "VGT_INSTANCE_BASE_ID"
8800  },
8801  {
8802   "chips": ["gfx10"],
8803   "map": {"at": 199020, "to": "mm"},
8804   "name": "GE_CNTL",
8805   "type_ref": "GE_CNTL"
8806  },
8807  {
8808   "chips": ["gfx10"],
8809   "map": {"at": 199024, "to": "mm"},
8810   "name": "GE_USER_VGPR1",
8811   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8812  },
8813  {
8814   "chips": ["gfx10"],
8815   "map": {"at": 199028, "to": "mm"},
8816   "name": "GE_USER_VGPR2",
8817   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8818  },
8819  {
8820   "chips": ["gfx10"],
8821   "map": {"at": 199032, "to": "mm"},
8822   "name": "GE_USER_VGPR3",
8823   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8824  },
8825  {
8826   "chips": ["gfx10"],
8827   "map": {"at": 199036, "to": "mm"},
8828   "name": "GE_STEREO_CNTL",
8829   "type_ref": "GE_STEREO_CNTL"
8830  },
8831  {
8832   "chips": ["gfx10"],
8833   "map": {"at": 199040, "to": "mm"},
8834   "name": "GE_PC_ALLOC",
8835   "type_ref": "GE_PC_ALLOC"
8836  },
8837  {
8838   "chips": ["gfx10"],
8839   "map": {"at": 199044, "to": "mm"},
8840   "name": "VGT_TF_MEMORY_BASE_HI_UMD",
8841   "type_ref": "DB_Z_READ_BASE_HI"
8842  },
8843  {
8844   "chips": ["gfx10"],
8845   "map": {"at": 199048, "to": "mm"},
8846   "name": "GE_USER_VGPR_EN",
8847   "type_ref": "GE_USER_VGPR_EN"
8848  },
8849  {
8850   "chips": ["gfx10"],
8851   "map": {"at": 199168, "to": "mm"},
8852   "name": "PA_SU_LINE_STIPPLE_VALUE",
8853   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
8854  },
8855  {
8856   "chips": ["gfx10"],
8857   "map": {"at": 199172, "to": "mm"},
8858   "name": "PA_SC_LINE_STIPPLE_STATE",
8859   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
8860  },
8861  {
8862   "chips": ["gfx10"],
8863   "map": {"at": 199184, "to": "mm"},
8864   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
8865   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8866  },
8867  {
8868   "chips": ["gfx10"],
8869   "map": {"at": 199188, "to": "mm"},
8870   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
8871   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8872  },
8873  {
8874   "chips": ["gfx10"],
8875   "map": {"at": 199192, "to": "mm"},
8876   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
8877   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8878  },
8879  {
8880   "chips": ["gfx10"],
8881   "map": {"at": 199212, "to": "mm"},
8882   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
8883   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8884  },
8885  {
8886   "chips": ["gfx10"],
8887   "map": {"at": 199296, "to": "mm"},
8888   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
8889   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8890  },
8891  {
8892   "chips": ["gfx10"],
8893   "map": {"at": 199300, "to": "mm"},
8894   "name": "PA_SC_P3D_TRAP_SCREEN_H",
8895   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8896  },
8897  {
8898   "chips": ["gfx10"],
8899   "map": {"at": 199304, "to": "mm"},
8900   "name": "PA_SC_P3D_TRAP_SCREEN_V",
8901   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8902  },
8903  {
8904   "chips": ["gfx10"],
8905   "map": {"at": 199308, "to": "mm"},
8906   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
8907   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8908  },
8909  {
8910   "chips": ["gfx10"],
8911   "map": {"at": 199312, "to": "mm"},
8912   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
8913   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8914  },
8915  {
8916   "chips": ["gfx10"],
8917   "map": {"at": 199328, "to": "mm"},
8918   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
8919   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8920  },
8921  {
8922   "chips": ["gfx10"],
8923   "map": {"at": 199332, "to": "mm"},
8924   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
8925   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8926  },
8927  {
8928   "chips": ["gfx10"],
8929   "map": {"at": 199336, "to": "mm"},
8930   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
8931   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8932  },
8933  {
8934   "chips": ["gfx10"],
8935   "map": {"at": 199340, "to": "mm"},
8936   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
8937   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8938  },
8939  {
8940   "chips": ["gfx10"],
8941   "map": {"at": 199344, "to": "mm"},
8942   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
8943   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8944  },
8945  {
8946   "chips": ["gfx10"],
8947   "map": {"at": 199360, "to": "mm"},
8948   "name": "PA_SC_TRAP_SCREEN_HV_EN",
8949   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8950  },
8951  {
8952   "chips": ["gfx10"],
8953   "map": {"at": 199364, "to": "mm"},
8954   "name": "PA_SC_TRAP_SCREEN_H",
8955   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8956  },
8957  {
8958   "chips": ["gfx10"],
8959   "map": {"at": 199368, "to": "mm"},
8960   "name": "PA_SC_TRAP_SCREEN_V",
8961   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8962  },
8963  {
8964   "chips": ["gfx10"],
8965   "map": {"at": 199372, "to": "mm"},
8966   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
8967   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8968  },
8969  {
8970   "chips": ["gfx10"],
8971   "map": {"at": 199376, "to": "mm"},
8972   "name": "PA_SC_TRAP_SCREEN_COUNT",
8973   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8974  },
8975  {
8976   "chips": ["gfx10"],
8977   "map": {"at": 199936, "to": "mm"},
8978   "name": "SQ_THREAD_TRACE_USERDATA_0",
8979   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8980  },
8981  {
8982   "chips": ["gfx10"],
8983   "map": {"at": 199940, "to": "mm"},
8984   "name": "SQ_THREAD_TRACE_USERDATA_1",
8985   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8986  },
8987  {
8988   "chips": ["gfx10"],
8989   "map": {"at": 199944, "to": "mm"},
8990   "name": "SQ_THREAD_TRACE_USERDATA_2",
8991   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8992  },
8993  {
8994   "chips": ["gfx10"],
8995   "map": {"at": 199948, "to": "mm"},
8996   "name": "SQ_THREAD_TRACE_USERDATA_3",
8997   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8998  },
8999  {
9000   "chips": ["gfx10"],
9001   "map": {"at": 199952, "to": "mm"},
9002   "name": "SQ_THREAD_TRACE_USERDATA_4",
9003   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9004  },
9005  {
9006   "chips": ["gfx10"],
9007   "map": {"at": 199956, "to": "mm"},
9008   "name": "SQ_THREAD_TRACE_USERDATA_5",
9009   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9010  },
9011  {
9012   "chips": ["gfx10"],
9013   "map": {"at": 199960, "to": "mm"},
9014   "name": "SQ_THREAD_TRACE_USERDATA_6",
9015   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9016  },
9017  {
9018   "chips": ["gfx10"],
9019   "map": {"at": 199964, "to": "mm"},
9020   "name": "SQ_THREAD_TRACE_USERDATA_7",
9021   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9022  },
9023  {
9024   "chips": ["gfx10"],
9025   "map": {"at": 199968, "to": "mm"},
9026   "name": "SQC_CACHES",
9027   "type_ref": "SQC_CACHES"
9028  },
9029  {
9030   "chips": ["gfx10"],
9031   "map": {"at": 199972, "to": "mm"},
9032   "name": "SQC_WRITEBACK",
9033   "type_ref": "SQC_WRITEBACK"
9034  },
9035  {
9036   "chips": ["gfx10"],
9037   "map": {"at": 200192, "to": "mm"},
9038   "name": "TA_CS_BC_BASE_ADDR",
9039   "type_ref": "TA_BC_BASE_ADDR"
9040  },
9041  {
9042   "chips": ["gfx10"],
9043   "map": {"at": 200196, "to": "mm"},
9044   "name": "TA_CS_BC_BASE_ADDR_HI",
9045   "type_ref": "TA_BC_BASE_ADDR_HI"
9046  },
9047  {
9048   "chips": ["gfx10"],
9049   "map": {"at": 200448, "to": "mm"},
9050   "name": "DB_OCCLUSION_COUNT0_LOW",
9051   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9052  },
9053  {
9054   "chips": ["gfx10"],
9055   "map": {"at": 200452, "to": "mm"},
9056   "name": "DB_OCCLUSION_COUNT0_HI",
9057   "type_ref": "DB_OCCLUSION_COUNT0_HI"
9058  },
9059  {
9060   "chips": ["gfx10"],
9061   "map": {"at": 200456, "to": "mm"},
9062   "name": "DB_OCCLUSION_COUNT1_LOW",
9063   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9064  },
9065  {
9066   "chips": ["gfx10"],
9067   "map": {"at": 200460, "to": "mm"},
9068   "name": "DB_OCCLUSION_COUNT1_HI",
9069   "type_ref": "DB_OCCLUSION_COUNT0_HI"
9070  },
9071  {
9072   "chips": ["gfx10"],
9073   "map": {"at": 200464, "to": "mm"},
9074   "name": "DB_OCCLUSION_COUNT2_LOW",
9075   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9076  },
9077  {
9078   "chips": ["gfx10"],
9079   "map": {"at": 200468, "to": "mm"},
9080   "name": "DB_OCCLUSION_COUNT2_HI",
9081   "type_ref": "DB_OCCLUSION_COUNT0_HI"
9082  },
9083  {
9084   "chips": ["gfx10"],
9085   "map": {"at": 200472, "to": "mm"},
9086   "name": "DB_OCCLUSION_COUNT3_LOW",
9087   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9088  },
9089  {
9090   "chips": ["gfx10"],
9091   "map": {"at": 200476, "to": "mm"},
9092   "name": "DB_OCCLUSION_COUNT3_HI",
9093   "type_ref": "DB_OCCLUSION_COUNT0_HI"
9094  },
9095  {
9096   "chips": ["gfx10"],
9097   "map": {"at": 200696, "to": "mm"},
9098   "name": "DB_ZPASS_COUNT_LOW",
9099   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
9100  },
9101  {
9102   "chips": ["gfx10"],
9103   "map": {"at": 200700, "to": "mm"},
9104   "name": "DB_ZPASS_COUNT_HI",
9105   "type_ref": "DB_OCCLUSION_COUNT0_HI"
9106  },
9107  {
9108   "chips": ["gfx10"],
9109   "map": {"at": 200704, "to": "mm"},
9110   "name": "GDS_RD_ADDR",
9111   "type_ref": "GDS_RD_ADDR"
9112  },
9113  {
9114   "chips": ["gfx10"],
9115   "map": {"at": 200708, "to": "mm"},
9116   "name": "GDS_RD_DATA",
9117   "type_ref": "GDS_RD_DATA"
9118  },
9119  {
9120   "chips": ["gfx10"],
9121   "map": {"at": 200712, "to": "mm"},
9122   "name": "GDS_RD_BURST_ADDR",
9123   "type_ref": "GDS_RD_BURST_ADDR"
9124  },
9125  {
9126   "chips": ["gfx10"],
9127   "map": {"at": 200716, "to": "mm"},
9128   "name": "GDS_RD_BURST_COUNT",
9129   "type_ref": "GDS_RD_BURST_COUNT"
9130  },
9131  {
9132   "chips": ["gfx10"],
9133   "map": {"at": 200720, "to": "mm"},
9134   "name": "GDS_RD_BURST_DATA",
9135   "type_ref": "GDS_RD_BURST_DATA"
9136  },
9137  {
9138   "chips": ["gfx10"],
9139   "map": {"at": 200724, "to": "mm"},
9140   "name": "GDS_WR_ADDR",
9141   "type_ref": "GDS_WR_ADDR"
9142  },
9143  {
9144   "chips": ["gfx10"],
9145   "map": {"at": 200728, "to": "mm"},
9146   "name": "GDS_WR_DATA",
9147   "type_ref": "GDS_WR_DATA"
9148  },
9149  {
9150   "chips": ["gfx10"],
9151   "map": {"at": 200732, "to": "mm"},
9152   "name": "GDS_WR_BURST_ADDR",
9153   "type_ref": "GDS_WR_ADDR"
9154  },
9155  {
9156   "chips": ["gfx10"],
9157   "map": {"at": 200736, "to": "mm"},
9158   "name": "GDS_WR_BURST_DATA",
9159   "type_ref": "GDS_WR_DATA"
9160  },
9161  {
9162   "chips": ["gfx10"],
9163   "map": {"at": 200740, "to": "mm"},
9164   "name": "GDS_WRITE_COMPLETE",
9165   "type_ref": "GDS_WRITE_COMPLETE"
9166  },
9167  {
9168   "chips": ["gfx10"],
9169   "map": {"at": 200744, "to": "mm"},
9170   "name": "GDS_ATOM_CNTL",
9171   "type_ref": "GDS_ATOM_CNTL"
9172  },
9173  {
9174   "chips": ["gfx10"],
9175   "map": {"at": 200748, "to": "mm"},
9176   "name": "GDS_ATOM_COMPLETE",
9177   "type_ref": "GDS_ATOM_COMPLETE"
9178  },
9179  {
9180   "chips": ["gfx10"],
9181   "map": {"at": 200752, "to": "mm"},
9182   "name": "GDS_ATOM_BASE",
9183   "type_ref": "GDS_ATOM_BASE"
9184  },
9185  {
9186   "chips": ["gfx10"],
9187   "map": {"at": 200756, "to": "mm"},
9188   "name": "GDS_ATOM_SIZE",
9189   "type_ref": "GDS_ATOM_SIZE"
9190  },
9191  {
9192   "chips": ["gfx10"],
9193   "map": {"at": 200760, "to": "mm"},
9194   "name": "GDS_ATOM_OFFSET0",
9195   "type_ref": "GDS_ATOM_OFFSET0"
9196  },
9197  {
9198   "chips": ["gfx10"],
9199   "map": {"at": 200764, "to": "mm"},
9200   "name": "GDS_ATOM_OFFSET1",
9201   "type_ref": "GDS_ATOM_OFFSET1"
9202  },
9203  {
9204   "chips": ["gfx10"],
9205   "map": {"at": 200768, "to": "mm"},
9206   "name": "GDS_ATOM_DST",
9207   "type_ref": "GDS_ATOM_DST"
9208  },
9209  {
9210   "chips": ["gfx10"],
9211   "map": {"at": 200772, "to": "mm"},
9212   "name": "GDS_ATOM_OP",
9213   "type_ref": "GDS_ATOM_OP"
9214  },
9215  {
9216   "chips": ["gfx10"],
9217   "map": {"at": 200776, "to": "mm"},
9218   "name": "GDS_ATOM_SRC0",
9219   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9220  },
9221  {
9222   "chips": ["gfx10"],
9223   "map": {"at": 200780, "to": "mm"},
9224   "name": "GDS_ATOM_SRC0_U",
9225   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9226  },
9227  {
9228   "chips": ["gfx10"],
9229   "map": {"at": 200784, "to": "mm"},
9230   "name": "GDS_ATOM_SRC1",
9231   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9232  },
9233  {
9234   "chips": ["gfx10"],
9235   "map": {"at": 200788, "to": "mm"},
9236   "name": "GDS_ATOM_SRC1_U",
9237   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9238  },
9239  {
9240   "chips": ["gfx10"],
9241   "map": {"at": 200792, "to": "mm"},
9242   "name": "GDS_ATOM_READ0",
9243   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9244  },
9245  {
9246   "chips": ["gfx10"],
9247   "map": {"at": 200796, "to": "mm"},
9248   "name": "GDS_ATOM_READ0_U",
9249   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9250  },
9251  {
9252   "chips": ["gfx10"],
9253   "map": {"at": 200800, "to": "mm"},
9254   "name": "GDS_ATOM_READ1",
9255   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9256  },
9257  {
9258   "chips": ["gfx10"],
9259   "map": {"at": 200804, "to": "mm"},
9260   "name": "GDS_ATOM_READ1_U",
9261   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9262  },
9263  {
9264   "chips": ["gfx10"],
9265   "map": {"at": 200808, "to": "mm"},
9266   "name": "GDS_GWS_RESOURCE_CNTL",
9267   "type_ref": "GDS_GWS_RESOURCE_CNTL"
9268  },
9269  {
9270   "chips": ["gfx10"],
9271   "map": {"at": 200812, "to": "mm"},
9272   "name": "GDS_GWS_RESOURCE",
9273   "type_ref": "GDS_GWS_RESOURCE"
9274  },
9275  {
9276   "chips": ["gfx10"],
9277   "map": {"at": 200816, "to": "mm"},
9278   "name": "GDS_GWS_RESOURCE_CNT",
9279   "type_ref": "GDS_GWS_RESOURCE_CNT"
9280  },
9281  {
9282   "chips": ["gfx10"],
9283   "map": {"at": 200820, "to": "mm"},
9284   "name": "GDS_OA_CNTL",
9285   "type_ref": "GDS_OA_CNTL"
9286  },
9287  {
9288   "chips": ["gfx10"],
9289   "map": {"at": 200824, "to": "mm"},
9290   "name": "GDS_OA_COUNTER",
9291   "type_ref": "GDS_OA_COUNTER"
9292  },
9293  {
9294   "chips": ["gfx10"],
9295   "map": {"at": 200828, "to": "mm"},
9296   "name": "GDS_OA_ADDRESS",
9297   "type_ref": "GDS_OA_ADDRESS"
9298  },
9299  {
9300   "chips": ["gfx10"],
9301   "map": {"at": 200832, "to": "mm"},
9302   "name": "GDS_OA_INCDEC",
9303   "type_ref": "GDS_OA_INCDEC"
9304  },
9305  {
9306   "chips": ["gfx10"],
9307   "map": {"at": 200836, "to": "mm"},
9308   "name": "GDS_OA_RING_SIZE",
9309   "type_ref": "GDS_OA_RING_SIZE"
9310  },
9311  {
9312   "chips": ["gfx10"],
9313   "map": {"at": 200960, "to": "mm"},
9314   "name": "SPI_CONFIG_CNTL_REMAP",
9315   "type_ref": "SPI_CONFIG_CNTL_REMAP"
9316  },
9317  {
9318   "chips": ["gfx10"],
9319   "map": {"at": 200964, "to": "mm"},
9320   "name": "SPI_CONFIG_CNTL_1_REMAP",
9321   "type_ref": "SPI_CONFIG_CNTL_REMAP"
9322  },
9323  {
9324   "chips": ["gfx10"],
9325   "map": {"at": 200968, "to": "mm"},
9326   "name": "SPI_CONFIG_CNTL_2_REMAP",
9327   "type_ref": "SPI_CONFIG_CNTL_REMAP"
9328  },
9329  {
9330   "chips": ["gfx10"],
9331   "map": {"at": 200972, "to": "mm"},
9332   "name": "SPI_WAVE_LIMIT_CNTL_REMAP",
9333   "type_ref": "SPI_CONFIG_CNTL_REMAP"
9334  },
9335  {
9336   "chips": ["gfx10"],
9337   "map": {"at": 212992, "to": "mm"},
9338   "name": "CPG_PERFCOUNTER1_LO",
9339   "type_ref": "CPG_PERFCOUNTER1_LO"
9340  },
9341  {
9342   "chips": ["gfx10"],
9343   "map": {"at": 212996, "to": "mm"},
9344   "name": "CPG_PERFCOUNTER1_HI",
9345   "type_ref": "CPG_PERFCOUNTER1_HI"
9346  },
9347  {
9348   "chips": ["gfx10"],
9349   "map": {"at": 213000, "to": "mm"},
9350   "name": "CPG_PERFCOUNTER0_LO",
9351   "type_ref": "CPG_PERFCOUNTER1_LO"
9352  },
9353  {
9354   "chips": ["gfx10"],
9355   "map": {"at": 213004, "to": "mm"},
9356   "name": "CPG_PERFCOUNTER0_HI",
9357   "type_ref": "CPG_PERFCOUNTER1_HI"
9358  },
9359  {
9360   "chips": ["gfx10"],
9361   "map": {"at": 213008, "to": "mm"},
9362   "name": "CPC_PERFCOUNTER1_LO",
9363   "type_ref": "CPG_PERFCOUNTER1_LO"
9364  },
9365  {
9366   "chips": ["gfx10"],
9367   "map": {"at": 213012, "to": "mm"},
9368   "name": "CPC_PERFCOUNTER1_HI",
9369   "type_ref": "CPG_PERFCOUNTER1_HI"
9370  },
9371  {
9372   "chips": ["gfx10"],
9373   "map": {"at": 213016, "to": "mm"},
9374   "name": "CPC_PERFCOUNTER0_LO",
9375   "type_ref": "CPG_PERFCOUNTER1_LO"
9376  },
9377  {
9378   "chips": ["gfx10"],
9379   "map": {"at": 213020, "to": "mm"},
9380   "name": "CPC_PERFCOUNTER0_HI",
9381   "type_ref": "CPG_PERFCOUNTER1_HI"
9382  },
9383  {
9384   "chips": ["gfx10"],
9385   "map": {"at": 213024, "to": "mm"},
9386   "name": "CPF_PERFCOUNTER1_LO",
9387   "type_ref": "CPG_PERFCOUNTER1_LO"
9388  },
9389  {
9390   "chips": ["gfx10"],
9391   "map": {"at": 213028, "to": "mm"},
9392   "name": "CPF_PERFCOUNTER1_HI",
9393   "type_ref": "CPG_PERFCOUNTER1_HI"
9394  },
9395  {
9396   "chips": ["gfx10"],
9397   "map": {"at": 213032, "to": "mm"},
9398   "name": "CPF_PERFCOUNTER0_LO",
9399   "type_ref": "CPG_PERFCOUNTER1_LO"
9400  },
9401  {
9402   "chips": ["gfx10"],
9403   "map": {"at": 213036, "to": "mm"},
9404   "name": "CPF_PERFCOUNTER0_HI",
9405   "type_ref": "CPG_PERFCOUNTER1_HI"
9406  },
9407  {
9408   "chips": ["gfx10"],
9409   "map": {"at": 213040, "to": "mm"},
9410   "name": "CPF_LATENCY_STATS_DATA",
9411   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9412  },
9413  {
9414   "chips": ["gfx10"],
9415   "map": {"at": 213044, "to": "mm"},
9416   "name": "CPG_LATENCY_STATS_DATA",
9417   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9418  },
9419  {
9420   "chips": ["gfx10"],
9421   "map": {"at": 213048, "to": "mm"},
9422   "name": "CPC_LATENCY_STATS_DATA",
9423   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
9424  },
9425  {
9426   "chips": ["gfx10"],
9427   "map": {"at": 213248, "to": "mm"},
9428   "name": "GRBM_PERFCOUNTER0_LO",
9429   "type_ref": "CPG_PERFCOUNTER1_LO"
9430  },
9431  {
9432   "chips": ["gfx10"],
9433   "map": {"at": 213252, "to": "mm"},
9434   "name": "GRBM_PERFCOUNTER0_HI",
9435   "type_ref": "CPG_PERFCOUNTER1_HI"
9436  },
9437  {
9438   "chips": ["gfx10"],
9439   "map": {"at": 213260, "to": "mm"},
9440   "name": "GRBM_PERFCOUNTER1_LO",
9441   "type_ref": "CPG_PERFCOUNTER1_LO"
9442  },
9443  {
9444   "chips": ["gfx10"],
9445   "map": {"at": 213264, "to": "mm"},
9446   "name": "GRBM_PERFCOUNTER1_HI",
9447   "type_ref": "CPG_PERFCOUNTER1_HI"
9448  },
9449  {
9450   "chips": ["gfx10"],
9451   "map": {"at": 213268, "to": "mm"},
9452   "name": "GRBM_SE0_PERFCOUNTER_LO",
9453   "type_ref": "CPG_PERFCOUNTER1_LO"
9454  },
9455  {
9456   "chips": ["gfx10"],
9457   "map": {"at": 213272, "to": "mm"},
9458   "name": "GRBM_SE0_PERFCOUNTER_HI",
9459   "type_ref": "CPG_PERFCOUNTER1_HI"
9460  },
9461  {
9462   "chips": ["gfx10"],
9463   "map": {"at": 213276, "to": "mm"},
9464   "name": "GRBM_SE1_PERFCOUNTER_LO",
9465   "type_ref": "CPG_PERFCOUNTER1_LO"
9466  },
9467  {
9468   "chips": ["gfx10"],
9469   "map": {"at": 213280, "to": "mm"},
9470   "name": "GRBM_SE1_PERFCOUNTER_HI",
9471   "type_ref": "CPG_PERFCOUNTER1_HI"
9472  },
9473  {
9474   "chips": ["gfx10"],
9475   "map": {"at": 213284, "to": "mm"},
9476   "name": "GRBM_SE2_PERFCOUNTER_LO",
9477   "type_ref": "CPG_PERFCOUNTER1_LO"
9478  },
9479  {
9480   "chips": ["gfx10"],
9481   "map": {"at": 213288, "to": "mm"},
9482   "name": "GRBM_SE2_PERFCOUNTER_HI",
9483   "type_ref": "CPG_PERFCOUNTER1_HI"
9484  },
9485  {
9486   "chips": ["gfx10"],
9487   "map": {"at": 213292, "to": "mm"},
9488   "name": "GRBM_SE3_PERFCOUNTER_LO",
9489   "type_ref": "CPG_PERFCOUNTER1_LO"
9490  },
9491  {
9492   "chips": ["gfx10"],
9493   "map": {"at": 213296, "to": "mm"},
9494   "name": "GRBM_SE3_PERFCOUNTER_HI",
9495   "type_ref": "CPG_PERFCOUNTER1_HI"
9496  },
9497  {
9498   "chips": ["gfx10"],
9499   "map": {"at": 213504, "to": "mm"},
9500   "name": "GE_PERFCOUNTER0_LO",
9501   "type_ref": "CPG_PERFCOUNTER1_LO"
9502  },
9503  {
9504   "chips": ["gfx10"],
9505   "map": {"at": 213508, "to": "mm"},
9506   "name": "GE_PERFCOUNTER0_HI",
9507   "type_ref": "CPG_PERFCOUNTER1_HI"
9508  },
9509  {
9510   "chips": ["gfx10"],
9511   "map": {"at": 213512, "to": "mm"},
9512   "name": "GE_PERFCOUNTER1_LO",
9513   "type_ref": "CPG_PERFCOUNTER1_LO"
9514  },
9515  {
9516   "chips": ["gfx10"],
9517   "map": {"at": 213516, "to": "mm"},
9518   "name": "GE_PERFCOUNTER1_HI",
9519   "type_ref": "CPG_PERFCOUNTER1_HI"
9520  },
9521  {
9522   "chips": ["gfx10"],
9523   "map": {"at": 213520, "to": "mm"},
9524   "name": "GE_PERFCOUNTER2_LO",
9525   "type_ref": "CPG_PERFCOUNTER1_LO"
9526  },
9527  {
9528   "chips": ["gfx10"],
9529   "map": {"at": 213524, "to": "mm"},
9530   "name": "GE_PERFCOUNTER2_HI",
9531   "type_ref": "CPG_PERFCOUNTER1_HI"
9532  },
9533  {
9534   "chips": ["gfx10"],
9535   "map": {"at": 213528, "to": "mm"},
9536   "name": "GE_PERFCOUNTER3_LO",
9537   "type_ref": "CPG_PERFCOUNTER1_LO"
9538  },
9539  {
9540   "chips": ["gfx10"],
9541   "map": {"at": 213532, "to": "mm"},
9542   "name": "GE_PERFCOUNTER3_HI",
9543   "type_ref": "CPG_PERFCOUNTER1_HI"
9544  },
9545  {
9546   "chips": ["gfx10"],
9547   "map": {"at": 213536, "to": "mm"},
9548   "name": "GE_PERFCOUNTER4_LO",
9549   "type_ref": "CPG_PERFCOUNTER1_LO"
9550  },
9551  {
9552   "chips": ["gfx10"],
9553   "map": {"at": 213540, "to": "mm"},
9554   "name": "GE_PERFCOUNTER4_HI",
9555   "type_ref": "CPG_PERFCOUNTER1_HI"
9556  },
9557  {
9558   "chips": ["gfx10"],
9559   "map": {"at": 213544, "to": "mm"},
9560   "name": "GE_PERFCOUNTER5_LO",
9561   "type_ref": "CPG_PERFCOUNTER1_LO"
9562  },
9563  {
9564   "chips": ["gfx10"],
9565   "map": {"at": 213548, "to": "mm"},
9566   "name": "GE_PERFCOUNTER5_HI",
9567   "type_ref": "CPG_PERFCOUNTER1_HI"
9568  },
9569  {
9570   "chips": ["gfx10"],
9571   "map": {"at": 213552, "to": "mm"},
9572   "name": "GE_PERFCOUNTER6_LO",
9573   "type_ref": "CPG_PERFCOUNTER1_LO"
9574  },
9575  {
9576   "chips": ["gfx10"],
9577   "map": {"at": 213556, "to": "mm"},
9578   "name": "GE_PERFCOUNTER6_HI",
9579   "type_ref": "CPG_PERFCOUNTER1_HI"
9580  },
9581  {
9582   "chips": ["gfx10"],
9583   "map": {"at": 213560, "to": "mm"},
9584   "name": "GE_PERFCOUNTER7_LO",
9585   "type_ref": "CPG_PERFCOUNTER1_LO"
9586  },
9587  {
9588   "chips": ["gfx10"],
9589   "map": {"at": 213564, "to": "mm"},
9590   "name": "GE_PERFCOUNTER7_HI",
9591   "type_ref": "CPG_PERFCOUNTER1_HI"
9592  },
9593  {
9594   "chips": ["gfx10"],
9595   "map": {"at": 213568, "to": "mm"},
9596   "name": "GE_PERFCOUNTER8_LO",
9597   "type_ref": "CPG_PERFCOUNTER1_LO"
9598  },
9599  {
9600   "chips": ["gfx10"],
9601   "map": {"at": 213572, "to": "mm"},
9602   "name": "GE_PERFCOUNTER8_HI",
9603   "type_ref": "CPG_PERFCOUNTER1_HI"
9604  },
9605  {
9606   "chips": ["gfx10"],
9607   "map": {"at": 213576, "to": "mm"},
9608   "name": "GE_PERFCOUNTER9_LO",
9609   "type_ref": "CPG_PERFCOUNTER1_LO"
9610  },
9611  {
9612   "chips": ["gfx10"],
9613   "map": {"at": 213580, "to": "mm"},
9614   "name": "GE_PERFCOUNTER9_HI",
9615   "type_ref": "CPG_PERFCOUNTER1_HI"
9616  },
9617  {
9618   "chips": ["gfx10"],
9619   "map": {"at": 213584, "to": "mm"},
9620   "name": "GE_PERFCOUNTER10_LO",
9621   "type_ref": "CPG_PERFCOUNTER1_LO"
9622  },
9623  {
9624   "chips": ["gfx10"],
9625   "map": {"at": 213588, "to": "mm"},
9626   "name": "GE_PERFCOUNTER10_HI",
9627   "type_ref": "CPG_PERFCOUNTER1_HI"
9628  },
9629  {
9630   "chips": ["gfx10"],
9631   "map": {"at": 213592, "to": "mm"},
9632   "name": "GE_PERFCOUNTER11_LO",
9633   "type_ref": "CPG_PERFCOUNTER1_LO"
9634  },
9635  {
9636   "chips": ["gfx10"],
9637   "map": {"at": 213596, "to": "mm"},
9638   "name": "GE_PERFCOUNTER11_HI",
9639   "type_ref": "CPG_PERFCOUNTER1_HI"
9640  },
9641  {
9642   "chips": ["gfx10"],
9643   "map": {"at": 214016, "to": "mm"},
9644   "name": "PA_SU_PERFCOUNTER0_LO",
9645   "type_ref": "CPG_PERFCOUNTER1_LO"
9646  },
9647  {
9648   "chips": ["gfx10"],
9649   "map": {"at": 214020, "to": "mm"},
9650   "name": "PA_SU_PERFCOUNTER0_HI",
9651   "type_ref": "PA_SU_PERFCOUNTER0_HI"
9652  },
9653  {
9654   "chips": ["gfx10"],
9655   "map": {"at": 214024, "to": "mm"},
9656   "name": "PA_SU_PERFCOUNTER1_LO",
9657   "type_ref": "CPG_PERFCOUNTER1_LO"
9658  },
9659  {
9660   "chips": ["gfx10"],
9661   "map": {"at": 214028, "to": "mm"},
9662   "name": "PA_SU_PERFCOUNTER1_HI",
9663   "type_ref": "PA_SU_PERFCOUNTER0_HI"
9664  },
9665  {
9666   "chips": ["gfx10"],
9667   "map": {"at": 214032, "to": "mm"},
9668   "name": "PA_SU_PERFCOUNTER2_LO",
9669   "type_ref": "CPG_PERFCOUNTER1_LO"
9670  },
9671  {
9672   "chips": ["gfx10"],
9673   "map": {"at": 214036, "to": "mm"},
9674   "name": "PA_SU_PERFCOUNTER2_HI",
9675   "type_ref": "PA_SU_PERFCOUNTER0_HI"
9676  },
9677  {
9678   "chips": ["gfx10"],
9679   "map": {"at": 214040, "to": "mm"},
9680   "name": "PA_SU_PERFCOUNTER3_LO",
9681   "type_ref": "CPG_PERFCOUNTER1_LO"
9682  },
9683  {
9684   "chips": ["gfx10"],
9685   "map": {"at": 214044, "to": "mm"},
9686   "name": "PA_SU_PERFCOUNTER3_HI",
9687   "type_ref": "PA_SU_PERFCOUNTER0_HI"
9688  },
9689  {
9690   "chips": ["gfx10"],
9691   "map": {"at": 214272, "to": "mm"},
9692   "name": "PA_SC_PERFCOUNTER0_LO",
9693   "type_ref": "CPG_PERFCOUNTER1_LO"
9694  },
9695  {
9696   "chips": ["gfx10"],
9697   "map": {"at": 214276, "to": "mm"},
9698   "name": "PA_SC_PERFCOUNTER0_HI",
9699   "type_ref": "CPG_PERFCOUNTER1_HI"
9700  },
9701  {
9702   "chips": ["gfx10"],
9703   "map": {"at": 214280, "to": "mm"},
9704   "name": "PA_SC_PERFCOUNTER1_LO",
9705   "type_ref": "CPG_PERFCOUNTER1_LO"
9706  },
9707  {
9708   "chips": ["gfx10"],
9709   "map": {"at": 214284, "to": "mm"},
9710   "name": "PA_SC_PERFCOUNTER1_HI",
9711   "type_ref": "CPG_PERFCOUNTER1_HI"
9712  },
9713  {
9714   "chips": ["gfx10"],
9715   "map": {"at": 214288, "to": "mm"},
9716   "name": "PA_SC_PERFCOUNTER2_LO",
9717   "type_ref": "CPG_PERFCOUNTER1_LO"
9718  },
9719  {
9720   "chips": ["gfx10"],
9721   "map": {"at": 214292, "to": "mm"},
9722   "name": "PA_SC_PERFCOUNTER2_HI",
9723   "type_ref": "CPG_PERFCOUNTER1_HI"
9724  },
9725  {
9726   "chips": ["gfx10"],
9727   "map": {"at": 214296, "to": "mm"},
9728   "name": "PA_SC_PERFCOUNTER3_LO",
9729   "type_ref": "CPG_PERFCOUNTER1_LO"
9730  },
9731  {
9732   "chips": ["gfx10"],
9733   "map": {"at": 214300, "to": "mm"},
9734   "name": "PA_SC_PERFCOUNTER3_HI",
9735   "type_ref": "CPG_PERFCOUNTER1_HI"
9736  },
9737  {
9738   "chips": ["gfx10"],
9739   "map": {"at": 214304, "to": "mm"},
9740   "name": "PA_SC_PERFCOUNTER4_LO",
9741   "type_ref": "CPG_PERFCOUNTER1_LO"
9742  },
9743  {
9744   "chips": ["gfx10"],
9745   "map": {"at": 214308, "to": "mm"},
9746   "name": "PA_SC_PERFCOUNTER4_HI",
9747   "type_ref": "CPG_PERFCOUNTER1_HI"
9748  },
9749  {
9750   "chips": ["gfx10"],
9751   "map": {"at": 214312, "to": "mm"},
9752   "name": "PA_SC_PERFCOUNTER5_LO",
9753   "type_ref": "CPG_PERFCOUNTER1_LO"
9754  },
9755  {
9756   "chips": ["gfx10"],
9757   "map": {"at": 214316, "to": "mm"},
9758   "name": "PA_SC_PERFCOUNTER5_HI",
9759   "type_ref": "CPG_PERFCOUNTER1_HI"
9760  },
9761  {
9762   "chips": ["gfx10"],
9763   "map": {"at": 214320, "to": "mm"},
9764   "name": "PA_SC_PERFCOUNTER6_LO",
9765   "type_ref": "CPG_PERFCOUNTER1_LO"
9766  },
9767  {
9768   "chips": ["gfx10"],
9769   "map": {"at": 214324, "to": "mm"},
9770   "name": "PA_SC_PERFCOUNTER6_HI",
9771   "type_ref": "CPG_PERFCOUNTER1_HI"
9772  },
9773  {
9774   "chips": ["gfx10"],
9775   "map": {"at": 214328, "to": "mm"},
9776   "name": "PA_SC_PERFCOUNTER7_LO",
9777   "type_ref": "CPG_PERFCOUNTER1_LO"
9778  },
9779  {
9780   "chips": ["gfx10"],
9781   "map": {"at": 214332, "to": "mm"},
9782   "name": "PA_SC_PERFCOUNTER7_HI",
9783   "type_ref": "CPG_PERFCOUNTER1_HI"
9784  },
9785  {
9786   "chips": ["gfx10"],
9787   "map": {"at": 214528, "to": "mm"},
9788   "name": "SPI_PERFCOUNTER0_HI",
9789   "type_ref": "CPG_PERFCOUNTER1_HI"
9790  },
9791  {
9792   "chips": ["gfx10"],
9793   "map": {"at": 214532, "to": "mm"},
9794   "name": "SPI_PERFCOUNTER0_LO",
9795   "type_ref": "CPG_PERFCOUNTER1_LO"
9796  },
9797  {
9798   "chips": ["gfx10"],
9799   "map": {"at": 214536, "to": "mm"},
9800   "name": "SPI_PERFCOUNTER1_HI",
9801   "type_ref": "CPG_PERFCOUNTER1_HI"
9802  },
9803  {
9804   "chips": ["gfx10"],
9805   "map": {"at": 214540, "to": "mm"},
9806   "name": "SPI_PERFCOUNTER1_LO",
9807   "type_ref": "CPG_PERFCOUNTER1_LO"
9808  },
9809  {
9810   "chips": ["gfx10"],
9811   "map": {"at": 214544, "to": "mm"},
9812   "name": "SPI_PERFCOUNTER2_HI",
9813   "type_ref": "CPG_PERFCOUNTER1_HI"
9814  },
9815  {
9816   "chips": ["gfx10"],
9817   "map": {"at": 214548, "to": "mm"},
9818   "name": "SPI_PERFCOUNTER2_LO",
9819   "type_ref": "CPG_PERFCOUNTER1_LO"
9820  },
9821  {
9822   "chips": ["gfx10"],
9823   "map": {"at": 214552, "to": "mm"},
9824   "name": "SPI_PERFCOUNTER3_HI",
9825   "type_ref": "CPG_PERFCOUNTER1_HI"
9826  },
9827  {
9828   "chips": ["gfx10"],
9829   "map": {"at": 214556, "to": "mm"},
9830   "name": "SPI_PERFCOUNTER3_LO",
9831   "type_ref": "CPG_PERFCOUNTER1_LO"
9832  },
9833  {
9834   "chips": ["gfx10"],
9835   "map": {"at": 214560, "to": "mm"},
9836   "name": "SPI_PERFCOUNTER4_HI",
9837   "type_ref": "CPG_PERFCOUNTER1_HI"
9838  },
9839  {
9840   "chips": ["gfx10"],
9841   "map": {"at": 214564, "to": "mm"},
9842   "name": "SPI_PERFCOUNTER4_LO",
9843   "type_ref": "CPG_PERFCOUNTER1_LO"
9844  },
9845  {
9846   "chips": ["gfx10"],
9847   "map": {"at": 214568, "to": "mm"},
9848   "name": "SPI_PERFCOUNTER5_HI",
9849   "type_ref": "CPG_PERFCOUNTER1_HI"
9850  },
9851  {
9852   "chips": ["gfx10"],
9853   "map": {"at": 214572, "to": "mm"},
9854   "name": "SPI_PERFCOUNTER5_LO",
9855   "type_ref": "CPG_PERFCOUNTER1_LO"
9856  },
9857  {
9858   "chips": ["gfx10"],
9859   "map": {"at": 214784, "to": "mm"},
9860   "name": "SQ_PERFCOUNTER0_LO",
9861   "type_ref": "CPG_PERFCOUNTER1_LO"
9862  },
9863  {
9864   "chips": ["gfx10"],
9865   "map": {"at": 214788, "to": "mm"},
9866   "name": "SQ_PERFCOUNTER0_HI",
9867   "type_ref": "CPG_PERFCOUNTER1_HI"
9868  },
9869  {
9870   "chips": ["gfx10"],
9871   "map": {"at": 214792, "to": "mm"},
9872   "name": "SQ_PERFCOUNTER1_LO",
9873   "type_ref": "CPG_PERFCOUNTER1_LO"
9874  },
9875  {
9876   "chips": ["gfx10"],
9877   "map": {"at": 214796, "to": "mm"},
9878   "name": "SQ_PERFCOUNTER1_HI",
9879   "type_ref": "CPG_PERFCOUNTER1_HI"
9880  },
9881  {
9882   "chips": ["gfx10"],
9883   "map": {"at": 214800, "to": "mm"},
9884   "name": "SQ_PERFCOUNTER2_LO",
9885   "type_ref": "CPG_PERFCOUNTER1_LO"
9886  },
9887  {
9888   "chips": ["gfx10"],
9889   "map": {"at": 214804, "to": "mm"},
9890   "name": "SQ_PERFCOUNTER2_HI",
9891   "type_ref": "CPG_PERFCOUNTER1_HI"
9892  },
9893  {
9894   "chips": ["gfx10"],
9895   "map": {"at": 214808, "to": "mm"},
9896   "name": "SQ_PERFCOUNTER3_LO",
9897   "type_ref": "CPG_PERFCOUNTER1_LO"
9898  },
9899  {
9900   "chips": ["gfx10"],
9901   "map": {"at": 214812, "to": "mm"},
9902   "name": "SQ_PERFCOUNTER3_HI",
9903   "type_ref": "CPG_PERFCOUNTER1_HI"
9904  },
9905  {
9906   "chips": ["gfx10"],
9907   "map": {"at": 214816, "to": "mm"},
9908   "name": "SQ_PERFCOUNTER4_LO",
9909   "type_ref": "CPG_PERFCOUNTER1_LO"
9910  },
9911  {
9912   "chips": ["gfx10"],
9913   "map": {"at": 214820, "to": "mm"},
9914   "name": "SQ_PERFCOUNTER4_HI",
9915   "type_ref": "CPG_PERFCOUNTER1_HI"
9916  },
9917  {
9918   "chips": ["gfx10"],
9919   "map": {"at": 214824, "to": "mm"},
9920   "name": "SQ_PERFCOUNTER5_LO",
9921   "type_ref": "CPG_PERFCOUNTER1_LO"
9922  },
9923  {
9924   "chips": ["gfx10"],
9925   "map": {"at": 214828, "to": "mm"},
9926   "name": "SQ_PERFCOUNTER5_HI",
9927   "type_ref": "CPG_PERFCOUNTER1_HI"
9928  },
9929  {
9930   "chips": ["gfx10"],
9931   "map": {"at": 214832, "to": "mm"},
9932   "name": "SQ_PERFCOUNTER6_LO",
9933   "type_ref": "CPG_PERFCOUNTER1_LO"
9934  },
9935  {
9936   "chips": ["gfx10"],
9937   "map": {"at": 214836, "to": "mm"},
9938   "name": "SQ_PERFCOUNTER6_HI",
9939   "type_ref": "CPG_PERFCOUNTER1_HI"
9940  },
9941  {
9942   "chips": ["gfx10"],
9943   "map": {"at": 214840, "to": "mm"},
9944   "name": "SQ_PERFCOUNTER7_LO",
9945   "type_ref": "CPG_PERFCOUNTER1_LO"
9946  },
9947  {
9948   "chips": ["gfx10"],
9949   "map": {"at": 214844, "to": "mm"},
9950   "name": "SQ_PERFCOUNTER7_HI",
9951   "type_ref": "CPG_PERFCOUNTER1_HI"
9952  },
9953  {
9954   "chips": ["gfx10"],
9955   "map": {"at": 214848, "to": "mm"},
9956   "name": "SQ_PERFCOUNTER8_LO",
9957   "type_ref": "CPG_PERFCOUNTER1_LO"
9958  },
9959  {
9960   "chips": ["gfx10"],
9961   "map": {"at": 214852, "to": "mm"},
9962   "name": "SQ_PERFCOUNTER8_HI",
9963   "type_ref": "CPG_PERFCOUNTER1_HI"
9964  },
9965  {
9966   "chips": ["gfx10"],
9967   "map": {"at": 214856, "to": "mm"},
9968   "name": "SQ_PERFCOUNTER9_LO",
9969   "type_ref": "CPG_PERFCOUNTER1_LO"
9970  },
9971  {
9972   "chips": ["gfx10"],
9973   "map": {"at": 214860, "to": "mm"},
9974   "name": "SQ_PERFCOUNTER9_HI",
9975   "type_ref": "CPG_PERFCOUNTER1_HI"
9976  },
9977  {
9978   "chips": ["gfx10"],
9979   "map": {"at": 214864, "to": "mm"},
9980   "name": "SQ_PERFCOUNTER10_LO",
9981   "type_ref": "CPG_PERFCOUNTER1_LO"
9982  },
9983  {
9984   "chips": ["gfx10"],
9985   "map": {"at": 214868, "to": "mm"},
9986   "name": "SQ_PERFCOUNTER10_HI",
9987   "type_ref": "CPG_PERFCOUNTER1_HI"
9988  },
9989  {
9990   "chips": ["gfx10"],
9991   "map": {"at": 214872, "to": "mm"},
9992   "name": "SQ_PERFCOUNTER11_LO",
9993   "type_ref": "CPG_PERFCOUNTER1_LO"
9994  },
9995  {
9996   "chips": ["gfx10"],
9997   "map": {"at": 214876, "to": "mm"},
9998   "name": "SQ_PERFCOUNTER11_HI",
9999   "type_ref": "CPG_PERFCOUNTER1_HI"
10000  },
10001  {
10002   "chips": ["gfx10"],
10003   "map": {"at": 214880, "to": "mm"},
10004   "name": "SQ_PERFCOUNTER12_LO",
10005   "type_ref": "CPG_PERFCOUNTER1_LO"
10006  },
10007  {
10008   "chips": ["gfx10"],
10009   "map": {"at": 214884, "to": "mm"},
10010   "name": "SQ_PERFCOUNTER12_HI",
10011   "type_ref": "CPG_PERFCOUNTER1_HI"
10012  },
10013  {
10014   "chips": ["gfx10"],
10015   "map": {"at": 214888, "to": "mm"},
10016   "name": "SQ_PERFCOUNTER13_LO",
10017   "type_ref": "CPG_PERFCOUNTER1_LO"
10018  },
10019  {
10020   "chips": ["gfx10"],
10021   "map": {"at": 214892, "to": "mm"},
10022   "name": "SQ_PERFCOUNTER13_HI",
10023   "type_ref": "CPG_PERFCOUNTER1_HI"
10024  },
10025  {
10026   "chips": ["gfx10"],
10027   "map": {"at": 214896, "to": "mm"},
10028   "name": "SQ_PERFCOUNTER14_LO",
10029   "type_ref": "CPG_PERFCOUNTER1_LO"
10030  },
10031  {
10032   "chips": ["gfx10"],
10033   "map": {"at": 214900, "to": "mm"},
10034   "name": "SQ_PERFCOUNTER14_HI",
10035   "type_ref": "CPG_PERFCOUNTER1_HI"
10036  },
10037  {
10038   "chips": ["gfx10"],
10039   "map": {"at": 214904, "to": "mm"},
10040   "name": "SQ_PERFCOUNTER15_LO",
10041   "type_ref": "CPG_PERFCOUNTER1_LO"
10042  },
10043  {
10044   "chips": ["gfx10"],
10045   "map": {"at": 214908, "to": "mm"},
10046   "name": "SQ_PERFCOUNTER15_HI",
10047   "type_ref": "CPG_PERFCOUNTER1_HI"
10048  },
10049  {
10050   "chips": ["gfx10"],
10051   "map": {"at": 215296, "to": "mm"},
10052   "name": "SX_PERFCOUNTER0_LO",
10053   "type_ref": "CPG_PERFCOUNTER1_LO"
10054  },
10055  {
10056   "chips": ["gfx10"],
10057   "map": {"at": 215300, "to": "mm"},
10058   "name": "SX_PERFCOUNTER0_HI",
10059   "type_ref": "CPG_PERFCOUNTER1_HI"
10060  },
10061  {
10062   "chips": ["gfx10"],
10063   "map": {"at": 215304, "to": "mm"},
10064   "name": "SX_PERFCOUNTER1_LO",
10065   "type_ref": "CPG_PERFCOUNTER1_LO"
10066  },
10067  {
10068   "chips": ["gfx10"],
10069   "map": {"at": 215308, "to": "mm"},
10070   "name": "SX_PERFCOUNTER1_HI",
10071   "type_ref": "CPG_PERFCOUNTER1_HI"
10072  },
10073  {
10074   "chips": ["gfx10"],
10075   "map": {"at": 215312, "to": "mm"},
10076   "name": "SX_PERFCOUNTER2_LO",
10077   "type_ref": "CPG_PERFCOUNTER1_LO"
10078  },
10079  {
10080   "chips": ["gfx10"],
10081   "map": {"at": 215316, "to": "mm"},
10082   "name": "SX_PERFCOUNTER2_HI",
10083   "type_ref": "CPG_PERFCOUNTER1_HI"
10084  },
10085  {
10086   "chips": ["gfx10"],
10087   "map": {"at": 215320, "to": "mm"},
10088   "name": "SX_PERFCOUNTER3_LO",
10089   "type_ref": "CPG_PERFCOUNTER1_LO"
10090  },
10091  {
10092   "chips": ["gfx10"],
10093   "map": {"at": 215324, "to": "mm"},
10094   "name": "SX_PERFCOUNTER3_HI",
10095   "type_ref": "CPG_PERFCOUNTER1_HI"
10096  },
10097  {
10098   "chips": ["gfx10"],
10099   "map": {"at": 215424, "to": "mm"},
10100   "name": "GCEA_PERFCOUNTER2_LO",
10101   "type_ref": "CPG_PERFCOUNTER1_LO"
10102  },
10103  {
10104   "chips": ["gfx10"],
10105   "map": {"at": 215428, "to": "mm"},
10106   "name": "GCEA_PERFCOUNTER2_HI",
10107   "type_ref": "CPG_PERFCOUNTER1_HI"
10108  },
10109  {
10110   "chips": ["gfx10"],
10111   "map": {"at": 215552, "to": "mm"},
10112   "name": "GDS_PERFCOUNTER0_LO",
10113   "type_ref": "CPG_PERFCOUNTER1_LO"
10114  },
10115  {
10116   "chips": ["gfx10"],
10117   "map": {"at": 215556, "to": "mm"},
10118   "name": "GDS_PERFCOUNTER0_HI",
10119   "type_ref": "CPG_PERFCOUNTER1_HI"
10120  },
10121  {
10122   "chips": ["gfx10"],
10123   "map": {"at": 215560, "to": "mm"},
10124   "name": "GDS_PERFCOUNTER1_LO",
10125   "type_ref": "CPG_PERFCOUNTER1_LO"
10126  },
10127  {
10128   "chips": ["gfx10"],
10129   "map": {"at": 215564, "to": "mm"},
10130   "name": "GDS_PERFCOUNTER1_HI",
10131   "type_ref": "CPG_PERFCOUNTER1_HI"
10132  },
10133  {
10134   "chips": ["gfx10"],
10135   "map": {"at": 215568, "to": "mm"},
10136   "name": "GDS_PERFCOUNTER2_LO",
10137   "type_ref": "CPG_PERFCOUNTER1_LO"
10138  },
10139  {
10140   "chips": ["gfx10"],
10141   "map": {"at": 215572, "to": "mm"},
10142   "name": "GDS_PERFCOUNTER2_HI",
10143   "type_ref": "CPG_PERFCOUNTER1_HI"
10144  },
10145  {
10146   "chips": ["gfx10"],
10147   "map": {"at": 215576, "to": "mm"},
10148   "name": "GDS_PERFCOUNTER3_LO",
10149   "type_ref": "CPG_PERFCOUNTER1_LO"
10150  },
10151  {
10152   "chips": ["gfx10"],
10153   "map": {"at": 215580, "to": "mm"},
10154   "name": "GDS_PERFCOUNTER3_HI",
10155   "type_ref": "CPG_PERFCOUNTER1_HI"
10156  },
10157  {
10158   "chips": ["gfx10"],
10159   "map": {"at": 215808, "to": "mm"},
10160   "name": "TA_PERFCOUNTER0_LO",
10161   "type_ref": "CPG_PERFCOUNTER1_LO"
10162  },
10163  {
10164   "chips": ["gfx10"],
10165   "map": {"at": 215812, "to": "mm"},
10166   "name": "TA_PERFCOUNTER0_HI",
10167   "type_ref": "CPG_PERFCOUNTER1_HI"
10168  },
10169  {
10170   "chips": ["gfx10"],
10171   "map": {"at": 215816, "to": "mm"},
10172   "name": "TA_PERFCOUNTER1_LO",
10173   "type_ref": "CPG_PERFCOUNTER1_LO"
10174  },
10175  {
10176   "chips": ["gfx10"],
10177   "map": {"at": 215820, "to": "mm"},
10178   "name": "TA_PERFCOUNTER1_HI",
10179   "type_ref": "CPG_PERFCOUNTER1_HI"
10180  },
10181  {
10182   "chips": ["gfx10"],
10183   "map": {"at": 216064, "to": "mm"},
10184   "name": "TD_PERFCOUNTER0_LO",
10185   "type_ref": "CPG_PERFCOUNTER1_LO"
10186  },
10187  {
10188   "chips": ["gfx10"],
10189   "map": {"at": 216068, "to": "mm"},
10190   "name": "TD_PERFCOUNTER0_HI",
10191   "type_ref": "CPG_PERFCOUNTER1_HI"
10192  },
10193  {
10194   "chips": ["gfx10"],
10195   "map": {"at": 216072, "to": "mm"},
10196   "name": "TD_PERFCOUNTER1_LO",
10197   "type_ref": "CPG_PERFCOUNTER1_LO"
10198  },
10199  {
10200   "chips": ["gfx10"],
10201   "map": {"at": 216076, "to": "mm"},
10202   "name": "TD_PERFCOUNTER1_HI",
10203   "type_ref": "CPG_PERFCOUNTER1_HI"
10204  },
10205  {
10206   "chips": ["gfx10"],
10207   "map": {"at": 216320, "to": "mm"},
10208   "name": "TCP_PERFCOUNTER0_LO",
10209   "type_ref": "CPG_PERFCOUNTER1_LO"
10210  },
10211  {
10212   "chips": ["gfx10"],
10213   "map": {"at": 216324, "to": "mm"},
10214   "name": "TCP_PERFCOUNTER0_HI",
10215   "type_ref": "CPG_PERFCOUNTER1_HI"
10216  },
10217  {
10218   "chips": ["gfx10"],
10219   "map": {"at": 216328, "to": "mm"},
10220   "name": "TCP_PERFCOUNTER1_LO",
10221   "type_ref": "CPG_PERFCOUNTER1_LO"
10222  },
10223  {
10224   "chips": ["gfx10"],
10225   "map": {"at": 216332, "to": "mm"},
10226   "name": "TCP_PERFCOUNTER1_HI",
10227   "type_ref": "CPG_PERFCOUNTER1_HI"
10228  },
10229  {
10230   "chips": ["gfx10"],
10231   "map": {"at": 216336, "to": "mm"},
10232   "name": "TCP_PERFCOUNTER2_LO",
10233   "type_ref": "CPG_PERFCOUNTER1_LO"
10234  },
10235  {
10236   "chips": ["gfx10"],
10237   "map": {"at": 216340, "to": "mm"},
10238   "name": "TCP_PERFCOUNTER2_HI",
10239   "type_ref": "CPG_PERFCOUNTER1_HI"
10240  },
10241  {
10242   "chips": ["gfx10"],
10243   "map": {"at": 216344, "to": "mm"},
10244   "name": "TCP_PERFCOUNTER3_LO",
10245   "type_ref": "CPG_PERFCOUNTER1_LO"
10246  },
10247  {
10248   "chips": ["gfx10"],
10249   "map": {"at": 216348, "to": "mm"},
10250   "name": "TCP_PERFCOUNTER3_HI",
10251   "type_ref": "CPG_PERFCOUNTER1_HI"
10252  },
10253  {
10254   "chips": ["gfx10"],
10255   "map": {"at": 216576, "to": "mm"},
10256   "name": "GL2C_PERFCOUNTER0_LO",
10257   "type_ref": "CPG_PERFCOUNTER1_LO"
10258  },
10259  {
10260   "chips": ["gfx10"],
10261   "map": {"at": 216580, "to": "mm"},
10262   "name": "GL2C_PERFCOUNTER0_HI",
10263   "type_ref": "CPG_PERFCOUNTER1_HI"
10264  },
10265  {
10266   "chips": ["gfx10"],
10267   "map": {"at": 216584, "to": "mm"},
10268   "name": "GL2C_PERFCOUNTER1_LO",
10269   "type_ref": "CPG_PERFCOUNTER1_LO"
10270  },
10271  {
10272   "chips": ["gfx10"],
10273   "map": {"at": 216588, "to": "mm"},
10274   "name": "GL2C_PERFCOUNTER1_HI",
10275   "type_ref": "CPG_PERFCOUNTER1_HI"
10276  },
10277  {
10278   "chips": ["gfx10"],
10279   "map": {"at": 216592, "to": "mm"},
10280   "name": "GL2C_PERFCOUNTER2_LO",
10281   "type_ref": "CPG_PERFCOUNTER1_LO"
10282  },
10283  {
10284   "chips": ["gfx10"],
10285   "map": {"at": 216596, "to": "mm"},
10286   "name": "GL2C_PERFCOUNTER2_HI",
10287   "type_ref": "CPG_PERFCOUNTER1_HI"
10288  },
10289  {
10290   "chips": ["gfx10"],
10291   "map": {"at": 216600, "to": "mm"},
10292   "name": "GL2C_PERFCOUNTER3_LO",
10293   "type_ref": "CPG_PERFCOUNTER1_LO"
10294  },
10295  {
10296   "chips": ["gfx10"],
10297   "map": {"at": 216604, "to": "mm"},
10298   "name": "GL2C_PERFCOUNTER3_HI",
10299   "type_ref": "CPG_PERFCOUNTER1_HI"
10300  },
10301  {
10302   "chips": ["gfx10"],
10303   "map": {"at": 216640, "to": "mm"},
10304   "name": "GL2A_PERFCOUNTER0_LO",
10305   "type_ref": "CPG_PERFCOUNTER1_LO"
10306  },
10307  {
10308   "chips": ["gfx10"],
10309   "map": {"at": 216644, "to": "mm"},
10310   "name": "GL2A_PERFCOUNTER0_HI",
10311   "type_ref": "CPG_PERFCOUNTER1_HI"
10312  },
10313  {
10314   "chips": ["gfx10"],
10315   "map": {"at": 216648, "to": "mm"},
10316   "name": "GL2A_PERFCOUNTER1_LO",
10317   "type_ref": "CPG_PERFCOUNTER1_LO"
10318  },
10319  {
10320   "chips": ["gfx10"],
10321   "map": {"at": 216652, "to": "mm"},
10322   "name": "GL2A_PERFCOUNTER1_HI",
10323   "type_ref": "CPG_PERFCOUNTER1_HI"
10324  },
10325  {
10326   "chips": ["gfx10"],
10327   "map": {"at": 216656, "to": "mm"},
10328   "name": "GL2A_PERFCOUNTER2_LO",
10329   "type_ref": "CPG_PERFCOUNTER1_LO"
10330  },
10331  {
10332   "chips": ["gfx10"],
10333   "map": {"at": 216660, "to": "mm"},
10334   "name": "GL2A_PERFCOUNTER2_HI",
10335   "type_ref": "CPG_PERFCOUNTER1_HI"
10336  },
10337  {
10338   "chips": ["gfx10"],
10339   "map": {"at": 216664, "to": "mm"},
10340   "name": "GL2A_PERFCOUNTER3_LO",
10341   "type_ref": "CPG_PERFCOUNTER1_LO"
10342  },
10343  {
10344   "chips": ["gfx10"],
10345   "map": {"at": 216668, "to": "mm"},
10346   "name": "GL2A_PERFCOUNTER3_HI",
10347   "type_ref": "CPG_PERFCOUNTER1_HI"
10348  },
10349  {
10350   "chips": ["gfx10"],
10351   "map": {"at": 216704, "to": "mm"},
10352   "name": "GL1C_PERFCOUNTER0_LO",
10353   "type_ref": "CPG_PERFCOUNTER1_LO"
10354  },
10355  {
10356   "chips": ["gfx10"],
10357   "map": {"at": 216708, "to": "mm"},
10358   "name": "GL1C_PERFCOUNTER0_HI",
10359   "type_ref": "CPG_PERFCOUNTER1_HI"
10360  },
10361  {
10362   "chips": ["gfx10"],
10363   "map": {"at": 216712, "to": "mm"},
10364   "name": "GL1C_PERFCOUNTER1_LO",
10365   "type_ref": "CPG_PERFCOUNTER1_LO"
10366  },
10367  {
10368   "chips": ["gfx10"],
10369   "map": {"at": 216716, "to": "mm"},
10370   "name": "GL1C_PERFCOUNTER1_HI",
10371   "type_ref": "CPG_PERFCOUNTER1_HI"
10372  },
10373  {
10374   "chips": ["gfx10"],
10375   "map": {"at": 216720, "to": "mm"},
10376   "name": "GL1C_PERFCOUNTER2_LO",
10377   "type_ref": "CPG_PERFCOUNTER1_LO"
10378  },
10379  {
10380   "chips": ["gfx10"],
10381   "map": {"at": 216724, "to": "mm"},
10382   "name": "GL1C_PERFCOUNTER2_HI",
10383   "type_ref": "CPG_PERFCOUNTER1_HI"
10384  },
10385  {
10386   "chips": ["gfx10"],
10387   "map": {"at": 216728, "to": "mm"},
10388   "name": "GL1C_PERFCOUNTER3_LO",
10389   "type_ref": "CPG_PERFCOUNTER1_LO"
10390  },
10391  {
10392   "chips": ["gfx10"],
10393   "map": {"at": 216732, "to": "mm"},
10394   "name": "GL1C_PERFCOUNTER3_HI",
10395   "type_ref": "CPG_PERFCOUNTER1_HI"
10396  },
10397  {
10398   "chips": ["gfx10"],
10399   "map": {"at": 216832, "to": "mm"},
10400   "name": "CHC_PERFCOUNTER0_LO",
10401   "type_ref": "CPG_PERFCOUNTER1_LO"
10402  },
10403  {
10404   "chips": ["gfx10"],
10405   "map": {"at": 216836, "to": "mm"},
10406   "name": "CHC_PERFCOUNTER0_HI",
10407   "type_ref": "CPG_PERFCOUNTER1_HI"
10408  },
10409  {
10410   "chips": ["gfx10"],
10411   "map": {"at": 216840, "to": "mm"},
10412   "name": "CHC_PERFCOUNTER1_LO",
10413   "type_ref": "CPG_PERFCOUNTER1_LO"
10414  },
10415  {
10416   "chips": ["gfx10"],
10417   "map": {"at": 216844, "to": "mm"},
10418   "name": "CHC_PERFCOUNTER1_HI",
10419   "type_ref": "CPG_PERFCOUNTER1_HI"
10420  },
10421  {
10422   "chips": ["gfx10"],
10423   "map": {"at": 216848, "to": "mm"},
10424   "name": "CHC_PERFCOUNTER2_LO",
10425   "type_ref": "CPG_PERFCOUNTER1_LO"
10426  },
10427  {
10428   "chips": ["gfx10"],
10429   "map": {"at": 216852, "to": "mm"},
10430   "name": "CHC_PERFCOUNTER2_HI",
10431   "type_ref": "CPG_PERFCOUNTER1_HI"
10432  },
10433  {
10434   "chips": ["gfx10"],
10435   "map": {"at": 216856, "to": "mm"},
10436   "name": "CHC_PERFCOUNTER3_LO",
10437   "type_ref": "CPG_PERFCOUNTER1_LO"
10438  },
10439  {
10440   "chips": ["gfx10"],
10441   "map": {"at": 216860, "to": "mm"},
10442   "name": "CHC_PERFCOUNTER3_HI",
10443   "type_ref": "CPG_PERFCOUNTER1_HI"
10444  },
10445  {
10446   "chips": ["gfx10"],
10447   "map": {"at": 216864, "to": "mm"},
10448   "name": "CHCG_PERFCOUNTER0_LO",
10449   "type_ref": "CPG_PERFCOUNTER1_LO"
10450  },
10451  {
10452   "chips": ["gfx10"],
10453   "map": {"at": 216868, "to": "mm"},
10454   "name": "CHCG_PERFCOUNTER0_HI",
10455   "type_ref": "CPG_PERFCOUNTER1_HI"
10456  },
10457  {
10458   "chips": ["gfx10"],
10459   "map": {"at": 216872, "to": "mm"},
10460   "name": "CHCG_PERFCOUNTER1_LO",
10461   "type_ref": "CPG_PERFCOUNTER1_LO"
10462  },
10463  {
10464   "chips": ["gfx10"],
10465   "map": {"at": 216876, "to": "mm"},
10466   "name": "CHCG_PERFCOUNTER1_HI",
10467   "type_ref": "CPG_PERFCOUNTER1_HI"
10468  },
10469  {
10470   "chips": ["gfx10"],
10471   "map": {"at": 216880, "to": "mm"},
10472   "name": "CHCG_PERFCOUNTER2_LO",
10473   "type_ref": "CPG_PERFCOUNTER1_LO"
10474  },
10475  {
10476   "chips": ["gfx10"],
10477   "map": {"at": 216884, "to": "mm"},
10478   "name": "CHCG_PERFCOUNTER2_HI",
10479   "type_ref": "CPG_PERFCOUNTER1_HI"
10480  },
10481  {
10482   "chips": ["gfx10"],
10483   "map": {"at": 216888, "to": "mm"},
10484   "name": "CHCG_PERFCOUNTER3_LO",
10485   "type_ref": "CPG_PERFCOUNTER1_LO"
10486  },
10487  {
10488   "chips": ["gfx10"],
10489   "map": {"at": 216892, "to": "mm"},
10490   "name": "CHCG_PERFCOUNTER3_HI",
10491   "type_ref": "CPG_PERFCOUNTER1_HI"
10492  },
10493  {
10494   "chips": ["gfx10"],
10495   "map": {"at": 217112, "to": "mm"},
10496   "name": "CB_PERFCOUNTER0_LO",
10497   "type_ref": "CPG_PERFCOUNTER1_LO"
10498  },
10499  {
10500   "chips": ["gfx10"],
10501   "map": {"at": 217116, "to": "mm"},
10502   "name": "CB_PERFCOUNTER0_HI",
10503   "type_ref": "CPG_PERFCOUNTER1_HI"
10504  },
10505  {
10506   "chips": ["gfx10"],
10507   "map": {"at": 217120, "to": "mm"},
10508   "name": "CB_PERFCOUNTER1_LO",
10509   "type_ref": "CPG_PERFCOUNTER1_LO"
10510  },
10511  {
10512   "chips": ["gfx10"],
10513   "map": {"at": 217124, "to": "mm"},
10514   "name": "CB_PERFCOUNTER1_HI",
10515   "type_ref": "CPG_PERFCOUNTER1_HI"
10516  },
10517  {
10518   "chips": ["gfx10"],
10519   "map": {"at": 217128, "to": "mm"},
10520   "name": "CB_PERFCOUNTER2_LO",
10521   "type_ref": "CPG_PERFCOUNTER1_LO"
10522  },
10523  {
10524   "chips": ["gfx10"],
10525   "map": {"at": 217132, "to": "mm"},
10526   "name": "CB_PERFCOUNTER2_HI",
10527   "type_ref": "CPG_PERFCOUNTER1_HI"
10528  },
10529  {
10530   "chips": ["gfx10"],
10531   "map": {"at": 217136, "to": "mm"},
10532   "name": "CB_PERFCOUNTER3_LO",
10533   "type_ref": "CPG_PERFCOUNTER1_LO"
10534  },
10535  {
10536   "chips": ["gfx10"],
10537   "map": {"at": 217140, "to": "mm"},
10538   "name": "CB_PERFCOUNTER3_HI",
10539   "type_ref": "CPG_PERFCOUNTER1_HI"
10540  },
10541  {
10542   "chips": ["gfx10"],
10543   "map": {"at": 217344, "to": "mm"},
10544   "name": "DB_PERFCOUNTER0_LO",
10545   "type_ref": "CPG_PERFCOUNTER1_LO"
10546  },
10547  {
10548   "chips": ["gfx10"],
10549   "map": {"at": 217348, "to": "mm"},
10550   "name": "DB_PERFCOUNTER0_HI",
10551   "type_ref": "CPG_PERFCOUNTER1_HI"
10552  },
10553  {
10554   "chips": ["gfx10"],
10555   "map": {"at": 217352, "to": "mm"},
10556   "name": "DB_PERFCOUNTER1_LO",
10557   "type_ref": "CPG_PERFCOUNTER1_LO"
10558  },
10559  {
10560   "chips": ["gfx10"],
10561   "map": {"at": 217356, "to": "mm"},
10562   "name": "DB_PERFCOUNTER1_HI",
10563   "type_ref": "CPG_PERFCOUNTER1_HI"
10564  },
10565  {
10566   "chips": ["gfx10"],
10567   "map": {"at": 217360, "to": "mm"},
10568   "name": "DB_PERFCOUNTER2_LO",
10569   "type_ref": "CPG_PERFCOUNTER1_LO"
10570  },
10571  {
10572   "chips": ["gfx10"],
10573   "map": {"at": 217364, "to": "mm"},
10574   "name": "DB_PERFCOUNTER2_HI",
10575   "type_ref": "CPG_PERFCOUNTER1_HI"
10576  },
10577  {
10578   "chips": ["gfx10"],
10579   "map": {"at": 217368, "to": "mm"},
10580   "name": "DB_PERFCOUNTER3_LO",
10581   "type_ref": "CPG_PERFCOUNTER1_LO"
10582  },
10583  {
10584   "chips": ["gfx10"],
10585   "map": {"at": 217372, "to": "mm"},
10586   "name": "DB_PERFCOUNTER3_HI",
10587   "type_ref": "CPG_PERFCOUNTER1_HI"
10588  },
10589  {
10590   "chips": ["gfx10"],
10591   "map": {"at": 217600, "to": "mm"},
10592   "name": "RLC_PERFCOUNTER0_LO",
10593   "type_ref": "CPG_PERFCOUNTER1_LO"
10594  },
10595  {
10596   "chips": ["gfx10"],
10597   "map": {"at": 217604, "to": "mm"},
10598   "name": "RLC_PERFCOUNTER0_HI",
10599   "type_ref": "CPG_PERFCOUNTER1_HI"
10600  },
10601  {
10602   "chips": ["gfx10"],
10603   "map": {"at": 217608, "to": "mm"},
10604   "name": "RLC_PERFCOUNTER1_LO",
10605   "type_ref": "CPG_PERFCOUNTER1_LO"
10606  },
10607  {
10608   "chips": ["gfx10"],
10609   "map": {"at": 217612, "to": "mm"},
10610   "name": "RLC_PERFCOUNTER1_HI",
10611   "type_ref": "CPG_PERFCOUNTER1_HI"
10612  },
10613  {
10614   "chips": ["gfx10"],
10615   "map": {"at": 217856, "to": "mm"},
10616   "name": "RMI_PERFCOUNTER0_LO",
10617   "type_ref": "CPG_PERFCOUNTER1_LO"
10618  },
10619  {
10620   "chips": ["gfx10"],
10621   "map": {"at": 217860, "to": "mm"},
10622   "name": "RMI_PERFCOUNTER0_HI",
10623   "type_ref": "CPG_PERFCOUNTER1_HI"
10624  },
10625  {
10626   "chips": ["gfx10"],
10627   "map": {"at": 217864, "to": "mm"},
10628   "name": "RMI_PERFCOUNTER1_LO",
10629   "type_ref": "CPG_PERFCOUNTER1_LO"
10630  },
10631  {
10632   "chips": ["gfx10"],
10633   "map": {"at": 217868, "to": "mm"},
10634   "name": "RMI_PERFCOUNTER1_HI",
10635   "type_ref": "CPG_PERFCOUNTER1_HI"
10636  },
10637  {
10638   "chips": ["gfx10"],
10639   "map": {"at": 217872, "to": "mm"},
10640   "name": "RMI_PERFCOUNTER2_LO",
10641   "type_ref": "CPG_PERFCOUNTER1_LO"
10642  },
10643  {
10644   "chips": ["gfx10"],
10645   "map": {"at": 217876, "to": "mm"},
10646   "name": "RMI_PERFCOUNTER2_HI",
10647   "type_ref": "CPG_PERFCOUNTER1_HI"
10648  },
10649  {
10650   "chips": ["gfx10"],
10651   "map": {"at": 217880, "to": "mm"},
10652   "name": "RMI_PERFCOUNTER3_LO",
10653   "type_ref": "CPG_PERFCOUNTER1_LO"
10654  },
10655  {
10656   "chips": ["gfx10"],
10657   "map": {"at": 217884, "to": "mm"},
10658   "name": "RMI_PERFCOUNTER3_HI",
10659   "type_ref": "CPG_PERFCOUNTER1_HI"
10660  },
10661  {
10662   "chips": ["gfx10"],
10663   "map": {"at": 217984, "to": "mm"},
10664   "name": "GC_ATC_L2_PERFCOUNTER_LO",
10665   "type_ref": "GC_ATC_L2_PERFCOUNTER_LO"
10666  },
10667  {
10668   "chips": ["gfx10"],
10669   "map": {"at": 217988, "to": "mm"},
10670   "name": "GC_ATC_L2_PERFCOUNTER_HI",
10671   "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
10672  },
10673  {
10674   "chips": ["gfx10"],
10675   "map": {"at": 218016, "to": "mm"},
10676   "name": "GCMC_VM_L2_PERFCOUNTER_LO",
10677   "type_ref": "GC_ATC_L2_PERFCOUNTER_LO"
10678  },
10679  {
10680   "chips": ["gfx10"],
10681   "map": {"at": 218020, "to": "mm"},
10682   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
10683   "type_ref": "GC_ATC_L2_PERFCOUNTER_HI"
10684  },
10685  {
10686   "chips": ["gfx10"],
10687   "map": {"at": 218080, "to": "mm"},
10688   "name": "GCVML2_PERFCOUNTER2_0_LO",
10689   "type_ref": "CPG_PERFCOUNTER1_LO"
10690  },
10691  {
10692   "chips": ["gfx10"],
10693   "map": {"at": 218084, "to": "mm"},
10694   "name": "GCVML2_PERFCOUNTER2_1_LO",
10695   "type_ref": "CPG_PERFCOUNTER1_LO"
10696  },
10697  {
10698   "chips": ["gfx10"],
10699   "map": {"at": 218088, "to": "mm"},
10700   "name": "GCVML2_PERFCOUNTER2_0_HI",
10701   "type_ref": "CPG_PERFCOUNTER1_HI"
10702  },
10703  {
10704   "chips": ["gfx10"],
10705   "map": {"at": 218092, "to": "mm"},
10706   "name": "GCVML2_PERFCOUNTER2_1_HI",
10707   "type_ref": "CPG_PERFCOUNTER1_HI"
10708  },
10709  {
10710   "chips": ["gfx10"],
10711   "map": {"at": 218096, "to": "mm"},
10712   "name": "GC_ATC_L2_PERFCOUNTER2_LO",
10713   "type_ref": "CPG_PERFCOUNTER1_LO"
10714  },
10715  {
10716   "chips": ["gfx10"],
10717   "map": {"at": 218100, "to": "mm"},
10718   "name": "GC_ATC_L2_PERFCOUNTER2_HI",
10719   "type_ref": "CPG_PERFCOUNTER1_HI"
10720  },
10721  {
10722   "chips": ["gfx10"],
10723   "map": {"at": 218224, "to": "mm"},
10724   "name": "UTCL1_PERFCOUNTER0_LO",
10725   "type_ref": "CPG_PERFCOUNTER1_LO"
10726  },
10727  {
10728   "chips": ["gfx10"],
10729   "map": {"at": 218228, "to": "mm"},
10730   "name": "UTCL1_PERFCOUNTER0_HI",
10731   "type_ref": "CPG_PERFCOUNTER1_HI"
10732  },
10733  {
10734   "chips": ["gfx10"],
10735   "map": {"at": 218232, "to": "mm"},
10736   "name": "UTCL1_PERFCOUNTER1_LO",
10737   "type_ref": "CPG_PERFCOUNTER1_LO"
10738  },
10739  {
10740   "chips": ["gfx10"],
10741   "map": {"at": 218236, "to": "mm"},
10742   "name": "UTCL1_PERFCOUNTER1_HI",
10743   "type_ref": "CPG_PERFCOUNTER1_HI"
10744  },
10745  {
10746   "chips": ["gfx10"],
10747   "map": {"at": 218240, "to": "mm"},
10748   "name": "GCR_PERFCOUNTER0_LO",
10749   "type_ref": "CPG_PERFCOUNTER1_LO"
10750  },
10751  {
10752   "chips": ["gfx10"],
10753   "map": {"at": 218244, "to": "mm"},
10754   "name": "GCR_PERFCOUNTER0_HI",
10755   "type_ref": "CPG_PERFCOUNTER1_HI"
10756  },
10757  {
10758   "chips": ["gfx10"],
10759   "map": {"at": 218248, "to": "mm"},
10760   "name": "GCR_PERFCOUNTER1_LO",
10761   "type_ref": "CPG_PERFCOUNTER1_LO"
10762  },
10763  {
10764   "chips": ["gfx10"],
10765   "map": {"at": 218252, "to": "mm"},
10766   "name": "GCR_PERFCOUNTER1_HI",
10767   "type_ref": "CPG_PERFCOUNTER1_HI"
10768  },
10769  {
10770   "chips": ["gfx10"],
10771   "map": {"at": 218624, "to": "mm"},
10772   "name": "PA_PH_PERFCOUNTER0_LO",
10773   "type_ref": "CPG_PERFCOUNTER1_LO"
10774  },
10775  {
10776   "chips": ["gfx10"],
10777   "map": {"at": 218628, "to": "mm"},
10778   "name": "PA_PH_PERFCOUNTER0_HI",
10779   "type_ref": "CPG_PERFCOUNTER1_HI"
10780  },
10781  {
10782   "chips": ["gfx10"],
10783   "map": {"at": 218632, "to": "mm"},
10784   "name": "PA_PH_PERFCOUNTER1_LO",
10785   "type_ref": "CPG_PERFCOUNTER1_LO"
10786  },
10787  {
10788   "chips": ["gfx10"],
10789   "map": {"at": 218636, "to": "mm"},
10790   "name": "PA_PH_PERFCOUNTER1_HI",
10791   "type_ref": "CPG_PERFCOUNTER1_HI"
10792  },
10793  {
10794   "chips": ["gfx10"],
10795   "map": {"at": 218640, "to": "mm"},
10796   "name": "PA_PH_PERFCOUNTER2_LO",
10797   "type_ref": "CPG_PERFCOUNTER1_LO"
10798  },
10799  {
10800   "chips": ["gfx10"],
10801   "map": {"at": 218644, "to": "mm"},
10802   "name": "PA_PH_PERFCOUNTER2_HI",
10803   "type_ref": "CPG_PERFCOUNTER1_HI"
10804  },
10805  {
10806   "chips": ["gfx10"],
10807   "map": {"at": 218648, "to": "mm"},
10808   "name": "PA_PH_PERFCOUNTER3_LO",
10809   "type_ref": "CPG_PERFCOUNTER1_LO"
10810  },
10811  {
10812   "chips": ["gfx10"],
10813   "map": {"at": 218652, "to": "mm"},
10814   "name": "PA_PH_PERFCOUNTER3_HI",
10815   "type_ref": "CPG_PERFCOUNTER1_HI"
10816  },
10817  {
10818   "chips": ["gfx10"],
10819   "map": {"at": 218656, "to": "mm"},
10820   "name": "PA_PH_PERFCOUNTER4_LO",
10821   "type_ref": "CPG_PERFCOUNTER1_LO"
10822  },
10823  {
10824   "chips": ["gfx10"],
10825   "map": {"at": 218660, "to": "mm"},
10826   "name": "PA_PH_PERFCOUNTER4_HI",
10827   "type_ref": "CPG_PERFCOUNTER1_HI"
10828  },
10829  {
10830   "chips": ["gfx10"],
10831   "map": {"at": 218664, "to": "mm"},
10832   "name": "PA_PH_PERFCOUNTER5_LO",
10833   "type_ref": "CPG_PERFCOUNTER1_LO"
10834  },
10835  {
10836   "chips": ["gfx10"],
10837   "map": {"at": 218668, "to": "mm"},
10838   "name": "PA_PH_PERFCOUNTER5_HI",
10839   "type_ref": "CPG_PERFCOUNTER1_HI"
10840  },
10841  {
10842   "chips": ["gfx10"],
10843   "map": {"at": 218672, "to": "mm"},
10844   "name": "PA_PH_PERFCOUNTER6_LO",
10845   "type_ref": "CPG_PERFCOUNTER1_LO"
10846  },
10847  {
10848   "chips": ["gfx10"],
10849   "map": {"at": 218676, "to": "mm"},
10850   "name": "PA_PH_PERFCOUNTER6_HI",
10851   "type_ref": "CPG_PERFCOUNTER1_HI"
10852  },
10853  {
10854   "chips": ["gfx10"],
10855   "map": {"at": 218680, "to": "mm"},
10856   "name": "PA_PH_PERFCOUNTER7_LO",
10857   "type_ref": "CPG_PERFCOUNTER1_LO"
10858  },
10859  {
10860   "chips": ["gfx10"],
10861   "map": {"at": 218684, "to": "mm"},
10862   "name": "PA_PH_PERFCOUNTER7_HI",
10863   "type_ref": "CPG_PERFCOUNTER1_HI"
10864  },
10865  {
10866   "chips": ["gfx10"],
10867   "map": {"at": 218880, "to": "mm"},
10868   "name": "GL1A_PERFCOUNTER0_LO",
10869   "type_ref": "CPG_PERFCOUNTER1_LO"
10870  },
10871  {
10872   "chips": ["gfx10"],
10873   "map": {"at": 218884, "to": "mm"},
10874   "name": "GL1A_PERFCOUNTER0_HI",
10875   "type_ref": "CPG_PERFCOUNTER1_HI"
10876  },
10877  {
10878   "chips": ["gfx10"],
10879   "map": {"at": 218888, "to": "mm"},
10880   "name": "GL1A_PERFCOUNTER1_LO",
10881   "type_ref": "CPG_PERFCOUNTER1_LO"
10882  },
10883  {
10884   "chips": ["gfx10"],
10885   "map": {"at": 218892, "to": "mm"},
10886   "name": "GL1A_PERFCOUNTER1_HI",
10887   "type_ref": "CPG_PERFCOUNTER1_HI"
10888  },
10889  {
10890   "chips": ["gfx10"],
10891   "map": {"at": 218896, "to": "mm"},
10892   "name": "GL1A_PERFCOUNTER2_LO",
10893   "type_ref": "CPG_PERFCOUNTER1_LO"
10894  },
10895  {
10896   "chips": ["gfx10"],
10897   "map": {"at": 218900, "to": "mm"},
10898   "name": "GL1A_PERFCOUNTER2_HI",
10899   "type_ref": "CPG_PERFCOUNTER1_HI"
10900  },
10901  {
10902   "chips": ["gfx10"],
10903   "map": {"at": 218904, "to": "mm"},
10904   "name": "GL1A_PERFCOUNTER3_LO",
10905   "type_ref": "CPG_PERFCOUNTER1_LO"
10906  },
10907  {
10908   "chips": ["gfx10"],
10909   "map": {"at": 218908, "to": "mm"},
10910   "name": "GL1A_PERFCOUNTER3_HI",
10911   "type_ref": "CPG_PERFCOUNTER1_HI"
10912  },
10913  {
10914   "chips": ["gfx10"],
10915   "map": {"at": 219136, "to": "mm"},
10916   "name": "CHA_PERFCOUNTER0_LO",
10917   "type_ref": "CPG_PERFCOUNTER1_LO"
10918  },
10919  {
10920   "chips": ["gfx10"],
10921   "map": {"at": 219140, "to": "mm"},
10922   "name": "CHA_PERFCOUNTER0_HI",
10923   "type_ref": "CPG_PERFCOUNTER1_HI"
10924  },
10925  {
10926   "chips": ["gfx10"],
10927   "map": {"at": 219144, "to": "mm"},
10928   "name": "CHA_PERFCOUNTER1_LO",
10929   "type_ref": "CPG_PERFCOUNTER1_LO"
10930  },
10931  {
10932   "chips": ["gfx10"],
10933   "map": {"at": 219148, "to": "mm"},
10934   "name": "CHA_PERFCOUNTER1_HI",
10935   "type_ref": "CPG_PERFCOUNTER1_HI"
10936  },
10937  {
10938   "chips": ["gfx10"],
10939   "map": {"at": 219152, "to": "mm"},
10940   "name": "CHA_PERFCOUNTER2_LO",
10941   "type_ref": "CPG_PERFCOUNTER1_LO"
10942  },
10943  {
10944   "chips": ["gfx10"],
10945   "map": {"at": 219156, "to": "mm"},
10946   "name": "CHA_PERFCOUNTER2_HI",
10947   "type_ref": "CPG_PERFCOUNTER1_HI"
10948  },
10949  {
10950   "chips": ["gfx10"],
10951   "map": {"at": 219160, "to": "mm"},
10952   "name": "CHA_PERFCOUNTER3_LO",
10953   "type_ref": "CPG_PERFCOUNTER1_LO"
10954  },
10955  {
10956   "chips": ["gfx10"],
10957   "map": {"at": 219164, "to": "mm"},
10958   "name": "CHA_PERFCOUNTER3_HI",
10959   "type_ref": "CPG_PERFCOUNTER1_HI"
10960  },
10961  {
10962   "chips": ["gfx10"],
10963   "map": {"at": 219392, "to": "mm"},
10964   "name": "GUS_PERFCOUNTER2_LO",
10965   "type_ref": "CPG_PERFCOUNTER1_LO"
10966  },
10967  {
10968   "chips": ["gfx10"],
10969   "map": {"at": 219396, "to": "mm"},
10970   "name": "GUS_PERFCOUNTER2_HI",
10971   "type_ref": "CPG_PERFCOUNTER1_HI"
10972  },
10973  {
10974   "chips": ["gfx10"],
10975   "map": {"at": 221184, "to": "mm"},
10976   "name": "CPG_PERFCOUNTER1_SELECT",
10977   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10978  },
10979  {
10980   "chips": ["gfx10"],
10981   "map": {"at": 221188, "to": "mm"},
10982   "name": "CPG_PERFCOUNTER0_SELECT1",
10983   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10984  },
10985  {
10986   "chips": ["gfx10"],
10987   "map": {"at": 221192, "to": "mm"},
10988   "name": "CPG_PERFCOUNTER0_SELECT",
10989   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10990  },
10991  {
10992   "chips": ["gfx10"],
10993   "map": {"at": 221196, "to": "mm"},
10994   "name": "CPC_PERFCOUNTER1_SELECT",
10995   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10996  },
10997  {
10998   "chips": ["gfx10"],
10999   "map": {"at": 221200, "to": "mm"},
11000   "name": "CPC_PERFCOUNTER0_SELECT1",
11001   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
11002  },
11003  {
11004   "chips": ["gfx10"],
11005   "map": {"at": 221204, "to": "mm"},
11006   "name": "CPF_PERFCOUNTER1_SELECT",
11007   "type_ref": "CPG_PERFCOUNTER1_SELECT"
11008  },
11009  {
11010   "chips": ["gfx10"],
11011   "map": {"at": 221208, "to": "mm"},
11012   "name": "CPF_PERFCOUNTER0_SELECT1",
11013   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
11014  },
11015  {
11016   "chips": ["gfx10"],
11017   "map": {"at": 221212, "to": "mm"},
11018   "name": "CPF_PERFCOUNTER0_SELECT",
11019   "type_ref": "CPG_PERFCOUNTER1_SELECT"
11020  },
11021  {
11022   "chips": ["gfx10"],
11023   "map": {"at": 221216, "to": "mm"},
11024   "name": "CP_PERFMON_CNTL",
11025   "type_ref": "CP_PERFMON_CNTL"
11026  },
11027  {
11028   "chips": ["gfx10"],
11029   "map": {"at": 221220, "to": "mm"},
11030   "name": "CPC_PERFCOUNTER0_SELECT",
11031   "type_ref": "CPG_PERFCOUNTER1_SELECT"
11032  },
11033  {
11034   "chips": ["gfx10"],
11035   "map": {"at": 221224, "to": "mm"},
11036   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
11037   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
11038  },
11039  {
11040   "chips": ["gfx10"],
11041   "map": {"at": 221228, "to": "mm"},
11042   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
11043   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
11044  },
11045  {
11046   "chips": ["gfx10"],
11047   "map": {"at": 221232, "to": "mm"},
11048   "name": "CPF_LATENCY_STATS_SELECT",
11049   "type_ref": "CPF_LATENCY_STATS_SELECT"
11050  },
11051  {
11052   "chips": ["gfx10"],
11053   "map": {"at": 221236, "to": "mm"},
11054   "name": "CPG_LATENCY_STATS_SELECT",
11055   "type_ref": "CPG_LATENCY_STATS_SELECT"
11056  },
11057  {
11058   "chips": ["gfx10"],
11059   "map": {"at": 221240, "to": "mm"},
11060   "name": "CPC_LATENCY_STATS_SELECT",
11061   "type_ref": "CPF_LATENCY_STATS_SELECT"
11062  },
11063  {
11064   "chips": ["gfx10"],
11065   "map": {"at": 221248, "to": "mm"},
11066   "name": "CP_DRAW_OBJECT",
11067   "type_ref": "CP_DRAW_OBJECT"
11068  },
11069  {
11070   "chips": ["gfx10"],
11071   "map": {"at": 221252, "to": "mm"},
11072   "name": "CP_DRAW_OBJECT_COUNTER",
11073   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
11074  },
11075  {
11076   "chips": ["gfx10"],
11077   "map": {"at": 221256, "to": "mm"},
11078   "name": "CP_DRAW_WINDOW_MASK_HI",
11079   "type_ref": "CP_DRAW_WINDOW_MASK_HI"
11080  },
11081  {
11082   "chips": ["gfx10"],
11083   "map": {"at": 221260, "to": "mm"},
11084   "name": "CP_DRAW_WINDOW_HI",
11085   "type_ref": "CP_DRAW_WINDOW_HI"
11086  },
11087  {
11088   "chips": ["gfx10"],
11089   "map": {"at": 221264, "to": "mm"},
11090   "name": "CP_DRAW_WINDOW_LO",
11091   "type_ref": "CP_DRAW_WINDOW_LO"
11092  },
11093  {
11094   "chips": ["gfx10"],
11095   "map": {"at": 221268, "to": "mm"},
11096   "name": "CP_DRAW_WINDOW_CNTL",
11097   "type_ref": "CP_DRAW_WINDOW_CNTL"
11098  },
11099  {
11100   "chips": ["gfx10"],
11101   "map": {"at": 221440, "to": "mm"},
11102   "name": "GRBM_PERFCOUNTER0_SELECT",
11103   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
11104  },
11105  {
11106   "chips": ["gfx10"],
11107   "map": {"at": 221444, "to": "mm"},
11108   "name": "GRBM_PERFCOUNTER1_SELECT",
11109   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
11110  },
11111  {
11112   "chips": ["gfx10"],
11113   "map": {"at": 221448, "to": "mm"},
11114   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
11115   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11116  },
11117  {
11118   "chips": ["gfx10"],
11119   "map": {"at": 221452, "to": "mm"},
11120   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
11121   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11122  },
11123  {
11124   "chips": ["gfx10"],
11125   "map": {"at": 221456, "to": "mm"},
11126   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
11127   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11128  },
11129  {
11130   "chips": ["gfx10"],
11131   "map": {"at": 221460, "to": "mm"},
11132   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
11133   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
11134  },
11135  {
11136   "chips": ["gfx10"],
11137   "map": {"at": 221492, "to": "mm"},
11138   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
11139   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
11140  },
11141  {
11142   "chips": ["gfx10"],
11143   "map": {"at": 221496, "to": "mm"},
11144   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
11145   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
11146  },
11147  {
11148   "chips": ["gfx10"],
11149   "map": {"at": 221696, "to": "mm"},
11150   "name": "GE_PERFCOUNTER0_SELECT",
11151   "type_ref": "GE_PERFCOUNTER0_SELECT"
11152  },
11153  {
11154   "chips": ["gfx10"],
11155   "map": {"at": 221700, "to": "mm"},
11156   "name": "GE_PERFCOUNTER0_SELECT1",
11157   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11158  },
11159  {
11160   "chips": ["gfx10"],
11161   "map": {"at": 221704, "to": "mm"},
11162   "name": "GE_PERFCOUNTER1_SELECT",
11163   "type_ref": "GE_PERFCOUNTER0_SELECT"
11164  },
11165  {
11166   "chips": ["gfx10"],
11167   "map": {"at": 221708, "to": "mm"},
11168   "name": "GE_PERFCOUNTER1_SELECT1",
11169   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11170  },
11171  {
11172   "chips": ["gfx10"],
11173   "map": {"at": 221712, "to": "mm"},
11174   "name": "GE_PERFCOUNTER2_SELECT",
11175   "type_ref": "GE_PERFCOUNTER0_SELECT"
11176  },
11177  {
11178   "chips": ["gfx10"],
11179   "map": {"at": 221716, "to": "mm"},
11180   "name": "GE_PERFCOUNTER2_SELECT1",
11181   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11182  },
11183  {
11184   "chips": ["gfx10"],
11185   "map": {"at": 221720, "to": "mm"},
11186   "name": "GE_PERFCOUNTER3_SELECT",
11187   "type_ref": "GE_PERFCOUNTER0_SELECT"
11188  },
11189  {
11190   "chips": ["gfx10"],
11191   "map": {"at": 221724, "to": "mm"},
11192   "name": "GE_PERFCOUNTER3_SELECT1",
11193   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11194  },
11195  {
11196   "chips": ["gfx10"],
11197   "map": {"at": 221728, "to": "mm"},
11198   "name": "GE_PERFCOUNTER4_SELECT",
11199   "type_ref": "GE_PERFCOUNTER4_SELECT"
11200  },
11201  {
11202   "chips": ["gfx10"],
11203   "map": {"at": 221736, "to": "mm"},
11204   "name": "GE_PERFCOUNTER5_SELECT",
11205   "type_ref": "GE_PERFCOUNTER4_SELECT"
11206  },
11207  {
11208   "chips": ["gfx10"],
11209   "map": {"at": 221744, "to": "mm"},
11210   "name": "GE_PERFCOUNTER6_SELECT",
11211   "type_ref": "GE_PERFCOUNTER4_SELECT"
11212  },
11213  {
11214   "chips": ["gfx10"],
11215   "map": {"at": 221752, "to": "mm"},
11216   "name": "GE_PERFCOUNTER7_SELECT",
11217   "type_ref": "GE_PERFCOUNTER4_SELECT"
11218  },
11219  {
11220   "chips": ["gfx10"],
11221   "map": {"at": 221760, "to": "mm"},
11222   "name": "GE_PERFCOUNTER8_SELECT",
11223   "type_ref": "GE_PERFCOUNTER4_SELECT"
11224  },
11225  {
11226   "chips": ["gfx10"],
11227   "map": {"at": 221768, "to": "mm"},
11228   "name": "GE_PERFCOUNTER9_SELECT",
11229   "type_ref": "GE_PERFCOUNTER4_SELECT"
11230  },
11231  {
11232   "chips": ["gfx10"],
11233   "map": {"at": 221776, "to": "mm"},
11234   "name": "GE_PERFCOUNTER10_SELECT",
11235   "type_ref": "GE_PERFCOUNTER4_SELECT"
11236  },
11237  {
11238   "chips": ["gfx10"],
11239   "map": {"at": 221784, "to": "mm"},
11240   "name": "GE_PERFCOUNTER11_SELECT",
11241   "type_ref": "GE_PERFCOUNTER4_SELECT"
11242  },
11243  {
11244   "chips": ["gfx10"],
11245   "map": {"at": 222208, "to": "mm"},
11246   "name": "PA_SU_PERFCOUNTER0_SELECT",
11247   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11248  },
11249  {
11250   "chips": ["gfx10"],
11251   "map": {"at": 222212, "to": "mm"},
11252   "name": "PA_SU_PERFCOUNTER0_SELECT1",
11253   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11254  },
11255  {
11256   "chips": ["gfx10"],
11257   "map": {"at": 222216, "to": "mm"},
11258   "name": "PA_SU_PERFCOUNTER1_SELECT",
11259   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11260  },
11261  {
11262   "chips": ["gfx10"],
11263   "map": {"at": 222220, "to": "mm"},
11264   "name": "PA_SU_PERFCOUNTER1_SELECT1",
11265   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11266  },
11267  {
11268   "chips": ["gfx10"],
11269   "map": {"at": 222224, "to": "mm"},
11270   "name": "PA_SU_PERFCOUNTER2_SELECT",
11271   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11272  },
11273  {
11274   "chips": ["gfx10"],
11275   "map": {"at": 222228, "to": "mm"},
11276   "name": "PA_SU_PERFCOUNTER2_SELECT1",
11277   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11278  },
11279  {
11280   "chips": ["gfx10"],
11281   "map": {"at": 222232, "to": "mm"},
11282   "name": "PA_SU_PERFCOUNTER3_SELECT",
11283   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11284  },
11285  {
11286   "chips": ["gfx10"],
11287   "map": {"at": 222236, "to": "mm"},
11288   "name": "PA_SU_PERFCOUNTER3_SELECT1",
11289   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11290  },
11291  {
11292   "chips": ["gfx10"],
11293   "map": {"at": 222464, "to": "mm"},
11294   "name": "PA_SC_PERFCOUNTER0_SELECT",
11295   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11296  },
11297  {
11298   "chips": ["gfx10"],
11299   "map": {"at": 222468, "to": "mm"},
11300   "name": "PA_SC_PERFCOUNTER0_SELECT1",
11301   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11302  },
11303  {
11304   "chips": ["gfx10"],
11305   "map": {"at": 222472, "to": "mm"},
11306   "name": "PA_SC_PERFCOUNTER1_SELECT",
11307   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11308  },
11309  {
11310   "chips": ["gfx10"],
11311   "map": {"at": 222476, "to": "mm"},
11312   "name": "PA_SC_PERFCOUNTER2_SELECT",
11313   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11314  },
11315  {
11316   "chips": ["gfx10"],
11317   "map": {"at": 222480, "to": "mm"},
11318   "name": "PA_SC_PERFCOUNTER3_SELECT",
11319   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11320  },
11321  {
11322   "chips": ["gfx10"],
11323   "map": {"at": 222484, "to": "mm"},
11324   "name": "PA_SC_PERFCOUNTER4_SELECT",
11325   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11326  },
11327  {
11328   "chips": ["gfx10"],
11329   "map": {"at": 222488, "to": "mm"},
11330   "name": "PA_SC_PERFCOUNTER5_SELECT",
11331   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11332  },
11333  {
11334   "chips": ["gfx10"],
11335   "map": {"at": 222492, "to": "mm"},
11336   "name": "PA_SC_PERFCOUNTER6_SELECT",
11337   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11338  },
11339  {
11340   "chips": ["gfx10"],
11341   "map": {"at": 222496, "to": "mm"},
11342   "name": "PA_SC_PERFCOUNTER7_SELECT",
11343   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11344  },
11345  {
11346   "chips": ["gfx10"],
11347   "map": {"at": 222720, "to": "mm"},
11348   "name": "SPI_PERFCOUNTER0_SELECT",
11349   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11350  },
11351  {
11352   "chips": ["gfx10"],
11353   "map": {"at": 222724, "to": "mm"},
11354   "name": "SPI_PERFCOUNTER1_SELECT",
11355   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11356  },
11357  {
11358   "chips": ["gfx10"],
11359   "map": {"at": 222728, "to": "mm"},
11360   "name": "SPI_PERFCOUNTER2_SELECT",
11361   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11362  },
11363  {
11364   "chips": ["gfx10"],
11365   "map": {"at": 222732, "to": "mm"},
11366   "name": "SPI_PERFCOUNTER3_SELECT",
11367   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11368  },
11369  {
11370   "chips": ["gfx10"],
11371   "map": {"at": 222736, "to": "mm"},
11372   "name": "SPI_PERFCOUNTER0_SELECT1",
11373   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11374  },
11375  {
11376   "chips": ["gfx10"],
11377   "map": {"at": 222740, "to": "mm"},
11378   "name": "SPI_PERFCOUNTER1_SELECT1",
11379   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11380  },
11381  {
11382   "chips": ["gfx10"],
11383   "map": {"at": 222744, "to": "mm"},
11384   "name": "SPI_PERFCOUNTER2_SELECT1",
11385   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11386  },
11387  {
11388   "chips": ["gfx10"],
11389   "map": {"at": 222748, "to": "mm"},
11390   "name": "SPI_PERFCOUNTER3_SELECT1",
11391   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11392  },
11393  {
11394   "chips": ["gfx10"],
11395   "map": {"at": 222752, "to": "mm"},
11396   "name": "SPI_PERFCOUNTER4_SELECT",
11397   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11398  },
11399  {
11400   "chips": ["gfx10"],
11401   "map": {"at": 222756, "to": "mm"},
11402   "name": "SPI_PERFCOUNTER5_SELECT",
11403   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
11404  },
11405  {
11406   "chips": ["gfx10"],
11407   "map": {"at": 222760, "to": "mm"},
11408   "name": "SPI_PERFCOUNTER_BINS",
11409   "type_ref": "SPI_PERFCOUNTER_BINS"
11410  },
11411  {
11412   "chips": ["gfx10"],
11413   "map": {"at": 222976, "to": "mm"},
11414   "name": "SQ_PERFCOUNTER0_SELECT",
11415   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11416  },
11417  {
11418   "chips": ["gfx10"],
11419   "map": {"at": 222980, "to": "mm"},
11420   "name": "SQ_PERFCOUNTER1_SELECT",
11421   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11422  },
11423  {
11424   "chips": ["gfx10"],
11425   "map": {"at": 222984, "to": "mm"},
11426   "name": "SQ_PERFCOUNTER2_SELECT",
11427   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11428  },
11429  {
11430   "chips": ["gfx10"],
11431   "map": {"at": 222988, "to": "mm"},
11432   "name": "SQ_PERFCOUNTER3_SELECT",
11433   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11434  },
11435  {
11436   "chips": ["gfx10"],
11437   "map": {"at": 222992, "to": "mm"},
11438   "name": "SQ_PERFCOUNTER4_SELECT",
11439   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11440  },
11441  {
11442   "chips": ["gfx10"],
11443   "map": {"at": 222996, "to": "mm"},
11444   "name": "SQ_PERFCOUNTER5_SELECT",
11445   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11446  },
11447  {
11448   "chips": ["gfx10"],
11449   "map": {"at": 223000, "to": "mm"},
11450   "name": "SQ_PERFCOUNTER6_SELECT",
11451   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11452  },
11453  {
11454   "chips": ["gfx10"],
11455   "map": {"at": 223004, "to": "mm"},
11456   "name": "SQ_PERFCOUNTER7_SELECT",
11457   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11458  },
11459  {
11460   "chips": ["gfx10"],
11461   "map": {"at": 223008, "to": "mm"},
11462   "name": "SQ_PERFCOUNTER8_SELECT",
11463   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11464  },
11465  {
11466   "chips": ["gfx10"],
11467   "map": {"at": 223012, "to": "mm"},
11468   "name": "SQ_PERFCOUNTER9_SELECT",
11469   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11470  },
11471  {
11472   "chips": ["gfx10"],
11473   "map": {"at": 223016, "to": "mm"},
11474   "name": "SQ_PERFCOUNTER10_SELECT",
11475   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11476  },
11477  {
11478   "chips": ["gfx10"],
11479   "map": {"at": 223020, "to": "mm"},
11480   "name": "SQ_PERFCOUNTER11_SELECT",
11481   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11482  },
11483  {
11484   "chips": ["gfx10"],
11485   "map": {"at": 223024, "to": "mm"},
11486   "name": "SQ_PERFCOUNTER12_SELECT",
11487   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11488  },
11489  {
11490   "chips": ["gfx10"],
11491   "map": {"at": 223028, "to": "mm"},
11492   "name": "SQ_PERFCOUNTER13_SELECT",
11493   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11494  },
11495  {
11496   "chips": ["gfx10"],
11497   "map": {"at": 223032, "to": "mm"},
11498   "name": "SQ_PERFCOUNTER14_SELECT",
11499   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11500  },
11501  {
11502   "chips": ["gfx10"],
11503   "map": {"at": 223036, "to": "mm"},
11504   "name": "SQ_PERFCOUNTER15_SELECT",
11505   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11506  },
11507  {
11508   "chips": ["gfx10"],
11509   "map": {"at": 223104, "to": "mm"},
11510   "name": "SQ_PERFCOUNTER_CTRL",
11511   "type_ref": "SQ_PERFCOUNTER_CTRL"
11512  },
11513  {
11514   "chips": ["gfx10"],
11515   "map": {"at": 223112, "to": "mm"},
11516   "name": "SQ_PERFCOUNTER_CTRL2",
11517   "type_ref": "SQ_PERFCOUNTER_CTRL2"
11518  },
11519  {
11520   "chips": ["gfx10"],
11521   "map": {"at": 223232, "to": "mm"},
11522   "name": "GCEA_PERFCOUNTER2_SELECT",
11523   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11524  },
11525  {
11526   "chips": ["gfx10"],
11527   "map": {"at": 223236, "to": "mm"},
11528   "name": "GCEA_PERFCOUNTER2_SELECT1",
11529   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11530  },
11531  {
11532   "chips": ["gfx10"],
11533   "map": {"at": 223240, "to": "mm"},
11534   "name": "GCEA_PERFCOUNTER2_MODE",
11535   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11536  },
11537  {
11538   "chips": ["gfx10"],
11539   "map": {"at": 223488, "to": "mm"},
11540   "name": "SX_PERFCOUNTER0_SELECT",
11541   "type_ref": "SX_PERFCOUNTER0_SELECT"
11542  },
11543  {
11544   "chips": ["gfx10"],
11545   "map": {"at": 223492, "to": "mm"},
11546   "name": "SX_PERFCOUNTER1_SELECT",
11547   "type_ref": "SX_PERFCOUNTER0_SELECT"
11548  },
11549  {
11550   "chips": ["gfx10"],
11551   "map": {"at": 223496, "to": "mm"},
11552   "name": "SX_PERFCOUNTER2_SELECT",
11553   "type_ref": "SX_PERFCOUNTER0_SELECT"
11554  },
11555  {
11556   "chips": ["gfx10"],
11557   "map": {"at": 223500, "to": "mm"},
11558   "name": "SX_PERFCOUNTER3_SELECT",
11559   "type_ref": "SX_PERFCOUNTER0_SELECT"
11560  },
11561  {
11562   "chips": ["gfx10"],
11563   "map": {"at": 223504, "to": "mm"},
11564   "name": "SX_PERFCOUNTER0_SELECT1",
11565   "type_ref": "SX_PERFCOUNTER0_SELECT1"
11566  },
11567  {
11568   "chips": ["gfx10"],
11569   "map": {"at": 223508, "to": "mm"},
11570   "name": "SX_PERFCOUNTER1_SELECT1",
11571   "type_ref": "SX_PERFCOUNTER0_SELECT1"
11572  },
11573  {
11574   "chips": ["gfx10"],
11575   "map": {"at": 223744, "to": "mm"},
11576   "name": "GDS_PERFCOUNTER0_SELECT",
11577   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11578  },
11579  {
11580   "chips": ["gfx10"],
11581   "map": {"at": 223748, "to": "mm"},
11582   "name": "GDS_PERFCOUNTER1_SELECT",
11583   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11584  },
11585  {
11586   "chips": ["gfx10"],
11587   "map": {"at": 223752, "to": "mm"},
11588   "name": "GDS_PERFCOUNTER2_SELECT",
11589   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11590  },
11591  {
11592   "chips": ["gfx10"],
11593   "map": {"at": 223756, "to": "mm"},
11594   "name": "GDS_PERFCOUNTER3_SELECT",
11595   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11596  },
11597  {
11598   "chips": ["gfx10"],
11599   "map": {"at": 223760, "to": "mm"},
11600   "name": "GDS_PERFCOUNTER0_SELECT1",
11601   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11602  },
11603  {
11604   "chips": ["gfx10"],
11605   "map": {"at": 224000, "to": "mm"},
11606   "name": "TA_PERFCOUNTER0_SELECT",
11607   "type_ref": "TA_PERFCOUNTER0_SELECT"
11608  },
11609  {
11610   "chips": ["gfx10"],
11611   "map": {"at": 224004, "to": "mm"},
11612   "name": "TA_PERFCOUNTER0_SELECT1",
11613   "type_ref": "TA_PERFCOUNTER0_SELECT1"
11614  },
11615  {
11616   "chips": ["gfx10"],
11617   "map": {"at": 224008, "to": "mm"},
11618   "name": "TA_PERFCOUNTER1_SELECT",
11619   "type_ref": "TA_PERFCOUNTER1_SELECT"
11620  },
11621  {
11622   "chips": ["gfx10"],
11623   "map": {"at": 224256, "to": "mm"},
11624   "name": "TD_PERFCOUNTER0_SELECT",
11625   "type_ref": "TA_PERFCOUNTER0_SELECT"
11626  },
11627  {
11628   "chips": ["gfx10"],
11629   "map": {"at": 224260, "to": "mm"},
11630   "name": "TD_PERFCOUNTER0_SELECT1",
11631   "type_ref": "TA_PERFCOUNTER0_SELECT1"
11632  },
11633  {
11634   "chips": ["gfx10"],
11635   "map": {"at": 224264, "to": "mm"},
11636   "name": "TD_PERFCOUNTER1_SELECT",
11637   "type_ref": "TA_PERFCOUNTER1_SELECT"
11638  },
11639  {
11640   "chips": ["gfx10"],
11641   "map": {"at": 224512, "to": "mm"},
11642   "name": "TCP_PERFCOUNTER0_SELECT",
11643   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11644  },
11645  {
11646   "chips": ["gfx10"],
11647   "map": {"at": 224516, "to": "mm"},
11648   "name": "TCP_PERFCOUNTER0_SELECT1",
11649   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11650  },
11651  {
11652   "chips": ["gfx10"],
11653   "map": {"at": 224520, "to": "mm"},
11654   "name": "TCP_PERFCOUNTER1_SELECT",
11655   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11656  },
11657  {
11658   "chips": ["gfx10"],
11659   "map": {"at": 224524, "to": "mm"},
11660   "name": "TCP_PERFCOUNTER1_SELECT1",
11661   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11662  },
11663  {
11664   "chips": ["gfx10"],
11665   "map": {"at": 224528, "to": "mm"},
11666   "name": "TCP_PERFCOUNTER2_SELECT",
11667   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11668  },
11669  {
11670   "chips": ["gfx10"],
11671   "map": {"at": 224532, "to": "mm"},
11672   "name": "TCP_PERFCOUNTER3_SELECT",
11673   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11674  },
11675  {
11676   "chips": ["gfx10"],
11677   "map": {"at": 224768, "to": "mm"},
11678   "name": "GL2C_PERFCOUNTER0_SELECT",
11679   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11680  },
11681  {
11682   "chips": ["gfx10"],
11683   "map": {"at": 224772, "to": "mm"},
11684   "name": "GL2C_PERFCOUNTER0_SELECT1",
11685   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11686  },
11687  {
11688   "chips": ["gfx10"],
11689   "map": {"at": 224776, "to": "mm"},
11690   "name": "GL2C_PERFCOUNTER1_SELECT",
11691   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11692  },
11693  {
11694   "chips": ["gfx10"],
11695   "map": {"at": 224780, "to": "mm"},
11696   "name": "GL2C_PERFCOUNTER1_SELECT1",
11697   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11698  },
11699  {
11700   "chips": ["gfx10"],
11701   "map": {"at": 224784, "to": "mm"},
11702   "name": "GL2C_PERFCOUNTER2_SELECT",
11703   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11704  },
11705  {
11706   "chips": ["gfx10"],
11707   "map": {"at": 224788, "to": "mm"},
11708   "name": "GL2C_PERFCOUNTER3_SELECT",
11709   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11710  },
11711  {
11712   "chips": ["gfx10"],
11713   "map": {"at": 224832, "to": "mm"},
11714   "name": "GL2A_PERFCOUNTER0_SELECT",
11715   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11716  },
11717  {
11718   "chips": ["gfx10"],
11719   "map": {"at": 224836, "to": "mm"},
11720   "name": "GL2A_PERFCOUNTER0_SELECT1",
11721   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11722  },
11723  {
11724   "chips": ["gfx10"],
11725   "map": {"at": 224840, "to": "mm"},
11726   "name": "GL2A_PERFCOUNTER1_SELECT",
11727   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11728  },
11729  {
11730   "chips": ["gfx10"],
11731   "map": {"at": 224844, "to": "mm"},
11732   "name": "GL2A_PERFCOUNTER1_SELECT1",
11733   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11734  },
11735  {
11736   "chips": ["gfx10"],
11737   "map": {"at": 224848, "to": "mm"},
11738   "name": "GL2A_PERFCOUNTER2_SELECT",
11739   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11740  },
11741  {
11742   "chips": ["gfx10"],
11743   "map": {"at": 224852, "to": "mm"},
11744   "name": "GL2A_PERFCOUNTER3_SELECT",
11745   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11746  },
11747  {
11748   "chips": ["gfx10"],
11749   "map": {"at": 224896, "to": "mm"},
11750   "name": "GL1C_PERFCOUNTER0_SELECT",
11751   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11752  },
11753  {
11754   "chips": ["gfx10"],
11755   "map": {"at": 224900, "to": "mm"},
11756   "name": "GL1C_PERFCOUNTER0_SELECT1",
11757   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11758  },
11759  {
11760   "chips": ["gfx10"],
11761   "map": {"at": 224904, "to": "mm"},
11762   "name": "GL1C_PERFCOUNTER1_SELECT",
11763   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11764  },
11765  {
11766   "chips": ["gfx10"],
11767   "map": {"at": 224908, "to": "mm"},
11768   "name": "GL1C_PERFCOUNTER2_SELECT",
11769   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11770  },
11771  {
11772   "chips": ["gfx10"],
11773   "map": {"at": 224912, "to": "mm"},
11774   "name": "GL1C_PERFCOUNTER3_SELECT",
11775   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11776  },
11777  {
11778   "chips": ["gfx10"],
11779   "map": {"at": 225024, "to": "mm"},
11780   "name": "CHC_PERFCOUNTER0_SELECT",
11781   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11782  },
11783  {
11784   "chips": ["gfx10"],
11785   "map": {"at": 225028, "to": "mm"},
11786   "name": "CHC_PERFCOUNTER0_SELECT1",
11787   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11788  },
11789  {
11790   "chips": ["gfx10"],
11791   "map": {"at": 225032, "to": "mm"},
11792   "name": "CHC_PERFCOUNTER1_SELECT",
11793   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11794  },
11795  {
11796   "chips": ["gfx10"],
11797   "map": {"at": 225036, "to": "mm"},
11798   "name": "CHC_PERFCOUNTER2_SELECT",
11799   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11800  },
11801  {
11802   "chips": ["gfx10"],
11803   "map": {"at": 225040, "to": "mm"},
11804   "name": "CHC_PERFCOUNTER3_SELECT",
11805   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11806  },
11807  {
11808   "chips": ["gfx10"],
11809   "map": {"at": 225048, "to": "mm"},
11810   "name": "CHCG_PERFCOUNTER0_SELECT",
11811   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11812  },
11813  {
11814   "chips": ["gfx10"],
11815   "map": {"at": 225052, "to": "mm"},
11816   "name": "CHCG_PERFCOUNTER0_SELECT1",
11817   "type_ref": "GE_PERFCOUNTER0_SELECT1"
11818  },
11819  {
11820   "chips": ["gfx10"],
11821   "map": {"at": 225056, "to": "mm"},
11822   "name": "CHCG_PERFCOUNTER1_SELECT",
11823   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11824  },
11825  {
11826   "chips": ["gfx10"],
11827   "map": {"at": 225060, "to": "mm"},
11828   "name": "CHCG_PERFCOUNTER2_SELECT",
11829   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11830  },
11831  {
11832   "chips": ["gfx10"],
11833   "map": {"at": 225064, "to": "mm"},
11834   "name": "CHCG_PERFCOUNTER3_SELECT",
11835   "type_ref": "TCP_PERFCOUNTER2_SELECT"
11836  },
11837  {
11838   "chips": ["gfx10"],
11839   "map": {"at": 225280, "to": "mm"},
11840   "name": "CB_PERFCOUNTER_FILTER",
11841   "type_ref": "CB_PERFCOUNTER_FILTER"
11842  },
11843  {
11844   "chips": ["gfx10"],
11845   "map": {"at": 225284, "to": "mm"},
11846   "name": "CB_PERFCOUNTER0_SELECT",
11847   "type_ref": "CB_PERFCOUNTER0_SELECT"
11848  },
11849  {
11850   "chips": ["gfx10"],
11851   "map": {"at": 225288, "to": "mm"},
11852   "name": "CB_PERFCOUNTER0_SELECT1",
11853   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11854  },
11855  {
11856   "chips": ["gfx10"],
11857   "map": {"at": 225292, "to": "mm"},
11858   "name": "CB_PERFCOUNTER1_SELECT",
11859   "type_ref": "CB_PERFCOUNTER1_SELECT"
11860  },
11861  {
11862   "chips": ["gfx10"],
11863   "map": {"at": 225296, "to": "mm"},
11864   "name": "CB_PERFCOUNTER2_SELECT",
11865   "type_ref": "CB_PERFCOUNTER1_SELECT"
11866  },
11867  {
11868   "chips": ["gfx10"],
11869   "map": {"at": 225300, "to": "mm"},
11870   "name": "CB_PERFCOUNTER3_SELECT",
11871   "type_ref": "CB_PERFCOUNTER1_SELECT"
11872  },
11873  {
11874   "chips": ["gfx10"],
11875   "map": {"at": 225536, "to": "mm"},
11876   "name": "DB_PERFCOUNTER0_SELECT",
11877   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11878  },
11879  {
11880   "chips": ["gfx10"],
11881   "map": {"at": 225540, "to": "mm"},
11882   "name": "DB_PERFCOUNTER0_SELECT1",
11883   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11884  },
11885  {
11886   "chips": ["gfx10"],
11887   "map": {"at": 225544, "to": "mm"},
11888   "name": "DB_PERFCOUNTER1_SELECT",
11889   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11890  },
11891  {
11892   "chips": ["gfx10"],
11893   "map": {"at": 225548, "to": "mm"},
11894   "name": "DB_PERFCOUNTER1_SELECT1",
11895   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11896  },
11897  {
11898   "chips": ["gfx10"],
11899   "map": {"at": 225552, "to": "mm"},
11900   "name": "DB_PERFCOUNTER2_SELECT",
11901   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11902  },
11903  {
11904   "chips": ["gfx10"],
11905   "map": {"at": 225560, "to": "mm"},
11906   "name": "DB_PERFCOUNTER3_SELECT",
11907   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11908  },
11909  {
11910   "chips": ["gfx10"],
11911   "map": {"at": 225792, "to": "mm"},
11912   "name": "RLC_SPM_PERFMON_CNTL",
11913   "type_ref": "RLC_SPM_PERFMON_CNTL"
11914  },
11915  {
11916   "chips": ["gfx10"],
11917   "map": {"at": 225796, "to": "mm"},
11918   "name": "RLC_SPM_PERFMON_RING_BASE_LO",
11919   "type_ref": "RLC_SPM_PERFMON_RING_BASE_LO"
11920  },
11921  {
11922   "chips": ["gfx10"],
11923   "map": {"at": 225800, "to": "mm"},
11924   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
11925   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
11926  },
11927  {
11928   "chips": ["gfx10"],
11929   "map": {"at": 225804, "to": "mm"},
11930   "name": "RLC_SPM_PERFMON_RING_SIZE",
11931   "type_ref": "RLC_SPM_PERFMON_RING_SIZE"
11932  },
11933  {
11934   "chips": ["gfx10"],
11935   "map": {"at": 225808, "to": "mm"},
11936   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
11937   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
11938  },
11939  {
11940   "chips": ["gfx10"],
11941   "map": {"at": 225812, "to": "mm"},
11942   "name": "RLC_SPM_RING_RDPTR",
11943   "type_ref": "RLC_SPM_RING_RDPTR"
11944  },
11945  {
11946   "chips": ["gfx10"],
11947   "map": {"at": 225816, "to": "mm"},
11948   "name": "RLC_SPM_SEGMENT_THRESHOLD",
11949   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
11950  },
11951  {
11952   "chips": ["gfx10"],
11953   "map": {"at": 225820, "to": "mm"},
11954   "name": "RLC_SPM_SE_MUXSEL_ADDR",
11955   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
11956  },
11957  {
11958   "chips": ["gfx10"],
11959   "map": {"at": 225824, "to": "mm"},
11960   "name": "RLC_SPM_SE_MUXSEL_DATA",
11961   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11962  },
11963  {
11964   "chips": ["gfx10"],
11965   "map": {"at": 225828, "to": "mm"},
11966   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
11967   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
11968  },
11969  {
11970   "chips": ["gfx10"],
11971   "map": {"at": 225832, "to": "mm"},
11972   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA",
11973   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11974  },
11975  {
11976   "chips": ["gfx10"],
11977   "map": {"at": 225836, "to": "mm"},
11978   "name": "RLC_SPM_DESER_START_SKEW",
11979   "type_ref": "RLC_SPM_DESER_START_SKEW"
11980  },
11981  {
11982   "chips": ["gfx10"],
11983   "map": {"at": 225840, "to": "mm"},
11984   "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
11985   "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
11986  },
11987  {
11988   "chips": ["gfx10"],
11989   "map": {"at": 225844, "to": "mm"},
11990   "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
11991   "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
11992  },
11993  {
11994   "chips": ["gfx10"],
11995   "map": {"at": 225848, "to": "mm"},
11996   "name": "RLC_SPM_SE_SAMPLE_SKEW",
11997   "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
11998  },
11999  {
12000   "chips": ["gfx10"],
12001   "map": {"at": 225852, "to": "mm"},
12002   "name": "RLC_SPM_SE_MUXSEL_SKEW",
12003   "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
12004  },
12005  {
12006   "chips": ["gfx10"],
12007   "map": {"at": 225856, "to": "mm"},
12008   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR",
12009   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
12010  },
12011  {
12012   "chips": ["gfx10"],
12013   "map": {"at": 225860, "to": "mm"},
12014   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
12015   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
12016  },
12017  {
12018   "chips": ["gfx10"],
12019   "map": {"at": 225864, "to": "mm"},
12020   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR",
12021   "type_ref": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
12022  },
12023  {
12024   "chips": ["gfx10"],
12025   "map": {"at": 225868, "to": "mm"},
12026   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
12027   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
12028  },
12029  {
12030   "chips": ["gfx10"],
12031   "map": {"at": 225872, "to": "mm"},
12032   "name": "RLC_SPM_RING_WRPTR",
12033   "type_ref": "RLC_SPM_RING_WRPTR"
12034  },
12035  {
12036   "chips": ["gfx10"],
12037   "map": {"at": 225876, "to": "mm"},
12038   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
12039   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
12040  },
12041  {
12042   "chips": ["gfx10"],
12043   "map": {"at": 225880, "to": "mm"},
12044   "name": "RLC_SPM_ACCUM_DATARAM_DATA",
12045   "type_ref": "RLC_SPM_ACCUM_DATARAM_DATA"
12046  },
12047  {
12048   "chips": ["gfx10"],
12049   "map": {"at": 225884, "to": "mm"},
12050   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
12051   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
12052  },
12053  {
12054   "chips": ["gfx10"],
12055   "map": {"at": 225888, "to": "mm"},
12056   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
12057   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
12058  },
12059  {
12060   "chips": ["gfx10"],
12061   "map": {"at": 225892, "to": "mm"},
12062   "name": "RLC_SPM_ACCUM_STATUS",
12063   "type_ref": "RLC_SPM_ACCUM_STATUS"
12064  },
12065  {
12066   "chips": ["gfx10"],
12067   "map": {"at": 225896, "to": "mm"},
12068   "name": "RLC_SPM_ACCUM_CTRL",
12069   "type_ref": "RLC_SPM_ACCUM_CTRL"
12070  },
12071  {
12072   "chips": ["gfx10"],
12073   "map": {"at": 225900, "to": "mm"},
12074   "name": "RLC_SPM_ACCUM_MODE",
12075   "type_ref": "RLC_SPM_ACCUM_MODE"
12076  },
12077  {
12078   "chips": ["gfx10"],
12079   "map": {"at": 225904, "to": "mm"},
12080   "name": "RLC_SPM_ACCUM_THRESHOLD",
12081   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
12082  },
12083  {
12084   "chips": ["gfx10"],
12085   "map": {"at": 225908, "to": "mm"},
12086   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
12087   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
12088  },
12089  {
12090   "chips": ["gfx10"],
12091   "map": {"at": 225912, "to": "mm"},
12092   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
12093   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
12094  },
12095  {
12096   "chips": ["gfx10"],
12097   "map": {"at": 225916, "to": "mm"},
12098   "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
12099   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
12100  },
12101  {
12102   "chips": ["gfx10"],
12103   "map": {"at": 225920, "to": "mm"},
12104   "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
12105   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
12106  },
12107  {
12108   "chips": ["gfx10"],
12109   "map": {"at": 225924, "to": "mm"},
12110   "name": "RLC_SPM_VIRT_CTRL",
12111   "type_ref": "RLC_SPM_VIRT_CTRL"
12112  },
12113  {
12114   "chips": ["gfx10"],
12115   "map": {"at": 225932, "to": "mm"},
12116   "name": "RLC_SPM_VIRT_STATUS",
12117   "type_ref": "RLC_SPM_VIRT_STATUS"
12118  },
12119  {
12120   "chips": ["gfx10"],
12121   "map": {"at": 226048, "to": "mm"},
12122   "name": "RLC_PERFMON_CNTL",
12123   "type_ref": "RLC_PERFMON_CNTL"
12124  },
12125  {
12126   "chips": ["gfx10"],
12127   "map": {"at": 226052, "to": "mm"},
12128   "name": "RLC_PERFCOUNTER0_SELECT",
12129   "type_ref": "RLC_PERFCOUNTER0_SELECT"
12130  },
12131  {
12132   "chips": ["gfx10"],
12133   "map": {"at": 226056, "to": "mm"},
12134   "name": "RLC_PERFCOUNTER1_SELECT",
12135   "type_ref": "RLC_PERFCOUNTER0_SELECT"
12136  },
12137  {
12138   "chips": ["gfx10"],
12139   "map": {"at": 226060, "to": "mm"},
12140   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
12141   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
12142  },
12143  {
12144   "chips": ["gfx10"],
12145   "map": {"at": 226064, "to": "mm"},
12146   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
12147   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
12148  },
12149  {
12150   "chips": ["gfx10"],
12151   "map": {"at": 226068, "to": "mm"},
12152   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA",
12153   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
12154  },
12155  {
12156   "chips": ["gfx10"],
12157   "map": {"at": 226072, "to": "mm"},
12158   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
12159   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
12160  },
12161  {
12162   "chips": ["gfx10"],
12163   "map": {"at": 226076, "to": "mm"},
12164   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA",
12165   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
12166  },
12167  {
12168   "chips": ["gfx10"],
12169   "map": {"at": 226192, "to": "mm"},
12170   "name": "RLC_PERFMON_CLK_CNTL",
12171   "type_ref": "RLC_PERFMON_CLK_CNTL"
12172  },
12173  {
12174   "chips": ["gfx10"],
12175   "map": {"at": 226196, "to": "mm"},
12176   "name": "RLC_PERFMON_CLK_CNTL_UCODE",
12177   "type_ref": "RLC_PERFMON_CLK_CNTL"
12178  },
12179  {
12180   "chips": ["gfx10"],
12181   "map": {"at": 226304, "to": "mm"},
12182   "name": "RMI_PERFCOUNTER0_SELECT",
12183   "type_ref": "CB_PERFCOUNTER0_SELECT"
12184  },
12185  {
12186   "chips": ["gfx10"],
12187   "map": {"at": 226308, "to": "mm"},
12188   "name": "RMI_PERFCOUNTER0_SELECT1",
12189   "type_ref": "CB_PERFCOUNTER0_SELECT1"
12190  },
12191  {
12192   "chips": ["gfx10"],
12193   "map": {"at": 226312, "to": "mm"},
12194   "name": "RMI_PERFCOUNTER1_SELECT",
12195   "type_ref": "CB_PERFCOUNTER1_SELECT"
12196  },
12197  {
12198   "chips": ["gfx10"],
12199   "map": {"at": 226316, "to": "mm"},
12200   "name": "RMI_PERFCOUNTER2_SELECT",
12201   "type_ref": "CB_PERFCOUNTER0_SELECT"
12202  },
12203  {
12204   "chips": ["gfx10"],
12205   "map": {"at": 226320, "to": "mm"},
12206   "name": "RMI_PERFCOUNTER2_SELECT1",
12207   "type_ref": "CB_PERFCOUNTER0_SELECT1"
12208  },
12209  {
12210   "chips": ["gfx10"],
12211   "map": {"at": 226324, "to": "mm"},
12212   "name": "RMI_PERFCOUNTER3_SELECT",
12213   "type_ref": "CB_PERFCOUNTER1_SELECT"
12214  },
12215  {
12216   "chips": ["gfx10"],
12217   "map": {"at": 226328, "to": "mm"},
12218   "name": "RMI_PERF_COUNTER_CNTL",
12219   "type_ref": "RMI_PERF_COUNTER_CNTL"
12220  },
12221  {
12222   "chips": ["gfx10"],
12223   "map": {"at": 226432, "to": "mm"},
12224   "name": "GC_ATC_L2_PERFCOUNTER0_CFG",
12225   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12226  },
12227  {
12228   "chips": ["gfx10"],
12229   "map": {"at": 226436, "to": "mm"},
12230   "name": "GC_ATC_L2_PERFCOUNTER1_CFG",
12231   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12232  },
12233  {
12234   "chips": ["gfx10"],
12235   "map": {"at": 226440, "to": "mm"},
12236   "name": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL",
12237   "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
12238  },
12239  {
12240   "chips": ["gfx10"],
12241   "map": {"at": 226480, "to": "mm"},
12242   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
12243   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12244  },
12245  {
12246   "chips": ["gfx10"],
12247   "map": {"at": 226484, "to": "mm"},
12248   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
12249   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12250  },
12251  {
12252   "chips": ["gfx10"],
12253   "map": {"at": 226488, "to": "mm"},
12254   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
12255   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12256  },
12257  {
12258   "chips": ["gfx10"],
12259   "map": {"at": 226492, "to": "mm"},
12260   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
12261   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12262  },
12263  {
12264   "chips": ["gfx10"],
12265   "map": {"at": 226496, "to": "mm"},
12266   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
12267   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12268  },
12269  {
12270   "chips": ["gfx10"],
12271   "map": {"at": 226500, "to": "mm"},
12272   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
12273   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12274  },
12275  {
12276   "chips": ["gfx10"],
12277   "map": {"at": 226504, "to": "mm"},
12278   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
12279   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12280  },
12281  {
12282   "chips": ["gfx10"],
12283   "map": {"at": 226508, "to": "mm"},
12284   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
12285   "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG"
12286  },
12287  {
12288   "chips": ["gfx10"],
12289   "map": {"at": 226512, "to": "mm"},
12290   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
12291   "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL"
12292  },
12293  {
12294   "chips": ["gfx10"],
12295   "map": {"at": 226544, "to": "mm"},
12296   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
12297   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12298  },
12299  {
12300   "chips": ["gfx10"],
12301   "map": {"at": 226548, "to": "mm"},
12302   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
12303   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12304  },
12305  {
12306   "chips": ["gfx10"],
12307   "map": {"at": 226552, "to": "mm"},
12308   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
12309   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12310  },
12311  {
12312   "chips": ["gfx10"],
12313   "map": {"at": 226556, "to": "mm"},
12314   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
12315   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12316  },
12317  {
12318   "chips": ["gfx10"],
12319   "map": {"at": 226560, "to": "mm"},
12320   "name": "GCVML2_PERFCOUNTER2_0_MODE",
12321   "type_ref": "GCEA_PERFCOUNTER2_MODE"
12322  },
12323  {
12324   "chips": ["gfx10"],
12325   "map": {"at": 226564, "to": "mm"},
12326   "name": "GCVML2_PERFCOUNTER2_1_MODE",
12327   "type_ref": "GCEA_PERFCOUNTER2_MODE"
12328  },
12329  {
12330   "chips": ["gfx10"],
12331   "map": {"at": 226608, "to": "mm"},
12332   "name": "GC_ATC_L2_PERFCOUNTER2_SELECT",
12333   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12334  },
12335  {
12336   "chips": ["gfx10"],
12337   "map": {"at": 226612, "to": "mm"},
12338   "name": "GC_ATC_L2_PERFCOUNTER2_SELECT1",
12339   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12340  },
12341  {
12342   "chips": ["gfx10"],
12343   "map": {"at": 226616, "to": "mm"},
12344   "name": "GC_ATC_L2_PERFCOUNTER2_MODE",
12345   "type_ref": "GCEA_PERFCOUNTER2_MODE"
12346  },
12347  {
12348   "chips": ["gfx10"],
12349   "map": {"at": 226688, "to": "mm"},
12350   "name": "GCR_PERFCOUNTER0_SELECT",
12351   "type_ref": "CB_PERFCOUNTER0_SELECT"
12352  },
12353  {
12354   "chips": ["gfx10"],
12355   "map": {"at": 226692, "to": "mm"},
12356   "name": "GCR_PERFCOUNTER0_SELECT1",
12357   "type_ref": "CB_PERFCOUNTER0_SELECT1"
12358  },
12359  {
12360   "chips": ["gfx10"],
12361   "map": {"at": 226696, "to": "mm"},
12362   "name": "GCR_PERFCOUNTER1_SELECT",
12363   "type_ref": "GCR_PERFCOUNTER1_SELECT"
12364  },
12365  {
12366   "chips": ["gfx10"],
12367   "map": {"at": 226700, "to": "mm"},
12368   "name": "UTCL1_PERFCOUNTER0_SELECT",
12369   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12370  },
12371  {
12372   "chips": ["gfx10"],
12373   "map": {"at": 226704, "to": "mm"},
12374   "name": "UTCL1_PERFCOUNTER1_SELECT",
12375   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12376  },
12377  {
12378   "chips": ["gfx10"],
12379   "map": {"at": 226816, "to": "mm"},
12380   "name": "PA_PH_PERFCOUNTER0_SELECT",
12381   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12382  },
12383  {
12384   "chips": ["gfx10"],
12385   "map": {"at": 226820, "to": "mm"},
12386   "name": "PA_PH_PERFCOUNTER0_SELECT1",
12387   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12388  },
12389  {
12390   "chips": ["gfx10"],
12391   "map": {"at": 226824, "to": "mm"},
12392   "name": "PA_PH_PERFCOUNTER1_SELECT",
12393   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12394  },
12395  {
12396   "chips": ["gfx10"],
12397   "map": {"at": 226828, "to": "mm"},
12398   "name": "PA_PH_PERFCOUNTER2_SELECT",
12399   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12400  },
12401  {
12402   "chips": ["gfx10"],
12403   "map": {"at": 226832, "to": "mm"},
12404   "name": "PA_PH_PERFCOUNTER3_SELECT",
12405   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12406  },
12407  {
12408   "chips": ["gfx10"],
12409   "map": {"at": 226836, "to": "mm"},
12410   "name": "PA_PH_PERFCOUNTER4_SELECT",
12411   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12412  },
12413  {
12414   "chips": ["gfx10"],
12415   "map": {"at": 226840, "to": "mm"},
12416   "name": "PA_PH_PERFCOUNTER5_SELECT",
12417   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12418  },
12419  {
12420   "chips": ["gfx10"],
12421   "map": {"at": 226844, "to": "mm"},
12422   "name": "PA_PH_PERFCOUNTER6_SELECT",
12423   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12424  },
12425  {
12426   "chips": ["gfx10"],
12427   "map": {"at": 226848, "to": "mm"},
12428   "name": "PA_PH_PERFCOUNTER7_SELECT",
12429   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12430  },
12431  {
12432   "chips": ["gfx10"],
12433   "map": {"at": 226880, "to": "mm"},
12434   "name": "PA_PH_PERFCOUNTER1_SELECT1",
12435   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12436  },
12437  {
12438   "chips": ["gfx10"],
12439   "map": {"at": 226884, "to": "mm"},
12440   "name": "PA_PH_PERFCOUNTER2_SELECT1",
12441   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12442  },
12443  {
12444   "chips": ["gfx10"],
12445   "map": {"at": 226888, "to": "mm"},
12446   "name": "PA_PH_PERFCOUNTER3_SELECT1",
12447   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12448  },
12449  {
12450   "chips": ["gfx10"],
12451   "map": {"at": 227072, "to": "mm"},
12452   "name": "GL1A_PERFCOUNTER0_SELECT",
12453   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12454  },
12455  {
12456   "chips": ["gfx10"],
12457   "map": {"at": 227076, "to": "mm"},
12458   "name": "GL1A_PERFCOUNTER0_SELECT1",
12459   "type_ref": "GE_PERFCOUNTER0_SELECT1"
12460  },
12461  {
12462   "chips": ["gfx10"],
12463   "map": {"at": 227080, "to": "mm"},
12464   "name": "GL1A_PERFCOUNTER1_SELECT",
12465   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12466  },
12467  {
12468   "chips": ["gfx10"],
12469   "map": {"at": 227084, "to": "mm"},
12470   "name": "GL1A_PERFCOUNTER2_SELECT",
12471   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12472  },
12473  {
12474   "chips": ["gfx10"],
12475   "map": {"at": 227088, "to": "mm"},
12476   "name": "GL1A_PERFCOUNTER3_SELECT",
12477   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12478  },
12479  {
12480   "chips": ["gfx10"],
12481   "map": {"at": 227200, "to": "mm"},
12482   "name": "CHA_PERFCOUNTER0_SELECT",
12483   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12484  },
12485  {
12486   "chips": ["gfx10"],
12487   "map": {"at": 227204, "to": "mm"},
12488   "name": "CHA_PERFCOUNTER0_SELECT1",
12489   "type_ref": "GE_PERFCOUNTER0_SELECT1"
12490  },
12491  {
12492   "chips": ["gfx10"],
12493   "map": {"at": 227208, "to": "mm"},
12494   "name": "CHA_PERFCOUNTER1_SELECT",
12495   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12496  },
12497  {
12498   "chips": ["gfx10"],
12499   "map": {"at": 227212, "to": "mm"},
12500   "name": "CHA_PERFCOUNTER2_SELECT",
12501   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12502  },
12503  {
12504   "chips": ["gfx10"],
12505   "map": {"at": 227216, "to": "mm"},
12506   "name": "CHA_PERFCOUNTER3_SELECT",
12507   "type_ref": "TCP_PERFCOUNTER2_SELECT"
12508  },
12509  {
12510   "chips": ["gfx10"],
12511   "map": {"at": 227328, "to": "mm"},
12512   "name": "GUS_PERFCOUNTER2_SELECT",
12513   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12514  },
12515  {
12516   "chips": ["gfx10"],
12517   "map": {"at": 227332, "to": "mm"},
12518   "name": "GUS_PERFCOUNTER2_SELECT1",
12519   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12520  },
12521  {
12522   "chips": ["gfx10"],
12523   "map": {"at": 227336, "to": "mm"},
12524   "name": "GUS_PERFCOUNTER2_MODE",
12525   "type_ref": "GCEA_PERFCOUNTER2_MODE"
12526  }
12527 ],
12528 "register_types": {
12529  "CB_BLEND0_CONTROL": {
12530   "fields": [
12531    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
12532    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
12533    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
12534    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
12535    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
12536    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
12537    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
12538    {"bits": [30, 30], "name": "ENABLE"},
12539    {"bits": [31, 31], "name": "DISABLE_ROP3"}
12540   ]
12541  },
12542  "CB_BLEND_ALPHA": {
12543   "fields": [
12544    {"bits": [0, 31], "name": "BLEND_ALPHA"}
12545   ]
12546  },
12547  "CB_BLEND_BLUE": {
12548   "fields": [
12549    {"bits": [0, 31], "name": "BLEND_BLUE"}
12550   ]
12551  },
12552  "CB_BLEND_GREEN": {
12553   "fields": [
12554    {"bits": [0, 31], "name": "BLEND_GREEN"}
12555   ]
12556  },
12557  "CB_BLEND_RED": {
12558   "fields": [
12559    {"bits": [0, 31], "name": "BLEND_RED"}
12560   ]
12561  },
12562  "CB_COLOR0_ATTRIB": {
12563   "fields": [
12564    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
12565    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
12566    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
12567    {"bits": [12, 14], "name": "NUM_SAMPLES"},
12568    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
12569    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
12570    {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
12571    {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
12572   ]
12573  },
12574  "CB_COLOR0_ATTRIB2": {
12575   "fields": [
12576    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
12577    {"bits": [14, 27], "name": "MIP0_WIDTH"},
12578    {"bits": [28, 31], "name": "MAX_MIP"}
12579   ]
12580  },
12581  "CB_COLOR0_ATTRIB3": {
12582   "fields": [
12583    {"bits": [0, 12], "name": "MIP0_DEPTH"},
12584    {"bits": [13, 13], "name": "META_LINEAR"},
12585    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
12586    {"bits": [19, 23], "name": "FMASK_SW_MODE"},
12587    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
12588    {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
12589    {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
12590    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}
12591   ]
12592  },
12593  "CB_COLOR0_BASE_EXT": {
12594   "fields": [
12595    {"bits": [0, 7], "name": "BASE_256B"}
12596   ]
12597  },
12598  "CB_COLOR0_CLEAR_WORD0": {
12599   "fields": [
12600    {"bits": [0, 31], "name": "CLEAR_WORD0"}
12601   ]
12602  },
12603  "CB_COLOR0_CLEAR_WORD1": {
12604   "fields": [
12605    {"bits": [0, 31], "name": "CLEAR_WORD1"}
12606   ]
12607  },
12608  "CB_COLOR0_CMASK_SLICE": {
12609   "fields": [
12610    {"bits": [0, 13], "name": "TILE_MAX"}
12611   ]
12612  },
12613  "CB_COLOR0_DCC_CONTROL": {
12614   "fields": [
12615    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12616    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
12617    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
12618    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
12619    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
12620    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
12621    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
12622    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
12623    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
12624    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12625    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
12626    {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"}
12627   ]
12628  },
12629  "CB_COLOR0_INFO": {
12630   "fields": [
12631    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
12632    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
12633    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
12634    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
12635    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
12636    {"bits": [13, 13], "name": "FAST_CLEAR"},
12637    {"bits": [14, 14], "name": "COMPRESSION"},
12638    {"bits": [15, 15], "name": "BLEND_CLAMP"},
12639    {"bits": [16, 16], "name": "BLEND_BYPASS"},
12640    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
12641    {"bits": [18, 18], "name": "ROUND_MODE"},
12642    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
12643    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
12644    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
12645    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
12646    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
12647    {"bits": [28, 28], "name": "DCC_ENABLE"},
12648    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
12649    {"bits": [31, 31], "name": "ALT_TILE_MODE"}
12650   ]
12651  },
12652  "CB_COLOR0_PITCH": {
12653   "fields": [
12654    {"bits": [0, 10], "name": "TILE_MAX"},
12655    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
12656   ]
12657  },
12658  "CB_COLOR0_SLICE": {
12659   "fields": [
12660    {"bits": [0, 21], "name": "TILE_MAX"}
12661   ]
12662  },
12663  "CB_COLOR0_VIEW": {
12664   "fields": [
12665    {"bits": [0, 12], "name": "SLICE_START"},
12666    {"bits": [13, 25], "name": "SLICE_MAX"},
12667    {"bits": [26, 29], "name": "MIP_LEVEL"}
12668   ]
12669  },
12670  "CB_COLOR_CONTROL": {
12671   "fields": [
12672    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
12673    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
12674    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
12675    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
12676   ]
12677  },
12678  "CB_COVERAGE_OUT_CONTROL": {
12679   "fields": [
12680    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
12681    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
12682    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
12683    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
12684   ]
12685  },
12686  "CB_DCC_CONTROL": {
12687   "fields": [
12688    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12689    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
12690    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
12691    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
12692    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12693    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
12694    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
12695    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
12696   ]
12697  },
12698  "CB_PERFCOUNTER0_SELECT": {
12699   "fields": [
12700    {"bits": [0, 8], "name": "PERF_SEL"},
12701    {"bits": [10, 18], "name": "PERF_SEL1"},
12702    {"bits": [20, 23], "name": "CNTR_MODE"},
12703    {"bits": [24, 27], "name": "PERF_MODE1"},
12704    {"bits": [28, 31], "name": "PERF_MODE"}
12705   ]
12706  },
12707  "CB_PERFCOUNTER0_SELECT1": {
12708   "fields": [
12709    {"bits": [0, 8], "name": "PERF_SEL2"},
12710    {"bits": [10, 18], "name": "PERF_SEL3"},
12711    {"bits": [24, 27], "name": "PERF_MODE3"},
12712    {"bits": [28, 31], "name": "PERF_MODE2"}
12713   ]
12714  },
12715  "CB_PERFCOUNTER1_SELECT": {
12716   "fields": [
12717    {"bits": [0, 8], "name": "PERF_SEL"},
12718    {"bits": [28, 31], "name": "PERF_MODE"}
12719   ]
12720  },
12721  "CB_PERFCOUNTER_FILTER": {
12722   "fields": [
12723    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
12724    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
12725    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
12726    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
12727    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
12728    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
12729    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
12730    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
12731    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
12732    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
12733    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
12734    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
12735   ]
12736  },
12737  "CB_RMI_GL2_CACHE_CONTROL": {
12738   "fields": [
12739    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
12740    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
12741    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
12742    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
12743    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
12744    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
12745    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
12746    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
12747    {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
12748    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
12749   ]
12750  },
12751  "CB_SHADER_MASK": {
12752   "fields": [
12753    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
12754    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
12755    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
12756    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
12757    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
12758    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
12759    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
12760    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
12761   ]
12762  },
12763  "CB_TARGET_MASK": {
12764   "fields": [
12765    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
12766    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
12767    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
12768    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
12769    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
12770    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
12771    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
12772    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
12773   ]
12774  },
12775  "COHER_DEST_BASE_2": {
12776   "fields": [
12777    {"bits": [0, 31], "name": "DEST_BASE_256B"}
12778   ]
12779  },
12780  "COHER_DEST_BASE_HI_0": {
12781   "fields": [
12782    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
12783   ]
12784  },
12785  "COMPUTE_DDID_INDEX": {
12786   "fields": [
12787    {"bits": [0, 10], "name": "INDEX"}
12788   ]
12789  },
12790  "COMPUTE_DESTINATION_EN_SE0": {
12791   "fields": [
12792    {"bits": [0, 31], "name": "CU_EN"}
12793   ]
12794  },
12795  "COMPUTE_DIM_X": {
12796   "fields": [
12797    {"bits": [0, 31], "name": "SIZE"}
12798   ]
12799  },
12800  "COMPUTE_DISPATCH_ID": {
12801   "fields": [
12802    {"bits": [0, 31], "name": "DISPATCH_ID"}
12803   ]
12804  },
12805  "COMPUTE_DISPATCH_INITIATOR": {
12806   "fields": [
12807    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
12808    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
12809    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
12810    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
12811    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
12812    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
12813    {"bits": [6, 6], "name": "ORDER_MODE"},
12814    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
12815    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
12816    {"bits": [12, 12], "name": "RESERVED"},
12817    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
12818    {"bits": [14, 14], "name": "RESTORE"},
12819    {"bits": [15, 15], "name": "CS_W32_EN"}
12820   ]
12821  },
12822  "COMPUTE_DISPATCH_TUNNEL": {
12823   "fields": [
12824    {"bits": [0, 9], "name": "OFF_DELAY"},
12825    {"bits": [10, 10], "name": "IMMEDIATE"}
12826   ]
12827  },
12828  "COMPUTE_MISC_RESERVED": {
12829   "fields": [
12830    {"bits": [0, 1], "name": "SEND_SEID"},
12831    {"bits": [2, 2], "name": "RESERVED2"},
12832    {"bits": [3, 3], "name": "RESERVED3"},
12833    {"bits": [4, 4], "name": "RESERVED4"},
12834    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
12835   ]
12836  },
12837  "COMPUTE_NUM_THREAD_X": {
12838   "fields": [
12839    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
12840    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
12841   ]
12842  },
12843  "COMPUTE_PERFCOUNT_ENABLE": {
12844   "fields": [
12845    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
12846   ]
12847  },
12848  "COMPUTE_PGM_HI": {
12849   "fields": [
12850    {"bits": [0, 7], "name": "DATA"}
12851   ]
12852  },
12853  "COMPUTE_PGM_RSRC1": {
12854   "fields": [
12855    {"bits": [0, 5], "name": "VGPRS"},
12856    {"bits": [6, 9], "name": "SGPRS"},
12857    {"bits": [10, 11], "name": "PRIORITY"},
12858    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12859    {"bits": [20, 20], "name": "PRIV"},
12860    {"bits": [21, 21], "name": "DX10_CLAMP"},
12861    {"bits": [23, 23], "name": "IEEE_MODE"},
12862    {"bits": [24, 24], "name": "BULKY"},
12863    {"bits": [26, 26], "name": "FP16_OVFL"},
12864    {"bits": [29, 29], "name": "WGP_MODE"},
12865    {"bits": [30, 30], "name": "MEM_ORDERED"},
12866    {"bits": [31, 31], "name": "FWD_PROGRESS"}
12867   ]
12868  },
12869  "COMPUTE_PGM_RSRC2": {
12870   "fields": [
12871    {"bits": [0, 0], "name": "SCRATCH_EN"},
12872    {"bits": [1, 5], "name": "USER_SGPR"},
12873    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12874    {"bits": [7, 7], "name": "TGID_X_EN"},
12875    {"bits": [8, 8], "name": "TGID_Y_EN"},
12876    {"bits": [9, 9], "name": "TGID_Z_EN"},
12877    {"bits": [10, 10], "name": "TG_SIZE_EN"},
12878    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
12879    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
12880    {"bits": [15, 23], "name": "LDS_SIZE"},
12881    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12882   ]
12883  },
12884  "COMPUTE_PGM_RSRC3": {
12885   "fields": [
12886    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
12887   ]
12888  },
12889  "COMPUTE_PIPELINESTAT_ENABLE": {
12890   "fields": [
12891    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
12892   ]
12893  },
12894  "COMPUTE_RELAUNCH": {
12895   "fields": [
12896    {"bits": [0, 29], "name": "PAYLOAD"},
12897    {"bits": [30, 30], "name": "IS_EVENT"},
12898    {"bits": [31, 31], "name": "IS_STATE"}
12899   ]
12900  },
12901  "COMPUTE_REQ_CTRL": {
12902   "fields": [
12903    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
12904    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
12905    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
12906    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
12907    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
12908    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
12909    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
12910    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
12911    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
12912   ]
12913  },
12914  "COMPUTE_RESOURCE_LIMITS": {
12915   "fields": [
12916    {"bits": [0, 9], "name": "WAVES_PER_SH"},
12917    {"bits": [12, 15], "name": "TG_PER_CU"},
12918    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
12919    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
12920    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
12921    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
12922   ]
12923  },
12924  "COMPUTE_RESTART_X": {
12925   "fields": [
12926    {"bits": [0, 31], "name": "RESTART"}
12927   ]
12928  },
12929  "COMPUTE_START_X": {
12930   "fields": [
12931    {"bits": [0, 31], "name": "START"}
12932   ]
12933  },
12934  "COMPUTE_THREADGROUP_ID": {
12935   "fields": [
12936    {"bits": [0, 31], "name": "THREADGROUP_ID"}
12937   ]
12938  },
12939  "COMPUTE_THREAD_TRACE_ENABLE": {
12940   "fields": [
12941    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
12942   ]
12943  },
12944  "COMPUTE_TMPRING_SIZE": {
12945   "fields": [
12946    {"bits": [0, 11], "name": "WAVES"},
12947    {"bits": [12, 24], "name": "WAVESIZE"}
12948   ]
12949  },
12950  "COMPUTE_VMID": {
12951   "fields": [
12952    {"bits": [0, 3], "name": "DATA"}
12953   ]
12954  },
12955  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
12956   "fields": [
12957    {"bits": [0, 15], "name": "ADDR"}
12958   ]
12959  },
12960  "COMPUTE_WAVE_RESTORE_ADDR_LO": {
12961   "fields": [
12962    {"bits": [0, 31], "name": "ADDR"}
12963   ]
12964  },
12965  "CPF_LATENCY_STATS_SELECT": {
12966   "fields": [
12967    {"bits": [0, 3], "name": "INDEX"},
12968    {"bits": [30, 30], "name": "CLEAR"},
12969    {"bits": [31, 31], "name": "ENABLE"}
12970   ]
12971  },
12972  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
12973   "fields": [
12974    {"bits": [0, 2], "name": "INDEX"},
12975    {"bits": [30, 30], "name": "ALWAYS"},
12976    {"bits": [31, 31], "name": "ENABLE"}
12977   ]
12978  },
12979  "CPG_LATENCY_STATS_SELECT": {
12980   "fields": [
12981    {"bits": [0, 4], "name": "INDEX"},
12982    {"bits": [30, 30], "name": "CLEAR"},
12983    {"bits": [31, 31], "name": "ENABLE"}
12984   ]
12985  },
12986  "CPG_PERFCOUNTER0_SELECT1": {
12987   "fields": [
12988    {"bits": [0, 9], "name": "PERF_SEL2"},
12989    {"bits": [10, 19], "name": "PERF_SEL3"},
12990    {"bits": [24, 27], "name": "CNTR_MODE3"},
12991    {"bits": [28, 31], "name": "CNTR_MODE2"}
12992   ]
12993  },
12994  "CPG_PERFCOUNTER1_HI": {
12995   "fields": [
12996    {"bits": [0, 31], "name": "PERFCOUNTER_HI"}
12997   ]
12998  },
12999  "CPG_PERFCOUNTER1_LO": {
13000   "fields": [
13001    {"bits": [0, 31], "name": "PERFCOUNTER_LO"}
13002   ]
13003  },
13004  "CPG_PERFCOUNTER1_SELECT": {
13005   "fields": [
13006    {"bits": [0, 9], "name": "PERF_SEL"},
13007    {"bits": [10, 19], "name": "PERF_SEL1"},
13008    {"bits": [20, 23], "name": "SPM_MODE"},
13009    {"bits": [24, 27], "name": "CNTR_MODE1"},
13010    {"bits": [28, 31], "name": "CNTR_MODE0"}
13011   ]
13012  },
13013  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
13014   "fields": [
13015    {"bits": [0, 4], "name": "INDEX"},
13016    {"bits": [30, 30], "name": "ALWAYS"},
13017    {"bits": [31, 31], "name": "ENABLE"}
13018   ]
13019  },
13020  "CP_APPEND_ADDR_HI": {
13021   "fields": [
13022    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
13023    {"bits": [16, 16], "name": "CS_PS_SEL"},
13024    {"bits": [25, 26], "name": "CACHE_POLICY"},
13025    {"bits": [29, 31], "name": "COMMAND"}
13026   ]
13027  },
13028  "CP_APPEND_ADDR_LO": {
13029   "fields": [
13030    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
13031   ]
13032  },
13033  "CP_APPEND_LAST_CS_FENCE_HI": {
13034   "fields": [
13035    {"bits": [0, 31], "name": "LAST_FENCE"}
13036   ]
13037  },
13038  "CP_CE_COUNTER": {
13039   "fields": [
13040    {"bits": [0, 31], "name": "CONST_ENGINE_COUNT"}
13041   ]
13042  },
13043  "CP_CE_IB1_BASE_HI": {
13044   "fields": [
13045    {"bits": [0, 15], "name": "IB1_BASE_HI"}
13046   ]
13047  },
13048  "CP_CE_IB1_BASE_LO": {
13049   "fields": [
13050    {"bits": [2, 31], "name": "IB1_BASE_LO"}
13051   ]
13052  },
13053  "CP_CE_IB1_BUFSZ": {
13054   "fields": [
13055    {"bits": [0, 19], "name": "IB1_BUFSZ"}
13056   ]
13057  },
13058  "CP_CE_IB1_CMD_BUFSZ": {
13059   "fields": [
13060    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
13061   ]
13062  },
13063  "CP_CE_IB2_BASE_HI": {
13064   "fields": [
13065    {"bits": [0, 15], "name": "IB2_BASE_HI"}
13066   ]
13067  },
13068  "CP_CE_IB2_BASE_LO": {
13069   "fields": [
13070    {"bits": [2, 31], "name": "IB2_BASE_LO"}
13071   ]
13072  },
13073  "CP_CE_IB2_BUFSZ": {
13074   "fields": [
13075    {"bits": [0, 19], "name": "IB2_BUFSZ"}
13076   ]
13077  },
13078  "CP_CE_IB2_CMD_BUFSZ": {
13079   "fields": [
13080    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
13081   ]
13082  },
13083  "CP_CE_INIT_BASE_HI": {
13084   "fields": [
13085    {"bits": [0, 15], "name": "INIT_BASE_HI"}
13086   ]
13087  },
13088  "CP_CE_INIT_BASE_LO": {
13089   "fields": [
13090    {"bits": [5, 31], "name": "INIT_BASE_LO"}
13091   ]
13092  },
13093  "CP_CE_INIT_BUFSZ": {
13094   "fields": [
13095    {"bits": [0, 11], "name": "INIT_BUFSZ"}
13096   ]
13097  },
13098  "CP_CE_INIT_CMD_BUFSZ": {
13099   "fields": [
13100    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
13101   ]
13102  },
13103  "CP_COHER_BASE": {
13104   "fields": [
13105    {"bits": [0, 31], "name": "COHER_BASE_256B"}
13106   ]
13107  },
13108  "CP_COHER_BASE_HI": {
13109   "fields": [
13110    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
13111   ]
13112  },
13113  "CP_COHER_CNTL": {
13114   "fields": [
13115    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
13116    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
13117    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
13118    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
13119    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
13120    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
13121    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
13122    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
13123    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
13124    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
13125    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
13126    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
13127    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
13128   ]
13129  },
13130  "CP_COHER_SIZE": {
13131   "fields": [
13132    {"bits": [0, 31], "name": "COHER_SIZE_256B"}
13133   ]
13134  },
13135  "CP_COHER_SIZE_HI": {
13136   "fields": [
13137    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
13138   ]
13139  },
13140  "CP_COHER_START_DELAY": {
13141   "fields": [
13142    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
13143   ]
13144  },
13145  "CP_COHER_STATUS": {
13146   "fields": [
13147    {"bits": [24, 25], "name": "MEID"},
13148    {"bits": [31, 31], "name": "STATUS"}
13149   ]
13150  },
13151  "CP_CPC_BUSY_STAT": {
13152   "fields": [
13153    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
13154    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
13155    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
13156    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
13157    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
13158    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
13159    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
13160    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
13161    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
13162    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
13163    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
13164    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
13165    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
13166    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
13167    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
13168    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
13169    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
13170    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
13171    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
13172    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
13173    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
13174    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
13175    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
13176    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
13177    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
13178    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
13179    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
13180    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
13181   ]
13182  },
13183  "CP_CPC_BUSY_STAT2": {
13184   "fields": [
13185    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
13186    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
13187    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
13188    {"bits": [7, 7], "name": "MES_TC_BUSY"},
13189    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
13190    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
13191    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
13192    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
13193    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
13194   ]
13195  },
13196  "CP_CPC_GRBM_FREE_COUNT": {
13197   "fields": [
13198    {"bits": [0, 5], "name": "FREE_COUNT"}
13199   ]
13200  },
13201  "CP_CPC_HALT_HYST_COUNT": {
13202   "fields": [
13203    {"bits": [0, 3], "name": "COUNT"}
13204   ]
13205  },
13206  "CP_CPC_SCRATCH_DATA": {
13207   "fields": [
13208    {"bits": [0, 31], "name": "SCRATCH_DATA"}
13209   ]
13210  },
13211  "CP_CPC_SCRATCH_INDEX": {
13212   "fields": [
13213    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
13214    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
13215   ]
13216  },
13217  "CP_CPC_STALLED_STAT1": {
13218   "fields": [
13219    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
13220    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
13221    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
13222    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
13223    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
13224    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
13225    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
13226    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
13227    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
13228    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
13229    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
13230    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
13231    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
13232    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
13233    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
13234   ]
13235  },
13236  "CP_CPC_STATUS": {
13237   "fields": [
13238    {"bits": [0, 0], "name": "MEC1_BUSY"},
13239    {"bits": [1, 1], "name": "MEC2_BUSY"},
13240    {"bits": [2, 2], "name": "DC0_BUSY"},
13241    {"bits": [3, 3], "name": "DC1_BUSY"},
13242    {"bits": [4, 4], "name": "RCIU1_BUSY"},
13243    {"bits": [5, 5], "name": "RCIU2_BUSY"},
13244    {"bits": [6, 6], "name": "ROQ1_BUSY"},
13245    {"bits": [7, 7], "name": "ROQ2_BUSY"},
13246    {"bits": [10, 10], "name": "TCIU_BUSY"},
13247    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
13248    {"bits": [12, 12], "name": "QU_BUSY"},
13249    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
13250    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
13251    {"bits": [15, 15], "name": "GCRIU_BUSY"},
13252    {"bits": [16, 16], "name": "MES_BUSY"},
13253    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
13254    {"bits": [18, 18], "name": "RCIU3_BUSY"},
13255    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
13256    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
13257    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
13258    {"bits": [31, 31], "name": "CPC_BUSY"}
13259   ]
13260  },
13261  "CP_CPF_BUSY_STAT": {
13262   "fields": [
13263    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
13264    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
13265    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
13266    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
13267    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
13268    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
13269    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
13270    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
13271    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
13272    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
13273    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
13274    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
13275    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
13276    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
13277    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
13278    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
13279    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
13280    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
13281    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
13282    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
13283    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
13284    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
13285    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
13286    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
13287    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
13288    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
13289    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
13290    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
13291    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
13292    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
13293    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
13294    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
13295   ]
13296  },
13297  "CP_CPF_BUSY_STAT2": {
13298   "fields": [
13299    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
13300    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
13301    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
13302    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
13303    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
13304    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
13305    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
13306    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
13307    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
13308   ]
13309  },
13310  "CP_CPF_GRBM_FREE_COUNT": {
13311   "fields": [
13312    {"bits": [0, 2], "name": "FREE_COUNT"}
13313   ]
13314  },
13315  "CP_CPF_STALLED_STAT1": {
13316   "fields": [
13317    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
13318    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
13319    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
13320    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
13321    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
13322    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
13323    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
13324    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
13325    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
13326    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
13327    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
13328    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
13329    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
13330   ]
13331  },
13332  "CP_CPF_STATUS": {
13333   "fields": [
13334    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
13335    {"bits": [1, 1], "name": "CSF_BUSY"},
13336    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
13337    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
13338    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
13339    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
13340    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
13341    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
13342    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
13343    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
13344    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
13345    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
13346    {"bits": [14, 14], "name": "TCIU_BUSY"},
13347    {"bits": [15, 15], "name": "HQD_BUSY"},
13348    {"bits": [16, 16], "name": "PRT_BUSY"},
13349    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
13350    {"bits": [18, 18], "name": "RCIU_BUSY"},
13351    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
13352    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
13353    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
13354    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
13355    {"bits": [23, 23], "name": "GCRIU_BUSY"},
13356    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
13357    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
13358    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
13359    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
13360    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
13361    {"bits": [31, 31], "name": "CPF_BUSY"}
13362   ]
13363  },
13364  "CP_DB_BASE_HI": {
13365   "fields": [
13366    {"bits": [0, 15], "name": "DB_BASE_HI"}
13367   ]
13368  },
13369  "CP_DB_BASE_LO": {
13370   "fields": [
13371    {"bits": [2, 31], "name": "DB_BASE_LO"}
13372   ]
13373  },
13374  "CP_DB_BUFSZ": {
13375   "fields": [
13376    {"bits": [0, 19], "name": "DB_BUFSZ"}
13377   ]
13378  },
13379  "CP_DB_CMD_BUFSZ": {
13380   "fields": [
13381    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
13382   ]
13383  },
13384  "CP_DMA_CNTL": {
13385   "fields": [
13386    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
13387    {"bits": [1, 1], "name": "WATCH_CONTROL"},
13388    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
13389    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
13390    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
13391    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
13392    {"bits": [30, 31], "name": "PIO_COUNT"}
13393   ]
13394  },
13395  "CP_DMA_ME_CMD_ADDR_HI": {
13396   "fields": [
13397    {"bits": [0, 15], "name": "ADDR_HI"},
13398    {"bits": [16, 31], "name": "RSVD"}
13399   ]
13400  },
13401  "CP_DMA_ME_CMD_ADDR_LO": {
13402   "fields": [
13403    {"bits": [0, 1], "name": "RSVD"},
13404    {"bits": [2, 31], "name": "ADDR_LO"}
13405   ]
13406  },
13407  "CP_DMA_ME_COMMAND": {
13408   "fields": [
13409    {"bits": [0, 25], "name": "BYTE_COUNT"},
13410    {"bits": [26, 26], "name": "SAS"},
13411    {"bits": [27, 27], "name": "DAS"},
13412    {"bits": [28, 28], "name": "SAIC"},
13413    {"bits": [29, 29], "name": "DAIC"},
13414    {"bits": [30, 30], "name": "RAW_WAIT"},
13415    {"bits": [31, 31], "name": "DIS_WC"}
13416   ]
13417  },
13418  "CP_DMA_ME_DST_ADDR": {
13419   "fields": [
13420    {"bits": [0, 31], "name": "DST_ADDR"}
13421   ]
13422  },
13423  "CP_DMA_ME_DST_ADDR_HI": {
13424   "fields": [
13425    {"bits": [0, 15], "name": "DST_ADDR_HI"}
13426   ]
13427  },
13428  "CP_DMA_ME_SRC_ADDR": {
13429   "fields": [
13430    {"bits": [0, 31], "name": "SRC_ADDR"}
13431   ]
13432  },
13433  "CP_DMA_ME_SRC_ADDR_HI": {
13434   "fields": [
13435    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
13436   ]
13437  },
13438  "CP_DMA_PFP_CONTROL": {
13439   "fields": [
13440    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
13441    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
13442    {"bits": [15, 15], "name": "SRC_VOLATLE"},
13443    {"bits": [20, 21], "name": "DST_SELECT"},
13444    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
13445    {"bits": [27, 27], "name": "DST_VOLATLE"},
13446    {"bits": [29, 30], "name": "SRC_SELECT"}
13447   ]
13448  },
13449  "CP_DMA_READ_TAGS": {
13450   "fields": [
13451    {"bits": [0, 25], "name": "DMA_READ_TAG"},
13452    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
13453   ]
13454  },
13455  "CP_DRAW_OBJECT": {
13456   "fields": [
13457    {"bits": [0, 31], "name": "OBJECT"}
13458   ]
13459  },
13460  "CP_DRAW_WINDOW_CNTL": {
13461   "fields": [
13462    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
13463    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
13464    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
13465    {"bits": [8, 8], "name": "MODE"}
13466   ]
13467  },
13468  "CP_DRAW_WINDOW_HI": {
13469   "fields": [
13470    {"bits": [0, 31], "name": "WINDOW_HI"}
13471   ]
13472  },
13473  "CP_DRAW_WINDOW_LO": {
13474   "fields": [
13475    {"bits": [0, 15], "name": "MIN"},
13476    {"bits": [16, 31], "name": "MAX"}
13477   ]
13478  },
13479  "CP_DRAW_WINDOW_MASK_HI": {
13480   "fields": [
13481    {"bits": [0, 31], "name": "WINDOW_MASK_HI"}
13482   ]
13483  },
13484  "CP_EOP_DONE_ADDR_HI": {
13485   "fields": [
13486    {"bits": [0, 15], "name": "ADDR_HI"}
13487   ]
13488  },
13489  "CP_EOP_DONE_ADDR_LO": {
13490   "fields": [
13491    {"bits": [2, 31], "name": "ADDR_LO"}
13492   ]
13493  },
13494  "CP_EOP_DONE_CNTX_ID": {
13495   "fields": [
13496    {"bits": [0, 31], "name": "CNTX_ID"}
13497   ]
13498  },
13499  "CP_EOP_DONE_DATA_CNTL": {
13500   "fields": [
13501    {"bits": [16, 17], "name": "DST_SEL"},
13502    {"bits": [24, 26], "name": "INT_SEL"},
13503    {"bits": [29, 31], "name": "DATA_SEL"}
13504   ]
13505  },
13506  "CP_EOP_DONE_DATA_HI": {
13507   "fields": [
13508    {"bits": [0, 31], "name": "DATA_HI"}
13509   ]
13510  },
13511  "CP_EOP_DONE_DATA_LO": {
13512   "fields": [
13513    {"bits": [0, 31], "name": "DATA_LO"}
13514   ]
13515  },
13516  "CP_EOP_DONE_DOORBELL": {
13517   "fields": [
13518    {"bits": [2, 27], "name": "DOORBELL_OFFSET"}
13519   ]
13520  },
13521  "CP_EOP_DONE_EVENT_CNTL": {
13522   "fields": [
13523    {"bits": [12, 23], "name": "GCR_CNTL"},
13524    {"bits": [25, 26], "name": "CACHE_POLICY"},
13525    {"bits": [27, 27], "name": "EOP_VOLATILE"},
13526    {"bits": [28, 28], "name": "EXECUTE"}
13527   ]
13528  },
13529  "CP_EOP_LAST_FENCE_HI": {
13530   "fields": [
13531    {"bits": [0, 31], "name": "LAST_FENCE_HI"}
13532   ]
13533  },
13534  "CP_EOP_LAST_FENCE_LO": {
13535   "fields": [
13536    {"bits": [0, 31], "name": "LAST_FENCE_LO"}
13537   ]
13538  },
13539  "CP_IB1_OFFSET": {
13540   "fields": [
13541    {"bits": [0, 19], "name": "IB1_OFFSET"}
13542   ]
13543  },
13544  "CP_IB1_PREAMBLE_BEGIN": {
13545   "fields": [
13546    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
13547   ]
13548  },
13549  "CP_IB1_PREAMBLE_END": {
13550   "fields": [
13551    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
13552   ]
13553  },
13554  "CP_IB2_OFFSET": {
13555   "fields": [
13556    {"bits": [0, 19], "name": "IB2_OFFSET"}
13557   ]
13558  },
13559  "CP_IB2_PREAMBLE_BEGIN": {
13560   "fields": [
13561    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
13562   ]
13563  },
13564  "CP_IB2_PREAMBLE_END": {
13565   "fields": [
13566    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
13567   ]
13568  },
13569  "CP_INDEX_TYPE": {
13570   "fields": [
13571    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
13572   ]
13573  },
13574  "CP_ME_COHER_CNTL": {
13575   "fields": [
13576    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
13577    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
13578    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
13579    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
13580    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
13581    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
13582    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
13583    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
13584    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
13585    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
13586    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
13587    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
13588    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
13589   ]
13590  },
13591  "CP_ME_COHER_STATUS": {
13592   "fields": [
13593    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
13594    {"bits": [31, 31], "name": "STATUS"}
13595   ]
13596  },
13597  "CP_ME_MC_RADDR_HI": {
13598   "fields": [
13599    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
13600    {"bits": [22, 23], "name": "CACHE_POLICY"}
13601   ]
13602  },
13603  "CP_ME_MC_RADDR_LO": {
13604   "fields": [
13605    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
13606   ]
13607  },
13608  "CP_ME_MC_WADDR_HI": {
13609   "fields": [
13610    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
13611    {"bits": [22, 23], "name": "CACHE_POLICY"}
13612   ]
13613  },
13614  "CP_ME_MC_WADDR_LO": {
13615   "fields": [
13616    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
13617   ]
13618  },
13619  "CP_ME_MC_WDATA_HI": {
13620   "fields": [
13621    {"bits": [0, 31], "name": "ME_MC_WDATA_HI"}
13622   ]
13623  },
13624  "CP_ME_MC_WDATA_LO": {
13625   "fields": [
13626    {"bits": [0, 31], "name": "ME_MC_WDATA_LO"}
13627   ]
13628  },
13629  "CP_NUM_PRIM_NEEDED_COUNT0_HI": {
13630   "fields": [
13631    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"}
13632   ]
13633  },
13634  "CP_NUM_PRIM_NEEDED_COUNT0_LO": {
13635   "fields": [
13636    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"}
13637   ]
13638  },
13639  "CP_NUM_PRIM_NEEDED_COUNT1_HI": {
13640   "fields": [
13641    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"}
13642   ]
13643  },
13644  "CP_NUM_PRIM_NEEDED_COUNT1_LO": {
13645   "fields": [
13646    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"}
13647   ]
13648  },
13649  "CP_NUM_PRIM_NEEDED_COUNT2_HI": {
13650   "fields": [
13651    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"}
13652   ]
13653  },
13654  "CP_NUM_PRIM_NEEDED_COUNT2_LO": {
13655   "fields": [
13656    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"}
13657   ]
13658  },
13659  "CP_NUM_PRIM_NEEDED_COUNT3_HI": {
13660   "fields": [
13661    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"}
13662   ]
13663  },
13664  "CP_NUM_PRIM_NEEDED_COUNT3_LO": {
13665   "fields": [
13666    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"}
13667   ]
13668  },
13669  "CP_NUM_PRIM_WRITTEN_COUNT0_HI": {
13670   "fields": [
13671    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"}
13672   ]
13673  },
13674  "CP_NUM_PRIM_WRITTEN_COUNT0_LO": {
13675   "fields": [
13676    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"}
13677   ]
13678  },
13679  "CP_NUM_PRIM_WRITTEN_COUNT1_HI": {
13680   "fields": [
13681    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"}
13682   ]
13683  },
13684  "CP_NUM_PRIM_WRITTEN_COUNT1_LO": {
13685   "fields": [
13686    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"}
13687   ]
13688  },
13689  "CP_NUM_PRIM_WRITTEN_COUNT2_HI": {
13690   "fields": [
13691    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"}
13692   ]
13693  },
13694  "CP_NUM_PRIM_WRITTEN_COUNT2_LO": {
13695   "fields": [
13696    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"}
13697   ]
13698  },
13699  "CP_NUM_PRIM_WRITTEN_COUNT3_HI": {
13700   "fields": [
13701    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"}
13702   ]
13703  },
13704  "CP_NUM_PRIM_WRITTEN_COUNT3_LO": {
13705   "fields": [
13706    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"}
13707   ]
13708  },
13709  "CP_PA_CINVOC_COUNT_HI": {
13710   "fields": [
13711    {"bits": [0, 31], "name": "CINVOC_COUNT_HI"}
13712   ]
13713  },
13714  "CP_PA_CINVOC_COUNT_LO": {
13715   "fields": [
13716    {"bits": [0, 31], "name": "CINVOC_COUNT_LO"}
13717   ]
13718  },
13719  "CP_PA_CPRIM_COUNT_HI": {
13720   "fields": [
13721    {"bits": [0, 31], "name": "CPRIM_COUNT_HI"}
13722   ]
13723  },
13724  "CP_PA_CPRIM_COUNT_LO": {
13725   "fields": [
13726    {"bits": [0, 31], "name": "CPRIM_COUNT_LO"}
13727   ]
13728  },
13729  "CP_PERFMON_CNTL": {
13730   "fields": [
13731    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13732    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
13733    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
13734    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13735   ]
13736  },
13737  "CP_PERFMON_CNTX_CNTL": {
13738   "fields": [
13739    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
13740   ]
13741  },
13742  "CP_PFP_ATOMIC_PREOP_HI": {
13743   "fields": [
13744    {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"}
13745   ]
13746  },
13747  "CP_PFP_ATOMIC_PREOP_LO": {
13748   "fields": [
13749    {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"}
13750   ]
13751  },
13752  "CP_PFP_COMPLETION_STATUS": {
13753   "fields": [
13754    {"bits": [0, 1], "name": "STATUS"}
13755   ]
13756  },
13757  "CP_PFP_GDS_ATOMIC0_PREOP_HI": {
13758   "fields": [
13759    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"}
13760   ]
13761  },
13762  "CP_PFP_GDS_ATOMIC0_PREOP_LO": {
13763   "fields": [
13764    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"}
13765   ]
13766  },
13767  "CP_PFP_GDS_ATOMIC1_PREOP_HI": {
13768   "fields": [
13769    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"}
13770   ]
13771  },
13772  "CP_PFP_GDS_ATOMIC1_PREOP_LO": {
13773   "fields": [
13774    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"}
13775   ]
13776  },
13777  "CP_PFP_IB_CONTROL": {
13778   "fields": [
13779    {"bits": [0, 7], "name": "IB_EN"}
13780   ]
13781  },
13782  "CP_PFP_LOAD_CONTROL": {
13783   "fields": [
13784    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
13785    {"bits": [1, 1], "name": "CNTX_REG_EN"},
13786    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
13787    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
13788   ]
13789  },
13790  "CP_PFP_METADATA_BASE_ADDR": {
13791   "fields": [
13792    {"bits": [0, 31], "name": "ADDR_LO"}
13793   ]
13794  },
13795  "CP_PIPEID": {
13796   "fields": [
13797    {"bits": [0, 1], "name": "PIPE_ID"}
13798   ]
13799  },
13800  "CP_PIPE_STATS_ADDR_HI": {
13801   "fields": [
13802    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
13803   ]
13804  },
13805  "CP_PIPE_STATS_ADDR_LO": {
13806   "fields": [
13807    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
13808   ]
13809  },
13810  "CP_PIPE_STATS_CONTROL": {
13811   "fields": [
13812    {"bits": [25, 26], "name": "CACHE_POLICY"}
13813   ]
13814  },
13815  "CP_PRED_NOT_VISIBLE": {
13816   "fields": [
13817    {"bits": [0, 0], "name": "NOT_VISIBLE"}
13818   ]
13819  },
13820  "CP_RB_OFFSET": {
13821   "fields": [
13822    {"bits": [0, 19], "name": "RB_OFFSET"}
13823   ]
13824  },
13825  "CP_SAMPLE_STATUS": {
13826   "fields": [
13827    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
13828    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
13829    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
13830    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
13831    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
13832    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
13833    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
13834    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
13835   ]
13836  },
13837  "CP_SCRATCH_INDEX": {
13838   "fields": [
13839    {"bits": [0, 7], "name": "SCRATCH_INDEX"},
13840    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
13841   ]
13842  },
13843  "CP_SC_PSINVOC_COUNT0_HI": {
13844   "fields": [
13845    {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"}
13846   ]
13847  },
13848  "CP_SC_PSINVOC_COUNT0_LO": {
13849   "fields": [
13850    {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"}
13851   ]
13852  },
13853  "CP_SC_PSINVOC_COUNT1_LO": {
13854   "fields": [
13855    {"bits": [0, 31], "name": "OBSOLETE"}
13856   ]
13857  },
13858  "CP_SEM_WAIT_TIMER": {
13859   "fields": [
13860    {"bits": [0, 31], "name": "SEM_WAIT_TIMER"}
13861   ]
13862  },
13863  "CP_SIG_SEM_ADDR_HI": {
13864   "fields": [
13865    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
13866    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
13867    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
13868    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
13869    {"bits": [29, 31], "name": "SEM_SELECT"}
13870   ]
13871  },
13872  "CP_SIG_SEM_ADDR_LO": {
13873   "fields": [
13874    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
13875    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
13876   ]
13877  },
13878  "CP_STREAM_OUT_ADDR_HI": {
13879   "fields": [
13880    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
13881   ]
13882  },
13883  "CP_STREAM_OUT_ADDR_LO": {
13884   "fields": [
13885    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
13886   ]
13887  },
13888  "CP_STRMOUT_CNTL": {
13889   "fields": [
13890    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
13891   ]
13892  },
13893  "CP_ST_BASE_HI": {
13894   "fields": [
13895    {"bits": [0, 15], "name": "ST_BASE_HI"}
13896   ]
13897  },
13898  "CP_ST_BASE_LO": {
13899   "fields": [
13900    {"bits": [2, 31], "name": "ST_BASE_LO"}
13901   ]
13902  },
13903  "CP_ST_BUFSZ": {
13904   "fields": [
13905    {"bits": [0, 19], "name": "ST_BUFSZ"}
13906   ]
13907  },
13908  "CP_ST_CMD_BUFSZ": {
13909   "fields": [
13910    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
13911   ]
13912  },
13913  "CP_VGT_CSINVOC_COUNT_HI": {
13914   "fields": [
13915    {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"}
13916   ]
13917  },
13918  "CP_VGT_CSINVOC_COUNT_LO": {
13919   "fields": [
13920    {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"}
13921   ]
13922  },
13923  "CP_VGT_DSINVOC_COUNT_HI": {
13924   "fields": [
13925    {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"}
13926   ]
13927  },
13928  "CP_VGT_DSINVOC_COUNT_LO": {
13929   "fields": [
13930    {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"}
13931   ]
13932  },
13933  "CP_VGT_GSINVOC_COUNT_HI": {
13934   "fields": [
13935    {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"}
13936   ]
13937  },
13938  "CP_VGT_GSINVOC_COUNT_LO": {
13939   "fields": [
13940    {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"}
13941   ]
13942  },
13943  "CP_VGT_GSPRIM_COUNT_HI": {
13944   "fields": [
13945    {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"}
13946   ]
13947  },
13948  "CP_VGT_GSPRIM_COUNT_LO": {
13949   "fields": [
13950    {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"}
13951   ]
13952  },
13953  "CP_VGT_HSINVOC_COUNT_HI": {
13954   "fields": [
13955    {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"}
13956   ]
13957  },
13958  "CP_VGT_HSINVOC_COUNT_LO": {
13959   "fields": [
13960    {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"}
13961   ]
13962  },
13963  "CP_VGT_IAPRIM_COUNT_HI": {
13964   "fields": [
13965    {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"}
13966   ]
13967  },
13968  "CP_VGT_IAPRIM_COUNT_LO": {
13969   "fields": [
13970    {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"}
13971   ]
13972  },
13973  "CP_VGT_IAVERT_COUNT_HI": {
13974   "fields": [
13975    {"bits": [0, 31], "name": "IAVERT_COUNT_HI"}
13976   ]
13977  },
13978  "CP_VGT_IAVERT_COUNT_LO": {
13979   "fields": [
13980    {"bits": [0, 31], "name": "IAVERT_COUNT_LO"}
13981   ]
13982  },
13983  "CP_VGT_VSINVOC_COUNT_HI": {
13984   "fields": [
13985    {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"}
13986   ]
13987  },
13988  "CP_VGT_VSINVOC_COUNT_LO": {
13989   "fields": [
13990    {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"}
13991   ]
13992  },
13993  "CP_VMID": {
13994   "fields": [
13995    {"bits": [0, 3], "name": "VMID"}
13996   ]
13997  },
13998  "CP_WAIT_REG_MEM_TIMEOUT": {
13999   "fields": [
14000    {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"}
14001   ]
14002  },
14003  "CS_COPY_STATE": {
14004   "fields": [
14005    {"bits": [0, 2], "name": "SRC_STATE_ID"}
14006   ]
14007  },
14008  "DB_ALPHA_TO_MASK": {
14009   "fields": [
14010    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
14011    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
14012    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
14013    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
14014    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
14015    {"bits": [16, 16], "name": "OFFSET_ROUND"}
14016   ]
14017  },
14018  "DB_COUNT_CONTROL": {
14019   "fields": [
14020    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
14021    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
14022    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
14023    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
14024    {"bits": [4, 6], "name": "SAMPLE_RATE"},
14025    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
14026    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
14027    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
14028    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
14029    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
14030    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
14031   ]
14032  },
14033  "DB_DEPTH_BOUNDS_MAX": {
14034   "fields": [
14035    {"bits": [0, 31], "name": "MAX"}
14036   ]
14037  },
14038  "DB_DEPTH_BOUNDS_MIN": {
14039   "fields": [
14040    {"bits": [0, 31], "name": "MIN"}
14041   ]
14042  },
14043  "DB_DEPTH_CLEAR": {
14044   "fields": [
14045    {"bits": [0, 31], "name": "DEPTH_CLEAR"}
14046   ]
14047  },
14048  "DB_DEPTH_CONTROL": {
14049   "fields": [
14050    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
14051    {"bits": [1, 1], "name": "Z_ENABLE"},
14052    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
14053    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
14054    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
14055    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
14056    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
14057    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
14058    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
14059    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
14060   ]
14061  },
14062  "DB_DEPTH_SIZE_XY": {
14063   "fields": [
14064    {"bits": [0, 13], "name": "X_MAX"},
14065    {"bits": [16, 29], "name": "Y_MAX"}
14066   ]
14067  },
14068  "DB_DEPTH_VIEW": {
14069   "fields": [
14070    {"bits": [0, 10], "name": "SLICE_START"},
14071    {"bits": [11, 12], "name": "SLICE_START_HI"},
14072    {"bits": [13, 23], "name": "SLICE_MAX"},
14073    {"bits": [24, 24], "name": "Z_READ_ONLY"},
14074    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
14075    {"bits": [26, 29], "name": "MIPID"},
14076    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
14077   ]
14078  },
14079  "DB_DFSM_CONTROL": {
14080   "fields": [
14081    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
14082    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
14083    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
14084   ]
14085  },
14086  "DB_EQAA": {
14087   "fields": [
14088    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
14089    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
14090    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
14091    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
14092    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
14093    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
14094    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
14095    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
14096    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
14097    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
14098    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
14099    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
14100   ]
14101  },
14102  "DB_HTILE_DATA_BASE": {
14103   "fields": [
14104    {"bits": [0, 31], "name": "BASE_256B"}
14105   ]
14106  },
14107  "DB_HTILE_SURFACE": {
14108   "fields": [
14109    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
14110    {"bits": [1, 1], "name": "FULL_CACHE"},
14111    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
14112    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
14113    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
14114    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
14115    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
14116    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
14117    {"bits": [18, 18], "name": "PIPE_ALIGNED"}
14118   ]
14119  },
14120  "DB_OCCLUSION_COUNT0_HI": {
14121   "fields": [
14122    {"bits": [0, 30], "name": "COUNT_HI"}
14123   ]
14124  },
14125  "DB_OCCLUSION_COUNT0_LOW": {
14126   "fields": [
14127    {"bits": [0, 31], "name": "COUNT_LOW"}
14128   ]
14129  },
14130  "DB_PRELOAD_CONTROL": {
14131   "fields": [
14132    {"bits": [0, 7], "name": "START_X"},
14133    {"bits": [8, 15], "name": "START_Y"},
14134    {"bits": [16, 23], "name": "MAX_X"},
14135    {"bits": [24, 31], "name": "MAX_Y"}
14136   ]
14137  },
14138  "DB_RENDER_CONTROL": {
14139   "fields": [
14140    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
14141    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
14142    {"bits": [2, 2], "name": "DEPTH_COPY"},
14143    {"bits": [3, 3], "name": "STENCIL_COPY"},
14144    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
14145    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
14146    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
14147    {"bits": [7, 7], "name": "COPY_CENTROID"},
14148    {"bits": [8, 11], "name": "COPY_SAMPLE"},
14149    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
14150   ]
14151  },
14152  "DB_RENDER_OVERRIDE": {
14153   "fields": [
14154    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
14155    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
14156    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
14157    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
14158    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
14159    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
14160    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
14161    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
14162    {"bits": [11, 11], "name": "FORCE_Z_READ"},
14163    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
14164    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
14165    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
14166    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
14167    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
14168    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
14169    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
14170    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
14171    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
14172    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
14173    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
14174    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
14175    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
14176    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
14177   ]
14178  },
14179  "DB_RENDER_OVERRIDE2": {
14180   "fields": [
14181    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
14182    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
14183    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
14184    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
14185    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
14186    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
14187    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
14188    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
14189    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
14190    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
14191    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
14192    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
14193    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
14194    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
14195    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
14196    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"}
14197   ]
14198  },
14199  "DB_RESERVED_REG_1": {
14200   "fields": [
14201    {"bits": [0, 10], "name": "FIELD_1"},
14202    {"bits": [11, 21], "name": "FIELD_2"}
14203   ]
14204  },
14205  "DB_RESERVED_REG_2": {
14206   "fields": [
14207    {"bits": [0, 3], "name": "FIELD_1"},
14208    {"bits": [4, 7], "name": "FIELD_2"},
14209    {"bits": [8, 12], "name": "FIELD_3"},
14210    {"bits": [13, 14], "name": "FIELD_4"},
14211    {"bits": [15, 16], "name": "FIELD_5"},
14212    {"bits": [17, 18], "name": "FIELD_6"},
14213    {"bits": [19, 20], "name": "FIELD_7"},
14214    {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
14215   ]
14216  },
14217  "DB_RESERVED_REG_3": {
14218   "fields": [
14219    {"bits": [0, 21], "name": "FIELD_1"}
14220   ]
14221  },
14222  "DB_RMI_L2_CACHE_CONTROL": {
14223   "fields": [
14224    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
14225    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
14226    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
14227    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
14228    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
14229    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
14230    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
14231    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
14232    {"bits": [25, 25], "name": "S_BIG_PAGE"}
14233   ]
14234  },
14235  "DB_SHADER_CONTROL": {
14236   "fields": [
14237    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
14238    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
14239    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
14240    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
14241    {"bits": [6, 6], "name": "KILL_ENABLE"},
14242    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
14243    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
14244    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
14245    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
14246    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
14247    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
14248    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
14249    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
14250    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
14251    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
14252    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
14253    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
14254   ]
14255  },
14256  "DB_SRESULTS_COMPARE_STATE0": {
14257   "fields": [
14258    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
14259    {"bits": [4, 11], "name": "COMPAREVALUE0"},
14260    {"bits": [12, 19], "name": "COMPAREMASK0"},
14261    {"bits": [24, 24], "name": "ENABLE0"}
14262   ]
14263  },
14264  "DB_SRESULTS_COMPARE_STATE1": {
14265   "fields": [
14266    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
14267    {"bits": [4, 11], "name": "COMPAREVALUE1"},
14268    {"bits": [12, 19], "name": "COMPAREMASK1"},
14269    {"bits": [24, 24], "name": "ENABLE1"}
14270   ]
14271  },
14272  "DB_STENCILREFMASK": {
14273   "fields": [
14274    {"bits": [0, 7], "name": "STENCILTESTVAL"},
14275    {"bits": [8, 15], "name": "STENCILMASK"},
14276    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
14277    {"bits": [24, 31], "name": "STENCILOPVAL"}
14278   ]
14279  },
14280  "DB_STENCILREFMASK_BF": {
14281   "fields": [
14282    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
14283    {"bits": [8, 15], "name": "STENCILMASK_BF"},
14284    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
14285    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
14286   ]
14287  },
14288  "DB_STENCIL_CLEAR": {
14289   "fields": [
14290    {"bits": [0, 7], "name": "CLEAR"}
14291   ]
14292  },
14293  "DB_STENCIL_CONTROL": {
14294   "fields": [
14295    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
14296    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
14297    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
14298    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
14299    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
14300    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
14301   ]
14302  },
14303  "DB_STENCIL_INFO": {
14304   "fields": [
14305    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
14306    {"bits": [4, 8], "name": "SW_MODE"},
14307    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14308    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14309    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14310    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14311    {"bits": [20, 20], "name": "ITERATE_256"},
14312    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14313    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
14314   ]
14315  },
14316  "DB_Z_INFO": {
14317   "fields": [
14318    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
14319    {"bits": [2, 3], "name": "NUM_SAMPLES"},
14320    {"bits": [4, 8], "name": "SW_MODE"},
14321    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14322    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14323    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14324    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14325    {"bits": [16, 19], "name": "MAXMIP"},
14326    {"bits": [20, 20], "name": "ITERATE_256"},
14327    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
14328    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14329    {"bits": [28, 28], "name": "READ_SIZE"},
14330    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
14331    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
14332   ]
14333  },
14334  "DB_Z_READ_BASE_HI": {
14335   "fields": [
14336    {"bits": [0, 7], "name": "BASE_HI"}
14337   ]
14338  },
14339  "GB_ADDR_CONFIG": {
14340   "fields": [
14341    {"bits": [0, 2], "name": "NUM_PIPES"},
14342    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
14343    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
14344    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
14345    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
14346   ]
14347  },
14348  "GB_MACROTILE_MODE0": {
14349   "fields": [
14350    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
14351    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
14352    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
14353    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
14354   ]
14355  },
14356  "GB_TILE_MODE0": {
14357   "fields": [
14358    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
14359    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
14360    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
14361    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
14362    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
14363   ]
14364  },
14365  "GCEA_PERFCOUNTER2_MODE": {
14366   "fields": [
14367    {"bits": [0, 1], "name": "COMPARE_MODE0"},
14368    {"bits": [2, 3], "name": "COMPARE_MODE1"},
14369    {"bits": [4, 5], "name": "COMPARE_MODE2"},
14370    {"bits": [6, 7], "name": "COMPARE_MODE3"},
14371    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
14372    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
14373    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
14374    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
14375   ]
14376  },
14377  "GCR_PERFCOUNTER1_SELECT": {
14378   "fields": [
14379    {"bits": [0, 8], "name": "PERF_SEL"},
14380    {"bits": [24, 27], "name": "PERF_MODE"},
14381    {"bits": [28, 31], "name": "CNTL_MODE"}
14382   ]
14383  },
14384  "GC_ATC_L2_PERFCOUNTER0_CFG": {
14385   "fields": [
14386    {"bits": [0, 7], "name": "PERF_SEL"},
14387    {"bits": [8, 15], "name": "PERF_SEL_END"},
14388    {"bits": [24, 27], "name": "PERF_MODE"},
14389    {"bits": [28, 28], "name": "ENABLE"},
14390    {"bits": [29, 29], "name": "CLEAR"}
14391   ]
14392  },
14393  "GC_ATC_L2_PERFCOUNTER_HI": {
14394   "fields": [
14395    {"bits": [0, 15], "name": "COUNTER_HI"},
14396    {"bits": [16, 31], "name": "COMPARE_VALUE"}
14397   ]
14398  },
14399  "GC_ATC_L2_PERFCOUNTER_LO": {
14400   "fields": [
14401    {"bits": [0, 31], "name": "COUNTER_LO"}
14402   ]
14403  },
14404  "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL": {
14405   "fields": [
14406    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
14407    {"bits": [8, 15], "name": "START_TRIGGER"},
14408    {"bits": [16, 23], "name": "STOP_TRIGGER"},
14409    {"bits": [24, 24], "name": "ENABLE_ANY"},
14410    {"bits": [25, 25], "name": "CLEAR_ALL"},
14411    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
14412   ]
14413  },
14414  "GDS_ATOM_BASE": {
14415   "fields": [
14416    {"bits": [0, 15], "name": "BASE"},
14417    {"bits": [16, 31], "name": "UNUSED"}
14418   ]
14419  },
14420  "GDS_ATOM_CNTL": {
14421   "fields": [
14422    {"bits": [0, 5], "name": "AINC"},
14423    {"bits": [6, 7], "name": "UNUSED1"},
14424    {"bits": [8, 9], "name": "DMODE"},
14425    {"bits": [10, 31], "name": "UNUSED2"}
14426   ]
14427  },
14428  "GDS_ATOM_COMPLETE": {
14429   "fields": [
14430    {"bits": [0, 0], "name": "COMPLETE"},
14431    {"bits": [1, 31], "name": "UNUSED"}
14432   ]
14433  },
14434  "GDS_ATOM_DST": {
14435   "fields": [
14436    {"bits": [0, 31], "name": "DST"}
14437   ]
14438  },
14439  "GDS_ATOM_OFFSET0": {
14440   "fields": [
14441    {"bits": [0, 7], "name": "OFFSET0"},
14442    {"bits": [8, 31], "name": "UNUSED"}
14443   ]
14444  },
14445  "GDS_ATOM_OFFSET1": {
14446   "fields": [
14447    {"bits": [0, 7], "name": "OFFSET1"},
14448    {"bits": [8, 31], "name": "UNUSED"}
14449   ]
14450  },
14451  "GDS_ATOM_OP": {
14452   "fields": [
14453    {"bits": [0, 7], "name": "OP"},
14454    {"bits": [8, 31], "name": "UNUSED"}
14455   ]
14456  },
14457  "GDS_ATOM_SIZE": {
14458   "fields": [
14459    {"bits": [0, 15], "name": "SIZE"},
14460    {"bits": [16, 31], "name": "UNUSED"}
14461   ]
14462  },
14463  "GDS_GWS_RESOURCE": {
14464   "fields": [
14465    {"bits": [0, 0], "name": "FLAG"},
14466    {"bits": [1, 12], "name": "COUNTER"},
14467    {"bits": [13, 13], "name": "TYPE"},
14468    {"bits": [14, 14], "name": "DED"},
14469    {"bits": [15, 15], "name": "RELEASE_ALL"},
14470    {"bits": [16, 26], "name": "HEAD_QUEUE"},
14471    {"bits": [27, 27], "name": "HEAD_VALID"},
14472    {"bits": [28, 28], "name": "HEAD_FLAG"},
14473    {"bits": [29, 29], "name": "HALTED"},
14474    {"bits": [30, 31], "name": "UNUSED1"}
14475   ]
14476  },
14477  "GDS_GWS_RESOURCE_CNT": {
14478   "fields": [
14479    {"bits": [0, 15], "name": "RESOURCE_CNT"},
14480    {"bits": [16, 31], "name": "UNUSED"}
14481   ]
14482  },
14483  "GDS_GWS_RESOURCE_CNTL": {
14484   "fields": [
14485    {"bits": [0, 5], "name": "INDEX"},
14486    {"bits": [6, 31], "name": "UNUSED"}
14487   ]
14488  },
14489  "GDS_OA_ADDRESS": {
14490   "fields": [
14491    {"bits": [0, 15], "name": "DS_ADDRESS"},
14492    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
14493    {"bits": [20, 23], "name": "CRAWLER"},
14494    {"bits": [24, 29], "name": "UNUSED"},
14495    {"bits": [30, 30], "name": "NO_ALLOC"},
14496    {"bits": [31, 31], "name": "ENABLE"}
14497   ]
14498  },
14499  "GDS_OA_CNTL": {
14500   "fields": [
14501    {"bits": [0, 3], "name": "INDEX"},
14502    {"bits": [4, 31], "name": "UNUSED"}
14503   ]
14504  },
14505  "GDS_OA_COUNTER": {
14506   "fields": [
14507    {"bits": [0, 31], "name": "SPACE_AVAILABLE"}
14508   ]
14509  },
14510  "GDS_OA_INCDEC": {
14511   "fields": [
14512    {"bits": [0, 30], "name": "VALUE"},
14513    {"bits": [31, 31], "name": "INCDEC"}
14514   ]
14515  },
14516  "GDS_OA_RING_SIZE": {
14517   "fields": [
14518    {"bits": [0, 31], "name": "RING_SIZE"}
14519   ]
14520  },
14521  "GDS_RD_ADDR": {
14522   "fields": [
14523    {"bits": [0, 31], "name": "READ_ADDR"}
14524   ]
14525  },
14526  "GDS_RD_BURST_ADDR": {
14527   "fields": [
14528    {"bits": [0, 31], "name": "BURST_ADDR"}
14529   ]
14530  },
14531  "GDS_RD_BURST_COUNT": {
14532   "fields": [
14533    {"bits": [0, 31], "name": "BURST_COUNT"}
14534   ]
14535  },
14536  "GDS_RD_BURST_DATA": {
14537   "fields": [
14538    {"bits": [0, 31], "name": "BURST_DATA"}
14539   ]
14540  },
14541  "GDS_RD_DATA": {
14542   "fields": [
14543    {"bits": [0, 31], "name": "READ_DATA"}
14544   ]
14545  },
14546  "GDS_WRITE_COMPLETE": {
14547   "fields": [
14548    {"bits": [0, 31], "name": "WRITE_COMPLETE"}
14549   ]
14550  },
14551  "GDS_WR_ADDR": {
14552   "fields": [
14553    {"bits": [0, 31], "name": "WRITE_ADDR"}
14554   ]
14555  },
14556  "GDS_WR_DATA": {
14557   "fields": [
14558    {"bits": [0, 31], "name": "WRITE_DATA"}
14559   ]
14560  },
14561  "GE_CNTL": {
14562   "fields": [
14563    {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
14564    {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
14565    {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
14566    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
14567   ]
14568  },
14569  "GE_DMA_FIRST_INDEX": {
14570   "fields": [
14571    {"bits": [0, 31], "name": "FIRST_INDEX"}
14572   ]
14573  },
14574  "GE_MAX_OUTPUT_PER_SUBGROUP": {
14575   "fields": [
14576    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
14577   ]
14578  },
14579  "GE_NGG_SUBGRP_CNTL": {
14580   "fields": [
14581    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
14582    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
14583   ]
14584  },
14585  "GE_PC_ALLOC": {
14586   "fields": [
14587    {"bits": [0, 0], "name": "OVERSUB_EN"},
14588    {"bits": [1, 10], "name": "NUM_PC_LINES"}
14589   ]
14590  },
14591  "GE_PERFCOUNTER0_SELECT": {
14592   "fields": [
14593    {"bits": [0, 9], "name": "PERF_SEL0"},
14594    {"bits": [10, 19], "name": "PERF_SEL1"},
14595    {"bits": [20, 23], "name": "CNTR_MODE"},
14596    {"bits": [24, 27], "name": "PERF_MODE0"},
14597    {"bits": [28, 31], "name": "PERF_MODE1"}
14598   ]
14599  },
14600  "GE_PERFCOUNTER0_SELECT1": {
14601   "fields": [
14602    {"bits": [0, 9], "name": "PERF_SEL2"},
14603    {"bits": [10, 19], "name": "PERF_SEL3"},
14604    {"bits": [24, 27], "name": "PERF_MODE2"},
14605    {"bits": [28, 31], "name": "PERF_MODE3"}
14606   ]
14607  },
14608  "GE_PERFCOUNTER4_SELECT": {
14609   "fields": [
14610    {"bits": [0, 9], "name": "PERF_SEL0"},
14611    {"bits": [28, 31], "name": "PERF_MODE"}
14612   ]
14613  },
14614  "GE_STEREO_CNTL": {
14615   "fields": [
14616    {"bits": [0, 2], "name": "RT_SLICE"},
14617    {"bits": [3, 6], "name": "VIEWPORT"},
14618    {"bits": [8, 8], "name": "EN_STEREO"}
14619   ]
14620  },
14621  "GE_USER_VGPR_EN": {
14622   "fields": [
14623    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
14624    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
14625    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
14626   ]
14627  },
14628  "GRBM_GFX_INDEX": {
14629   "fields": [
14630    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
14631    {"bits": [8, 15], "name": "SA_INDEX"},
14632    {"bits": [16, 23], "name": "SE_INDEX"},
14633    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
14634    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
14635    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
14636   ]
14637  },
14638  "GRBM_PERFCOUNTER0_SELECT": {
14639   "fields": [
14640    {"bits": [0, 5], "name": "PERF_SEL"},
14641    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14642    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14643    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
14644    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
14645    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14646    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
14647    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
14648    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
14649    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
14650    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
14651    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
14652    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
14653    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14654    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
14655    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14656    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
14657    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
14658    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
14659    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
14660   ]
14661  },
14662  "GRBM_PERFCOUNTER0_SELECT_HI": {
14663   "fields": [
14664    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14665    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
14666    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
14667    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
14668    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
14669    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
14670    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
14671    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14672   ]
14673  },
14674  "GRBM_SE0_PERFCOUNTER_SELECT": {
14675   "fields": [
14676    {"bits": [0, 5], "name": "PERF_SEL"},
14677    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14678    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14679    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
14680    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
14681    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14682    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
14683    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
14684    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
14685    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
14686    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14687    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
14688    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14689    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14690    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14691   ]
14692  },
14693  "GRBM_STATUS": {
14694   "fields": [
14695    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
14696    {"bits": [5, 5], "name": "RSMU_RQ_PENDING"},
14697    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
14698    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
14699    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
14700    {"bits": [12, 12], "name": "DB_CLEAN"},
14701    {"bits": [13, 13], "name": "CB_CLEAN"},
14702    {"bits": [14, 14], "name": "TA_BUSY"},
14703    {"bits": [15, 15], "name": "GDS_BUSY"},
14704    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
14705    {"bits": [20, 20], "name": "SX_BUSY"},
14706    {"bits": [21, 21], "name": "GE_BUSY"},
14707    {"bits": [22, 22], "name": "SPI_BUSY"},
14708    {"bits": [23, 23], "name": "BCI_BUSY"},
14709    {"bits": [24, 24], "name": "SC_BUSY"},
14710    {"bits": [25, 25], "name": "PA_BUSY"},
14711    {"bits": [26, 26], "name": "DB_BUSY"},
14712    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
14713    {"bits": [29, 29], "name": "CP_BUSY"},
14714    {"bits": [30, 30], "name": "CB_BUSY"},
14715    {"bits": [31, 31], "name": "GUI_ACTIVE"}
14716   ]
14717  },
14718  "GRBM_STATUS2": {
14719   "fields": [
14720    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
14721    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
14722    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
14723    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
14724    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
14725    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
14726    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
14727    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
14728    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
14729    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
14730    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
14731    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
14732    {"bits": [15, 15], "name": "UTCL2_BUSY"},
14733    {"bits": [16, 16], "name": "EA_BUSY"},
14734    {"bits": [17, 17], "name": "RMI_BUSY"},
14735    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
14736    {"bits": [19, 19], "name": "CPF_RQ_PENDING"},
14737    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
14738    {"bits": [21, 21], "name": "SDMA_BUSY"},
14739    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
14740    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
14741    {"bits": [24, 24], "name": "RLC_BUSY"},
14742    {"bits": [25, 25], "name": "TCP_BUSY"},
14743    {"bits": [28, 28], "name": "CPF_BUSY"},
14744    {"bits": [29, 29], "name": "CPC_BUSY"},
14745    {"bits": [30, 30], "name": "CPG_BUSY"},
14746    {"bits": [31, 31], "name": "CPAXI_BUSY"}
14747   ]
14748  },
14749  "GRBM_STATUS3": {
14750   "fields": [
14751    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
14752    {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
14753    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
14754    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
14755    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
14756    {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
14757    {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
14758    {"bits": [13, 13], "name": "PH_BUSY"},
14759    {"bits": [14, 14], "name": "CH_BUSY"},
14760    {"bits": [15, 15], "name": "GL2CC_BUSY"},
14761    {"bits": [16, 16], "name": "GL1CC_BUSY"},
14762    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
14763    {"bits": [29, 29], "name": "GUS_BUSY"},
14764    {"bits": [30, 30], "name": "UTCL1_BUSY"},
14765    {"bits": [31, 31], "name": "PMM_BUSY"}
14766   ]
14767  },
14768  "GRBM_STATUS_SE0": {
14769   "fields": [
14770    {"bits": [1, 1], "name": "DB_CLEAN"},
14771    {"bits": [2, 2], "name": "CB_CLEAN"},
14772    {"bits": [3, 3], "name": "UTCL1_BUSY"},
14773    {"bits": [4, 4], "name": "TCP_BUSY"},
14774    {"bits": [5, 5], "name": "GL1CC_BUSY"},
14775    {"bits": [21, 21], "name": "RMI_BUSY"},
14776    {"bits": [22, 22], "name": "BCI_BUSY"},
14777    {"bits": [24, 24], "name": "PA_BUSY"},
14778    {"bits": [25, 25], "name": "TA_BUSY"},
14779    {"bits": [26, 26], "name": "SX_BUSY"},
14780    {"bits": [27, 27], "name": "SPI_BUSY"},
14781    {"bits": [29, 29], "name": "SC_BUSY"},
14782    {"bits": [30, 30], "name": "DB_BUSY"},
14783    {"bits": [31, 31], "name": "CB_BUSY"}
14784   ]
14785  },
14786  "IA_MULTI_VGT_PARAM": {
14787   "fields": [
14788    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14789    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14790    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14791    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14792    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14793    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
14794   ]
14795  },
14796  "IA_MULTI_VGT_PARAM_PIPED": {
14797   "fields": [
14798    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14799    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14800    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14801    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14802    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14803    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
14804    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
14805    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
14806    {"bits": [23, 23], "name": "HW_USE_ONLY"}
14807   ]
14808  },
14809  "PA_CL_CLIP_CNTL": {
14810   "fields": [
14811    {"bits": [0, 0], "name": "UCP_ENA_0"},
14812    {"bits": [1, 1], "name": "UCP_ENA_1"},
14813    {"bits": [2, 2], "name": "UCP_ENA_2"},
14814    {"bits": [3, 3], "name": "UCP_ENA_3"},
14815    {"bits": [4, 4], "name": "UCP_ENA_4"},
14816    {"bits": [5, 5], "name": "UCP_ENA_5"},
14817    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
14818    {"bits": [14, 15], "name": "PS_UCP_MODE"},
14819    {"bits": [16, 16], "name": "CLIP_DISABLE"},
14820    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
14821    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
14822    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
14823    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
14824    {"bits": [21, 21], "name": "VTX_KILL_OR"},
14825    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
14826    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
14827    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
14828    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
14829    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
14830    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
14831   ]
14832  },
14833  "PA_CL_NANINF_CNTL": {
14834   "fields": [
14835    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
14836    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
14837    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
14838    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
14839    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
14840    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
14841    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
14842    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
14843    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
14844    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
14845    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
14846    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
14847    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
14848    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
14849    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
14850    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
14851   ]
14852  },
14853  "PA_CL_NGG_CNTL": {
14854   "fields": [
14855    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
14856    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"}
14857   ]
14858  },
14859  "PA_CL_OBJPRIM_ID_CNTL": {
14860   "fields": [
14861    {"bits": [0, 0], "name": "OBJ_ID_SEL"},
14862    {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}
14863   ]
14864  },
14865  "PA_CL_UCP_0_X": {
14866   "fields": [
14867    {"bits": [0, 31], "name": "DATA_REGISTER"}
14868   ]
14869  },
14870  "PA_CL_VPORT_XOFFSET": {
14871   "fields": [
14872    {"bits": [0, 31], "name": "VPORT_XOFFSET"}
14873   ]
14874  },
14875  "PA_CL_VPORT_XSCALE": {
14876   "fields": [
14877    {"bits": [0, 31], "name": "VPORT_XSCALE"}
14878   ]
14879  },
14880  "PA_CL_VPORT_YOFFSET": {
14881   "fields": [
14882    {"bits": [0, 31], "name": "VPORT_YOFFSET"}
14883   ]
14884  },
14885  "PA_CL_VPORT_YSCALE": {
14886   "fields": [
14887    {"bits": [0, 31], "name": "VPORT_YSCALE"}
14888   ]
14889  },
14890  "PA_CL_VPORT_ZOFFSET": {
14891   "fields": [
14892    {"bits": [0, 31], "name": "VPORT_ZOFFSET"}
14893   ]
14894  },
14895  "PA_CL_VPORT_ZSCALE": {
14896   "fields": [
14897    {"bits": [0, 31], "name": "VPORT_ZSCALE"}
14898   ]
14899  },
14900  "PA_CL_VS_OUT_CNTL": {
14901   "fields": [
14902    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
14903    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
14904    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
14905    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
14906    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
14907    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
14908    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
14909    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
14910    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
14911    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
14912    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
14913    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
14914    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
14915    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
14916    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
14917    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
14918    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
14919    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
14920    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
14921    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
14922    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
14923    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
14924    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
14925    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
14926    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
14927    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
14928    {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"},
14929    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"}
14930   ]
14931  },
14932  "PA_CL_VTE_CNTL": {
14933   "fields": [
14934    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
14935    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
14936    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
14937    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
14938    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
14939    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
14940    {"bits": [8, 8], "name": "VTX_XY_FMT"},
14941    {"bits": [9, 9], "name": "VTX_Z_FMT"},
14942    {"bits": [10, 10], "name": "VTX_W0_FMT"},
14943    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
14944   ]
14945  },
14946  "PA_SC_AA_CONFIG": {
14947   "fields": [
14948    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
14949    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
14950    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
14951    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
14952    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
14953    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}
14954   ]
14955  },
14956  "PA_SC_AA_MASK_X0Y0_X1Y0": {
14957   "fields": [
14958    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
14959    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
14960   ]
14961  },
14962  "PA_SC_AA_MASK_X0Y1_X1Y1": {
14963   "fields": [
14964    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
14965    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
14966   ]
14967  },
14968  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
14969   "fields": [
14970    {"bits": [0, 3], "name": "S0_X"},
14971    {"bits": [4, 7], "name": "S0_Y"},
14972    {"bits": [8, 11], "name": "S1_X"},
14973    {"bits": [12, 15], "name": "S1_Y"},
14974    {"bits": [16, 19], "name": "S2_X"},
14975    {"bits": [20, 23], "name": "S2_Y"},
14976    {"bits": [24, 27], "name": "S3_X"},
14977    {"bits": [28, 31], "name": "S3_Y"}
14978   ]
14979  },
14980  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
14981   "fields": [
14982    {"bits": [0, 3], "name": "S4_X"},
14983    {"bits": [4, 7], "name": "S4_Y"},
14984    {"bits": [8, 11], "name": "S5_X"},
14985    {"bits": [12, 15], "name": "S5_Y"},
14986    {"bits": [16, 19], "name": "S6_X"},
14987    {"bits": [20, 23], "name": "S6_Y"},
14988    {"bits": [24, 27], "name": "S7_X"},
14989    {"bits": [28, 31], "name": "S7_Y"}
14990   ]
14991  },
14992  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
14993   "fields": [
14994    {"bits": [0, 3], "name": "S8_X"},
14995    {"bits": [4, 7], "name": "S8_Y"},
14996    {"bits": [8, 11], "name": "S9_X"},
14997    {"bits": [12, 15], "name": "S9_Y"},
14998    {"bits": [16, 19], "name": "S10_X"},
14999    {"bits": [20, 23], "name": "S10_Y"},
15000    {"bits": [24, 27], "name": "S11_X"},
15001    {"bits": [28, 31], "name": "S11_Y"}
15002   ]
15003  },
15004  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
15005   "fields": [
15006    {"bits": [0, 3], "name": "S12_X"},
15007    {"bits": [4, 7], "name": "S12_Y"},
15008    {"bits": [8, 11], "name": "S13_X"},
15009    {"bits": [12, 15], "name": "S13_Y"},
15010    {"bits": [16, 19], "name": "S14_X"},
15011    {"bits": [20, 23], "name": "S14_Y"},
15012    {"bits": [24, 27], "name": "S15_X"},
15013    {"bits": [28, 31], "name": "S15_Y"}
15014   ]
15015  },
15016  "PA_SC_BINNER_CNTL_0": {
15017   "fields": [
15018    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
15019    {"bits": [2, 2], "name": "BIN_SIZE_X"},
15020    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
15021    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
15022    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
15023    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
15024    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
15025    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
15026    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
15027    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
15028    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
15029    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
15030   ]
15031  },
15032  "PA_SC_BINNER_CNTL_1": {
15033   "fields": [
15034    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
15035    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
15036   ]
15037  },
15038  "PA_SC_CENTROID_PRIORITY_0": {
15039   "fields": [
15040    {"bits": [0, 3], "name": "DISTANCE_0"},
15041    {"bits": [4, 7], "name": "DISTANCE_1"},
15042    {"bits": [8, 11], "name": "DISTANCE_2"},
15043    {"bits": [12, 15], "name": "DISTANCE_3"},
15044    {"bits": [16, 19], "name": "DISTANCE_4"},
15045    {"bits": [20, 23], "name": "DISTANCE_5"},
15046    {"bits": [24, 27], "name": "DISTANCE_6"},
15047    {"bits": [28, 31], "name": "DISTANCE_7"}
15048   ]
15049  },
15050  "PA_SC_CENTROID_PRIORITY_1": {
15051   "fields": [
15052    {"bits": [0, 3], "name": "DISTANCE_8"},
15053    {"bits": [4, 7], "name": "DISTANCE_9"},
15054    {"bits": [8, 11], "name": "DISTANCE_10"},
15055    {"bits": [12, 15], "name": "DISTANCE_11"},
15056    {"bits": [16, 19], "name": "DISTANCE_12"},
15057    {"bits": [20, 23], "name": "DISTANCE_13"},
15058    {"bits": [24, 27], "name": "DISTANCE_14"},
15059    {"bits": [28, 31], "name": "DISTANCE_15"}
15060   ]
15061  },
15062  "PA_SC_CLIPRECT_0_TL": {
15063   "fields": [
15064    {"bits": [0, 14], "name": "TL_X"},
15065    {"bits": [16, 30], "name": "TL_Y"}
15066   ]
15067  },
15068  "PA_SC_CLIPRECT_RULE": {
15069   "fields": [
15070    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
15071   ]
15072  },
15073  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
15074   "fields": [
15075    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
15076    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
15077    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
15078    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
15079    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
15080    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
15081    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
15082    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
15083    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
15084    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
15085    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
15086    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
15087    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
15088    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
15089    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
15090    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
15091    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
15092    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
15093    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
15094    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
15095   ]
15096  },
15097  "PA_SC_EDGERULE": {
15098   "fields": [
15099    {"bits": [0, 3], "name": "ER_TRI"},
15100    {"bits": [4, 7], "name": "ER_POINT"},
15101    {"bits": [8, 11], "name": "ER_RECT"},
15102    {"bits": [12, 17], "name": "ER_LINE_LR"},
15103    {"bits": [18, 23], "name": "ER_LINE_RL"},
15104    {"bits": [24, 27], "name": "ER_LINE_TB"},
15105    {"bits": [28, 31], "name": "ER_LINE_BT"}
15106   ]
15107  },
15108  "PA_SC_HORIZ_GRID": {
15109   "fields": [
15110    {"bits": [0, 7], "name": "TOP_QTR"},
15111    {"bits": [8, 15], "name": "TOP_HALF"},
15112    {"bits": [16, 23], "name": "BOT_HALF"},
15113    {"bits": [24, 31], "name": "BOT_QTR"}
15114   ]
15115  },
15116  "PA_SC_LINE_CNTL": {
15117   "fields": [
15118    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
15119    {"bits": [10, 10], "name": "LAST_PIXEL"},
15120    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
15121    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
15122    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
15123   ]
15124  },
15125  "PA_SC_LINE_STIPPLE": {
15126   "fields": [
15127    {"bits": [0, 15], "name": "LINE_PATTERN"},
15128    {"bits": [16, 23], "name": "REPEAT_COUNT"},
15129    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
15130    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
15131   ]
15132  },
15133  "PA_SC_LINE_STIPPLE_STATE": {
15134   "fields": [
15135    {"bits": [0, 3], "name": "CURRENT_PTR"},
15136    {"bits": [8, 15], "name": "CURRENT_COUNT"}
15137   ]
15138  },
15139  "PA_SC_MODE_CNTL_0": {
15140   "fields": [
15141    {"bits": [0, 0], "name": "MSAA_ENABLE"},
15142    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
15143    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
15144    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
15145    {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"},
15146    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
15147    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
15148   ]
15149  },
15150  "PA_SC_MODE_CNTL_1": {
15151   "fields": [
15152    {"bits": [0, 0], "name": "WALK_SIZE"},
15153    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
15154    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
15155    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
15156    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
15157    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
15158    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
15159    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
15160    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
15161    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
15162    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
15163    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
15164    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
15165    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
15166    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
15167    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
15168    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
15169    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
15170    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
15171    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
15172    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
15173    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
15174    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
15175    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
15176   ]
15177  },
15178  "PA_SC_NGG_MODE_CNTL": {
15179   "fields": [
15180    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
15181    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
15182   ]
15183  },
15184  "PA_SC_P3D_TRAP_SCREEN_H": {
15185   "fields": [
15186    {"bits": [0, 13], "name": "X_COORD"}
15187   ]
15188  },
15189  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
15190   "fields": [
15191    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
15192    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
15193   ]
15194  },
15195  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
15196   "fields": [
15197    {"bits": [0, 15], "name": "COUNT"}
15198   ]
15199  },
15200  "PA_SC_P3D_TRAP_SCREEN_V": {
15201   "fields": [
15202    {"bits": [0, 13], "name": "Y_COORD"}
15203   ]
15204  },
15205  "PA_SC_PERFCOUNTER1_SELECT": {
15206   "fields": [
15207    {"bits": [0, 9], "name": "PERF_SEL"}
15208   ]
15209  },
15210  "PA_SC_RASTER_CONFIG": {
15211   "fields": [
15212    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
15213    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
15214    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
15215    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
15216    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
15217    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
15218    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
15219    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
15220    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
15221    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
15222    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
15223    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
15224    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
15225    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
15226    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
15227   ]
15228  },
15229  "PA_SC_RASTER_CONFIG_1": {
15230   "fields": [
15231    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
15232    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
15233    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
15234   ]
15235  },
15236  "PA_SC_RIGHT_VERT_GRID": {
15237   "fields": [
15238    {"bits": [0, 7], "name": "LEFT_QTR"},
15239    {"bits": [8, 15], "name": "LEFT_HALF"},
15240    {"bits": [16, 23], "name": "RIGHT_HALF"},
15241    {"bits": [24, 31], "name": "RIGHT_QTR"}
15242   ]
15243  },
15244  "PA_SC_SCREEN_EXTENT_CONTROL": {
15245   "fields": [
15246    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
15247    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
15248   ]
15249  },
15250  "PA_SC_SCREEN_EXTENT_MIN_0": {
15251   "fields": [
15252    {"bits": [0, 15], "name": "X"},
15253    {"bits": [16, 31], "name": "Y"}
15254   ]
15255  },
15256  "PA_SC_SCREEN_SCISSOR_BR": {
15257   "fields": [
15258    {"bits": [0, 15], "name": "BR_X"},
15259    {"bits": [16, 31], "name": "BR_Y"}
15260   ]
15261  },
15262  "PA_SC_SCREEN_SCISSOR_TL": {
15263   "fields": [
15264    {"bits": [0, 15], "name": "TL_X"},
15265    {"bits": [16, 31], "name": "TL_Y"}
15266   ]
15267  },
15268  "PA_SC_SHADER_CONTROL": {
15269   "fields": [
15270    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
15271    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
15272    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
15273    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
15274   ]
15275  },
15276  "PA_SC_TILE_STEERING_OVERRIDE": {
15277   "fields": [
15278    {"bits": [0, 0], "name": "ENABLE"},
15279    {"bits": [1, 2], "name": "NUM_SE"},
15280    {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
15281    {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"},
15282    {"bits": [12, 13], "name": "NUM_SC"},
15283    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
15284    {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"}
15285   ]
15286  },
15287  "PA_SC_VPORT_ZMAX_0": {
15288   "fields": [
15289    {"bits": [0, 31], "name": "VPORT_ZMAX"}
15290   ]
15291  },
15292  "PA_SC_VPORT_ZMIN_0": {
15293   "fields": [
15294    {"bits": [0, 31], "name": "VPORT_ZMIN"}
15295   ]
15296  },
15297  "PA_SC_WINDOW_OFFSET": {
15298   "fields": [
15299    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
15300    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
15301   ]
15302  },
15303  "PA_SC_WINDOW_SCISSOR_BR": {
15304   "fields": [
15305    {"bits": [0, 14], "name": "BR_X"},
15306    {"bits": [16, 30], "name": "BR_Y"}
15307   ]
15308  },
15309  "PA_SC_WINDOW_SCISSOR_TL": {
15310   "fields": [
15311    {"bits": [0, 14], "name": "TL_X"},
15312    {"bits": [16, 30], "name": "TL_Y"},
15313    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
15314   ]
15315  },
15316  "PA_STATE_STEREO_X": {
15317   "fields": [
15318    {"bits": [0, 31], "name": "STEREO_X_OFFSET"}
15319   ]
15320  },
15321  "PA_STEREO_CNTL": {
15322   "fields": [
15323    {"bits": [1, 4], "name": "STEREO_MODE"},
15324    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
15325    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
15326    {"bits": [16, 18], "name": "VP_ID_MODE"},
15327    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
15328   ]
15329  },
15330  "PA_SU_HARDWARE_SCREEN_OFFSET": {
15331   "fields": [
15332    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
15333    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
15334   ]
15335  },
15336  "PA_SU_LINE_CNTL": {
15337   "fields": [
15338    {"bits": [0, 15], "name": "WIDTH"}
15339   ]
15340  },
15341  "PA_SU_LINE_STIPPLE_CNTL": {
15342   "fields": [
15343    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
15344    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
15345    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
15346    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
15347   ]
15348  },
15349  "PA_SU_LINE_STIPPLE_SCALE": {
15350   "fields": [
15351    {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"}
15352   ]
15353  },
15354  "PA_SU_LINE_STIPPLE_VALUE": {
15355   "fields": [
15356    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
15357   ]
15358  },
15359  "PA_SU_OVER_RASTERIZATION_CNTL": {
15360   "fields": [
15361    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
15362    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
15363    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
15364    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
15365    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
15366   ]
15367  },
15368  "PA_SU_PERFCOUNTER0_HI": {
15369   "fields": [
15370    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
15371   ]
15372  },
15373  "PA_SU_PERFCOUNTER0_SELECT": {
15374   "fields": [
15375    {"bits": [0, 9], "name": "PERF_SEL"},
15376    {"bits": [10, 19], "name": "PERF_SEL1"},
15377    {"bits": [20, 23], "name": "CNTR_MODE"},
15378    {"bits": [24, 27], "name": "PERF_MODE1"},
15379    {"bits": [28, 31], "name": "PERF_MODE"}
15380   ]
15381  },
15382  "PA_SU_PERFCOUNTER0_SELECT1": {
15383   "fields": [
15384    {"bits": [0, 9], "name": "PERF_SEL2"},
15385    {"bits": [10, 19], "name": "PERF_SEL3"},
15386    {"bits": [24, 27], "name": "PERF_MODE3"},
15387    {"bits": [28, 31], "name": "PERF_MODE2"}
15388   ]
15389  },
15390  "PA_SU_POINT_MINMAX": {
15391   "fields": [
15392    {"bits": [0, 15], "name": "MIN_SIZE"},
15393    {"bits": [16, 31], "name": "MAX_SIZE"}
15394   ]
15395  },
15396  "PA_SU_POINT_SIZE": {
15397   "fields": [
15398    {"bits": [0, 15], "name": "HEIGHT"},
15399    {"bits": [16, 31], "name": "WIDTH"}
15400   ]
15401  },
15402  "PA_SU_POLY_OFFSET_CLAMP": {
15403   "fields": [
15404    {"bits": [0, 31], "name": "CLAMP"}
15405   ]
15406  },
15407  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
15408   "fields": [
15409    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
15410    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
15411   ]
15412  },
15413  "PA_SU_POLY_OFFSET_FRONT_SCALE": {
15414   "fields": [
15415    {"bits": [0, 31], "name": "SCALE"}
15416   ]
15417  },
15418  "PA_SU_PRIM_FILTER_CNTL": {
15419   "fields": [
15420    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
15421    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
15422    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
15423    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
15424    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
15425    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
15426    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
15427    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
15428    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
15429    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
15430    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
15431   ]
15432  },
15433  "PA_SU_SC_MODE_CNTL": {
15434   "fields": [
15435    {"bits": [0, 0], "name": "CULL_FRONT"},
15436    {"bits": [1, 1], "name": "CULL_BACK"},
15437    {"bits": [2, 2], "name": "FACE"},
15438    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
15439    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
15440    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
15441    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
15442    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
15443    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
15444    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
15445    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
15446    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
15447    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
15448    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
15449    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
15450    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
15451   ]
15452  },
15453  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
15454   "fields": [
15455    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
15456    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
15457    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
15458    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
15459    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"},
15460    {"bits": [5, 5], "name": "SRBSL_ENABLE"},
15461    {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"}
15462   ]
15463  },
15464  "PA_SU_VTX_CNTL": {
15465   "fields": [
15466    {"bits": [0, 0], "name": "PIX_CENTER"},
15467    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
15468    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
15469   ]
15470  },
15471  "RLC_GPM_PERF_COUNT_0": {
15472   "fields": [
15473    {"bits": [0, 3], "name": "FEATURE_SEL"},
15474    {"bits": [4, 7], "name": "SE_INDEX"},
15475    {"bits": [8, 11], "name": "SA_INDEX"},
15476    {"bits": [12, 15], "name": "WGP_INDEX"},
15477    {"bits": [16, 17], "name": "EVENT_SEL"},
15478    {"bits": [18, 19], "name": "UNUSED"},
15479    {"bits": [20, 20], "name": "ENABLE"},
15480    {"bits": [21, 31], "name": "RESERVED"}
15481   ]
15482  },
15483  "RLC_GPU_IOV_PERF_CNT_CNTL": {
15484   "fields": [
15485    {"bits": [0, 0], "name": "ENABLE"},
15486    {"bits": [1, 1], "name": "MODE_SELECT"},
15487    {"bits": [2, 2], "name": "RESET"},
15488    {"bits": [3, 31], "name": "RESERVED"}
15489   ]
15490  },
15491  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
15492   "fields": [
15493    {"bits": [0, 3], "name": "VFID"},
15494    {"bits": [4, 5], "name": "CNT_ID"},
15495    {"bits": [6, 31], "name": "RESERVED"}
15496   ]
15497  },
15498  "RLC_PERFCOUNTER0_SELECT": {
15499   "fields": [
15500    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
15501   ]
15502  },
15503  "RLC_PERFMON_CLK_CNTL": {
15504   "fields": [
15505    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
15506   ]
15507  },
15508  "RLC_PERFMON_CNTL": {
15509   "fields": [
15510    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
15511    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
15512   ]
15513  },
15514  "RLC_SPM_ACCUM_CTRL": {
15515   "fields": [
15516    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
15517    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
15518    {"bits": [2, 2], "name": "StrobeRearmAccum"},
15519    {"bits": [3, 3], "name": "StrobeSpmDoneInt"},
15520    {"bits": [4, 4], "name": "StrobeAccumDoneInt"},
15521    {"bits": [5, 5], "name": "StrobeResetAccum"},
15522    {"bits": [6, 9], "name": "StrobeStartSpm"},
15523    {"bits": [10, 31], "name": "RESERVED"}
15524   ]
15525  },
15526  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
15527   "fields": [
15528    {"bits": [0, 8], "name": "addr"},
15529    {"bits": [9, 31], "name": "RESERVED"}
15530   ]
15531  },
15532  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
15533   "fields": [
15534    {"bits": [0, 7], "name": "data"},
15535    {"bits": [8, 31], "name": "RESERVED"}
15536   ]
15537  },
15538  "RLC_SPM_ACCUM_DATARAM_ADDR": {
15539   "fields": [
15540    {"bits": [0, 6], "name": "addr"},
15541    {"bits": [7, 31], "name": "RESERVED"}
15542   ]
15543  },
15544  "RLC_SPM_ACCUM_DATARAM_DATA": {
15545   "fields": [
15546    {"bits": [0, 31], "name": "data"}
15547   ]
15548  },
15549  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
15550   "fields": [
15551    {"bits": [0, 18], "name": "DataRamWrCount"},
15552    {"bits": [19, 31], "name": "RESERVED"}
15553   ]
15554  },
15555  "RLC_SPM_ACCUM_MODE": {
15556   "fields": [
15557    {"bits": [0, 0], "name": "EnableAccum"},
15558    {"bits": [1, 1], "name": "AutoAccumEn"},
15559    {"bits": [2, 2], "name": "AutoSpmEn"},
15560    {"bits": [3, 3], "name": "Globals_LoadOverride"},
15561    {"bits": [4, 4], "name": "SE0_LoadOverride"},
15562    {"bits": [5, 5], "name": "SE1_LoadOverride"},
15563    {"bits": [6, 6], "name": "AutoResetPerfmonDisable"},
15564    {"bits": [7, 31], "name": "RESERVED"}
15565   ]
15566  },
15567  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
15568   "fields": [
15569    {"bits": [0, 7], "name": "SamplesRequested"},
15570    {"bits": [8, 31], "name": "RESERVED"}
15571   ]
15572  },
15573  "RLC_SPM_ACCUM_STATUS": {
15574   "fields": [
15575    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
15576    {"bits": [8, 8], "name": "AccumDone"},
15577    {"bits": [9, 9], "name": "SpmDone"},
15578    {"bits": [10, 10], "name": "AccumOverflow"},
15579    {"bits": [11, 11], "name": "AccumArmed"},
15580    {"bits": [12, 12], "name": "SequenceInProgress"},
15581    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
15582    {"bits": [14, 14], "name": "AllFifosEmpty"},
15583    {"bits": [15, 15], "name": "FSMIsIdle"},
15584    {"bits": [16, 31], "name": "RESERVED"}
15585   ]
15586  },
15587  "RLC_SPM_ACCUM_THRESHOLD": {
15588   "fields": [
15589    {"bits": [0, 15], "name": "Threshold"},
15590    {"bits": [16, 31], "name": "RESERVED"}
15591   ]
15592  },
15593  "RLC_SPM_DESER_START_SKEW": {
15594   "fields": [
15595    {"bits": [0, 6], "name": "DESER_START_SKEW"},
15596    {"bits": [7, 31], "name": "RESERVED"}
15597   ]
15598  },
15599  "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR": {
15600   "fields": [
15601    {"bits": [0, 31], "name": "GLB_SAMPLEDELAY_INDEX"}
15602   ]
15603  },
15604  "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
15605   "fields": [
15606    {"bits": [0, 6], "name": "data"},
15607    {"bits": [7, 31], "name": "RESERVED"}
15608   ]
15609  },
15610  "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
15611   "fields": [
15612    {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
15613    {"bits": [7, 31], "name": "RESERVED"}
15614   ]
15615  },
15616  "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
15617   "fields": [
15618    {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
15619    {"bits": [7, 31], "name": "RESERVED"}
15620   ]
15621  },
15622  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
15623   "fields": [
15624    {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
15625    {"bits": [8, 31], "name": "RESERVED"}
15626   ]
15627  },
15628  "RLC_SPM_PERFMON_CNTL": {
15629   "fields": [
15630    {"bits": [0, 11], "name": "RESERVED1"},
15631    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
15632    {"bits": [14, 15], "name": "RESERVED"},
15633    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
15634   ]
15635  },
15636  "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
15637   "fields": [
15638    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15639    {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
15640    {"bits": [16, 31], "name": "RESERVED"}
15641   ]
15642  },
15643  "RLC_SPM_PERFMON_RING_BASE_HI": {
15644   "fields": [
15645    {"bits": [0, 15], "name": "RING_BASE_HI"},
15646    {"bits": [16, 31], "name": "RESERVED"}
15647   ]
15648  },
15649  "RLC_SPM_PERFMON_RING_BASE_LO": {
15650   "fields": [
15651    {"bits": [0, 31], "name": "RING_BASE_LO"}
15652   ]
15653  },
15654  "RLC_SPM_PERFMON_RING_SIZE": {
15655   "fields": [
15656    {"bits": [0, 31], "name": "RING_BASE_SIZE"}
15657   ]
15658  },
15659  "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
15660   "fields": [
15661    {"bits": [0, 7], "name": "SE0_NUM_LINE"},
15662    {"bits": [8, 15], "name": "SE1_NUM_LINE"},
15663    {"bits": [16, 23], "name": "SE2_NUM_LINE"},
15664    {"bits": [24, 31], "name": "SE3_NUM_LINE"}
15665   ]
15666  },
15667  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
15668   "fields": [
15669    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15670    {"bits": [8, 10], "name": "RESERVED1"},
15671    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
15672    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
15673    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
15674    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
15675    {"bits": [31, 31], "name": "RESERVED"}
15676   ]
15677  },
15678  "RLC_SPM_RING_RDPTR": {
15679   "fields": [
15680    {"bits": [0, 31], "name": "PERFMON_RING_RDPTR"}
15681   ]
15682  },
15683  "RLC_SPM_RING_WRPTR": {
15684   "fields": [
15685    {"bits": [0, 4], "name": "RESERVED"},
15686    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
15687   ]
15688  },
15689  "RLC_SPM_SEGMENT_THRESHOLD": {
15690   "fields": [
15691    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
15692    {"bits": [8, 31], "name": "RESERVED"}
15693   ]
15694  },
15695  "RLC_SPM_SE_MUXSEL_ADDR": {
15696   "fields": [
15697    {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
15698    {"bits": [9, 31], "name": "RESERVED"}
15699   ]
15700  },
15701  "RLC_SPM_SE_MUXSEL_DATA": {
15702   "fields": [
15703    {"bits": [0, 31], "name": "PERFMON_SEL_DATA"}
15704   ]
15705  },
15706  "RLC_SPM_SE_MUXSEL_SKEW": {
15707   "fields": [
15708    {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
15709    {"bits": [7, 31], "name": "RESERVED"}
15710   ]
15711  },
15712  "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR": {
15713   "fields": [
15714    {"bits": [0, 31], "name": "SE_SAMPLEDELAY_INDEX"}
15715   ]
15716  },
15717  "RLC_SPM_SE_SAMPLE_SKEW": {
15718   "fields": [
15719    {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
15720    {"bits": [7, 31], "name": "RESERVED"}
15721   ]
15722  },
15723  "RLC_SPM_VIRT_CTRL": {
15724   "fields": [
15725    {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
15726   ]
15727  },
15728  "RLC_SPM_VIRT_STATUS": {
15729   "fields": [
15730    {"bits": [0, 0], "name": "SpmSamplingPaused"}
15731   ]
15732  },
15733  "RMI_PERF_COUNTER_CNTL": {
15734   "fields": [
15735    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
15736    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
15737    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
15738    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
15739    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
15740    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
15741    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
15742    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
15743    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
15744    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
15745   ]
15746  },
15747  "SCRATCH_ADDR": {
15748   "fields": [
15749    {"bits": [0, 31], "name": "OBSOLETE_ADDR"}
15750   ]
15751  },
15752  "SCRATCH_REG0": {
15753   "fields": [
15754    {"bits": [0, 31], "name": "SCRATCH_REG0"}
15755   ]
15756  },
15757  "SCRATCH_REG1": {
15758   "fields": [
15759    {"bits": [0, 31], "name": "SCRATCH_REG1"}
15760   ]
15761  },
15762  "SCRATCH_REG2": {
15763   "fields": [
15764    {"bits": [0, 31], "name": "SCRATCH_REG2"}
15765   ]
15766  },
15767  "SCRATCH_REG3": {
15768   "fields": [
15769    {"bits": [0, 31], "name": "SCRATCH_REG3"}
15770   ]
15771  },
15772  "SCRATCH_REG4": {
15773   "fields": [
15774    {"bits": [0, 31], "name": "SCRATCH_REG4"}
15775   ]
15776  },
15777  "SCRATCH_REG5": {
15778   "fields": [
15779    {"bits": [0, 31], "name": "SCRATCH_REG5"}
15780   ]
15781  },
15782  "SCRATCH_REG6": {
15783   "fields": [
15784    {"bits": [0, 31], "name": "SCRATCH_REG6"}
15785   ]
15786  },
15787  "SCRATCH_REG7": {
15788   "fields": [
15789    {"bits": [0, 31], "name": "SCRATCH_REG7"}
15790   ]
15791  },
15792  "SCRATCH_UMSK": {
15793   "fields": [
15794    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
15795    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
15796   ]
15797  },
15798  "SPI_BARYC_CNTL": {
15799   "fields": [
15800    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
15801    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
15802    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
15803    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
15804    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
15805    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
15806    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
15807   ]
15808  },
15809  "SPI_CONFIG_CNTL": {
15810   "fields": [
15811    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
15812    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
15813    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
15814    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
15815    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
15816    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
15817    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
15818    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
15819    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
15820   ]
15821  },
15822  "SPI_CONFIG_CNTL_REMAP": {
15823   "fields": [
15824    {"bits": [0, 31], "name": "RESERVED"}
15825   ]
15826  },
15827  "SPI_INTERP_CONTROL_0": {
15828   "fields": [
15829    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
15830    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
15831    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
15832    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
15833    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
15834    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
15835    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
15836   ]
15837  },
15838  "SPI_PERFCOUNTER_BINS": {
15839   "fields": [
15840    {"bits": [0, 3], "name": "BIN0_MIN"},
15841    {"bits": [4, 7], "name": "BIN0_MAX"},
15842    {"bits": [8, 11], "name": "BIN1_MIN"},
15843    {"bits": [12, 15], "name": "BIN1_MAX"},
15844    {"bits": [16, 19], "name": "BIN2_MIN"},
15845    {"bits": [20, 23], "name": "BIN2_MAX"},
15846    {"bits": [24, 27], "name": "BIN3_MIN"},
15847    {"bits": [28, 31], "name": "BIN3_MAX"}
15848   ]
15849  },
15850  "SPI_PS_INPUT_CNTL_0": {
15851   "fields": [
15852    {"bits": [0, 5], "name": "OFFSET"},
15853    {"bits": [8, 9], "name": "DEFAULT_VAL"},
15854    {"bits": [10, 10], "name": "FLAT_SHADE"},
15855    {"bits": [13, 16], "name": "CYL_WRAP"},
15856    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
15857    {"bits": [18, 18], "name": "DUP"},
15858    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15859    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15860    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15861    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
15862    {"bits": [24, 24], "name": "ATTR0_VALID"},
15863    {"bits": [25, 25], "name": "ATTR1_VALID"}
15864   ]
15865  },
15866  "SPI_PS_INPUT_CNTL_20": {
15867   "fields": [
15868    {"bits": [0, 5], "name": "OFFSET"},
15869    {"bits": [8, 9], "name": "DEFAULT_VAL"},
15870    {"bits": [10, 10], "name": "FLAT_SHADE"},
15871    {"bits": [18, 18], "name": "DUP"},
15872    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15873    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15874    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15875    {"bits": [24, 24], "name": "ATTR0_VALID"},
15876    {"bits": [25, 25], "name": "ATTR1_VALID"}
15877   ]
15878  },
15879  "SPI_PS_INPUT_ENA": {
15880   "fields": [
15881    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
15882    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
15883    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
15884    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
15885    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
15886    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
15887    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
15888    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
15889    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
15890    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
15891    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
15892    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
15893    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
15894    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
15895    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
15896    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
15897   ]
15898  },
15899  "SPI_PS_IN_CONTROL": {
15900   "fields": [
15901    {"bits": [0, 5], "name": "NUM_INTERP"},
15902    {"bits": [6, 6], "name": "PARAM_GEN"},
15903    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
15904    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
15905    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
15906    {"bits": [15, 15], "name": "PS_W32_EN"}
15907   ]
15908  },
15909  "SPI_SHADER_COL_FORMAT": {
15910   "fields": [
15911    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
15912    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
15913    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
15914    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
15915    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
15916    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
15917    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
15918    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
15919   ]
15920  },
15921  "SPI_SHADER_IDX_FORMAT": {
15922   "fields": [
15923    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
15924   ]
15925  },
15926  "SPI_SHADER_LATE_ALLOC_VS": {
15927   "fields": [
15928    {"bits": [0, 5], "name": "LIMIT"}
15929   ]
15930  },
15931  "SPI_SHADER_PGM_CHKSUM_PS": {
15932   "fields": [
15933    {"bits": [0, 31], "name": "CHECKSUM"}
15934   ]
15935  },
15936  "SPI_SHADER_PGM_HI_PS": {
15937   "fields": [
15938    {"bits": [0, 7], "name": "MEM_BASE"}
15939   ]
15940  },
15941  "SPI_SHADER_PGM_LO_PS": {
15942   "fields": [
15943    {"bits": [0, 31], "name": "MEM_BASE"}
15944   ]
15945  },
15946  "SPI_SHADER_PGM_RSRC1_ES": {
15947   "fields": [
15948    {"bits": [0, 5], "name": "VGPRS"},
15949    {"bits": [6, 9], "name": "SGPRS"},
15950    {"bits": [10, 11], "name": "PRIORITY"},
15951    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15952    {"bits": [20, 20], "name": "PRIV"},
15953    {"bits": [21, 21], "name": "DX10_CLAMP"},
15954    {"bits": [23, 23], "name": "IEEE_MODE"},
15955    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
15956    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
15957    {"bits": [31, 31], "name": "FP16_OVFL"}
15958   ]
15959  },
15960  "SPI_SHADER_PGM_RSRC1_GS": {
15961   "fields": [
15962    {"bits": [0, 5], "name": "VGPRS"},
15963    {"bits": [6, 9], "name": "SGPRS"},
15964    {"bits": [10, 11], "name": "PRIORITY"},
15965    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15966    {"bits": [20, 20], "name": "PRIV"},
15967    {"bits": [21, 21], "name": "DX10_CLAMP"},
15968    {"bits": [23, 23], "name": "IEEE_MODE"},
15969    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
15970    {"bits": [25, 25], "name": "MEM_ORDERED"},
15971    {"bits": [26, 26], "name": "FWD_PROGRESS"},
15972    {"bits": [27, 27], "name": "WGP_MODE"},
15973    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
15974    {"bits": [31, 31], "name": "FP16_OVFL"}
15975   ]
15976  },
15977  "SPI_SHADER_PGM_RSRC1_HS": {
15978   "fields": [
15979    {"bits": [0, 5], "name": "VGPRS"},
15980    {"bits": [6, 9], "name": "SGPRS"},
15981    {"bits": [10, 11], "name": "PRIORITY"},
15982    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15983    {"bits": [20, 20], "name": "PRIV"},
15984    {"bits": [21, 21], "name": "DX10_CLAMP"},
15985    {"bits": [23, 23], "name": "IEEE_MODE"},
15986    {"bits": [24, 24], "name": "MEM_ORDERED"},
15987    {"bits": [25, 25], "name": "FWD_PROGRESS"},
15988    {"bits": [26, 26], "name": "WGP_MODE"},
15989    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
15990    {"bits": [30, 30], "name": "FP16_OVFL"}
15991   ]
15992  },
15993  "SPI_SHADER_PGM_RSRC1_LS": {
15994   "fields": [
15995    {"bits": [0, 5], "name": "VGPRS"},
15996    {"bits": [6, 9], "name": "SGPRS"},
15997    {"bits": [10, 11], "name": "PRIORITY"},
15998    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15999    {"bits": [20, 20], "name": "PRIV"},
16000    {"bits": [21, 21], "name": "DX10_CLAMP"},
16001    {"bits": [23, 23], "name": "IEEE_MODE"},
16002    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
16003    {"bits": [30, 30], "name": "FP16_OVFL"}
16004   ]
16005  },
16006  "SPI_SHADER_PGM_RSRC1_PS": {
16007   "fields": [
16008    {"bits": [0, 5], "name": "VGPRS"},
16009    {"bits": [6, 9], "name": "SGPRS"},
16010    {"bits": [10, 11], "name": "PRIORITY"},
16011    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
16012    {"bits": [20, 20], "name": "PRIV"},
16013    {"bits": [21, 21], "name": "DX10_CLAMP"},
16014    {"bits": [23, 23], "name": "IEEE_MODE"},
16015    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
16016    {"bits": [25, 25], "name": "MEM_ORDERED"},
16017    {"bits": [26, 26], "name": "FWD_PROGRESS"},
16018    {"bits": [29, 29], "name": "FP16_OVFL"}
16019   ]
16020  },
16021  "SPI_SHADER_PGM_RSRC1_VS": {
16022   "fields": [
16023    {"bits": [0, 5], "name": "VGPRS"},
16024    {"bits": [6, 9], "name": "SGPRS"},
16025    {"bits": [10, 11], "name": "PRIORITY"},
16026    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
16027    {"bits": [20, 20], "name": "PRIV"},
16028    {"bits": [21, 21], "name": "DX10_CLAMP"},
16029    {"bits": [23, 23], "name": "IEEE_MODE"},
16030    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
16031    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
16032    {"bits": [27, 27], "name": "MEM_ORDERED"},
16033    {"bits": [28, 28], "name": "FWD_PROGRESS"},
16034    {"bits": [31, 31], "name": "FP16_OVFL"}
16035   ]
16036  },
16037  "SPI_SHADER_PGM_RSRC2_ES_VS": {
16038   "fields": [
16039    {"bits": [0, 0], "name": "SCRATCH_EN"},
16040    {"bits": [1, 5], "name": "USER_SGPR"},
16041    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16042    {"bits": [7, 7], "name": "OC_LDS_EN"},
16043    {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16044    {"bits": [20, 28], "name": "LDS_SIZE"}
16045   ]
16046  },
16047  "SPI_SHADER_PGM_RSRC2_GS": {
16048   "fields": [
16049    {"bits": [0, 0], "name": "SCRATCH_EN"},
16050    {"bits": [1, 5], "name": "USER_SGPR"},
16051    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16052    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16053    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
16054    {"bits": [18, 18], "name": "OC_LDS_EN"},
16055    {"bits": [19, 26], "name": "LDS_SIZE"},
16056    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16057    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16058   ]
16059  },
16060  "SPI_SHADER_PGM_RSRC2_GS_VS": {
16061   "fields": [
16062    {"bits": [0, 0], "name": "SCRATCH_EN"},
16063    {"bits": [1, 5], "name": "USER_SGPR"},
16064    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16065    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16066    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
16067    {"bits": [18, 18], "name": "OC_LDS_EN"},
16068    {"bits": [19, 26], "name": "LDS_SIZE"},
16069    {"bits": [27, 27], "name": "SKIP_USGPR0"},
16070    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
16071   ]
16072  },
16073  "SPI_SHADER_PGM_RSRC2_HS": {
16074   "fields": [
16075    {"bits": [0, 0], "name": "SCRATCH_EN"},
16076    {"bits": [1, 5], "name": "USER_SGPR"},
16077    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16078    {"bits": [7, 7], "name": "OC_LDS_EN"},
16079    {"bits": [8, 8], "name": "TG_SIZE_EN"},
16080    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16081    {"bits": [18, 26], "name": "LDS_SIZE"},
16082    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16083    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16084   ]
16085  },
16086  "SPI_SHADER_PGM_RSRC2_LS_VS": {
16087   "fields": [
16088    {"bits": [0, 0], "name": "SCRATCH_EN"},
16089    {"bits": [1, 5], "name": "USER_SGPR"},
16090    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16091    {"bits": [7, 15], "name": "LDS_SIZE"},
16092    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
16093   ]
16094  },
16095  "SPI_SHADER_PGM_RSRC2_PS": {
16096   "fields": [
16097    {"bits": [0, 0], "name": "SCRATCH_EN"},
16098    {"bits": [1, 5], "name": "USER_SGPR"},
16099    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16100    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
16101    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
16102    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16103    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
16104    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
16105    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16106    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16107   ]
16108  },
16109  "SPI_SHADER_PGM_RSRC2_VS": {
16110   "fields": [
16111    {"bits": [0, 0], "name": "SCRATCH_EN"},
16112    {"bits": [1, 5], "name": "USER_SGPR"},
16113    {"bits": [6, 6], "name": "TRAP_PRESENT"},
16114    {"bits": [7, 7], "name": "OC_LDS_EN"},
16115    {"bits": [8, 8], "name": "SO_BASE0_EN"},
16116    {"bits": [9, 9], "name": "SO_BASE1_EN"},
16117    {"bits": [10, 10], "name": "SO_BASE2_EN"},
16118    {"bits": [11, 11], "name": "SO_BASE3_EN"},
16119    {"bits": [12, 12], "name": "SO_EN"},
16120    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16121    {"bits": [22, 22], "name": "PC_BASE_EN"},
16122    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
16123    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
16124    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
16125   ]
16126  },
16127  "SPI_SHADER_PGM_RSRC3_GS": {
16128   "fields": [
16129    {"bits": [0, 15], "name": "CU_EN"},
16130    {"bits": [16, 21], "name": "WAVE_LIMIT"},
16131    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
16132    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
16133   ]
16134  },
16135  "SPI_SHADER_PGM_RSRC3_HS": {
16136   "fields": [
16137    {"bits": [0, 5], "name": "WAVE_LIMIT"},
16138    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
16139    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
16140    {"bits": [16, 31], "name": "CU_EN"}
16141   ]
16142  },
16143  "SPI_SHADER_PGM_RSRC3_PS": {
16144   "fields": [
16145    {"bits": [0, 15], "name": "CU_EN"},
16146    {"bits": [16, 21], "name": "WAVE_LIMIT"},
16147    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
16148   ]
16149  },
16150  "SPI_SHADER_PGM_RSRC4_GS": {
16151   "fields": [
16152    {"bits": [0, 15], "name": "CU_EN"},
16153    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
16154   ]
16155  },
16156  "SPI_SHADER_PGM_RSRC4_PS": {
16157   "fields": [
16158    {"bits": [0, 15], "name": "CU_EN"}
16159   ]
16160  },
16161  "SPI_SHADER_POS_FORMAT": {
16162   "fields": [
16163    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
16164    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
16165    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
16166    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
16167    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
16168   ]
16169  },
16170  "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS": {
16171   "fields": [
16172    {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"},
16173    {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"},
16174    {"bits": [6, 6], "name": "GROUP_UPDATE_EN"},
16175    {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"},
16176    {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"}
16177   ]
16178  },
16179  "SPI_SHADER_REQ_CTRL_PS": {
16180   "fields": [
16181    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
16182    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
16183    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
16184    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
16185    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
16186    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
16187    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
16188    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
16189   ]
16190  },
16191  "SPI_SHADER_USER_ACCUM_PS_0": {
16192   "fields": [
16193    {"bits": [0, 6], "name": "CONTRIBUTION"}
16194   ]
16195  },
16196  "SPI_SHADER_USER_DATA_PS_0": {
16197   "fields": [
16198    {"bits": [0, 31], "name": "DATA"}
16199   ]
16200  },
16201  "SPI_SHADER_Z_FORMAT": {
16202   "fields": [
16203    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
16204   ]
16205  },
16206  "SPI_VS_OUT_CONFIG": {
16207   "fields": [
16208    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
16209    {"bits": [6, 6], "name": "VS_HALF_PACK"},
16210    {"bits": [7, 7], "name": "NO_PC_EXPORT"}
16211   ]
16212  },
16213  "SQC_CACHES": {
16214   "fields": [
16215    {"bits": [0, 0], "name": "TARGET_INST"},
16216    {"bits": [1, 1], "name": "TARGET_DATA"},
16217    {"bits": [2, 2], "name": "INVALIDATE"},
16218    {"bits": [3, 3], "name": "WRITEBACK"},
16219    {"bits": [4, 4], "name": "VOL"},
16220    {"bits": [16, 16], "name": "COMPLETE"},
16221    {"bits": [17, 18], "name": "L2_WB_POLICY"}
16222   ]
16223  },
16224  "SQC_WRITEBACK": {
16225   "fields": [
16226    {"bits": [0, 0], "name": "DWB"},
16227    {"bits": [1, 1], "name": "DIRTY"}
16228   ]
16229  },
16230  "SQ_PERFCOUNTER0_SELECT": {
16231   "fields": [
16232    {"bits": [0, 8], "name": "PERF_SEL"},
16233    {"bits": [12, 15], "name": "SQC_BANK_MASK"},
16234    {"bits": [20, 23], "name": "SPM_MODE"},
16235    {"bits": [28, 31], "name": "PERF_MODE"}
16236   ]
16237  },
16238  "SQ_PERFCOUNTER_CTRL": {
16239   "fields": [
16240    {"bits": [0, 0], "name": "PS_EN"},
16241    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16242    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16243    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16244    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16245    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16246    {"bits": [6, 6], "name": "CS_EN"},
16247    {"bits": [8, 9], "name": "CNTR_RATE"},
16248    {"bits": [13, 13], "name": "DISABLE_FLUSH"}
16249   ]
16250  },
16251  "SQ_PERFCOUNTER_CTRL2": {
16252   "fields": [
16253    {"bits": [0, 0], "name": "FORCE_EN"}
16254   ]
16255  },
16256  "SQ_THREAD_TRACE_BUF0_BASE": {
16257   "fields": [
16258    {"bits": [0, 31], "name": "BASE_LO"}
16259   ]
16260  },
16261  "SQ_THREAD_TRACE_BUF0_SIZE": {
16262   "fields": [
16263    {"bits": [0, 3], "name": "BASE_HI"},
16264    {"bits": [8, 29], "name": "SIZE"}
16265   ]
16266  },
16267  "SQ_THREAD_TRACE_CTRL": {
16268   "fields": [
16269    {"bits": [0, 1], "name": "MODE"},
16270    {"bits": [2, 2], "name": "ALL_VMID"},
16271    {"bits": [3, 3], "name": "CH_PERF_EN"},
16272    {"bits": [4, 4], "name": "INTERRUPT_EN"},
16273    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
16274    {"bits": [6, 8], "name": "HIWATER"},
16275    {"bits": [9, 9], "name": "REG_STALL_EN"},
16276    {"bits": [10, 10], "name": "SPI_STALL_EN"},
16277    {"bits": [11, 11], "name": "SQ_STALL_EN"},
16278    {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
16279    {"bits": [13, 13], "name": "UTIL_TIMER"},
16280    {"bits": [14, 15], "name": "WAVESTART_MODE"},
16281    {"bits": [16, 17], "name": "RT_FREQ"},
16282    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
16283    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
16284    {"bits": [30, 30], "name": "CAPTURE_ALL"},
16285    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
16286   ]
16287  },
16288  "SQ_THREAD_TRACE_DROPPED_CNTR": {
16289   "fields": [
16290    {"bits": [0, 31], "name": "CNTR"}
16291   ]
16292  },
16293  "SQ_THREAD_TRACE_MASK": {
16294   "fields": [
16295    {"bits": [0, 1], "name": "SIMD_SEL"},
16296    {"bits": [4, 7], "name": "WGP_SEL"},
16297    {"bits": [9, 9], "name": "SA_SEL"},
16298    {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
16299   ]
16300  },
16301  "SQ_THREAD_TRACE_STATUS": {
16302   "fields": [
16303    {"bits": [0, 11], "name": "FINISH_PENDING"},
16304    {"bits": [12, 23], "name": "FINISH_DONE"},
16305    {"bits": [24, 24], "name": "UTC_ERR"},
16306    {"bits": [25, 25], "name": "BUSY"},
16307    {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
16308    {"bits": [27, 27], "name": "EVENT_CNTR_STALL"}
16309   ]
16310  },
16311  "SQ_THREAD_TRACE_TOKEN_MASK": {
16312   "fields": [
16313    {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
16314    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
16315    {"bits": [24, 25], "name": "INST_EXCLUDE"},
16316    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
16317   ]
16318  },
16319  "SQ_THREAD_TRACE_WPTR": {
16320   "fields": [
16321    {"bits": [0, 28], "name": "OFFSET"},
16322    {"bits": [31, 31], "name": "BUFFER_ID"}
16323   ]
16324  },
16325  "SQ_WAVE_EXEC_HI": {
16326   "fields": [
16327    {"bits": [0, 31], "name": "EXEC_HI"}
16328   ]
16329  },
16330  "SQ_WAVE_EXEC_LO": {
16331   "fields": [
16332    {"bits": [0, 31], "name": "EXEC_LO"}
16333   ]
16334  },
16335  "SQ_WAVE_FLAT_XNACK_MASK": {
16336   "fields": [
16337    {"bits": [0, 31], "name": "MASK"}
16338   ]
16339  },
16340  "SQ_WAVE_FLUSH_IB": {
16341   "fields": [
16342    {"bits": [0, 31], "name": "UNUSED"}
16343   ]
16344  },
16345  "SQ_WAVE_GPR_ALLOC": {
16346   "fields": [
16347    {"bits": [0, 7], "name": "VGPR_BASE"},
16348    {"bits": [8, 15], "name": "VGPR_SIZE"},
16349    {"bits": [16, 23], "name": "SGPR_BASE"},
16350    {"bits": [24, 27], "name": "SGPR_SIZE"}
16351   ]
16352  },
16353  "SQ_WAVE_HW_ID1": {
16354   "fields": [
16355    {"bits": [0, 4], "name": "WAVE_ID"},
16356    {"bits": [8, 9], "name": "SIMD_ID"},
16357    {"bits": [10, 13], "name": "WGP_ID"},
16358    {"bits": [16, 16], "name": "SA_ID"},
16359    {"bits": [18, 19], "name": "SE_ID"}
16360   ]
16361  },
16362  "SQ_WAVE_HW_ID2": {
16363   "fields": [
16364    {"bits": [0, 3], "name": "QUEUE_ID"},
16365    {"bits": [4, 5], "name": "PIPE_ID"},
16366    {"bits": [8, 9], "name": "ME_ID"},
16367    {"bits": [12, 14], "name": "STATE_ID"},
16368    {"bits": [16, 20], "name": "WG_ID"},
16369    {"bits": [24, 27], "name": "VM_ID"},
16370    {"bits": [29, 30], "name": "COMPAT_LEVEL"}
16371   ]
16372  },
16373  "SQ_WAVE_HW_ID_LEGACY": {
16374   "fields": [
16375    {"bits": [0, 3], "name": "WAVE_ID"},
16376    {"bits": [4, 5], "name": "SIMD_ID"},
16377    {"bits": [6, 7], "name": "PIPE_ID"},
16378    {"bits": [8, 11], "name": "CU_ID"},
16379    {"bits": [12, 12], "name": "SH_ID"},
16380    {"bits": [13, 14], "name": "SE_ID"},
16381    {"bits": [15, 15], "name": "WAVE_ID_MSB"},
16382    {"bits": [16, 19], "name": "TG_ID"},
16383    {"bits": [20, 23], "name": "VM_ID"},
16384    {"bits": [24, 26], "name": "QUEUE_ID"},
16385    {"bits": [27, 29], "name": "STATE_ID"},
16386    {"bits": [30, 31], "name": "ME_ID"}
16387   ]
16388  },
16389  "SQ_WAVE_IB_DBG1": {
16390   "fields": [
16391    {"bits": [0, 0], "name": "XNACK_ERROR"},
16392    {"bits": [1, 1], "name": "XNACK"},
16393    {"bits": [2, 2], "name": "TA_NEED_RESET"},
16394    {"bits": [3, 3], "name": "XNACK_OVERRIDE"},
16395    {"bits": [4, 9], "name": "XCNT"},
16396    {"bits": [11, 16], "name": "QCNT"},
16397    {"bits": [18, 23], "name": "RCNT"},
16398    {"bits": [24, 24], "name": "WAVE_IDLE"},
16399    {"bits": [25, 31], "name": "MISC_CNT"}
16400   ]
16401  },
16402  "SQ_WAVE_IB_STS": {
16403   "fields": [
16404    {"bits": [0, 3], "name": "VM_CNT"},
16405    {"bits": [4, 6], "name": "EXP_CNT"},
16406    {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
16407    {"bits": [8, 11], "name": "LGKM_CNT"},
16408    {"bits": [12, 14], "name": "VALU_CNT"},
16409    {"bits": [15, 15], "name": "FIRST_REPLAY"},
16410    {"bits": [16, 21], "name": "RCNT"},
16411    {"bits": [22, 23], "name": "VM_CNT_HI"},
16412    {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
16413    {"bits": [25, 25], "name": "REPLAY_W64H"},
16414    {"bits": [26, 31], "name": "VS_CNT"}
16415   ]
16416  },
16417  "SQ_WAVE_IB_STS2": {
16418   "fields": [
16419    {"bits": [0, 1], "name": "INST_PREFETCH"},
16420    {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
16421    {"bits": [8, 9], "name": "MEM_ORDER"},
16422    {"bits": [10, 10], "name": "FWD_PROGRESS"},
16423    {"bits": [11, 11], "name": "WAVE64"},
16424    {"bits": [12, 12], "name": "WAVE64HI"},
16425    {"bits": [13, 13], "name": "SUBV_LOOP"}
16426   ]
16427  },
16428  "SQ_WAVE_INST_DW0": {
16429   "fields": [
16430    {"bits": [0, 31], "name": "INST_DW0"}
16431   ]
16432  },
16433  "SQ_WAVE_LDS_ALLOC": {
16434   "fields": [
16435    {"bits": [0, 8], "name": "LDS_BASE"},
16436    {"bits": [12, 20], "name": "LDS_SIZE"},
16437    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
16438   ]
16439  },
16440  "SQ_WAVE_M0": {
16441   "fields": [
16442    {"bits": [0, 31], "name": "M0"}
16443   ]
16444  },
16445  "SQ_WAVE_MODE": {
16446   "fields": [
16447    {"bits": [0, 3], "name": "FP_ROUND"},
16448    {"bits": [4, 7], "name": "FP_DENORM"},
16449    {"bits": [8, 8], "name": "DX10_CLAMP"},
16450    {"bits": [9, 9], "name": "IEEE"},
16451    {"bits": [10, 10], "name": "LOD_CLAMPED"},
16452    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16453    {"bits": [23, 23], "name": "FP16_OVFL"},
16454    {"bits": [27, 27], "name": "DISABLE_PERF"},
16455    {"bits": [28, 28], "name": "VSKIP"},
16456    {"bits": [29, 31], "name": "CSP"}
16457   ]
16458  },
16459  "SQ_WAVE_PC_HI": {
16460   "fields": [
16461    {"bits": [0, 15], "name": "PC_HI"}
16462   ]
16463  },
16464  "SQ_WAVE_PC_LO": {
16465   "fields": [
16466    {"bits": [0, 31], "name": "PC_LO"}
16467   ]
16468  },
16469  "SQ_WAVE_POPS_PACKER": {
16470   "fields": [
16471    {"bits": [0, 0], "name": "POPS_EN"},
16472    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
16473   ]
16474  },
16475  "SQ_WAVE_SCHED_MODE": {
16476   "fields": [
16477    {"bits": [0, 1], "name": "DEP_MODE"}
16478   ]
16479  },
16480  "SQ_WAVE_STATUS": {
16481   "fields": [
16482    {"bits": [0, 0], "name": "SCC"},
16483    {"bits": [1, 2], "name": "SPI_PRIO"},
16484    {"bits": [3, 4], "name": "USER_PRIO"},
16485    {"bits": [5, 5], "name": "PRIV"},
16486    {"bits": [6, 6], "name": "TRAP_EN"},
16487    {"bits": [7, 7], "name": "TTRACE_EN"},
16488    {"bits": [8, 8], "name": "EXPORT_RDY"},
16489    {"bits": [9, 9], "name": "EXECZ"},
16490    {"bits": [10, 10], "name": "VCCZ"},
16491    {"bits": [11, 11], "name": "IN_TG"},
16492    {"bits": [12, 12], "name": "IN_BARRIER"},
16493    {"bits": [13, 13], "name": "HALT"},
16494    {"bits": [14, 14], "name": "TRAP"},
16495    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
16496    {"bits": [16, 16], "name": "VALID"},
16497    {"bits": [17, 17], "name": "ECC_ERR"},
16498    {"bits": [18, 18], "name": "SKIP_EXPORT"},
16499    {"bits": [19, 19], "name": "PERF_EN"},
16500    {"bits": [23, 23], "name": "FATAL_HALT"},
16501    {"bits": [27, 27], "name": "MUST_EXPORT"}
16502   ]
16503  },
16504  "SQ_WAVE_TRAPSTS": {
16505   "fields": [
16506    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
16507    {"bits": [10, 10], "name": "SAVECTX"},
16508    {"bits": [11, 11], "name": "ILLEGAL_INST"},
16509    {"bits": [12, 14], "name": "EXCP_HI"},
16510    {"bits": [15, 15], "name": "BUFFER_OOB"},
16511    {"bits": [16, 19], "name": "EXCP_CYCLE"},
16512    {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
16513    {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
16514    {"bits": [28, 28], "name": "XNACK_ERROR"},
16515    {"bits": [29, 31], "name": "DP_RATE"}
16516   ]
16517  },
16518  "SQ_WAVE_VGPR_OFFSET": {
16519   "fields": [
16520    {"bits": [0, 5], "name": "SRC0"},
16521    {"bits": [6, 11], "name": "SRC1"},
16522    {"bits": [12, 17], "name": "SRC2"},
16523    {"bits": [18, 23], "name": "DST"}
16524   ]
16525  },
16526  "SX_BLEND_OPT_CONTROL": {
16527   "fields": [
16528    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
16529    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
16530    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
16531    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
16532    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
16533    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
16534    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
16535    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
16536    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
16537    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
16538    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
16539    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
16540    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
16541    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
16542    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
16543    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
16544    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
16545   ]
16546  },
16547  "SX_BLEND_OPT_EPSILON": {
16548   "fields": [
16549    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
16550    {"bits": [4, 7], "name": "MRT1_EPSILON"},
16551    {"bits": [8, 11], "name": "MRT2_EPSILON"},
16552    {"bits": [12, 15], "name": "MRT3_EPSILON"},
16553    {"bits": [16, 19], "name": "MRT4_EPSILON"},
16554    {"bits": [20, 23], "name": "MRT5_EPSILON"},
16555    {"bits": [24, 27], "name": "MRT6_EPSILON"},
16556    {"bits": [28, 31], "name": "MRT7_EPSILON"}
16557   ]
16558  },
16559  "SX_MRT0_BLEND_OPT": {
16560   "fields": [
16561    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
16562    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
16563    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
16564    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
16565    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
16566    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
16567   ]
16568  },
16569  "SX_PERFCOUNTER0_SELECT": {
16570   "fields": [
16571    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
16572    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
16573    {"bits": [20, 23], "name": "CNTR_MODE"}
16574   ]
16575  },
16576  "SX_PERFCOUNTER0_SELECT1": {
16577   "fields": [
16578    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
16579    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
16580   ]
16581  },
16582  "SX_PS_DOWNCONVERT": {
16583   "fields": [
16584    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
16585    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
16586    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
16587    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
16588    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
16589    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
16590    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
16591    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
16592   ]
16593  },
16594  "TA_BC_BASE_ADDR": {
16595   "fields": [
16596    {"bits": [0, 31], "name": "ADDRESS"}
16597   ]
16598  },
16599  "TA_BC_BASE_ADDR_HI": {
16600   "fields": [
16601    {"bits": [0, 7], "name": "ADDRESS"}
16602   ]
16603  },
16604  "TA_PERFCOUNTER0_SELECT": {
16605   "fields": [
16606    {"bits": [0, 7], "name": "PERF_SEL"},
16607    {"bits": [10, 17], "name": "PERF_SEL1"},
16608    {"bits": [20, 23], "name": "CNTR_MODE"},
16609    {"bits": [24, 27], "name": "PERF_MODE1"},
16610    {"bits": [28, 31], "name": "PERF_MODE"}
16611   ]
16612  },
16613  "TA_PERFCOUNTER0_SELECT1": {
16614   "fields": [
16615    {"bits": [0, 7], "name": "PERF_SEL2"},
16616    {"bits": [10, 17], "name": "PERF_SEL3"},
16617    {"bits": [24, 27], "name": "PERF_MODE3"},
16618    {"bits": [28, 31], "name": "PERF_MODE2"}
16619   ]
16620  },
16621  "TA_PERFCOUNTER1_SELECT": {
16622   "fields": [
16623    {"bits": [0, 7], "name": "PERF_SEL"},
16624    {"bits": [20, 23], "name": "CNTR_MODE"},
16625    {"bits": [28, 31], "name": "PERF_MODE"}
16626   ]
16627  },
16628  "TCP_PERFCOUNTER2_SELECT": {
16629   "fields": [
16630    {"bits": [0, 9], "name": "PERF_SEL"},
16631    {"bits": [20, 23], "name": "CNTR_MODE"},
16632    {"bits": [28, 31], "name": "PERF_MODE"}
16633   ]
16634  },
16635  "UTCL1_PERFCOUNTER0_SELECT": {
16636   "fields": [
16637    {"bits": [0, 9], "name": "PERF_SEL"},
16638    {"bits": [28, 31], "name": "COUNTER_MODE"}
16639   ]
16640  },
16641  "VGT_DISPATCH_DRAW_INDEX": {
16642   "fields": [
16643    {"bits": [0, 31], "name": "MATCH_INDEX"}
16644   ]
16645  },
16646  "VGT_DMA_BASE": {
16647   "fields": [
16648    {"bits": [0, 31], "name": "BASE_ADDR"}
16649   ]
16650  },
16651  "VGT_DMA_BASE_HI": {
16652   "fields": [
16653    {"bits": [0, 15], "name": "BASE_ADDR"}
16654   ]
16655  },
16656  "VGT_DMA_INDEX_TYPE": {
16657   "fields": [
16658    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
16659    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
16660    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
16661    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
16662    {"bits": [8, 8], "name": "ATC"},
16663    {"bits": [9, 9], "name": "NOT_EOP"},
16664    {"bits": [10, 10], "name": "REQ_PATH"},
16665    {"bits": [11, 13], "name": "MTYPE"}
16666   ]
16667  },
16668  "VGT_DMA_MAX_SIZE": {
16669   "fields": [
16670    {"bits": [0, 31], "name": "MAX_SIZE"}
16671   ]
16672  },
16673  "VGT_DMA_NUM_INSTANCES": {
16674   "fields": [
16675    {"bits": [0, 31], "name": "NUM_INSTANCES"}
16676   ]
16677  },
16678  "VGT_DMA_SIZE": {
16679   "fields": [
16680    {"bits": [0, 31], "name": "NUM_INDICES"}
16681   ]
16682  },
16683  "VGT_DRAW_INITIATOR": {
16684   "fields": [
16685    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
16686    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
16687    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
16688    {"bits": [5, 5], "name": "NOT_EOP"},
16689    {"bits": [6, 6], "name": "USE_OPAQUE"},
16690    {"bits": [7, 7], "name": "UNROLLED_INST"},
16691    {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"},
16692    {"bits": [29, 31], "name": "REG_RT_INDEX"}
16693   ]
16694  },
16695  "VGT_DRAW_PAYLOAD_CNTL": {
16696   "fields": [
16697    {"bits": [0, 0], "name": "OBJPRIM_ID_EN"},
16698    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
16699    {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"},
16700    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
16701    {"bits": [4, 4], "name": "EN_DRAW_VP"}
16702   ]
16703  },
16704  "VGT_ENHANCE": {
16705   "fields": [
16706    {"bits": [0, 31], "name": "MISC"}
16707   ]
16708  },
16709  "VGT_ESGS_RING_ITEMSIZE": {
16710   "fields": [
16711    {"bits": [0, 14], "name": "ITEMSIZE"}
16712   ]
16713  },
16714  "VGT_ESGS_RING_SIZE_UMD": {
16715   "fields": [
16716    {"bits": [0, 31], "name": "MEM_SIZE"}
16717   ]
16718  },
16719  "VGT_ES_PER_GS": {
16720   "fields": [
16721    {"bits": [0, 10], "name": "ES_PER_GS"}
16722   ]
16723  },
16724  "VGT_EVENT_ADDRESS_REG": {
16725   "fields": [
16726    {"bits": [0, 27], "name": "ADDRESS_LOW"}
16727   ]
16728  },
16729  "VGT_EVENT_INITIATOR": {
16730   "fields": [
16731    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
16732    {"bits": [10, 26], "name": "ADDRESS_HI"},
16733    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
16734   ]
16735  },
16736  "VGT_GROUP_DECR": {
16737   "fields": [
16738    {"bits": [0, 3], "name": "DECR"}
16739   ]
16740  },
16741  "VGT_GROUP_FIRST_DECR": {
16742   "fields": [
16743    {"bits": [0, 3], "name": "FIRST_DECR"}
16744   ]
16745  },
16746  "VGT_GROUP_PRIM_TYPE": {
16747   "fields": [
16748    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
16749    {"bits": [14, 14], "name": "RETAIN_ORDER"},
16750    {"bits": [15, 15], "name": "RETAIN_QUADS"},
16751    {"bits": [16, 18], "name": "PRIM_ORDER"}
16752   ]
16753  },
16754  "VGT_GROUP_VECT_0_CNTL": {
16755   "fields": [
16756    {"bits": [0, 0], "name": "COMP_X_EN"},
16757    {"bits": [1, 1], "name": "COMP_Y_EN"},
16758    {"bits": [2, 2], "name": "COMP_Z_EN"},
16759    {"bits": [3, 3], "name": "COMP_W_EN"},
16760    {"bits": [8, 15], "name": "STRIDE"},
16761    {"bits": [16, 23], "name": "SHIFT"}
16762   ]
16763  },
16764  "VGT_GROUP_VECT_0_FMT_CNTL": {
16765   "fields": [
16766    {"bits": [0, 3], "name": "X_CONV"},
16767    {"bits": [4, 7], "name": "X_OFFSET"},
16768    {"bits": [8, 11], "name": "Y_CONV"},
16769    {"bits": [12, 15], "name": "Y_OFFSET"},
16770    {"bits": [16, 19], "name": "Z_CONV"},
16771    {"bits": [20, 23], "name": "Z_OFFSET"},
16772    {"bits": [24, 27], "name": "W_CONV"},
16773    {"bits": [28, 31], "name": "W_OFFSET"}
16774   ]
16775  },
16776  "VGT_GSVS_RING_OFFSET_1": {
16777   "fields": [
16778    {"bits": [0, 14], "name": "OFFSET"}
16779   ]
16780  },
16781  "VGT_GS_INSTANCE_CNT": {
16782   "fields": [
16783    {"bits": [0, 0], "name": "ENABLE"},
16784    {"bits": [2, 8], "name": "CNT"},
16785    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
16786   ]
16787  },
16788  "VGT_GS_MAX_VERT_OUT": {
16789   "fields": [
16790    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
16791   ]
16792  },
16793  "VGT_GS_MODE": {
16794   "fields": [
16795    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
16796    {"bits": [3, 3], "name": "RESERVED_0"},
16797    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
16798    {"bits": [6, 10], "name": "RESERVED_1"},
16799    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
16800    {"bits": [12, 12], "name": "RESERVED_2"},
16801    {"bits": [13, 13], "name": "ES_PASSTHRU"},
16802    {"bits": [14, 14], "name": "COMPUTE_MODE"},
16803    {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
16804    {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
16805    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
16806    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
16807    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
16808    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
16809    {"bits": [21, 22], "name": "ONCHIP"}
16810   ]
16811  },
16812  "VGT_GS_ONCHIP_CNTL": {
16813   "fields": [
16814    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
16815    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
16816    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
16817   ]
16818  },
16819  "VGT_GS_OUT_PRIM_TYPE": {
16820   "fields": [
16821    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
16822    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
16823    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
16824    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
16825    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
16826   ]
16827  },
16828  "VGT_GS_PER_ES": {
16829   "fields": [
16830    {"bits": [0, 10], "name": "GS_PER_ES"}
16831   ]
16832  },
16833  "VGT_GS_PER_VS": {
16834   "fields": [
16835    {"bits": [0, 3], "name": "GS_PER_VS"}
16836   ]
16837  },
16838  "VGT_HOS_CNTL": {
16839   "fields": [
16840    {"bits": [0, 1], "name": "TESS_MODE"}
16841   ]
16842  },
16843  "VGT_HOS_MAX_TESS_LEVEL": {
16844   "fields": [
16845    {"bits": [0, 31], "name": "MAX_TESS"}
16846   ]
16847  },
16848  "VGT_HOS_MIN_TESS_LEVEL": {
16849   "fields": [
16850    {"bits": [0, 31], "name": "MIN_TESS"}
16851   ]
16852  },
16853  "VGT_HOS_REUSE_DEPTH": {
16854   "fields": [
16855    {"bits": [0, 7], "name": "REUSE_DEPTH"}
16856   ]
16857  },
16858  "VGT_HS_OFFCHIP_PARAM_UMD": {
16859   "fields": [
16860    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
16861    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
16862   ]
16863  },
16864  "VGT_INDX_OFFSET": {
16865   "fields": [
16866    {"bits": [0, 31], "name": "INDX_OFFSET"}
16867   ]
16868  },
16869  "VGT_INSTANCE_BASE_ID": {
16870   "fields": [
16871    {"bits": [0, 31], "name": "INSTANCE_BASE_ID"}
16872   ]
16873  },
16874  "VGT_INSTANCE_STEP_RATE_0": {
16875   "fields": [
16876    {"bits": [0, 31], "name": "STEP_RATE"}
16877   ]
16878  },
16879  "VGT_LS_HS_CONFIG": {
16880   "fields": [
16881    {"bits": [0, 7], "name": "NUM_PATCHES"},
16882    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
16883    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
16884   ]
16885  },
16886  "VGT_MAX_VTX_INDX": {
16887   "fields": [
16888    {"bits": [0, 31], "name": "MAX_INDX"}
16889   ]
16890  },
16891  "VGT_MIN_VTX_INDX": {
16892   "fields": [
16893    {"bits": [0, 31], "name": "MIN_INDX"}
16894   ]
16895  },
16896  "VGT_MULTI_PRIM_IB_RESET_EN": {
16897   "fields": [
16898    {"bits": [0, 0], "name": "RESET_EN"},
16899    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
16900   ]
16901  },
16902  "VGT_MULTI_PRIM_IB_RESET_INDX": {
16903   "fields": [
16904    {"bits": [0, 31], "name": "RESET_INDX"}
16905   ]
16906  },
16907  "VGT_OUTPUT_PATH_CNTL": {
16908   "fields": [
16909    {"bits": [0, 2], "name": "PATH_SELECT"}
16910   ]
16911  },
16912  "VGT_OUT_DEALLOC_CNTL": {
16913   "fields": [
16914    {"bits": [0, 6], "name": "DEALLOC_DIST"}
16915   ]
16916  },
16917  "VGT_PRIMITIVEID_EN": {
16918   "fields": [
16919    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
16920    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
16921    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
16922   ]
16923  },
16924  "VGT_PRIMITIVEID_RESET": {
16925   "fields": [
16926    {"bits": [0, 31], "name": "VALUE"}
16927   ]
16928  },
16929  "VGT_PRIMITIVE_TYPE": {
16930   "fields": [
16931    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
16932   ]
16933  },
16934  "VGT_REUSE_OFF": {
16935   "fields": [
16936    {"bits": [0, 0], "name": "REUSE_OFF"}
16937   ]
16938  },
16939  "VGT_SHADER_STAGES_EN": {
16940   "fields": [
16941    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16942    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16943    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16944    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16945    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16946    {"bits": [8, 8], "name": "DYNAMIC_HS"},
16947    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
16948    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
16949    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
16950    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
16951    {"bits": [13, 13], "name": "PRIMGEN_EN"},
16952    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
16953    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
16954    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
16955    {"bits": [21, 21], "name": "HS_W32_EN"},
16956    {"bits": [22, 22], "name": "GS_W32_EN"},
16957    {"bits": [23, 23], "name": "VS_W32_EN"},
16958    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
16959    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}
16960   ]
16961  },
16962  "VGT_STRMOUT_BUFFER_CONFIG": {
16963   "fields": [
16964    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
16965    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
16966    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
16967    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
16968   ]
16969  },
16970  "VGT_STRMOUT_BUFFER_OFFSET_0": {
16971   "fields": [
16972    {"bits": [0, 31], "name": "OFFSET"}
16973   ]
16974  },
16975  "VGT_STRMOUT_CONFIG": {
16976   "fields": [
16977    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
16978    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
16979    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
16980    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
16981    {"bits": [4, 6], "name": "RAST_STREAM"},
16982    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
16983    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
16984    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
16985   ]
16986  },
16987  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
16988   "fields": [
16989    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
16990   ]
16991  },
16992  "VGT_STRMOUT_VTX_STRIDE_0": {
16993   "fields": [
16994    {"bits": [0, 9], "name": "STRIDE"}
16995   ]
16996  },
16997  "VGT_TESS_DISTRIBUTION": {
16998   "fields": [
16999    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
17000    {"bits": [8, 15], "name": "ACCUM_TRI"},
17001    {"bits": [16, 23], "name": "ACCUM_QUAD"},
17002    {"bits": [24, 28], "name": "DONUT_SPLIT"},
17003    {"bits": [29, 31], "name": "TRAP_SPLIT"}
17004   ]
17005  },
17006  "VGT_TF_MEMORY_BASE_UMD": {
17007   "fields": [
17008    {"bits": [0, 31], "name": "BASE"}
17009   ]
17010  },
17011  "VGT_TF_PARAM": {
17012   "fields": [
17013    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
17014    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
17015    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
17016    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
17017    {"bits": [9, 9], "name": "DEPRECATED"},
17018    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
17019    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
17020    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
17021    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
17022    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
17023    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
17024    {"bits": [23, 25], "name": "MTYPE"}
17025   ]
17026  },
17027  "VGT_TF_RING_SIZE_UMD": {
17028   "fields": [
17029    {"bits": [0, 15], "name": "SIZE"}
17030   ]
17031  },
17032  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
17033   "fields": [
17034    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
17035   ]
17036  },
17037  "VGT_VTX_CNT_EN": {
17038   "fields": [
17039    {"bits": [0, 0], "name": "VTX_CNT_EN"}
17040   ]
17041  }
17042 }
17043}
17044