1{
2 "enums": {
3  "BinMapMode": {
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6    {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
7    {"name": "BIN_MAP_MODE_POPS", "value": 2}
8   ]
9  },
10  "BinSizeExtend": {
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13    {"name": "BIN_SIZE_64_PIXELS", "value": 1},
14    {"name": "BIN_SIZE_128_PIXELS", "value": 2},
15    {"name": "BIN_SIZE_256_PIXELS", "value": 3},
16    {"name": "BIN_SIZE_512_PIXELS", "value": 4}
17   ]
18  },
19  "BinningMode": {
20   "entries": [
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22    {"name": "FORCE_BINNING_ON", "value": 1},
23    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
24    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
25   ]
26  },
27  "BlendOp": {
28   "entries": [
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30    {"name": "BLEND_ONE", "value": 1},
31    {"name": "BLEND_SRC_COLOR", "value": 2},
32    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
33    {"name": "BLEND_SRC_ALPHA", "value": 4},
34    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
35    {"name": "BLEND_DST_ALPHA", "value": 6},
36    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
37    {"name": "BLEND_DST_COLOR", "value": 8},
38    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
39    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
40    {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
41    {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
42    {"name": "BLEND_CONSTANT_COLOR", "value": 13},
43    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
44    {"name": "BLEND_SRC1_COLOR", "value": 15},
45    {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
46    {"name": "BLEND_SRC1_ALPHA", "value": 17},
47    {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
48    {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
49    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
50   ]
51  },
52  "BlendOpt": {
53   "entries": [
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55    {"name": "FORCE_OPT_DISABLE", "value": 1},
56    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
57    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
58    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
59    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
60    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
61    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
62   ]
63  },
64  "CBMode": {
65   "entries": [
66    {"name": "CB_DISABLE", "value": 0},
67    {"name": "CB_NORMAL", "value": 1},
68    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
69    {"name": "CB_RESOLVE", "value": 3},
70    {"name": "CB_DECOMPRESS", "value": 4},
71    {"name": "CB_FMASK_DECOMPRESS", "value": 5},
72    {"name": "CB_DCC_DECOMPRESS", "value": 6},
73    {"name": "CB_RESERVED", "value": 7}
74   ]
75  },
76  "CBPerfClearFilterSel": {
77   "entries": [
78    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
79    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
80   ]
81  },
82  "CBPerfOpFilterSel": {
83   "entries": [
84    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
85    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
86    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
87    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
88    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
89    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
90   ]
91  },
92  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
93   "entries": [
94    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
95    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
96    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
97   ]
98  },
99  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
100   "entries": [
101    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
102    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
103   ]
104  },
105  "CLIP_RULE": {
106   "entries": [
107    {"name": "OUT", "value": 1},
108    {"name": "IN_0", "value": 2},
109    {"name": "IN_1", "value": 4},
110    {"name": "IN_10", "value": 8},
111    {"name": "IN_2", "value": 16},
112    {"name": "IN_20", "value": 32},
113    {"name": "IN_21", "value": 64},
114    {"name": "IN_210", "value": 128},
115    {"name": "IN_3", "value": 256},
116    {"name": "IN_30", "value": 512},
117    {"name": "IN_31", "value": 1024},
118    {"name": "IN_310", "value": 2048},
119    {"name": "IN_32", "value": 4096},
120    {"name": "IN_320", "value": 8192},
121    {"name": "IN_321", "value": 16384},
122    {"name": "IN_3210", "value": 32768}
123   ]
124  },
125  "CP_PERFMON_ENABLE_MODE": {
126   "entries": [
127    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
128    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
129    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
130    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
131   ]
132  },
133  "CP_PERFMON_STATE": {
134   "entries": [
135    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
136    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
137    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
138    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
139    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
140    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
141   ]
142  },
143  "CmaskAddr": {
144   "entries": [
145    {"name": "CMASK_ADDR_TILED", "value": 0},
146    {"name": "CMASK_ADDR_LINEAR", "value": 1},
147    {"name": "CMASK_ADDR_COMPATIBLE", "value": 2}
148   ]
149  },
150  "ColorFormat": {
151   "entries": [
152    {"name": "COLOR_INVALID", "value": 0},
153    {"name": "COLOR_8", "value": 1},
154    {"name": "COLOR_16", "value": 2},
155    {"name": "COLOR_8_8", "value": 3},
156    {"name": "COLOR_32", "value": 4},
157    {"name": "COLOR_16_16", "value": 5},
158    {"name": "COLOR_10_11_11", "value": 6},
159    {"name": "COLOR_11_11_10", "value": 7},
160    {"name": "COLOR_10_10_10_2", "value": 8},
161    {"name": "COLOR_2_10_10_10", "value": 9},
162    {"name": "COLOR_8_8_8_8", "value": 10},
163    {"name": "COLOR_32_32", "value": 11},
164    {"name": "COLOR_16_16_16_16", "value": 12},
165    {"name": "COLOR_32_32_32_32", "value": 14},
166    {"name": "COLOR_5_6_5", "value": 16},
167    {"name": "COLOR_1_5_5_5", "value": 17},
168    {"name": "COLOR_5_5_5_1", "value": 18},
169    {"name": "COLOR_4_4_4_4", "value": 19},
170    {"name": "COLOR_8_24", "value": 20},
171    {"name": "COLOR_24_8", "value": 21},
172    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
173    {"name": "COLOR_5_9_9_9", "value": 24}
174   ]
175  },
176  "CombFunc": {
177   "entries": [
178    {"name": "COMB_DST_PLUS_SRC", "value": 0},
179    {"name": "COMB_SRC_MINUS_DST", "value": 1},
180    {"name": "COMB_MIN_DST_SRC", "value": 2},
181    {"name": "COMB_MAX_DST_SRC", "value": 3},
182    {"name": "COMB_DST_MINUS_SRC", "value": 4}
183   ]
184  },
185  "CompareFrag": {
186   "entries": [
187    {"name": "FRAG_NEVER", "value": 0},
188    {"name": "FRAG_LESS", "value": 1},
189    {"name": "FRAG_EQUAL", "value": 2},
190    {"name": "FRAG_LEQUAL", "value": 3},
191    {"name": "FRAG_GREATER", "value": 4},
192    {"name": "FRAG_NOTEQUAL", "value": 5},
193    {"name": "FRAG_GEQUAL", "value": 6},
194    {"name": "FRAG_ALWAYS", "value": 7}
195   ]
196  },
197  "ConservativeZExport": {
198   "entries": [
199    {"name": "EXPORT_ANY_Z", "value": 0},
200    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
201    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
202    {"name": "EXPORT_RESERVED", "value": 3}
203   ]
204  },
205  "CovToShaderSel": {
206   "entries": [
207    {"name": "INPUT_COVERAGE", "value": 0},
208    {"name": "INPUT_INNER_COVERAGE", "value": 1},
209    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
210    {"name": "RAW", "value": 3}
211   ]
212  },
213  "DB_DFSM_CONTROL__PUNCHOUT_MODE": {
214   "entries": [
215    {"name": "AUTO", "value": 0},
216    {"name": "FORCE_ON", "value": 1},
217    {"name": "FORCE_OFF", "value": 2},
218    {"name": "RESERVED", "value": 3}
219   ]
220  },
221  "DbPRTFaultBehavior": {
222   "entries": [
223    {"name": "FAULT_ZERO", "value": 0},
224    {"name": "FAULT_ONE", "value": 1},
225    {"name": "FAULT_FAIL", "value": 2},
226    {"name": "FAULT_PASS", "value": 3}
227   ]
228  },
229  "DbPSLControl": {
230   "entries": [
231    {"name": "PSLC_AUTO", "value": 0},
232    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
233    {"name": "PSLC_ASAP", "value": 2},
234    {"name": "PSLC_COUNTDOWN", "value": 3}
235   ]
236  },
237  "EXCP_EN": {
238   "entries": [
239    {"name": "INVALID", "value": 1},
240    {"name": "INPUT_DENORMAL", "value": 2},
241    {"name": "DIVIDE_BY_ZERO", "value": 4},
242    {"name": "OVERFLOW", "value": 8},
243    {"name": "UNDERFLOW", "value": 16},
244    {"name": "INEXACT", "value": 32},
245    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
246    {"name": "ADDRESS_WATCH", "value": 128},
247    {"name": "MEMORY_VIOLATION", "value": 256}
248   ]
249  },
250  "FLOAT_MODE": {
251   "entries": [
252    {"name": "FP_32_DENORMS", "value": 48},
253    {"name": "FP_64_DENORMS", "value": 192},
254    {"name": "FP_ALL_DENORMS", "value": 240}
255   ]
256  },
257  "ForceControl": {
258   "entries": [
259    {"name": "FORCE_OFF", "value": 0},
260    {"name": "FORCE_ENABLE", "value": 1},
261    {"name": "FORCE_DISABLE", "value": 2},
262    {"name": "FORCE_RESERVED", "value": 3}
263   ]
264  },
265  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
266   "entries": [
267    {"name": "X_DRAW_POINTS", "value": 0},
268    {"name": "X_DRAW_LINES", "value": 1},
269    {"name": "X_DRAW_TRIANGLES", "value": 2}
270   ]
271  },
272  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
273   "entries": [
274    {"name": "X_DISABLE_POLY_MODE", "value": 0},
275    {"name": "X_DUAL_MODE", "value": 1}
276   ]
277  },
278  "PA_SU_VTX_CNTL__ROUND_MODE": {
279   "entries": [
280    {"name": "X_TRUNCATE", "value": 0},
281    {"name": "X_ROUND", "value": 1},
282    {"name": "X_ROUND_TO_EVEN", "value": 2},
283    {"name": "X_ROUND_TO_ODD", "value": 3}
284   ]
285  },
286  "PkrMap": {
287   "entries": [
288    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
289    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
290    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
291    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
292   ]
293  },
294  "PkrXsel": {
295   "entries": [
296    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
297    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
298    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
299    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
300   ]
301  },
302  "PkrXsel2": {
303   "entries": [
304    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
305    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
306    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
307    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
308   ]
309  },
310  "PkrYsel": {
311   "entries": [
312    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
313    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
314    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
315    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
316   ]
317  },
318  "QUANT_MODE": {
319   "entries": [
320    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
321    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
322    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
323    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
324    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
325    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
326    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
327    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
328   ]
329  },
330  "ROP3": {
331   "entries": [
332    {"name": "ROP3_CLEAR", "value": 0},
333    {"name": "X_0X05", "value": 5},
334    {"name": "X_0X0A", "value": 10},
335    {"name": "X_0X0F", "value": 15},
336    {"name": "ROP3_NOR", "value": 17},
337    {"name": "ROP3_AND_INVERTED", "value": 34},
338    {"name": "ROP3_COPY_INVERTED", "value": 51},
339    {"name": "ROP3_AND_REVERSE", "value": 68},
340    {"name": "X_0X50", "value": 80},
341    {"name": "ROP3_INVERT", "value": 85},
342    {"name": "X_0X5A", "value": 90},
343    {"name": "X_0X5F", "value": 95},
344    {"name": "ROP3_XOR", "value": 102},
345    {"name": "ROP3_NAND", "value": 119},
346    {"name": "ROP3_AND", "value": 136},
347    {"name": "ROP3_EQUIVALENT", "value": 153},
348    {"name": "X_0XA0", "value": 160},
349    {"name": "X_0XA5", "value": 165},
350    {"name": "ROP3_NO_OP", "value": 170},
351    {"name": "X_0XAF", "value": 175},
352    {"name": "ROP3_OR_INVERTED", "value": 187},
353    {"name": "ROP3_COPY", "value": 204},
354    {"name": "ROP3_OR_REVERSE", "value": 221},
355    {"name": "ROP3_OR", "value": 238},
356    {"name": "X_0XF0", "value": 240},
357    {"name": "X_0XF5", "value": 245},
358    {"name": "X_0XFA", "value": 250},
359    {"name": "ROP3_SET", "value": 255}
360   ]
361  },
362  "RbMap": {
363   "entries": [
364    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
365    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
366    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
367    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
368   ]
369  },
370  "RbXsel": {
371   "entries": [
372    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
373    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
374   ]
375  },
376  "RbXsel2": {
377   "entries": [
378    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
379    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
380    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
381    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
382   ]
383  },
384  "RbYsel": {
385   "entries": [
386    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
387    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
388   ]
389  },
390  "ReadPolicy": {
391   "entries": [
392    {"name": "CACHE_LRU_RD", "value": 0},
393    {"name": "CACHE_NOA", "value": 1},
394    {"name": "UNCACHED_RD", "value": 2},
395    {"name": "RESERVED_RDPOLICY", "value": 3}
396   ]
397  },
398  "SPI_PNT_SPRITE_OVERRIDE": {
399   "entries": [
400    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
401    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
402    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
403    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
404    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
405   ]
406  },
407  "SPI_SHADER_EX_FORMAT": {
408   "entries": [
409    {"name": "SPI_SHADER_ZERO", "value": 0},
410    {"name": "SPI_SHADER_32_R", "value": 1},
411    {"name": "SPI_SHADER_32_GR", "value": 2},
412    {"name": "SPI_SHADER_32_AR", "value": 3},
413    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
414    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
415    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
416    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
417    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
418    {"name": "SPI_SHADER_32_ABGR", "value": 9}
419   ]
420  },
421  "SPI_SHADER_FORMAT": {
422   "entries": [
423    {"name": "SPI_SHADER_NONE", "value": 0},
424    {"name": "SPI_SHADER_1COMP", "value": 1},
425    {"name": "SPI_SHADER_2COMP", "value": 2},
426    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
427    {"name": "SPI_SHADER_4COMP", "value": 4}
428   ]
429  },
430  "SPM_PERFMON_STATE": {
431   "entries": [
432    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
433    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
434    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
435    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
436    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
437    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
438   ]
439  },
440  "SX_BLEND_OPT": {
441   "entries": [
442    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
443    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
444    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
445    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
446    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
447    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
448    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
449    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
450   ]
451  },
452  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
453   "entries": [
454    {"name": "EXACT", "value": 0},
455    {"name": "11BIT_FORMAT", "value": 1},
456    {"name": "10BIT_FORMAT", "value": 3},
457    {"name": "8BIT_FORMAT", "value": 6},
458    {"name": "6BIT_FORMAT", "value": 11},
459    {"name": "5BIT_FORMAT", "value": 13},
460    {"name": "4BIT_FORMAT", "value": 15}
461   ]
462  },
463  "SX_DOWNCONVERT_FORMAT": {
464   "entries": [
465    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
466    {"name": "SX_RT_EXPORT_32_R", "value": 1},
467    {"name": "SX_RT_EXPORT_32_A", "value": 2},
468    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
469    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
470    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
471    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
472    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
473    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
474    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
475    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
476    {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11}
477   ]
478  },
479  "SX_OPT_COMB_FCN": {
480   "entries": [
481    {"name": "OPT_COMB_NONE", "value": 0},
482    {"name": "OPT_COMB_ADD", "value": 1},
483    {"name": "OPT_COMB_SUBTRACT", "value": 2},
484    {"name": "OPT_COMB_MIN", "value": 3},
485    {"name": "OPT_COMB_MAX", "value": 4},
486    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
487    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
488    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
489   ]
490  },
491  "ScMap": {
492   "entries": [
493    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
494    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
495    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
496    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
497   ]
498  },
499  "ScUncertaintyRegionMode": {
500   "entries": [
501    {"name": "SC_HALF_LSB", "value": 0},
502    {"name": "SC_LSB_ONE_SIDED", "value": 1},
503    {"name": "SC_LSB_TWO_SIDED", "value": 2}
504   ]
505  },
506  "ScXsel": {
507   "entries": [
508    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
509    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
510    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
511    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
512   ]
513  },
514  "ScYsel": {
515   "entries": [
516    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
517    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
518    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
519    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
520   ]
521  },
522  "SeMap": {
523   "entries": [
524    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
525    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
526    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
527    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
528   ]
529  },
530  "SePairMap": {
531   "entries": [
532    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
533    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
534    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
535    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
536   ]
537  },
538  "SePairXsel": {
539   "entries": [
540    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
541    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
542    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
543    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
544   ]
545  },
546  "SePairYsel": {
547   "entries": [
548    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
549    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
550    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
551    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
552   ]
553  },
554  "SeXsel": {
555   "entries": [
556    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
557    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
558    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
559    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
560   ]
561  },
562  "SeYsel": {
563   "entries": [
564    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
565    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
566    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
567    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
568   ]
569  },
570  "StencilFormat": {
571   "entries": [
572    {"name": "STENCIL_INVALID", "value": 0},
573    {"name": "STENCIL_8", "value": 1}
574   ]
575  },
576  "StencilOp": {
577   "entries": [
578    {"name": "STENCIL_KEEP", "value": 0},
579    {"name": "STENCIL_ZERO", "value": 1},
580    {"name": "STENCIL_ONES", "value": 2},
581    {"name": "STENCIL_REPLACE_TEST", "value": 3},
582    {"name": "STENCIL_REPLACE_OP", "value": 4},
583    {"name": "STENCIL_ADD_CLAMP", "value": 5},
584    {"name": "STENCIL_SUB_CLAMP", "value": 6},
585    {"name": "STENCIL_INVERT", "value": 7},
586    {"name": "STENCIL_ADD_WRAP", "value": 8},
587    {"name": "STENCIL_SUB_WRAP", "value": 9},
588    {"name": "STENCIL_AND", "value": 10},
589    {"name": "STENCIL_OR", "value": 11},
590    {"name": "STENCIL_XOR", "value": 12},
591    {"name": "STENCIL_NAND", "value": 13},
592    {"name": "STENCIL_NOR", "value": 14},
593    {"name": "STENCIL_XNOR", "value": 15}
594   ]
595  },
596  "SurfaceEndian": {
597   "entries": [
598    {"name": "ENDIAN_NONE", "value": 0},
599    {"name": "ENDIAN_8IN16", "value": 1},
600    {"name": "ENDIAN_8IN32", "value": 2},
601    {"name": "ENDIAN_8IN64", "value": 3}
602   ]
603  },
604  "SurfaceNumber": {
605   "entries": [
606    {"name": "NUMBER_UNORM", "value": 0},
607    {"name": "NUMBER_SNORM", "value": 1},
608    {"name": "NUMBER_USCALED", "value": 2},
609    {"name": "NUMBER_SSCALED", "value": 3},
610    {"name": "NUMBER_UINT", "value": 4},
611    {"name": "NUMBER_SINT", "value": 5},
612    {"name": "NUMBER_SRGB", "value": 6},
613    {"name": "NUMBER_FLOAT", "value": 7}
614   ]
615  },
616  "SurfaceSwap": {
617   "entries": [
618    {"name": "SWAP_STD", "value": 0},
619    {"name": "SWAP_ALT", "value": 1},
620    {"name": "SWAP_STD_REV", "value": 2},
621    {"name": "SWAP_ALT_REV", "value": 3}
622   ]
623  },
624  "ThreadTraceRegInclude": {
625   "entries": [
626    {"name": "REG_INCLUDE_SQDEC", "value": 1},
627    {"name": "REG_INCLUDE_SHDEC", "value": 2},
628    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
629    {"name": "REG_INCLUDE_COMP", "value": 8},
630    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
631    {"name": "REG_INCLUDE_CONFIG", "value": 32},
632    {"name": "REG_INCLUDE_OTHER", "value": 64},
633    {"name": "REG_INCLUDE_READS", "value": 128}
634   ]
635  },
636  "ThreadTraceTokenExclude": {
637   "entries": [
638    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
639    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
640    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
641    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
642    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
643    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
644    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
645    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
646    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
647    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
648    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
649    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
650   ]
651  },
652  "VGT_DETECT_ONE": {
653   "entries": [
654    {"name": "PRE_CLAMP_TF1", "value": 0},
655    {"name": "POST_CLAMP_TF1", "value": 1},
656    {"name": "DISABLE_TF1", "value": 2}
657   ]
658  },
659  "VGT_DETECT_ZERO": {
660   "entries": [
661    {"name": "PRE_CLAMP_TF0", "value": 0},
662    {"name": "POST_CLAMP_TF0", "value": 1},
663    {"name": "DISABLE_TF0", "value": 2}
664   ]
665  },
666  "VGT_DIST_MODE": {
667   "entries": [
668    {"name": "NO_DIST", "value": 0},
669    {"name": "PATCHES", "value": 1},
670    {"name": "DONUTS", "value": 2},
671    {"name": "TRAPEZOIDS", "value": 3}
672   ]
673  },
674  "VGT_DI_MAJOR_MODE_SELECT": {
675   "entries": [
676    {"name": "DI_MAJOR_MODE_0", "value": 0},
677    {"name": "DI_MAJOR_MODE_1", "value": 1}
678   ]
679  },
680  "VGT_DI_PRIM_TYPE": {
681   "entries": [
682    {"name": "DI_PT_NONE", "value": 0},
683    {"name": "DI_PT_POINTLIST", "value": 1},
684    {"name": "DI_PT_LINELIST", "value": 2},
685    {"name": "DI_PT_LINESTRIP", "value": 3},
686    {"name": "DI_PT_TRILIST", "value": 4},
687    {"name": "DI_PT_TRIFAN", "value": 5},
688    {"name": "DI_PT_TRISTRIP", "value": 6},
689    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
690    {"name": "DI_PT_UNUSED_1", "value": 8},
691    {"name": "DI_PT_PATCH", "value": 9},
692    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
693    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
694    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
695    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
696    {"name": "DI_PT_UNUSED_3", "value": 14},
697    {"name": "DI_PT_UNUSED_4", "value": 15},
698    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
699    {"name": "DI_PT_RECTLIST", "value": 17},
700    {"name": "DI_PT_LINELOOP", "value": 18},
701    {"name": "DI_PT_QUADLIST", "value": 19},
702    {"name": "DI_PT_QUADSTRIP", "value": 20},
703    {"name": "DI_PT_POLYGON", "value": 21}
704   ]
705  },
706  "VGT_DI_SOURCE_SELECT": {
707   "entries": [
708    {"name": "DI_SRC_SEL_DMA", "value": 0},
709    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
710    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
711    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
712   ]
713  },
714  "VGT_DMA_BUF_TYPE": {
715   "entries": [
716    {"name": "VGT_DMA_BUF_MEM", "value": 0},
717    {"name": "VGT_DMA_BUF_RING", "value": 1},
718    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
719    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
720   ]
721  },
722  "VGT_DMA_SWAP_MODE": {
723   "entries": [
724    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
725    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
726    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
727    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
728   ]
729  },
730  "VGT_EVENT_TYPE": {
731   "entries": [
732    {"name": "Reserved_0x00", "value": 0},
733    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
734    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
735    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
736    {"name": "CACHE_FLUSH_TS", "value": 4},
737    {"name": "CONTEXT_DONE", "value": 5},
738    {"name": "CACHE_FLUSH", "value": 6},
739    {"name": "CS_PARTIAL_FLUSH", "value": 7},
740    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
741    {"name": "SET_FE_ID", "value": 9},
742    {"name": "VGT_STREAMOUT_RESET", "value": 10},
743    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
744    {"name": "END_OF_PIPE_IB_END", "value": 12},
745    {"name": "RST_PIX_CNT", "value": 13},
746    {"name": "BREAK_BATCH", "value": 14},
747    {"name": "VS_PARTIAL_FLUSH", "value": 15},
748    {"name": "PS_PARTIAL_FLUSH", "value": 16},
749    {"name": "FLUSH_HS_OUTPUT", "value": 17},
750    {"name": "FLUSH_DFSM", "value": 18},
751    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
752    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
753    {"name": "ZPASS_DONE", "value": 21},
754    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
755    {"name": "PERFCOUNTER_START", "value": 23},
756    {"name": "PERFCOUNTER_STOP", "value": 24},
757    {"name": "PIPELINESTAT_START", "value": 25},
758    {"name": "PIPELINESTAT_STOP", "value": 26},
759    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
760    {"name": "FLUSH_ES_OUTPUT", "value": 28},
761    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
762    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
763    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
764    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
765    {"name": "RESET_VTX_CNT", "value": 33},
766    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
767    {"name": "CS_CONTEXT_DONE", "value": 35},
768    {"name": "VGT_FLUSH", "value": 36},
769    {"name": "TGID_ROLLOVER", "value": 37},
770    {"name": "SQ_NON_EVENT", "value": 38},
771    {"name": "SC_SEND_DB_VPZ", "value": 39},
772    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
773    {"name": "FLUSH_SX_TS", "value": 41},
774    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
775    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
776    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
777    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
778    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
779    {"name": "CS_DONE", "value": 47},
780    {"name": "PS_DONE", "value": 48},
781    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
782    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
783    {"name": "THREAD_TRACE_START", "value": 51},
784    {"name": "THREAD_TRACE_STOP", "value": 52},
785    {"name": "THREAD_TRACE_MARKER", "value": 53},
786    {"name": "THREAD_TRACE_DRAW", "value": 54},
787    {"name": "THREAD_TRACE_FINISH", "value": 55},
788    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
789    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
790    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
791    {"name": "CONTEXT_SUSPEND", "value": 59},
792    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
793    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
794    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
795    {"name": "DRAW_DONE", "value": 63}
796   ]
797  },
798  "VGT_GS_CUT_MODE": {
799   "entries": [
800    {"name": "GS_CUT_1024", "value": 0},
801    {"name": "GS_CUT_512", "value": 1},
802    {"name": "GS_CUT_256", "value": 2},
803    {"name": "GS_CUT_128", "value": 3}
804   ]
805  },
806  "VGT_GS_MODE_TYPE": {
807   "entries": [
808    {"name": "GS_OFF", "value": 0},
809    {"name": "GS_SCENARIO_A", "value": 1},
810    {"name": "GS_SCENARIO_B", "value": 2},
811    {"name": "GS_SCENARIO_G", "value": 3},
812    {"name": "GS_SCENARIO_C", "value": 4},
813    {"name": "SPRITE_EN", "value": 5}
814   ]
815  },
816  "VGT_GS_OUTPRIM_TYPE": {
817   "entries": [
818    {"name": "POINTLIST", "value": 0},
819    {"name": "LINESTRIP", "value": 1},
820    {"name": "TRISTRIP", "value": 2},
821    {"name": "RECTLIST", "value": 3}
822   ]
823  },
824  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
825   "entries": [
826    {"name": "X_8K_DWORDS", "value": 0},
827    {"name": "X_4K_DWORDS", "value": 1},
828    {"name": "X_2K_DWORDS", "value": 2},
829    {"name": "X_1K_DWORDS", "value": 3}
830   ]
831  },
832  "VGT_INDEX_TYPE_MODE": {
833   "entries": [
834    {"name": "VGT_INDEX_16", "value": 0},
835    {"name": "VGT_INDEX_32", "value": 1},
836    {"name": "VGT_INDEX_8", "value": 2}
837   ]
838  },
839  "VGT_RDREQ_POLICY": {
840   "entries": [
841    {"name": "VGT_POLICY_LRU", "value": 0},
842    {"name": "VGT_POLICY_STREAM", "value": 1},
843    {"name": "VGT_POLICY_BYPASS", "value": 2}
844   ]
845  },
846  "VGT_STAGES_ES_EN": {
847   "entries": [
848    {"name": "ES_STAGE_OFF", "value": 0},
849    {"name": "ES_STAGE_DS", "value": 1},
850    {"name": "ES_STAGE_REAL", "value": 2},
851    {"name": "RESERVED_ES", "value": 3}
852   ]
853  },
854  "VGT_STAGES_GS_EN": {
855   "entries": [
856    {"name": "GS_STAGE_OFF", "value": 0},
857    {"name": "GS_STAGE_ON", "value": 1}
858   ]
859  },
860  "VGT_STAGES_HS_EN": {
861   "entries": [
862    {"name": "HS_STAGE_OFF", "value": 0},
863    {"name": "HS_STAGE_ON", "value": 1}
864   ]
865  },
866  "VGT_STAGES_LS_EN": {
867   "entries": [
868    {"name": "LS_STAGE_OFF", "value": 0},
869    {"name": "LS_STAGE_ON", "value": 1},
870    {"name": "CS_STAGE_ON", "value": 2},
871    {"name": "RESERVED_LS", "value": 3}
872   ]
873  },
874  "VGT_STAGES_VS_EN": {
875   "entries": [
876    {"name": "VS_STAGE_REAL", "value": 0},
877    {"name": "VS_STAGE_DS", "value": 1},
878    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
879    {"name": "RESERVED_VS", "value": 3}
880   ]
881  },
882  "VGT_TESS_PARTITION": {
883   "entries": [
884    {"name": "PART_INTEGER", "value": 0},
885    {"name": "PART_POW2", "value": 1},
886    {"name": "PART_FRAC_ODD", "value": 2},
887    {"name": "PART_FRAC_EVEN", "value": 3}
888   ]
889  },
890  "VGT_TESS_TOPOLOGY": {
891   "entries": [
892    {"name": "OUTPUT_POINT", "value": 0},
893    {"name": "OUTPUT_LINE", "value": 1},
894    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
895    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
896   ]
897  },
898  "VGT_TESS_TYPE": {
899   "entries": [
900    {"name": "TESS_ISOLINE", "value": 0},
901    {"name": "TESS_TRIANGLE", "value": 1},
902    {"name": "TESS_QUAD", "value": 2}
903   ]
904  },
905  "WritePolicy": {
906   "entries": [
907    {"name": "CACHE_LRU_WR", "value": 0},
908    {"name": "CACHE_STREAM", "value": 1},
909    {"name": "CACHE_BYPASS", "value": 2},
910    {"name": "UNCACHED_WR", "value": 3}
911   ]
912  },
913  "ZFormat": {
914   "entries": [
915    {"name": "Z_INVALID", "value": 0},
916    {"name": "Z_16", "value": 1},
917    {"name": "Z_24", "value": 2},
918    {"name": "Z_32_FLOAT", "value": 3}
919   ]
920  },
921  "ZLimitSumm": {
922   "entries": [
923    {"name": "FORCE_SUMM_OFF", "value": 0},
924    {"name": "FORCE_SUMM_MINZ", "value": 1},
925    {"name": "FORCE_SUMM_MAXZ", "value": 2},
926    {"name": "FORCE_SUMM_BOTH", "value": 3}
927   ]
928  },
929  "ZOrder": {
930   "entries": [
931    {"name": "LATE_Z", "value": 0},
932    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
933    {"name": "RE_Z", "value": 2},
934    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
935   ]
936  }
937 },
938 "register_mappings": [
939  {
940   "chips": ["gfx103"],
941   "map": {"at": 40, "to": "mm"},
942   "name": "SQ_WAVE_ACTIVE",
943   "type_ref": "SQ_WAVE_ACTIVE"
944  },
945  {
946   "chips": ["gfx103"],
947   "map": {"at": 44, "to": "mm"},
948   "name": "SQ_WAVE_VALID_AND_IDLE",
949   "type_ref": "SQ_WAVE_ACTIVE"
950  },
951  {
952   "chips": ["gfx103"],
953   "map": {"at": 1028, "to": "mm"},
954   "name": "SQ_WAVE_MODE",
955   "type_ref": "SQ_WAVE_MODE"
956  },
957  {
958   "chips": ["gfx103"],
959   "map": {"at": 1032, "to": "mm"},
960   "name": "SQ_WAVE_STATUS",
961   "type_ref": "SQ_WAVE_STATUS"
962  },
963  {
964   "chips": ["gfx103"],
965   "map": {"at": 1036, "to": "mm"},
966   "name": "SQ_WAVE_TRAPSTS",
967   "type_ref": "SQ_WAVE_TRAPSTS"
968  },
969  {
970   "chips": ["gfx103"],
971   "map": {"at": 1040, "to": "mm"},
972   "name": "SQ_WAVE_HW_ID_LEGACY",
973   "type_ref": "SQ_WAVE_HW_ID_LEGACY"
974  },
975  {
976   "chips": ["gfx103"],
977   "map": {"at": 1044, "to": "mm"},
978   "name": "SQ_WAVE_GPR_ALLOC",
979   "type_ref": "SQ_WAVE_GPR_ALLOC"
980  },
981  {
982   "chips": ["gfx103"],
983   "map": {"at": 1048, "to": "mm"},
984   "name": "SQ_WAVE_LDS_ALLOC",
985   "type_ref": "SQ_WAVE_LDS_ALLOC"
986  },
987  {
988   "chips": ["gfx103"],
989   "map": {"at": 1052, "to": "mm"},
990   "name": "SQ_WAVE_IB_STS",
991   "type_ref": "SQ_WAVE_IB_STS"
992  },
993  {
994   "chips": ["gfx103"],
995   "map": {"at": 1056, "to": "mm"},
996   "name": "SQ_WAVE_PC_LO",
997   "type_ref": "SQ_WAVE_PC_LO"
998  },
999  {
1000   "chips": ["gfx103"],
1001   "map": {"at": 1060, "to": "mm"},
1002   "name": "SQ_WAVE_PC_HI",
1003   "type_ref": "SQ_WAVE_PC_HI"
1004  },
1005  {
1006   "chips": ["gfx103"],
1007   "map": {"at": 1064, "to": "mm"},
1008   "name": "SQ_WAVE_INST_DW0",
1009   "type_ref": "SQ_WAVE_INST_DW0"
1010  },
1011  {
1012   "chips": ["gfx103"],
1013   "map": {"at": 1076, "to": "mm"},
1014   "name": "SQ_WAVE_IB_DBG1",
1015   "type_ref": "SQ_WAVE_IB_DBG1"
1016  },
1017  {
1018   "chips": ["gfx103"],
1019   "map": {"at": 1080, "to": "mm"},
1020   "name": "SQ_WAVE_FLUSH_IB",
1021   "type_ref": "SQ_WAVE_FLUSH_IB"
1022  },
1023  {
1024   "chips": ["gfx103"],
1025   "map": {"at": 1104, "to": "mm"},
1026   "name": "SQ_WAVE_FLAT_SCRATCH_LO",
1027   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1028  },
1029  {
1030   "chips": ["gfx103"],
1031   "map": {"at": 1108, "to": "mm"},
1032   "name": "SQ_WAVE_FLAT_SCRATCH_HI",
1033   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1034  },
1035  {
1036   "chips": ["gfx103"],
1037   "map": {"at": 1116, "to": "mm"},
1038   "name": "SQ_WAVE_HW_ID1",
1039   "type_ref": "SQ_WAVE_HW_ID1"
1040  },
1041  {
1042   "chips": ["gfx103"],
1043   "map": {"at": 1120, "to": "mm"},
1044   "name": "SQ_WAVE_HW_ID2",
1045   "type_ref": "SQ_WAVE_HW_ID2"
1046  },
1047  {
1048   "chips": ["gfx103"],
1049   "map": {"at": 1124, "to": "mm"},
1050   "name": "SQ_WAVE_POPS_PACKER",
1051   "type_ref": "SQ_WAVE_POPS_PACKER"
1052  },
1053  {
1054   "chips": ["gfx103"],
1055   "map": {"at": 1128, "to": "mm"},
1056   "name": "SQ_WAVE_SCHED_MODE",
1057   "type_ref": "SQ_WAVE_SCHED_MODE"
1058  },
1059  {
1060   "chips": ["gfx103"],
1061   "map": {"at": 1132, "to": "mm"},
1062   "name": "SQ_WAVE_VGPR_OFFSET",
1063   "type_ref": "SQ_WAVE_VGPR_OFFSET"
1064  },
1065  {
1066   "chips": ["gfx103"],
1067   "map": {"at": 1136, "to": "mm"},
1068   "name": "SQ_WAVE_IB_STS2",
1069   "type_ref": "SQ_WAVE_IB_STS2"
1070  },
1071  {
1072   "chips": ["gfx103"],
1073   "map": {"at": 1140, "to": "mm"},
1074   "name": "SQ_WAVE_SHADER_CYCLES",
1075   "type_ref": "SQ_WAVE_SHADER_CYCLES"
1076  },
1077  {
1078   "chips": ["gfx103"],
1079   "map": {"at": 2480, "to": "mm"},
1080   "name": "SQ_WAVE_TTMP0",
1081   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1082  },
1083  {
1084   "chips": ["gfx103"],
1085   "map": {"at": 2484, "to": "mm"},
1086   "name": "SQ_WAVE_TTMP1",
1087   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1088  },
1089  {
1090   "chips": ["gfx103"],
1091   "map": {"at": 2488, "to": "mm"},
1092   "name": "SQ_WAVE_TTMP2",
1093   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1094  },
1095  {
1096   "chips": ["gfx103"],
1097   "map": {"at": 2492, "to": "mm"},
1098   "name": "SQ_WAVE_TTMP3",
1099   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1100  },
1101  {
1102   "chips": ["gfx103"],
1103   "map": {"at": 2496, "to": "mm"},
1104   "name": "SQ_WAVE_TTMP4",
1105   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1106  },
1107  {
1108   "chips": ["gfx103"],
1109   "map": {"at": 2500, "to": "mm"},
1110   "name": "SQ_WAVE_TTMP5",
1111   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1112  },
1113  {
1114   "chips": ["gfx103"],
1115   "map": {"at": 2504, "to": "mm"},
1116   "name": "SQ_WAVE_TTMP6",
1117   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1118  },
1119  {
1120   "chips": ["gfx103"],
1121   "map": {"at": 2508, "to": "mm"},
1122   "name": "SQ_WAVE_TTMP7",
1123   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1124  },
1125  {
1126   "chips": ["gfx103"],
1127   "map": {"at": 2512, "to": "mm"},
1128   "name": "SQ_WAVE_TTMP8",
1129   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1130  },
1131  {
1132   "chips": ["gfx103"],
1133   "map": {"at": 2516, "to": "mm"},
1134   "name": "SQ_WAVE_TTMP9",
1135   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1136  },
1137  {
1138   "chips": ["gfx103"],
1139   "map": {"at": 2520, "to": "mm"},
1140   "name": "SQ_WAVE_TTMP10",
1141   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1142  },
1143  {
1144   "chips": ["gfx103"],
1145   "map": {"at": 2524, "to": "mm"},
1146   "name": "SQ_WAVE_TTMP11",
1147   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1148  },
1149  {
1150   "chips": ["gfx103"],
1151   "map": {"at": 2528, "to": "mm"},
1152   "name": "SQ_WAVE_TTMP12",
1153   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1154  },
1155  {
1156   "chips": ["gfx103"],
1157   "map": {"at": 2532, "to": "mm"},
1158   "name": "SQ_WAVE_TTMP13",
1159   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1160  },
1161  {
1162   "chips": ["gfx103"],
1163   "map": {"at": 2536, "to": "mm"},
1164   "name": "SQ_WAVE_TTMP14",
1165   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1166  },
1167  {
1168   "chips": ["gfx103"],
1169   "map": {"at": 2540, "to": "mm"},
1170   "name": "SQ_WAVE_TTMP15",
1171   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1172  },
1173  {
1174   "chips": ["gfx103"],
1175   "map": {"at": 2544, "to": "mm"},
1176   "name": "SQ_WAVE_M0",
1177   "type_ref": "SQ_WAVE_M0"
1178  },
1179  {
1180   "chips": ["gfx103"],
1181   "map": {"at": 2552, "to": "mm"},
1182   "name": "SQ_WAVE_EXEC_LO",
1183   "type_ref": "SQ_WAVE_EXEC_LO"
1184  },
1185  {
1186   "chips": ["gfx103"],
1187   "map": {"at": 2556, "to": "mm"},
1188   "name": "SQ_WAVE_EXEC_HI",
1189   "type_ref": "SQ_WAVE_EXEC_HI"
1190  },
1191  {
1192   "chips": ["gfx103"],
1193   "map": {"at": 32776, "to": "mm"},
1194   "name": "GRBM_STATUS2",
1195   "type_ref": "GRBM_STATUS2"
1196  },
1197  {
1198   "chips": ["gfx103"],
1199   "map": {"at": 32784, "to": "mm"},
1200   "name": "GRBM_STATUS",
1201   "type_ref": "GRBM_STATUS"
1202  },
1203  {
1204   "chips": ["gfx103"],
1205   "map": {"at": 32788, "to": "mm"},
1206   "name": "GRBM_STATUS_SE0",
1207   "type_ref": "GRBM_STATUS_SE0"
1208  },
1209  {
1210   "chips": ["gfx103"],
1211   "map": {"at": 32792, "to": "mm"},
1212   "name": "GRBM_STATUS_SE1",
1213   "type_ref": "GRBM_STATUS_SE0"
1214  },
1215  {
1216   "chips": ["gfx103"],
1217   "map": {"at": 32796, "to": "mm"},
1218   "name": "GRBM_STATUS3",
1219   "type_ref": "GRBM_STATUS3"
1220  },
1221  {
1222   "chips": ["gfx103"],
1223   "map": {"at": 32824, "to": "mm"},
1224   "name": "GRBM_STATUS_SE2",
1225   "type_ref": "GRBM_STATUS_SE0"
1226  },
1227  {
1228   "chips": ["gfx103"],
1229   "map": {"at": 32828, "to": "mm"},
1230   "name": "GRBM_STATUS_SE3",
1231   "type_ref": "GRBM_STATUS_SE0"
1232  },
1233  {
1234   "chips": ["gfx103"],
1235   "map": {"at": 33296, "to": "mm"},
1236   "name": "CP_CPC_STATUS",
1237   "type_ref": "CP_CPC_STATUS"
1238  },
1239  {
1240   "chips": ["gfx103"],
1241   "map": {"at": 33300, "to": "mm"},
1242   "name": "CP_CPC_BUSY_STAT",
1243   "type_ref": "CP_CPC_BUSY_STAT"
1244  },
1245  {
1246   "chips": ["gfx103"],
1247   "map": {"at": 33304, "to": "mm"},
1248   "name": "CP_CPC_STALLED_STAT1",
1249   "type_ref": "CP_CPC_STALLED_STAT1"
1250  },
1251  {
1252   "chips": ["gfx103"],
1253   "map": {"at": 33308, "to": "mm"},
1254   "name": "CP_CPF_STATUS",
1255   "type_ref": "CP_CPF_STATUS"
1256  },
1257  {
1258   "chips": ["gfx103"],
1259   "map": {"at": 33312, "to": "mm"},
1260   "name": "CP_CPF_BUSY_STAT",
1261   "type_ref": "CP_CPF_BUSY_STAT"
1262  },
1263  {
1264   "chips": ["gfx103"],
1265   "map": {"at": 33316, "to": "mm"},
1266   "name": "CP_CPF_STALLED_STAT1",
1267   "type_ref": "CP_CPF_STALLED_STAT1"
1268  },
1269  {
1270   "chips": ["gfx103"],
1271   "map": {"at": 33320, "to": "mm"},
1272   "name": "CP_CPC_BUSY_STAT2",
1273   "type_ref": "CP_CPC_BUSY_STAT2"
1274  },
1275  {
1276   "chips": ["gfx103"],
1277   "map": {"at": 33324, "to": "mm"},
1278   "name": "CP_CPC_GRBM_FREE_COUNT",
1279   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1280  },
1281  {
1282   "chips": ["gfx103"],
1283   "map": {"at": 33328, "to": "mm"},
1284   "name": "CP_CPC_PRIV_VIOLATION_ADDR",
1285   "type_ref": "CP_CPC_PRIV_VIOLATION_ADDR"
1286  },
1287  {
1288   "chips": ["gfx103"],
1289   "map": {"at": 33344, "to": "mm"},
1290   "name": "CP_CPC_SCRATCH_INDEX",
1291   "type_ref": "CP_CPC_SCRATCH_INDEX"
1292  },
1293  {
1294   "chips": ["gfx103"],
1295   "map": {"at": 33348, "to": "mm"},
1296   "name": "CP_CPC_SCRATCH_DATA",
1297   "type_ref": "CP_CPC_SCRATCH_DATA"
1298  },
1299  {
1300   "chips": ["gfx103"],
1301   "map": {"at": 33352, "to": "mm"},
1302   "name": "CP_CPF_GRBM_FREE_COUNT",
1303   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1304  },
1305  {
1306   "chips": ["gfx103"],
1307   "map": {"at": 33356, "to": "mm"},
1308   "name": "CP_CPF_BUSY_STAT2",
1309   "type_ref": "CP_CPF_BUSY_STAT2"
1310  },
1311  {
1312   "chips": ["gfx103"],
1313   "map": {"at": 33436, "to": "mm"},
1314   "name": "CP_CPC_HALT_HYST_COUNT",
1315   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1316  },
1317  {
1318   "chips": ["gfx103"],
1319   "map": {"at": 36096, "to": "mm"},
1320   "name": "SQ_THREAD_TRACE_BUF0_BASE",
1321   "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1322  },
1323  {
1324   "chips": ["gfx103"],
1325   "map": {"at": 36100, "to": "mm"},
1326   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
1327   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1328  },
1329  {
1330   "chips": ["gfx103"],
1331   "map": {"at": 36104, "to": "mm"},
1332   "name": "SQ_THREAD_TRACE_BUF1_BASE",
1333   "type_ref": "SQ_THREAD_TRACE_BUF0_BASE"
1334  },
1335  {
1336   "chips": ["gfx103"],
1337   "map": {"at": 36108, "to": "mm"},
1338   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
1339   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
1340  },
1341  {
1342   "chips": ["gfx103"],
1343   "map": {"at": 36112, "to": "mm"},
1344   "name": "SQ_THREAD_TRACE_WPTR",
1345   "type_ref": "SQ_THREAD_TRACE_WPTR"
1346  },
1347  {
1348   "chips": ["gfx103"],
1349   "map": {"at": 36116, "to": "mm"},
1350   "name": "SQ_THREAD_TRACE_MASK",
1351   "type_ref": "SQ_THREAD_TRACE_MASK"
1352  },
1353  {
1354   "chips": ["gfx103"],
1355   "map": {"at": 36120, "to": "mm"},
1356   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
1357   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
1358  },
1359  {
1360   "chips": ["gfx103"],
1361   "map": {"at": 36124, "to": "mm"},
1362   "name": "SQ_THREAD_TRACE_CTRL",
1363   "type_ref": "SQ_THREAD_TRACE_CTRL"
1364  },
1365  {
1366   "chips": ["gfx103"],
1367   "map": {"at": 36128, "to": "mm"},
1368   "name": "SQ_THREAD_TRACE_STATUS",
1369   "type_ref": "SQ_THREAD_TRACE_STATUS"
1370  },
1371  {
1372   "chips": ["gfx103"],
1373   "map": {"at": 36132, "to": "mm"},
1374   "name": "SQ_THREAD_TRACE_DROPPED_CNTR",
1375   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1376  },
1377  {
1378   "chips": ["gfx103"],
1379   "map": {"at": 36140, "to": "mm"},
1380   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR",
1381   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1382  },
1383  {
1384   "chips": ["gfx103"],
1385   "map": {"at": 36144, "to": "mm"},
1386   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR",
1387   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1388  },
1389  {
1390   "chips": ["gfx103"],
1391   "map": {"at": 36148, "to": "mm"},
1392   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR",
1393   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1394  },
1395  {
1396   "chips": ["gfx103"],
1397   "map": {"at": 36152, "to": "mm"},
1398   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR",
1399   "type_ref": "SQ_THREAD_TRACE_DROPPED_CNTR"
1400  },
1401  {
1402   "chips": ["gfx103"],
1403   "map": {"at": 36156, "to": "mm"},
1404   "name": "SQ_THREAD_TRACE_STATUS2",
1405   "type_ref": "SQ_THREAD_TRACE_STATUS2"
1406  },
1407  {
1408   "chips": ["gfx103"],
1409   "map": {"at": 37168, "to": "mm"},
1410   "name": "SPI_CONFIG_CNTL",
1411   "type_ref": "SPI_CONFIG_CNTL"
1412  },
1413  {
1414   "chips": ["gfx103"],
1415   "map": {"at": 39160, "to": "mm"},
1416   "name": "GB_ADDR_CONFIG",
1417   "type_ref": "GB_ADDR_CONFIG"
1418  },
1419  {
1420   "chips": ["gfx103"],
1421   "map": {"at": 45060, "to": "mm"},
1422   "name": "SPI_SHADER_PGM_RSRC4_PS",
1423   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1424  },
1425  {
1426   "chips": ["gfx103"],
1427   "map": {"at": 45080, "to": "mm"},
1428   "name": "SPI_SHADER_PGM_CHKSUM_PS",
1429   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
1430  },
1431  {
1432   "chips": ["gfx103"],
1433   "map": {"at": 45084, "to": "mm"},
1434   "name": "SPI_SHADER_PGM_RSRC3_PS",
1435   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1436  },
1437  {
1438   "chips": ["gfx103"],
1439   "map": {"at": 45088, "to": "mm"},
1440   "name": "SPI_SHADER_PGM_LO_PS",
1441   "type_ref": "SPI_SHADER_PGM_LO_PS"
1442  },
1443  {
1444   "chips": ["gfx103"],
1445   "map": {"at": 45092, "to": "mm"},
1446   "name": "SPI_SHADER_PGM_HI_PS",
1447   "type_ref": "SPI_SHADER_PGM_HI_PS"
1448  },
1449  {
1450   "chips": ["gfx103"],
1451   "map": {"at": 45096, "to": "mm"},
1452   "name": "SPI_SHADER_PGM_RSRC1_PS",
1453   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1454  },
1455  {
1456   "chips": ["gfx103"],
1457   "map": {"at": 45100, "to": "mm"},
1458   "name": "SPI_SHADER_PGM_RSRC2_PS",
1459   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1460  },
1461  {
1462   "chips": ["gfx103"],
1463   "map": {"at": 45104, "to": "mm"},
1464   "name": "SPI_SHADER_USER_DATA_PS_0",
1465   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1466  },
1467  {
1468   "chips": ["gfx103"],
1469   "map": {"at": 45108, "to": "mm"},
1470   "name": "SPI_SHADER_USER_DATA_PS_1",
1471   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1472  },
1473  {
1474   "chips": ["gfx103"],
1475   "map": {"at": 45112, "to": "mm"},
1476   "name": "SPI_SHADER_USER_DATA_PS_2",
1477   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1478  },
1479  {
1480   "chips": ["gfx103"],
1481   "map": {"at": 45116, "to": "mm"},
1482   "name": "SPI_SHADER_USER_DATA_PS_3",
1483   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1484  },
1485  {
1486   "chips": ["gfx103"],
1487   "map": {"at": 45120, "to": "mm"},
1488   "name": "SPI_SHADER_USER_DATA_PS_4",
1489   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1490  },
1491  {
1492   "chips": ["gfx103"],
1493   "map": {"at": 45124, "to": "mm"},
1494   "name": "SPI_SHADER_USER_DATA_PS_5",
1495   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1496  },
1497  {
1498   "chips": ["gfx103"],
1499   "map": {"at": 45128, "to": "mm"},
1500   "name": "SPI_SHADER_USER_DATA_PS_6",
1501   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1502  },
1503  {
1504   "chips": ["gfx103"],
1505   "map": {"at": 45132, "to": "mm"},
1506   "name": "SPI_SHADER_USER_DATA_PS_7",
1507   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1508  },
1509  {
1510   "chips": ["gfx103"],
1511   "map": {"at": 45136, "to": "mm"},
1512   "name": "SPI_SHADER_USER_DATA_PS_8",
1513   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1514  },
1515  {
1516   "chips": ["gfx103"],
1517   "map": {"at": 45140, "to": "mm"},
1518   "name": "SPI_SHADER_USER_DATA_PS_9",
1519   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1520  },
1521  {
1522   "chips": ["gfx103"],
1523   "map": {"at": 45144, "to": "mm"},
1524   "name": "SPI_SHADER_USER_DATA_PS_10",
1525   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1526  },
1527  {
1528   "chips": ["gfx103"],
1529   "map": {"at": 45148, "to": "mm"},
1530   "name": "SPI_SHADER_USER_DATA_PS_11",
1531   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1532  },
1533  {
1534   "chips": ["gfx103"],
1535   "map": {"at": 45152, "to": "mm"},
1536   "name": "SPI_SHADER_USER_DATA_PS_12",
1537   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1538  },
1539  {
1540   "chips": ["gfx103"],
1541   "map": {"at": 45156, "to": "mm"},
1542   "name": "SPI_SHADER_USER_DATA_PS_13",
1543   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1544  },
1545  {
1546   "chips": ["gfx103"],
1547   "map": {"at": 45160, "to": "mm"},
1548   "name": "SPI_SHADER_USER_DATA_PS_14",
1549   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1550  },
1551  {
1552   "chips": ["gfx103"],
1553   "map": {"at": 45164, "to": "mm"},
1554   "name": "SPI_SHADER_USER_DATA_PS_15",
1555   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1556  },
1557  {
1558   "chips": ["gfx103"],
1559   "map": {"at": 45168, "to": "mm"},
1560   "name": "SPI_SHADER_USER_DATA_PS_16",
1561   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1562  },
1563  {
1564   "chips": ["gfx103"],
1565   "map": {"at": 45172, "to": "mm"},
1566   "name": "SPI_SHADER_USER_DATA_PS_17",
1567   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1568  },
1569  {
1570   "chips": ["gfx103"],
1571   "map": {"at": 45176, "to": "mm"},
1572   "name": "SPI_SHADER_USER_DATA_PS_18",
1573   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1574  },
1575  {
1576   "chips": ["gfx103"],
1577   "map": {"at": 45180, "to": "mm"},
1578   "name": "SPI_SHADER_USER_DATA_PS_19",
1579   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1580  },
1581  {
1582   "chips": ["gfx103"],
1583   "map": {"at": 45184, "to": "mm"},
1584   "name": "SPI_SHADER_USER_DATA_PS_20",
1585   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1586  },
1587  {
1588   "chips": ["gfx103"],
1589   "map": {"at": 45188, "to": "mm"},
1590   "name": "SPI_SHADER_USER_DATA_PS_21",
1591   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1592  },
1593  {
1594   "chips": ["gfx103"],
1595   "map": {"at": 45192, "to": "mm"},
1596   "name": "SPI_SHADER_USER_DATA_PS_22",
1597   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1598  },
1599  {
1600   "chips": ["gfx103"],
1601   "map": {"at": 45196, "to": "mm"},
1602   "name": "SPI_SHADER_USER_DATA_PS_23",
1603   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1604  },
1605  {
1606   "chips": ["gfx103"],
1607   "map": {"at": 45200, "to": "mm"},
1608   "name": "SPI_SHADER_USER_DATA_PS_24",
1609   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1610  },
1611  {
1612   "chips": ["gfx103"],
1613   "map": {"at": 45204, "to": "mm"},
1614   "name": "SPI_SHADER_USER_DATA_PS_25",
1615   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1616  },
1617  {
1618   "chips": ["gfx103"],
1619   "map": {"at": 45208, "to": "mm"},
1620   "name": "SPI_SHADER_USER_DATA_PS_26",
1621   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1622  },
1623  {
1624   "chips": ["gfx103"],
1625   "map": {"at": 45212, "to": "mm"},
1626   "name": "SPI_SHADER_USER_DATA_PS_27",
1627   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1628  },
1629  {
1630   "chips": ["gfx103"],
1631   "map": {"at": 45216, "to": "mm"},
1632   "name": "SPI_SHADER_USER_DATA_PS_28",
1633   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1634  },
1635  {
1636   "chips": ["gfx103"],
1637   "map": {"at": 45220, "to": "mm"},
1638   "name": "SPI_SHADER_USER_DATA_PS_29",
1639   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1640  },
1641  {
1642   "chips": ["gfx103"],
1643   "map": {"at": 45224, "to": "mm"},
1644   "name": "SPI_SHADER_USER_DATA_PS_30",
1645   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1646  },
1647  {
1648   "chips": ["gfx103"],
1649   "map": {"at": 45228, "to": "mm"},
1650   "name": "SPI_SHADER_USER_DATA_PS_31",
1651   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1652  },
1653  {
1654   "chips": ["gfx103"],
1655   "map": {"at": 45248, "to": "mm"},
1656   "name": "SPI_SHADER_REQ_CTRL_PS",
1657   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1658  },
1659  {
1660   "chips": ["gfx103"],
1661   "map": {"at": 45256, "to": "mm"},
1662   "name": "SPI_SHADER_USER_ACCUM_PS_0",
1663   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1664  },
1665  {
1666   "chips": ["gfx103"],
1667   "map": {"at": 45260, "to": "mm"},
1668   "name": "SPI_SHADER_USER_ACCUM_PS_1",
1669   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1670  },
1671  {
1672   "chips": ["gfx103"],
1673   "map": {"at": 45264, "to": "mm"},
1674   "name": "SPI_SHADER_USER_ACCUM_PS_2",
1675   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1676  },
1677  {
1678   "chips": ["gfx103"],
1679   "map": {"at": 45268, "to": "mm"},
1680   "name": "SPI_SHADER_USER_ACCUM_PS_3",
1681   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1682  },
1683  {
1684   "chips": ["gfx103"],
1685   "map": {"at": 45316, "to": "mm"},
1686   "name": "SPI_SHADER_PGM_RSRC4_VS",
1687   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1688  },
1689  {
1690   "chips": ["gfx103"],
1691   "map": {"at": 45332, "to": "mm"},
1692   "name": "SPI_SHADER_PGM_CHKSUM_VS",
1693   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
1694  },
1695  {
1696   "chips": ["gfx103"],
1697   "map": {"at": 45336, "to": "mm"},
1698   "name": "SPI_SHADER_PGM_RSRC3_VS",
1699   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1700  },
1701  {
1702   "chips": ["gfx103"],
1703   "map": {"at": 45340, "to": "mm"},
1704   "name": "SPI_SHADER_LATE_ALLOC_VS",
1705   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
1706  },
1707  {
1708   "chips": ["gfx103"],
1709   "map": {"at": 45344, "to": "mm"},
1710   "name": "SPI_SHADER_PGM_LO_VS",
1711   "type_ref": "SPI_SHADER_PGM_LO_PS"
1712  },
1713  {
1714   "chips": ["gfx103"],
1715   "map": {"at": 45348, "to": "mm"},
1716   "name": "SPI_SHADER_PGM_HI_VS",
1717   "type_ref": "SPI_SHADER_PGM_HI_PS"
1718  },
1719  {
1720   "chips": ["gfx103"],
1721   "map": {"at": 45352, "to": "mm"},
1722   "name": "SPI_SHADER_PGM_RSRC1_VS",
1723   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
1724  },
1725  {
1726   "chips": ["gfx103"],
1727   "map": {"at": 45356, "to": "mm"},
1728   "name": "SPI_SHADER_PGM_RSRC2_VS",
1729   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
1730  },
1731  {
1732   "chips": ["gfx103"],
1733   "map": {"at": 45360, "to": "mm"},
1734   "name": "SPI_SHADER_USER_DATA_VS_0",
1735   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1736  },
1737  {
1738   "chips": ["gfx103"],
1739   "map": {"at": 45364, "to": "mm"},
1740   "name": "SPI_SHADER_USER_DATA_VS_1",
1741   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1742  },
1743  {
1744   "chips": ["gfx103"],
1745   "map": {"at": 45368, "to": "mm"},
1746   "name": "SPI_SHADER_USER_DATA_VS_2",
1747   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1748  },
1749  {
1750   "chips": ["gfx103"],
1751   "map": {"at": 45372, "to": "mm"},
1752   "name": "SPI_SHADER_USER_DATA_VS_3",
1753   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1754  },
1755  {
1756   "chips": ["gfx103"],
1757   "map": {"at": 45376, "to": "mm"},
1758   "name": "SPI_SHADER_USER_DATA_VS_4",
1759   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1760  },
1761  {
1762   "chips": ["gfx103"],
1763   "map": {"at": 45380, "to": "mm"},
1764   "name": "SPI_SHADER_USER_DATA_VS_5",
1765   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1766  },
1767  {
1768   "chips": ["gfx103"],
1769   "map": {"at": 45384, "to": "mm"},
1770   "name": "SPI_SHADER_USER_DATA_VS_6",
1771   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1772  },
1773  {
1774   "chips": ["gfx103"],
1775   "map": {"at": 45388, "to": "mm"},
1776   "name": "SPI_SHADER_USER_DATA_VS_7",
1777   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1778  },
1779  {
1780   "chips": ["gfx103"],
1781   "map": {"at": 45392, "to": "mm"},
1782   "name": "SPI_SHADER_USER_DATA_VS_8",
1783   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1784  },
1785  {
1786   "chips": ["gfx103"],
1787   "map": {"at": 45396, "to": "mm"},
1788   "name": "SPI_SHADER_USER_DATA_VS_9",
1789   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1790  },
1791  {
1792   "chips": ["gfx103"],
1793   "map": {"at": 45400, "to": "mm"},
1794   "name": "SPI_SHADER_USER_DATA_VS_10",
1795   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1796  },
1797  {
1798   "chips": ["gfx103"],
1799   "map": {"at": 45404, "to": "mm"},
1800   "name": "SPI_SHADER_USER_DATA_VS_11",
1801   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1802  },
1803  {
1804   "chips": ["gfx103"],
1805   "map": {"at": 45408, "to": "mm"},
1806   "name": "SPI_SHADER_USER_DATA_VS_12",
1807   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1808  },
1809  {
1810   "chips": ["gfx103"],
1811   "map": {"at": 45412, "to": "mm"},
1812   "name": "SPI_SHADER_USER_DATA_VS_13",
1813   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1814  },
1815  {
1816   "chips": ["gfx103"],
1817   "map": {"at": 45416, "to": "mm"},
1818   "name": "SPI_SHADER_USER_DATA_VS_14",
1819   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1820  },
1821  {
1822   "chips": ["gfx103"],
1823   "map": {"at": 45420, "to": "mm"},
1824   "name": "SPI_SHADER_USER_DATA_VS_15",
1825   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1826  },
1827  {
1828   "chips": ["gfx103"],
1829   "map": {"at": 45424, "to": "mm"},
1830   "name": "SPI_SHADER_USER_DATA_VS_16",
1831   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1832  },
1833  {
1834   "chips": ["gfx103"],
1835   "map": {"at": 45428, "to": "mm"},
1836   "name": "SPI_SHADER_USER_DATA_VS_17",
1837   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1838  },
1839  {
1840   "chips": ["gfx103"],
1841   "map": {"at": 45432, "to": "mm"},
1842   "name": "SPI_SHADER_USER_DATA_VS_18",
1843   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1844  },
1845  {
1846   "chips": ["gfx103"],
1847   "map": {"at": 45436, "to": "mm"},
1848   "name": "SPI_SHADER_USER_DATA_VS_19",
1849   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1850  },
1851  {
1852   "chips": ["gfx103"],
1853   "map": {"at": 45440, "to": "mm"},
1854   "name": "SPI_SHADER_USER_DATA_VS_20",
1855   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1856  },
1857  {
1858   "chips": ["gfx103"],
1859   "map": {"at": 45444, "to": "mm"},
1860   "name": "SPI_SHADER_USER_DATA_VS_21",
1861   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1862  },
1863  {
1864   "chips": ["gfx103"],
1865   "map": {"at": 45448, "to": "mm"},
1866   "name": "SPI_SHADER_USER_DATA_VS_22",
1867   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1868  },
1869  {
1870   "chips": ["gfx103"],
1871   "map": {"at": 45452, "to": "mm"},
1872   "name": "SPI_SHADER_USER_DATA_VS_23",
1873   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1874  },
1875  {
1876   "chips": ["gfx103"],
1877   "map": {"at": 45456, "to": "mm"},
1878   "name": "SPI_SHADER_USER_DATA_VS_24",
1879   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1880  },
1881  {
1882   "chips": ["gfx103"],
1883   "map": {"at": 45460, "to": "mm"},
1884   "name": "SPI_SHADER_USER_DATA_VS_25",
1885   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1886  },
1887  {
1888   "chips": ["gfx103"],
1889   "map": {"at": 45464, "to": "mm"},
1890   "name": "SPI_SHADER_USER_DATA_VS_26",
1891   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1892  },
1893  {
1894   "chips": ["gfx103"],
1895   "map": {"at": 45468, "to": "mm"},
1896   "name": "SPI_SHADER_USER_DATA_VS_27",
1897   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1898  },
1899  {
1900   "chips": ["gfx103"],
1901   "map": {"at": 45472, "to": "mm"},
1902   "name": "SPI_SHADER_USER_DATA_VS_28",
1903   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1904  },
1905  {
1906   "chips": ["gfx103"],
1907   "map": {"at": 45476, "to": "mm"},
1908   "name": "SPI_SHADER_USER_DATA_VS_29",
1909   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1910  },
1911  {
1912   "chips": ["gfx103"],
1913   "map": {"at": 45480, "to": "mm"},
1914   "name": "SPI_SHADER_USER_DATA_VS_30",
1915   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1916  },
1917  {
1918   "chips": ["gfx103"],
1919   "map": {"at": 45484, "to": "mm"},
1920   "name": "SPI_SHADER_USER_DATA_VS_31",
1921   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
1922  },
1923  {
1924   "chips": ["gfx103"],
1925   "map": {"at": 45504, "to": "mm"},
1926   "name": "SPI_SHADER_REQ_CTRL_VS",
1927   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1928  },
1929  {
1930   "chips": ["gfx103"],
1931   "map": {"at": 45512, "to": "mm"},
1932   "name": "SPI_SHADER_USER_ACCUM_VS_0",
1933   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1934  },
1935  {
1936   "chips": ["gfx103"],
1937   "map": {"at": 45516, "to": "mm"},
1938   "name": "SPI_SHADER_USER_ACCUM_VS_1",
1939   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1940  },
1941  {
1942   "chips": ["gfx103"],
1943   "map": {"at": 45520, "to": "mm"},
1944   "name": "SPI_SHADER_USER_ACCUM_VS_2",
1945   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1946  },
1947  {
1948   "chips": ["gfx103"],
1949   "map": {"at": 45524, "to": "mm"},
1950   "name": "SPI_SHADER_USER_ACCUM_VS_3",
1951   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1952  },
1953  {
1954   "chips": ["gfx103"],
1955   "map": {"at": 45548, "to": "mm"},
1956   "name": "SPI_SHADER_PGM_RSRC2_GS_VS",
1957   "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS"
1958  },
1959  {
1960   "chips": ["gfx103"],
1961   "map": {"at": 45568, "to": "mm"},
1962   "name": "SPI_SHADER_PGM_CHKSUM_GS",
1963   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
1964  },
1965  {
1966   "chips": ["gfx103"],
1967   "map": {"at": 45572, "to": "mm"},
1968   "name": "SPI_SHADER_PGM_RSRC4_GS",
1969   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
1970  },
1971  {
1972   "chips": ["gfx103"],
1973   "map": {"at": 45576, "to": "mm"},
1974   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS",
1975   "type_ref": "SPI_SHADER_PGM_LO_PS"
1976  },
1977  {
1978   "chips": ["gfx103"],
1979   "map": {"at": 45580, "to": "mm"},
1980   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS",
1981   "type_ref": "SPI_SHADER_PGM_LO_PS"
1982  },
1983  {
1984   "chips": ["gfx103"],
1985   "map": {"at": 45584, "to": "mm"},
1986   "name": "SPI_SHADER_PGM_LO_ES_GS",
1987   "type_ref": "SPI_SHADER_PGM_LO_PS"
1988  },
1989  {
1990   "chips": ["gfx103"],
1991   "map": {"at": 45588, "to": "mm"},
1992   "name": "SPI_SHADER_PGM_HI_ES_GS",
1993   "type_ref": "SPI_SHADER_PGM_HI_PS"
1994  },
1995  {
1996   "chips": ["gfx103"],
1997   "map": {"at": 45596, "to": "mm"},
1998   "name": "SPI_SHADER_PGM_RSRC3_GS",
1999   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2000  },
2001  {
2002   "chips": ["gfx103"],
2003   "map": {"at": 45600, "to": "mm"},
2004   "name": "SPI_SHADER_PGM_LO_GS",
2005   "type_ref": "SPI_SHADER_PGM_LO_PS"
2006  },
2007  {
2008   "chips": ["gfx103"],
2009   "map": {"at": 45604, "to": "mm"},
2010   "name": "SPI_SHADER_PGM_HI_GS",
2011   "type_ref": "SPI_SHADER_PGM_HI_PS"
2012  },
2013  {
2014   "chips": ["gfx103"],
2015   "map": {"at": 45608, "to": "mm"},
2016   "name": "SPI_SHADER_PGM_RSRC1_GS",
2017   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2018  },
2019  {
2020   "chips": ["gfx103"],
2021   "map": {"at": 45612, "to": "mm"},
2022   "name": "SPI_SHADER_PGM_RSRC2_GS",
2023   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2024  },
2025  {
2026   "chips": ["gfx103"],
2027   "map": {"at": 45616, "to": "mm"},
2028   "name": "SPI_SHADER_USER_DATA_GS_0",
2029   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2030  },
2031  {
2032   "chips": ["gfx103"],
2033   "map": {"at": 45620, "to": "mm"},
2034   "name": "SPI_SHADER_USER_DATA_GS_1",
2035   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2036  },
2037  {
2038   "chips": ["gfx103"],
2039   "map": {"at": 45624, "to": "mm"},
2040   "name": "SPI_SHADER_USER_DATA_GS_2",
2041   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2042  },
2043  {
2044   "chips": ["gfx103"],
2045   "map": {"at": 45628, "to": "mm"},
2046   "name": "SPI_SHADER_USER_DATA_GS_3",
2047   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2048  },
2049  {
2050   "chips": ["gfx103"],
2051   "map": {"at": 45632, "to": "mm"},
2052   "name": "SPI_SHADER_USER_DATA_GS_4",
2053   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2054  },
2055  {
2056   "chips": ["gfx103"],
2057   "map": {"at": 45636, "to": "mm"},
2058   "name": "SPI_SHADER_USER_DATA_GS_5",
2059   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2060  },
2061  {
2062   "chips": ["gfx103"],
2063   "map": {"at": 45640, "to": "mm"},
2064   "name": "SPI_SHADER_USER_DATA_GS_6",
2065   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2066  },
2067  {
2068   "chips": ["gfx103"],
2069   "map": {"at": 45644, "to": "mm"},
2070   "name": "SPI_SHADER_USER_DATA_GS_7",
2071   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2072  },
2073  {
2074   "chips": ["gfx103"],
2075   "map": {"at": 45648, "to": "mm"},
2076   "name": "SPI_SHADER_USER_DATA_GS_8",
2077   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2078  },
2079  {
2080   "chips": ["gfx103"],
2081   "map": {"at": 45652, "to": "mm"},
2082   "name": "SPI_SHADER_USER_DATA_GS_9",
2083   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2084  },
2085  {
2086   "chips": ["gfx103"],
2087   "map": {"at": 45656, "to": "mm"},
2088   "name": "SPI_SHADER_USER_DATA_GS_10",
2089   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2090  },
2091  {
2092   "chips": ["gfx103"],
2093   "map": {"at": 45660, "to": "mm"},
2094   "name": "SPI_SHADER_USER_DATA_GS_11",
2095   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2096  },
2097  {
2098   "chips": ["gfx103"],
2099   "map": {"at": 45664, "to": "mm"},
2100   "name": "SPI_SHADER_USER_DATA_GS_12",
2101   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2102  },
2103  {
2104   "chips": ["gfx103"],
2105   "map": {"at": 45668, "to": "mm"},
2106   "name": "SPI_SHADER_USER_DATA_GS_13",
2107   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2108  },
2109  {
2110   "chips": ["gfx103"],
2111   "map": {"at": 45672, "to": "mm"},
2112   "name": "SPI_SHADER_USER_DATA_GS_14",
2113   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2114  },
2115  {
2116   "chips": ["gfx103"],
2117   "map": {"at": 45676, "to": "mm"},
2118   "name": "SPI_SHADER_USER_DATA_GS_15",
2119   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2120  },
2121  {
2122   "chips": ["gfx103"],
2123   "map": {"at": 45680, "to": "mm"},
2124   "name": "SPI_SHADER_USER_DATA_GS_16",
2125   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2126  },
2127  {
2128   "chips": ["gfx103"],
2129   "map": {"at": 45684, "to": "mm"},
2130   "name": "SPI_SHADER_USER_DATA_GS_17",
2131   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2132  },
2133  {
2134   "chips": ["gfx103"],
2135   "map": {"at": 45688, "to": "mm"},
2136   "name": "SPI_SHADER_USER_DATA_GS_18",
2137   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2138  },
2139  {
2140   "chips": ["gfx103"],
2141   "map": {"at": 45692, "to": "mm"},
2142   "name": "SPI_SHADER_USER_DATA_GS_19",
2143   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2144  },
2145  {
2146   "chips": ["gfx103"],
2147   "map": {"at": 45696, "to": "mm"},
2148   "name": "SPI_SHADER_USER_DATA_GS_20",
2149   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2150  },
2151  {
2152   "chips": ["gfx103"],
2153   "map": {"at": 45700, "to": "mm"},
2154   "name": "SPI_SHADER_USER_DATA_GS_21",
2155   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2156  },
2157  {
2158   "chips": ["gfx103"],
2159   "map": {"at": 45704, "to": "mm"},
2160   "name": "SPI_SHADER_USER_DATA_GS_22",
2161   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2162  },
2163  {
2164   "chips": ["gfx103"],
2165   "map": {"at": 45708, "to": "mm"},
2166   "name": "SPI_SHADER_USER_DATA_GS_23",
2167   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2168  },
2169  {
2170   "chips": ["gfx103"],
2171   "map": {"at": 45712, "to": "mm"},
2172   "name": "SPI_SHADER_USER_DATA_GS_24",
2173   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2174  },
2175  {
2176   "chips": ["gfx103"],
2177   "map": {"at": 45716, "to": "mm"},
2178   "name": "SPI_SHADER_USER_DATA_GS_25",
2179   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2180  },
2181  {
2182   "chips": ["gfx103"],
2183   "map": {"at": 45720, "to": "mm"},
2184   "name": "SPI_SHADER_USER_DATA_GS_26",
2185   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2186  },
2187  {
2188   "chips": ["gfx103"],
2189   "map": {"at": 45724, "to": "mm"},
2190   "name": "SPI_SHADER_USER_DATA_GS_27",
2191   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2192  },
2193  {
2194   "chips": ["gfx103"],
2195   "map": {"at": 45728, "to": "mm"},
2196   "name": "SPI_SHADER_USER_DATA_GS_28",
2197   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2198  },
2199  {
2200   "chips": ["gfx103"],
2201   "map": {"at": 45732, "to": "mm"},
2202   "name": "SPI_SHADER_USER_DATA_GS_29",
2203   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2204  },
2205  {
2206   "chips": ["gfx103"],
2207   "map": {"at": 45736, "to": "mm"},
2208   "name": "SPI_SHADER_USER_DATA_GS_30",
2209   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2210  },
2211  {
2212   "chips": ["gfx103"],
2213   "map": {"at": 45740, "to": "mm"},
2214   "name": "SPI_SHADER_USER_DATA_GS_31",
2215   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2216  },
2217  {
2218   "chips": ["gfx103"],
2219   "map": {"at": 45760, "to": "mm"},
2220   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2221   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2222  },
2223  {
2224   "chips": ["gfx103"],
2225   "map": {"at": 45768, "to": "mm"},
2226   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2227   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2228  },
2229  {
2230   "chips": ["gfx103"],
2231   "map": {"at": 45772, "to": "mm"},
2232   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2233   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2234  },
2235  {
2236   "chips": ["gfx103"],
2237   "map": {"at": 45776, "to": "mm"},
2238   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2239   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2240  },
2241  {
2242   "chips": ["gfx103"],
2243   "map": {"at": 45780, "to": "mm"},
2244   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2245   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2246  },
2247  {
2248   "chips": ["gfx103"],
2249   "map": {"at": 45856, "to": "mm"},
2250   "name": "SPI_SHADER_PGM_LO_ES",
2251   "type_ref": "SPI_SHADER_PGM_LO_PS"
2252  },
2253  {
2254   "chips": ["gfx103"],
2255   "map": {"at": 45860, "to": "mm"},
2256   "name": "SPI_SHADER_PGM_HI_ES",
2257   "type_ref": "SPI_SHADER_PGM_HI_PS"
2258  },
2259  {
2260   "chips": ["gfx103"],
2261   "map": {"at": 46080, "to": "mm"},
2262   "name": "SPI_SHADER_PGM_CHKSUM_HS",
2263   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2264  },
2265  {
2266   "chips": ["gfx103"],
2267   "map": {"at": 46084, "to": "mm"},
2268   "name": "SPI_SHADER_PGM_RSRC4_HS",
2269   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2270  },
2271  {
2272   "chips": ["gfx103"],
2273   "map": {"at": 46088, "to": "mm"},
2274   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS",
2275   "type_ref": "SPI_SHADER_PGM_LO_PS"
2276  },
2277  {
2278   "chips": ["gfx103"],
2279   "map": {"at": 46092, "to": "mm"},
2280   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS",
2281   "type_ref": "SPI_SHADER_PGM_LO_PS"
2282  },
2283  {
2284   "chips": ["gfx103"],
2285   "map": {"at": 46096, "to": "mm"},
2286   "name": "SPI_SHADER_PGM_LO_LS_HS",
2287   "type_ref": "SPI_SHADER_PGM_LO_PS"
2288  },
2289  {
2290   "chips": ["gfx103"],
2291   "map": {"at": 46100, "to": "mm"},
2292   "name": "SPI_SHADER_PGM_HI_LS_HS",
2293   "type_ref": "SPI_SHADER_PGM_HI_PS"
2294  },
2295  {
2296   "chips": ["gfx103"],
2297   "map": {"at": 46108, "to": "mm"},
2298   "name": "SPI_SHADER_PGM_RSRC3_HS",
2299   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2300  },
2301  {
2302   "chips": ["gfx103"],
2303   "map": {"at": 46112, "to": "mm"},
2304   "name": "SPI_SHADER_PGM_LO_HS",
2305   "type_ref": "SPI_SHADER_PGM_LO_PS"
2306  },
2307  {
2308   "chips": ["gfx103"],
2309   "map": {"at": 46116, "to": "mm"},
2310   "name": "SPI_SHADER_PGM_HI_HS",
2311   "type_ref": "SPI_SHADER_PGM_HI_PS"
2312  },
2313  {
2314   "chips": ["gfx103"],
2315   "map": {"at": 46120, "to": "mm"},
2316   "name": "SPI_SHADER_PGM_RSRC1_HS",
2317   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2318  },
2319  {
2320   "chips": ["gfx103"],
2321   "map": {"at": 46124, "to": "mm"},
2322   "name": "SPI_SHADER_PGM_RSRC2_HS",
2323   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2324  },
2325  {
2326   "chips": ["gfx103"],
2327   "map": {"at": 46128, "to": "mm"},
2328   "name": "SPI_SHADER_USER_DATA_HS_0",
2329   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2330  },
2331  {
2332   "chips": ["gfx103"],
2333   "map": {"at": 46132, "to": "mm"},
2334   "name": "SPI_SHADER_USER_DATA_HS_1",
2335   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2336  },
2337  {
2338   "chips": ["gfx103"],
2339   "map": {"at": 46136, "to": "mm"},
2340   "name": "SPI_SHADER_USER_DATA_HS_2",
2341   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2342  },
2343  {
2344   "chips": ["gfx103"],
2345   "map": {"at": 46140, "to": "mm"},
2346   "name": "SPI_SHADER_USER_DATA_HS_3",
2347   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2348  },
2349  {
2350   "chips": ["gfx103"],
2351   "map": {"at": 46144, "to": "mm"},
2352   "name": "SPI_SHADER_USER_DATA_HS_4",
2353   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2354  },
2355  {
2356   "chips": ["gfx103"],
2357   "map": {"at": 46148, "to": "mm"},
2358   "name": "SPI_SHADER_USER_DATA_HS_5",
2359   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2360  },
2361  {
2362   "chips": ["gfx103"],
2363   "map": {"at": 46152, "to": "mm"},
2364   "name": "SPI_SHADER_USER_DATA_HS_6",
2365   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2366  },
2367  {
2368   "chips": ["gfx103"],
2369   "map": {"at": 46156, "to": "mm"},
2370   "name": "SPI_SHADER_USER_DATA_HS_7",
2371   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2372  },
2373  {
2374   "chips": ["gfx103"],
2375   "map": {"at": 46160, "to": "mm"},
2376   "name": "SPI_SHADER_USER_DATA_HS_8",
2377   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2378  },
2379  {
2380   "chips": ["gfx103"],
2381   "map": {"at": 46164, "to": "mm"},
2382   "name": "SPI_SHADER_USER_DATA_HS_9",
2383   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2384  },
2385  {
2386   "chips": ["gfx103"],
2387   "map": {"at": 46168, "to": "mm"},
2388   "name": "SPI_SHADER_USER_DATA_HS_10",
2389   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2390  },
2391  {
2392   "chips": ["gfx103"],
2393   "map": {"at": 46172, "to": "mm"},
2394   "name": "SPI_SHADER_USER_DATA_HS_11",
2395   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2396  },
2397  {
2398   "chips": ["gfx103"],
2399   "map": {"at": 46176, "to": "mm"},
2400   "name": "SPI_SHADER_USER_DATA_HS_12",
2401   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2402  },
2403  {
2404   "chips": ["gfx103"],
2405   "map": {"at": 46180, "to": "mm"},
2406   "name": "SPI_SHADER_USER_DATA_HS_13",
2407   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2408  },
2409  {
2410   "chips": ["gfx103"],
2411   "map": {"at": 46184, "to": "mm"},
2412   "name": "SPI_SHADER_USER_DATA_HS_14",
2413   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2414  },
2415  {
2416   "chips": ["gfx103"],
2417   "map": {"at": 46188, "to": "mm"},
2418   "name": "SPI_SHADER_USER_DATA_HS_15",
2419   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2420  },
2421  {
2422   "chips": ["gfx103"],
2423   "map": {"at": 46192, "to": "mm"},
2424   "name": "SPI_SHADER_USER_DATA_HS_16",
2425   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2426  },
2427  {
2428   "chips": ["gfx103"],
2429   "map": {"at": 46196, "to": "mm"},
2430   "name": "SPI_SHADER_USER_DATA_HS_17",
2431   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2432  },
2433  {
2434   "chips": ["gfx103"],
2435   "map": {"at": 46200, "to": "mm"},
2436   "name": "SPI_SHADER_USER_DATA_HS_18",
2437   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2438  },
2439  {
2440   "chips": ["gfx103"],
2441   "map": {"at": 46204, "to": "mm"},
2442   "name": "SPI_SHADER_USER_DATA_HS_19",
2443   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2444  },
2445  {
2446   "chips": ["gfx103"],
2447   "map": {"at": 46208, "to": "mm"},
2448   "name": "SPI_SHADER_USER_DATA_HS_20",
2449   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2450  },
2451  {
2452   "chips": ["gfx103"],
2453   "map": {"at": 46212, "to": "mm"},
2454   "name": "SPI_SHADER_USER_DATA_HS_21",
2455   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2456  },
2457  {
2458   "chips": ["gfx103"],
2459   "map": {"at": 46216, "to": "mm"},
2460   "name": "SPI_SHADER_USER_DATA_HS_22",
2461   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2462  },
2463  {
2464   "chips": ["gfx103"],
2465   "map": {"at": 46220, "to": "mm"},
2466   "name": "SPI_SHADER_USER_DATA_HS_23",
2467   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2468  },
2469  {
2470   "chips": ["gfx103"],
2471   "map": {"at": 46224, "to": "mm"},
2472   "name": "SPI_SHADER_USER_DATA_HS_24",
2473   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2474  },
2475  {
2476   "chips": ["gfx103"],
2477   "map": {"at": 46228, "to": "mm"},
2478   "name": "SPI_SHADER_USER_DATA_HS_25",
2479   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2480  },
2481  {
2482   "chips": ["gfx103"],
2483   "map": {"at": 46232, "to": "mm"},
2484   "name": "SPI_SHADER_USER_DATA_HS_26",
2485   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2486  },
2487  {
2488   "chips": ["gfx103"],
2489   "map": {"at": 46236, "to": "mm"},
2490   "name": "SPI_SHADER_USER_DATA_HS_27",
2491   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2492  },
2493  {
2494   "chips": ["gfx103"],
2495   "map": {"at": 46240, "to": "mm"},
2496   "name": "SPI_SHADER_USER_DATA_HS_28",
2497   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2498  },
2499  {
2500   "chips": ["gfx103"],
2501   "map": {"at": 46244, "to": "mm"},
2502   "name": "SPI_SHADER_USER_DATA_HS_29",
2503   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2504  },
2505  {
2506   "chips": ["gfx103"],
2507   "map": {"at": 46248, "to": "mm"},
2508   "name": "SPI_SHADER_USER_DATA_HS_30",
2509   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2510  },
2511  {
2512   "chips": ["gfx103"],
2513   "map": {"at": 46252, "to": "mm"},
2514   "name": "SPI_SHADER_USER_DATA_HS_31",
2515   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2516  },
2517  {
2518   "chips": ["gfx103"],
2519   "map": {"at": 46272, "to": "mm"},
2520   "name": "SPI_SHADER_REQ_CTRL_LSHS",
2521   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2522  },
2523  {
2524   "chips": ["gfx103"],
2525   "map": {"at": 46280, "to": "mm"},
2526   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2527   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2528  },
2529  {
2530   "chips": ["gfx103"],
2531   "map": {"at": 46284, "to": "mm"},
2532   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2533   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2534  },
2535  {
2536   "chips": ["gfx103"],
2537   "map": {"at": 46288, "to": "mm"},
2538   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2539   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2540  },
2541  {
2542   "chips": ["gfx103"],
2543   "map": {"at": 46292, "to": "mm"},
2544   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2545   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2546  },
2547  {
2548   "chips": ["gfx103"],
2549   "map": {"at": 46368, "to": "mm"},
2550   "name": "SPI_SHADER_PGM_LO_LS",
2551   "type_ref": "SPI_SHADER_PGM_LO_PS"
2552  },
2553  {
2554   "chips": ["gfx103"],
2555   "map": {"at": 46372, "to": "mm"},
2556   "name": "SPI_SHADER_PGM_HI_LS",
2557   "type_ref": "SPI_SHADER_PGM_HI_PS"
2558  },
2559  {
2560   "chips": ["gfx103"],
2561   "map": {"at": 47104, "to": "mm"},
2562   "name": "COMPUTE_DISPATCH_INITIATOR",
2563   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2564  },
2565  {
2566   "chips": ["gfx103"],
2567   "map": {"at": 47108, "to": "mm"},
2568   "name": "COMPUTE_DIM_X",
2569   "type_ref": "COMPUTE_DIM_X"
2570  },
2571  {
2572   "chips": ["gfx103"],
2573   "map": {"at": 47112, "to": "mm"},
2574   "name": "COMPUTE_DIM_Y",
2575   "type_ref": "COMPUTE_DIM_X"
2576  },
2577  {
2578   "chips": ["gfx103"],
2579   "map": {"at": 47116, "to": "mm"},
2580   "name": "COMPUTE_DIM_Z",
2581   "type_ref": "COMPUTE_DIM_X"
2582  },
2583  {
2584   "chips": ["gfx103"],
2585   "map": {"at": 47120, "to": "mm"},
2586   "name": "COMPUTE_START_X",
2587   "type_ref": "COMPUTE_START_X"
2588  },
2589  {
2590   "chips": ["gfx103"],
2591   "map": {"at": 47124, "to": "mm"},
2592   "name": "COMPUTE_START_Y",
2593   "type_ref": "COMPUTE_START_X"
2594  },
2595  {
2596   "chips": ["gfx103"],
2597   "map": {"at": 47128, "to": "mm"},
2598   "name": "COMPUTE_START_Z",
2599   "type_ref": "COMPUTE_START_X"
2600  },
2601  {
2602   "chips": ["gfx103"],
2603   "map": {"at": 47132, "to": "mm"},
2604   "name": "COMPUTE_NUM_THREAD_X",
2605   "type_ref": "COMPUTE_NUM_THREAD_X"
2606  },
2607  {
2608   "chips": ["gfx103"],
2609   "map": {"at": 47136, "to": "mm"},
2610   "name": "COMPUTE_NUM_THREAD_Y",
2611   "type_ref": "COMPUTE_NUM_THREAD_X"
2612  },
2613  {
2614   "chips": ["gfx103"],
2615   "map": {"at": 47140, "to": "mm"},
2616   "name": "COMPUTE_NUM_THREAD_Z",
2617   "type_ref": "COMPUTE_NUM_THREAD_X"
2618  },
2619  {
2620   "chips": ["gfx103"],
2621   "map": {"at": 47144, "to": "mm"},
2622   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2623   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2624  },
2625  {
2626   "chips": ["gfx103"],
2627   "map": {"at": 47148, "to": "mm"},
2628   "name": "COMPUTE_PERFCOUNT_ENABLE",
2629   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2630  },
2631  {
2632   "chips": ["gfx103"],
2633   "map": {"at": 47152, "to": "mm"},
2634   "name": "COMPUTE_PGM_LO",
2635   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2636  },
2637  {
2638   "chips": ["gfx103"],
2639   "map": {"at": 47156, "to": "mm"},
2640   "name": "COMPUTE_PGM_HI",
2641   "type_ref": "COMPUTE_PGM_HI"
2642  },
2643  {
2644   "chips": ["gfx103"],
2645   "map": {"at": 47160, "to": "mm"},
2646   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO",
2647   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2648  },
2649  {
2650   "chips": ["gfx103"],
2651   "map": {"at": 47164, "to": "mm"},
2652   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
2653   "type_ref": "COMPUTE_PGM_HI"
2654  },
2655  {
2656   "chips": ["gfx103"],
2657   "map": {"at": 47168, "to": "mm"},
2658   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO",
2659   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2660  },
2661  {
2662   "chips": ["gfx103"],
2663   "map": {"at": 47172, "to": "mm"},
2664   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
2665   "type_ref": "COMPUTE_PGM_HI"
2666  },
2667  {
2668   "chips": ["gfx103"],
2669   "map": {"at": 47176, "to": "mm"},
2670   "name": "COMPUTE_PGM_RSRC1",
2671   "type_ref": "COMPUTE_PGM_RSRC1"
2672  },
2673  {
2674   "chips": ["gfx103"],
2675   "map": {"at": 47180, "to": "mm"},
2676   "name": "COMPUTE_PGM_RSRC2",
2677   "type_ref": "COMPUTE_PGM_RSRC2"
2678  },
2679  {
2680   "chips": ["gfx103"],
2681   "map": {"at": 47184, "to": "mm"},
2682   "name": "COMPUTE_VMID",
2683   "type_ref": "COMPUTE_VMID"
2684  },
2685  {
2686   "chips": ["gfx103"],
2687   "map": {"at": 47188, "to": "mm"},
2688   "name": "COMPUTE_RESOURCE_LIMITS",
2689   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2690  },
2691  {
2692   "chips": ["gfx103"],
2693   "map": {"at": 47192, "to": "mm"},
2694   "name": "COMPUTE_DESTINATION_EN_SE0",
2695   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
2696  },
2697  {
2698   "chips": ["gfx103"],
2699   "map": {"at": 47196, "to": "mm"},
2700   "name": "COMPUTE_DESTINATION_EN_SE1",
2701   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
2702  },
2703  {
2704   "chips": ["gfx103"],
2705   "map": {"at": 47200, "to": "mm"},
2706   "name": "COMPUTE_TMPRING_SIZE",
2707   "type_ref": "COMPUTE_TMPRING_SIZE"
2708  },
2709  {
2710   "chips": ["gfx103"],
2711   "map": {"at": 47204, "to": "mm"},
2712   "name": "COMPUTE_DESTINATION_EN_SE2",
2713   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
2714  },
2715  {
2716   "chips": ["gfx103"],
2717   "map": {"at": 47208, "to": "mm"},
2718   "name": "COMPUTE_DESTINATION_EN_SE3",
2719   "type_ref": "COMPUTE_DESTINATION_EN_SE0"
2720  },
2721  {
2722   "chips": ["gfx103"],
2723   "map": {"at": 47212, "to": "mm"},
2724   "name": "COMPUTE_RESTART_X",
2725   "type_ref": "COMPUTE_RESTART_X"
2726  },
2727  {
2728   "chips": ["gfx103"],
2729   "map": {"at": 47216, "to": "mm"},
2730   "name": "COMPUTE_RESTART_Y",
2731   "type_ref": "COMPUTE_RESTART_X"
2732  },
2733  {
2734   "chips": ["gfx103"],
2735   "map": {"at": 47220, "to": "mm"},
2736   "name": "COMPUTE_RESTART_Z",
2737   "type_ref": "COMPUTE_RESTART_X"
2738  },
2739  {
2740   "chips": ["gfx103"],
2741   "map": {"at": 47224, "to": "mm"},
2742   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2743   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2744  },
2745  {
2746   "chips": ["gfx103"],
2747   "map": {"at": 47228, "to": "mm"},
2748   "name": "COMPUTE_MISC_RESERVED",
2749   "type_ref": "COMPUTE_MISC_RESERVED"
2750  },
2751  {
2752   "chips": ["gfx103"],
2753   "map": {"at": 47232, "to": "mm"},
2754   "name": "COMPUTE_DISPATCH_ID",
2755   "type_ref": "COMPUTE_DISPATCH_ID"
2756  },
2757  {
2758   "chips": ["gfx103"],
2759   "map": {"at": 47236, "to": "mm"},
2760   "name": "COMPUTE_THREADGROUP_ID",
2761   "type_ref": "COMPUTE_THREADGROUP_ID"
2762  },
2763  {
2764   "chips": ["gfx103"],
2765   "map": {"at": 47240, "to": "mm"},
2766   "name": "COMPUTE_REQ_CTRL",
2767   "type_ref": "COMPUTE_REQ_CTRL"
2768  },
2769  {
2770   "chips": ["gfx103"],
2771   "map": {"at": 47248, "to": "mm"},
2772   "name": "COMPUTE_USER_ACCUM_0",
2773   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2774  },
2775  {
2776   "chips": ["gfx103"],
2777   "map": {"at": 47252, "to": "mm"},
2778   "name": "COMPUTE_USER_ACCUM_1",
2779   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2780  },
2781  {
2782   "chips": ["gfx103"],
2783   "map": {"at": 47256, "to": "mm"},
2784   "name": "COMPUTE_USER_ACCUM_2",
2785   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2786  },
2787  {
2788   "chips": ["gfx103"],
2789   "map": {"at": 47260, "to": "mm"},
2790   "name": "COMPUTE_USER_ACCUM_3",
2791   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2792  },
2793  {
2794   "chips": ["gfx103"],
2795   "map": {"at": 47264, "to": "mm"},
2796   "name": "COMPUTE_PGM_RSRC3",
2797   "type_ref": "COMPUTE_PGM_RSRC3"
2798  },
2799  {
2800   "chips": ["gfx103"],
2801   "map": {"at": 47268, "to": "mm"},
2802   "name": "COMPUTE_DDID_INDEX",
2803   "type_ref": "COMPUTE_DDID_INDEX"
2804  },
2805  {
2806   "chips": ["gfx103"],
2807   "map": {"at": 47272, "to": "mm"},
2808   "name": "COMPUTE_SHADER_CHKSUM",
2809   "type_ref": "SPI_SHADER_PGM_CHKSUM_PS"
2810  },
2811  {
2812   "chips": ["gfx103"],
2813   "map": {"at": 47276, "to": "mm"},
2814   "name": "COMPUTE_RELAUNCH",
2815   "type_ref": "COMPUTE_RELAUNCH"
2816  },
2817  {
2818   "chips": ["gfx103"],
2819   "map": {"at": 47280, "to": "mm"},
2820   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO",
2821   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2822  },
2823  {
2824   "chips": ["gfx103"],
2825   "map": {"at": 47284, "to": "mm"},
2826   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2827   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2828  },
2829  {
2830   "chips": ["gfx103"],
2831   "map": {"at": 47288, "to": "mm"},
2832   "name": "COMPUTE_RELAUNCH2",
2833   "type_ref": "COMPUTE_RELAUNCH"
2834  },
2835  {
2836   "chips": ["gfx103"],
2837   "map": {"at": 47360, "to": "mm"},
2838   "name": "COMPUTE_USER_DATA_0",
2839   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2840  },
2841  {
2842   "chips": ["gfx103"],
2843   "map": {"at": 47364, "to": "mm"},
2844   "name": "COMPUTE_USER_DATA_1",
2845   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2846  },
2847  {
2848   "chips": ["gfx103"],
2849   "map": {"at": 47368, "to": "mm"},
2850   "name": "COMPUTE_USER_DATA_2",
2851   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2852  },
2853  {
2854   "chips": ["gfx103"],
2855   "map": {"at": 47372, "to": "mm"},
2856   "name": "COMPUTE_USER_DATA_3",
2857   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2858  },
2859  {
2860   "chips": ["gfx103"],
2861   "map": {"at": 47376, "to": "mm"},
2862   "name": "COMPUTE_USER_DATA_4",
2863   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2864  },
2865  {
2866   "chips": ["gfx103"],
2867   "map": {"at": 47380, "to": "mm"},
2868   "name": "COMPUTE_USER_DATA_5",
2869   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2870  },
2871  {
2872   "chips": ["gfx103"],
2873   "map": {"at": 47384, "to": "mm"},
2874   "name": "COMPUTE_USER_DATA_6",
2875   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2876  },
2877  {
2878   "chips": ["gfx103"],
2879   "map": {"at": 47388, "to": "mm"},
2880   "name": "COMPUTE_USER_DATA_7",
2881   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2882  },
2883  {
2884   "chips": ["gfx103"],
2885   "map": {"at": 47392, "to": "mm"},
2886   "name": "COMPUTE_USER_DATA_8",
2887   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2888  },
2889  {
2890   "chips": ["gfx103"],
2891   "map": {"at": 47396, "to": "mm"},
2892   "name": "COMPUTE_USER_DATA_9",
2893   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2894  },
2895  {
2896   "chips": ["gfx103"],
2897   "map": {"at": 47400, "to": "mm"},
2898   "name": "COMPUTE_USER_DATA_10",
2899   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2900  },
2901  {
2902   "chips": ["gfx103"],
2903   "map": {"at": 47404, "to": "mm"},
2904   "name": "COMPUTE_USER_DATA_11",
2905   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2906  },
2907  {
2908   "chips": ["gfx103"],
2909   "map": {"at": 47408, "to": "mm"},
2910   "name": "COMPUTE_USER_DATA_12",
2911   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2912  },
2913  {
2914   "chips": ["gfx103"],
2915   "map": {"at": 47412, "to": "mm"},
2916   "name": "COMPUTE_USER_DATA_13",
2917   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2918  },
2919  {
2920   "chips": ["gfx103"],
2921   "map": {"at": 47416, "to": "mm"},
2922   "name": "COMPUTE_USER_DATA_14",
2923   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2924  },
2925  {
2926   "chips": ["gfx103"],
2927   "map": {"at": 47420, "to": "mm"},
2928   "name": "COMPUTE_USER_DATA_15",
2929   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2930  },
2931  {
2932   "chips": ["gfx103"],
2933   "map": {"at": 47604, "to": "mm"},
2934   "name": "COMPUTE_DISPATCH_TUNNEL",
2935   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
2936  },
2937  {
2938   "chips": ["gfx103"],
2939   "map": {"at": 47608, "to": "mm"},
2940   "name": "COMPUTE_DISPATCH_END",
2941   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2942  },
2943  {
2944   "chips": ["gfx103"],
2945   "map": {"at": 47612, "to": "mm"},
2946   "name": "COMPUTE_NOWHERE",
2947   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2948  },
2949  {
2950   "chips": ["gfx103"],
2951   "map": {"at": 47616, "to": "mm"},
2952   "name": "SH_RESERVED_REG0",
2953   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2954  },
2955  {
2956   "chips": ["gfx103"],
2957   "map": {"at": 47620, "to": "mm"},
2958   "name": "SH_RESERVED_REG1",
2959   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
2960  },
2961  {
2962   "chips": ["gfx103"],
2963   "map": {"at": 163840, "to": "mm"},
2964   "name": "DB_RENDER_CONTROL",
2965   "type_ref": "DB_RENDER_CONTROL"
2966  },
2967  {
2968   "chips": ["gfx103"],
2969   "map": {"at": 163844, "to": "mm"},
2970   "name": "DB_COUNT_CONTROL",
2971   "type_ref": "DB_COUNT_CONTROL"
2972  },
2973  {
2974   "chips": ["gfx103"],
2975   "map": {"at": 163848, "to": "mm"},
2976   "name": "DB_DEPTH_VIEW",
2977   "type_ref": "DB_DEPTH_VIEW"
2978  },
2979  {
2980   "chips": ["gfx103"],
2981   "map": {"at": 163852, "to": "mm"},
2982   "name": "DB_RENDER_OVERRIDE",
2983   "type_ref": "DB_RENDER_OVERRIDE"
2984  },
2985  {
2986   "chips": ["gfx103"],
2987   "map": {"at": 163856, "to": "mm"},
2988   "name": "DB_RENDER_OVERRIDE2",
2989   "type_ref": "DB_RENDER_OVERRIDE2"
2990  },
2991  {
2992   "chips": ["gfx103"],
2993   "map": {"at": 163860, "to": "mm"},
2994   "name": "DB_HTILE_DATA_BASE",
2995   "type_ref": "DB_HTILE_DATA_BASE"
2996  },
2997  {
2998   "chips": ["gfx103"],
2999   "map": {"at": 163868, "to": "mm"},
3000   "name": "DB_DEPTH_SIZE_XY",
3001   "type_ref": "DB_DEPTH_SIZE_XY"
3002  },
3003  {
3004   "chips": ["gfx103"],
3005   "map": {"at": 163872, "to": "mm"},
3006   "name": "DB_DEPTH_BOUNDS_MIN",
3007   "type_ref": "DB_DEPTH_BOUNDS_MIN"
3008  },
3009  {
3010   "chips": ["gfx103"],
3011   "map": {"at": 163876, "to": "mm"},
3012   "name": "DB_DEPTH_BOUNDS_MAX",
3013   "type_ref": "DB_DEPTH_BOUNDS_MAX"
3014  },
3015  {
3016   "chips": ["gfx103"],
3017   "map": {"at": 163880, "to": "mm"},
3018   "name": "DB_STENCIL_CLEAR",
3019   "type_ref": "DB_STENCIL_CLEAR"
3020  },
3021  {
3022   "chips": ["gfx103"],
3023   "map": {"at": 163884, "to": "mm"},
3024   "name": "DB_DEPTH_CLEAR",
3025   "type_ref": "DB_DEPTH_CLEAR"
3026  },
3027  {
3028   "chips": ["gfx103"],
3029   "map": {"at": 163888, "to": "mm"},
3030   "name": "PA_SC_SCREEN_SCISSOR_TL",
3031   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3032  },
3033  {
3034   "chips": ["gfx103"],
3035   "map": {"at": 163892, "to": "mm"},
3036   "name": "PA_SC_SCREEN_SCISSOR_BR",
3037   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3038  },
3039  {
3040   "chips": ["gfx103"],
3041   "map": {"at": 163896, "to": "mm"},
3042   "name": "DB_DFSM_CONTROL",
3043   "type_ref": "DB_DFSM_CONTROL"
3044  },
3045  {
3046   "chips": ["gfx103"],
3047   "map": {"at": 163900, "to": "mm"},
3048   "name": "DB_RESERVED_REG_2",
3049   "type_ref": "DB_RESERVED_REG_2"
3050  },
3051  {
3052   "chips": ["gfx103"],
3053   "map": {"at": 163904, "to": "mm"},
3054   "name": "DB_Z_INFO",
3055   "type_ref": "DB_Z_INFO"
3056  },
3057  {
3058   "chips": ["gfx103"],
3059   "map": {"at": 163908, "to": "mm"},
3060   "name": "DB_STENCIL_INFO",
3061   "type_ref": "DB_STENCIL_INFO"
3062  },
3063  {
3064   "chips": ["gfx103"],
3065   "map": {"at": 163912, "to": "mm"},
3066   "name": "DB_Z_READ_BASE",
3067   "type_ref": "DB_HTILE_DATA_BASE"
3068  },
3069  {
3070   "chips": ["gfx103"],
3071   "map": {"at": 163916, "to": "mm"},
3072   "name": "DB_STENCIL_READ_BASE",
3073   "type_ref": "DB_HTILE_DATA_BASE"
3074  },
3075  {
3076   "chips": ["gfx103"],
3077   "map": {"at": 163920, "to": "mm"},
3078   "name": "DB_Z_WRITE_BASE",
3079   "type_ref": "DB_HTILE_DATA_BASE"
3080  },
3081  {
3082   "chips": ["gfx103"],
3083   "map": {"at": 163924, "to": "mm"},
3084   "name": "DB_STENCIL_WRITE_BASE",
3085   "type_ref": "DB_HTILE_DATA_BASE"
3086  },
3087  {
3088   "chips": ["gfx103"],
3089   "map": {"at": 163928, "to": "mm"},
3090   "name": "DB_RESERVED_REG_1",
3091   "type_ref": "DB_RESERVED_REG_1"
3092  },
3093  {
3094   "chips": ["gfx103"],
3095   "map": {"at": 163932, "to": "mm"},
3096   "name": "DB_RESERVED_REG_3",
3097   "type_ref": "DB_RESERVED_REG_3"
3098  },
3099  {
3100   "chips": ["gfx103"],
3101   "map": {"at": 163940, "to": "mm"},
3102   "name": "DB_VRS_OVERRIDE_CNTL",
3103   "type_ref": "DB_VRS_OVERRIDE_CNTL"
3104  },
3105  {
3106   "chips": ["gfx103"],
3107   "map": {"at": 163944, "to": "mm"},
3108   "name": "DB_Z_READ_BASE_HI",
3109   "type_ref": "DB_Z_READ_BASE_HI"
3110  },
3111  {
3112   "chips": ["gfx103"],
3113   "map": {"at": 163948, "to": "mm"},
3114   "name": "DB_STENCIL_READ_BASE_HI",
3115   "type_ref": "DB_Z_READ_BASE_HI"
3116  },
3117  {
3118   "chips": ["gfx103"],
3119   "map": {"at": 163952, "to": "mm"},
3120   "name": "DB_Z_WRITE_BASE_HI",
3121   "type_ref": "DB_Z_READ_BASE_HI"
3122  },
3123  {
3124   "chips": ["gfx103"],
3125   "map": {"at": 163956, "to": "mm"},
3126   "name": "DB_STENCIL_WRITE_BASE_HI",
3127   "type_ref": "DB_Z_READ_BASE_HI"
3128  },
3129  {
3130   "chips": ["gfx103"],
3131   "map": {"at": 163960, "to": "mm"},
3132   "name": "DB_HTILE_DATA_BASE_HI",
3133   "type_ref": "DB_Z_READ_BASE_HI"
3134  },
3135  {
3136   "chips": ["gfx103"],
3137   "map": {"at": 163964, "to": "mm"},
3138   "name": "DB_RMI_L2_CACHE_CONTROL",
3139   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
3140  },
3141  {
3142   "chips": ["gfx103"],
3143   "map": {"at": 163968, "to": "mm"},
3144   "name": "TA_BC_BASE_ADDR",
3145   "type_ref": "TA_BC_BASE_ADDR"
3146  },
3147  {
3148   "chips": ["gfx103"],
3149   "map": {"at": 163972, "to": "mm"},
3150   "name": "TA_BC_BASE_ADDR_HI",
3151   "type_ref": "TA_BC_BASE_ADDR_HI"
3152  },
3153  {
3154   "chips": ["gfx103"],
3155   "map": {"at": 164328, "to": "mm"},
3156   "name": "COHER_DEST_BASE_HI_0",
3157   "type_ref": "COHER_DEST_BASE_HI_0"
3158  },
3159  {
3160   "chips": ["gfx103"],
3161   "map": {"at": 164332, "to": "mm"},
3162   "name": "COHER_DEST_BASE_HI_1",
3163   "type_ref": "COHER_DEST_BASE_HI_0"
3164  },
3165  {
3166   "chips": ["gfx103"],
3167   "map": {"at": 164336, "to": "mm"},
3168   "name": "COHER_DEST_BASE_HI_2",
3169   "type_ref": "COHER_DEST_BASE_HI_0"
3170  },
3171  {
3172   "chips": ["gfx103"],
3173   "map": {"at": 164340, "to": "mm"},
3174   "name": "COHER_DEST_BASE_HI_3",
3175   "type_ref": "COHER_DEST_BASE_HI_0"
3176  },
3177  {
3178   "chips": ["gfx103"],
3179   "map": {"at": 164344, "to": "mm"},
3180   "name": "COHER_DEST_BASE_2",
3181   "type_ref": "COHER_DEST_BASE_2"
3182  },
3183  {
3184   "chips": ["gfx103"],
3185   "map": {"at": 164348, "to": "mm"},
3186   "name": "COHER_DEST_BASE_3",
3187   "type_ref": "COHER_DEST_BASE_2"
3188  },
3189  {
3190   "chips": ["gfx103"],
3191   "map": {"at": 164352, "to": "mm"},
3192   "name": "PA_SC_WINDOW_OFFSET",
3193   "type_ref": "PA_SC_WINDOW_OFFSET"
3194  },
3195  {
3196   "chips": ["gfx103"],
3197   "map": {"at": 164356, "to": "mm"},
3198   "name": "PA_SC_WINDOW_SCISSOR_TL",
3199   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3200  },
3201  {
3202   "chips": ["gfx103"],
3203   "map": {"at": 164360, "to": "mm"},
3204   "name": "PA_SC_WINDOW_SCISSOR_BR",
3205   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3206  },
3207  {
3208   "chips": ["gfx103"],
3209   "map": {"at": 164364, "to": "mm"},
3210   "name": "PA_SC_CLIPRECT_RULE",
3211   "type_ref": "PA_SC_CLIPRECT_RULE"
3212  },
3213  {
3214   "chips": ["gfx103"],
3215   "map": {"at": 164368, "to": "mm"},
3216   "name": "PA_SC_CLIPRECT_0_TL",
3217   "type_ref": "PA_SC_CLIPRECT_0_TL"
3218  },
3219  {
3220   "chips": ["gfx103"],
3221   "map": {"at": 164372, "to": "mm"},
3222   "name": "PA_SC_CLIPRECT_0_BR",
3223   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3224  },
3225  {
3226   "chips": ["gfx103"],
3227   "map": {"at": 164376, "to": "mm"},
3228   "name": "PA_SC_CLIPRECT_1_TL",
3229   "type_ref": "PA_SC_CLIPRECT_0_TL"
3230  },
3231  {
3232   "chips": ["gfx103"],
3233   "map": {"at": 164380, "to": "mm"},
3234   "name": "PA_SC_CLIPRECT_1_BR",
3235   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3236  },
3237  {
3238   "chips": ["gfx103"],
3239   "map": {"at": 164384, "to": "mm"},
3240   "name": "PA_SC_CLIPRECT_2_TL",
3241   "type_ref": "PA_SC_CLIPRECT_0_TL"
3242  },
3243  {
3244   "chips": ["gfx103"],
3245   "map": {"at": 164388, "to": "mm"},
3246   "name": "PA_SC_CLIPRECT_2_BR",
3247   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3248  },
3249  {
3250   "chips": ["gfx103"],
3251   "map": {"at": 164392, "to": "mm"},
3252   "name": "PA_SC_CLIPRECT_3_TL",
3253   "type_ref": "PA_SC_CLIPRECT_0_TL"
3254  },
3255  {
3256   "chips": ["gfx103"],
3257   "map": {"at": 164396, "to": "mm"},
3258   "name": "PA_SC_CLIPRECT_3_BR",
3259   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3260  },
3261  {
3262   "chips": ["gfx103"],
3263   "map": {"at": 164400, "to": "mm"},
3264   "name": "PA_SC_EDGERULE",
3265   "type_ref": "PA_SC_EDGERULE"
3266  },
3267  {
3268   "chips": ["gfx103"],
3269   "map": {"at": 164404, "to": "mm"},
3270   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3271   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3272  },
3273  {
3274   "chips": ["gfx103"],
3275   "map": {"at": 164408, "to": "mm"},
3276   "name": "CB_TARGET_MASK",
3277   "type_ref": "CB_TARGET_MASK"
3278  },
3279  {
3280   "chips": ["gfx103"],
3281   "map": {"at": 164412, "to": "mm"},
3282   "name": "CB_SHADER_MASK",
3283   "type_ref": "CB_SHADER_MASK"
3284  },
3285  {
3286   "chips": ["gfx103"],
3287   "map": {"at": 164416, "to": "mm"},
3288   "name": "PA_SC_GENERIC_SCISSOR_TL",
3289   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3290  },
3291  {
3292   "chips": ["gfx103"],
3293   "map": {"at": 164420, "to": "mm"},
3294   "name": "PA_SC_GENERIC_SCISSOR_BR",
3295   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3296  },
3297  {
3298   "chips": ["gfx103"],
3299   "map": {"at": 164424, "to": "mm"},
3300   "name": "COHER_DEST_BASE_0",
3301   "type_ref": "COHER_DEST_BASE_2"
3302  },
3303  {
3304   "chips": ["gfx103"],
3305   "map": {"at": 164428, "to": "mm"},
3306   "name": "COHER_DEST_BASE_1",
3307   "type_ref": "COHER_DEST_BASE_2"
3308  },
3309  {
3310   "chips": ["gfx103"],
3311   "map": {"at": 164432, "to": "mm"},
3312   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3313   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3314  },
3315  {
3316   "chips": ["gfx103"],
3317   "map": {"at": 164436, "to": "mm"},
3318   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3319   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3320  },
3321  {
3322   "chips": ["gfx103"],
3323   "map": {"at": 164440, "to": "mm"},
3324   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3325   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3326  },
3327  {
3328   "chips": ["gfx103"],
3329   "map": {"at": 164444, "to": "mm"},
3330   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3331   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3332  },
3333  {
3334   "chips": ["gfx103"],
3335   "map": {"at": 164448, "to": "mm"},
3336   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3337   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3338  },
3339  {
3340   "chips": ["gfx103"],
3341   "map": {"at": 164452, "to": "mm"},
3342   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3343   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3344  },
3345  {
3346   "chips": ["gfx103"],
3347   "map": {"at": 164456, "to": "mm"},
3348   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3349   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3350  },
3351  {
3352   "chips": ["gfx103"],
3353   "map": {"at": 164460, "to": "mm"},
3354   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3355   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3356  },
3357  {
3358   "chips": ["gfx103"],
3359   "map": {"at": 164464, "to": "mm"},
3360   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3361   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3362  },
3363  {
3364   "chips": ["gfx103"],
3365   "map": {"at": 164468, "to": "mm"},
3366   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3367   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3368  },
3369  {
3370   "chips": ["gfx103"],
3371   "map": {"at": 164472, "to": "mm"},
3372   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3373   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3374  },
3375  {
3376   "chips": ["gfx103"],
3377   "map": {"at": 164476, "to": "mm"},
3378   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3379   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3380  },
3381  {
3382   "chips": ["gfx103"],
3383   "map": {"at": 164480, "to": "mm"},
3384   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3385   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3386  },
3387  {
3388   "chips": ["gfx103"],
3389   "map": {"at": 164484, "to": "mm"},
3390   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3391   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3392  },
3393  {
3394   "chips": ["gfx103"],
3395   "map": {"at": 164488, "to": "mm"},
3396   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3397   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3398  },
3399  {
3400   "chips": ["gfx103"],
3401   "map": {"at": 164492, "to": "mm"},
3402   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3403   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3404  },
3405  {
3406   "chips": ["gfx103"],
3407   "map": {"at": 164496, "to": "mm"},
3408   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3409   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3410  },
3411  {
3412   "chips": ["gfx103"],
3413   "map": {"at": 164500, "to": "mm"},
3414   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3415   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3416  },
3417  {
3418   "chips": ["gfx103"],
3419   "map": {"at": 164504, "to": "mm"},
3420   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3421   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3422  },
3423  {
3424   "chips": ["gfx103"],
3425   "map": {"at": 164508, "to": "mm"},
3426   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3427   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3428  },
3429  {
3430   "chips": ["gfx103"],
3431   "map": {"at": 164512, "to": "mm"},
3432   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3433   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3434  },
3435  {
3436   "chips": ["gfx103"],
3437   "map": {"at": 164516, "to": "mm"},
3438   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3439   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3440  },
3441  {
3442   "chips": ["gfx103"],
3443   "map": {"at": 164520, "to": "mm"},
3444   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3445   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3446  },
3447  {
3448   "chips": ["gfx103"],
3449   "map": {"at": 164524, "to": "mm"},
3450   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3451   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3452  },
3453  {
3454   "chips": ["gfx103"],
3455   "map": {"at": 164528, "to": "mm"},
3456   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3457   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3458  },
3459  {
3460   "chips": ["gfx103"],
3461   "map": {"at": 164532, "to": "mm"},
3462   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3463   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3464  },
3465  {
3466   "chips": ["gfx103"],
3467   "map": {"at": 164536, "to": "mm"},
3468   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3469   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3470  },
3471  {
3472   "chips": ["gfx103"],
3473   "map": {"at": 164540, "to": "mm"},
3474   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3475   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3476  },
3477  {
3478   "chips": ["gfx103"],
3479   "map": {"at": 164544, "to": "mm"},
3480   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3481   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3482  },
3483  {
3484   "chips": ["gfx103"],
3485   "map": {"at": 164548, "to": "mm"},
3486   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3487   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3488  },
3489  {
3490   "chips": ["gfx103"],
3491   "map": {"at": 164552, "to": "mm"},
3492   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3493   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3494  },
3495  {
3496   "chips": ["gfx103"],
3497   "map": {"at": 164556, "to": "mm"},
3498   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3499   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3500  },
3501  {
3502   "chips": ["gfx103"],
3503   "map": {"at": 164560, "to": "mm"},
3504   "name": "PA_SC_VPORT_ZMIN_0",
3505   "type_ref": "PA_SC_VPORT_ZMIN_0"
3506  },
3507  {
3508   "chips": ["gfx103"],
3509   "map": {"at": 164564, "to": "mm"},
3510   "name": "PA_SC_VPORT_ZMAX_0",
3511   "type_ref": "PA_SC_VPORT_ZMAX_0"
3512  },
3513  {
3514   "chips": ["gfx103"],
3515   "map": {"at": 164568, "to": "mm"},
3516   "name": "PA_SC_VPORT_ZMIN_1",
3517   "type_ref": "PA_SC_VPORT_ZMIN_0"
3518  },
3519  {
3520   "chips": ["gfx103"],
3521   "map": {"at": 164572, "to": "mm"},
3522   "name": "PA_SC_VPORT_ZMAX_1",
3523   "type_ref": "PA_SC_VPORT_ZMAX_0"
3524  },
3525  {
3526   "chips": ["gfx103"],
3527   "map": {"at": 164576, "to": "mm"},
3528   "name": "PA_SC_VPORT_ZMIN_2",
3529   "type_ref": "PA_SC_VPORT_ZMIN_0"
3530  },
3531  {
3532   "chips": ["gfx103"],
3533   "map": {"at": 164580, "to": "mm"},
3534   "name": "PA_SC_VPORT_ZMAX_2",
3535   "type_ref": "PA_SC_VPORT_ZMAX_0"
3536  },
3537  {
3538   "chips": ["gfx103"],
3539   "map": {"at": 164584, "to": "mm"},
3540   "name": "PA_SC_VPORT_ZMIN_3",
3541   "type_ref": "PA_SC_VPORT_ZMIN_0"
3542  },
3543  {
3544   "chips": ["gfx103"],
3545   "map": {"at": 164588, "to": "mm"},
3546   "name": "PA_SC_VPORT_ZMAX_3",
3547   "type_ref": "PA_SC_VPORT_ZMAX_0"
3548  },
3549  {
3550   "chips": ["gfx103"],
3551   "map": {"at": 164592, "to": "mm"},
3552   "name": "PA_SC_VPORT_ZMIN_4",
3553   "type_ref": "PA_SC_VPORT_ZMIN_0"
3554  },
3555  {
3556   "chips": ["gfx103"],
3557   "map": {"at": 164596, "to": "mm"},
3558   "name": "PA_SC_VPORT_ZMAX_4",
3559   "type_ref": "PA_SC_VPORT_ZMAX_0"
3560  },
3561  {
3562   "chips": ["gfx103"],
3563   "map": {"at": 164600, "to": "mm"},
3564   "name": "PA_SC_VPORT_ZMIN_5",
3565   "type_ref": "PA_SC_VPORT_ZMIN_0"
3566  },
3567  {
3568   "chips": ["gfx103"],
3569   "map": {"at": 164604, "to": "mm"},
3570   "name": "PA_SC_VPORT_ZMAX_5",
3571   "type_ref": "PA_SC_VPORT_ZMAX_0"
3572  },
3573  {
3574   "chips": ["gfx103"],
3575   "map": {"at": 164608, "to": "mm"},
3576   "name": "PA_SC_VPORT_ZMIN_6",
3577   "type_ref": "PA_SC_VPORT_ZMIN_0"
3578  },
3579  {
3580   "chips": ["gfx103"],
3581   "map": {"at": 164612, "to": "mm"},
3582   "name": "PA_SC_VPORT_ZMAX_6",
3583   "type_ref": "PA_SC_VPORT_ZMAX_0"
3584  },
3585  {
3586   "chips": ["gfx103"],
3587   "map": {"at": 164616, "to": "mm"},
3588   "name": "PA_SC_VPORT_ZMIN_7",
3589   "type_ref": "PA_SC_VPORT_ZMIN_0"
3590  },
3591  {
3592   "chips": ["gfx103"],
3593   "map": {"at": 164620, "to": "mm"},
3594   "name": "PA_SC_VPORT_ZMAX_7",
3595   "type_ref": "PA_SC_VPORT_ZMAX_0"
3596  },
3597  {
3598   "chips": ["gfx103"],
3599   "map": {"at": 164624, "to": "mm"},
3600   "name": "PA_SC_VPORT_ZMIN_8",
3601   "type_ref": "PA_SC_VPORT_ZMIN_0"
3602  },
3603  {
3604   "chips": ["gfx103"],
3605   "map": {"at": 164628, "to": "mm"},
3606   "name": "PA_SC_VPORT_ZMAX_8",
3607   "type_ref": "PA_SC_VPORT_ZMAX_0"
3608  },
3609  {
3610   "chips": ["gfx103"],
3611   "map": {"at": 164632, "to": "mm"},
3612   "name": "PA_SC_VPORT_ZMIN_9",
3613   "type_ref": "PA_SC_VPORT_ZMIN_0"
3614  },
3615  {
3616   "chips": ["gfx103"],
3617   "map": {"at": 164636, "to": "mm"},
3618   "name": "PA_SC_VPORT_ZMAX_9",
3619   "type_ref": "PA_SC_VPORT_ZMAX_0"
3620  },
3621  {
3622   "chips": ["gfx103"],
3623   "map": {"at": 164640, "to": "mm"},
3624   "name": "PA_SC_VPORT_ZMIN_10",
3625   "type_ref": "PA_SC_VPORT_ZMIN_0"
3626  },
3627  {
3628   "chips": ["gfx103"],
3629   "map": {"at": 164644, "to": "mm"},
3630   "name": "PA_SC_VPORT_ZMAX_10",
3631   "type_ref": "PA_SC_VPORT_ZMAX_0"
3632  },
3633  {
3634   "chips": ["gfx103"],
3635   "map": {"at": 164648, "to": "mm"},
3636   "name": "PA_SC_VPORT_ZMIN_11",
3637   "type_ref": "PA_SC_VPORT_ZMIN_0"
3638  },
3639  {
3640   "chips": ["gfx103"],
3641   "map": {"at": 164652, "to": "mm"},
3642   "name": "PA_SC_VPORT_ZMAX_11",
3643   "type_ref": "PA_SC_VPORT_ZMAX_0"
3644  },
3645  {
3646   "chips": ["gfx103"],
3647   "map": {"at": 164656, "to": "mm"},
3648   "name": "PA_SC_VPORT_ZMIN_12",
3649   "type_ref": "PA_SC_VPORT_ZMIN_0"
3650  },
3651  {
3652   "chips": ["gfx103"],
3653   "map": {"at": 164660, "to": "mm"},
3654   "name": "PA_SC_VPORT_ZMAX_12",
3655   "type_ref": "PA_SC_VPORT_ZMAX_0"
3656  },
3657  {
3658   "chips": ["gfx103"],
3659   "map": {"at": 164664, "to": "mm"},
3660   "name": "PA_SC_VPORT_ZMIN_13",
3661   "type_ref": "PA_SC_VPORT_ZMIN_0"
3662  },
3663  {
3664   "chips": ["gfx103"],
3665   "map": {"at": 164668, "to": "mm"},
3666   "name": "PA_SC_VPORT_ZMAX_13",
3667   "type_ref": "PA_SC_VPORT_ZMAX_0"
3668  },
3669  {
3670   "chips": ["gfx103"],
3671   "map": {"at": 164672, "to": "mm"},
3672   "name": "PA_SC_VPORT_ZMIN_14",
3673   "type_ref": "PA_SC_VPORT_ZMIN_0"
3674  },
3675  {
3676   "chips": ["gfx103"],
3677   "map": {"at": 164676, "to": "mm"},
3678   "name": "PA_SC_VPORT_ZMAX_14",
3679   "type_ref": "PA_SC_VPORT_ZMAX_0"
3680  },
3681  {
3682   "chips": ["gfx103"],
3683   "map": {"at": 164680, "to": "mm"},
3684   "name": "PA_SC_VPORT_ZMIN_15",
3685   "type_ref": "PA_SC_VPORT_ZMIN_0"
3686  },
3687  {
3688   "chips": ["gfx103"],
3689   "map": {"at": 164684, "to": "mm"},
3690   "name": "PA_SC_VPORT_ZMAX_15",
3691   "type_ref": "PA_SC_VPORT_ZMAX_0"
3692  },
3693  {
3694   "chips": ["gfx103"],
3695   "map": {"at": 164688, "to": "mm"},
3696   "name": "PA_SC_RASTER_CONFIG",
3697   "type_ref": "PA_SC_RASTER_CONFIG"
3698  },
3699  {
3700   "chips": ["gfx103"],
3701   "map": {"at": 164692, "to": "mm"},
3702   "name": "PA_SC_RASTER_CONFIG_1",
3703   "type_ref": "PA_SC_RASTER_CONFIG_1"
3704  },
3705  {
3706   "chips": ["gfx103"],
3707   "map": {"at": 164696, "to": "mm"},
3708   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3709   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3710  },
3711  {
3712   "chips": ["gfx103"],
3713   "map": {"at": 164700, "to": "mm"},
3714   "name": "PA_SC_TILE_STEERING_OVERRIDE",
3715   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
3716  },
3717  {
3718   "chips": ["gfx103"],
3719   "map": {"at": 164704, "to": "mm"},
3720   "name": "CP_PERFMON_CNTX_CNTL",
3721   "type_ref": "CP_PERFMON_CNTX_CNTL"
3722  },
3723  {
3724   "chips": ["gfx103"],
3725   "map": {"at": 164708, "to": "mm"},
3726   "name": "CP_PIPEID",
3727   "type_ref": "CP_PIPEID"
3728  },
3729  {
3730   "chips": ["gfx103"],
3731   "map": {"at": 164712, "to": "mm"},
3732   "name": "CP_VMID",
3733   "type_ref": "CP_VMID"
3734  },
3735  {
3736   "chips": ["gfx103"],
3737   "map": {"at": 164716, "to": "mm"},
3738   "name": "CONTEXT_RESERVED_REG0",
3739   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3740  },
3741  {
3742   "chips": ["gfx103"],
3743   "map": {"at": 164720, "to": "mm"},
3744   "name": "CONTEXT_RESERVED_REG1",
3745   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
3746  },
3747  {
3748   "chips": ["gfx103"],
3749   "map": {"at": 164864, "to": "mm"},
3750   "name": "VGT_MAX_VTX_INDX",
3751   "type_ref": "VGT_MAX_VTX_INDX"
3752  },
3753  {
3754   "chips": ["gfx103"],
3755   "map": {"at": 164868, "to": "mm"},
3756   "name": "VGT_MIN_VTX_INDX",
3757   "type_ref": "VGT_MIN_VTX_INDX"
3758  },
3759  {
3760   "chips": ["gfx103"],
3761   "map": {"at": 164872, "to": "mm"},
3762   "name": "VGT_INDX_OFFSET",
3763   "type_ref": "VGT_INDX_OFFSET"
3764  },
3765  {
3766   "chips": ["gfx103"],
3767   "map": {"at": 164876, "to": "mm"},
3768   "name": "VGT_MULTI_PRIM_IB_RESET_INDX",
3769   "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX"
3770  },
3771  {
3772   "chips": ["gfx103"],
3773   "map": {"at": 164880, "to": "mm"},
3774   "name": "CB_RMI_GL2_CACHE_CONTROL",
3775   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
3776  },
3777  {
3778   "chips": ["gfx103"],
3779   "map": {"at": 164884, "to": "mm"},
3780   "name": "CB_BLEND_RED",
3781   "type_ref": "CB_BLEND_RED"
3782  },
3783  {
3784   "chips": ["gfx103"],
3785   "map": {"at": 164888, "to": "mm"},
3786   "name": "CB_BLEND_GREEN",
3787   "type_ref": "CB_BLEND_GREEN"
3788  },
3789  {
3790   "chips": ["gfx103"],
3791   "map": {"at": 164892, "to": "mm"},
3792   "name": "CB_BLEND_BLUE",
3793   "type_ref": "CB_BLEND_BLUE"
3794  },
3795  {
3796   "chips": ["gfx103"],
3797   "map": {"at": 164896, "to": "mm"},
3798   "name": "CB_BLEND_ALPHA",
3799   "type_ref": "CB_BLEND_ALPHA"
3800  },
3801  {
3802   "chips": ["gfx103"],
3803   "map": {"at": 164900, "to": "mm"},
3804   "name": "CB_DCC_CONTROL",
3805   "type_ref": "CB_DCC_CONTROL"
3806  },
3807  {
3808   "chips": ["gfx103"],
3809   "map": {"at": 164904, "to": "mm"},
3810   "name": "CB_COVERAGE_OUT_CONTROL",
3811   "type_ref": "CB_COVERAGE_OUT_CONTROL"
3812  },
3813  {
3814   "chips": ["gfx103"],
3815   "map": {"at": 164908, "to": "mm"},
3816   "name": "DB_STENCIL_CONTROL",
3817   "type_ref": "DB_STENCIL_CONTROL"
3818  },
3819  {
3820   "chips": ["gfx103"],
3821   "map": {"at": 164912, "to": "mm"},
3822   "name": "DB_STENCILREFMASK",
3823   "type_ref": "DB_STENCILREFMASK"
3824  },
3825  {
3826   "chips": ["gfx103"],
3827   "map": {"at": 164916, "to": "mm"},
3828   "name": "DB_STENCILREFMASK_BF",
3829   "type_ref": "DB_STENCILREFMASK_BF"
3830  },
3831  {
3832   "chips": ["gfx103"],
3833   "map": {"at": 164924, "to": "mm"},
3834   "name": "PA_CL_VPORT_XSCALE",
3835   "type_ref": "PA_CL_VPORT_XSCALE"
3836  },
3837  {
3838   "chips": ["gfx103"],
3839   "map": {"at": 164928, "to": "mm"},
3840   "name": "PA_CL_VPORT_XOFFSET",
3841   "type_ref": "PA_CL_VPORT_XOFFSET"
3842  },
3843  {
3844   "chips": ["gfx103"],
3845   "map": {"at": 164932, "to": "mm"},
3846   "name": "PA_CL_VPORT_YSCALE",
3847   "type_ref": "PA_CL_VPORT_YSCALE"
3848  },
3849  {
3850   "chips": ["gfx103"],
3851   "map": {"at": 164936, "to": "mm"},
3852   "name": "PA_CL_VPORT_YOFFSET",
3853   "type_ref": "PA_CL_VPORT_YOFFSET"
3854  },
3855  {
3856   "chips": ["gfx103"],
3857   "map": {"at": 164940, "to": "mm"},
3858   "name": "PA_CL_VPORT_ZSCALE",
3859   "type_ref": "PA_CL_VPORT_ZSCALE"
3860  },
3861  {
3862   "chips": ["gfx103"],
3863   "map": {"at": 164944, "to": "mm"},
3864   "name": "PA_CL_VPORT_ZOFFSET",
3865   "type_ref": "PA_CL_VPORT_ZOFFSET"
3866  },
3867  {
3868   "chips": ["gfx103"],
3869   "map": {"at": 164948, "to": "mm"},
3870   "name": "PA_CL_VPORT_XSCALE_1",
3871   "type_ref": "PA_CL_VPORT_XSCALE"
3872  },
3873  {
3874   "chips": ["gfx103"],
3875   "map": {"at": 164952, "to": "mm"},
3876   "name": "PA_CL_VPORT_XOFFSET_1",
3877   "type_ref": "PA_CL_VPORT_XOFFSET"
3878  },
3879  {
3880   "chips": ["gfx103"],
3881   "map": {"at": 164956, "to": "mm"},
3882   "name": "PA_CL_VPORT_YSCALE_1",
3883   "type_ref": "PA_CL_VPORT_YSCALE"
3884  },
3885  {
3886   "chips": ["gfx103"],
3887   "map": {"at": 164960, "to": "mm"},
3888   "name": "PA_CL_VPORT_YOFFSET_1",
3889   "type_ref": "PA_CL_VPORT_YOFFSET"
3890  },
3891  {
3892   "chips": ["gfx103"],
3893   "map": {"at": 164964, "to": "mm"},
3894   "name": "PA_CL_VPORT_ZSCALE_1",
3895   "type_ref": "PA_CL_VPORT_ZSCALE"
3896  },
3897  {
3898   "chips": ["gfx103"],
3899   "map": {"at": 164968, "to": "mm"},
3900   "name": "PA_CL_VPORT_ZOFFSET_1",
3901   "type_ref": "PA_CL_VPORT_ZOFFSET"
3902  },
3903  {
3904   "chips": ["gfx103"],
3905   "map": {"at": 164972, "to": "mm"},
3906   "name": "PA_CL_VPORT_XSCALE_2",
3907   "type_ref": "PA_CL_VPORT_XSCALE"
3908  },
3909  {
3910   "chips": ["gfx103"],
3911   "map": {"at": 164976, "to": "mm"},
3912   "name": "PA_CL_VPORT_XOFFSET_2",
3913   "type_ref": "PA_CL_VPORT_XOFFSET"
3914  },
3915  {
3916   "chips": ["gfx103"],
3917   "map": {"at": 164980, "to": "mm"},
3918   "name": "PA_CL_VPORT_YSCALE_2",
3919   "type_ref": "PA_CL_VPORT_YSCALE"
3920  },
3921  {
3922   "chips": ["gfx103"],
3923   "map": {"at": 164984, "to": "mm"},
3924   "name": "PA_CL_VPORT_YOFFSET_2",
3925   "type_ref": "PA_CL_VPORT_YOFFSET"
3926  },
3927  {
3928   "chips": ["gfx103"],
3929   "map": {"at": 164988, "to": "mm"},
3930   "name": "PA_CL_VPORT_ZSCALE_2",
3931   "type_ref": "PA_CL_VPORT_ZSCALE"
3932  },
3933  {
3934   "chips": ["gfx103"],
3935   "map": {"at": 164992, "to": "mm"},
3936   "name": "PA_CL_VPORT_ZOFFSET_2",
3937   "type_ref": "PA_CL_VPORT_ZOFFSET"
3938  },
3939  {
3940   "chips": ["gfx103"],
3941   "map": {"at": 164996, "to": "mm"},
3942   "name": "PA_CL_VPORT_XSCALE_3",
3943   "type_ref": "PA_CL_VPORT_XSCALE"
3944  },
3945  {
3946   "chips": ["gfx103"],
3947   "map": {"at": 165000, "to": "mm"},
3948   "name": "PA_CL_VPORT_XOFFSET_3",
3949   "type_ref": "PA_CL_VPORT_XOFFSET"
3950  },
3951  {
3952   "chips": ["gfx103"],
3953   "map": {"at": 165004, "to": "mm"},
3954   "name": "PA_CL_VPORT_YSCALE_3",
3955   "type_ref": "PA_CL_VPORT_YSCALE"
3956  },
3957  {
3958   "chips": ["gfx103"],
3959   "map": {"at": 165008, "to": "mm"},
3960   "name": "PA_CL_VPORT_YOFFSET_3",
3961   "type_ref": "PA_CL_VPORT_YOFFSET"
3962  },
3963  {
3964   "chips": ["gfx103"],
3965   "map": {"at": 165012, "to": "mm"},
3966   "name": "PA_CL_VPORT_ZSCALE_3",
3967   "type_ref": "PA_CL_VPORT_ZSCALE"
3968  },
3969  {
3970   "chips": ["gfx103"],
3971   "map": {"at": 165016, "to": "mm"},
3972   "name": "PA_CL_VPORT_ZOFFSET_3",
3973   "type_ref": "PA_CL_VPORT_ZOFFSET"
3974  },
3975  {
3976   "chips": ["gfx103"],
3977   "map": {"at": 165020, "to": "mm"},
3978   "name": "PA_CL_VPORT_XSCALE_4",
3979   "type_ref": "PA_CL_VPORT_XSCALE"
3980  },
3981  {
3982   "chips": ["gfx103"],
3983   "map": {"at": 165024, "to": "mm"},
3984   "name": "PA_CL_VPORT_XOFFSET_4",
3985   "type_ref": "PA_CL_VPORT_XOFFSET"
3986  },
3987  {
3988   "chips": ["gfx103"],
3989   "map": {"at": 165028, "to": "mm"},
3990   "name": "PA_CL_VPORT_YSCALE_4",
3991   "type_ref": "PA_CL_VPORT_YSCALE"
3992  },
3993  {
3994   "chips": ["gfx103"],
3995   "map": {"at": 165032, "to": "mm"},
3996   "name": "PA_CL_VPORT_YOFFSET_4",
3997   "type_ref": "PA_CL_VPORT_YOFFSET"
3998  },
3999  {
4000   "chips": ["gfx103"],
4001   "map": {"at": 165036, "to": "mm"},
4002   "name": "PA_CL_VPORT_ZSCALE_4",
4003   "type_ref": "PA_CL_VPORT_ZSCALE"
4004  },
4005  {
4006   "chips": ["gfx103"],
4007   "map": {"at": 165040, "to": "mm"},
4008   "name": "PA_CL_VPORT_ZOFFSET_4",
4009   "type_ref": "PA_CL_VPORT_ZOFFSET"
4010  },
4011  {
4012   "chips": ["gfx103"],
4013   "map": {"at": 165044, "to": "mm"},
4014   "name": "PA_CL_VPORT_XSCALE_5",
4015   "type_ref": "PA_CL_VPORT_XSCALE"
4016  },
4017  {
4018   "chips": ["gfx103"],
4019   "map": {"at": 165048, "to": "mm"},
4020   "name": "PA_CL_VPORT_XOFFSET_5",
4021   "type_ref": "PA_CL_VPORT_XOFFSET"
4022  },
4023  {
4024   "chips": ["gfx103"],
4025   "map": {"at": 165052, "to": "mm"},
4026   "name": "PA_CL_VPORT_YSCALE_5",
4027   "type_ref": "PA_CL_VPORT_YSCALE"
4028  },
4029  {
4030   "chips": ["gfx103"],
4031   "map": {"at": 165056, "to": "mm"},
4032   "name": "PA_CL_VPORT_YOFFSET_5",
4033   "type_ref": "PA_CL_VPORT_YOFFSET"
4034  },
4035  {
4036   "chips": ["gfx103"],
4037   "map": {"at": 165060, "to": "mm"},
4038   "name": "PA_CL_VPORT_ZSCALE_5",
4039   "type_ref": "PA_CL_VPORT_ZSCALE"
4040  },
4041  {
4042   "chips": ["gfx103"],
4043   "map": {"at": 165064, "to": "mm"},
4044   "name": "PA_CL_VPORT_ZOFFSET_5",
4045   "type_ref": "PA_CL_VPORT_ZOFFSET"
4046  },
4047  {
4048   "chips": ["gfx103"],
4049   "map": {"at": 165068, "to": "mm"},
4050   "name": "PA_CL_VPORT_XSCALE_6",
4051   "type_ref": "PA_CL_VPORT_XSCALE"
4052  },
4053  {
4054   "chips": ["gfx103"],
4055   "map": {"at": 165072, "to": "mm"},
4056   "name": "PA_CL_VPORT_XOFFSET_6",
4057   "type_ref": "PA_CL_VPORT_XOFFSET"
4058  },
4059  {
4060   "chips": ["gfx103"],
4061   "map": {"at": 165076, "to": "mm"},
4062   "name": "PA_CL_VPORT_YSCALE_6",
4063   "type_ref": "PA_CL_VPORT_YSCALE"
4064  },
4065  {
4066   "chips": ["gfx103"],
4067   "map": {"at": 165080, "to": "mm"},
4068   "name": "PA_CL_VPORT_YOFFSET_6",
4069   "type_ref": "PA_CL_VPORT_YOFFSET"
4070  },
4071  {
4072   "chips": ["gfx103"],
4073   "map": {"at": 165084, "to": "mm"},
4074   "name": "PA_CL_VPORT_ZSCALE_6",
4075   "type_ref": "PA_CL_VPORT_ZSCALE"
4076  },
4077  {
4078   "chips": ["gfx103"],
4079   "map": {"at": 165088, "to": "mm"},
4080   "name": "PA_CL_VPORT_ZOFFSET_6",
4081   "type_ref": "PA_CL_VPORT_ZOFFSET"
4082  },
4083  {
4084   "chips": ["gfx103"],
4085   "map": {"at": 165092, "to": "mm"},
4086   "name": "PA_CL_VPORT_XSCALE_7",
4087   "type_ref": "PA_CL_VPORT_XSCALE"
4088  },
4089  {
4090   "chips": ["gfx103"],
4091   "map": {"at": 165096, "to": "mm"},
4092   "name": "PA_CL_VPORT_XOFFSET_7",
4093   "type_ref": "PA_CL_VPORT_XOFFSET"
4094  },
4095  {
4096   "chips": ["gfx103"],
4097   "map": {"at": 165100, "to": "mm"},
4098   "name": "PA_CL_VPORT_YSCALE_7",
4099   "type_ref": "PA_CL_VPORT_YSCALE"
4100  },
4101  {
4102   "chips": ["gfx103"],
4103   "map": {"at": 165104, "to": "mm"},
4104   "name": "PA_CL_VPORT_YOFFSET_7",
4105   "type_ref": "PA_CL_VPORT_YOFFSET"
4106  },
4107  {
4108   "chips": ["gfx103"],
4109   "map": {"at": 165108, "to": "mm"},
4110   "name": "PA_CL_VPORT_ZSCALE_7",
4111   "type_ref": "PA_CL_VPORT_ZSCALE"
4112  },
4113  {
4114   "chips": ["gfx103"],
4115   "map": {"at": 165112, "to": "mm"},
4116   "name": "PA_CL_VPORT_ZOFFSET_7",
4117   "type_ref": "PA_CL_VPORT_ZOFFSET"
4118  },
4119  {
4120   "chips": ["gfx103"],
4121   "map": {"at": 165116, "to": "mm"},
4122   "name": "PA_CL_VPORT_XSCALE_8",
4123   "type_ref": "PA_CL_VPORT_XSCALE"
4124  },
4125  {
4126   "chips": ["gfx103"],
4127   "map": {"at": 165120, "to": "mm"},
4128   "name": "PA_CL_VPORT_XOFFSET_8",
4129   "type_ref": "PA_CL_VPORT_XOFFSET"
4130  },
4131  {
4132   "chips": ["gfx103"],
4133   "map": {"at": 165124, "to": "mm"},
4134   "name": "PA_CL_VPORT_YSCALE_8",
4135   "type_ref": "PA_CL_VPORT_YSCALE"
4136  },
4137  {
4138   "chips": ["gfx103"],
4139   "map": {"at": 165128, "to": "mm"},
4140   "name": "PA_CL_VPORT_YOFFSET_8",
4141   "type_ref": "PA_CL_VPORT_YOFFSET"
4142  },
4143  {
4144   "chips": ["gfx103"],
4145   "map": {"at": 165132, "to": "mm"},
4146   "name": "PA_CL_VPORT_ZSCALE_8",
4147   "type_ref": "PA_CL_VPORT_ZSCALE"
4148  },
4149  {
4150   "chips": ["gfx103"],
4151   "map": {"at": 165136, "to": "mm"},
4152   "name": "PA_CL_VPORT_ZOFFSET_8",
4153   "type_ref": "PA_CL_VPORT_ZOFFSET"
4154  },
4155  {
4156   "chips": ["gfx103"],
4157   "map": {"at": 165140, "to": "mm"},
4158   "name": "PA_CL_VPORT_XSCALE_9",
4159   "type_ref": "PA_CL_VPORT_XSCALE"
4160  },
4161  {
4162   "chips": ["gfx103"],
4163   "map": {"at": 165144, "to": "mm"},
4164   "name": "PA_CL_VPORT_XOFFSET_9",
4165   "type_ref": "PA_CL_VPORT_XOFFSET"
4166  },
4167  {
4168   "chips": ["gfx103"],
4169   "map": {"at": 165148, "to": "mm"},
4170   "name": "PA_CL_VPORT_YSCALE_9",
4171   "type_ref": "PA_CL_VPORT_YSCALE"
4172  },
4173  {
4174   "chips": ["gfx103"],
4175   "map": {"at": 165152, "to": "mm"},
4176   "name": "PA_CL_VPORT_YOFFSET_9",
4177   "type_ref": "PA_CL_VPORT_YOFFSET"
4178  },
4179  {
4180   "chips": ["gfx103"],
4181   "map": {"at": 165156, "to": "mm"},
4182   "name": "PA_CL_VPORT_ZSCALE_9",
4183   "type_ref": "PA_CL_VPORT_ZSCALE"
4184  },
4185  {
4186   "chips": ["gfx103"],
4187   "map": {"at": 165160, "to": "mm"},
4188   "name": "PA_CL_VPORT_ZOFFSET_9",
4189   "type_ref": "PA_CL_VPORT_ZOFFSET"
4190  },
4191  {
4192   "chips": ["gfx103"],
4193   "map": {"at": 165164, "to": "mm"},
4194   "name": "PA_CL_VPORT_XSCALE_10",
4195   "type_ref": "PA_CL_VPORT_XSCALE"
4196  },
4197  {
4198   "chips": ["gfx103"],
4199   "map": {"at": 165168, "to": "mm"},
4200   "name": "PA_CL_VPORT_XOFFSET_10",
4201   "type_ref": "PA_CL_VPORT_XOFFSET"
4202  },
4203  {
4204   "chips": ["gfx103"],
4205   "map": {"at": 165172, "to": "mm"},
4206   "name": "PA_CL_VPORT_YSCALE_10",
4207   "type_ref": "PA_CL_VPORT_YSCALE"
4208  },
4209  {
4210   "chips": ["gfx103"],
4211   "map": {"at": 165176, "to": "mm"},
4212   "name": "PA_CL_VPORT_YOFFSET_10",
4213   "type_ref": "PA_CL_VPORT_YOFFSET"
4214  },
4215  {
4216   "chips": ["gfx103"],
4217   "map": {"at": 165180, "to": "mm"},
4218   "name": "PA_CL_VPORT_ZSCALE_10",
4219   "type_ref": "PA_CL_VPORT_ZSCALE"
4220  },
4221  {
4222   "chips": ["gfx103"],
4223   "map": {"at": 165184, "to": "mm"},
4224   "name": "PA_CL_VPORT_ZOFFSET_10",
4225   "type_ref": "PA_CL_VPORT_ZOFFSET"
4226  },
4227  {
4228   "chips": ["gfx103"],
4229   "map": {"at": 165188, "to": "mm"},
4230   "name": "PA_CL_VPORT_XSCALE_11",
4231   "type_ref": "PA_CL_VPORT_XSCALE"
4232  },
4233  {
4234   "chips": ["gfx103"],
4235   "map": {"at": 165192, "to": "mm"},
4236   "name": "PA_CL_VPORT_XOFFSET_11",
4237   "type_ref": "PA_CL_VPORT_XOFFSET"
4238  },
4239  {
4240   "chips": ["gfx103"],
4241   "map": {"at": 165196, "to": "mm"},
4242   "name": "PA_CL_VPORT_YSCALE_11",
4243   "type_ref": "PA_CL_VPORT_YSCALE"
4244  },
4245  {
4246   "chips": ["gfx103"],
4247   "map": {"at": 165200, "to": "mm"},
4248   "name": "PA_CL_VPORT_YOFFSET_11",
4249   "type_ref": "PA_CL_VPORT_YOFFSET"
4250  },
4251  {
4252   "chips": ["gfx103"],
4253   "map": {"at": 165204, "to": "mm"},
4254   "name": "PA_CL_VPORT_ZSCALE_11",
4255   "type_ref": "PA_CL_VPORT_ZSCALE"
4256  },
4257  {
4258   "chips": ["gfx103"],
4259   "map": {"at": 165208, "to": "mm"},
4260   "name": "PA_CL_VPORT_ZOFFSET_11",
4261   "type_ref": "PA_CL_VPORT_ZOFFSET"
4262  },
4263  {
4264   "chips": ["gfx103"],
4265   "map": {"at": 165212, "to": "mm"},
4266   "name": "PA_CL_VPORT_XSCALE_12",
4267   "type_ref": "PA_CL_VPORT_XSCALE"
4268  },
4269  {
4270   "chips": ["gfx103"],
4271   "map": {"at": 165216, "to": "mm"},
4272   "name": "PA_CL_VPORT_XOFFSET_12",
4273   "type_ref": "PA_CL_VPORT_XOFFSET"
4274  },
4275  {
4276   "chips": ["gfx103"],
4277   "map": {"at": 165220, "to": "mm"},
4278   "name": "PA_CL_VPORT_YSCALE_12",
4279   "type_ref": "PA_CL_VPORT_YSCALE"
4280  },
4281  {
4282   "chips": ["gfx103"],
4283   "map": {"at": 165224, "to": "mm"},
4284   "name": "PA_CL_VPORT_YOFFSET_12",
4285   "type_ref": "PA_CL_VPORT_YOFFSET"
4286  },
4287  {
4288   "chips": ["gfx103"],
4289   "map": {"at": 165228, "to": "mm"},
4290   "name": "PA_CL_VPORT_ZSCALE_12",
4291   "type_ref": "PA_CL_VPORT_ZSCALE"
4292  },
4293  {
4294   "chips": ["gfx103"],
4295   "map": {"at": 165232, "to": "mm"},
4296   "name": "PA_CL_VPORT_ZOFFSET_12",
4297   "type_ref": "PA_CL_VPORT_ZOFFSET"
4298  },
4299  {
4300   "chips": ["gfx103"],
4301   "map": {"at": 165236, "to": "mm"},
4302   "name": "PA_CL_VPORT_XSCALE_13",
4303   "type_ref": "PA_CL_VPORT_XSCALE"
4304  },
4305  {
4306   "chips": ["gfx103"],
4307   "map": {"at": 165240, "to": "mm"},
4308   "name": "PA_CL_VPORT_XOFFSET_13",
4309   "type_ref": "PA_CL_VPORT_XOFFSET"
4310  },
4311  {
4312   "chips": ["gfx103"],
4313   "map": {"at": 165244, "to": "mm"},
4314   "name": "PA_CL_VPORT_YSCALE_13",
4315   "type_ref": "PA_CL_VPORT_YSCALE"
4316  },
4317  {
4318   "chips": ["gfx103"],
4319   "map": {"at": 165248, "to": "mm"},
4320   "name": "PA_CL_VPORT_YOFFSET_13",
4321   "type_ref": "PA_CL_VPORT_YOFFSET"
4322  },
4323  {
4324   "chips": ["gfx103"],
4325   "map": {"at": 165252, "to": "mm"},
4326   "name": "PA_CL_VPORT_ZSCALE_13",
4327   "type_ref": "PA_CL_VPORT_ZSCALE"
4328  },
4329  {
4330   "chips": ["gfx103"],
4331   "map": {"at": 165256, "to": "mm"},
4332   "name": "PA_CL_VPORT_ZOFFSET_13",
4333   "type_ref": "PA_CL_VPORT_ZOFFSET"
4334  },
4335  {
4336   "chips": ["gfx103"],
4337   "map": {"at": 165260, "to": "mm"},
4338   "name": "PA_CL_VPORT_XSCALE_14",
4339   "type_ref": "PA_CL_VPORT_XSCALE"
4340  },
4341  {
4342   "chips": ["gfx103"],
4343   "map": {"at": 165264, "to": "mm"},
4344   "name": "PA_CL_VPORT_XOFFSET_14",
4345   "type_ref": "PA_CL_VPORT_XOFFSET"
4346  },
4347  {
4348   "chips": ["gfx103"],
4349   "map": {"at": 165268, "to": "mm"},
4350   "name": "PA_CL_VPORT_YSCALE_14",
4351   "type_ref": "PA_CL_VPORT_YSCALE"
4352  },
4353  {
4354   "chips": ["gfx103"],
4355   "map": {"at": 165272, "to": "mm"},
4356   "name": "PA_CL_VPORT_YOFFSET_14",
4357   "type_ref": "PA_CL_VPORT_YOFFSET"
4358  },
4359  {
4360   "chips": ["gfx103"],
4361   "map": {"at": 165276, "to": "mm"},
4362   "name": "PA_CL_VPORT_ZSCALE_14",
4363   "type_ref": "PA_CL_VPORT_ZSCALE"
4364  },
4365  {
4366   "chips": ["gfx103"],
4367   "map": {"at": 165280, "to": "mm"},
4368   "name": "PA_CL_VPORT_ZOFFSET_14",
4369   "type_ref": "PA_CL_VPORT_ZOFFSET"
4370  },
4371  {
4372   "chips": ["gfx103"],
4373   "map": {"at": 165284, "to": "mm"},
4374   "name": "PA_CL_VPORT_XSCALE_15",
4375   "type_ref": "PA_CL_VPORT_XSCALE"
4376  },
4377  {
4378   "chips": ["gfx103"],
4379   "map": {"at": 165288, "to": "mm"},
4380   "name": "PA_CL_VPORT_XOFFSET_15",
4381   "type_ref": "PA_CL_VPORT_XOFFSET"
4382  },
4383  {
4384   "chips": ["gfx103"],
4385   "map": {"at": 165292, "to": "mm"},
4386   "name": "PA_CL_VPORT_YSCALE_15",
4387   "type_ref": "PA_CL_VPORT_YSCALE"
4388  },
4389  {
4390   "chips": ["gfx103"],
4391   "map": {"at": 165296, "to": "mm"},
4392   "name": "PA_CL_VPORT_YOFFSET_15",
4393   "type_ref": "PA_CL_VPORT_YOFFSET"
4394  },
4395  {
4396   "chips": ["gfx103"],
4397   "map": {"at": 165300, "to": "mm"},
4398   "name": "PA_CL_VPORT_ZSCALE_15",
4399   "type_ref": "PA_CL_VPORT_ZSCALE"
4400  },
4401  {
4402   "chips": ["gfx103"],
4403   "map": {"at": 165304, "to": "mm"},
4404   "name": "PA_CL_VPORT_ZOFFSET_15",
4405   "type_ref": "PA_CL_VPORT_ZOFFSET"
4406  },
4407  {
4408   "chips": ["gfx103"],
4409   "map": {"at": 165308, "to": "mm"},
4410   "name": "PA_CL_UCP_0_X",
4411   "type_ref": "PA_CL_UCP_0_X"
4412  },
4413  {
4414   "chips": ["gfx103"],
4415   "map": {"at": 165312, "to": "mm"},
4416   "name": "PA_CL_UCP_0_Y",
4417   "type_ref": "PA_CL_UCP_0_X"
4418  },
4419  {
4420   "chips": ["gfx103"],
4421   "map": {"at": 165316, "to": "mm"},
4422   "name": "PA_CL_UCP_0_Z",
4423   "type_ref": "PA_CL_UCP_0_X"
4424  },
4425  {
4426   "chips": ["gfx103"],
4427   "map": {"at": 165320, "to": "mm"},
4428   "name": "PA_CL_UCP_0_W",
4429   "type_ref": "PA_CL_UCP_0_X"
4430  },
4431  {
4432   "chips": ["gfx103"],
4433   "map": {"at": 165324, "to": "mm"},
4434   "name": "PA_CL_UCP_1_X",
4435   "type_ref": "PA_CL_UCP_0_X"
4436  },
4437  {
4438   "chips": ["gfx103"],
4439   "map": {"at": 165328, "to": "mm"},
4440   "name": "PA_CL_UCP_1_Y",
4441   "type_ref": "PA_CL_UCP_0_X"
4442  },
4443  {
4444   "chips": ["gfx103"],
4445   "map": {"at": 165332, "to": "mm"},
4446   "name": "PA_CL_UCP_1_Z",
4447   "type_ref": "PA_CL_UCP_0_X"
4448  },
4449  {
4450   "chips": ["gfx103"],
4451   "map": {"at": 165336, "to": "mm"},
4452   "name": "PA_CL_UCP_1_W",
4453   "type_ref": "PA_CL_UCP_0_X"
4454  },
4455  {
4456   "chips": ["gfx103"],
4457   "map": {"at": 165340, "to": "mm"},
4458   "name": "PA_CL_UCP_2_X",
4459   "type_ref": "PA_CL_UCP_0_X"
4460  },
4461  {
4462   "chips": ["gfx103"],
4463   "map": {"at": 165344, "to": "mm"},
4464   "name": "PA_CL_UCP_2_Y",
4465   "type_ref": "PA_CL_UCP_0_X"
4466  },
4467  {
4468   "chips": ["gfx103"],
4469   "map": {"at": 165348, "to": "mm"},
4470   "name": "PA_CL_UCP_2_Z",
4471   "type_ref": "PA_CL_UCP_0_X"
4472  },
4473  {
4474   "chips": ["gfx103"],
4475   "map": {"at": 165352, "to": "mm"},
4476   "name": "PA_CL_UCP_2_W",
4477   "type_ref": "PA_CL_UCP_0_X"
4478  },
4479  {
4480   "chips": ["gfx103"],
4481   "map": {"at": 165356, "to": "mm"},
4482   "name": "PA_CL_UCP_3_X",
4483   "type_ref": "PA_CL_UCP_0_X"
4484  },
4485  {
4486   "chips": ["gfx103"],
4487   "map": {"at": 165360, "to": "mm"},
4488   "name": "PA_CL_UCP_3_Y",
4489   "type_ref": "PA_CL_UCP_0_X"
4490  },
4491  {
4492   "chips": ["gfx103"],
4493   "map": {"at": 165364, "to": "mm"},
4494   "name": "PA_CL_UCP_3_Z",
4495   "type_ref": "PA_CL_UCP_0_X"
4496  },
4497  {
4498   "chips": ["gfx103"],
4499   "map": {"at": 165368, "to": "mm"},
4500   "name": "PA_CL_UCP_3_W",
4501   "type_ref": "PA_CL_UCP_0_X"
4502  },
4503  {
4504   "chips": ["gfx103"],
4505   "map": {"at": 165372, "to": "mm"},
4506   "name": "PA_CL_UCP_4_X",
4507   "type_ref": "PA_CL_UCP_0_X"
4508  },
4509  {
4510   "chips": ["gfx103"],
4511   "map": {"at": 165376, "to": "mm"},
4512   "name": "PA_CL_UCP_4_Y",
4513   "type_ref": "PA_CL_UCP_0_X"
4514  },
4515  {
4516   "chips": ["gfx103"],
4517   "map": {"at": 165380, "to": "mm"},
4518   "name": "PA_CL_UCP_4_Z",
4519   "type_ref": "PA_CL_UCP_0_X"
4520  },
4521  {
4522   "chips": ["gfx103"],
4523   "map": {"at": 165384, "to": "mm"},
4524   "name": "PA_CL_UCP_4_W",
4525   "type_ref": "PA_CL_UCP_0_X"
4526  },
4527  {
4528   "chips": ["gfx103"],
4529   "map": {"at": 165388, "to": "mm"},
4530   "name": "PA_CL_UCP_5_X",
4531   "type_ref": "PA_CL_UCP_0_X"
4532  },
4533  {
4534   "chips": ["gfx103"],
4535   "map": {"at": 165392, "to": "mm"},
4536   "name": "PA_CL_UCP_5_Y",
4537   "type_ref": "PA_CL_UCP_0_X"
4538  },
4539  {
4540   "chips": ["gfx103"],
4541   "map": {"at": 165396, "to": "mm"},
4542   "name": "PA_CL_UCP_5_Z",
4543   "type_ref": "PA_CL_UCP_0_X"
4544  },
4545  {
4546   "chips": ["gfx103"],
4547   "map": {"at": 165400, "to": "mm"},
4548   "name": "PA_CL_UCP_5_W",
4549   "type_ref": "PA_CL_UCP_0_X"
4550  },
4551  {
4552   "chips": ["gfx103"],
4553   "map": {"at": 165404, "to": "mm"},
4554   "name": "PA_CL_PROG_NEAR_CLIP_Z",
4555   "type_ref": "PA_CL_UCP_0_X"
4556  },
4557  {
4558   "chips": ["gfx103"],
4559   "map": {"at": 165444, "to": "mm"},
4560   "name": "SPI_PS_INPUT_CNTL_0",
4561   "type_ref": "SPI_PS_INPUT_CNTL_0"
4562  },
4563  {
4564   "chips": ["gfx103"],
4565   "map": {"at": 165448, "to": "mm"},
4566   "name": "SPI_PS_INPUT_CNTL_1",
4567   "type_ref": "SPI_PS_INPUT_CNTL_0"
4568  },
4569  {
4570   "chips": ["gfx103"],
4571   "map": {"at": 165452, "to": "mm"},
4572   "name": "SPI_PS_INPUT_CNTL_2",
4573   "type_ref": "SPI_PS_INPUT_CNTL_0"
4574  },
4575  {
4576   "chips": ["gfx103"],
4577   "map": {"at": 165456, "to": "mm"},
4578   "name": "SPI_PS_INPUT_CNTL_3",
4579   "type_ref": "SPI_PS_INPUT_CNTL_0"
4580  },
4581  {
4582   "chips": ["gfx103"],
4583   "map": {"at": 165460, "to": "mm"},
4584   "name": "SPI_PS_INPUT_CNTL_4",
4585   "type_ref": "SPI_PS_INPUT_CNTL_0"
4586  },
4587  {
4588   "chips": ["gfx103"],
4589   "map": {"at": 165464, "to": "mm"},
4590   "name": "SPI_PS_INPUT_CNTL_5",
4591   "type_ref": "SPI_PS_INPUT_CNTL_0"
4592  },
4593  {
4594   "chips": ["gfx103"],
4595   "map": {"at": 165468, "to": "mm"},
4596   "name": "SPI_PS_INPUT_CNTL_6",
4597   "type_ref": "SPI_PS_INPUT_CNTL_0"
4598  },
4599  {
4600   "chips": ["gfx103"],
4601   "map": {"at": 165472, "to": "mm"},
4602   "name": "SPI_PS_INPUT_CNTL_7",
4603   "type_ref": "SPI_PS_INPUT_CNTL_0"
4604  },
4605  {
4606   "chips": ["gfx103"],
4607   "map": {"at": 165476, "to": "mm"},
4608   "name": "SPI_PS_INPUT_CNTL_8",
4609   "type_ref": "SPI_PS_INPUT_CNTL_0"
4610  },
4611  {
4612   "chips": ["gfx103"],
4613   "map": {"at": 165480, "to": "mm"},
4614   "name": "SPI_PS_INPUT_CNTL_9",
4615   "type_ref": "SPI_PS_INPUT_CNTL_0"
4616  },
4617  {
4618   "chips": ["gfx103"],
4619   "map": {"at": 165484, "to": "mm"},
4620   "name": "SPI_PS_INPUT_CNTL_10",
4621   "type_ref": "SPI_PS_INPUT_CNTL_0"
4622  },
4623  {
4624   "chips": ["gfx103"],
4625   "map": {"at": 165488, "to": "mm"},
4626   "name": "SPI_PS_INPUT_CNTL_11",
4627   "type_ref": "SPI_PS_INPUT_CNTL_0"
4628  },
4629  {
4630   "chips": ["gfx103"],
4631   "map": {"at": 165492, "to": "mm"},
4632   "name": "SPI_PS_INPUT_CNTL_12",
4633   "type_ref": "SPI_PS_INPUT_CNTL_0"
4634  },
4635  {
4636   "chips": ["gfx103"],
4637   "map": {"at": 165496, "to": "mm"},
4638   "name": "SPI_PS_INPUT_CNTL_13",
4639   "type_ref": "SPI_PS_INPUT_CNTL_0"
4640  },
4641  {
4642   "chips": ["gfx103"],
4643   "map": {"at": 165500, "to": "mm"},
4644   "name": "SPI_PS_INPUT_CNTL_14",
4645   "type_ref": "SPI_PS_INPUT_CNTL_0"
4646  },
4647  {
4648   "chips": ["gfx103"],
4649   "map": {"at": 165504, "to": "mm"},
4650   "name": "SPI_PS_INPUT_CNTL_15",
4651   "type_ref": "SPI_PS_INPUT_CNTL_0"
4652  },
4653  {
4654   "chips": ["gfx103"],
4655   "map": {"at": 165508, "to": "mm"},
4656   "name": "SPI_PS_INPUT_CNTL_16",
4657   "type_ref": "SPI_PS_INPUT_CNTL_0"
4658  },
4659  {
4660   "chips": ["gfx103"],
4661   "map": {"at": 165512, "to": "mm"},
4662   "name": "SPI_PS_INPUT_CNTL_17",
4663   "type_ref": "SPI_PS_INPUT_CNTL_0"
4664  },
4665  {
4666   "chips": ["gfx103"],
4667   "map": {"at": 165516, "to": "mm"},
4668   "name": "SPI_PS_INPUT_CNTL_18",
4669   "type_ref": "SPI_PS_INPUT_CNTL_0"
4670  },
4671  {
4672   "chips": ["gfx103"],
4673   "map": {"at": 165520, "to": "mm"},
4674   "name": "SPI_PS_INPUT_CNTL_19",
4675   "type_ref": "SPI_PS_INPUT_CNTL_0"
4676  },
4677  {
4678   "chips": ["gfx103"],
4679   "map": {"at": 165524, "to": "mm"},
4680   "name": "SPI_PS_INPUT_CNTL_20",
4681   "type_ref": "SPI_PS_INPUT_CNTL_20"
4682  },
4683  {
4684   "chips": ["gfx103"],
4685   "map": {"at": 165528, "to": "mm"},
4686   "name": "SPI_PS_INPUT_CNTL_21",
4687   "type_ref": "SPI_PS_INPUT_CNTL_20"
4688  },
4689  {
4690   "chips": ["gfx103"],
4691   "map": {"at": 165532, "to": "mm"},
4692   "name": "SPI_PS_INPUT_CNTL_22",
4693   "type_ref": "SPI_PS_INPUT_CNTL_20"
4694  },
4695  {
4696   "chips": ["gfx103"],
4697   "map": {"at": 165536, "to": "mm"},
4698   "name": "SPI_PS_INPUT_CNTL_23",
4699   "type_ref": "SPI_PS_INPUT_CNTL_20"
4700  },
4701  {
4702   "chips": ["gfx103"],
4703   "map": {"at": 165540, "to": "mm"},
4704   "name": "SPI_PS_INPUT_CNTL_24",
4705   "type_ref": "SPI_PS_INPUT_CNTL_20"
4706  },
4707  {
4708   "chips": ["gfx103"],
4709   "map": {"at": 165544, "to": "mm"},
4710   "name": "SPI_PS_INPUT_CNTL_25",
4711   "type_ref": "SPI_PS_INPUT_CNTL_20"
4712  },
4713  {
4714   "chips": ["gfx103"],
4715   "map": {"at": 165548, "to": "mm"},
4716   "name": "SPI_PS_INPUT_CNTL_26",
4717   "type_ref": "SPI_PS_INPUT_CNTL_20"
4718  },
4719  {
4720   "chips": ["gfx103"],
4721   "map": {"at": 165552, "to": "mm"},
4722   "name": "SPI_PS_INPUT_CNTL_27",
4723   "type_ref": "SPI_PS_INPUT_CNTL_20"
4724  },
4725  {
4726   "chips": ["gfx103"],
4727   "map": {"at": 165556, "to": "mm"},
4728   "name": "SPI_PS_INPUT_CNTL_28",
4729   "type_ref": "SPI_PS_INPUT_CNTL_20"
4730  },
4731  {
4732   "chips": ["gfx103"],
4733   "map": {"at": 165560, "to": "mm"},
4734   "name": "SPI_PS_INPUT_CNTL_29",
4735   "type_ref": "SPI_PS_INPUT_CNTL_20"
4736  },
4737  {
4738   "chips": ["gfx103"],
4739   "map": {"at": 165564, "to": "mm"},
4740   "name": "SPI_PS_INPUT_CNTL_30",
4741   "type_ref": "SPI_PS_INPUT_CNTL_20"
4742  },
4743  {
4744   "chips": ["gfx103"],
4745   "map": {"at": 165568, "to": "mm"},
4746   "name": "SPI_PS_INPUT_CNTL_31",
4747   "type_ref": "SPI_PS_INPUT_CNTL_20"
4748  },
4749  {
4750   "chips": ["gfx103"],
4751   "map": {"at": 165572, "to": "mm"},
4752   "name": "SPI_VS_OUT_CONFIG",
4753   "type_ref": "SPI_VS_OUT_CONFIG"
4754  },
4755  {
4756   "chips": ["gfx103"],
4757   "map": {"at": 165580, "to": "mm"},
4758   "name": "SPI_PS_INPUT_ENA",
4759   "type_ref": "SPI_PS_INPUT_ENA"
4760  },
4761  {
4762   "chips": ["gfx103"],
4763   "map": {"at": 165584, "to": "mm"},
4764   "name": "SPI_PS_INPUT_ADDR",
4765   "type_ref": "SPI_PS_INPUT_ENA"
4766  },
4767  {
4768   "chips": ["gfx103"],
4769   "map": {"at": 165588, "to": "mm"},
4770   "name": "SPI_INTERP_CONTROL_0",
4771   "type_ref": "SPI_INTERP_CONTROL_0"
4772  },
4773  {
4774   "chips": ["gfx103"],
4775   "map": {"at": 165592, "to": "mm"},
4776   "name": "SPI_PS_IN_CONTROL",
4777   "type_ref": "SPI_PS_IN_CONTROL"
4778  },
4779  {
4780   "chips": ["gfx103"],
4781   "map": {"at": 165600, "to": "mm"},
4782   "name": "SPI_BARYC_CNTL",
4783   "type_ref": "SPI_BARYC_CNTL"
4784  },
4785  {
4786   "chips": ["gfx103"],
4787   "map": {"at": 165608, "to": "mm"},
4788   "name": "SPI_TMPRING_SIZE",
4789   "type_ref": "COMPUTE_TMPRING_SIZE"
4790  },
4791  {
4792   "chips": ["gfx103"],
4793   "map": {"at": 165640, "to": "mm"},
4794   "name": "SPI_SHADER_IDX_FORMAT",
4795   "type_ref": "SPI_SHADER_IDX_FORMAT"
4796  },
4797  {
4798   "chips": ["gfx103"],
4799   "map": {"at": 165644, "to": "mm"},
4800   "name": "SPI_SHADER_POS_FORMAT",
4801   "type_ref": "SPI_SHADER_POS_FORMAT"
4802  },
4803  {
4804   "chips": ["gfx103"],
4805   "map": {"at": 165648, "to": "mm"},
4806   "name": "SPI_SHADER_Z_FORMAT",
4807   "type_ref": "SPI_SHADER_Z_FORMAT"
4808  },
4809  {
4810   "chips": ["gfx103"],
4811   "map": {"at": 165652, "to": "mm"},
4812   "name": "SPI_SHADER_COL_FORMAT",
4813   "type_ref": "SPI_SHADER_COL_FORMAT"
4814  },
4815  {
4816   "chips": ["gfx103"],
4817   "map": {"at": 165712, "to": "mm"},
4818   "name": "SX_PS_DOWNCONVERT_CONTROL",
4819   "type_ref": "SX_PS_DOWNCONVERT_CONTROL"
4820  },
4821  {
4822   "chips": ["gfx103"],
4823   "map": {"at": 165716, "to": "mm"},
4824   "name": "SX_PS_DOWNCONVERT",
4825   "type_ref": "SX_PS_DOWNCONVERT"
4826  },
4827  {
4828   "chips": ["gfx103"],
4829   "map": {"at": 165720, "to": "mm"},
4830   "name": "SX_BLEND_OPT_EPSILON",
4831   "type_ref": "SX_BLEND_OPT_EPSILON"
4832  },
4833  {
4834   "chips": ["gfx103"],
4835   "map": {"at": 165724, "to": "mm"},
4836   "name": "SX_BLEND_OPT_CONTROL",
4837   "type_ref": "SX_BLEND_OPT_CONTROL"
4838  },
4839  {
4840   "chips": ["gfx103"],
4841   "map": {"at": 165728, "to": "mm"},
4842   "name": "SX_MRT0_BLEND_OPT",
4843   "type_ref": "SX_MRT0_BLEND_OPT"
4844  },
4845  {
4846   "chips": ["gfx103"],
4847   "map": {"at": 165732, "to": "mm"},
4848   "name": "SX_MRT1_BLEND_OPT",
4849   "type_ref": "SX_MRT0_BLEND_OPT"
4850  },
4851  {
4852   "chips": ["gfx103"],
4853   "map": {"at": 165736, "to": "mm"},
4854   "name": "SX_MRT2_BLEND_OPT",
4855   "type_ref": "SX_MRT0_BLEND_OPT"
4856  },
4857  {
4858   "chips": ["gfx103"],
4859   "map": {"at": 165740, "to": "mm"},
4860   "name": "SX_MRT3_BLEND_OPT",
4861   "type_ref": "SX_MRT0_BLEND_OPT"
4862  },
4863  {
4864   "chips": ["gfx103"],
4865   "map": {"at": 165744, "to": "mm"},
4866   "name": "SX_MRT4_BLEND_OPT",
4867   "type_ref": "SX_MRT0_BLEND_OPT"
4868  },
4869  {
4870   "chips": ["gfx103"],
4871   "map": {"at": 165748, "to": "mm"},
4872   "name": "SX_MRT5_BLEND_OPT",
4873   "type_ref": "SX_MRT0_BLEND_OPT"
4874  },
4875  {
4876   "chips": ["gfx103"],
4877   "map": {"at": 165752, "to": "mm"},
4878   "name": "SX_MRT6_BLEND_OPT",
4879   "type_ref": "SX_MRT0_BLEND_OPT"
4880  },
4881  {
4882   "chips": ["gfx103"],
4883   "map": {"at": 165756, "to": "mm"},
4884   "name": "SX_MRT7_BLEND_OPT",
4885   "type_ref": "SX_MRT0_BLEND_OPT"
4886  },
4887  {
4888   "chips": ["gfx103"],
4889   "map": {"at": 165760, "to": "mm"},
4890   "name": "CB_BLEND0_CONTROL",
4891   "type_ref": "CB_BLEND0_CONTROL"
4892  },
4893  {
4894   "chips": ["gfx103"],
4895   "map": {"at": 165764, "to": "mm"},
4896   "name": "CB_BLEND1_CONTROL",
4897   "type_ref": "CB_BLEND0_CONTROL"
4898  },
4899  {
4900   "chips": ["gfx103"],
4901   "map": {"at": 165768, "to": "mm"},
4902   "name": "CB_BLEND2_CONTROL",
4903   "type_ref": "CB_BLEND0_CONTROL"
4904  },
4905  {
4906   "chips": ["gfx103"],
4907   "map": {"at": 165772, "to": "mm"},
4908   "name": "CB_BLEND3_CONTROL",
4909   "type_ref": "CB_BLEND0_CONTROL"
4910  },
4911  {
4912   "chips": ["gfx103"],
4913   "map": {"at": 165776, "to": "mm"},
4914   "name": "CB_BLEND4_CONTROL",
4915   "type_ref": "CB_BLEND0_CONTROL"
4916  },
4917  {
4918   "chips": ["gfx103"],
4919   "map": {"at": 165780, "to": "mm"},
4920   "name": "CB_BLEND5_CONTROL",
4921   "type_ref": "CB_BLEND0_CONTROL"
4922  },
4923  {
4924   "chips": ["gfx103"],
4925   "map": {"at": 165784, "to": "mm"},
4926   "name": "CB_BLEND6_CONTROL",
4927   "type_ref": "CB_BLEND0_CONTROL"
4928  },
4929  {
4930   "chips": ["gfx103"],
4931   "map": {"at": 165788, "to": "mm"},
4932   "name": "CB_BLEND7_CONTROL",
4933   "type_ref": "CB_BLEND0_CONTROL"
4934  },
4935  {
4936   "chips": ["gfx103"],
4937   "map": {"at": 165836, "to": "mm"},
4938   "name": "CS_COPY_STATE",
4939   "type_ref": "CS_COPY_STATE"
4940  },
4941  {
4942   "chips": ["gfx103"],
4943   "map": {"at": 165840, "to": "mm"},
4944   "name": "GFX_COPY_STATE",
4945   "type_ref": "CS_COPY_STATE"
4946  },
4947  {
4948   "chips": ["gfx103"],
4949   "map": {"at": 165844, "to": "mm"},
4950   "name": "PA_CL_POINT_X_RAD",
4951   "type_ref": "PA_CL_UCP_0_X"
4952  },
4953  {
4954   "chips": ["gfx103"],
4955   "map": {"at": 165848, "to": "mm"},
4956   "name": "PA_CL_POINT_Y_RAD",
4957   "type_ref": "PA_CL_UCP_0_X"
4958  },
4959  {
4960   "chips": ["gfx103"],
4961   "map": {"at": 165852, "to": "mm"},
4962   "name": "PA_CL_POINT_SIZE",
4963   "type_ref": "PA_CL_UCP_0_X"
4964  },
4965  {
4966   "chips": ["gfx103"],
4967   "map": {"at": 165856, "to": "mm"},
4968   "name": "PA_CL_POINT_CULL_RAD",
4969   "type_ref": "PA_CL_UCP_0_X"
4970  },
4971  {
4972   "chips": ["gfx103"],
4973   "map": {"at": 165860, "to": "mm"},
4974   "name": "VGT_DMA_BASE_HI",
4975   "type_ref": "VGT_DMA_BASE_HI"
4976  },
4977  {
4978   "chips": ["gfx103"],
4979   "map": {"at": 165864, "to": "mm"},
4980   "name": "VGT_DMA_BASE",
4981   "type_ref": "VGT_DMA_BASE"
4982  },
4983  {
4984   "chips": ["gfx103"],
4985   "map": {"at": 165872, "to": "mm"},
4986   "name": "VGT_DRAW_INITIATOR",
4987   "type_ref": "VGT_DRAW_INITIATOR"
4988  },
4989  {
4990   "chips": ["gfx103"],
4991   "map": {"at": 165876, "to": "mm"},
4992   "name": "VGT_IMMED_DATA",
4993   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
4994  },
4995  {
4996   "chips": ["gfx103"],
4997   "map": {"at": 165880, "to": "mm"},
4998   "name": "VGT_EVENT_ADDRESS_REG",
4999   "type_ref": "VGT_EVENT_ADDRESS_REG"
5000  },
5001  {
5002   "chips": ["gfx103"],
5003   "map": {"at": 165884, "to": "mm"},
5004   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
5005   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
5006  },
5007  {
5008   "chips": ["gfx103"],
5009   "map": {"at": 165888, "to": "mm"},
5010   "name": "DB_DEPTH_CONTROL",
5011   "type_ref": "DB_DEPTH_CONTROL"
5012  },
5013  {
5014   "chips": ["gfx103"],
5015   "map": {"at": 165892, "to": "mm"},
5016   "name": "DB_EQAA",
5017   "type_ref": "DB_EQAA"
5018  },
5019  {
5020   "chips": ["gfx103"],
5021   "map": {"at": 165896, "to": "mm"},
5022   "name": "CB_COLOR_CONTROL",
5023   "type_ref": "CB_COLOR_CONTROL"
5024  },
5025  {
5026   "chips": ["gfx103"],
5027   "map": {"at": 165900, "to": "mm"},
5028   "name": "DB_SHADER_CONTROL",
5029   "type_ref": "DB_SHADER_CONTROL"
5030  },
5031  {
5032   "chips": ["gfx103"],
5033   "map": {"at": 165904, "to": "mm"},
5034   "name": "PA_CL_CLIP_CNTL",
5035   "type_ref": "PA_CL_CLIP_CNTL"
5036  },
5037  {
5038   "chips": ["gfx103"],
5039   "map": {"at": 165908, "to": "mm"},
5040   "name": "PA_SU_SC_MODE_CNTL",
5041   "type_ref": "PA_SU_SC_MODE_CNTL"
5042  },
5043  {
5044   "chips": ["gfx103"],
5045   "map": {"at": 165912, "to": "mm"},
5046   "name": "PA_CL_VTE_CNTL",
5047   "type_ref": "PA_CL_VTE_CNTL"
5048  },
5049  {
5050   "chips": ["gfx103"],
5051   "map": {"at": 165916, "to": "mm"},
5052   "name": "PA_CL_VS_OUT_CNTL",
5053   "type_ref": "PA_CL_VS_OUT_CNTL"
5054  },
5055  {
5056   "chips": ["gfx103"],
5057   "map": {"at": 165920, "to": "mm"},
5058   "name": "PA_CL_NANINF_CNTL",
5059   "type_ref": "PA_CL_NANINF_CNTL"
5060  },
5061  {
5062   "chips": ["gfx103"],
5063   "map": {"at": 165924, "to": "mm"},
5064   "name": "PA_SU_LINE_STIPPLE_CNTL",
5065   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5066  },
5067  {
5068   "chips": ["gfx103"],
5069   "map": {"at": 165928, "to": "mm"},
5070   "name": "PA_SU_LINE_STIPPLE_SCALE",
5071   "type_ref": "PA_SU_LINE_STIPPLE_SCALE"
5072  },
5073  {
5074   "chips": ["gfx103"],
5075   "map": {"at": 165932, "to": "mm"},
5076   "name": "PA_SU_PRIM_FILTER_CNTL",
5077   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5078  },
5079  {
5080   "chips": ["gfx103"],
5081   "map": {"at": 165936, "to": "mm"},
5082   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
5083   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
5084  },
5085  {
5086   "chips": ["gfx103"],
5087   "map": {"at": 165944, "to": "mm"},
5088   "name": "PA_CL_NGG_CNTL",
5089   "type_ref": "PA_CL_NGG_CNTL"
5090  },
5091  {
5092   "chips": ["gfx103"],
5093   "map": {"at": 165948, "to": "mm"},
5094   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
5095   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
5096  },
5097  {
5098   "chips": ["gfx103"],
5099   "map": {"at": 165952, "to": "mm"},
5100   "name": "PA_STEREO_CNTL",
5101   "type_ref": "PA_STEREO_CNTL"
5102  },
5103  {
5104   "chips": ["gfx103"],
5105   "map": {"at": 165956, "to": "mm"},
5106   "name": "PA_STATE_STEREO_X",
5107   "type_ref": "PA_STATE_STEREO_X"
5108  },
5109  {
5110   "chips": ["gfx103"],
5111   "map": {"at": 165960, "to": "mm"},
5112   "name": "PA_CL_VRS_CNTL",
5113   "type_ref": "PA_CL_VRS_CNTL"
5114  },
5115  {
5116   "chips": ["gfx103"],
5117   "map": {"at": 166400, "to": "mm"},
5118   "name": "PA_SU_POINT_SIZE",
5119   "type_ref": "PA_SU_POINT_SIZE"
5120  },
5121  {
5122   "chips": ["gfx103"],
5123   "map": {"at": 166404, "to": "mm"},
5124   "name": "PA_SU_POINT_MINMAX",
5125   "type_ref": "PA_SU_POINT_MINMAX"
5126  },
5127  {
5128   "chips": ["gfx103"],
5129   "map": {"at": 166408, "to": "mm"},
5130   "name": "PA_SU_LINE_CNTL",
5131   "type_ref": "PA_SU_LINE_CNTL"
5132  },
5133  {
5134   "chips": ["gfx103"],
5135   "map": {"at": 166412, "to": "mm"},
5136   "name": "PA_SC_LINE_STIPPLE",
5137   "type_ref": "PA_SC_LINE_STIPPLE"
5138  },
5139  {
5140   "chips": ["gfx103"],
5141   "map": {"at": 166416, "to": "mm"},
5142   "name": "VGT_OUTPUT_PATH_CNTL",
5143   "type_ref": "VGT_OUTPUT_PATH_CNTL"
5144  },
5145  {
5146   "chips": ["gfx103"],
5147   "map": {"at": 166420, "to": "mm"},
5148   "name": "VGT_HOS_CNTL",
5149   "type_ref": "VGT_HOS_CNTL"
5150  },
5151  {
5152   "chips": ["gfx103"],
5153   "map": {"at": 166424, "to": "mm"},
5154   "name": "VGT_HOS_MAX_TESS_LEVEL",
5155   "type_ref": "VGT_HOS_MAX_TESS_LEVEL"
5156  },
5157  {
5158   "chips": ["gfx103"],
5159   "map": {"at": 166428, "to": "mm"},
5160   "name": "VGT_HOS_MIN_TESS_LEVEL",
5161   "type_ref": "VGT_HOS_MIN_TESS_LEVEL"
5162  },
5163  {
5164   "chips": ["gfx103"],
5165   "map": {"at": 166432, "to": "mm"},
5166   "name": "VGT_HOS_REUSE_DEPTH",
5167   "type_ref": "VGT_HOS_REUSE_DEPTH"
5168  },
5169  {
5170   "chips": ["gfx103"],
5171   "map": {"at": 166436, "to": "mm"},
5172   "name": "VGT_GROUP_PRIM_TYPE",
5173   "type_ref": "VGT_GROUP_PRIM_TYPE"
5174  },
5175  {
5176   "chips": ["gfx103"],
5177   "map": {"at": 166440, "to": "mm"},
5178   "name": "VGT_GROUP_FIRST_DECR",
5179   "type_ref": "VGT_GROUP_FIRST_DECR"
5180  },
5181  {
5182   "chips": ["gfx103"],
5183   "map": {"at": 166444, "to": "mm"},
5184   "name": "VGT_GROUP_DECR",
5185   "type_ref": "VGT_GROUP_DECR"
5186  },
5187  {
5188   "chips": ["gfx103"],
5189   "map": {"at": 166448, "to": "mm"},
5190   "name": "VGT_GROUP_VECT_0_CNTL",
5191   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5192  },
5193  {
5194   "chips": ["gfx103"],
5195   "map": {"at": 166452, "to": "mm"},
5196   "name": "VGT_GROUP_VECT_1_CNTL",
5197   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5198  },
5199  {
5200   "chips": ["gfx103"],
5201   "map": {"at": 166456, "to": "mm"},
5202   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5203   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5204  },
5205  {
5206   "chips": ["gfx103"],
5207   "map": {"at": 166460, "to": "mm"},
5208   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5209   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5210  },
5211  {
5212   "chips": ["gfx103"],
5213   "map": {"at": 166464, "to": "mm"},
5214   "name": "VGT_GS_MODE",
5215   "type_ref": "VGT_GS_MODE"
5216  },
5217  {
5218   "chips": ["gfx103"],
5219   "map": {"at": 166468, "to": "mm"},
5220   "name": "VGT_GS_ONCHIP_CNTL",
5221   "type_ref": "VGT_GS_ONCHIP_CNTL"
5222  },
5223  {
5224   "chips": ["gfx103"],
5225   "map": {"at": 166472, "to": "mm"},
5226   "name": "PA_SC_MODE_CNTL_0",
5227   "type_ref": "PA_SC_MODE_CNTL_0"
5228  },
5229  {
5230   "chips": ["gfx103"],
5231   "map": {"at": 166476, "to": "mm"},
5232   "name": "PA_SC_MODE_CNTL_1",
5233   "type_ref": "PA_SC_MODE_CNTL_1"
5234  },
5235  {
5236   "chips": ["gfx103"],
5237   "map": {"at": 166480, "to": "mm"},
5238   "name": "VGT_ENHANCE",
5239   "type_ref": "VGT_ENHANCE"
5240  },
5241  {
5242   "chips": ["gfx103"],
5243   "map": {"at": 166484, "to": "mm"},
5244   "name": "VGT_GS_PER_ES",
5245   "type_ref": "VGT_GS_PER_ES"
5246  },
5247  {
5248   "chips": ["gfx103"],
5249   "map": {"at": 166488, "to": "mm"},
5250   "name": "VGT_ES_PER_GS",
5251   "type_ref": "VGT_ES_PER_GS"
5252  },
5253  {
5254   "chips": ["gfx103"],
5255   "map": {"at": 166492, "to": "mm"},
5256   "name": "VGT_GS_PER_VS",
5257   "type_ref": "VGT_GS_PER_VS"
5258  },
5259  {
5260   "chips": ["gfx103"],
5261   "map": {"at": 166496, "to": "mm"},
5262   "name": "VGT_GSVS_RING_OFFSET_1",
5263   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5264  },
5265  {
5266   "chips": ["gfx103"],
5267   "map": {"at": 166500, "to": "mm"},
5268   "name": "VGT_GSVS_RING_OFFSET_2",
5269   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5270  },
5271  {
5272   "chips": ["gfx103"],
5273   "map": {"at": 166504, "to": "mm"},
5274   "name": "VGT_GSVS_RING_OFFSET_3",
5275   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5276  },
5277  {
5278   "chips": ["gfx103"],
5279   "map": {"at": 166508, "to": "mm"},
5280   "name": "VGT_GS_OUT_PRIM_TYPE",
5281   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5282  },
5283  {
5284   "chips": ["gfx103"],
5285   "map": {"at": 166512, "to": "mm"},
5286   "name": "IA_ENHANCE",
5287   "type_ref": "VGT_ENHANCE"
5288  },
5289  {
5290   "chips": ["gfx103"],
5291   "map": {"at": 166516, "to": "mm"},
5292   "name": "VGT_DMA_SIZE",
5293   "type_ref": "VGT_DMA_SIZE"
5294  },
5295  {
5296   "chips": ["gfx103"],
5297   "map": {"at": 166520, "to": "mm"},
5298   "name": "VGT_DMA_MAX_SIZE",
5299   "type_ref": "VGT_DMA_MAX_SIZE"
5300  },
5301  {
5302   "chips": ["gfx103"],
5303   "map": {"at": 166524, "to": "mm"},
5304   "name": "VGT_DMA_INDEX_TYPE",
5305   "type_ref": "VGT_DMA_INDEX_TYPE"
5306  },
5307  {
5308   "chips": ["gfx103"],
5309   "map": {"at": 166528, "to": "mm"},
5310   "name": "WD_ENHANCE",
5311   "type_ref": "VGT_ENHANCE"
5312  },
5313  {
5314   "chips": ["gfx103"],
5315   "map": {"at": 166532, "to": "mm"},
5316   "name": "VGT_PRIMITIVEID_EN",
5317   "type_ref": "VGT_PRIMITIVEID_EN"
5318  },
5319  {
5320   "chips": ["gfx103"],
5321   "map": {"at": 166536, "to": "mm"},
5322   "name": "VGT_DMA_NUM_INSTANCES",
5323   "type_ref": "VGT_DMA_NUM_INSTANCES"
5324  },
5325  {
5326   "chips": ["gfx103"],
5327   "map": {"at": 166540, "to": "mm"},
5328   "name": "VGT_PRIMITIVEID_RESET",
5329   "type_ref": "VGT_PRIMITIVEID_RESET"
5330  },
5331  {
5332   "chips": ["gfx103"],
5333   "map": {"at": 166544, "to": "mm"},
5334   "name": "VGT_EVENT_INITIATOR",
5335   "type_ref": "VGT_EVENT_INITIATOR"
5336  },
5337  {
5338   "chips": ["gfx103"],
5339   "map": {"at": 166548, "to": "mm"},
5340   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5341   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
5342  },
5343  {
5344   "chips": ["gfx103"],
5345   "map": {"at": 166552, "to": "mm"},
5346   "name": "VGT_DRAW_PAYLOAD_CNTL",
5347   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
5348  },
5349  {
5350   "chips": ["gfx103"],
5351   "map": {"at": 166560, "to": "mm"},
5352   "name": "VGT_INSTANCE_STEP_RATE_0",
5353   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5354  },
5355  {
5356   "chips": ["gfx103"],
5357   "map": {"at": 166564, "to": "mm"},
5358   "name": "VGT_INSTANCE_STEP_RATE_1",
5359   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5360  },
5361  {
5362   "chips": ["gfx103"],
5363   "map": {"at": 166568, "to": "mm"},
5364   "name": "IA_MULTI_VGT_PARAM",
5365   "type_ref": "IA_MULTI_VGT_PARAM"
5366  },
5367  {
5368   "chips": ["gfx103"],
5369   "map": {"at": 166572, "to": "mm"},
5370   "name": "VGT_ESGS_RING_ITEMSIZE",
5371   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5372  },
5373  {
5374   "chips": ["gfx103"],
5375   "map": {"at": 166576, "to": "mm"},
5376   "name": "VGT_GSVS_RING_ITEMSIZE",
5377   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5378  },
5379  {
5380   "chips": ["gfx103"],
5381   "map": {"at": 166580, "to": "mm"},
5382   "name": "VGT_REUSE_OFF",
5383   "type_ref": "VGT_REUSE_OFF"
5384  },
5385  {
5386   "chips": ["gfx103"],
5387   "map": {"at": 166584, "to": "mm"},
5388   "name": "VGT_VTX_CNT_EN",
5389   "type_ref": "VGT_VTX_CNT_EN"
5390  },
5391  {
5392   "chips": ["gfx103"],
5393   "map": {"at": 166588, "to": "mm"},
5394   "name": "DB_HTILE_SURFACE",
5395   "type_ref": "DB_HTILE_SURFACE"
5396  },
5397  {
5398   "chips": ["gfx103"],
5399   "map": {"at": 166592, "to": "mm"},
5400   "name": "DB_SRESULTS_COMPARE_STATE0",
5401   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5402  },
5403  {
5404   "chips": ["gfx103"],
5405   "map": {"at": 166596, "to": "mm"},
5406   "name": "DB_SRESULTS_COMPARE_STATE1",
5407   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5408  },
5409  {
5410   "chips": ["gfx103"],
5411   "map": {"at": 166600, "to": "mm"},
5412   "name": "DB_PRELOAD_CONTROL",
5413   "type_ref": "DB_PRELOAD_CONTROL"
5414  },
5415  {
5416   "chips": ["gfx103"],
5417   "map": {"at": 166608, "to": "mm"},
5418   "name": "VGT_STRMOUT_BUFFER_SIZE_0",
5419   "type_ref": "COMPUTE_DIM_X"
5420  },
5421  {
5422   "chips": ["gfx103"],
5423   "map": {"at": 166612, "to": "mm"},
5424   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5425   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5426  },
5427  {
5428   "chips": ["gfx103"],
5429   "map": {"at": 166620, "to": "mm"},
5430   "name": "VGT_STRMOUT_BUFFER_OFFSET_0",
5431   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5432  },
5433  {
5434   "chips": ["gfx103"],
5435   "map": {"at": 166624, "to": "mm"},
5436   "name": "VGT_STRMOUT_BUFFER_SIZE_1",
5437   "type_ref": "COMPUTE_DIM_X"
5438  },
5439  {
5440   "chips": ["gfx103"],
5441   "map": {"at": 166628, "to": "mm"},
5442   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5443   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5444  },
5445  {
5446   "chips": ["gfx103"],
5447   "map": {"at": 166636, "to": "mm"},
5448   "name": "VGT_STRMOUT_BUFFER_OFFSET_1",
5449   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5450  },
5451  {
5452   "chips": ["gfx103"],
5453   "map": {"at": 166640, "to": "mm"},
5454   "name": "VGT_STRMOUT_BUFFER_SIZE_2",
5455   "type_ref": "COMPUTE_DIM_X"
5456  },
5457  {
5458   "chips": ["gfx103"],
5459   "map": {"at": 166644, "to": "mm"},
5460   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5461   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5462  },
5463  {
5464   "chips": ["gfx103"],
5465   "map": {"at": 166652, "to": "mm"},
5466   "name": "VGT_STRMOUT_BUFFER_OFFSET_2",
5467   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5468  },
5469  {
5470   "chips": ["gfx103"],
5471   "map": {"at": 166656, "to": "mm"},
5472   "name": "VGT_STRMOUT_BUFFER_SIZE_3",
5473   "type_ref": "COMPUTE_DIM_X"
5474  },
5475  {
5476   "chips": ["gfx103"],
5477   "map": {"at": 166660, "to": "mm"},
5478   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5479   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5480  },
5481  {
5482   "chips": ["gfx103"],
5483   "map": {"at": 166668, "to": "mm"},
5484   "name": "VGT_STRMOUT_BUFFER_OFFSET_3",
5485   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5486  },
5487  {
5488   "chips": ["gfx103"],
5489   "map": {"at": 166696, "to": "mm"},
5490   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET",
5491   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5492  },
5493  {
5494   "chips": ["gfx103"],
5495   "map": {"at": 166700, "to": "mm"},
5496   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE",
5497   "type_ref": "COMPUTE_DIM_X"
5498  },
5499  {
5500   "chips": ["gfx103"],
5501   "map": {"at": 166704, "to": "mm"},
5502   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5503   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5504  },
5505  {
5506   "chips": ["gfx103"],
5507   "map": {"at": 166712, "to": "mm"},
5508   "name": "VGT_GS_MAX_VERT_OUT",
5509   "type_ref": "VGT_GS_MAX_VERT_OUT"
5510  },
5511  {
5512   "chips": ["gfx103"],
5513   "map": {"at": 166732, "to": "mm"},
5514   "name": "GE_NGG_SUBGRP_CNTL",
5515   "type_ref": "GE_NGG_SUBGRP_CNTL"
5516  },
5517  {
5518   "chips": ["gfx103"],
5519   "map": {"at": 166736, "to": "mm"},
5520   "name": "VGT_TESS_DISTRIBUTION",
5521   "type_ref": "VGT_TESS_DISTRIBUTION"
5522  },
5523  {
5524   "chips": ["gfx103"],
5525   "map": {"at": 166740, "to": "mm"},
5526   "name": "VGT_SHADER_STAGES_EN",
5527   "type_ref": "VGT_SHADER_STAGES_EN"
5528  },
5529  {
5530   "chips": ["gfx103"],
5531   "map": {"at": 166744, "to": "mm"},
5532   "name": "VGT_LS_HS_CONFIG",
5533   "type_ref": "VGT_LS_HS_CONFIG"
5534  },
5535  {
5536   "chips": ["gfx103"],
5537   "map": {"at": 166748, "to": "mm"},
5538   "name": "VGT_GS_VERT_ITEMSIZE",
5539   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5540  },
5541  {
5542   "chips": ["gfx103"],
5543   "map": {"at": 166752, "to": "mm"},
5544   "name": "VGT_GS_VERT_ITEMSIZE_1",
5545   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5546  },
5547  {
5548   "chips": ["gfx103"],
5549   "map": {"at": 166756, "to": "mm"},
5550   "name": "VGT_GS_VERT_ITEMSIZE_2",
5551   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5552  },
5553  {
5554   "chips": ["gfx103"],
5555   "map": {"at": 166760, "to": "mm"},
5556   "name": "VGT_GS_VERT_ITEMSIZE_3",
5557   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5558  },
5559  {
5560   "chips": ["gfx103"],
5561   "map": {"at": 166764, "to": "mm"},
5562   "name": "VGT_TF_PARAM",
5563   "type_ref": "VGT_TF_PARAM"
5564  },
5565  {
5566   "chips": ["gfx103"],
5567   "map": {"at": 166768, "to": "mm"},
5568   "name": "DB_ALPHA_TO_MASK",
5569   "type_ref": "DB_ALPHA_TO_MASK"
5570  },
5571  {
5572   "chips": ["gfx103"],
5573   "map": {"at": 166772, "to": "mm"},
5574   "name": "VGT_DISPATCH_DRAW_INDEX",
5575   "type_ref": "VGT_DISPATCH_DRAW_INDEX"
5576  },
5577  {
5578   "chips": ["gfx103"],
5579   "map": {"at": 166776, "to": "mm"},
5580   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5581   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5582  },
5583  {
5584   "chips": ["gfx103"],
5585   "map": {"at": 166780, "to": "mm"},
5586   "name": "PA_SU_POLY_OFFSET_CLAMP",
5587   "type_ref": "PA_SU_POLY_OFFSET_CLAMP"
5588  },
5589  {
5590   "chips": ["gfx103"],
5591   "map": {"at": 166784, "to": "mm"},
5592   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE",
5593   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5594  },
5595  {
5596   "chips": ["gfx103"],
5597   "map": {"at": 166788, "to": "mm"},
5598   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET",
5599   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5600  },
5601  {
5602   "chips": ["gfx103"],
5603   "map": {"at": 166792, "to": "mm"},
5604   "name": "PA_SU_POLY_OFFSET_BACK_SCALE",
5605   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5606  },
5607  {
5608   "chips": ["gfx103"],
5609   "map": {"at": 166796, "to": "mm"},
5610   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET",
5611   "type_ref": "VGT_STRMOUT_BUFFER_OFFSET_0"
5612  },
5613  {
5614   "chips": ["gfx103"],
5615   "map": {"at": 166800, "to": "mm"},
5616   "name": "VGT_GS_INSTANCE_CNT",
5617   "type_ref": "VGT_GS_INSTANCE_CNT"
5618  },
5619  {
5620   "chips": ["gfx103"],
5621   "map": {"at": 166804, "to": "mm"},
5622   "name": "VGT_STRMOUT_CONFIG",
5623   "type_ref": "VGT_STRMOUT_CONFIG"
5624  },
5625  {
5626   "chips": ["gfx103"],
5627   "map": {"at": 166808, "to": "mm"},
5628   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5629   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5630  },
5631  {
5632   "chips": ["gfx103"],
5633   "map": {"at": 166812, "to": "mm"},
5634   "name": "VGT_DMA_EVENT_INITIATOR",
5635   "type_ref": "VGT_EVENT_INITIATOR"
5636  },
5637  {
5638   "chips": ["gfx103"],
5639   "map": {"at": 166868, "to": "mm"},
5640   "name": "PA_SC_CENTROID_PRIORITY_0",
5641   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5642  },
5643  {
5644   "chips": ["gfx103"],
5645   "map": {"at": 166872, "to": "mm"},
5646   "name": "PA_SC_CENTROID_PRIORITY_1",
5647   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5648  },
5649  {
5650   "chips": ["gfx103"],
5651   "map": {"at": 166876, "to": "mm"},
5652   "name": "PA_SC_LINE_CNTL",
5653   "type_ref": "PA_SC_LINE_CNTL"
5654  },
5655  {
5656   "chips": ["gfx103"],
5657   "map": {"at": 166880, "to": "mm"},
5658   "name": "PA_SC_AA_CONFIG",
5659   "type_ref": "PA_SC_AA_CONFIG"
5660  },
5661  {
5662   "chips": ["gfx103"],
5663   "map": {"at": 166884, "to": "mm"},
5664   "name": "PA_SU_VTX_CNTL",
5665   "type_ref": "PA_SU_VTX_CNTL"
5666  },
5667  {
5668   "chips": ["gfx103"],
5669   "map": {"at": 166888, "to": "mm"},
5670   "name": "PA_CL_GB_VERT_CLIP_ADJ",
5671   "type_ref": "PA_CL_UCP_0_X"
5672  },
5673  {
5674   "chips": ["gfx103"],
5675   "map": {"at": 166892, "to": "mm"},
5676   "name": "PA_CL_GB_VERT_DISC_ADJ",
5677   "type_ref": "PA_CL_UCP_0_X"
5678  },
5679  {
5680   "chips": ["gfx103"],
5681   "map": {"at": 166896, "to": "mm"},
5682   "name": "PA_CL_GB_HORZ_CLIP_ADJ",
5683   "type_ref": "PA_CL_UCP_0_X"
5684  },
5685  {
5686   "chips": ["gfx103"],
5687   "map": {"at": 166900, "to": "mm"},
5688   "name": "PA_CL_GB_HORZ_DISC_ADJ",
5689   "type_ref": "PA_CL_UCP_0_X"
5690  },
5691  {
5692   "chips": ["gfx103"],
5693   "map": {"at": 166904, "to": "mm"},
5694   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5695   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5696  },
5697  {
5698   "chips": ["gfx103"],
5699   "map": {"at": 166908, "to": "mm"},
5700   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5701   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5702  },
5703  {
5704   "chips": ["gfx103"],
5705   "map": {"at": 166912, "to": "mm"},
5706   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5707   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5708  },
5709  {
5710   "chips": ["gfx103"],
5711   "map": {"at": 166916, "to": "mm"},
5712   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5713   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5714  },
5715  {
5716   "chips": ["gfx103"],
5717   "map": {"at": 166920, "to": "mm"},
5718   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5719   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5720  },
5721  {
5722   "chips": ["gfx103"],
5723   "map": {"at": 166924, "to": "mm"},
5724   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5725   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5726  },
5727  {
5728   "chips": ["gfx103"],
5729   "map": {"at": 166928, "to": "mm"},
5730   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5731   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5732  },
5733  {
5734   "chips": ["gfx103"],
5735   "map": {"at": 166932, "to": "mm"},
5736   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5737   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5738  },
5739  {
5740   "chips": ["gfx103"],
5741   "map": {"at": 166936, "to": "mm"},
5742   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5743   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5744  },
5745  {
5746   "chips": ["gfx103"],
5747   "map": {"at": 166940, "to": "mm"},
5748   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5749   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5750  },
5751  {
5752   "chips": ["gfx103"],
5753   "map": {"at": 166944, "to": "mm"},
5754   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5755   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5756  },
5757  {
5758   "chips": ["gfx103"],
5759   "map": {"at": 166948, "to": "mm"},
5760   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5761   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5762  },
5763  {
5764   "chips": ["gfx103"],
5765   "map": {"at": 166952, "to": "mm"},
5766   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5767   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5768  },
5769  {
5770   "chips": ["gfx103"],
5771   "map": {"at": 166956, "to": "mm"},
5772   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5773   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5774  },
5775  {
5776   "chips": ["gfx103"],
5777   "map": {"at": 166960, "to": "mm"},
5778   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5779   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5780  },
5781  {
5782   "chips": ["gfx103"],
5783   "map": {"at": 166964, "to": "mm"},
5784   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5785   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5786  },
5787  {
5788   "chips": ["gfx103"],
5789   "map": {"at": 166968, "to": "mm"},
5790   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5791   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5792  },
5793  {
5794   "chips": ["gfx103"],
5795   "map": {"at": 166972, "to": "mm"},
5796   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5797   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5798  },
5799  {
5800   "chips": ["gfx103"],
5801   "map": {"at": 166976, "to": "mm"},
5802   "name": "PA_SC_SHADER_CONTROL",
5803   "type_ref": "PA_SC_SHADER_CONTROL"
5804  },
5805  {
5806   "chips": ["gfx103"],
5807   "map": {"at": 166980, "to": "mm"},
5808   "name": "PA_SC_BINNER_CNTL_0",
5809   "type_ref": "PA_SC_BINNER_CNTL_0"
5810  },
5811  {
5812   "chips": ["gfx103"],
5813   "map": {"at": 166984, "to": "mm"},
5814   "name": "PA_SC_BINNER_CNTL_1",
5815   "type_ref": "PA_SC_BINNER_CNTL_1"
5816  },
5817  {
5818   "chips": ["gfx103"],
5819   "map": {"at": 166988, "to": "mm"},
5820   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5821   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5822  },
5823  {
5824   "chips": ["gfx103"],
5825   "map": {"at": 166992, "to": "mm"},
5826   "name": "PA_SC_NGG_MODE_CNTL",
5827   "type_ref": "PA_SC_NGG_MODE_CNTL"
5828  },
5829  {
5830   "chips": ["gfx103"],
5831   "map": {"at": 167000, "to": "mm"},
5832   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5833   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5834  },
5835  {
5836   "chips": ["gfx103"],
5837   "map": {"at": 167004, "to": "mm"},
5838   "name": "VGT_OUT_DEALLOC_CNTL",
5839   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5840  },
5841  {
5842   "chips": ["gfx103"],
5843   "map": {"at": 167008, "to": "mm"},
5844   "name": "CB_COLOR0_BASE",
5845   "type_ref": "DB_HTILE_DATA_BASE"
5846  },
5847  {
5848   "chips": ["gfx103"],
5849   "map": {"at": 167012, "to": "mm"},
5850   "name": "CB_COLOR0_PITCH",
5851   "type_ref": "CB_COLOR0_PITCH"
5852  },
5853  {
5854   "chips": ["gfx103"],
5855   "map": {"at": 167016, "to": "mm"},
5856   "name": "CB_COLOR0_SLICE",
5857   "type_ref": "CB_COLOR0_SLICE"
5858  },
5859  {
5860   "chips": ["gfx103"],
5861   "map": {"at": 167020, "to": "mm"},
5862   "name": "CB_COLOR0_VIEW",
5863   "type_ref": "CB_COLOR0_VIEW"
5864  },
5865  {
5866   "chips": ["gfx103"],
5867   "map": {"at": 167024, "to": "mm"},
5868   "name": "CB_COLOR0_INFO",
5869   "type_ref": "CB_COLOR0_INFO"
5870  },
5871  {
5872   "chips": ["gfx103"],
5873   "map": {"at": 167028, "to": "mm"},
5874   "name": "CB_COLOR0_ATTRIB",
5875   "type_ref": "CB_COLOR0_ATTRIB"
5876  },
5877  {
5878   "chips": ["gfx103"],
5879   "map": {"at": 167032, "to": "mm"},
5880   "name": "CB_COLOR0_DCC_CONTROL",
5881   "type_ref": "CB_COLOR0_DCC_CONTROL"
5882  },
5883  {
5884   "chips": ["gfx103"],
5885   "map": {"at": 167036, "to": "mm"},
5886   "name": "CB_COLOR0_CMASK",
5887   "type_ref": "DB_HTILE_DATA_BASE"
5888  },
5889  {
5890   "chips": ["gfx103"],
5891   "map": {"at": 167040, "to": "mm"},
5892   "name": "CB_COLOR0_CMASK_SLICE",
5893   "type_ref": "CB_COLOR0_CMASK_SLICE"
5894  },
5895  {
5896   "chips": ["gfx103"],
5897   "map": {"at": 167044, "to": "mm"},
5898   "name": "CB_COLOR0_FMASK",
5899   "type_ref": "DB_HTILE_DATA_BASE"
5900  },
5901  {
5902   "chips": ["gfx103"],
5903   "map": {"at": 167048, "to": "mm"},
5904   "name": "CB_COLOR0_FMASK_SLICE",
5905   "type_ref": "CB_COLOR0_SLICE"
5906  },
5907  {
5908   "chips": ["gfx103"],
5909   "map": {"at": 167052, "to": "mm"},
5910   "name": "CB_COLOR0_CLEAR_WORD0",
5911   "type_ref": "CB_COLOR0_CLEAR_WORD0"
5912  },
5913  {
5914   "chips": ["gfx103"],
5915   "map": {"at": 167056, "to": "mm"},
5916   "name": "CB_COLOR0_CLEAR_WORD1",
5917   "type_ref": "CB_COLOR0_CLEAR_WORD1"
5918  },
5919  {
5920   "chips": ["gfx103"],
5921   "map": {"at": 167060, "to": "mm"},
5922   "name": "CB_COLOR0_DCC_BASE",
5923   "type_ref": "DB_HTILE_DATA_BASE"
5924  },
5925  {
5926   "chips": ["gfx103"],
5927   "map": {"at": 167068, "to": "mm"},
5928   "name": "CB_COLOR1_BASE",
5929   "type_ref": "DB_HTILE_DATA_BASE"
5930  },
5931  {
5932   "chips": ["gfx103"],
5933   "map": {"at": 167072, "to": "mm"},
5934   "name": "CB_COLOR1_PITCH",
5935   "type_ref": "CB_COLOR0_PITCH"
5936  },
5937  {
5938   "chips": ["gfx103"],
5939   "map": {"at": 167076, "to": "mm"},
5940   "name": "CB_COLOR1_SLICE",
5941   "type_ref": "CB_COLOR0_SLICE"
5942  },
5943  {
5944   "chips": ["gfx103"],
5945   "map": {"at": 167080, "to": "mm"},
5946   "name": "CB_COLOR1_VIEW",
5947   "type_ref": "CB_COLOR0_VIEW"
5948  },
5949  {
5950   "chips": ["gfx103"],
5951   "map": {"at": 167084, "to": "mm"},
5952   "name": "CB_COLOR1_INFO",
5953   "type_ref": "CB_COLOR0_INFO"
5954  },
5955  {
5956   "chips": ["gfx103"],
5957   "map": {"at": 167088, "to": "mm"},
5958   "name": "CB_COLOR1_ATTRIB",
5959   "type_ref": "CB_COLOR0_ATTRIB"
5960  },
5961  {
5962   "chips": ["gfx103"],
5963   "map": {"at": 167092, "to": "mm"},
5964   "name": "CB_COLOR1_DCC_CONTROL",
5965   "type_ref": "CB_COLOR0_DCC_CONTROL"
5966  },
5967  {
5968   "chips": ["gfx103"],
5969   "map": {"at": 167096, "to": "mm"},
5970   "name": "CB_COLOR1_CMASK",
5971   "type_ref": "DB_HTILE_DATA_BASE"
5972  },
5973  {
5974   "chips": ["gfx103"],
5975   "map": {"at": 167100, "to": "mm"},
5976   "name": "CB_COLOR1_CMASK_SLICE",
5977   "type_ref": "CB_COLOR0_CMASK_SLICE"
5978  },
5979  {
5980   "chips": ["gfx103"],
5981   "map": {"at": 167104, "to": "mm"},
5982   "name": "CB_COLOR1_FMASK",
5983   "type_ref": "DB_HTILE_DATA_BASE"
5984  },
5985  {
5986   "chips": ["gfx103"],
5987   "map": {"at": 167108, "to": "mm"},
5988   "name": "CB_COLOR1_FMASK_SLICE",
5989   "type_ref": "CB_COLOR0_SLICE"
5990  },
5991  {
5992   "chips": ["gfx103"],
5993   "map": {"at": 167112, "to": "mm"},
5994   "name": "CB_COLOR1_CLEAR_WORD0",
5995   "type_ref": "CB_COLOR0_CLEAR_WORD0"
5996  },
5997  {
5998   "chips": ["gfx103"],
5999   "map": {"at": 167116, "to": "mm"},
6000   "name": "CB_COLOR1_CLEAR_WORD1",
6001   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6002  },
6003  {
6004   "chips": ["gfx103"],
6005   "map": {"at": 167120, "to": "mm"},
6006   "name": "CB_COLOR1_DCC_BASE",
6007   "type_ref": "DB_HTILE_DATA_BASE"
6008  },
6009  {
6010   "chips": ["gfx103"],
6011   "map": {"at": 167128, "to": "mm"},
6012   "name": "CB_COLOR2_BASE",
6013   "type_ref": "DB_HTILE_DATA_BASE"
6014  },
6015  {
6016   "chips": ["gfx103"],
6017   "map": {"at": 167132, "to": "mm"},
6018   "name": "CB_COLOR2_PITCH",
6019   "type_ref": "CB_COLOR0_PITCH"
6020  },
6021  {
6022   "chips": ["gfx103"],
6023   "map": {"at": 167136, "to": "mm"},
6024   "name": "CB_COLOR2_SLICE",
6025   "type_ref": "CB_COLOR0_SLICE"
6026  },
6027  {
6028   "chips": ["gfx103"],
6029   "map": {"at": 167140, "to": "mm"},
6030   "name": "CB_COLOR2_VIEW",
6031   "type_ref": "CB_COLOR0_VIEW"
6032  },
6033  {
6034   "chips": ["gfx103"],
6035   "map": {"at": 167144, "to": "mm"},
6036   "name": "CB_COLOR2_INFO",
6037   "type_ref": "CB_COLOR0_INFO"
6038  },
6039  {
6040   "chips": ["gfx103"],
6041   "map": {"at": 167148, "to": "mm"},
6042   "name": "CB_COLOR2_ATTRIB",
6043   "type_ref": "CB_COLOR0_ATTRIB"
6044  },
6045  {
6046   "chips": ["gfx103"],
6047   "map": {"at": 167152, "to": "mm"},
6048   "name": "CB_COLOR2_DCC_CONTROL",
6049   "type_ref": "CB_COLOR0_DCC_CONTROL"
6050  },
6051  {
6052   "chips": ["gfx103"],
6053   "map": {"at": 167156, "to": "mm"},
6054   "name": "CB_COLOR2_CMASK",
6055   "type_ref": "DB_HTILE_DATA_BASE"
6056  },
6057  {
6058   "chips": ["gfx103"],
6059   "map": {"at": 167160, "to": "mm"},
6060   "name": "CB_COLOR2_CMASK_SLICE",
6061   "type_ref": "CB_COLOR0_CMASK_SLICE"
6062  },
6063  {
6064   "chips": ["gfx103"],
6065   "map": {"at": 167164, "to": "mm"},
6066   "name": "CB_COLOR2_FMASK",
6067   "type_ref": "DB_HTILE_DATA_BASE"
6068  },
6069  {
6070   "chips": ["gfx103"],
6071   "map": {"at": 167168, "to": "mm"},
6072   "name": "CB_COLOR2_FMASK_SLICE",
6073   "type_ref": "CB_COLOR0_SLICE"
6074  },
6075  {
6076   "chips": ["gfx103"],
6077   "map": {"at": 167172, "to": "mm"},
6078   "name": "CB_COLOR2_CLEAR_WORD0",
6079   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6080  },
6081  {
6082   "chips": ["gfx103"],
6083   "map": {"at": 167176, "to": "mm"},
6084   "name": "CB_COLOR2_CLEAR_WORD1",
6085   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6086  },
6087  {
6088   "chips": ["gfx103"],
6089   "map": {"at": 167180, "to": "mm"},
6090   "name": "CB_COLOR2_DCC_BASE",
6091   "type_ref": "DB_HTILE_DATA_BASE"
6092  },
6093  {
6094   "chips": ["gfx103"],
6095   "map": {"at": 167188, "to": "mm"},
6096   "name": "CB_COLOR3_BASE",
6097   "type_ref": "DB_HTILE_DATA_BASE"
6098  },
6099  {
6100   "chips": ["gfx103"],
6101   "map": {"at": 167192, "to": "mm"},
6102   "name": "CB_COLOR3_PITCH",
6103   "type_ref": "CB_COLOR0_PITCH"
6104  },
6105  {
6106   "chips": ["gfx103"],
6107   "map": {"at": 167196, "to": "mm"},
6108   "name": "CB_COLOR3_SLICE",
6109   "type_ref": "CB_COLOR0_SLICE"
6110  },
6111  {
6112   "chips": ["gfx103"],
6113   "map": {"at": 167200, "to": "mm"},
6114   "name": "CB_COLOR3_VIEW",
6115   "type_ref": "CB_COLOR0_VIEW"
6116  },
6117  {
6118   "chips": ["gfx103"],
6119   "map": {"at": 167204, "to": "mm"},
6120   "name": "CB_COLOR3_INFO",
6121   "type_ref": "CB_COLOR0_INFO"
6122  },
6123  {
6124   "chips": ["gfx103"],
6125   "map": {"at": 167208, "to": "mm"},
6126   "name": "CB_COLOR3_ATTRIB",
6127   "type_ref": "CB_COLOR0_ATTRIB"
6128  },
6129  {
6130   "chips": ["gfx103"],
6131   "map": {"at": 167212, "to": "mm"},
6132   "name": "CB_COLOR3_DCC_CONTROL",
6133   "type_ref": "CB_COLOR0_DCC_CONTROL"
6134  },
6135  {
6136   "chips": ["gfx103"],
6137   "map": {"at": 167216, "to": "mm"},
6138   "name": "CB_COLOR3_CMASK",
6139   "type_ref": "DB_HTILE_DATA_BASE"
6140  },
6141  {
6142   "chips": ["gfx103"],
6143   "map": {"at": 167220, "to": "mm"},
6144   "name": "CB_COLOR3_CMASK_SLICE",
6145   "type_ref": "CB_COLOR0_CMASK_SLICE"
6146  },
6147  {
6148   "chips": ["gfx103"],
6149   "map": {"at": 167224, "to": "mm"},
6150   "name": "CB_COLOR3_FMASK",
6151   "type_ref": "DB_HTILE_DATA_BASE"
6152  },
6153  {
6154   "chips": ["gfx103"],
6155   "map": {"at": 167228, "to": "mm"},
6156   "name": "CB_COLOR3_FMASK_SLICE",
6157   "type_ref": "CB_COLOR0_SLICE"
6158  },
6159  {
6160   "chips": ["gfx103"],
6161   "map": {"at": 167232, "to": "mm"},
6162   "name": "CB_COLOR3_CLEAR_WORD0",
6163   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6164  },
6165  {
6166   "chips": ["gfx103"],
6167   "map": {"at": 167236, "to": "mm"},
6168   "name": "CB_COLOR3_CLEAR_WORD1",
6169   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6170  },
6171  {
6172   "chips": ["gfx103"],
6173   "map": {"at": 167240, "to": "mm"},
6174   "name": "CB_COLOR3_DCC_BASE",
6175   "type_ref": "DB_HTILE_DATA_BASE"
6176  },
6177  {
6178   "chips": ["gfx103"],
6179   "map": {"at": 167248, "to": "mm"},
6180   "name": "CB_COLOR4_BASE",
6181   "type_ref": "DB_HTILE_DATA_BASE"
6182  },
6183  {
6184   "chips": ["gfx103"],
6185   "map": {"at": 167252, "to": "mm"},
6186   "name": "CB_COLOR4_PITCH",
6187   "type_ref": "CB_COLOR0_PITCH"
6188  },
6189  {
6190   "chips": ["gfx103"],
6191   "map": {"at": 167256, "to": "mm"},
6192   "name": "CB_COLOR4_SLICE",
6193   "type_ref": "CB_COLOR0_SLICE"
6194  },
6195  {
6196   "chips": ["gfx103"],
6197   "map": {"at": 167260, "to": "mm"},
6198   "name": "CB_COLOR4_VIEW",
6199   "type_ref": "CB_COLOR0_VIEW"
6200  },
6201  {
6202   "chips": ["gfx103"],
6203   "map": {"at": 167264, "to": "mm"},
6204   "name": "CB_COLOR4_INFO",
6205   "type_ref": "CB_COLOR0_INFO"
6206  },
6207  {
6208   "chips": ["gfx103"],
6209   "map": {"at": 167268, "to": "mm"},
6210   "name": "CB_COLOR4_ATTRIB",
6211   "type_ref": "CB_COLOR0_ATTRIB"
6212  },
6213  {
6214   "chips": ["gfx103"],
6215   "map": {"at": 167272, "to": "mm"},
6216   "name": "CB_COLOR4_DCC_CONTROL",
6217   "type_ref": "CB_COLOR0_DCC_CONTROL"
6218  },
6219  {
6220   "chips": ["gfx103"],
6221   "map": {"at": 167276, "to": "mm"},
6222   "name": "CB_COLOR4_CMASK",
6223   "type_ref": "DB_HTILE_DATA_BASE"
6224  },
6225  {
6226   "chips": ["gfx103"],
6227   "map": {"at": 167280, "to": "mm"},
6228   "name": "CB_COLOR4_CMASK_SLICE",
6229   "type_ref": "CB_COLOR0_CMASK_SLICE"
6230  },
6231  {
6232   "chips": ["gfx103"],
6233   "map": {"at": 167284, "to": "mm"},
6234   "name": "CB_COLOR4_FMASK",
6235   "type_ref": "DB_HTILE_DATA_BASE"
6236  },
6237  {
6238   "chips": ["gfx103"],
6239   "map": {"at": 167288, "to": "mm"},
6240   "name": "CB_COLOR4_FMASK_SLICE",
6241   "type_ref": "CB_COLOR0_SLICE"
6242  },
6243  {
6244   "chips": ["gfx103"],
6245   "map": {"at": 167292, "to": "mm"},
6246   "name": "CB_COLOR4_CLEAR_WORD0",
6247   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6248  },
6249  {
6250   "chips": ["gfx103"],
6251   "map": {"at": 167296, "to": "mm"},
6252   "name": "CB_COLOR4_CLEAR_WORD1",
6253   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6254  },
6255  {
6256   "chips": ["gfx103"],
6257   "map": {"at": 167300, "to": "mm"},
6258   "name": "CB_COLOR4_DCC_BASE",
6259   "type_ref": "DB_HTILE_DATA_BASE"
6260  },
6261  {
6262   "chips": ["gfx103"],
6263   "map": {"at": 167308, "to": "mm"},
6264   "name": "CB_COLOR5_BASE",
6265   "type_ref": "DB_HTILE_DATA_BASE"
6266  },
6267  {
6268   "chips": ["gfx103"],
6269   "map": {"at": 167312, "to": "mm"},
6270   "name": "CB_COLOR5_PITCH",
6271   "type_ref": "CB_COLOR0_PITCH"
6272  },
6273  {
6274   "chips": ["gfx103"],
6275   "map": {"at": 167316, "to": "mm"},
6276   "name": "CB_COLOR5_SLICE",
6277   "type_ref": "CB_COLOR0_SLICE"
6278  },
6279  {
6280   "chips": ["gfx103"],
6281   "map": {"at": 167320, "to": "mm"},
6282   "name": "CB_COLOR5_VIEW",
6283   "type_ref": "CB_COLOR0_VIEW"
6284  },
6285  {
6286   "chips": ["gfx103"],
6287   "map": {"at": 167324, "to": "mm"},
6288   "name": "CB_COLOR5_INFO",
6289   "type_ref": "CB_COLOR0_INFO"
6290  },
6291  {
6292   "chips": ["gfx103"],
6293   "map": {"at": 167328, "to": "mm"},
6294   "name": "CB_COLOR5_ATTRIB",
6295   "type_ref": "CB_COLOR0_ATTRIB"
6296  },
6297  {
6298   "chips": ["gfx103"],
6299   "map": {"at": 167332, "to": "mm"},
6300   "name": "CB_COLOR5_DCC_CONTROL",
6301   "type_ref": "CB_COLOR0_DCC_CONTROL"
6302  },
6303  {
6304   "chips": ["gfx103"],
6305   "map": {"at": 167336, "to": "mm"},
6306   "name": "CB_COLOR5_CMASK",
6307   "type_ref": "DB_HTILE_DATA_BASE"
6308  },
6309  {
6310   "chips": ["gfx103"],
6311   "map": {"at": 167340, "to": "mm"},
6312   "name": "CB_COLOR5_CMASK_SLICE",
6313   "type_ref": "CB_COLOR0_CMASK_SLICE"
6314  },
6315  {
6316   "chips": ["gfx103"],
6317   "map": {"at": 167344, "to": "mm"},
6318   "name": "CB_COLOR5_FMASK",
6319   "type_ref": "DB_HTILE_DATA_BASE"
6320  },
6321  {
6322   "chips": ["gfx103"],
6323   "map": {"at": 167348, "to": "mm"},
6324   "name": "CB_COLOR5_FMASK_SLICE",
6325   "type_ref": "CB_COLOR0_SLICE"
6326  },
6327  {
6328   "chips": ["gfx103"],
6329   "map": {"at": 167352, "to": "mm"},
6330   "name": "CB_COLOR5_CLEAR_WORD0",
6331   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6332  },
6333  {
6334   "chips": ["gfx103"],
6335   "map": {"at": 167356, "to": "mm"},
6336   "name": "CB_COLOR5_CLEAR_WORD1",
6337   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6338  },
6339  {
6340   "chips": ["gfx103"],
6341   "map": {"at": 167360, "to": "mm"},
6342   "name": "CB_COLOR5_DCC_BASE",
6343   "type_ref": "DB_HTILE_DATA_BASE"
6344  },
6345  {
6346   "chips": ["gfx103"],
6347   "map": {"at": 167368, "to": "mm"},
6348   "name": "CB_COLOR6_BASE",
6349   "type_ref": "DB_HTILE_DATA_BASE"
6350  },
6351  {
6352   "chips": ["gfx103"],
6353   "map": {"at": 167372, "to": "mm"},
6354   "name": "CB_COLOR6_PITCH",
6355   "type_ref": "CB_COLOR0_PITCH"
6356  },
6357  {
6358   "chips": ["gfx103"],
6359   "map": {"at": 167376, "to": "mm"},
6360   "name": "CB_COLOR6_SLICE",
6361   "type_ref": "CB_COLOR0_SLICE"
6362  },
6363  {
6364   "chips": ["gfx103"],
6365   "map": {"at": 167380, "to": "mm"},
6366   "name": "CB_COLOR6_VIEW",
6367   "type_ref": "CB_COLOR0_VIEW"
6368  },
6369  {
6370   "chips": ["gfx103"],
6371   "map": {"at": 167384, "to": "mm"},
6372   "name": "CB_COLOR6_INFO",
6373   "type_ref": "CB_COLOR0_INFO"
6374  },
6375  {
6376   "chips": ["gfx103"],
6377   "map": {"at": 167388, "to": "mm"},
6378   "name": "CB_COLOR6_ATTRIB",
6379   "type_ref": "CB_COLOR0_ATTRIB"
6380  },
6381  {
6382   "chips": ["gfx103"],
6383   "map": {"at": 167392, "to": "mm"},
6384   "name": "CB_COLOR6_DCC_CONTROL",
6385   "type_ref": "CB_COLOR0_DCC_CONTROL"
6386  },
6387  {
6388   "chips": ["gfx103"],
6389   "map": {"at": 167396, "to": "mm"},
6390   "name": "CB_COLOR6_CMASK",
6391   "type_ref": "DB_HTILE_DATA_BASE"
6392  },
6393  {
6394   "chips": ["gfx103"],
6395   "map": {"at": 167400, "to": "mm"},
6396   "name": "CB_COLOR6_CMASK_SLICE",
6397   "type_ref": "CB_COLOR0_CMASK_SLICE"
6398  },
6399  {
6400   "chips": ["gfx103"],
6401   "map": {"at": 167404, "to": "mm"},
6402   "name": "CB_COLOR6_FMASK",
6403   "type_ref": "DB_HTILE_DATA_BASE"
6404  },
6405  {
6406   "chips": ["gfx103"],
6407   "map": {"at": 167408, "to": "mm"},
6408   "name": "CB_COLOR6_FMASK_SLICE",
6409   "type_ref": "CB_COLOR0_SLICE"
6410  },
6411  {
6412   "chips": ["gfx103"],
6413   "map": {"at": 167412, "to": "mm"},
6414   "name": "CB_COLOR6_CLEAR_WORD0",
6415   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6416  },
6417  {
6418   "chips": ["gfx103"],
6419   "map": {"at": 167416, "to": "mm"},
6420   "name": "CB_COLOR6_CLEAR_WORD1",
6421   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6422  },
6423  {
6424   "chips": ["gfx103"],
6425   "map": {"at": 167420, "to": "mm"},
6426   "name": "CB_COLOR6_DCC_BASE",
6427   "type_ref": "DB_HTILE_DATA_BASE"
6428  },
6429  {
6430   "chips": ["gfx103"],
6431   "map": {"at": 167428, "to": "mm"},
6432   "name": "CB_COLOR7_BASE",
6433   "type_ref": "DB_HTILE_DATA_BASE"
6434  },
6435  {
6436   "chips": ["gfx103"],
6437   "map": {"at": 167432, "to": "mm"},
6438   "name": "CB_COLOR7_PITCH",
6439   "type_ref": "CB_COLOR0_PITCH"
6440  },
6441  {
6442   "chips": ["gfx103"],
6443   "map": {"at": 167436, "to": "mm"},
6444   "name": "CB_COLOR7_SLICE",
6445   "type_ref": "CB_COLOR0_SLICE"
6446  },
6447  {
6448   "chips": ["gfx103"],
6449   "map": {"at": 167440, "to": "mm"},
6450   "name": "CB_COLOR7_VIEW",
6451   "type_ref": "CB_COLOR0_VIEW"
6452  },
6453  {
6454   "chips": ["gfx103"],
6455   "map": {"at": 167444, "to": "mm"},
6456   "name": "CB_COLOR7_INFO",
6457   "type_ref": "CB_COLOR0_INFO"
6458  },
6459  {
6460   "chips": ["gfx103"],
6461   "map": {"at": 167448, "to": "mm"},
6462   "name": "CB_COLOR7_ATTRIB",
6463   "type_ref": "CB_COLOR0_ATTRIB"
6464  },
6465  {
6466   "chips": ["gfx103"],
6467   "map": {"at": 167452, "to": "mm"},
6468   "name": "CB_COLOR7_DCC_CONTROL",
6469   "type_ref": "CB_COLOR0_DCC_CONTROL"
6470  },
6471  {
6472   "chips": ["gfx103"],
6473   "map": {"at": 167456, "to": "mm"},
6474   "name": "CB_COLOR7_CMASK",
6475   "type_ref": "DB_HTILE_DATA_BASE"
6476  },
6477  {
6478   "chips": ["gfx103"],
6479   "map": {"at": 167460, "to": "mm"},
6480   "name": "CB_COLOR7_CMASK_SLICE",
6481   "type_ref": "CB_COLOR0_CMASK_SLICE"
6482  },
6483  {
6484   "chips": ["gfx103"],
6485   "map": {"at": 167464, "to": "mm"},
6486   "name": "CB_COLOR7_FMASK",
6487   "type_ref": "DB_HTILE_DATA_BASE"
6488  },
6489  {
6490   "chips": ["gfx103"],
6491   "map": {"at": 167468, "to": "mm"},
6492   "name": "CB_COLOR7_FMASK_SLICE",
6493   "type_ref": "CB_COLOR0_SLICE"
6494  },
6495  {
6496   "chips": ["gfx103"],
6497   "map": {"at": 167472, "to": "mm"},
6498   "name": "CB_COLOR7_CLEAR_WORD0",
6499   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6500  },
6501  {
6502   "chips": ["gfx103"],
6503   "map": {"at": 167476, "to": "mm"},
6504   "name": "CB_COLOR7_CLEAR_WORD1",
6505   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6506  },
6507  {
6508   "chips": ["gfx103"],
6509   "map": {"at": 167480, "to": "mm"},
6510   "name": "CB_COLOR7_DCC_BASE",
6511   "type_ref": "DB_HTILE_DATA_BASE"
6512  },
6513  {
6514   "chips": ["gfx103"],
6515   "map": {"at": 167488, "to": "mm"},
6516   "name": "CB_COLOR0_BASE_EXT",
6517   "type_ref": "CB_COLOR0_BASE_EXT"
6518  },
6519  {
6520   "chips": ["gfx103"],
6521   "map": {"at": 167492, "to": "mm"},
6522   "name": "CB_COLOR1_BASE_EXT",
6523   "type_ref": "CB_COLOR0_BASE_EXT"
6524  },
6525  {
6526   "chips": ["gfx103"],
6527   "map": {"at": 167496, "to": "mm"},
6528   "name": "CB_COLOR2_BASE_EXT",
6529   "type_ref": "CB_COLOR0_BASE_EXT"
6530  },
6531  {
6532   "chips": ["gfx103"],
6533   "map": {"at": 167500, "to": "mm"},
6534   "name": "CB_COLOR3_BASE_EXT",
6535   "type_ref": "CB_COLOR0_BASE_EXT"
6536  },
6537  {
6538   "chips": ["gfx103"],
6539   "map": {"at": 167504, "to": "mm"},
6540   "name": "CB_COLOR4_BASE_EXT",
6541   "type_ref": "CB_COLOR0_BASE_EXT"
6542  },
6543  {
6544   "chips": ["gfx103"],
6545   "map": {"at": 167508, "to": "mm"},
6546   "name": "CB_COLOR5_BASE_EXT",
6547   "type_ref": "CB_COLOR0_BASE_EXT"
6548  },
6549  {
6550   "chips": ["gfx103"],
6551   "map": {"at": 167512, "to": "mm"},
6552   "name": "CB_COLOR6_BASE_EXT",
6553   "type_ref": "CB_COLOR0_BASE_EXT"
6554  },
6555  {
6556   "chips": ["gfx103"],
6557   "map": {"at": 167516, "to": "mm"},
6558   "name": "CB_COLOR7_BASE_EXT",
6559   "type_ref": "CB_COLOR0_BASE_EXT"
6560  },
6561  {
6562   "chips": ["gfx103"],
6563   "map": {"at": 167520, "to": "mm"},
6564   "name": "CB_COLOR0_CMASK_BASE_EXT",
6565   "type_ref": "CB_COLOR0_BASE_EXT"
6566  },
6567  {
6568   "chips": ["gfx103"],
6569   "map": {"at": 167524, "to": "mm"},
6570   "name": "CB_COLOR1_CMASK_BASE_EXT",
6571   "type_ref": "CB_COLOR0_BASE_EXT"
6572  },
6573  {
6574   "chips": ["gfx103"],
6575   "map": {"at": 167528, "to": "mm"},
6576   "name": "CB_COLOR2_CMASK_BASE_EXT",
6577   "type_ref": "CB_COLOR0_BASE_EXT"
6578  },
6579  {
6580   "chips": ["gfx103"],
6581   "map": {"at": 167532, "to": "mm"},
6582   "name": "CB_COLOR3_CMASK_BASE_EXT",
6583   "type_ref": "CB_COLOR0_BASE_EXT"
6584  },
6585  {
6586   "chips": ["gfx103"],
6587   "map": {"at": 167536, "to": "mm"},
6588   "name": "CB_COLOR4_CMASK_BASE_EXT",
6589   "type_ref": "CB_COLOR0_BASE_EXT"
6590  },
6591  {
6592   "chips": ["gfx103"],
6593   "map": {"at": 167540, "to": "mm"},
6594   "name": "CB_COLOR5_CMASK_BASE_EXT",
6595   "type_ref": "CB_COLOR0_BASE_EXT"
6596  },
6597  {
6598   "chips": ["gfx103"],
6599   "map": {"at": 167544, "to": "mm"},
6600   "name": "CB_COLOR6_CMASK_BASE_EXT",
6601   "type_ref": "CB_COLOR0_BASE_EXT"
6602  },
6603  {
6604   "chips": ["gfx103"],
6605   "map": {"at": 167548, "to": "mm"},
6606   "name": "CB_COLOR7_CMASK_BASE_EXT",
6607   "type_ref": "CB_COLOR0_BASE_EXT"
6608  },
6609  {
6610   "chips": ["gfx103"],
6611   "map": {"at": 167552, "to": "mm"},
6612   "name": "CB_COLOR0_FMASK_BASE_EXT",
6613   "type_ref": "CB_COLOR0_BASE_EXT"
6614  },
6615  {
6616   "chips": ["gfx103"],
6617   "map": {"at": 167556, "to": "mm"},
6618   "name": "CB_COLOR1_FMASK_BASE_EXT",
6619   "type_ref": "CB_COLOR0_BASE_EXT"
6620  },
6621  {
6622   "chips": ["gfx103"],
6623   "map": {"at": 167560, "to": "mm"},
6624   "name": "CB_COLOR2_FMASK_BASE_EXT",
6625   "type_ref": "CB_COLOR0_BASE_EXT"
6626  },
6627  {
6628   "chips": ["gfx103"],
6629   "map": {"at": 167564, "to": "mm"},
6630   "name": "CB_COLOR3_FMASK_BASE_EXT",
6631   "type_ref": "CB_COLOR0_BASE_EXT"
6632  },
6633  {
6634   "chips": ["gfx103"],
6635   "map": {"at": 167568, "to": "mm"},
6636   "name": "CB_COLOR4_FMASK_BASE_EXT",
6637   "type_ref": "CB_COLOR0_BASE_EXT"
6638  },
6639  {
6640   "chips": ["gfx103"],
6641   "map": {"at": 167572, "to": "mm"},
6642   "name": "CB_COLOR5_FMASK_BASE_EXT",
6643   "type_ref": "CB_COLOR0_BASE_EXT"
6644  },
6645  {
6646   "chips": ["gfx103"],
6647   "map": {"at": 167576, "to": "mm"},
6648   "name": "CB_COLOR6_FMASK_BASE_EXT",
6649   "type_ref": "CB_COLOR0_BASE_EXT"
6650  },
6651  {
6652   "chips": ["gfx103"],
6653   "map": {"at": 167580, "to": "mm"},
6654   "name": "CB_COLOR7_FMASK_BASE_EXT",
6655   "type_ref": "CB_COLOR0_BASE_EXT"
6656  },
6657  {
6658   "chips": ["gfx103"],
6659   "map": {"at": 167584, "to": "mm"},
6660   "name": "CB_COLOR0_DCC_BASE_EXT",
6661   "type_ref": "CB_COLOR0_BASE_EXT"
6662  },
6663  {
6664   "chips": ["gfx103"],
6665   "map": {"at": 167588, "to": "mm"},
6666   "name": "CB_COLOR1_DCC_BASE_EXT",
6667   "type_ref": "CB_COLOR0_BASE_EXT"
6668  },
6669  {
6670   "chips": ["gfx103"],
6671   "map": {"at": 167592, "to": "mm"},
6672   "name": "CB_COLOR2_DCC_BASE_EXT",
6673   "type_ref": "CB_COLOR0_BASE_EXT"
6674  },
6675  {
6676   "chips": ["gfx103"],
6677   "map": {"at": 167596, "to": "mm"},
6678   "name": "CB_COLOR3_DCC_BASE_EXT",
6679   "type_ref": "CB_COLOR0_BASE_EXT"
6680  },
6681  {
6682   "chips": ["gfx103"],
6683   "map": {"at": 167600, "to": "mm"},
6684   "name": "CB_COLOR4_DCC_BASE_EXT",
6685   "type_ref": "CB_COLOR0_BASE_EXT"
6686  },
6687  {
6688   "chips": ["gfx103"],
6689   "map": {"at": 167604, "to": "mm"},
6690   "name": "CB_COLOR5_DCC_BASE_EXT",
6691   "type_ref": "CB_COLOR0_BASE_EXT"
6692  },
6693  {
6694   "chips": ["gfx103"],
6695   "map": {"at": 167608, "to": "mm"},
6696   "name": "CB_COLOR6_DCC_BASE_EXT",
6697   "type_ref": "CB_COLOR0_BASE_EXT"
6698  },
6699  {
6700   "chips": ["gfx103"],
6701   "map": {"at": 167612, "to": "mm"},
6702   "name": "CB_COLOR7_DCC_BASE_EXT",
6703   "type_ref": "CB_COLOR0_BASE_EXT"
6704  },
6705  {
6706   "chips": ["gfx103"],
6707   "map": {"at": 167616, "to": "mm"},
6708   "name": "CB_COLOR0_ATTRIB2",
6709   "type_ref": "CB_COLOR0_ATTRIB2"
6710  },
6711  {
6712   "chips": ["gfx103"],
6713   "map": {"at": 167620, "to": "mm"},
6714   "name": "CB_COLOR1_ATTRIB2",
6715   "type_ref": "CB_COLOR0_ATTRIB2"
6716  },
6717  {
6718   "chips": ["gfx103"],
6719   "map": {"at": 167624, "to": "mm"},
6720   "name": "CB_COLOR2_ATTRIB2",
6721   "type_ref": "CB_COLOR0_ATTRIB2"
6722  },
6723  {
6724   "chips": ["gfx103"],
6725   "map": {"at": 167628, "to": "mm"},
6726   "name": "CB_COLOR3_ATTRIB2",
6727   "type_ref": "CB_COLOR0_ATTRIB2"
6728  },
6729  {
6730   "chips": ["gfx103"],
6731   "map": {"at": 167632, "to": "mm"},
6732   "name": "CB_COLOR4_ATTRIB2",
6733   "type_ref": "CB_COLOR0_ATTRIB2"
6734  },
6735  {
6736   "chips": ["gfx103"],
6737   "map": {"at": 167636, "to": "mm"},
6738   "name": "CB_COLOR5_ATTRIB2",
6739   "type_ref": "CB_COLOR0_ATTRIB2"
6740  },
6741  {
6742   "chips": ["gfx103"],
6743   "map": {"at": 167640, "to": "mm"},
6744   "name": "CB_COLOR6_ATTRIB2",
6745   "type_ref": "CB_COLOR0_ATTRIB2"
6746  },
6747  {
6748   "chips": ["gfx103"],
6749   "map": {"at": 167644, "to": "mm"},
6750   "name": "CB_COLOR7_ATTRIB2",
6751   "type_ref": "CB_COLOR0_ATTRIB2"
6752  },
6753  {
6754   "chips": ["gfx103"],
6755   "map": {"at": 167648, "to": "mm"},
6756   "name": "CB_COLOR0_ATTRIB3",
6757   "type_ref": "CB_COLOR0_ATTRIB3"
6758  },
6759  {
6760   "chips": ["gfx103"],
6761   "map": {"at": 167652, "to": "mm"},
6762   "name": "CB_COLOR1_ATTRIB3",
6763   "type_ref": "CB_COLOR0_ATTRIB3"
6764  },
6765  {
6766   "chips": ["gfx103"],
6767   "map": {"at": 167656, "to": "mm"},
6768   "name": "CB_COLOR2_ATTRIB3",
6769   "type_ref": "CB_COLOR0_ATTRIB3"
6770  },
6771  {
6772   "chips": ["gfx103"],
6773   "map": {"at": 167660, "to": "mm"},
6774   "name": "CB_COLOR3_ATTRIB3",
6775   "type_ref": "CB_COLOR0_ATTRIB3"
6776  },
6777  {
6778   "chips": ["gfx103"],
6779   "map": {"at": 167664, "to": "mm"},
6780   "name": "CB_COLOR4_ATTRIB3",
6781   "type_ref": "CB_COLOR0_ATTRIB3"
6782  },
6783  {
6784   "chips": ["gfx103"],
6785   "map": {"at": 167668, "to": "mm"},
6786   "name": "CB_COLOR5_ATTRIB3",
6787   "type_ref": "CB_COLOR0_ATTRIB3"
6788  },
6789  {
6790   "chips": ["gfx103"],
6791   "map": {"at": 167672, "to": "mm"},
6792   "name": "CB_COLOR6_ATTRIB3",
6793   "type_ref": "CB_COLOR0_ATTRIB3"
6794  },
6795  {
6796   "chips": ["gfx103"],
6797   "map": {"at": 167676, "to": "mm"},
6798   "name": "CB_COLOR7_ATTRIB3",
6799   "type_ref": "CB_COLOR0_ATTRIB3"
6800  },
6801  {
6802   "chips": ["gfx103"],
6803   "map": {"at": 196608, "to": "mm"},
6804   "name": "CP_EOP_DONE_ADDR_LO",
6805   "type_ref": "CP_EOP_DONE_ADDR_LO"
6806  },
6807  {
6808   "chips": ["gfx103"],
6809   "map": {"at": 196612, "to": "mm"},
6810   "name": "CP_EOP_DONE_ADDR_HI",
6811   "type_ref": "CP_EOP_DONE_ADDR_HI"
6812  },
6813  {
6814   "chips": ["gfx103"],
6815   "map": {"at": 196616, "to": "mm"},
6816   "name": "CP_EOP_DONE_DATA_LO",
6817   "type_ref": "CP_EOP_DONE_DATA_LO"
6818  },
6819  {
6820   "chips": ["gfx103"],
6821   "map": {"at": 196620, "to": "mm"},
6822   "name": "CP_EOP_DONE_DATA_HI",
6823   "type_ref": "CP_EOP_DONE_DATA_HI"
6824  },
6825  {
6826   "chips": ["gfx103"],
6827   "map": {"at": 196624, "to": "mm"},
6828   "name": "CP_EOP_LAST_FENCE_LO",
6829   "type_ref": "CP_EOP_LAST_FENCE_LO"
6830  },
6831  {
6832   "chips": ["gfx103"],
6833   "map": {"at": 196628, "to": "mm"},
6834   "name": "CP_EOP_LAST_FENCE_HI",
6835   "type_ref": "CP_EOP_LAST_FENCE_HI"
6836  },
6837  {
6838   "chips": ["gfx103"],
6839   "map": {"at": 196632, "to": "mm"},
6840   "name": "CP_STREAM_OUT_ADDR_LO",
6841   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6842  },
6843  {
6844   "chips": ["gfx103"],
6845   "map": {"at": 196636, "to": "mm"},
6846   "name": "CP_STREAM_OUT_ADDR_HI",
6847   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6848  },
6849  {
6850   "chips": ["gfx103"],
6851   "map": {"at": 196640, "to": "mm"},
6852   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO",
6853   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6854  },
6855  {
6856   "chips": ["gfx103"],
6857   "map": {"at": 196644, "to": "mm"},
6858   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI",
6859   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6860  },
6861  {
6862   "chips": ["gfx103"],
6863   "map": {"at": 196648, "to": "mm"},
6864   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO",
6865   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6866  },
6867  {
6868   "chips": ["gfx103"],
6869   "map": {"at": 196652, "to": "mm"},
6870   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI",
6871   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6872  },
6873  {
6874   "chips": ["gfx103"],
6875   "map": {"at": 196656, "to": "mm"},
6876   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO",
6877   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6878  },
6879  {
6880   "chips": ["gfx103"],
6881   "map": {"at": 196660, "to": "mm"},
6882   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI",
6883   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6884  },
6885  {
6886   "chips": ["gfx103"],
6887   "map": {"at": 196664, "to": "mm"},
6888   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO",
6889   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6890  },
6891  {
6892   "chips": ["gfx103"],
6893   "map": {"at": 196668, "to": "mm"},
6894   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI",
6895   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6896  },
6897  {
6898   "chips": ["gfx103"],
6899   "map": {"at": 196672, "to": "mm"},
6900   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO",
6901   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6902  },
6903  {
6904   "chips": ["gfx103"],
6905   "map": {"at": 196676, "to": "mm"},
6906   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI",
6907   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6908  },
6909  {
6910   "chips": ["gfx103"],
6911   "map": {"at": 196680, "to": "mm"},
6912   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO",
6913   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6914  },
6915  {
6916   "chips": ["gfx103"],
6917   "map": {"at": 196684, "to": "mm"},
6918   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI",
6919   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6920  },
6921  {
6922   "chips": ["gfx103"],
6923   "map": {"at": 196688, "to": "mm"},
6924   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO",
6925   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6926  },
6927  {
6928   "chips": ["gfx103"],
6929   "map": {"at": 196692, "to": "mm"},
6930   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI",
6931   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6932  },
6933  {
6934   "chips": ["gfx103"],
6935   "map": {"at": 196696, "to": "mm"},
6936   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO",
6937   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6938  },
6939  {
6940   "chips": ["gfx103"],
6941   "map": {"at": 196700, "to": "mm"},
6942   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI",
6943   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6944  },
6945  {
6946   "chips": ["gfx103"],
6947   "map": {"at": 196704, "to": "mm"},
6948   "name": "CP_PIPE_STATS_ADDR_LO",
6949   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6950  },
6951  {
6952   "chips": ["gfx103"],
6953   "map": {"at": 196708, "to": "mm"},
6954   "name": "CP_PIPE_STATS_ADDR_HI",
6955   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6956  },
6957  {
6958   "chips": ["gfx103"],
6959   "map": {"at": 196712, "to": "mm"},
6960   "name": "CP_VGT_IAVERT_COUNT_LO",
6961   "type_ref": "CP_VGT_IAVERT_COUNT_LO"
6962  },
6963  {
6964   "chips": ["gfx103"],
6965   "map": {"at": 196716, "to": "mm"},
6966   "name": "CP_VGT_IAVERT_COUNT_HI",
6967   "type_ref": "CP_VGT_IAVERT_COUNT_HI"
6968  },
6969  {
6970   "chips": ["gfx103"],
6971   "map": {"at": 196720, "to": "mm"},
6972   "name": "CP_VGT_IAPRIM_COUNT_LO",
6973   "type_ref": "CP_VGT_IAPRIM_COUNT_LO"
6974  },
6975  {
6976   "chips": ["gfx103"],
6977   "map": {"at": 196724, "to": "mm"},
6978   "name": "CP_VGT_IAPRIM_COUNT_HI",
6979   "type_ref": "CP_VGT_IAPRIM_COUNT_HI"
6980  },
6981  {
6982   "chips": ["gfx103"],
6983   "map": {"at": 196728, "to": "mm"},
6984   "name": "CP_VGT_GSPRIM_COUNT_LO",
6985   "type_ref": "CP_VGT_GSPRIM_COUNT_LO"
6986  },
6987  {
6988   "chips": ["gfx103"],
6989   "map": {"at": 196732, "to": "mm"},
6990   "name": "CP_VGT_GSPRIM_COUNT_HI",
6991   "type_ref": "CP_VGT_GSPRIM_COUNT_HI"
6992  },
6993  {
6994   "chips": ["gfx103"],
6995   "map": {"at": 196736, "to": "mm"},
6996   "name": "CP_VGT_VSINVOC_COUNT_LO",
6997   "type_ref": "CP_VGT_VSINVOC_COUNT_LO"
6998  },
6999  {
7000   "chips": ["gfx103"],
7001   "map": {"at": 196740, "to": "mm"},
7002   "name": "CP_VGT_VSINVOC_COUNT_HI",
7003   "type_ref": "CP_VGT_VSINVOC_COUNT_HI"
7004  },
7005  {
7006   "chips": ["gfx103"],
7007   "map": {"at": 196744, "to": "mm"},
7008   "name": "CP_VGT_GSINVOC_COUNT_LO",
7009   "type_ref": "CP_VGT_GSINVOC_COUNT_LO"
7010  },
7011  {
7012   "chips": ["gfx103"],
7013   "map": {"at": 196748, "to": "mm"},
7014   "name": "CP_VGT_GSINVOC_COUNT_HI",
7015   "type_ref": "CP_VGT_GSINVOC_COUNT_HI"
7016  },
7017  {
7018   "chips": ["gfx103"],
7019   "map": {"at": 196752, "to": "mm"},
7020   "name": "CP_VGT_HSINVOC_COUNT_LO",
7021   "type_ref": "CP_VGT_HSINVOC_COUNT_LO"
7022  },
7023  {
7024   "chips": ["gfx103"],
7025   "map": {"at": 196756, "to": "mm"},
7026   "name": "CP_VGT_HSINVOC_COUNT_HI",
7027   "type_ref": "CP_VGT_HSINVOC_COUNT_HI"
7028  },
7029  {
7030   "chips": ["gfx103"],
7031   "map": {"at": 196760, "to": "mm"},
7032   "name": "CP_VGT_DSINVOC_COUNT_LO",
7033   "type_ref": "CP_VGT_DSINVOC_COUNT_LO"
7034  },
7035  {
7036   "chips": ["gfx103"],
7037   "map": {"at": 196764, "to": "mm"},
7038   "name": "CP_VGT_DSINVOC_COUNT_HI",
7039   "type_ref": "CP_VGT_DSINVOC_COUNT_HI"
7040  },
7041  {
7042   "chips": ["gfx103"],
7043   "map": {"at": 196768, "to": "mm"},
7044   "name": "CP_PA_CINVOC_COUNT_LO",
7045   "type_ref": "CP_PA_CINVOC_COUNT_LO"
7046  },
7047  {
7048   "chips": ["gfx103"],
7049   "map": {"at": 196772, "to": "mm"},
7050   "name": "CP_PA_CINVOC_COUNT_HI",
7051   "type_ref": "CP_PA_CINVOC_COUNT_HI"
7052  },
7053  {
7054   "chips": ["gfx103"],
7055   "map": {"at": 196776, "to": "mm"},
7056   "name": "CP_PA_CPRIM_COUNT_LO",
7057   "type_ref": "CP_PA_CPRIM_COUNT_LO"
7058  },
7059  {
7060   "chips": ["gfx103"],
7061   "map": {"at": 196780, "to": "mm"},
7062   "name": "CP_PA_CPRIM_COUNT_HI",
7063   "type_ref": "CP_PA_CPRIM_COUNT_HI"
7064  },
7065  {
7066   "chips": ["gfx103"],
7067   "map": {"at": 196784, "to": "mm"},
7068   "name": "CP_SC_PSINVOC_COUNT0_LO",
7069   "type_ref": "CP_SC_PSINVOC_COUNT0_LO"
7070  },
7071  {
7072   "chips": ["gfx103"],
7073   "map": {"at": 196788, "to": "mm"},
7074   "name": "CP_SC_PSINVOC_COUNT0_HI",
7075   "type_ref": "CP_SC_PSINVOC_COUNT0_HI"
7076  },
7077  {
7078   "chips": ["gfx103"],
7079   "map": {"at": 196792, "to": "mm"},
7080   "name": "CP_SC_PSINVOC_COUNT1_LO",
7081   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7082  },
7083  {
7084   "chips": ["gfx103"],
7085   "map": {"at": 196796, "to": "mm"},
7086   "name": "CP_SC_PSINVOC_COUNT1_HI",
7087   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
7088  },
7089  {
7090   "chips": ["gfx103"],
7091   "map": {"at": 196800, "to": "mm"},
7092   "name": "CP_VGT_CSINVOC_COUNT_LO",
7093   "type_ref": "CP_VGT_CSINVOC_COUNT_LO"
7094  },
7095  {
7096   "chips": ["gfx103"],
7097   "map": {"at": 196804, "to": "mm"},
7098   "name": "CP_VGT_CSINVOC_COUNT_HI",
7099   "type_ref": "CP_VGT_CSINVOC_COUNT_HI"
7100  },
7101  {
7102   "chips": ["gfx103"],
7103   "map": {"at": 196852, "to": "mm"},
7104   "name": "CP_PIPE_STATS_CONTROL",
7105   "type_ref": "CP_PIPE_STATS_CONTROL"
7106  },
7107  {
7108   "chips": ["gfx103"],
7109   "map": {"at": 196856, "to": "mm"},
7110   "name": "CP_STREAM_OUT_CONTROL",
7111   "type_ref": "CP_PIPE_STATS_CONTROL"
7112  },
7113  {
7114   "chips": ["gfx103"],
7115   "map": {"at": 196860, "to": "mm"},
7116   "name": "CP_STRMOUT_CNTL",
7117   "type_ref": "CP_STRMOUT_CNTL"
7118  },
7119  {
7120   "chips": ["gfx103"],
7121   "map": {"at": 196864, "to": "mm"},
7122   "name": "SCRATCH_REG0",
7123   "type_ref": "SCRATCH_REG0"
7124  },
7125  {
7126   "chips": ["gfx103"],
7127   "map": {"at": 196868, "to": "mm"},
7128   "name": "SCRATCH_REG1",
7129   "type_ref": "SCRATCH_REG1"
7130  },
7131  {
7132   "chips": ["gfx103"],
7133   "map": {"at": 196872, "to": "mm"},
7134   "name": "SCRATCH_REG2",
7135   "type_ref": "SCRATCH_REG2"
7136  },
7137  {
7138   "chips": ["gfx103"],
7139   "map": {"at": 196876, "to": "mm"},
7140   "name": "SCRATCH_REG3",
7141   "type_ref": "SCRATCH_REG3"
7142  },
7143  {
7144   "chips": ["gfx103"],
7145   "map": {"at": 196880, "to": "mm"},
7146   "name": "SCRATCH_REG4",
7147   "type_ref": "SCRATCH_REG4"
7148  },
7149  {
7150   "chips": ["gfx103"],
7151   "map": {"at": 196884, "to": "mm"},
7152   "name": "SCRATCH_REG5",
7153   "type_ref": "SCRATCH_REG5"
7154  },
7155  {
7156   "chips": ["gfx103"],
7157   "map": {"at": 196888, "to": "mm"},
7158   "name": "SCRATCH_REG6",
7159   "type_ref": "SCRATCH_REG6"
7160  },
7161  {
7162   "chips": ["gfx103"],
7163   "map": {"at": 196892, "to": "mm"},
7164   "name": "SCRATCH_REG7",
7165   "type_ref": "SCRATCH_REG7"
7166  },
7167  {
7168   "chips": ["gfx103"],
7169   "map": {"at": 196896, "to": "mm"},
7170   "name": "SCRATCH_REG_ATOMIC",
7171   "type_ref": "SCRATCH_REG_ATOMIC"
7172  },
7173  {
7174   "chips": ["gfx103"],
7175   "map": {"at": 196908, "to": "mm"},
7176   "name": "CP_APPEND_DDID_CNT",
7177   "type_ref": "COMPUTE_PGM_HI"
7178  },
7179  {
7180   "chips": ["gfx103"],
7181   "map": {"at": 196912, "to": "mm"},
7182   "name": "CP_APPEND_DATA_HI",
7183   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7184  },
7185  {
7186   "chips": ["gfx103"],
7187   "map": {"at": 196916, "to": "mm"},
7188   "name": "CP_APPEND_LAST_CS_FENCE_HI",
7189   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7190  },
7191  {
7192   "chips": ["gfx103"],
7193   "map": {"at": 196920, "to": "mm"},
7194   "name": "CP_APPEND_LAST_PS_FENCE_HI",
7195   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7196  },
7197  {
7198   "chips": ["gfx103"],
7199   "map": {"at": 196928, "to": "mm"},
7200   "name": "SCRATCH_UMSK",
7201   "type_ref": "SCRATCH_UMSK"
7202  },
7203  {
7204   "chips": ["gfx103"],
7205   "map": {"at": 196932, "to": "mm"},
7206   "name": "SCRATCH_ADDR",
7207   "type_ref": "SCRATCH_ADDR"
7208  },
7209  {
7210   "chips": ["gfx103"],
7211   "map": {"at": 196936, "to": "mm"},
7212   "name": "CP_PFP_ATOMIC_PREOP_LO",
7213   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7214  },
7215  {
7216   "chips": ["gfx103"],
7217   "map": {"at": 196940, "to": "mm"},
7218   "name": "CP_PFP_ATOMIC_PREOP_HI",
7219   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7220  },
7221  {
7222   "chips": ["gfx103"],
7223   "map": {"at": 196944, "to": "mm"},
7224   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO",
7225   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7226  },
7227  {
7228   "chips": ["gfx103"],
7229   "map": {"at": 196948, "to": "mm"},
7230   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI",
7231   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7232  },
7233  {
7234   "chips": ["gfx103"],
7235   "map": {"at": 196952, "to": "mm"},
7236   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO",
7237   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7238  },
7239  {
7240   "chips": ["gfx103"],
7241   "map": {"at": 196956, "to": "mm"},
7242   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI",
7243   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7244  },
7245  {
7246   "chips": ["gfx103"],
7247   "map": {"at": 196960, "to": "mm"},
7248   "name": "CP_APPEND_ADDR_LO",
7249   "type_ref": "CP_APPEND_ADDR_LO"
7250  },
7251  {
7252   "chips": ["gfx103"],
7253   "map": {"at": 196964, "to": "mm"},
7254   "name": "CP_APPEND_ADDR_HI",
7255   "type_ref": "CP_APPEND_ADDR_HI"
7256  },
7257  {
7258   "chips": ["gfx103"],
7259   "map": {"at": 196968, "to": "mm"},
7260   "name": "CP_APPEND_DATA",
7261   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7262  },
7263  {
7264   "chips": ["gfx103"],
7265   "map": {"at": 196972, "to": "mm"},
7266   "name": "CP_APPEND_LAST_CS_FENCE",
7267   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7268  },
7269  {
7270   "chips": ["gfx103"],
7271   "map": {"at": 196976, "to": "mm"},
7272   "name": "CP_APPEND_LAST_PS_FENCE",
7273   "type_ref": "CP_APPEND_LAST_CS_FENCE_HI"
7274  },
7275  {
7276   "chips": ["gfx103"],
7277   "map": {"at": 196980, "to": "mm"},
7278   "name": "CP_ATOMIC_PREOP_LO",
7279   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7280  },
7281  {
7282   "chips": ["gfx103"],
7283   "map": {"at": 196984, "to": "mm"},
7284   "name": "CP_ATOMIC_PREOP_HI",
7285   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7286  },
7287  {
7288   "chips": ["gfx103"],
7289   "map": {"at": 196988, "to": "mm"},
7290   "name": "CP_GDS_ATOMIC0_PREOP_LO",
7291   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7292  },
7293  {
7294   "chips": ["gfx103"],
7295   "map": {"at": 196992, "to": "mm"},
7296   "name": "CP_GDS_ATOMIC0_PREOP_HI",
7297   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7298  },
7299  {
7300   "chips": ["gfx103"],
7301   "map": {"at": 196996, "to": "mm"},
7302   "name": "CP_GDS_ATOMIC1_PREOP_LO",
7303   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7304  },
7305  {
7306   "chips": ["gfx103"],
7307   "map": {"at": 197000, "to": "mm"},
7308   "name": "CP_GDS_ATOMIC1_PREOP_HI",
7309   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7310  },
7311  {
7312   "chips": ["gfx103"],
7313   "map": {"at": 197028, "to": "mm"},
7314   "name": "CP_ME_MC_WADDR_LO",
7315   "type_ref": "CP_ME_MC_WADDR_LO"
7316  },
7317  {
7318   "chips": ["gfx103"],
7319   "map": {"at": 197032, "to": "mm"},
7320   "name": "CP_ME_MC_WADDR_HI",
7321   "type_ref": "CP_ME_MC_WADDR_HI"
7322  },
7323  {
7324   "chips": ["gfx103"],
7325   "map": {"at": 197036, "to": "mm"},
7326   "name": "CP_ME_MC_WDATA_LO",
7327   "type_ref": "CP_ME_MC_WDATA_LO"
7328  },
7329  {
7330   "chips": ["gfx103"],
7331   "map": {"at": 197040, "to": "mm"},
7332   "name": "CP_ME_MC_WDATA_HI",
7333   "type_ref": "CP_ME_MC_WDATA_HI"
7334  },
7335  {
7336   "chips": ["gfx103"],
7337   "map": {"at": 197044, "to": "mm"},
7338   "name": "CP_ME_MC_RADDR_LO",
7339   "type_ref": "CP_ME_MC_RADDR_LO"
7340  },
7341  {
7342   "chips": ["gfx103"],
7343   "map": {"at": 197048, "to": "mm"},
7344   "name": "CP_ME_MC_RADDR_HI",
7345   "type_ref": "CP_ME_MC_RADDR_HI"
7346  },
7347  {
7348   "chips": ["gfx103"],
7349   "map": {"at": 197052, "to": "mm"},
7350   "name": "CP_SEM_WAIT_TIMER",
7351   "type_ref": "CP_SEM_WAIT_TIMER"
7352  },
7353  {
7354   "chips": ["gfx103"],
7355   "map": {"at": 197056, "to": "mm"},
7356   "name": "CP_SIG_SEM_ADDR_LO",
7357   "type_ref": "CP_SIG_SEM_ADDR_LO"
7358  },
7359  {
7360   "chips": ["gfx103"],
7361   "map": {"at": 197060, "to": "mm"},
7362   "name": "CP_SIG_SEM_ADDR_HI",
7363   "type_ref": "CP_SIG_SEM_ADDR_HI"
7364  },
7365  {
7366   "chips": ["gfx103"],
7367   "map": {"at": 197072, "to": "mm"},
7368   "name": "CP_WAIT_REG_MEM_TIMEOUT",
7369   "type_ref": "CP_WAIT_REG_MEM_TIMEOUT"
7370  },
7371  {
7372   "chips": ["gfx103"],
7373   "map": {"at": 197076, "to": "mm"},
7374   "name": "CP_WAIT_SEM_ADDR_LO",
7375   "type_ref": "CP_SIG_SEM_ADDR_LO"
7376  },
7377  {
7378   "chips": ["gfx103"],
7379   "map": {"at": 197080, "to": "mm"},
7380   "name": "CP_WAIT_SEM_ADDR_HI",
7381   "type_ref": "CP_SIG_SEM_ADDR_HI"
7382  },
7383  {
7384   "chips": ["gfx103"],
7385   "map": {"at": 197084, "to": "mm"},
7386   "name": "CP_DMA_PFP_CONTROL",
7387   "type_ref": "CP_DMA_PFP_CONTROL"
7388  },
7389  {
7390   "chips": ["gfx103"],
7391   "map": {"at": 197088, "to": "mm"},
7392   "name": "CP_DMA_ME_CONTROL",
7393   "type_ref": "CP_DMA_PFP_CONTROL"
7394  },
7395  {
7396   "chips": ["gfx103"],
7397   "map": {"at": 197092, "to": "mm"},
7398   "name": "CP_COHER_BASE_HI",
7399   "type_ref": "CP_COHER_BASE_HI"
7400  },
7401  {
7402   "chips": ["gfx103"],
7403   "map": {"at": 197100, "to": "mm"},
7404   "name": "CP_COHER_START_DELAY",
7405   "type_ref": "CP_COHER_START_DELAY"
7406  },
7407  {
7408   "chips": ["gfx103"],
7409   "map": {"at": 197104, "to": "mm"},
7410   "name": "CP_COHER_CNTL",
7411   "type_ref": "CP_COHER_CNTL"
7412  },
7413  {
7414   "chips": ["gfx103"],
7415   "map": {"at": 197108, "to": "mm"},
7416   "name": "CP_COHER_SIZE",
7417   "type_ref": "CP_COHER_SIZE"
7418  },
7419  {
7420   "chips": ["gfx103"],
7421   "map": {"at": 197112, "to": "mm"},
7422   "name": "CP_COHER_BASE",
7423   "type_ref": "CP_COHER_BASE"
7424  },
7425  {
7426   "chips": ["gfx103"],
7427   "map": {"at": 197116, "to": "mm"},
7428   "name": "CP_COHER_STATUS",
7429   "type_ref": "CP_COHER_STATUS"
7430  },
7431  {
7432   "chips": ["gfx103"],
7433   "map": {"at": 197120, "to": "mm"},
7434   "name": "CP_DMA_ME_SRC_ADDR",
7435   "type_ref": "CP_DMA_ME_SRC_ADDR"
7436  },
7437  {
7438   "chips": ["gfx103"],
7439   "map": {"at": 197124, "to": "mm"},
7440   "name": "CP_DMA_ME_SRC_ADDR_HI",
7441   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7442  },
7443  {
7444   "chips": ["gfx103"],
7445   "map": {"at": 197128, "to": "mm"},
7446   "name": "CP_DMA_ME_DST_ADDR",
7447   "type_ref": "CP_DMA_ME_DST_ADDR"
7448  },
7449  {
7450   "chips": ["gfx103"],
7451   "map": {"at": 197132, "to": "mm"},
7452   "name": "CP_DMA_ME_DST_ADDR_HI",
7453   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7454  },
7455  {
7456   "chips": ["gfx103"],
7457   "map": {"at": 197136, "to": "mm"},
7458   "name": "CP_DMA_ME_COMMAND",
7459   "type_ref": "CP_DMA_ME_COMMAND"
7460  },
7461  {
7462   "chips": ["gfx103"],
7463   "map": {"at": 197140, "to": "mm"},
7464   "name": "CP_DMA_PFP_SRC_ADDR",
7465   "type_ref": "CP_DMA_ME_SRC_ADDR"
7466  },
7467  {
7468   "chips": ["gfx103"],
7469   "map": {"at": 197144, "to": "mm"},
7470   "name": "CP_DMA_PFP_SRC_ADDR_HI",
7471   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7472  },
7473  {
7474   "chips": ["gfx103"],
7475   "map": {"at": 197148, "to": "mm"},
7476   "name": "CP_DMA_PFP_DST_ADDR",
7477   "type_ref": "CP_DMA_ME_DST_ADDR"
7478  },
7479  {
7480   "chips": ["gfx103"],
7481   "map": {"at": 197152, "to": "mm"},
7482   "name": "CP_DMA_PFP_DST_ADDR_HI",
7483   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7484  },
7485  {
7486   "chips": ["gfx103"],
7487   "map": {"at": 197156, "to": "mm"},
7488   "name": "CP_DMA_PFP_COMMAND",
7489   "type_ref": "CP_DMA_ME_COMMAND"
7490  },
7491  {
7492   "chips": ["gfx103"],
7493   "map": {"at": 197160, "to": "mm"},
7494   "name": "CP_DMA_CNTL",
7495   "type_ref": "CP_DMA_CNTL"
7496  },
7497  {
7498   "chips": ["gfx103"],
7499   "map": {"at": 197164, "to": "mm"},
7500   "name": "CP_DMA_READ_TAGS",
7501   "type_ref": "CP_DMA_READ_TAGS"
7502  },
7503  {
7504   "chips": ["gfx103"],
7505   "map": {"at": 197168, "to": "mm"},
7506   "name": "CP_COHER_SIZE_HI",
7507   "type_ref": "CP_COHER_SIZE_HI"
7508  },
7509  {
7510   "chips": ["gfx103"],
7511   "map": {"at": 197172, "to": "mm"},
7512   "name": "CP_PFP_IB_CONTROL",
7513   "type_ref": "CP_PFP_IB_CONTROL"
7514  },
7515  {
7516   "chips": ["gfx103"],
7517   "map": {"at": 197176, "to": "mm"},
7518   "name": "CP_PFP_LOAD_CONTROL",
7519   "type_ref": "CP_PFP_LOAD_CONTROL"
7520  },
7521  {
7522   "chips": ["gfx103"],
7523   "map": {"at": 197180, "to": "mm"},
7524   "name": "CP_SCRATCH_INDEX",
7525   "type_ref": "CP_CPC_SCRATCH_INDEX"
7526  },
7527  {
7528   "chips": ["gfx103"],
7529   "map": {"at": 197184, "to": "mm"},
7530   "name": "CP_SCRATCH_DATA",
7531   "type_ref": "CP_CPC_SCRATCH_DATA"
7532  },
7533  {
7534   "chips": ["gfx103"],
7535   "map": {"at": 197188, "to": "mm"},
7536   "name": "CP_RB_OFFSET",
7537   "type_ref": "CP_RB_OFFSET"
7538  },
7539  {
7540   "chips": ["gfx103"],
7541   "map": {"at": 197196, "to": "mm"},
7542   "name": "CP_IB2_OFFSET",
7543   "type_ref": "CP_IB2_OFFSET"
7544  },
7545  {
7546   "chips": ["gfx103"],
7547   "map": {"at": 197208, "to": "mm"},
7548   "name": "CP_IB2_PREAMBLE_BEGIN",
7549   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7550  },
7551  {
7552   "chips": ["gfx103"],
7553   "map": {"at": 197212, "to": "mm"},
7554   "name": "CP_IB2_PREAMBLE_END",
7555   "type_ref": "CP_IB2_PREAMBLE_END"
7556  },
7557  {
7558   "chips": ["gfx103"],
7559   "map": {"at": 197216, "to": "mm"},
7560   "name": "CP_CE_IB1_OFFSET",
7561   "type_ref": "CP_CE_IB1_OFFSET"
7562  },
7563  {
7564   "chips": ["gfx103"],
7565   "map": {"at": 197220, "to": "mm"},
7566   "name": "CP_CE_IB2_OFFSET",
7567   "type_ref": "CP_IB2_OFFSET"
7568  },
7569  {
7570   "chips": ["gfx103"],
7571   "map": {"at": 197224, "to": "mm"},
7572   "name": "CP_CE_COUNTER",
7573   "type_ref": "CP_CE_COUNTER"
7574  },
7575  {
7576   "chips": ["gfx103"],
7577   "map": {"at": 197232, "to": "mm"},
7578   "name": "CP_DMA_ME_CMD_ADDR_LO",
7579   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7580  },
7581  {
7582   "chips": ["gfx103"],
7583   "map": {"at": 197236, "to": "mm"},
7584   "name": "CP_DMA_ME_CMD_ADDR_HI",
7585   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7586  },
7587  {
7588   "chips": ["gfx103"],
7589   "map": {"at": 197240, "to": "mm"},
7590   "name": "CP_DMA_PFP_CMD_ADDR_LO",
7591   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7592  },
7593  {
7594   "chips": ["gfx103"],
7595   "map": {"at": 197244, "to": "mm"},
7596   "name": "CP_DMA_PFP_CMD_ADDR_HI",
7597   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7598  },
7599  {
7600   "chips": ["gfx103"],
7601   "map": {"at": 197248, "to": "mm"},
7602   "name": "CP_APPEND_CMD_ADDR_LO",
7603   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
7604  },
7605  {
7606   "chips": ["gfx103"],
7607   "map": {"at": 197252, "to": "mm"},
7608   "name": "CP_APPEND_CMD_ADDR_HI",
7609   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
7610  },
7611  {
7612   "chips": ["gfx103"],
7613   "map": {"at": 197256, "to": "mm"},
7614   "name": "UCONFIG_RESERVED_REG0",
7615   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7616  },
7617  {
7618   "chips": ["gfx103"],
7619   "map": {"at": 197260, "to": "mm"},
7620   "name": "UCONFIG_RESERVED_REG1",
7621   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
7622  },
7623  {
7624   "chips": ["gfx103"],
7625   "map": {"at": 197280, "to": "mm"},
7626   "name": "CP_CE_ATOMIC_PREOP_LO",
7627   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
7628  },
7629  {
7630   "chips": ["gfx103"],
7631   "map": {"at": 197284, "to": "mm"},
7632   "name": "CP_CE_ATOMIC_PREOP_HI",
7633   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
7634  },
7635  {
7636   "chips": ["gfx103"],
7637   "map": {"at": 197288, "to": "mm"},
7638   "name": "CP_CE_GDS_ATOMIC0_PREOP_LO",
7639   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
7640  },
7641  {
7642   "chips": ["gfx103"],
7643   "map": {"at": 197292, "to": "mm"},
7644   "name": "CP_CE_GDS_ATOMIC0_PREOP_HI",
7645   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
7646  },
7647  {
7648   "chips": ["gfx103"],
7649   "map": {"at": 197296, "to": "mm"},
7650   "name": "CP_CE_GDS_ATOMIC1_PREOP_LO",
7651   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
7652  },
7653  {
7654   "chips": ["gfx103"],
7655   "map": {"at": 197300, "to": "mm"},
7656   "name": "CP_CE_GDS_ATOMIC1_PREOP_HI",
7657   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
7658  },
7659  {
7660   "chips": ["gfx103"],
7661   "map": {"at": 197364, "to": "mm"},
7662   "name": "CP_CE_INIT_CMD_BUFSZ",
7663   "type_ref": "CP_CE_INIT_CMD_BUFSZ"
7664  },
7665  {
7666   "chips": ["gfx103"],
7667   "map": {"at": 197368, "to": "mm"},
7668   "name": "CP_CE_IB1_CMD_BUFSZ",
7669   "type_ref": "CP_CE_IB1_CMD_BUFSZ"
7670  },
7671  {
7672   "chips": ["gfx103"],
7673   "map": {"at": 197372, "to": "mm"},
7674   "name": "CP_CE_IB2_CMD_BUFSZ",
7675   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7676  },
7677  {
7678   "chips": ["gfx103"],
7679   "map": {"at": 197380, "to": "mm"},
7680   "name": "CP_IB2_CMD_BUFSZ",
7681   "type_ref": "CP_CE_IB2_CMD_BUFSZ"
7682  },
7683  {
7684   "chips": ["gfx103"],
7685   "map": {"at": 197384, "to": "mm"},
7686   "name": "CP_ST_CMD_BUFSZ",
7687   "type_ref": "CP_ST_CMD_BUFSZ"
7688  },
7689  {
7690   "chips": ["gfx103"],
7691   "map": {"at": 197388, "to": "mm"},
7692   "name": "CP_CE_INIT_BASE_LO",
7693   "type_ref": "CP_CE_INIT_BASE_LO"
7694  },
7695  {
7696   "chips": ["gfx103"],
7697   "map": {"at": 197392, "to": "mm"},
7698   "name": "CP_CE_INIT_BASE_HI",
7699   "type_ref": "CP_CE_INIT_BASE_HI"
7700  },
7701  {
7702   "chips": ["gfx103"],
7703   "map": {"at": 197396, "to": "mm"},
7704   "name": "CP_CE_INIT_BUFSZ",
7705   "type_ref": "CP_CE_INIT_BUFSZ"
7706  },
7707  {
7708   "chips": ["gfx103"],
7709   "map": {"at": 197400, "to": "mm"},
7710   "name": "CP_CE_IB1_BASE_LO",
7711   "type_ref": "CP_CE_IB1_BASE_LO"
7712  },
7713  {
7714   "chips": ["gfx103"],
7715   "map": {"at": 197404, "to": "mm"},
7716   "name": "CP_CE_IB1_BASE_HI",
7717   "type_ref": "CP_CE_IB1_BASE_HI"
7718  },
7719  {
7720   "chips": ["gfx103"],
7721   "map": {"at": 197408, "to": "mm"},
7722   "name": "CP_CE_IB1_BUFSZ",
7723   "type_ref": "CP_CE_IB1_BUFSZ"
7724  },
7725  {
7726   "chips": ["gfx103"],
7727   "map": {"at": 197412, "to": "mm"},
7728   "name": "CP_CE_IB2_BASE_LO",
7729   "type_ref": "CP_CE_IB2_BASE_LO"
7730  },
7731  {
7732   "chips": ["gfx103"],
7733   "map": {"at": 197416, "to": "mm"},
7734   "name": "CP_CE_IB2_BASE_HI",
7735   "type_ref": "CP_CE_IB2_BASE_HI"
7736  },
7737  {
7738   "chips": ["gfx103"],
7739   "map": {"at": 197420, "to": "mm"},
7740   "name": "CP_CE_IB2_BUFSZ",
7741   "type_ref": "CP_CE_IB2_BUFSZ"
7742  },
7743  {
7744   "chips": ["gfx103"],
7745   "map": {"at": 197436, "to": "mm"},
7746   "name": "CP_IB2_BASE_LO",
7747   "type_ref": "CP_CE_IB2_BASE_LO"
7748  },
7749  {
7750   "chips": ["gfx103"],
7751   "map": {"at": 197440, "to": "mm"},
7752   "name": "CP_IB2_BASE_HI",
7753   "type_ref": "CP_CE_IB2_BASE_HI"
7754  },
7755  {
7756   "chips": ["gfx103"],
7757   "map": {"at": 197444, "to": "mm"},
7758   "name": "CP_IB2_BUFSZ",
7759   "type_ref": "CP_CE_IB2_BUFSZ"
7760  },
7761  {
7762   "chips": ["gfx103"],
7763   "map": {"at": 197448, "to": "mm"},
7764   "name": "CP_ST_BASE_LO",
7765   "type_ref": "CP_ST_BASE_LO"
7766  },
7767  {
7768   "chips": ["gfx103"],
7769   "map": {"at": 197452, "to": "mm"},
7770   "name": "CP_ST_BASE_HI",
7771   "type_ref": "CP_ST_BASE_HI"
7772  },
7773  {
7774   "chips": ["gfx103"],
7775   "map": {"at": 197456, "to": "mm"},
7776   "name": "CP_ST_BUFSZ",
7777   "type_ref": "CP_ST_BUFSZ"
7778  },
7779  {
7780   "chips": ["gfx103"],
7781   "map": {"at": 197460, "to": "mm"},
7782   "name": "CP_EOP_DONE_EVENT_CNTL",
7783   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7784  },
7785  {
7786   "chips": ["gfx103"],
7787   "map": {"at": 197464, "to": "mm"},
7788   "name": "CP_EOP_DONE_DATA_CNTL",
7789   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7790  },
7791  {
7792   "chips": ["gfx103"],
7793   "map": {"at": 197468, "to": "mm"},
7794   "name": "CP_EOP_DONE_CNTX_ID",
7795   "type_ref": "CP_EOP_DONE_CNTX_ID"
7796  },
7797  {
7798   "chips": ["gfx103"],
7799   "map": {"at": 197472, "to": "mm"},
7800   "name": "CP_DB_BASE_LO",
7801   "type_ref": "CP_DB_BASE_LO"
7802  },
7803  {
7804   "chips": ["gfx103"],
7805   "map": {"at": 197476, "to": "mm"},
7806   "name": "CP_DB_BASE_HI",
7807   "type_ref": "CP_DB_BASE_HI"
7808  },
7809  {
7810   "chips": ["gfx103"],
7811   "map": {"at": 197480, "to": "mm"},
7812   "name": "CP_DB_BUFSZ",
7813   "type_ref": "CP_DB_BUFSZ"
7814  },
7815  {
7816   "chips": ["gfx103"],
7817   "map": {"at": 197484, "to": "mm"},
7818   "name": "CP_DB_CMD_BUFSZ",
7819   "type_ref": "CP_DB_CMD_BUFSZ"
7820  },
7821  {
7822   "chips": ["gfx103"],
7823   "map": {"at": 197488, "to": "mm"},
7824   "name": "CP_CE_DB_BASE_LO",
7825   "type_ref": "CP_DB_BASE_LO"
7826  },
7827  {
7828   "chips": ["gfx103"],
7829   "map": {"at": 197492, "to": "mm"},
7830   "name": "CP_CE_DB_BASE_HI",
7831   "type_ref": "CP_DB_BASE_HI"
7832  },
7833  {
7834   "chips": ["gfx103"],
7835   "map": {"at": 197496, "to": "mm"},
7836   "name": "CP_CE_DB_BUFSZ",
7837   "type_ref": "CP_DB_BUFSZ"
7838  },
7839  {
7840   "chips": ["gfx103"],
7841   "map": {"at": 197500, "to": "mm"},
7842   "name": "CP_CE_DB_CMD_BUFSZ",
7843   "type_ref": "CP_DB_CMD_BUFSZ"
7844  },
7845  {
7846   "chips": ["gfx103"],
7847   "map": {"at": 197552, "to": "mm"},
7848   "name": "CP_PFP_COMPLETION_STATUS",
7849   "type_ref": "CP_PFP_COMPLETION_STATUS"
7850  },
7851  {
7852   "chips": ["gfx103"],
7853   "map": {"at": 197556, "to": "mm"},
7854   "name": "CP_CE_COMPLETION_STATUS",
7855   "type_ref": "CP_PFP_COMPLETION_STATUS"
7856  },
7857  {
7858   "chips": ["gfx103"],
7859   "map": {"at": 197560, "to": "mm"},
7860   "name": "CP_PRED_NOT_VISIBLE",
7861   "type_ref": "CP_PRED_NOT_VISIBLE"
7862  },
7863  {
7864   "chips": ["gfx103"],
7865   "map": {"at": 197568, "to": "mm"},
7866   "name": "CP_PFP_METADATA_BASE_ADDR",
7867   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7868  },
7869  {
7870   "chips": ["gfx103"],
7871   "map": {"at": 197572, "to": "mm"},
7872   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7873   "type_ref": "CP_EOP_DONE_ADDR_HI"
7874  },
7875  {
7876   "chips": ["gfx103"],
7877   "map": {"at": 197576, "to": "mm"},
7878   "name": "CP_CE_METADATA_BASE_ADDR",
7879   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7880  },
7881  {
7882   "chips": ["gfx103"],
7883   "map": {"at": 197580, "to": "mm"},
7884   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7885   "type_ref": "CP_EOP_DONE_ADDR_HI"
7886  },
7887  {
7888   "chips": ["gfx103"],
7889   "map": {"at": 197584, "to": "mm"},
7890   "name": "CP_DRAW_INDX_INDR_ADDR",
7891   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7892  },
7893  {
7894   "chips": ["gfx103"],
7895   "map": {"at": 197588, "to": "mm"},
7896   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7897   "type_ref": "CP_EOP_DONE_ADDR_HI"
7898  },
7899  {
7900   "chips": ["gfx103"],
7901   "map": {"at": 197592, "to": "mm"},
7902   "name": "CP_DISPATCH_INDR_ADDR",
7903   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7904  },
7905  {
7906   "chips": ["gfx103"],
7907   "map": {"at": 197596, "to": "mm"},
7908   "name": "CP_DISPATCH_INDR_ADDR_HI",
7909   "type_ref": "CP_EOP_DONE_ADDR_HI"
7910  },
7911  {
7912   "chips": ["gfx103"],
7913   "map": {"at": 197600, "to": "mm"},
7914   "name": "CP_INDEX_BASE_ADDR",
7915   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7916  },
7917  {
7918   "chips": ["gfx103"],
7919   "map": {"at": 197604, "to": "mm"},
7920   "name": "CP_INDEX_BASE_ADDR_HI",
7921   "type_ref": "CP_EOP_DONE_ADDR_HI"
7922  },
7923  {
7924   "chips": ["gfx103"],
7925   "map": {"at": 197608, "to": "mm"},
7926   "name": "CP_INDEX_TYPE",
7927   "type_ref": "CP_INDEX_TYPE"
7928  },
7929  {
7930   "chips": ["gfx103"],
7931   "map": {"at": 197612, "to": "mm"},
7932   "name": "CP_GDS_BKUP_ADDR",
7933   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7934  },
7935  {
7936   "chips": ["gfx103"],
7937   "map": {"at": 197616, "to": "mm"},
7938   "name": "CP_GDS_BKUP_ADDR_HI",
7939   "type_ref": "CP_EOP_DONE_ADDR_HI"
7940  },
7941  {
7942   "chips": ["gfx103"],
7943   "map": {"at": 197620, "to": "mm"},
7944   "name": "CP_SAMPLE_STATUS",
7945   "type_ref": "CP_SAMPLE_STATUS"
7946  },
7947  {
7948   "chips": ["gfx103"],
7949   "map": {"at": 197624, "to": "mm"},
7950   "name": "CP_ME_COHER_CNTL",
7951   "type_ref": "CP_ME_COHER_CNTL"
7952  },
7953  {
7954   "chips": ["gfx103"],
7955   "map": {"at": 197628, "to": "mm"},
7956   "name": "CP_ME_COHER_SIZE",
7957   "type_ref": "CP_COHER_SIZE"
7958  },
7959  {
7960   "chips": ["gfx103"],
7961   "map": {"at": 197632, "to": "mm"},
7962   "name": "CP_ME_COHER_SIZE_HI",
7963   "type_ref": "CP_COHER_SIZE_HI"
7964  },
7965  {
7966   "chips": ["gfx103"],
7967   "map": {"at": 197636, "to": "mm"},
7968   "name": "CP_ME_COHER_BASE",
7969   "type_ref": "CP_COHER_BASE"
7970  },
7971  {
7972   "chips": ["gfx103"],
7973   "map": {"at": 197640, "to": "mm"},
7974   "name": "CP_ME_COHER_BASE_HI",
7975   "type_ref": "CP_COHER_BASE_HI"
7976  },
7977  {
7978   "chips": ["gfx103"],
7979   "map": {"at": 197644, "to": "mm"},
7980   "name": "CP_ME_COHER_STATUS",
7981   "type_ref": "CP_ME_COHER_STATUS"
7982  },
7983  {
7984   "chips": ["gfx103"],
7985   "map": {"at": 197888, "to": "mm"},
7986   "name": "RLC_GPM_PERF_COUNT_0",
7987   "type_ref": "RLC_GPM_PERF_COUNT_0"
7988  },
7989  {
7990   "chips": ["gfx103"],
7991   "map": {"at": 197892, "to": "mm"},
7992   "name": "RLC_GPM_PERF_COUNT_1",
7993   "type_ref": "RLC_GPM_PERF_COUNT_0"
7994  },
7995  {
7996   "chips": ["gfx103"],
7997   "map": {"at": 198656, "to": "mm"},
7998   "name": "GRBM_GFX_INDEX",
7999   "type_ref": "GRBM_GFX_INDEX"
8000  },
8001  {
8002   "chips": ["gfx103"],
8003   "map": {"at": 198912, "to": "mm"},
8004   "name": "VGT_ESGS_RING_SIZE_UMD",
8005   "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8006  },
8007  {
8008   "chips": ["gfx103"],
8009   "map": {"at": 198916, "to": "mm"},
8010   "name": "VGT_GSVS_RING_SIZE_UMD",
8011   "type_ref": "VGT_ESGS_RING_SIZE_UMD"
8012  },
8013  {
8014   "chips": ["gfx103"],
8015   "map": {"at": 198920, "to": "mm"},
8016   "name": "VGT_PRIMITIVE_TYPE",
8017   "type_ref": "VGT_PRIMITIVE_TYPE"
8018  },
8019  {
8020   "chips": ["gfx103"],
8021   "map": {"at": 198924, "to": "mm"},
8022   "name": "VGT_INDEX_TYPE",
8023   "type_ref": "VGT_INDEX_TYPE"
8024  },
8025  {
8026   "chips": ["gfx103"],
8027   "map": {"at": 198928, "to": "mm"},
8028   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0",
8029   "type_ref": "COMPUTE_DIM_X"
8030  },
8031  {
8032   "chips": ["gfx103"],
8033   "map": {"at": 198932, "to": "mm"},
8034   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1",
8035   "type_ref": "COMPUTE_DIM_X"
8036  },
8037  {
8038   "chips": ["gfx103"],
8039   "map": {"at": 198936, "to": "mm"},
8040   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2",
8041   "type_ref": "COMPUTE_DIM_X"
8042  },
8043  {
8044   "chips": ["gfx103"],
8045   "map": {"at": 198940, "to": "mm"},
8046   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3",
8047   "type_ref": "COMPUTE_DIM_X"
8048  },
8049  {
8050   "chips": ["gfx103"],
8051   "map": {"at": 198948, "to": "mm"},
8052   "name": "GE_MIN_VTX_INDX",
8053   "type_ref": "VGT_MIN_VTX_INDX"
8054  },
8055  {
8056   "chips": ["gfx103"],
8057   "map": {"at": 198952, "to": "mm"},
8058   "name": "GE_INDX_OFFSET",
8059   "type_ref": "VGT_INDX_OFFSET"
8060  },
8061  {
8062   "chips": ["gfx103"],
8063   "map": {"at": 198956, "to": "mm"},
8064   "name": "GE_MULTI_PRIM_IB_RESET_EN",
8065   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
8066  },
8067  {
8068   "chips": ["gfx103"],
8069   "map": {"at": 198960, "to": "mm"},
8070   "name": "VGT_NUM_INDICES",
8071   "type_ref": "VGT_DMA_SIZE"
8072  },
8073  {
8074   "chips": ["gfx103"],
8075   "map": {"at": 198964, "to": "mm"},
8076   "name": "VGT_NUM_INSTANCES",
8077   "type_ref": "VGT_DMA_NUM_INSTANCES"
8078  },
8079  {
8080   "chips": ["gfx103"],
8081   "map": {"at": 198968, "to": "mm"},
8082   "name": "VGT_TF_RING_SIZE_UMD",
8083   "type_ref": "VGT_TF_RING_SIZE_UMD"
8084  },
8085  {
8086   "chips": ["gfx103"],
8087   "map": {"at": 198972, "to": "mm"},
8088   "name": "VGT_HS_OFFCHIP_PARAM_UMD",
8089   "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD"
8090  },
8091  {
8092   "chips": ["gfx103"],
8093   "map": {"at": 198976, "to": "mm"},
8094   "name": "VGT_TF_MEMORY_BASE_UMD",
8095   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8096  },
8097  {
8098   "chips": ["gfx103"],
8099   "map": {"at": 198980, "to": "mm"},
8100   "name": "GE_DMA_FIRST_INDEX",
8101   "type_ref": "GE_DMA_FIRST_INDEX"
8102  },
8103  {
8104   "chips": ["gfx103"],
8105   "map": {"at": 198984, "to": "mm"},
8106   "name": "WD_POS_BUF_BASE",
8107   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8108  },
8109  {
8110   "chips": ["gfx103"],
8111   "map": {"at": 198988, "to": "mm"},
8112   "name": "WD_POS_BUF_BASE_HI",
8113   "type_ref": "DB_Z_READ_BASE_HI"
8114  },
8115  {
8116   "chips": ["gfx103"],
8117   "map": {"at": 198992, "to": "mm"},
8118   "name": "WD_CNTL_SB_BUF_BASE",
8119   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8120  },
8121  {
8122   "chips": ["gfx103"],
8123   "map": {"at": 198996, "to": "mm"},
8124   "name": "WD_CNTL_SB_BUF_BASE_HI",
8125   "type_ref": "DB_Z_READ_BASE_HI"
8126  },
8127  {
8128   "chips": ["gfx103"],
8129   "map": {"at": 199000, "to": "mm"},
8130   "name": "WD_INDEX_BUF_BASE",
8131   "type_ref": "VGT_TF_MEMORY_BASE_UMD"
8132  },
8133  {
8134   "chips": ["gfx103"],
8135   "map": {"at": 199004, "to": "mm"},
8136   "name": "WD_INDEX_BUF_BASE_HI",
8137   "type_ref": "DB_Z_READ_BASE_HI"
8138  },
8139  {
8140   "chips": ["gfx103"],
8141   "map": {"at": 199008, "to": "mm"},
8142   "name": "IA_MULTI_VGT_PARAM_PIPED",
8143   "type_ref": "IA_MULTI_VGT_PARAM_PIPED"
8144  },
8145  {
8146   "chips": ["gfx103"],
8147   "map": {"at": 199012, "to": "mm"},
8148   "name": "GE_MAX_VTX_INDX",
8149   "type_ref": "VGT_MAX_VTX_INDX"
8150  },
8151  {
8152   "chips": ["gfx103"],
8153   "map": {"at": 199016, "to": "mm"},
8154   "name": "VGT_INSTANCE_BASE_ID",
8155   "type_ref": "VGT_INSTANCE_BASE_ID"
8156  },
8157  {
8158   "chips": ["gfx103"],
8159   "map": {"at": 199020, "to": "mm"},
8160   "name": "GE_CNTL",
8161   "type_ref": "GE_CNTL"
8162  },
8163  {
8164   "chips": ["gfx103"],
8165   "map": {"at": 199024, "to": "mm"},
8166   "name": "GE_USER_VGPR1",
8167   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8168  },
8169  {
8170   "chips": ["gfx103"],
8171   "map": {"at": 199028, "to": "mm"},
8172   "name": "GE_USER_VGPR2",
8173   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8174  },
8175  {
8176   "chips": ["gfx103"],
8177   "map": {"at": 199032, "to": "mm"},
8178   "name": "GE_USER_VGPR3",
8179   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8180  },
8181  {
8182   "chips": ["gfx103"],
8183   "map": {"at": 199036, "to": "mm"},
8184   "name": "GE_STEREO_CNTL",
8185   "type_ref": "GE_STEREO_CNTL"
8186  },
8187  {
8188   "chips": ["gfx103"],
8189   "map": {"at": 199040, "to": "mm"},
8190   "name": "GE_PC_ALLOC",
8191   "type_ref": "GE_PC_ALLOC"
8192  },
8193  {
8194   "chips": ["gfx103"],
8195   "map": {"at": 199044, "to": "mm"},
8196   "name": "VGT_TF_MEMORY_BASE_HI_UMD",
8197   "type_ref": "DB_Z_READ_BASE_HI"
8198  },
8199  {
8200   "chips": ["gfx103"],
8201   "map": {"at": 199048, "to": "mm"},
8202   "name": "GE_USER_VGPR_EN",
8203   "type_ref": "GE_USER_VGPR_EN"
8204  },
8205  {
8206   "chips": ["gfx103"],
8207   "map": {"at": 199168, "to": "mm"},
8208   "name": "PA_SU_LINE_STIPPLE_VALUE",
8209   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
8210  },
8211  {
8212   "chips": ["gfx103"],
8213   "map": {"at": 199172, "to": "mm"},
8214   "name": "PA_SC_LINE_STIPPLE_STATE",
8215   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
8216  },
8217  {
8218   "chips": ["gfx103"],
8219   "map": {"at": 199184, "to": "mm"},
8220   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
8221   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8222  },
8223  {
8224   "chips": ["gfx103"],
8225   "map": {"at": 199188, "to": "mm"},
8226   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
8227   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8228  },
8229  {
8230   "chips": ["gfx103"],
8231   "map": {"at": 199192, "to": "mm"},
8232   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
8233   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8234  },
8235  {
8236   "chips": ["gfx103"],
8237   "map": {"at": 199212, "to": "mm"},
8238   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
8239   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
8240  },
8241  {
8242   "chips": ["gfx103"],
8243   "map": {"at": 199296, "to": "mm"},
8244   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
8245   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8246  },
8247  {
8248   "chips": ["gfx103"],
8249   "map": {"at": 199300, "to": "mm"},
8250   "name": "PA_SC_P3D_TRAP_SCREEN_H",
8251   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8252  },
8253  {
8254   "chips": ["gfx103"],
8255   "map": {"at": 199304, "to": "mm"},
8256   "name": "PA_SC_P3D_TRAP_SCREEN_V",
8257   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8258  },
8259  {
8260   "chips": ["gfx103"],
8261   "map": {"at": 199308, "to": "mm"},
8262   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
8263   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8264  },
8265  {
8266   "chips": ["gfx103"],
8267   "map": {"at": 199312, "to": "mm"},
8268   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
8269   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8270  },
8271  {
8272   "chips": ["gfx103"],
8273   "map": {"at": 199328, "to": "mm"},
8274   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
8275   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8276  },
8277  {
8278   "chips": ["gfx103"],
8279   "map": {"at": 199332, "to": "mm"},
8280   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
8281   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8282  },
8283  {
8284   "chips": ["gfx103"],
8285   "map": {"at": 199336, "to": "mm"},
8286   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
8287   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8288  },
8289  {
8290   "chips": ["gfx103"],
8291   "map": {"at": 199340, "to": "mm"},
8292   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
8293   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8294  },
8295  {
8296   "chips": ["gfx103"],
8297   "map": {"at": 199344, "to": "mm"},
8298   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
8299   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8300  },
8301  {
8302   "chips": ["gfx103"],
8303   "map": {"at": 199360, "to": "mm"},
8304   "name": "PA_SC_TRAP_SCREEN_HV_EN",
8305   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
8306  },
8307  {
8308   "chips": ["gfx103"],
8309   "map": {"at": 199364, "to": "mm"},
8310   "name": "PA_SC_TRAP_SCREEN_H",
8311   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
8312  },
8313  {
8314   "chips": ["gfx103"],
8315   "map": {"at": 199368, "to": "mm"},
8316   "name": "PA_SC_TRAP_SCREEN_V",
8317   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
8318  },
8319  {
8320   "chips": ["gfx103"],
8321   "map": {"at": 199372, "to": "mm"},
8322   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
8323   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8324  },
8325  {
8326   "chips": ["gfx103"],
8327   "map": {"at": 199376, "to": "mm"},
8328   "name": "PA_SC_TRAP_SCREEN_COUNT",
8329   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8330  },
8331  {
8332   "chips": ["gfx103"],
8333   "map": {"at": 199936, "to": "mm"},
8334   "name": "SQ_THREAD_TRACE_USERDATA_0",
8335   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8336  },
8337  {
8338   "chips": ["gfx103"],
8339   "map": {"at": 199940, "to": "mm"},
8340   "name": "SQ_THREAD_TRACE_USERDATA_1",
8341   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8342  },
8343  {
8344   "chips": ["gfx103"],
8345   "map": {"at": 199944, "to": "mm"},
8346   "name": "SQ_THREAD_TRACE_USERDATA_2",
8347   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8348  },
8349  {
8350   "chips": ["gfx103"],
8351   "map": {"at": 199948, "to": "mm"},
8352   "name": "SQ_THREAD_TRACE_USERDATA_3",
8353   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8354  },
8355  {
8356   "chips": ["gfx103"],
8357   "map": {"at": 199952, "to": "mm"},
8358   "name": "SQ_THREAD_TRACE_USERDATA_4",
8359   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8360  },
8361  {
8362   "chips": ["gfx103"],
8363   "map": {"at": 199956, "to": "mm"},
8364   "name": "SQ_THREAD_TRACE_USERDATA_5",
8365   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8366  },
8367  {
8368   "chips": ["gfx103"],
8369   "map": {"at": 199960, "to": "mm"},
8370   "name": "SQ_THREAD_TRACE_USERDATA_6",
8371   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8372  },
8373  {
8374   "chips": ["gfx103"],
8375   "map": {"at": 199964, "to": "mm"},
8376   "name": "SQ_THREAD_TRACE_USERDATA_7",
8377   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8378  },
8379  {
8380   "chips": ["gfx103"],
8381   "map": {"at": 199968, "to": "mm"},
8382   "name": "SQC_CACHES",
8383   "type_ref": "SQC_CACHES"
8384  },
8385  {
8386   "chips": ["gfx103"],
8387   "map": {"at": 200192, "to": "mm"},
8388   "name": "TA_CS_BC_BASE_ADDR",
8389   "type_ref": "TA_BC_BASE_ADDR"
8390  },
8391  {
8392   "chips": ["gfx103"],
8393   "map": {"at": 200196, "to": "mm"},
8394   "name": "TA_CS_BC_BASE_ADDR_HI",
8395   "type_ref": "TA_BC_BASE_ADDR_HI"
8396  },
8397  {
8398   "chips": ["gfx103"],
8399   "map": {"at": 200448, "to": "mm"},
8400   "name": "DB_OCCLUSION_COUNT0_LOW",
8401   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
8402  },
8403  {
8404   "chips": ["gfx103"],
8405   "map": {"at": 200452, "to": "mm"},
8406   "name": "DB_OCCLUSION_COUNT0_HI",
8407   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8408  },
8409  {
8410   "chips": ["gfx103"],
8411   "map": {"at": 200456, "to": "mm"},
8412   "name": "DB_OCCLUSION_COUNT1_LOW",
8413   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
8414  },
8415  {
8416   "chips": ["gfx103"],
8417   "map": {"at": 200460, "to": "mm"},
8418   "name": "DB_OCCLUSION_COUNT1_HI",
8419   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8420  },
8421  {
8422   "chips": ["gfx103"],
8423   "map": {"at": 200464, "to": "mm"},
8424   "name": "DB_OCCLUSION_COUNT2_LOW",
8425   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
8426  },
8427  {
8428   "chips": ["gfx103"],
8429   "map": {"at": 200468, "to": "mm"},
8430   "name": "DB_OCCLUSION_COUNT2_HI",
8431   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8432  },
8433  {
8434   "chips": ["gfx103"],
8435   "map": {"at": 200472, "to": "mm"},
8436   "name": "DB_OCCLUSION_COUNT3_LOW",
8437   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
8438  },
8439  {
8440   "chips": ["gfx103"],
8441   "map": {"at": 200476, "to": "mm"},
8442   "name": "DB_OCCLUSION_COUNT3_HI",
8443   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8444  },
8445  {
8446   "chips": ["gfx103"],
8447   "map": {"at": 200696, "to": "mm"},
8448   "name": "DB_ZPASS_COUNT_LOW",
8449   "type_ref": "DB_OCCLUSION_COUNT0_LOW"
8450  },
8451  {
8452   "chips": ["gfx103"],
8453   "map": {"at": 200700, "to": "mm"},
8454   "name": "DB_ZPASS_COUNT_HI",
8455   "type_ref": "DB_OCCLUSION_COUNT0_HI"
8456  },
8457  {
8458   "chips": ["gfx103"],
8459   "map": {"at": 200704, "to": "mm"},
8460   "name": "GDS_RD_ADDR",
8461   "type_ref": "GDS_RD_ADDR"
8462  },
8463  {
8464   "chips": ["gfx103"],
8465   "map": {"at": 200708, "to": "mm"},
8466   "name": "GDS_RD_DATA",
8467   "type_ref": "GDS_RD_DATA"
8468  },
8469  {
8470   "chips": ["gfx103"],
8471   "map": {"at": 200712, "to": "mm"},
8472   "name": "GDS_RD_BURST_ADDR",
8473   "type_ref": "GDS_RD_BURST_ADDR"
8474  },
8475  {
8476   "chips": ["gfx103"],
8477   "map": {"at": 200716, "to": "mm"},
8478   "name": "GDS_RD_BURST_COUNT",
8479   "type_ref": "GDS_RD_BURST_COUNT"
8480  },
8481  {
8482   "chips": ["gfx103"],
8483   "map": {"at": 200720, "to": "mm"},
8484   "name": "GDS_RD_BURST_DATA",
8485   "type_ref": "GDS_RD_BURST_DATA"
8486  },
8487  {
8488   "chips": ["gfx103"],
8489   "map": {"at": 200724, "to": "mm"},
8490   "name": "GDS_WR_ADDR",
8491   "type_ref": "GDS_WR_ADDR"
8492  },
8493  {
8494   "chips": ["gfx103"],
8495   "map": {"at": 200728, "to": "mm"},
8496   "name": "GDS_WR_DATA",
8497   "type_ref": "GDS_WR_DATA"
8498  },
8499  {
8500   "chips": ["gfx103"],
8501   "map": {"at": 200732, "to": "mm"},
8502   "name": "GDS_WR_BURST_ADDR",
8503   "type_ref": "GDS_WR_ADDR"
8504  },
8505  {
8506   "chips": ["gfx103"],
8507   "map": {"at": 200736, "to": "mm"},
8508   "name": "GDS_WR_BURST_DATA",
8509   "type_ref": "GDS_WR_DATA"
8510  },
8511  {
8512   "chips": ["gfx103"],
8513   "map": {"at": 200740, "to": "mm"},
8514   "name": "GDS_WRITE_COMPLETE",
8515   "type_ref": "GDS_WRITE_COMPLETE"
8516  },
8517  {
8518   "chips": ["gfx103"],
8519   "map": {"at": 200744, "to": "mm"},
8520   "name": "GDS_ATOM_CNTL",
8521   "type_ref": "GDS_ATOM_CNTL"
8522  },
8523  {
8524   "chips": ["gfx103"],
8525   "map": {"at": 200748, "to": "mm"},
8526   "name": "GDS_ATOM_COMPLETE",
8527   "type_ref": "GDS_ATOM_COMPLETE"
8528  },
8529  {
8530   "chips": ["gfx103"],
8531   "map": {"at": 200752, "to": "mm"},
8532   "name": "GDS_ATOM_BASE",
8533   "type_ref": "GDS_ATOM_BASE"
8534  },
8535  {
8536   "chips": ["gfx103"],
8537   "map": {"at": 200756, "to": "mm"},
8538   "name": "GDS_ATOM_SIZE",
8539   "type_ref": "GDS_ATOM_SIZE"
8540  },
8541  {
8542   "chips": ["gfx103"],
8543   "map": {"at": 200760, "to": "mm"},
8544   "name": "GDS_ATOM_OFFSET0",
8545   "type_ref": "GDS_ATOM_OFFSET0"
8546  },
8547  {
8548   "chips": ["gfx103"],
8549   "map": {"at": 200764, "to": "mm"},
8550   "name": "GDS_ATOM_OFFSET1",
8551   "type_ref": "GDS_ATOM_OFFSET1"
8552  },
8553  {
8554   "chips": ["gfx103"],
8555   "map": {"at": 200768, "to": "mm"},
8556   "name": "GDS_ATOM_DST",
8557   "type_ref": "GDS_ATOM_DST"
8558  },
8559  {
8560   "chips": ["gfx103"],
8561   "map": {"at": 200772, "to": "mm"},
8562   "name": "GDS_ATOM_OP",
8563   "type_ref": "GDS_ATOM_OP"
8564  },
8565  {
8566   "chips": ["gfx103"],
8567   "map": {"at": 200776, "to": "mm"},
8568   "name": "GDS_ATOM_SRC0",
8569   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8570  },
8571  {
8572   "chips": ["gfx103"],
8573   "map": {"at": 200780, "to": "mm"},
8574   "name": "GDS_ATOM_SRC0_U",
8575   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8576  },
8577  {
8578   "chips": ["gfx103"],
8579   "map": {"at": 200784, "to": "mm"},
8580   "name": "GDS_ATOM_SRC1",
8581   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8582  },
8583  {
8584   "chips": ["gfx103"],
8585   "map": {"at": 200788, "to": "mm"},
8586   "name": "GDS_ATOM_SRC1_U",
8587   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8588  },
8589  {
8590   "chips": ["gfx103"],
8591   "map": {"at": 200792, "to": "mm"},
8592   "name": "GDS_ATOM_READ0",
8593   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8594  },
8595  {
8596   "chips": ["gfx103"],
8597   "map": {"at": 200796, "to": "mm"},
8598   "name": "GDS_ATOM_READ0_U",
8599   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8600  },
8601  {
8602   "chips": ["gfx103"],
8603   "map": {"at": 200800, "to": "mm"},
8604   "name": "GDS_ATOM_READ1",
8605   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8606  },
8607  {
8608   "chips": ["gfx103"],
8609   "map": {"at": 200804, "to": "mm"},
8610   "name": "GDS_ATOM_READ1_U",
8611   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8612  },
8613  {
8614   "chips": ["gfx103"],
8615   "map": {"at": 200808, "to": "mm"},
8616   "name": "GDS_GWS_RESOURCE_CNTL",
8617   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8618  },
8619  {
8620   "chips": ["gfx103"],
8621   "map": {"at": 200812, "to": "mm"},
8622   "name": "GDS_GWS_RESOURCE",
8623   "type_ref": "GDS_GWS_RESOURCE"
8624  },
8625  {
8626   "chips": ["gfx103"],
8627   "map": {"at": 200816, "to": "mm"},
8628   "name": "GDS_GWS_RESOURCE_CNT",
8629   "type_ref": "GDS_GWS_RESOURCE_CNT"
8630  },
8631  {
8632   "chips": ["gfx103"],
8633   "map": {"at": 200820, "to": "mm"},
8634   "name": "GDS_OA_CNTL",
8635   "type_ref": "GDS_OA_CNTL"
8636  },
8637  {
8638   "chips": ["gfx103"],
8639   "map": {"at": 200824, "to": "mm"},
8640   "name": "GDS_OA_COUNTER",
8641   "type_ref": "GDS_OA_COUNTER"
8642  },
8643  {
8644   "chips": ["gfx103"],
8645   "map": {"at": 200828, "to": "mm"},
8646   "name": "GDS_OA_ADDRESS",
8647   "type_ref": "GDS_OA_ADDRESS"
8648  },
8649  {
8650   "chips": ["gfx103"],
8651   "map": {"at": 200832, "to": "mm"},
8652   "name": "GDS_OA_INCDEC",
8653   "type_ref": "GDS_OA_INCDEC"
8654  },
8655  {
8656   "chips": ["gfx103"],
8657   "map": {"at": 200836, "to": "mm"},
8658   "name": "GDS_OA_RING_SIZE",
8659   "type_ref": "GDS_OA_RING_SIZE"
8660  },
8661  {
8662   "chips": ["gfx103"],
8663   "map": {"at": 200960, "to": "mm"},
8664   "name": "SPI_CONFIG_CNTL_REMAP",
8665   "type_ref": "SPI_CONFIG_CNTL_REMAP"
8666  },
8667  {
8668   "chips": ["gfx103"],
8669   "map": {"at": 200964, "to": "mm"},
8670   "name": "SPI_CONFIG_CNTL_1_REMAP",
8671   "type_ref": "SPI_CONFIG_CNTL_REMAP"
8672  },
8673  {
8674   "chips": ["gfx103"],
8675   "map": {"at": 200968, "to": "mm"},
8676   "name": "SPI_CONFIG_CNTL_2_REMAP",
8677   "type_ref": "SPI_CONFIG_CNTL_REMAP"
8678  },
8679  {
8680   "chips": ["gfx103"],
8681   "map": {"at": 200972, "to": "mm"},
8682   "name": "SPI_WAVE_LIMIT_CNTL_REMAP",
8683   "type_ref": "SPI_CONFIG_CNTL_REMAP"
8684  },
8685  {
8686   "chips": ["gfx103"],
8687   "map": {"at": 212992, "to": "mm"},
8688   "name": "CPG_PERFCOUNTER1_LO",
8689   "type_ref": "CPG_PERFCOUNTER1_LO"
8690  },
8691  {
8692   "chips": ["gfx103"],
8693   "map": {"at": 212996, "to": "mm"},
8694   "name": "CPG_PERFCOUNTER1_HI",
8695   "type_ref": "CPG_PERFCOUNTER1_HI"
8696  },
8697  {
8698   "chips": ["gfx103"],
8699   "map": {"at": 213000, "to": "mm"},
8700   "name": "CPG_PERFCOUNTER0_LO",
8701   "type_ref": "CPG_PERFCOUNTER1_LO"
8702  },
8703  {
8704   "chips": ["gfx103"],
8705   "map": {"at": 213004, "to": "mm"},
8706   "name": "CPG_PERFCOUNTER0_HI",
8707   "type_ref": "CPG_PERFCOUNTER1_HI"
8708  },
8709  {
8710   "chips": ["gfx103"],
8711   "map": {"at": 213008, "to": "mm"},
8712   "name": "CPC_PERFCOUNTER1_LO",
8713   "type_ref": "CPG_PERFCOUNTER1_LO"
8714  },
8715  {
8716   "chips": ["gfx103"],
8717   "map": {"at": 213012, "to": "mm"},
8718   "name": "CPC_PERFCOUNTER1_HI",
8719   "type_ref": "CPG_PERFCOUNTER1_HI"
8720  },
8721  {
8722   "chips": ["gfx103"],
8723   "map": {"at": 213016, "to": "mm"},
8724   "name": "CPC_PERFCOUNTER0_LO",
8725   "type_ref": "CPG_PERFCOUNTER1_LO"
8726  },
8727  {
8728   "chips": ["gfx103"],
8729   "map": {"at": 213020, "to": "mm"},
8730   "name": "CPC_PERFCOUNTER0_HI",
8731   "type_ref": "CPG_PERFCOUNTER1_HI"
8732  },
8733  {
8734   "chips": ["gfx103"],
8735   "map": {"at": 213024, "to": "mm"},
8736   "name": "CPF_PERFCOUNTER1_LO",
8737   "type_ref": "CPG_PERFCOUNTER1_LO"
8738  },
8739  {
8740   "chips": ["gfx103"],
8741   "map": {"at": 213028, "to": "mm"},
8742   "name": "CPF_PERFCOUNTER1_HI",
8743   "type_ref": "CPG_PERFCOUNTER1_HI"
8744  },
8745  {
8746   "chips": ["gfx103"],
8747   "map": {"at": 213032, "to": "mm"},
8748   "name": "CPF_PERFCOUNTER0_LO",
8749   "type_ref": "CPG_PERFCOUNTER1_LO"
8750  },
8751  {
8752   "chips": ["gfx103"],
8753   "map": {"at": 213036, "to": "mm"},
8754   "name": "CPF_PERFCOUNTER0_HI",
8755   "type_ref": "CPG_PERFCOUNTER1_HI"
8756  },
8757  {
8758   "chips": ["gfx103"],
8759   "map": {"at": 213040, "to": "mm"},
8760   "name": "CPF_LATENCY_STATS_DATA",
8761   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8762  },
8763  {
8764   "chips": ["gfx103"],
8765   "map": {"at": 213044, "to": "mm"},
8766   "name": "CPG_LATENCY_STATS_DATA",
8767   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8768  },
8769  {
8770   "chips": ["gfx103"],
8771   "map": {"at": 213048, "to": "mm"},
8772   "name": "CPC_LATENCY_STATS_DATA",
8773   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
8774  },
8775  {
8776   "chips": ["gfx103"],
8777   "map": {"at": 213248, "to": "mm"},
8778   "name": "GRBM_PERFCOUNTER0_LO",
8779   "type_ref": "CPG_PERFCOUNTER1_LO"
8780  },
8781  {
8782   "chips": ["gfx103"],
8783   "map": {"at": 213252, "to": "mm"},
8784   "name": "GRBM_PERFCOUNTER0_HI",
8785   "type_ref": "CPG_PERFCOUNTER1_HI"
8786  },
8787  {
8788   "chips": ["gfx103"],
8789   "map": {"at": 213260, "to": "mm"},
8790   "name": "GRBM_PERFCOUNTER1_LO",
8791   "type_ref": "CPG_PERFCOUNTER1_LO"
8792  },
8793  {
8794   "chips": ["gfx103"],
8795   "map": {"at": 213264, "to": "mm"},
8796   "name": "GRBM_PERFCOUNTER1_HI",
8797   "type_ref": "CPG_PERFCOUNTER1_HI"
8798  },
8799  {
8800   "chips": ["gfx103"],
8801   "map": {"at": 213268, "to": "mm"},
8802   "name": "GRBM_SE0_PERFCOUNTER_LO",
8803   "type_ref": "CPG_PERFCOUNTER1_LO"
8804  },
8805  {
8806   "chips": ["gfx103"],
8807   "map": {"at": 213272, "to": "mm"},
8808   "name": "GRBM_SE0_PERFCOUNTER_HI",
8809   "type_ref": "CPG_PERFCOUNTER1_HI"
8810  },
8811  {
8812   "chips": ["gfx103"],
8813   "map": {"at": 213276, "to": "mm"},
8814   "name": "GRBM_SE1_PERFCOUNTER_LO",
8815   "type_ref": "CPG_PERFCOUNTER1_LO"
8816  },
8817  {
8818   "chips": ["gfx103"],
8819   "map": {"at": 213280, "to": "mm"},
8820   "name": "GRBM_SE1_PERFCOUNTER_HI",
8821   "type_ref": "CPG_PERFCOUNTER1_HI"
8822  },
8823  {
8824   "chips": ["gfx103"],
8825   "map": {"at": 213284, "to": "mm"},
8826   "name": "GRBM_SE2_PERFCOUNTER_LO",
8827   "type_ref": "CPG_PERFCOUNTER1_LO"
8828  },
8829  {
8830   "chips": ["gfx103"],
8831   "map": {"at": 213288, "to": "mm"},
8832   "name": "GRBM_SE2_PERFCOUNTER_HI",
8833   "type_ref": "CPG_PERFCOUNTER1_HI"
8834  },
8835  {
8836   "chips": ["gfx103"],
8837   "map": {"at": 213292, "to": "mm"},
8838   "name": "GRBM_SE3_PERFCOUNTER_LO",
8839   "type_ref": "CPG_PERFCOUNTER1_LO"
8840  },
8841  {
8842   "chips": ["gfx103"],
8843   "map": {"at": 213296, "to": "mm"},
8844   "name": "GRBM_SE3_PERFCOUNTER_HI",
8845   "type_ref": "CPG_PERFCOUNTER1_HI"
8846  },
8847  {
8848   "chips": ["gfx103"],
8849   "map": {"at": 213648, "to": "mm"},
8850   "name": "GE1_PERFCOUNTER0_LO",
8851   "type_ref": "CPG_PERFCOUNTER1_LO"
8852  },
8853  {
8854   "chips": ["gfx103"],
8855   "map": {"at": 213652, "to": "mm"},
8856   "name": "GE1_PERFCOUNTER0_HI",
8857   "type_ref": "CPG_PERFCOUNTER1_HI"
8858  },
8859  {
8860   "chips": ["gfx103"],
8861   "map": {"at": 213656, "to": "mm"},
8862   "name": "GE1_PERFCOUNTER1_LO",
8863   "type_ref": "CPG_PERFCOUNTER1_LO"
8864  },
8865  {
8866   "chips": ["gfx103"],
8867   "map": {"at": 213660, "to": "mm"},
8868   "name": "GE1_PERFCOUNTER1_HI",
8869   "type_ref": "CPG_PERFCOUNTER1_HI"
8870  },
8871  {
8872   "chips": ["gfx103"],
8873   "map": {"at": 213664, "to": "mm"},
8874   "name": "GE1_PERFCOUNTER2_LO",
8875   "type_ref": "CPG_PERFCOUNTER1_LO"
8876  },
8877  {
8878   "chips": ["gfx103"],
8879   "map": {"at": 213668, "to": "mm"},
8880   "name": "GE1_PERFCOUNTER2_HI",
8881   "type_ref": "CPG_PERFCOUNTER1_HI"
8882  },
8883  {
8884   "chips": ["gfx103"],
8885   "map": {"at": 213672, "to": "mm"},
8886   "name": "GE1_PERFCOUNTER3_LO",
8887   "type_ref": "CPG_PERFCOUNTER1_LO"
8888  },
8889  {
8890   "chips": ["gfx103"],
8891   "map": {"at": 213676, "to": "mm"},
8892   "name": "GE1_PERFCOUNTER3_HI",
8893   "type_ref": "CPG_PERFCOUNTER1_HI"
8894  },
8895  {
8896   "chips": ["gfx103"],
8897   "map": {"at": 213680, "to": "mm"},
8898   "name": "GE2_DIST_PERFCOUNTER0_LO",
8899   "type_ref": "CPG_PERFCOUNTER1_LO"
8900  },
8901  {
8902   "chips": ["gfx103"],
8903   "map": {"at": 213684, "to": "mm"},
8904   "name": "GE2_DIST_PERFCOUNTER0_HI",
8905   "type_ref": "CPG_PERFCOUNTER1_HI"
8906  },
8907  {
8908   "chips": ["gfx103"],
8909   "map": {"at": 213688, "to": "mm"},
8910   "name": "GE2_DIST_PERFCOUNTER1_LO",
8911   "type_ref": "CPG_PERFCOUNTER1_LO"
8912  },
8913  {
8914   "chips": ["gfx103"],
8915   "map": {"at": 213692, "to": "mm"},
8916   "name": "GE2_DIST_PERFCOUNTER1_HI",
8917   "type_ref": "CPG_PERFCOUNTER1_HI"
8918  },
8919  {
8920   "chips": ["gfx103"],
8921   "map": {"at": 213696, "to": "mm"},
8922   "name": "GE2_DIST_PERFCOUNTER2_LO",
8923   "type_ref": "CPG_PERFCOUNTER1_LO"
8924  },
8925  {
8926   "chips": ["gfx103"],
8927   "map": {"at": 213700, "to": "mm"},
8928   "name": "GE2_DIST_PERFCOUNTER2_HI",
8929   "type_ref": "CPG_PERFCOUNTER1_HI"
8930  },
8931  {
8932   "chips": ["gfx103"],
8933   "map": {"at": 213704, "to": "mm"},
8934   "name": "GE2_DIST_PERFCOUNTER3_LO",
8935   "type_ref": "CPG_PERFCOUNTER1_LO"
8936  },
8937  {
8938   "chips": ["gfx103"],
8939   "map": {"at": 213708, "to": "mm"},
8940   "name": "GE2_DIST_PERFCOUNTER3_HI",
8941   "type_ref": "CPG_PERFCOUNTER1_HI"
8942  },
8943  {
8944   "chips": ["gfx103"],
8945   "map": {"at": 213712, "to": "mm"},
8946   "name": "GE2_SE_PERFCOUNTER0_LO",
8947   "type_ref": "CPG_PERFCOUNTER1_LO"
8948  },
8949  {
8950   "chips": ["gfx103"],
8951   "map": {"at": 213716, "to": "mm"},
8952   "name": "GE2_SE_PERFCOUNTER0_HI",
8953   "type_ref": "CPG_PERFCOUNTER1_HI"
8954  },
8955  {
8956   "chips": ["gfx103"],
8957   "map": {"at": 213720, "to": "mm"},
8958   "name": "GE2_SE_PERFCOUNTER1_LO",
8959   "type_ref": "CPG_PERFCOUNTER1_LO"
8960  },
8961  {
8962   "chips": ["gfx103"],
8963   "map": {"at": 213724, "to": "mm"},
8964   "name": "GE2_SE_PERFCOUNTER1_HI",
8965   "type_ref": "CPG_PERFCOUNTER1_HI"
8966  },
8967  {
8968   "chips": ["gfx103"],
8969   "map": {"at": 213728, "to": "mm"},
8970   "name": "GE2_SE_PERFCOUNTER2_LO",
8971   "type_ref": "CPG_PERFCOUNTER1_LO"
8972  },
8973  {
8974   "chips": ["gfx103"],
8975   "map": {"at": 213732, "to": "mm"},
8976   "name": "GE2_SE_PERFCOUNTER2_HI",
8977   "type_ref": "CPG_PERFCOUNTER1_HI"
8978  },
8979  {
8980   "chips": ["gfx103"],
8981   "map": {"at": 213736, "to": "mm"},
8982   "name": "GE2_SE_PERFCOUNTER3_LO",
8983   "type_ref": "CPG_PERFCOUNTER1_LO"
8984  },
8985  {
8986   "chips": ["gfx103"],
8987   "map": {"at": 213740, "to": "mm"},
8988   "name": "GE2_SE_PERFCOUNTER3_HI",
8989   "type_ref": "CPG_PERFCOUNTER1_HI"
8990  },
8991  {
8992   "chips": ["gfx103"],
8993   "map": {"at": 214016, "to": "mm"},
8994   "name": "PA_SU_PERFCOUNTER0_LO",
8995   "type_ref": "CPG_PERFCOUNTER1_LO"
8996  },
8997  {
8998   "chips": ["gfx103"],
8999   "map": {"at": 214020, "to": "mm"},
9000   "name": "PA_SU_PERFCOUNTER0_HI",
9001   "type_ref": "CPG_PERFCOUNTER1_HI"
9002  },
9003  {
9004   "chips": ["gfx103"],
9005   "map": {"at": 214024, "to": "mm"},
9006   "name": "PA_SU_PERFCOUNTER1_LO",
9007   "type_ref": "CPG_PERFCOUNTER1_LO"
9008  },
9009  {
9010   "chips": ["gfx103"],
9011   "map": {"at": 214028, "to": "mm"},
9012   "name": "PA_SU_PERFCOUNTER1_HI",
9013   "type_ref": "CPG_PERFCOUNTER1_HI"
9014  },
9015  {
9016   "chips": ["gfx103"],
9017   "map": {"at": 214032, "to": "mm"},
9018   "name": "PA_SU_PERFCOUNTER2_LO",
9019   "type_ref": "CPG_PERFCOUNTER1_LO"
9020  },
9021  {
9022   "chips": ["gfx103"],
9023   "map": {"at": 214036, "to": "mm"},
9024   "name": "PA_SU_PERFCOUNTER2_HI",
9025   "type_ref": "CPG_PERFCOUNTER1_HI"
9026  },
9027  {
9028   "chips": ["gfx103"],
9029   "map": {"at": 214040, "to": "mm"},
9030   "name": "PA_SU_PERFCOUNTER3_LO",
9031   "type_ref": "CPG_PERFCOUNTER1_LO"
9032  },
9033  {
9034   "chips": ["gfx103"],
9035   "map": {"at": 214044, "to": "mm"},
9036   "name": "PA_SU_PERFCOUNTER3_HI",
9037   "type_ref": "CPG_PERFCOUNTER1_HI"
9038  },
9039  {
9040   "chips": ["gfx103"],
9041   "map": {"at": 214272, "to": "mm"},
9042   "name": "PA_SC_PERFCOUNTER0_LO",
9043   "type_ref": "CPG_PERFCOUNTER1_LO"
9044  },
9045  {
9046   "chips": ["gfx103"],
9047   "map": {"at": 214276, "to": "mm"},
9048   "name": "PA_SC_PERFCOUNTER0_HI",
9049   "type_ref": "CPG_PERFCOUNTER1_HI"
9050  },
9051  {
9052   "chips": ["gfx103"],
9053   "map": {"at": 214280, "to": "mm"},
9054   "name": "PA_SC_PERFCOUNTER1_LO",
9055   "type_ref": "CPG_PERFCOUNTER1_LO"
9056  },
9057  {
9058   "chips": ["gfx103"],
9059   "map": {"at": 214284, "to": "mm"},
9060   "name": "PA_SC_PERFCOUNTER1_HI",
9061   "type_ref": "CPG_PERFCOUNTER1_HI"
9062  },
9063  {
9064   "chips": ["gfx103"],
9065   "map": {"at": 214288, "to": "mm"},
9066   "name": "PA_SC_PERFCOUNTER2_LO",
9067   "type_ref": "CPG_PERFCOUNTER1_LO"
9068  },
9069  {
9070   "chips": ["gfx103"],
9071   "map": {"at": 214292, "to": "mm"},
9072   "name": "PA_SC_PERFCOUNTER2_HI",
9073   "type_ref": "CPG_PERFCOUNTER1_HI"
9074  },
9075  {
9076   "chips": ["gfx103"],
9077   "map": {"at": 214296, "to": "mm"},
9078   "name": "PA_SC_PERFCOUNTER3_LO",
9079   "type_ref": "CPG_PERFCOUNTER1_LO"
9080  },
9081  {
9082   "chips": ["gfx103"],
9083   "map": {"at": 214300, "to": "mm"},
9084   "name": "PA_SC_PERFCOUNTER3_HI",
9085   "type_ref": "CPG_PERFCOUNTER1_HI"
9086  },
9087  {
9088   "chips": ["gfx103"],
9089   "map": {"at": 214304, "to": "mm"},
9090   "name": "PA_SC_PERFCOUNTER4_LO",
9091   "type_ref": "CPG_PERFCOUNTER1_LO"
9092  },
9093  {
9094   "chips": ["gfx103"],
9095   "map": {"at": 214308, "to": "mm"},
9096   "name": "PA_SC_PERFCOUNTER4_HI",
9097   "type_ref": "CPG_PERFCOUNTER1_HI"
9098  },
9099  {
9100   "chips": ["gfx103"],
9101   "map": {"at": 214312, "to": "mm"},
9102   "name": "PA_SC_PERFCOUNTER5_LO",
9103   "type_ref": "CPG_PERFCOUNTER1_LO"
9104  },
9105  {
9106   "chips": ["gfx103"],
9107   "map": {"at": 214316, "to": "mm"},
9108   "name": "PA_SC_PERFCOUNTER5_HI",
9109   "type_ref": "CPG_PERFCOUNTER1_HI"
9110  },
9111  {
9112   "chips": ["gfx103"],
9113   "map": {"at": 214320, "to": "mm"},
9114   "name": "PA_SC_PERFCOUNTER6_LO",
9115   "type_ref": "CPG_PERFCOUNTER1_LO"
9116  },
9117  {
9118   "chips": ["gfx103"],
9119   "map": {"at": 214324, "to": "mm"},
9120   "name": "PA_SC_PERFCOUNTER6_HI",
9121   "type_ref": "CPG_PERFCOUNTER1_HI"
9122  },
9123  {
9124   "chips": ["gfx103"],
9125   "map": {"at": 214328, "to": "mm"},
9126   "name": "PA_SC_PERFCOUNTER7_LO",
9127   "type_ref": "CPG_PERFCOUNTER1_LO"
9128  },
9129  {
9130   "chips": ["gfx103"],
9131   "map": {"at": 214332, "to": "mm"},
9132   "name": "PA_SC_PERFCOUNTER7_HI",
9133   "type_ref": "CPG_PERFCOUNTER1_HI"
9134  },
9135  {
9136   "chips": ["gfx103"],
9137   "map": {"at": 214528, "to": "mm"},
9138   "name": "SPI_PERFCOUNTER0_HI",
9139   "type_ref": "CPG_PERFCOUNTER1_HI"
9140  },
9141  {
9142   "chips": ["gfx103"],
9143   "map": {"at": 214532, "to": "mm"},
9144   "name": "SPI_PERFCOUNTER0_LO",
9145   "type_ref": "CPG_PERFCOUNTER1_LO"
9146  },
9147  {
9148   "chips": ["gfx103"],
9149   "map": {"at": 214536, "to": "mm"},
9150   "name": "SPI_PERFCOUNTER1_HI",
9151   "type_ref": "CPG_PERFCOUNTER1_HI"
9152  },
9153  {
9154   "chips": ["gfx103"],
9155   "map": {"at": 214540, "to": "mm"},
9156   "name": "SPI_PERFCOUNTER1_LO",
9157   "type_ref": "CPG_PERFCOUNTER1_LO"
9158  },
9159  {
9160   "chips": ["gfx103"],
9161   "map": {"at": 214544, "to": "mm"},
9162   "name": "SPI_PERFCOUNTER2_HI",
9163   "type_ref": "CPG_PERFCOUNTER1_HI"
9164  },
9165  {
9166   "chips": ["gfx103"],
9167   "map": {"at": 214548, "to": "mm"},
9168   "name": "SPI_PERFCOUNTER2_LO",
9169   "type_ref": "CPG_PERFCOUNTER1_LO"
9170  },
9171  {
9172   "chips": ["gfx103"],
9173   "map": {"at": 214552, "to": "mm"},
9174   "name": "SPI_PERFCOUNTER3_HI",
9175   "type_ref": "CPG_PERFCOUNTER1_HI"
9176  },
9177  {
9178   "chips": ["gfx103"],
9179   "map": {"at": 214556, "to": "mm"},
9180   "name": "SPI_PERFCOUNTER3_LO",
9181   "type_ref": "CPG_PERFCOUNTER1_LO"
9182  },
9183  {
9184   "chips": ["gfx103"],
9185   "map": {"at": 214560, "to": "mm"},
9186   "name": "SPI_PERFCOUNTER4_HI",
9187   "type_ref": "CPG_PERFCOUNTER1_HI"
9188  },
9189  {
9190   "chips": ["gfx103"],
9191   "map": {"at": 214564, "to": "mm"},
9192   "name": "SPI_PERFCOUNTER4_LO",
9193   "type_ref": "CPG_PERFCOUNTER1_LO"
9194  },
9195  {
9196   "chips": ["gfx103"],
9197   "map": {"at": 214568, "to": "mm"},
9198   "name": "SPI_PERFCOUNTER5_HI",
9199   "type_ref": "CPG_PERFCOUNTER1_HI"
9200  },
9201  {
9202   "chips": ["gfx103"],
9203   "map": {"at": 214572, "to": "mm"},
9204   "name": "SPI_PERFCOUNTER5_LO",
9205   "type_ref": "CPG_PERFCOUNTER1_LO"
9206  },
9207  {
9208   "chips": ["gfx103"],
9209   "map": {"at": 214784, "to": "mm"},
9210   "name": "SQ_PERFCOUNTER0_LO",
9211   "type_ref": "CPG_PERFCOUNTER1_LO"
9212  },
9213  {
9214   "chips": ["gfx103"],
9215   "map": {"at": 214788, "to": "mm"},
9216   "name": "SQ_PERFCOUNTER0_HI",
9217   "type_ref": "CPG_PERFCOUNTER1_HI"
9218  },
9219  {
9220   "chips": ["gfx103"],
9221   "map": {"at": 214792, "to": "mm"},
9222   "name": "SQ_PERFCOUNTER1_LO",
9223   "type_ref": "CPG_PERFCOUNTER1_LO"
9224  },
9225  {
9226   "chips": ["gfx103"],
9227   "map": {"at": 214796, "to": "mm"},
9228   "name": "SQ_PERFCOUNTER1_HI",
9229   "type_ref": "CPG_PERFCOUNTER1_HI"
9230  },
9231  {
9232   "chips": ["gfx103"],
9233   "map": {"at": 214800, "to": "mm"},
9234   "name": "SQ_PERFCOUNTER2_LO",
9235   "type_ref": "CPG_PERFCOUNTER1_LO"
9236  },
9237  {
9238   "chips": ["gfx103"],
9239   "map": {"at": 214804, "to": "mm"},
9240   "name": "SQ_PERFCOUNTER2_HI",
9241   "type_ref": "CPG_PERFCOUNTER1_HI"
9242  },
9243  {
9244   "chips": ["gfx103"],
9245   "map": {"at": 214808, "to": "mm"},
9246   "name": "SQ_PERFCOUNTER3_LO",
9247   "type_ref": "CPG_PERFCOUNTER1_LO"
9248  },
9249  {
9250   "chips": ["gfx103"],
9251   "map": {"at": 214812, "to": "mm"},
9252   "name": "SQ_PERFCOUNTER3_HI",
9253   "type_ref": "CPG_PERFCOUNTER1_HI"
9254  },
9255  {
9256   "chips": ["gfx103"],
9257   "map": {"at": 214816, "to": "mm"},
9258   "name": "SQ_PERFCOUNTER4_LO",
9259   "type_ref": "CPG_PERFCOUNTER1_LO"
9260  },
9261  {
9262   "chips": ["gfx103"],
9263   "map": {"at": 214820, "to": "mm"},
9264   "name": "SQ_PERFCOUNTER4_HI",
9265   "type_ref": "CPG_PERFCOUNTER1_HI"
9266  },
9267  {
9268   "chips": ["gfx103"],
9269   "map": {"at": 214824, "to": "mm"},
9270   "name": "SQ_PERFCOUNTER5_LO",
9271   "type_ref": "CPG_PERFCOUNTER1_LO"
9272  },
9273  {
9274   "chips": ["gfx103"],
9275   "map": {"at": 214828, "to": "mm"},
9276   "name": "SQ_PERFCOUNTER5_HI",
9277   "type_ref": "CPG_PERFCOUNTER1_HI"
9278  },
9279  {
9280   "chips": ["gfx103"],
9281   "map": {"at": 214832, "to": "mm"},
9282   "name": "SQ_PERFCOUNTER6_LO",
9283   "type_ref": "CPG_PERFCOUNTER1_LO"
9284  },
9285  {
9286   "chips": ["gfx103"],
9287   "map": {"at": 214836, "to": "mm"},
9288   "name": "SQ_PERFCOUNTER6_HI",
9289   "type_ref": "CPG_PERFCOUNTER1_HI"
9290  },
9291  {
9292   "chips": ["gfx103"],
9293   "map": {"at": 214840, "to": "mm"},
9294   "name": "SQ_PERFCOUNTER7_LO",
9295   "type_ref": "CPG_PERFCOUNTER1_LO"
9296  },
9297  {
9298   "chips": ["gfx103"],
9299   "map": {"at": 214844, "to": "mm"},
9300   "name": "SQ_PERFCOUNTER7_HI",
9301   "type_ref": "CPG_PERFCOUNTER1_HI"
9302  },
9303  {
9304   "chips": ["gfx103"],
9305   "map": {"at": 214848, "to": "mm"},
9306   "name": "SQ_PERFCOUNTER8_LO",
9307   "type_ref": "CPG_PERFCOUNTER1_LO"
9308  },
9309  {
9310   "chips": ["gfx103"],
9311   "map": {"at": 214852, "to": "mm"},
9312   "name": "SQ_PERFCOUNTER8_HI",
9313   "type_ref": "CPG_PERFCOUNTER1_HI"
9314  },
9315  {
9316   "chips": ["gfx103"],
9317   "map": {"at": 214856, "to": "mm"},
9318   "name": "SQ_PERFCOUNTER9_LO",
9319   "type_ref": "CPG_PERFCOUNTER1_LO"
9320  },
9321  {
9322   "chips": ["gfx103"],
9323   "map": {"at": 214860, "to": "mm"},
9324   "name": "SQ_PERFCOUNTER9_HI",
9325   "type_ref": "CPG_PERFCOUNTER1_HI"
9326  },
9327  {
9328   "chips": ["gfx103"],
9329   "map": {"at": 214864, "to": "mm"},
9330   "name": "SQ_PERFCOUNTER10_LO",
9331   "type_ref": "CPG_PERFCOUNTER1_LO"
9332  },
9333  {
9334   "chips": ["gfx103"],
9335   "map": {"at": 214868, "to": "mm"},
9336   "name": "SQ_PERFCOUNTER10_HI",
9337   "type_ref": "CPG_PERFCOUNTER1_HI"
9338  },
9339  {
9340   "chips": ["gfx103"],
9341   "map": {"at": 214872, "to": "mm"},
9342   "name": "SQ_PERFCOUNTER11_LO",
9343   "type_ref": "CPG_PERFCOUNTER1_LO"
9344  },
9345  {
9346   "chips": ["gfx103"],
9347   "map": {"at": 214876, "to": "mm"},
9348   "name": "SQ_PERFCOUNTER11_HI",
9349   "type_ref": "CPG_PERFCOUNTER1_HI"
9350  },
9351  {
9352   "chips": ["gfx103"],
9353   "map": {"at": 214880, "to": "mm"},
9354   "name": "SQ_PERFCOUNTER12_LO",
9355   "type_ref": "CPG_PERFCOUNTER1_LO"
9356  },
9357  {
9358   "chips": ["gfx103"],
9359   "map": {"at": 214884, "to": "mm"},
9360   "name": "SQ_PERFCOUNTER12_HI",
9361   "type_ref": "CPG_PERFCOUNTER1_HI"
9362  },
9363  {
9364   "chips": ["gfx103"],
9365   "map": {"at": 214888, "to": "mm"},
9366   "name": "SQ_PERFCOUNTER13_LO",
9367   "type_ref": "CPG_PERFCOUNTER1_LO"
9368  },
9369  {
9370   "chips": ["gfx103"],
9371   "map": {"at": 214892, "to": "mm"},
9372   "name": "SQ_PERFCOUNTER13_HI",
9373   "type_ref": "CPG_PERFCOUNTER1_HI"
9374  },
9375  {
9376   "chips": ["gfx103"],
9377   "map": {"at": 214896, "to": "mm"},
9378   "name": "SQ_PERFCOUNTER14_LO",
9379   "type_ref": "CPG_PERFCOUNTER1_LO"
9380  },
9381  {
9382   "chips": ["gfx103"],
9383   "map": {"at": 214900, "to": "mm"},
9384   "name": "SQ_PERFCOUNTER14_HI",
9385   "type_ref": "CPG_PERFCOUNTER1_HI"
9386  },
9387  {
9388   "chips": ["gfx103"],
9389   "map": {"at": 214904, "to": "mm"},
9390   "name": "SQ_PERFCOUNTER15_LO",
9391   "type_ref": "CPG_PERFCOUNTER1_LO"
9392  },
9393  {
9394   "chips": ["gfx103"],
9395   "map": {"at": 214908, "to": "mm"},
9396   "name": "SQ_PERFCOUNTER15_HI",
9397   "type_ref": "CPG_PERFCOUNTER1_HI"
9398  },
9399  {
9400   "chips": ["gfx103"],
9401   "map": {"at": 215296, "to": "mm"},
9402   "name": "SX_PERFCOUNTER0_LO",
9403   "type_ref": "CPG_PERFCOUNTER1_LO"
9404  },
9405  {
9406   "chips": ["gfx103"],
9407   "map": {"at": 215300, "to": "mm"},
9408   "name": "SX_PERFCOUNTER0_HI",
9409   "type_ref": "CPG_PERFCOUNTER1_HI"
9410  },
9411  {
9412   "chips": ["gfx103"],
9413   "map": {"at": 215304, "to": "mm"},
9414   "name": "SX_PERFCOUNTER1_LO",
9415   "type_ref": "CPG_PERFCOUNTER1_LO"
9416  },
9417  {
9418   "chips": ["gfx103"],
9419   "map": {"at": 215308, "to": "mm"},
9420   "name": "SX_PERFCOUNTER1_HI",
9421   "type_ref": "CPG_PERFCOUNTER1_HI"
9422  },
9423  {
9424   "chips": ["gfx103"],
9425   "map": {"at": 215312, "to": "mm"},
9426   "name": "SX_PERFCOUNTER2_LO",
9427   "type_ref": "CPG_PERFCOUNTER1_LO"
9428  },
9429  {
9430   "chips": ["gfx103"],
9431   "map": {"at": 215316, "to": "mm"},
9432   "name": "SX_PERFCOUNTER2_HI",
9433   "type_ref": "CPG_PERFCOUNTER1_HI"
9434  },
9435  {
9436   "chips": ["gfx103"],
9437   "map": {"at": 215320, "to": "mm"},
9438   "name": "SX_PERFCOUNTER3_LO",
9439   "type_ref": "CPG_PERFCOUNTER1_LO"
9440  },
9441  {
9442   "chips": ["gfx103"],
9443   "map": {"at": 215324, "to": "mm"},
9444   "name": "SX_PERFCOUNTER3_HI",
9445   "type_ref": "CPG_PERFCOUNTER1_HI"
9446  },
9447  {
9448   "chips": ["gfx103"],
9449   "map": {"at": 215424, "to": "mm"},
9450   "name": "GCEA_PERFCOUNTER2_LO",
9451   "type_ref": "CPG_PERFCOUNTER1_LO"
9452  },
9453  {
9454   "chips": ["gfx103"],
9455   "map": {"at": 215428, "to": "mm"},
9456   "name": "GCEA_PERFCOUNTER2_HI",
9457   "type_ref": "CPG_PERFCOUNTER1_HI"
9458  },
9459  {
9460   "chips": ["gfx103"],
9461   "map": {"at": 215432, "to": "mm"},
9462   "name": "GCEA_PERFCOUNTER_LO",
9463   "type_ref": "GCEA_PERFCOUNTER_LO"
9464  },
9465  {
9466   "chips": ["gfx103"],
9467   "map": {"at": 215436, "to": "mm"},
9468   "name": "GCEA_PERFCOUNTER_HI",
9469   "type_ref": "GCEA_PERFCOUNTER_HI"
9470  },
9471  {
9472   "chips": ["gfx103"],
9473   "map": {"at": 215552, "to": "mm"},
9474   "name": "GDS_PERFCOUNTER0_LO",
9475   "type_ref": "CPG_PERFCOUNTER1_LO"
9476  },
9477  {
9478   "chips": ["gfx103"],
9479   "map": {"at": 215556, "to": "mm"},
9480   "name": "GDS_PERFCOUNTER0_HI",
9481   "type_ref": "CPG_PERFCOUNTER1_HI"
9482  },
9483  {
9484   "chips": ["gfx103"],
9485   "map": {"at": 215560, "to": "mm"},
9486   "name": "GDS_PERFCOUNTER1_LO",
9487   "type_ref": "CPG_PERFCOUNTER1_LO"
9488  },
9489  {
9490   "chips": ["gfx103"],
9491   "map": {"at": 215564, "to": "mm"},
9492   "name": "GDS_PERFCOUNTER1_HI",
9493   "type_ref": "CPG_PERFCOUNTER1_HI"
9494  },
9495  {
9496   "chips": ["gfx103"],
9497   "map": {"at": 215568, "to": "mm"},
9498   "name": "GDS_PERFCOUNTER2_LO",
9499   "type_ref": "CPG_PERFCOUNTER1_LO"
9500  },
9501  {
9502   "chips": ["gfx103"],
9503   "map": {"at": 215572, "to": "mm"},
9504   "name": "GDS_PERFCOUNTER2_HI",
9505   "type_ref": "CPG_PERFCOUNTER1_HI"
9506  },
9507  {
9508   "chips": ["gfx103"],
9509   "map": {"at": 215576, "to": "mm"},
9510   "name": "GDS_PERFCOUNTER3_LO",
9511   "type_ref": "CPG_PERFCOUNTER1_LO"
9512  },
9513  {
9514   "chips": ["gfx103"],
9515   "map": {"at": 215580, "to": "mm"},
9516   "name": "GDS_PERFCOUNTER3_HI",
9517   "type_ref": "CPG_PERFCOUNTER1_HI"
9518  },
9519  {
9520   "chips": ["gfx103"],
9521   "map": {"at": 215808, "to": "mm"},
9522   "name": "TA_PERFCOUNTER0_LO",
9523   "type_ref": "CPG_PERFCOUNTER1_LO"
9524  },
9525  {
9526   "chips": ["gfx103"],
9527   "map": {"at": 215812, "to": "mm"},
9528   "name": "TA_PERFCOUNTER0_HI",
9529   "type_ref": "CPG_PERFCOUNTER1_HI"
9530  },
9531  {
9532   "chips": ["gfx103"],
9533   "map": {"at": 215816, "to": "mm"},
9534   "name": "TA_PERFCOUNTER1_LO",
9535   "type_ref": "CPG_PERFCOUNTER1_LO"
9536  },
9537  {
9538   "chips": ["gfx103"],
9539   "map": {"at": 215820, "to": "mm"},
9540   "name": "TA_PERFCOUNTER1_HI",
9541   "type_ref": "CPG_PERFCOUNTER1_HI"
9542  },
9543  {
9544   "chips": ["gfx103"],
9545   "map": {"at": 216064, "to": "mm"},
9546   "name": "TD_PERFCOUNTER0_LO",
9547   "type_ref": "CPG_PERFCOUNTER1_LO"
9548  },
9549  {
9550   "chips": ["gfx103"],
9551   "map": {"at": 216068, "to": "mm"},
9552   "name": "TD_PERFCOUNTER0_HI",
9553   "type_ref": "CPG_PERFCOUNTER1_HI"
9554  },
9555  {
9556   "chips": ["gfx103"],
9557   "map": {"at": 216072, "to": "mm"},
9558   "name": "TD_PERFCOUNTER1_LO",
9559   "type_ref": "CPG_PERFCOUNTER1_LO"
9560  },
9561  {
9562   "chips": ["gfx103"],
9563   "map": {"at": 216076, "to": "mm"},
9564   "name": "TD_PERFCOUNTER1_HI",
9565   "type_ref": "CPG_PERFCOUNTER1_HI"
9566  },
9567  {
9568   "chips": ["gfx103"],
9569   "map": {"at": 216320, "to": "mm"},
9570   "name": "TCP_PERFCOUNTER0_LO",
9571   "type_ref": "CPG_PERFCOUNTER1_LO"
9572  },
9573  {
9574   "chips": ["gfx103"],
9575   "map": {"at": 216324, "to": "mm"},
9576   "name": "TCP_PERFCOUNTER0_HI",
9577   "type_ref": "CPG_PERFCOUNTER1_HI"
9578  },
9579  {
9580   "chips": ["gfx103"],
9581   "map": {"at": 216328, "to": "mm"},
9582   "name": "TCP_PERFCOUNTER1_LO",
9583   "type_ref": "CPG_PERFCOUNTER1_LO"
9584  },
9585  {
9586   "chips": ["gfx103"],
9587   "map": {"at": 216332, "to": "mm"},
9588   "name": "TCP_PERFCOUNTER1_HI",
9589   "type_ref": "CPG_PERFCOUNTER1_HI"
9590  },
9591  {
9592   "chips": ["gfx103"],
9593   "map": {"at": 216336, "to": "mm"},
9594   "name": "TCP_PERFCOUNTER2_LO",
9595   "type_ref": "CPG_PERFCOUNTER1_LO"
9596  },
9597  {
9598   "chips": ["gfx103"],
9599   "map": {"at": 216340, "to": "mm"},
9600   "name": "TCP_PERFCOUNTER2_HI",
9601   "type_ref": "CPG_PERFCOUNTER1_HI"
9602  },
9603  {
9604   "chips": ["gfx103"],
9605   "map": {"at": 216344, "to": "mm"},
9606   "name": "TCP_PERFCOUNTER3_LO",
9607   "type_ref": "CPG_PERFCOUNTER1_LO"
9608  },
9609  {
9610   "chips": ["gfx103"],
9611   "map": {"at": 216348, "to": "mm"},
9612   "name": "TCP_PERFCOUNTER3_HI",
9613   "type_ref": "CPG_PERFCOUNTER1_HI"
9614  },
9615  {
9616   "chips": ["gfx103"],
9617   "map": {"at": 216576, "to": "mm"},
9618   "name": "GL2C_PERFCOUNTER0_LO",
9619   "type_ref": "CPG_PERFCOUNTER1_LO"
9620  },
9621  {
9622   "chips": ["gfx103"],
9623   "map": {"at": 216580, "to": "mm"},
9624   "name": "GL2C_PERFCOUNTER0_HI",
9625   "type_ref": "CPG_PERFCOUNTER1_HI"
9626  },
9627  {
9628   "chips": ["gfx103"],
9629   "map": {"at": 216584, "to": "mm"},
9630   "name": "GL2C_PERFCOUNTER1_LO",
9631   "type_ref": "CPG_PERFCOUNTER1_LO"
9632  },
9633  {
9634   "chips": ["gfx103"],
9635   "map": {"at": 216588, "to": "mm"},
9636   "name": "GL2C_PERFCOUNTER1_HI",
9637   "type_ref": "CPG_PERFCOUNTER1_HI"
9638  },
9639  {
9640   "chips": ["gfx103"],
9641   "map": {"at": 216592, "to": "mm"},
9642   "name": "GL2C_PERFCOUNTER2_LO",
9643   "type_ref": "CPG_PERFCOUNTER1_LO"
9644  },
9645  {
9646   "chips": ["gfx103"],
9647   "map": {"at": 216596, "to": "mm"},
9648   "name": "GL2C_PERFCOUNTER2_HI",
9649   "type_ref": "CPG_PERFCOUNTER1_HI"
9650  },
9651  {
9652   "chips": ["gfx103"],
9653   "map": {"at": 216600, "to": "mm"},
9654   "name": "GL2C_PERFCOUNTER3_LO",
9655   "type_ref": "CPG_PERFCOUNTER1_LO"
9656  },
9657  {
9658   "chips": ["gfx103"],
9659   "map": {"at": 216604, "to": "mm"},
9660   "name": "GL2C_PERFCOUNTER3_HI",
9661   "type_ref": "CPG_PERFCOUNTER1_HI"
9662  },
9663  {
9664   "chips": ["gfx103"],
9665   "map": {"at": 216640, "to": "mm"},
9666   "name": "GL2A_PERFCOUNTER0_LO",
9667   "type_ref": "CPG_PERFCOUNTER1_LO"
9668  },
9669  {
9670   "chips": ["gfx103"],
9671   "map": {"at": 216644, "to": "mm"},
9672   "name": "GL2A_PERFCOUNTER0_HI",
9673   "type_ref": "CPG_PERFCOUNTER1_HI"
9674  },
9675  {
9676   "chips": ["gfx103"],
9677   "map": {"at": 216648, "to": "mm"},
9678   "name": "GL2A_PERFCOUNTER1_LO",
9679   "type_ref": "CPG_PERFCOUNTER1_LO"
9680  },
9681  {
9682   "chips": ["gfx103"],
9683   "map": {"at": 216652, "to": "mm"},
9684   "name": "GL2A_PERFCOUNTER1_HI",
9685   "type_ref": "CPG_PERFCOUNTER1_HI"
9686  },
9687  {
9688   "chips": ["gfx103"],
9689   "map": {"at": 216656, "to": "mm"},
9690   "name": "GL2A_PERFCOUNTER2_LO",
9691   "type_ref": "CPG_PERFCOUNTER1_LO"
9692  },
9693  {
9694   "chips": ["gfx103"],
9695   "map": {"at": 216660, "to": "mm"},
9696   "name": "GL2A_PERFCOUNTER2_HI",
9697   "type_ref": "CPG_PERFCOUNTER1_HI"
9698  },
9699  {
9700   "chips": ["gfx103"],
9701   "map": {"at": 216664, "to": "mm"},
9702   "name": "GL2A_PERFCOUNTER3_LO",
9703   "type_ref": "CPG_PERFCOUNTER1_LO"
9704  },
9705  {
9706   "chips": ["gfx103"],
9707   "map": {"at": 216668, "to": "mm"},
9708   "name": "GL2A_PERFCOUNTER3_HI",
9709   "type_ref": "CPG_PERFCOUNTER1_HI"
9710  },
9711  {
9712   "chips": ["gfx103"],
9713   "map": {"at": 216704, "to": "mm"},
9714   "name": "GL1C_PERFCOUNTER0_LO",
9715   "type_ref": "CPG_PERFCOUNTER1_LO"
9716  },
9717  {
9718   "chips": ["gfx103"],
9719   "map": {"at": 216708, "to": "mm"},
9720   "name": "GL1C_PERFCOUNTER0_HI",
9721   "type_ref": "CPG_PERFCOUNTER1_HI"
9722  },
9723  {
9724   "chips": ["gfx103"],
9725   "map": {"at": 216712, "to": "mm"},
9726   "name": "GL1C_PERFCOUNTER1_LO",
9727   "type_ref": "CPG_PERFCOUNTER1_LO"
9728  },
9729  {
9730   "chips": ["gfx103"],
9731   "map": {"at": 216716, "to": "mm"},
9732   "name": "GL1C_PERFCOUNTER1_HI",
9733   "type_ref": "CPG_PERFCOUNTER1_HI"
9734  },
9735  {
9736   "chips": ["gfx103"],
9737   "map": {"at": 216720, "to": "mm"},
9738   "name": "GL1C_PERFCOUNTER2_LO",
9739   "type_ref": "CPG_PERFCOUNTER1_LO"
9740  },
9741  {
9742   "chips": ["gfx103"],
9743   "map": {"at": 216724, "to": "mm"},
9744   "name": "GL1C_PERFCOUNTER2_HI",
9745   "type_ref": "CPG_PERFCOUNTER1_HI"
9746  },
9747  {
9748   "chips": ["gfx103"],
9749   "map": {"at": 216728, "to": "mm"},
9750   "name": "GL1C_PERFCOUNTER3_LO",
9751   "type_ref": "CPG_PERFCOUNTER1_LO"
9752  },
9753  {
9754   "chips": ["gfx103"],
9755   "map": {"at": 216732, "to": "mm"},
9756   "name": "GL1C_PERFCOUNTER3_HI",
9757   "type_ref": "CPG_PERFCOUNTER1_HI"
9758  },
9759  {
9760   "chips": ["gfx103"],
9761   "map": {"at": 216832, "to": "mm"},
9762   "name": "CHC_PERFCOUNTER0_LO",
9763   "type_ref": "CPG_PERFCOUNTER1_LO"
9764  },
9765  {
9766   "chips": ["gfx103"],
9767   "map": {"at": 216836, "to": "mm"},
9768   "name": "CHC_PERFCOUNTER0_HI",
9769   "type_ref": "CPG_PERFCOUNTER1_HI"
9770  },
9771  {
9772   "chips": ["gfx103"],
9773   "map": {"at": 216840, "to": "mm"},
9774   "name": "CHC_PERFCOUNTER1_LO",
9775   "type_ref": "CPG_PERFCOUNTER1_LO"
9776  },
9777  {
9778   "chips": ["gfx103"],
9779   "map": {"at": 216844, "to": "mm"},
9780   "name": "CHC_PERFCOUNTER1_HI",
9781   "type_ref": "CPG_PERFCOUNTER1_HI"
9782  },
9783  {
9784   "chips": ["gfx103"],
9785   "map": {"at": 216848, "to": "mm"},
9786   "name": "CHC_PERFCOUNTER2_LO",
9787   "type_ref": "CPG_PERFCOUNTER1_LO"
9788  },
9789  {
9790   "chips": ["gfx103"],
9791   "map": {"at": 216852, "to": "mm"},
9792   "name": "CHC_PERFCOUNTER2_HI",
9793   "type_ref": "CPG_PERFCOUNTER1_HI"
9794  },
9795  {
9796   "chips": ["gfx103"],
9797   "map": {"at": 216856, "to": "mm"},
9798   "name": "CHC_PERFCOUNTER3_LO",
9799   "type_ref": "CPG_PERFCOUNTER1_LO"
9800  },
9801  {
9802   "chips": ["gfx103"],
9803   "map": {"at": 216860, "to": "mm"},
9804   "name": "CHC_PERFCOUNTER3_HI",
9805   "type_ref": "CPG_PERFCOUNTER1_HI"
9806  },
9807  {
9808   "chips": ["gfx103"],
9809   "map": {"at": 216864, "to": "mm"},
9810   "name": "CHCG_PERFCOUNTER0_LO",
9811   "type_ref": "CPG_PERFCOUNTER1_LO"
9812  },
9813  {
9814   "chips": ["gfx103"],
9815   "map": {"at": 216868, "to": "mm"},
9816   "name": "CHCG_PERFCOUNTER0_HI",
9817   "type_ref": "CPG_PERFCOUNTER1_HI"
9818  },
9819  {
9820   "chips": ["gfx103"],
9821   "map": {"at": 216872, "to": "mm"},
9822   "name": "CHCG_PERFCOUNTER1_LO",
9823   "type_ref": "CPG_PERFCOUNTER1_LO"
9824  },
9825  {
9826   "chips": ["gfx103"],
9827   "map": {"at": 216876, "to": "mm"},
9828   "name": "CHCG_PERFCOUNTER1_HI",
9829   "type_ref": "CPG_PERFCOUNTER1_HI"
9830  },
9831  {
9832   "chips": ["gfx103"],
9833   "map": {"at": 216880, "to": "mm"},
9834   "name": "CHCG_PERFCOUNTER2_LO",
9835   "type_ref": "CPG_PERFCOUNTER1_LO"
9836  },
9837  {
9838   "chips": ["gfx103"],
9839   "map": {"at": 216884, "to": "mm"},
9840   "name": "CHCG_PERFCOUNTER2_HI",
9841   "type_ref": "CPG_PERFCOUNTER1_HI"
9842  },
9843  {
9844   "chips": ["gfx103"],
9845   "map": {"at": 216888, "to": "mm"},
9846   "name": "CHCG_PERFCOUNTER3_LO",
9847   "type_ref": "CPG_PERFCOUNTER1_LO"
9848  },
9849  {
9850   "chips": ["gfx103"],
9851   "map": {"at": 216892, "to": "mm"},
9852   "name": "CHCG_PERFCOUNTER3_HI",
9853   "type_ref": "CPG_PERFCOUNTER1_HI"
9854  },
9855  {
9856   "chips": ["gfx103"],
9857   "map": {"at": 217112, "to": "mm"},
9858   "name": "CB_PERFCOUNTER0_LO",
9859   "type_ref": "CPG_PERFCOUNTER1_LO"
9860  },
9861  {
9862   "chips": ["gfx103"],
9863   "map": {"at": 217116, "to": "mm"},
9864   "name": "CB_PERFCOUNTER0_HI",
9865   "type_ref": "CPG_PERFCOUNTER1_HI"
9866  },
9867  {
9868   "chips": ["gfx103"],
9869   "map": {"at": 217120, "to": "mm"},
9870   "name": "CB_PERFCOUNTER1_LO",
9871   "type_ref": "CPG_PERFCOUNTER1_LO"
9872  },
9873  {
9874   "chips": ["gfx103"],
9875   "map": {"at": 217124, "to": "mm"},
9876   "name": "CB_PERFCOUNTER1_HI",
9877   "type_ref": "CPG_PERFCOUNTER1_HI"
9878  },
9879  {
9880   "chips": ["gfx103"],
9881   "map": {"at": 217128, "to": "mm"},
9882   "name": "CB_PERFCOUNTER2_LO",
9883   "type_ref": "CPG_PERFCOUNTER1_LO"
9884  },
9885  {
9886   "chips": ["gfx103"],
9887   "map": {"at": 217132, "to": "mm"},
9888   "name": "CB_PERFCOUNTER2_HI",
9889   "type_ref": "CPG_PERFCOUNTER1_HI"
9890  },
9891  {
9892   "chips": ["gfx103"],
9893   "map": {"at": 217136, "to": "mm"},
9894   "name": "CB_PERFCOUNTER3_LO",
9895   "type_ref": "CPG_PERFCOUNTER1_LO"
9896  },
9897  {
9898   "chips": ["gfx103"],
9899   "map": {"at": 217140, "to": "mm"},
9900   "name": "CB_PERFCOUNTER3_HI",
9901   "type_ref": "CPG_PERFCOUNTER1_HI"
9902  },
9903  {
9904   "chips": ["gfx103"],
9905   "map": {"at": 217344, "to": "mm"},
9906   "name": "DB_PERFCOUNTER0_LO",
9907   "type_ref": "CPG_PERFCOUNTER1_LO"
9908  },
9909  {
9910   "chips": ["gfx103"],
9911   "map": {"at": 217348, "to": "mm"},
9912   "name": "DB_PERFCOUNTER0_HI",
9913   "type_ref": "CPG_PERFCOUNTER1_HI"
9914  },
9915  {
9916   "chips": ["gfx103"],
9917   "map": {"at": 217352, "to": "mm"},
9918   "name": "DB_PERFCOUNTER1_LO",
9919   "type_ref": "CPG_PERFCOUNTER1_LO"
9920  },
9921  {
9922   "chips": ["gfx103"],
9923   "map": {"at": 217356, "to": "mm"},
9924   "name": "DB_PERFCOUNTER1_HI",
9925   "type_ref": "CPG_PERFCOUNTER1_HI"
9926  },
9927  {
9928   "chips": ["gfx103"],
9929   "map": {"at": 217360, "to": "mm"},
9930   "name": "DB_PERFCOUNTER2_LO",
9931   "type_ref": "CPG_PERFCOUNTER1_LO"
9932  },
9933  {
9934   "chips": ["gfx103"],
9935   "map": {"at": 217364, "to": "mm"},
9936   "name": "DB_PERFCOUNTER2_HI",
9937   "type_ref": "CPG_PERFCOUNTER1_HI"
9938  },
9939  {
9940   "chips": ["gfx103"],
9941   "map": {"at": 217368, "to": "mm"},
9942   "name": "DB_PERFCOUNTER3_LO",
9943   "type_ref": "CPG_PERFCOUNTER1_LO"
9944  },
9945  {
9946   "chips": ["gfx103"],
9947   "map": {"at": 217372, "to": "mm"},
9948   "name": "DB_PERFCOUNTER3_HI",
9949   "type_ref": "CPG_PERFCOUNTER1_HI"
9950  },
9951  {
9952   "chips": ["gfx103"],
9953   "map": {"at": 217600, "to": "mm"},
9954   "name": "RLC_PERFCOUNTER0_LO",
9955   "type_ref": "CPG_PERFCOUNTER1_LO"
9956  },
9957  {
9958   "chips": ["gfx103"],
9959   "map": {"at": 217604, "to": "mm"},
9960   "name": "RLC_PERFCOUNTER0_HI",
9961   "type_ref": "CPG_PERFCOUNTER1_HI"
9962  },
9963  {
9964   "chips": ["gfx103"],
9965   "map": {"at": 217608, "to": "mm"},
9966   "name": "RLC_PERFCOUNTER1_LO",
9967   "type_ref": "CPG_PERFCOUNTER1_LO"
9968  },
9969  {
9970   "chips": ["gfx103"],
9971   "map": {"at": 217612, "to": "mm"},
9972   "name": "RLC_PERFCOUNTER1_HI",
9973   "type_ref": "CPG_PERFCOUNTER1_HI"
9974  },
9975  {
9976   "chips": ["gfx103"],
9977   "map": {"at": 217856, "to": "mm"},
9978   "name": "RMI_PERFCOUNTER0_LO",
9979   "type_ref": "CPG_PERFCOUNTER1_LO"
9980  },
9981  {
9982   "chips": ["gfx103"],
9983   "map": {"at": 217860, "to": "mm"},
9984   "name": "RMI_PERFCOUNTER0_HI",
9985   "type_ref": "CPG_PERFCOUNTER1_HI"
9986  },
9987  {
9988   "chips": ["gfx103"],
9989   "map": {"at": 217864, "to": "mm"},
9990   "name": "RMI_PERFCOUNTER1_LO",
9991   "type_ref": "CPG_PERFCOUNTER1_LO"
9992  },
9993  {
9994   "chips": ["gfx103"],
9995   "map": {"at": 217868, "to": "mm"},
9996   "name": "RMI_PERFCOUNTER1_HI",
9997   "type_ref": "CPG_PERFCOUNTER1_HI"
9998  },
9999  {
10000   "chips": ["gfx103"],
10001   "map": {"at": 217872, "to": "mm"},
10002   "name": "RMI_PERFCOUNTER2_LO",
10003   "type_ref": "CPG_PERFCOUNTER1_LO"
10004  },
10005  {
10006   "chips": ["gfx103"],
10007   "map": {"at": 217876, "to": "mm"},
10008   "name": "RMI_PERFCOUNTER2_HI",
10009   "type_ref": "CPG_PERFCOUNTER1_HI"
10010  },
10011  {
10012   "chips": ["gfx103"],
10013   "map": {"at": 217880, "to": "mm"},
10014   "name": "RMI_PERFCOUNTER3_LO",
10015   "type_ref": "CPG_PERFCOUNTER1_LO"
10016  },
10017  {
10018   "chips": ["gfx103"],
10019   "map": {"at": 217884, "to": "mm"},
10020   "name": "RMI_PERFCOUNTER3_HI",
10021   "type_ref": "CPG_PERFCOUNTER1_HI"
10022  },
10023  {
10024   "chips": ["gfx103"],
10025   "map": {"at": 218016, "to": "mm"},
10026   "name": "GCMC_VM_L2_PERFCOUNTER_LO",
10027   "type_ref": "GCEA_PERFCOUNTER_LO"
10028  },
10029  {
10030   "chips": ["gfx103"],
10031   "map": {"at": 218020, "to": "mm"},
10032   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
10033   "type_ref": "GCEA_PERFCOUNTER_HI"
10034  },
10035  {
10036   "chips": ["gfx103"],
10037   "map": {"at": 218024, "to": "mm"},
10038   "name": "GCUTCL2_PERFCOUNTER_LO",
10039   "type_ref": "GCEA_PERFCOUNTER_LO"
10040  },
10041  {
10042   "chips": ["gfx103"],
10043   "map": {"at": 218028, "to": "mm"},
10044   "name": "GCUTCL2_PERFCOUNTER_HI",
10045   "type_ref": "GCEA_PERFCOUNTER_HI"
10046  },
10047  {
10048   "chips": ["gfx103"],
10049   "map": {"at": 218080, "to": "mm"},
10050   "name": "GCVML2_PERFCOUNTER2_0_LO",
10051   "type_ref": "CPG_PERFCOUNTER1_LO"
10052  },
10053  {
10054   "chips": ["gfx103"],
10055   "map": {"at": 218084, "to": "mm"},
10056   "name": "GCVML2_PERFCOUNTER2_1_LO",
10057   "type_ref": "CPG_PERFCOUNTER1_LO"
10058  },
10059  {
10060   "chips": ["gfx103"],
10061   "map": {"at": 218088, "to": "mm"},
10062   "name": "GCVML2_PERFCOUNTER2_0_HI",
10063   "type_ref": "CPG_PERFCOUNTER1_HI"
10064  },
10065  {
10066   "chips": ["gfx103"],
10067   "map": {"at": 218092, "to": "mm"},
10068   "name": "GCVML2_PERFCOUNTER2_1_HI",
10069   "type_ref": "CPG_PERFCOUNTER1_HI"
10070  },
10071  {
10072   "chips": ["gfx103"],
10073   "map": {"at": 218224, "to": "mm"},
10074   "name": "UTCL1_PERFCOUNTER0_LO",
10075   "type_ref": "CPG_PERFCOUNTER1_LO"
10076  },
10077  {
10078   "chips": ["gfx103"],
10079   "map": {"at": 218228, "to": "mm"},
10080   "name": "UTCL1_PERFCOUNTER0_HI",
10081   "type_ref": "CPG_PERFCOUNTER1_HI"
10082  },
10083  {
10084   "chips": ["gfx103"],
10085   "map": {"at": 218232, "to": "mm"},
10086   "name": "UTCL1_PERFCOUNTER1_LO",
10087   "type_ref": "CPG_PERFCOUNTER1_LO"
10088  },
10089  {
10090   "chips": ["gfx103"],
10091   "map": {"at": 218236, "to": "mm"},
10092   "name": "UTCL1_PERFCOUNTER1_HI",
10093   "type_ref": "CPG_PERFCOUNTER1_HI"
10094  },
10095  {
10096   "chips": ["gfx103"],
10097   "map": {"at": 218240, "to": "mm"},
10098   "name": "GCR_PERFCOUNTER0_LO",
10099   "type_ref": "CPG_PERFCOUNTER1_LO"
10100  },
10101  {
10102   "chips": ["gfx103"],
10103   "map": {"at": 218244, "to": "mm"},
10104   "name": "GCR_PERFCOUNTER0_HI",
10105   "type_ref": "CPG_PERFCOUNTER1_HI"
10106  },
10107  {
10108   "chips": ["gfx103"],
10109   "map": {"at": 218248, "to": "mm"},
10110   "name": "GCR_PERFCOUNTER1_LO",
10111   "type_ref": "CPG_PERFCOUNTER1_LO"
10112  },
10113  {
10114   "chips": ["gfx103"],
10115   "map": {"at": 218252, "to": "mm"},
10116   "name": "GCR_PERFCOUNTER1_HI",
10117   "type_ref": "CPG_PERFCOUNTER1_HI"
10118  },
10119  {
10120   "chips": ["gfx103"],
10121   "map": {"at": 218624, "to": "mm"},
10122   "name": "PA_PH_PERFCOUNTER0_LO",
10123   "type_ref": "CPG_PERFCOUNTER1_LO"
10124  },
10125  {
10126   "chips": ["gfx103"],
10127   "map": {"at": 218628, "to": "mm"},
10128   "name": "PA_PH_PERFCOUNTER0_HI",
10129   "type_ref": "CPG_PERFCOUNTER1_HI"
10130  },
10131  {
10132   "chips": ["gfx103"],
10133   "map": {"at": 218632, "to": "mm"},
10134   "name": "PA_PH_PERFCOUNTER1_LO",
10135   "type_ref": "CPG_PERFCOUNTER1_LO"
10136  },
10137  {
10138   "chips": ["gfx103"],
10139   "map": {"at": 218636, "to": "mm"},
10140   "name": "PA_PH_PERFCOUNTER1_HI",
10141   "type_ref": "CPG_PERFCOUNTER1_HI"
10142  },
10143  {
10144   "chips": ["gfx103"],
10145   "map": {"at": 218640, "to": "mm"},
10146   "name": "PA_PH_PERFCOUNTER2_LO",
10147   "type_ref": "CPG_PERFCOUNTER1_LO"
10148  },
10149  {
10150   "chips": ["gfx103"],
10151   "map": {"at": 218644, "to": "mm"},
10152   "name": "PA_PH_PERFCOUNTER2_HI",
10153   "type_ref": "CPG_PERFCOUNTER1_HI"
10154  },
10155  {
10156   "chips": ["gfx103"],
10157   "map": {"at": 218648, "to": "mm"},
10158   "name": "PA_PH_PERFCOUNTER3_LO",
10159   "type_ref": "CPG_PERFCOUNTER1_LO"
10160  },
10161  {
10162   "chips": ["gfx103"],
10163   "map": {"at": 218652, "to": "mm"},
10164   "name": "PA_PH_PERFCOUNTER3_HI",
10165   "type_ref": "CPG_PERFCOUNTER1_HI"
10166  },
10167  {
10168   "chips": ["gfx103"],
10169   "map": {"at": 218656, "to": "mm"},
10170   "name": "PA_PH_PERFCOUNTER4_LO",
10171   "type_ref": "CPG_PERFCOUNTER1_LO"
10172  },
10173  {
10174   "chips": ["gfx103"],
10175   "map": {"at": 218660, "to": "mm"},
10176   "name": "PA_PH_PERFCOUNTER4_HI",
10177   "type_ref": "CPG_PERFCOUNTER1_HI"
10178  },
10179  {
10180   "chips": ["gfx103"],
10181   "map": {"at": 218664, "to": "mm"},
10182   "name": "PA_PH_PERFCOUNTER5_LO",
10183   "type_ref": "CPG_PERFCOUNTER1_LO"
10184  },
10185  {
10186   "chips": ["gfx103"],
10187   "map": {"at": 218668, "to": "mm"},
10188   "name": "PA_PH_PERFCOUNTER5_HI",
10189   "type_ref": "CPG_PERFCOUNTER1_HI"
10190  },
10191  {
10192   "chips": ["gfx103"],
10193   "map": {"at": 218672, "to": "mm"},
10194   "name": "PA_PH_PERFCOUNTER6_LO",
10195   "type_ref": "CPG_PERFCOUNTER1_LO"
10196  },
10197  {
10198   "chips": ["gfx103"],
10199   "map": {"at": 218676, "to": "mm"},
10200   "name": "PA_PH_PERFCOUNTER6_HI",
10201   "type_ref": "CPG_PERFCOUNTER1_HI"
10202  },
10203  {
10204   "chips": ["gfx103"],
10205   "map": {"at": 218680, "to": "mm"},
10206   "name": "PA_PH_PERFCOUNTER7_LO",
10207   "type_ref": "CPG_PERFCOUNTER1_LO"
10208  },
10209  {
10210   "chips": ["gfx103"],
10211   "map": {"at": 218684, "to": "mm"},
10212   "name": "PA_PH_PERFCOUNTER7_HI",
10213   "type_ref": "CPG_PERFCOUNTER1_HI"
10214  },
10215  {
10216   "chips": ["gfx103"],
10217   "map": {"at": 218880, "to": "mm"},
10218   "name": "GL1A_PERFCOUNTER0_LO",
10219   "type_ref": "CPG_PERFCOUNTER1_LO"
10220  },
10221  {
10222   "chips": ["gfx103"],
10223   "map": {"at": 218884, "to": "mm"},
10224   "name": "GL1A_PERFCOUNTER0_HI",
10225   "type_ref": "CPG_PERFCOUNTER1_HI"
10226  },
10227  {
10228   "chips": ["gfx103"],
10229   "map": {"at": 218888, "to": "mm"},
10230   "name": "GL1A_PERFCOUNTER1_LO",
10231   "type_ref": "CPG_PERFCOUNTER1_LO"
10232  },
10233  {
10234   "chips": ["gfx103"],
10235   "map": {"at": 218892, "to": "mm"},
10236   "name": "GL1A_PERFCOUNTER1_HI",
10237   "type_ref": "CPG_PERFCOUNTER1_HI"
10238  },
10239  {
10240   "chips": ["gfx103"],
10241   "map": {"at": 218896, "to": "mm"},
10242   "name": "GL1A_PERFCOUNTER2_LO",
10243   "type_ref": "CPG_PERFCOUNTER1_LO"
10244  },
10245  {
10246   "chips": ["gfx103"],
10247   "map": {"at": 218900, "to": "mm"},
10248   "name": "GL1A_PERFCOUNTER2_HI",
10249   "type_ref": "CPG_PERFCOUNTER1_HI"
10250  },
10251  {
10252   "chips": ["gfx103"],
10253   "map": {"at": 218904, "to": "mm"},
10254   "name": "GL1A_PERFCOUNTER3_LO",
10255   "type_ref": "CPG_PERFCOUNTER1_LO"
10256  },
10257  {
10258   "chips": ["gfx103"],
10259   "map": {"at": 218908, "to": "mm"},
10260   "name": "GL1A_PERFCOUNTER3_HI",
10261   "type_ref": "CPG_PERFCOUNTER1_HI"
10262  },
10263  {
10264   "chips": ["gfx103"],
10265   "map": {"at": 219136, "to": "mm"},
10266   "name": "CHA_PERFCOUNTER0_LO",
10267   "type_ref": "CPG_PERFCOUNTER1_LO"
10268  },
10269  {
10270   "chips": ["gfx103"],
10271   "map": {"at": 219140, "to": "mm"},
10272   "name": "CHA_PERFCOUNTER0_HI",
10273   "type_ref": "CPG_PERFCOUNTER1_HI"
10274  },
10275  {
10276   "chips": ["gfx103"],
10277   "map": {"at": 219144, "to": "mm"},
10278   "name": "CHA_PERFCOUNTER1_LO",
10279   "type_ref": "CPG_PERFCOUNTER1_LO"
10280  },
10281  {
10282   "chips": ["gfx103"],
10283   "map": {"at": 219148, "to": "mm"},
10284   "name": "CHA_PERFCOUNTER1_HI",
10285   "type_ref": "CPG_PERFCOUNTER1_HI"
10286  },
10287  {
10288   "chips": ["gfx103"],
10289   "map": {"at": 219152, "to": "mm"},
10290   "name": "CHA_PERFCOUNTER2_LO",
10291   "type_ref": "CPG_PERFCOUNTER1_LO"
10292  },
10293  {
10294   "chips": ["gfx103"],
10295   "map": {"at": 219156, "to": "mm"},
10296   "name": "CHA_PERFCOUNTER2_HI",
10297   "type_ref": "CPG_PERFCOUNTER1_HI"
10298  },
10299  {
10300   "chips": ["gfx103"],
10301   "map": {"at": 219160, "to": "mm"},
10302   "name": "CHA_PERFCOUNTER3_LO",
10303   "type_ref": "CPG_PERFCOUNTER1_LO"
10304  },
10305  {
10306   "chips": ["gfx103"],
10307   "map": {"at": 219164, "to": "mm"},
10308   "name": "CHA_PERFCOUNTER3_HI",
10309   "type_ref": "CPG_PERFCOUNTER1_HI"
10310  },
10311  {
10312   "chips": ["gfx103"],
10313   "map": {"at": 219392, "to": "mm"},
10314   "name": "GUS_PERFCOUNTER2_LO",
10315   "type_ref": "CPG_PERFCOUNTER1_LO"
10316  },
10317  {
10318   "chips": ["gfx103"],
10319   "map": {"at": 219396, "to": "mm"},
10320   "name": "GUS_PERFCOUNTER2_HI",
10321   "type_ref": "CPG_PERFCOUNTER1_HI"
10322  },
10323  {
10324   "chips": ["gfx103"],
10325   "map": {"at": 219400, "to": "mm"},
10326   "name": "GUS_PERFCOUNTER_LO",
10327   "type_ref": "GCEA_PERFCOUNTER_LO"
10328  },
10329  {
10330   "chips": ["gfx103"],
10331   "map": {"at": 219404, "to": "mm"},
10332   "name": "GUS_PERFCOUNTER_HI",
10333   "type_ref": "GCEA_PERFCOUNTER_HI"
10334  },
10335  {
10336   "chips": ["gfx103"],
10337   "map": {"at": 219520, "to": "mm"},
10338   "name": "SDMA0_PERFCNT_PERFCOUNTER_LO",
10339   "type_ref": "GCEA_PERFCOUNTER_LO"
10340  },
10341  {
10342   "chips": ["gfx103"],
10343   "map": {"at": 219524, "to": "mm"},
10344   "name": "SDMA0_PERFCNT_PERFCOUNTER_HI",
10345   "type_ref": "GCEA_PERFCOUNTER_HI"
10346  },
10347  {
10348   "chips": ["gfx103"],
10349   "map": {"at": 219528, "to": "mm"},
10350   "name": "SDMA0_PERFCOUNTER0_LO",
10351   "type_ref": "CPG_PERFCOUNTER1_LO"
10352  },
10353  {
10354   "chips": ["gfx103"],
10355   "map": {"at": 219532, "to": "mm"},
10356   "name": "SDMA0_PERFCOUNTER0_HI",
10357   "type_ref": "CPG_PERFCOUNTER1_HI"
10358  },
10359  {
10360   "chips": ["gfx103"],
10361   "map": {"at": 219536, "to": "mm"},
10362   "name": "SDMA0_PERFCOUNTER1_LO",
10363   "type_ref": "CPG_PERFCOUNTER1_LO"
10364  },
10365  {
10366   "chips": ["gfx103"],
10367   "map": {"at": 219540, "to": "mm"},
10368   "name": "SDMA0_PERFCOUNTER1_HI",
10369   "type_ref": "CPG_PERFCOUNTER1_HI"
10370  },
10371  {
10372   "chips": ["gfx103"],
10373   "map": {"at": 219568, "to": "mm"},
10374   "name": "SDMA1_PERFCNT_PERFCOUNTER_LO",
10375   "type_ref": "GCEA_PERFCOUNTER_LO"
10376  },
10377  {
10378   "chips": ["gfx103"],
10379   "map": {"at": 219572, "to": "mm"},
10380   "name": "SDMA1_PERFCNT_PERFCOUNTER_HI",
10381   "type_ref": "GCEA_PERFCOUNTER_HI"
10382  },
10383  {
10384   "chips": ["gfx103"],
10385   "map": {"at": 219576, "to": "mm"},
10386   "name": "SDMA1_PERFCOUNTER0_LO",
10387   "type_ref": "CPG_PERFCOUNTER1_LO"
10388  },
10389  {
10390   "chips": ["gfx103"],
10391   "map": {"at": 219580, "to": "mm"},
10392   "name": "SDMA1_PERFCOUNTER0_HI",
10393   "type_ref": "CPG_PERFCOUNTER1_HI"
10394  },
10395  {
10396   "chips": ["gfx103"],
10397   "map": {"at": 219584, "to": "mm"},
10398   "name": "SDMA1_PERFCOUNTER1_LO",
10399   "type_ref": "CPG_PERFCOUNTER1_LO"
10400  },
10401  {
10402   "chips": ["gfx103"],
10403   "map": {"at": 219588, "to": "mm"},
10404   "name": "SDMA1_PERFCOUNTER1_HI",
10405   "type_ref": "CPG_PERFCOUNTER1_HI"
10406  },
10407  {
10408   "chips": ["gfx103"],
10409   "map": {"at": 219616, "to": "mm"},
10410   "name": "SDMA2_PERFCNT_PERFCOUNTER_LO",
10411   "type_ref": "GCEA_PERFCOUNTER_LO"
10412  },
10413  {
10414   "chips": ["gfx103"],
10415   "map": {"at": 219620, "to": "mm"},
10416   "name": "SDMA2_PERFCNT_PERFCOUNTER_HI",
10417   "type_ref": "GCEA_PERFCOUNTER_HI"
10418  },
10419  {
10420   "chips": ["gfx103"],
10421   "map": {"at": 219624, "to": "mm"},
10422   "name": "SDMA2_PERFCOUNTER0_LO",
10423   "type_ref": "CPG_PERFCOUNTER1_LO"
10424  },
10425  {
10426   "chips": ["gfx103"],
10427   "map": {"at": 219628, "to": "mm"},
10428   "name": "SDMA2_PERFCOUNTER0_HI",
10429   "type_ref": "CPG_PERFCOUNTER1_HI"
10430  },
10431  {
10432   "chips": ["gfx103"],
10433   "map": {"at": 219632, "to": "mm"},
10434   "name": "SDMA2_PERFCOUNTER1_LO",
10435   "type_ref": "CPG_PERFCOUNTER1_LO"
10436  },
10437  {
10438   "chips": ["gfx103"],
10439   "map": {"at": 219636, "to": "mm"},
10440   "name": "SDMA2_PERFCOUNTER1_HI",
10441   "type_ref": "CPG_PERFCOUNTER1_HI"
10442  },
10443  {
10444   "chips": ["gfx103"],
10445   "map": {"at": 219664, "to": "mm"},
10446   "name": "SDMA3_PERFCNT_PERFCOUNTER_LO",
10447   "type_ref": "GCEA_PERFCOUNTER_LO"
10448  },
10449  {
10450   "chips": ["gfx103"],
10451   "map": {"at": 219668, "to": "mm"},
10452   "name": "SDMA3_PERFCNT_PERFCOUNTER_HI",
10453   "type_ref": "GCEA_PERFCOUNTER_HI"
10454  },
10455  {
10456   "chips": ["gfx103"],
10457   "map": {"at": 219672, "to": "mm"},
10458   "name": "SDMA3_PERFCOUNTER0_LO",
10459   "type_ref": "CPG_PERFCOUNTER1_LO"
10460  },
10461  {
10462   "chips": ["gfx103"],
10463   "map": {"at": 219676, "to": "mm"},
10464   "name": "SDMA3_PERFCOUNTER0_HI",
10465   "type_ref": "CPG_PERFCOUNTER1_HI"
10466  },
10467  {
10468   "chips": ["gfx103"],
10469   "map": {"at": 219680, "to": "mm"},
10470   "name": "SDMA3_PERFCOUNTER1_LO",
10471   "type_ref": "CPG_PERFCOUNTER1_LO"
10472  },
10473  {
10474   "chips": ["gfx103"],
10475   "map": {"at": 219684, "to": "mm"},
10476   "name": "SDMA3_PERFCOUNTER1_HI",
10477   "type_ref": "CPG_PERFCOUNTER1_HI"
10478  },
10479  {
10480   "chips": ["gfx103"],
10481   "map": {"at": 221184, "to": "mm"},
10482   "name": "CPG_PERFCOUNTER1_SELECT",
10483   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10484  },
10485  {
10486   "chips": ["gfx103"],
10487   "map": {"at": 221188, "to": "mm"},
10488   "name": "CPG_PERFCOUNTER0_SELECT1",
10489   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10490  },
10491  {
10492   "chips": ["gfx103"],
10493   "map": {"at": 221192, "to": "mm"},
10494   "name": "CPG_PERFCOUNTER0_SELECT",
10495   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10496  },
10497  {
10498   "chips": ["gfx103"],
10499   "map": {"at": 221196, "to": "mm"},
10500   "name": "CPC_PERFCOUNTER1_SELECT",
10501   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10502  },
10503  {
10504   "chips": ["gfx103"],
10505   "map": {"at": 221200, "to": "mm"},
10506   "name": "CPC_PERFCOUNTER0_SELECT1",
10507   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10508  },
10509  {
10510   "chips": ["gfx103"],
10511   "map": {"at": 221204, "to": "mm"},
10512   "name": "CPF_PERFCOUNTER1_SELECT",
10513   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10514  },
10515  {
10516   "chips": ["gfx103"],
10517   "map": {"at": 221208, "to": "mm"},
10518   "name": "CPF_PERFCOUNTER0_SELECT1",
10519   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
10520  },
10521  {
10522   "chips": ["gfx103"],
10523   "map": {"at": 221212, "to": "mm"},
10524   "name": "CPF_PERFCOUNTER0_SELECT",
10525   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10526  },
10527  {
10528   "chips": ["gfx103"],
10529   "map": {"at": 221216, "to": "mm"},
10530   "name": "CP_PERFMON_CNTL",
10531   "type_ref": "CP_PERFMON_CNTL"
10532  },
10533  {
10534   "chips": ["gfx103"],
10535   "map": {"at": 221220, "to": "mm"},
10536   "name": "CPC_PERFCOUNTER0_SELECT",
10537   "type_ref": "CPG_PERFCOUNTER1_SELECT"
10538  },
10539  {
10540   "chips": ["gfx103"],
10541   "map": {"at": 221224, "to": "mm"},
10542   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
10543   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
10544  },
10545  {
10546   "chips": ["gfx103"],
10547   "map": {"at": 221228, "to": "mm"},
10548   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
10549   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
10550  },
10551  {
10552   "chips": ["gfx103"],
10553   "map": {"at": 221232, "to": "mm"},
10554   "name": "CPF_LATENCY_STATS_SELECT",
10555   "type_ref": "CPF_LATENCY_STATS_SELECT"
10556  },
10557  {
10558   "chips": ["gfx103"],
10559   "map": {"at": 221236, "to": "mm"},
10560   "name": "CPG_LATENCY_STATS_SELECT",
10561   "type_ref": "CPG_LATENCY_STATS_SELECT"
10562  },
10563  {
10564   "chips": ["gfx103"],
10565   "map": {"at": 221240, "to": "mm"},
10566   "name": "CPC_LATENCY_STATS_SELECT",
10567   "type_ref": "CPF_LATENCY_STATS_SELECT"
10568  },
10569  {
10570   "chips": ["gfx103"],
10571   "map": {"at": 221248, "to": "mm"},
10572   "name": "CP_DRAW_OBJECT",
10573   "type_ref": "CP_DRAW_OBJECT"
10574  },
10575  {
10576   "chips": ["gfx103"],
10577   "map": {"at": 221252, "to": "mm"},
10578   "name": "CP_DRAW_OBJECT_COUNTER",
10579   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
10580  },
10581  {
10582   "chips": ["gfx103"],
10583   "map": {"at": 221256, "to": "mm"},
10584   "name": "CP_DRAW_WINDOW_MASK_HI",
10585   "type_ref": "CP_DRAW_WINDOW_MASK_HI"
10586  },
10587  {
10588   "chips": ["gfx103"],
10589   "map": {"at": 221260, "to": "mm"},
10590   "name": "CP_DRAW_WINDOW_HI",
10591   "type_ref": "CP_DRAW_WINDOW_HI"
10592  },
10593  {
10594   "chips": ["gfx103"],
10595   "map": {"at": 221264, "to": "mm"},
10596   "name": "CP_DRAW_WINDOW_LO",
10597   "type_ref": "CP_DRAW_WINDOW_LO"
10598  },
10599  {
10600   "chips": ["gfx103"],
10601   "map": {"at": 221268, "to": "mm"},
10602   "name": "CP_DRAW_WINDOW_CNTL",
10603   "type_ref": "CP_DRAW_WINDOW_CNTL"
10604  },
10605  {
10606   "chips": ["gfx103"],
10607   "map": {"at": 221440, "to": "mm"},
10608   "name": "GRBM_PERFCOUNTER0_SELECT",
10609   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
10610  },
10611  {
10612   "chips": ["gfx103"],
10613   "map": {"at": 221444, "to": "mm"},
10614   "name": "GRBM_PERFCOUNTER1_SELECT",
10615   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
10616  },
10617  {
10618   "chips": ["gfx103"],
10619   "map": {"at": 221448, "to": "mm"},
10620   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
10621   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10622  },
10623  {
10624   "chips": ["gfx103"],
10625   "map": {"at": 221452, "to": "mm"},
10626   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
10627   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10628  },
10629  {
10630   "chips": ["gfx103"],
10631   "map": {"at": 221456, "to": "mm"},
10632   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
10633   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10634  },
10635  {
10636   "chips": ["gfx103"],
10637   "map": {"at": 221460, "to": "mm"},
10638   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
10639   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
10640  },
10641  {
10642   "chips": ["gfx103"],
10643   "map": {"at": 221492, "to": "mm"},
10644   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
10645   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
10646  },
10647  {
10648   "chips": ["gfx103"],
10649   "map": {"at": 221496, "to": "mm"},
10650   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
10651   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
10652  },
10653  {
10654   "chips": ["gfx103"],
10655   "map": {"at": 221840, "to": "mm"},
10656   "name": "GE1_PERFCOUNTER0_SELECT",
10657   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10658  },
10659  {
10660   "chips": ["gfx103"],
10661   "map": {"at": 221844, "to": "mm"},
10662   "name": "GE1_PERFCOUNTER0_SELECT1",
10663   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10664  },
10665  {
10666   "chips": ["gfx103"],
10667   "map": {"at": 221848, "to": "mm"},
10668   "name": "GE1_PERFCOUNTER1_SELECT",
10669   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10670  },
10671  {
10672   "chips": ["gfx103"],
10673   "map": {"at": 221852, "to": "mm"},
10674   "name": "GE1_PERFCOUNTER1_SELECT1",
10675   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10676  },
10677  {
10678   "chips": ["gfx103"],
10679   "map": {"at": 221856, "to": "mm"},
10680   "name": "GE1_PERFCOUNTER2_SELECT",
10681   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10682  },
10683  {
10684   "chips": ["gfx103"],
10685   "map": {"at": 221860, "to": "mm"},
10686   "name": "GE1_PERFCOUNTER2_SELECT1",
10687   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10688  },
10689  {
10690   "chips": ["gfx103"],
10691   "map": {"at": 221864, "to": "mm"},
10692   "name": "GE1_PERFCOUNTER3_SELECT",
10693   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10694  },
10695  {
10696   "chips": ["gfx103"],
10697   "map": {"at": 221868, "to": "mm"},
10698   "name": "GE1_PERFCOUNTER3_SELECT1",
10699   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10700  },
10701  {
10702   "chips": ["gfx103"],
10703   "map": {"at": 221872, "to": "mm"},
10704   "name": "GE2_DIST_PERFCOUNTER0_SELECT",
10705   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10706  },
10707  {
10708   "chips": ["gfx103"],
10709   "map": {"at": 221876, "to": "mm"},
10710   "name": "GE2_DIST_PERFCOUNTER0_SELECT1",
10711   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10712  },
10713  {
10714   "chips": ["gfx103"],
10715   "map": {"at": 221880, "to": "mm"},
10716   "name": "GE2_DIST_PERFCOUNTER1_SELECT",
10717   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10718  },
10719  {
10720   "chips": ["gfx103"],
10721   "map": {"at": 221884, "to": "mm"},
10722   "name": "GE2_DIST_PERFCOUNTER1_SELECT1",
10723   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10724  },
10725  {
10726   "chips": ["gfx103"],
10727   "map": {"at": 221888, "to": "mm"},
10728   "name": "GE2_DIST_PERFCOUNTER2_SELECT",
10729   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10730  },
10731  {
10732   "chips": ["gfx103"],
10733   "map": {"at": 221892, "to": "mm"},
10734   "name": "GE2_DIST_PERFCOUNTER2_SELECT1",
10735   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10736  },
10737  {
10738   "chips": ["gfx103"],
10739   "map": {"at": 221896, "to": "mm"},
10740   "name": "GE2_DIST_PERFCOUNTER3_SELECT",
10741   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10742  },
10743  {
10744   "chips": ["gfx103"],
10745   "map": {"at": 221900, "to": "mm"},
10746   "name": "GE2_DIST_PERFCOUNTER3_SELECT1",
10747   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10748  },
10749  {
10750   "chips": ["gfx103"],
10751   "map": {"at": 221904, "to": "mm"},
10752   "name": "GE2_SE_PERFCOUNTER0_SELECT",
10753   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10754  },
10755  {
10756   "chips": ["gfx103"],
10757   "map": {"at": 221908, "to": "mm"},
10758   "name": "GE2_SE_PERFCOUNTER0_SELECT1",
10759   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10760  },
10761  {
10762   "chips": ["gfx103"],
10763   "map": {"at": 221912, "to": "mm"},
10764   "name": "GE2_SE_PERFCOUNTER1_SELECT",
10765   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10766  },
10767  {
10768   "chips": ["gfx103"],
10769   "map": {"at": 221916, "to": "mm"},
10770   "name": "GE2_SE_PERFCOUNTER1_SELECT1",
10771   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10772  },
10773  {
10774   "chips": ["gfx103"],
10775   "map": {"at": 221920, "to": "mm"},
10776   "name": "GE2_SE_PERFCOUNTER2_SELECT",
10777   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10778  },
10779  {
10780   "chips": ["gfx103"],
10781   "map": {"at": 221924, "to": "mm"},
10782   "name": "GE2_SE_PERFCOUNTER2_SELECT1",
10783   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10784  },
10785  {
10786   "chips": ["gfx103"],
10787   "map": {"at": 221928, "to": "mm"},
10788   "name": "GE2_SE_PERFCOUNTER3_SELECT",
10789   "type_ref": "GE1_PERFCOUNTER0_SELECT"
10790  },
10791  {
10792   "chips": ["gfx103"],
10793   "map": {"at": 221932, "to": "mm"},
10794   "name": "GE2_SE_PERFCOUNTER3_SELECT1",
10795   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
10796  },
10797  {
10798   "chips": ["gfx103"],
10799   "map": {"at": 222208, "to": "mm"},
10800   "name": "PA_SU_PERFCOUNTER0_SELECT",
10801   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10802  },
10803  {
10804   "chips": ["gfx103"],
10805   "map": {"at": 222212, "to": "mm"},
10806   "name": "PA_SU_PERFCOUNTER0_SELECT1",
10807   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10808  },
10809  {
10810   "chips": ["gfx103"],
10811   "map": {"at": 222216, "to": "mm"},
10812   "name": "PA_SU_PERFCOUNTER1_SELECT",
10813   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10814  },
10815  {
10816   "chips": ["gfx103"],
10817   "map": {"at": 222220, "to": "mm"},
10818   "name": "PA_SU_PERFCOUNTER1_SELECT1",
10819   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10820  },
10821  {
10822   "chips": ["gfx103"],
10823   "map": {"at": 222224, "to": "mm"},
10824   "name": "PA_SU_PERFCOUNTER2_SELECT",
10825   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10826  },
10827  {
10828   "chips": ["gfx103"],
10829   "map": {"at": 222228, "to": "mm"},
10830   "name": "PA_SU_PERFCOUNTER2_SELECT1",
10831   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10832  },
10833  {
10834   "chips": ["gfx103"],
10835   "map": {"at": 222232, "to": "mm"},
10836   "name": "PA_SU_PERFCOUNTER3_SELECT",
10837   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10838  },
10839  {
10840   "chips": ["gfx103"],
10841   "map": {"at": 222236, "to": "mm"},
10842   "name": "PA_SU_PERFCOUNTER3_SELECT1",
10843   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10844  },
10845  {
10846   "chips": ["gfx103"],
10847   "map": {"at": 222464, "to": "mm"},
10848   "name": "PA_SC_PERFCOUNTER0_SELECT",
10849   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10850  },
10851  {
10852   "chips": ["gfx103"],
10853   "map": {"at": 222468, "to": "mm"},
10854   "name": "PA_SC_PERFCOUNTER0_SELECT1",
10855   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10856  },
10857  {
10858   "chips": ["gfx103"],
10859   "map": {"at": 222472, "to": "mm"},
10860   "name": "PA_SC_PERFCOUNTER1_SELECT",
10861   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10862  },
10863  {
10864   "chips": ["gfx103"],
10865   "map": {"at": 222476, "to": "mm"},
10866   "name": "PA_SC_PERFCOUNTER2_SELECT",
10867   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10868  },
10869  {
10870   "chips": ["gfx103"],
10871   "map": {"at": 222480, "to": "mm"},
10872   "name": "PA_SC_PERFCOUNTER3_SELECT",
10873   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10874  },
10875  {
10876   "chips": ["gfx103"],
10877   "map": {"at": 222484, "to": "mm"},
10878   "name": "PA_SC_PERFCOUNTER4_SELECT",
10879   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10880  },
10881  {
10882   "chips": ["gfx103"],
10883   "map": {"at": 222488, "to": "mm"},
10884   "name": "PA_SC_PERFCOUNTER5_SELECT",
10885   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10886  },
10887  {
10888   "chips": ["gfx103"],
10889   "map": {"at": 222492, "to": "mm"},
10890   "name": "PA_SC_PERFCOUNTER6_SELECT",
10891   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10892  },
10893  {
10894   "chips": ["gfx103"],
10895   "map": {"at": 222496, "to": "mm"},
10896   "name": "PA_SC_PERFCOUNTER7_SELECT",
10897   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10898  },
10899  {
10900   "chips": ["gfx103"],
10901   "map": {"at": 222720, "to": "mm"},
10902   "name": "SPI_PERFCOUNTER0_SELECT",
10903   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10904  },
10905  {
10906   "chips": ["gfx103"],
10907   "map": {"at": 222724, "to": "mm"},
10908   "name": "SPI_PERFCOUNTER1_SELECT",
10909   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10910  },
10911  {
10912   "chips": ["gfx103"],
10913   "map": {"at": 222728, "to": "mm"},
10914   "name": "SPI_PERFCOUNTER2_SELECT",
10915   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10916  },
10917  {
10918   "chips": ["gfx103"],
10919   "map": {"at": 222732, "to": "mm"},
10920   "name": "SPI_PERFCOUNTER3_SELECT",
10921   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
10922  },
10923  {
10924   "chips": ["gfx103"],
10925   "map": {"at": 222736, "to": "mm"},
10926   "name": "SPI_PERFCOUNTER0_SELECT1",
10927   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10928  },
10929  {
10930   "chips": ["gfx103"],
10931   "map": {"at": 222740, "to": "mm"},
10932   "name": "SPI_PERFCOUNTER1_SELECT1",
10933   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10934  },
10935  {
10936   "chips": ["gfx103"],
10937   "map": {"at": 222744, "to": "mm"},
10938   "name": "SPI_PERFCOUNTER2_SELECT1",
10939   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10940  },
10941  {
10942   "chips": ["gfx103"],
10943   "map": {"at": 222748, "to": "mm"},
10944   "name": "SPI_PERFCOUNTER3_SELECT1",
10945   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
10946  },
10947  {
10948   "chips": ["gfx103"],
10949   "map": {"at": 222752, "to": "mm"},
10950   "name": "SPI_PERFCOUNTER4_SELECT",
10951   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10952  },
10953  {
10954   "chips": ["gfx103"],
10955   "map": {"at": 222756, "to": "mm"},
10956   "name": "SPI_PERFCOUNTER5_SELECT",
10957   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10958  },
10959  {
10960   "chips": ["gfx103"],
10961   "map": {"at": 222760, "to": "mm"},
10962   "name": "SPI_PERFCOUNTER_BINS",
10963   "type_ref": "SPI_PERFCOUNTER_BINS"
10964  },
10965  {
10966   "chips": ["gfx103"],
10967   "map": {"at": 222976, "to": "mm"},
10968   "name": "SQ_PERFCOUNTER0_SELECT",
10969   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10970  },
10971  {
10972   "chips": ["gfx103"],
10973   "map": {"at": 222980, "to": "mm"},
10974   "name": "SQ_PERFCOUNTER1_SELECT",
10975   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10976  },
10977  {
10978   "chips": ["gfx103"],
10979   "map": {"at": 222984, "to": "mm"},
10980   "name": "SQ_PERFCOUNTER2_SELECT",
10981   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10982  },
10983  {
10984   "chips": ["gfx103"],
10985   "map": {"at": 222988, "to": "mm"},
10986   "name": "SQ_PERFCOUNTER3_SELECT",
10987   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10988  },
10989  {
10990   "chips": ["gfx103"],
10991   "map": {"at": 222992, "to": "mm"},
10992   "name": "SQ_PERFCOUNTER4_SELECT",
10993   "type_ref": "SQ_PERFCOUNTER0_SELECT"
10994  },
10995  {
10996   "chips": ["gfx103"],
10997   "map": {"at": 222996, "to": "mm"},
10998   "name": "SQ_PERFCOUNTER5_SELECT",
10999   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11000  },
11001  {
11002   "chips": ["gfx103"],
11003   "map": {"at": 223000, "to": "mm"},
11004   "name": "SQ_PERFCOUNTER6_SELECT",
11005   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11006  },
11007  {
11008   "chips": ["gfx103"],
11009   "map": {"at": 223004, "to": "mm"},
11010   "name": "SQ_PERFCOUNTER7_SELECT",
11011   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11012  },
11013  {
11014   "chips": ["gfx103"],
11015   "map": {"at": 223008, "to": "mm"},
11016   "name": "SQ_PERFCOUNTER8_SELECT",
11017   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11018  },
11019  {
11020   "chips": ["gfx103"],
11021   "map": {"at": 223012, "to": "mm"},
11022   "name": "SQ_PERFCOUNTER9_SELECT",
11023   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11024  },
11025  {
11026   "chips": ["gfx103"],
11027   "map": {"at": 223016, "to": "mm"},
11028   "name": "SQ_PERFCOUNTER10_SELECT",
11029   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11030  },
11031  {
11032   "chips": ["gfx103"],
11033   "map": {"at": 223020, "to": "mm"},
11034   "name": "SQ_PERFCOUNTER11_SELECT",
11035   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11036  },
11037  {
11038   "chips": ["gfx103"],
11039   "map": {"at": 223024, "to": "mm"},
11040   "name": "SQ_PERFCOUNTER12_SELECT",
11041   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11042  },
11043  {
11044   "chips": ["gfx103"],
11045   "map": {"at": 223028, "to": "mm"},
11046   "name": "SQ_PERFCOUNTER13_SELECT",
11047   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11048  },
11049  {
11050   "chips": ["gfx103"],
11051   "map": {"at": 223032, "to": "mm"},
11052   "name": "SQ_PERFCOUNTER14_SELECT",
11053   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11054  },
11055  {
11056   "chips": ["gfx103"],
11057   "map": {"at": 223036, "to": "mm"},
11058   "name": "SQ_PERFCOUNTER15_SELECT",
11059   "type_ref": "SQ_PERFCOUNTER0_SELECT"
11060  },
11061  {
11062   "chips": ["gfx103"],
11063   "map": {"at": 223104, "to": "mm"},
11064   "name": "SQ_PERFCOUNTER_CTRL",
11065   "type_ref": "SQ_PERFCOUNTER_CTRL"
11066  },
11067  {
11068   "chips": ["gfx103"],
11069   "map": {"at": 223112, "to": "mm"},
11070   "name": "SQ_PERFCOUNTER_CTRL2",
11071   "type_ref": "SQ_PERFCOUNTER_CTRL2"
11072  },
11073  {
11074   "chips": ["gfx103"],
11075   "map": {"at": 223232, "to": "mm"},
11076   "name": "GCEA_PERFCOUNTER2_SELECT",
11077   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11078  },
11079  {
11080   "chips": ["gfx103"],
11081   "map": {"at": 223236, "to": "mm"},
11082   "name": "GCEA_PERFCOUNTER2_SELECT1",
11083   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11084  },
11085  {
11086   "chips": ["gfx103"],
11087   "map": {"at": 223240, "to": "mm"},
11088   "name": "GCEA_PERFCOUNTER2_MODE",
11089   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11090  },
11091  {
11092   "chips": ["gfx103"],
11093   "map": {"at": 223244, "to": "mm"},
11094   "name": "GCEA_PERFCOUNTER0_CFG",
11095   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11096  },
11097  {
11098   "chips": ["gfx103"],
11099   "map": {"at": 223248, "to": "mm"},
11100   "name": "GCEA_PERFCOUNTER1_CFG",
11101   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11102  },
11103  {
11104   "chips": ["gfx103"],
11105   "map": {"at": 223252, "to": "mm"},
11106   "name": "GCEA_PERFCOUNTER_RSLT_CNTL",
11107   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11108  },
11109  {
11110   "chips": ["gfx103"],
11111   "map": {"at": 223488, "to": "mm"},
11112   "name": "SX_PERFCOUNTER0_SELECT",
11113   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11114  },
11115  {
11116   "chips": ["gfx103"],
11117   "map": {"at": 223492, "to": "mm"},
11118   "name": "SX_PERFCOUNTER1_SELECT",
11119   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11120  },
11121  {
11122   "chips": ["gfx103"],
11123   "map": {"at": 223496, "to": "mm"},
11124   "name": "SX_PERFCOUNTER2_SELECT",
11125   "type_ref": "SX_PERFCOUNTER2_SELECT"
11126  },
11127  {
11128   "chips": ["gfx103"],
11129   "map": {"at": 223500, "to": "mm"},
11130   "name": "SX_PERFCOUNTER3_SELECT",
11131   "type_ref": "SX_PERFCOUNTER2_SELECT"
11132  },
11133  {
11134   "chips": ["gfx103"],
11135   "map": {"at": 223504, "to": "mm"},
11136   "name": "SX_PERFCOUNTER0_SELECT1",
11137   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11138  },
11139  {
11140   "chips": ["gfx103"],
11141   "map": {"at": 223508, "to": "mm"},
11142   "name": "SX_PERFCOUNTER1_SELECT1",
11143   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11144  },
11145  {
11146   "chips": ["gfx103"],
11147   "map": {"at": 223744, "to": "mm"},
11148   "name": "GDS_PERFCOUNTER0_SELECT",
11149   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11150  },
11151  {
11152   "chips": ["gfx103"],
11153   "map": {"at": 223748, "to": "mm"},
11154   "name": "GDS_PERFCOUNTER1_SELECT",
11155   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11156  },
11157  {
11158   "chips": ["gfx103"],
11159   "map": {"at": 223752, "to": "mm"},
11160   "name": "GDS_PERFCOUNTER2_SELECT",
11161   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11162  },
11163  {
11164   "chips": ["gfx103"],
11165   "map": {"at": 223756, "to": "mm"},
11166   "name": "GDS_PERFCOUNTER3_SELECT",
11167   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11168  },
11169  {
11170   "chips": ["gfx103"],
11171   "map": {"at": 223760, "to": "mm"},
11172   "name": "GDS_PERFCOUNTER0_SELECT1",
11173   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11174  },
11175  {
11176   "chips": ["gfx103"],
11177   "map": {"at": 223764, "to": "mm"},
11178   "name": "GDS_PERFCOUNTER1_SELECT1",
11179   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11180  },
11181  {
11182   "chips": ["gfx103"],
11183   "map": {"at": 223768, "to": "mm"},
11184   "name": "GDS_PERFCOUNTER2_SELECT1",
11185   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11186  },
11187  {
11188   "chips": ["gfx103"],
11189   "map": {"at": 223772, "to": "mm"},
11190   "name": "GDS_PERFCOUNTER3_SELECT1",
11191   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11192  },
11193  {
11194   "chips": ["gfx103"],
11195   "map": {"at": 224000, "to": "mm"},
11196   "name": "TA_PERFCOUNTER0_SELECT",
11197   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11198  },
11199  {
11200   "chips": ["gfx103"],
11201   "map": {"at": 224004, "to": "mm"},
11202   "name": "TA_PERFCOUNTER0_SELECT1",
11203   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11204  },
11205  {
11206   "chips": ["gfx103"],
11207   "map": {"at": 224008, "to": "mm"},
11208   "name": "TA_PERFCOUNTER1_SELECT",
11209   "type_ref": "SX_PERFCOUNTER2_SELECT"
11210  },
11211  {
11212   "chips": ["gfx103"],
11213   "map": {"at": 224256, "to": "mm"},
11214   "name": "TD_PERFCOUNTER0_SELECT",
11215   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11216  },
11217  {
11218   "chips": ["gfx103"],
11219   "map": {"at": 224260, "to": "mm"},
11220   "name": "TD_PERFCOUNTER0_SELECT1",
11221   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11222  },
11223  {
11224   "chips": ["gfx103"],
11225   "map": {"at": 224264, "to": "mm"},
11226   "name": "TD_PERFCOUNTER1_SELECT",
11227   "type_ref": "SX_PERFCOUNTER2_SELECT"
11228  },
11229  {
11230   "chips": ["gfx103"],
11231   "map": {"at": 224512, "to": "mm"},
11232   "name": "TCP_PERFCOUNTER0_SELECT",
11233   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11234  },
11235  {
11236   "chips": ["gfx103"],
11237   "map": {"at": 224516, "to": "mm"},
11238   "name": "TCP_PERFCOUNTER0_SELECT1",
11239   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11240  },
11241  {
11242   "chips": ["gfx103"],
11243   "map": {"at": 224520, "to": "mm"},
11244   "name": "TCP_PERFCOUNTER1_SELECT",
11245   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11246  },
11247  {
11248   "chips": ["gfx103"],
11249   "map": {"at": 224524, "to": "mm"},
11250   "name": "TCP_PERFCOUNTER1_SELECT1",
11251   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11252  },
11253  {
11254   "chips": ["gfx103"],
11255   "map": {"at": 224528, "to": "mm"},
11256   "name": "TCP_PERFCOUNTER2_SELECT",
11257   "type_ref": "SX_PERFCOUNTER2_SELECT"
11258  },
11259  {
11260   "chips": ["gfx103"],
11261   "map": {"at": 224532, "to": "mm"},
11262   "name": "TCP_PERFCOUNTER3_SELECT",
11263   "type_ref": "SX_PERFCOUNTER2_SELECT"
11264  },
11265  {
11266   "chips": ["gfx103"],
11267   "map": {"at": 224768, "to": "mm"},
11268   "name": "GL2C_PERFCOUNTER0_SELECT",
11269   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11270  },
11271  {
11272   "chips": ["gfx103"],
11273   "map": {"at": 224772, "to": "mm"},
11274   "name": "GL2C_PERFCOUNTER0_SELECT1",
11275   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11276  },
11277  {
11278   "chips": ["gfx103"],
11279   "map": {"at": 224776, "to": "mm"},
11280   "name": "GL2C_PERFCOUNTER1_SELECT",
11281   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11282  },
11283  {
11284   "chips": ["gfx103"],
11285   "map": {"at": 224780, "to": "mm"},
11286   "name": "GL2C_PERFCOUNTER1_SELECT1",
11287   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11288  },
11289  {
11290   "chips": ["gfx103"],
11291   "map": {"at": 224784, "to": "mm"},
11292   "name": "GL2C_PERFCOUNTER2_SELECT",
11293   "type_ref": "SX_PERFCOUNTER2_SELECT"
11294  },
11295  {
11296   "chips": ["gfx103"],
11297   "map": {"at": 224788, "to": "mm"},
11298   "name": "GL2C_PERFCOUNTER3_SELECT",
11299   "type_ref": "SX_PERFCOUNTER2_SELECT"
11300  },
11301  {
11302   "chips": ["gfx103"],
11303   "map": {"at": 224832, "to": "mm"},
11304   "name": "GL2A_PERFCOUNTER0_SELECT",
11305   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11306  },
11307  {
11308   "chips": ["gfx103"],
11309   "map": {"at": 224836, "to": "mm"},
11310   "name": "GL2A_PERFCOUNTER0_SELECT1",
11311   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11312  },
11313  {
11314   "chips": ["gfx103"],
11315   "map": {"at": 224840, "to": "mm"},
11316   "name": "GL2A_PERFCOUNTER1_SELECT",
11317   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11318  },
11319  {
11320   "chips": ["gfx103"],
11321   "map": {"at": 224844, "to": "mm"},
11322   "name": "GL2A_PERFCOUNTER1_SELECT1",
11323   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11324  },
11325  {
11326   "chips": ["gfx103"],
11327   "map": {"at": 224848, "to": "mm"},
11328   "name": "GL2A_PERFCOUNTER2_SELECT",
11329   "type_ref": "SX_PERFCOUNTER2_SELECT"
11330  },
11331  {
11332   "chips": ["gfx103"],
11333   "map": {"at": 224852, "to": "mm"},
11334   "name": "GL2A_PERFCOUNTER3_SELECT",
11335   "type_ref": "SX_PERFCOUNTER2_SELECT"
11336  },
11337  {
11338   "chips": ["gfx103"],
11339   "map": {"at": 224896, "to": "mm"},
11340   "name": "GL1C_PERFCOUNTER0_SELECT",
11341   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11342  },
11343  {
11344   "chips": ["gfx103"],
11345   "map": {"at": 224900, "to": "mm"},
11346   "name": "GL1C_PERFCOUNTER0_SELECT1",
11347   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11348  },
11349  {
11350   "chips": ["gfx103"],
11351   "map": {"at": 224904, "to": "mm"},
11352   "name": "GL1C_PERFCOUNTER1_SELECT",
11353   "type_ref": "SX_PERFCOUNTER2_SELECT"
11354  },
11355  {
11356   "chips": ["gfx103"],
11357   "map": {"at": 224908, "to": "mm"},
11358   "name": "GL1C_PERFCOUNTER2_SELECT",
11359   "type_ref": "SX_PERFCOUNTER2_SELECT"
11360  },
11361  {
11362   "chips": ["gfx103"],
11363   "map": {"at": 224912, "to": "mm"},
11364   "name": "GL1C_PERFCOUNTER3_SELECT",
11365   "type_ref": "SX_PERFCOUNTER2_SELECT"
11366  },
11367  {
11368   "chips": ["gfx103"],
11369   "map": {"at": 225024, "to": "mm"},
11370   "name": "CHC_PERFCOUNTER0_SELECT",
11371   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11372  },
11373  {
11374   "chips": ["gfx103"],
11375   "map": {"at": 225028, "to": "mm"},
11376   "name": "CHC_PERFCOUNTER0_SELECT1",
11377   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11378  },
11379  {
11380   "chips": ["gfx103"],
11381   "map": {"at": 225032, "to": "mm"},
11382   "name": "CHC_PERFCOUNTER1_SELECT",
11383   "type_ref": "SX_PERFCOUNTER2_SELECT"
11384  },
11385  {
11386   "chips": ["gfx103"],
11387   "map": {"at": 225036, "to": "mm"},
11388   "name": "CHC_PERFCOUNTER2_SELECT",
11389   "type_ref": "SX_PERFCOUNTER2_SELECT"
11390  },
11391  {
11392   "chips": ["gfx103"],
11393   "map": {"at": 225040, "to": "mm"},
11394   "name": "CHC_PERFCOUNTER3_SELECT",
11395   "type_ref": "SX_PERFCOUNTER2_SELECT"
11396  },
11397  {
11398   "chips": ["gfx103"],
11399   "map": {"at": 225048, "to": "mm"},
11400   "name": "CHCG_PERFCOUNTER0_SELECT",
11401   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11402  },
11403  {
11404   "chips": ["gfx103"],
11405   "map": {"at": 225052, "to": "mm"},
11406   "name": "CHCG_PERFCOUNTER0_SELECT1",
11407   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
11408  },
11409  {
11410   "chips": ["gfx103"],
11411   "map": {"at": 225056, "to": "mm"},
11412   "name": "CHCG_PERFCOUNTER1_SELECT",
11413   "type_ref": "SX_PERFCOUNTER2_SELECT"
11414  },
11415  {
11416   "chips": ["gfx103"],
11417   "map": {"at": 225060, "to": "mm"},
11418   "name": "CHCG_PERFCOUNTER2_SELECT",
11419   "type_ref": "SX_PERFCOUNTER2_SELECT"
11420  },
11421  {
11422   "chips": ["gfx103"],
11423   "map": {"at": 225064, "to": "mm"},
11424   "name": "CHCG_PERFCOUNTER3_SELECT",
11425   "type_ref": "SX_PERFCOUNTER2_SELECT"
11426  },
11427  {
11428   "chips": ["gfx103"],
11429   "map": {"at": 225280, "to": "mm"},
11430   "name": "CB_PERFCOUNTER_FILTER",
11431   "type_ref": "CB_PERFCOUNTER_FILTER"
11432  },
11433  {
11434   "chips": ["gfx103"],
11435   "map": {"at": 225284, "to": "mm"},
11436   "name": "CB_PERFCOUNTER0_SELECT",
11437   "type_ref": "CB_PERFCOUNTER0_SELECT"
11438  },
11439  {
11440   "chips": ["gfx103"],
11441   "map": {"at": 225288, "to": "mm"},
11442   "name": "CB_PERFCOUNTER0_SELECT1",
11443   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11444  },
11445  {
11446   "chips": ["gfx103"],
11447   "map": {"at": 225292, "to": "mm"},
11448   "name": "CB_PERFCOUNTER1_SELECT",
11449   "type_ref": "CB_PERFCOUNTER1_SELECT"
11450  },
11451  {
11452   "chips": ["gfx103"],
11453   "map": {"at": 225296, "to": "mm"},
11454   "name": "CB_PERFCOUNTER2_SELECT",
11455   "type_ref": "CB_PERFCOUNTER1_SELECT"
11456  },
11457  {
11458   "chips": ["gfx103"],
11459   "map": {"at": 225300, "to": "mm"},
11460   "name": "CB_PERFCOUNTER3_SELECT",
11461   "type_ref": "CB_PERFCOUNTER1_SELECT"
11462  },
11463  {
11464   "chips": ["gfx103"],
11465   "map": {"at": 225536, "to": "mm"},
11466   "name": "DB_PERFCOUNTER0_SELECT",
11467   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11468  },
11469  {
11470   "chips": ["gfx103"],
11471   "map": {"at": 225540, "to": "mm"},
11472   "name": "DB_PERFCOUNTER0_SELECT1",
11473   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11474  },
11475  {
11476   "chips": ["gfx103"],
11477   "map": {"at": 225544, "to": "mm"},
11478   "name": "DB_PERFCOUNTER1_SELECT",
11479   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11480  },
11481  {
11482   "chips": ["gfx103"],
11483   "map": {"at": 225548, "to": "mm"},
11484   "name": "DB_PERFCOUNTER1_SELECT1",
11485   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11486  },
11487  {
11488   "chips": ["gfx103"],
11489   "map": {"at": 225552, "to": "mm"},
11490   "name": "DB_PERFCOUNTER2_SELECT",
11491   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11492  },
11493  {
11494   "chips": ["gfx103"],
11495   "map": {"at": 225560, "to": "mm"},
11496   "name": "DB_PERFCOUNTER3_SELECT",
11497   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11498  },
11499  {
11500   "chips": ["gfx103"],
11501   "map": {"at": 225792, "to": "mm"},
11502   "name": "RLC_SPM_PERFMON_CNTL",
11503   "type_ref": "RLC_SPM_PERFMON_CNTL"
11504  },
11505  {
11506   "chips": ["gfx103"],
11507   "map": {"at": 225796, "to": "mm"},
11508   "name": "RLC_SPM_PERFMON_RING_BASE_LO",
11509   "type_ref": "RLC_SPM_PERFMON_RING_BASE_LO"
11510  },
11511  {
11512   "chips": ["gfx103"],
11513   "map": {"at": 225800, "to": "mm"},
11514   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
11515   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
11516  },
11517  {
11518   "chips": ["gfx103"],
11519   "map": {"at": 225804, "to": "mm"},
11520   "name": "RLC_SPM_PERFMON_RING_SIZE",
11521   "type_ref": "RLC_SPM_PERFMON_RING_SIZE"
11522  },
11523  {
11524   "chips": ["gfx103"],
11525   "map": {"at": 225808, "to": "mm"},
11526   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
11527   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
11528  },
11529  {
11530   "chips": ["gfx103"],
11531   "map": {"at": 225812, "to": "mm"},
11532   "name": "RLC_SPM_RING_RDPTR",
11533   "type_ref": "RLC_SPM_RING_RDPTR"
11534  },
11535  {
11536   "chips": ["gfx103"],
11537   "map": {"at": 225816, "to": "mm"},
11538   "name": "RLC_SPM_SEGMENT_THRESHOLD",
11539   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
11540  },
11541  {
11542   "chips": ["gfx103"],
11543   "map": {"at": 225820, "to": "mm"},
11544   "name": "RLC_SPM_SE_MUXSEL_ADDR",
11545   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
11546  },
11547  {
11548   "chips": ["gfx103"],
11549   "map": {"at": 225824, "to": "mm"},
11550   "name": "RLC_SPM_SE_MUXSEL_DATA",
11551   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11552  },
11553  {
11554   "chips": ["gfx103"],
11555   "map": {"at": 225828, "to": "mm"},
11556   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
11557   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
11558  },
11559  {
11560   "chips": ["gfx103"],
11561   "map": {"at": 225832, "to": "mm"},
11562   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA",
11563   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
11564  },
11565  {
11566   "chips": ["gfx103"],
11567   "map": {"at": 225836, "to": "mm"},
11568   "name": "RLC_SPM_DESER_START_SKEW",
11569   "type_ref": "RLC_SPM_DESER_START_SKEW"
11570  },
11571  {
11572   "chips": ["gfx103"],
11573   "map": {"at": 225840, "to": "mm"},
11574   "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW",
11575   "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW"
11576  },
11577  {
11578   "chips": ["gfx103"],
11579   "map": {"at": 225844, "to": "mm"},
11580   "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW",
11581   "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW"
11582  },
11583  {
11584   "chips": ["gfx103"],
11585   "map": {"at": 225848, "to": "mm"},
11586   "name": "RLC_SPM_SE_SAMPLE_SKEW",
11587   "type_ref": "RLC_SPM_SE_SAMPLE_SKEW"
11588  },
11589  {
11590   "chips": ["gfx103"],
11591   "map": {"at": 225852, "to": "mm"},
11592   "name": "RLC_SPM_SE_MUXSEL_SKEW",
11593   "type_ref": "RLC_SPM_SE_MUXSEL_SKEW"
11594  },
11595  {
11596   "chips": ["gfx103"],
11597   "map": {"at": 225856, "to": "mm"},
11598   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR",
11599   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR"
11600  },
11601  {
11602   "chips": ["gfx103"],
11603   "map": {"at": 225860, "to": "mm"},
11604   "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA",
11605   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
11606  },
11607  {
11608   "chips": ["gfx103"],
11609   "map": {"at": 225864, "to": "mm"},
11610   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR",
11611   "type_ref": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR"
11612  },
11613  {
11614   "chips": ["gfx103"],
11615   "map": {"at": 225868, "to": "mm"},
11616   "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA",
11617   "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA"
11618  },
11619  {
11620   "chips": ["gfx103"],
11621   "map": {"at": 225872, "to": "mm"},
11622   "name": "RLC_SPM_RING_WRPTR",
11623   "type_ref": "RLC_SPM_RING_WRPTR"
11624  },
11625  {
11626   "chips": ["gfx103"],
11627   "map": {"at": 225876, "to": "mm"},
11628   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
11629   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
11630  },
11631  {
11632   "chips": ["gfx103"],
11633   "map": {"at": 225880, "to": "mm"},
11634   "name": "RLC_SPM_ACCUM_DATARAM_DATA",
11635   "type_ref": "RLC_SPM_ACCUM_DATARAM_DATA"
11636  },
11637  {
11638   "chips": ["gfx103"],
11639   "map": {"at": 225884, "to": "mm"},
11640   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
11641   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
11642  },
11643  {
11644   "chips": ["gfx103"],
11645   "map": {"at": 225888, "to": "mm"},
11646   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
11647   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
11648  },
11649  {
11650   "chips": ["gfx103"],
11651   "map": {"at": 225892, "to": "mm"},
11652   "name": "RLC_SPM_ACCUM_STATUS",
11653   "type_ref": "RLC_SPM_ACCUM_STATUS"
11654  },
11655  {
11656   "chips": ["gfx103"],
11657   "map": {"at": 225896, "to": "mm"},
11658   "name": "RLC_SPM_ACCUM_CTRL",
11659   "type_ref": "RLC_SPM_ACCUM_CTRL"
11660  },
11661  {
11662   "chips": ["gfx103"],
11663   "map": {"at": 225900, "to": "mm"},
11664   "name": "RLC_SPM_ACCUM_MODE",
11665   "type_ref": "RLC_SPM_ACCUM_MODE"
11666  },
11667  {
11668   "chips": ["gfx103"],
11669   "map": {"at": 225904, "to": "mm"},
11670   "name": "RLC_SPM_ACCUM_THRESHOLD",
11671   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
11672  },
11673  {
11674   "chips": ["gfx103"],
11675   "map": {"at": 225908, "to": "mm"},
11676   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
11677   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
11678  },
11679  {
11680   "chips": ["gfx103"],
11681   "map": {"at": 225912, "to": "mm"},
11682   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
11683   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
11684  },
11685  {
11686   "chips": ["gfx103"],
11687   "map": {"at": 225916, "to": "mm"},
11688   "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE",
11689   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
11690  },
11691  {
11692   "chips": ["gfx103"],
11693   "map": {"at": 225920, "to": "mm"},
11694   "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE",
11695   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
11696  },
11697  {
11698   "chips": ["gfx103"],
11699   "map": {"at": 225924, "to": "mm"},
11700   "name": "RLC_SPM_VIRT_CTRL",
11701   "type_ref": "RLC_SPM_VIRT_CTRL"
11702  },
11703  {
11704   "chips": ["gfx103"],
11705   "map": {"at": 225928, "to": "mm"},
11706   "name": "RLC_SPM_PERFMON_SWA_SEGMENT_SIZE",
11707   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
11708  },
11709  {
11710   "chips": ["gfx103"],
11711   "map": {"at": 225932, "to": "mm"},
11712   "name": "RLC_SPM_VIRT_STATUS",
11713   "type_ref": "RLC_SPM_VIRT_STATUS"
11714  },
11715  {
11716   "chips": ["gfx103"],
11717   "map": {"at": 225936, "to": "mm"},
11718   "name": "RLC_SPM_GFXCLOCK_HIGHCOUNT",
11719   "type_ref": "RLC_SPM_GFXCLOCK_HIGHCOUNT"
11720  },
11721  {
11722   "chips": ["gfx103"],
11723   "map": {"at": 225940, "to": "mm"},
11724   "name": "RLC_SPM_GFXCLOCK_LOWCOUNT",
11725   "type_ref": "RLC_SPM_GFXCLOCK_LOWCOUNT"
11726  },
11727  {
11728   "chips": ["gfx103"],
11729   "map": {"at": 225944, "to": "mm"},
11730   "name": "RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE",
11731   "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE"
11732  },
11733  {
11734   "chips": ["gfx103"],
11735   "map": {"at": 225948, "to": "mm"},
11736   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET",
11737   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
11738  },
11739  {
11740   "chips": ["gfx103"],
11741   "map": {"at": 225952, "to": "mm"},
11742   "name": "RLC_SPM_SE_MUXSEL_ADDR_OFFSET",
11743   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET"
11744  },
11745  {
11746   "chips": ["gfx103"],
11747   "map": {"at": 225956, "to": "mm"},
11748   "name": "RLC_SPM_ACCUM_SWA_DATARAM_ADDR",
11749   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
11750  },
11751  {
11752   "chips": ["gfx103"],
11753   "map": {"at": 225960, "to": "mm"},
11754   "name": "RLC_SPM_ACCUM_SWA_DATARAM_DATA",
11755   "type_ref": "RLC_SPM_ACCUM_DATARAM_DATA"
11756  },
11757  {
11758   "chips": ["gfx103"],
11759   "map": {"at": 225964, "to": "mm"},
11760   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET",
11761   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET"
11762  },
11763  {
11764   "chips": ["gfx103"],
11765   "map": {"at": 225968, "to": "mm"},
11766   "name": "RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE",
11767   "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE"
11768  },
11769  {
11770   "chips": ["gfx103"],
11771   "map": {"at": 225972, "to": "mm"},
11772   "name": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS",
11773   "type_ref": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS"
11774  },
11775  {
11776   "chips": ["gfx103"],
11777   "map": {"at": 226048, "to": "mm"},
11778   "name": "RLC_PERFMON_CNTL",
11779   "type_ref": "RLC_PERFMON_CNTL"
11780  },
11781  {
11782   "chips": ["gfx103"],
11783   "map": {"at": 226052, "to": "mm"},
11784   "name": "RLC_PERFCOUNTER0_SELECT",
11785   "type_ref": "RLC_PERFCOUNTER0_SELECT"
11786  },
11787  {
11788   "chips": ["gfx103"],
11789   "map": {"at": 226056, "to": "mm"},
11790   "name": "RLC_PERFCOUNTER1_SELECT",
11791   "type_ref": "RLC_PERFCOUNTER0_SELECT"
11792  },
11793  {
11794   "chips": ["gfx103"],
11795   "map": {"at": 226060, "to": "mm"},
11796   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
11797   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
11798  },
11799  {
11800   "chips": ["gfx103"],
11801   "map": {"at": 226064, "to": "mm"},
11802   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
11803   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
11804  },
11805  {
11806   "chips": ["gfx103"],
11807   "map": {"at": 226068, "to": "mm"},
11808   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA",
11809   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
11810  },
11811  {
11812   "chips": ["gfx103"],
11813   "map": {"at": 226072, "to": "mm"},
11814   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
11815   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
11816  },
11817  {
11818   "chips": ["gfx103"],
11819   "map": {"at": 226076, "to": "mm"},
11820   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA",
11821   "type_ref": "SPI_SHADER_USER_DATA_PS_0"
11822  },
11823  {
11824   "chips": ["gfx103"],
11825   "map": {"at": 226192, "to": "mm"},
11826   "name": "RLC_PERFMON_CLK_CNTL",
11827   "type_ref": "RLC_PERFMON_CLK_CNTL"
11828  },
11829  {
11830   "chips": ["gfx103"],
11831   "map": {"at": 226304, "to": "mm"},
11832   "name": "RMI_PERFCOUNTER0_SELECT",
11833   "type_ref": "CB_PERFCOUNTER0_SELECT"
11834  },
11835  {
11836   "chips": ["gfx103"],
11837   "map": {"at": 226308, "to": "mm"},
11838   "name": "RMI_PERFCOUNTER0_SELECT1",
11839   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11840  },
11841  {
11842   "chips": ["gfx103"],
11843   "map": {"at": 226312, "to": "mm"},
11844   "name": "RMI_PERFCOUNTER1_SELECT",
11845   "type_ref": "CB_PERFCOUNTER1_SELECT"
11846  },
11847  {
11848   "chips": ["gfx103"],
11849   "map": {"at": 226316, "to": "mm"},
11850   "name": "RMI_PERFCOUNTER2_SELECT",
11851   "type_ref": "CB_PERFCOUNTER0_SELECT"
11852  },
11853  {
11854   "chips": ["gfx103"],
11855   "map": {"at": 226320, "to": "mm"},
11856   "name": "RMI_PERFCOUNTER2_SELECT1",
11857   "type_ref": "CB_PERFCOUNTER0_SELECT1"
11858  },
11859  {
11860   "chips": ["gfx103"],
11861   "map": {"at": 226324, "to": "mm"},
11862   "name": "RMI_PERFCOUNTER3_SELECT",
11863   "type_ref": "CB_PERFCOUNTER1_SELECT"
11864  },
11865  {
11866   "chips": ["gfx103"],
11867   "map": {"at": 226328, "to": "mm"},
11868   "name": "RMI_PERF_COUNTER_CNTL",
11869   "type_ref": "RMI_PERF_COUNTER_CNTL"
11870  },
11871  {
11872   "chips": ["gfx103"],
11873   "map": {"at": 226480, "to": "mm"},
11874   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
11875   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11876  },
11877  {
11878   "chips": ["gfx103"],
11879   "map": {"at": 226484, "to": "mm"},
11880   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
11881   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11882  },
11883  {
11884   "chips": ["gfx103"],
11885   "map": {"at": 226488, "to": "mm"},
11886   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
11887   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11888  },
11889  {
11890   "chips": ["gfx103"],
11891   "map": {"at": 226492, "to": "mm"},
11892   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
11893   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11894  },
11895  {
11896   "chips": ["gfx103"],
11897   "map": {"at": 226496, "to": "mm"},
11898   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
11899   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11900  },
11901  {
11902   "chips": ["gfx103"],
11903   "map": {"at": 226500, "to": "mm"},
11904   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
11905   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11906  },
11907  {
11908   "chips": ["gfx103"],
11909   "map": {"at": 226504, "to": "mm"},
11910   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
11911   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11912  },
11913  {
11914   "chips": ["gfx103"],
11915   "map": {"at": 226508, "to": "mm"},
11916   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
11917   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11918  },
11919  {
11920   "chips": ["gfx103"],
11921   "map": {"at": 226512, "to": "mm"},
11922   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
11923   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11924  },
11925  {
11926   "chips": ["gfx103"],
11927   "map": {"at": 226516, "to": "mm"},
11928   "name": "GCUTCL2_PERFCOUNTER0_CFG",
11929   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11930  },
11931  {
11932   "chips": ["gfx103"],
11933   "map": {"at": 226520, "to": "mm"},
11934   "name": "GCUTCL2_PERFCOUNTER1_CFG",
11935   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11936  },
11937  {
11938   "chips": ["gfx103"],
11939   "map": {"at": 226524, "to": "mm"},
11940   "name": "GCUTCL2_PERFCOUNTER2_CFG",
11941   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11942  },
11943  {
11944   "chips": ["gfx103"],
11945   "map": {"at": 226528, "to": "mm"},
11946   "name": "GCUTCL2_PERFCOUNTER3_CFG",
11947   "type_ref": "GCEA_PERFCOUNTER0_CFG"
11948  },
11949  {
11950   "chips": ["gfx103"],
11951   "map": {"at": 226532, "to": "mm"},
11952   "name": "GCUTCL2_PERFCOUNTER_RSLT_CNTL",
11953   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
11954  },
11955  {
11956   "chips": ["gfx103"],
11957   "map": {"at": 226544, "to": "mm"},
11958   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
11959   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11960  },
11961  {
11962   "chips": ["gfx103"],
11963   "map": {"at": 226548, "to": "mm"},
11964   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
11965   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
11966  },
11967  {
11968   "chips": ["gfx103"],
11969   "map": {"at": 226552, "to": "mm"},
11970   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
11971   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11972  },
11973  {
11974   "chips": ["gfx103"],
11975   "map": {"at": 226556, "to": "mm"},
11976   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
11977   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
11978  },
11979  {
11980   "chips": ["gfx103"],
11981   "map": {"at": 226560, "to": "mm"},
11982   "name": "GCVML2_PERFCOUNTER2_0_MODE",
11983   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11984  },
11985  {
11986   "chips": ["gfx103"],
11987   "map": {"at": 226564, "to": "mm"},
11988   "name": "GCVML2_PERFCOUNTER2_1_MODE",
11989   "type_ref": "GCEA_PERFCOUNTER2_MODE"
11990  },
11991  {
11992   "chips": ["gfx103"],
11993   "map": {"at": 226688, "to": "mm"},
11994   "name": "GCR_PERFCOUNTER0_SELECT",
11995   "type_ref": "CB_PERFCOUNTER0_SELECT"
11996  },
11997  {
11998   "chips": ["gfx103"],
11999   "map": {"at": 226692, "to": "mm"},
12000   "name": "GCR_PERFCOUNTER0_SELECT1",
12001   "type_ref": "CB_PERFCOUNTER0_SELECT1"
12002  },
12003  {
12004   "chips": ["gfx103"],
12005   "map": {"at": 226696, "to": "mm"},
12006   "name": "GCR_PERFCOUNTER1_SELECT",
12007   "type_ref": "GCR_PERFCOUNTER1_SELECT"
12008  },
12009  {
12010   "chips": ["gfx103"],
12011   "map": {"at": 226700, "to": "mm"},
12012   "name": "UTCL1_PERFCOUNTER0_SELECT",
12013   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12014  },
12015  {
12016   "chips": ["gfx103"],
12017   "map": {"at": 226704, "to": "mm"},
12018   "name": "UTCL1_PERFCOUNTER1_SELECT",
12019   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
12020  },
12021  {
12022   "chips": ["gfx103"],
12023   "map": {"at": 226816, "to": "mm"},
12024   "name": "PA_PH_PERFCOUNTER0_SELECT",
12025   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12026  },
12027  {
12028   "chips": ["gfx103"],
12029   "map": {"at": 226820, "to": "mm"},
12030   "name": "PA_PH_PERFCOUNTER0_SELECT1",
12031   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12032  },
12033  {
12034   "chips": ["gfx103"],
12035   "map": {"at": 226824, "to": "mm"},
12036   "name": "PA_PH_PERFCOUNTER1_SELECT",
12037   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12038  },
12039  {
12040   "chips": ["gfx103"],
12041   "map": {"at": 226828, "to": "mm"},
12042   "name": "PA_PH_PERFCOUNTER2_SELECT",
12043   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12044  },
12045  {
12046   "chips": ["gfx103"],
12047   "map": {"at": 226832, "to": "mm"},
12048   "name": "PA_PH_PERFCOUNTER3_SELECT",
12049   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12050  },
12051  {
12052   "chips": ["gfx103"],
12053   "map": {"at": 226836, "to": "mm"},
12054   "name": "PA_PH_PERFCOUNTER4_SELECT",
12055   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12056  },
12057  {
12058   "chips": ["gfx103"],
12059   "map": {"at": 226840, "to": "mm"},
12060   "name": "PA_PH_PERFCOUNTER5_SELECT",
12061   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12062  },
12063  {
12064   "chips": ["gfx103"],
12065   "map": {"at": 226844, "to": "mm"},
12066   "name": "PA_PH_PERFCOUNTER6_SELECT",
12067   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12068  },
12069  {
12070   "chips": ["gfx103"],
12071   "map": {"at": 226848, "to": "mm"},
12072   "name": "PA_PH_PERFCOUNTER7_SELECT",
12073   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
12074  },
12075  {
12076   "chips": ["gfx103"],
12077   "map": {"at": 226880, "to": "mm"},
12078   "name": "PA_PH_PERFCOUNTER1_SELECT1",
12079   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12080  },
12081  {
12082   "chips": ["gfx103"],
12083   "map": {"at": 226884, "to": "mm"},
12084   "name": "PA_PH_PERFCOUNTER2_SELECT1",
12085   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12086  },
12087  {
12088   "chips": ["gfx103"],
12089   "map": {"at": 226888, "to": "mm"},
12090   "name": "PA_PH_PERFCOUNTER3_SELECT1",
12091   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12092  },
12093  {
12094   "chips": ["gfx103"],
12095   "map": {"at": 227072, "to": "mm"},
12096   "name": "GL1A_PERFCOUNTER0_SELECT",
12097   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12098  },
12099  {
12100   "chips": ["gfx103"],
12101   "map": {"at": 227076, "to": "mm"},
12102   "name": "GL1A_PERFCOUNTER0_SELECT1",
12103   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
12104  },
12105  {
12106   "chips": ["gfx103"],
12107   "map": {"at": 227080, "to": "mm"},
12108   "name": "GL1A_PERFCOUNTER1_SELECT",
12109   "type_ref": "SX_PERFCOUNTER2_SELECT"
12110  },
12111  {
12112   "chips": ["gfx103"],
12113   "map": {"at": 227084, "to": "mm"},
12114   "name": "GL1A_PERFCOUNTER2_SELECT",
12115   "type_ref": "SX_PERFCOUNTER2_SELECT"
12116  },
12117  {
12118   "chips": ["gfx103"],
12119   "map": {"at": 227088, "to": "mm"},
12120   "name": "GL1A_PERFCOUNTER3_SELECT",
12121   "type_ref": "SX_PERFCOUNTER2_SELECT"
12122  },
12123  {
12124   "chips": ["gfx103"],
12125   "map": {"at": 227200, "to": "mm"},
12126   "name": "CHA_PERFCOUNTER0_SELECT",
12127   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12128  },
12129  {
12130   "chips": ["gfx103"],
12131   "map": {"at": 227204, "to": "mm"},
12132   "name": "CHA_PERFCOUNTER0_SELECT1",
12133   "type_ref": "GE1_PERFCOUNTER0_SELECT1"
12134  },
12135  {
12136   "chips": ["gfx103"],
12137   "map": {"at": 227208, "to": "mm"},
12138   "name": "CHA_PERFCOUNTER1_SELECT",
12139   "type_ref": "SX_PERFCOUNTER2_SELECT"
12140  },
12141  {
12142   "chips": ["gfx103"],
12143   "map": {"at": 227212, "to": "mm"},
12144   "name": "CHA_PERFCOUNTER2_SELECT",
12145   "type_ref": "SX_PERFCOUNTER2_SELECT"
12146  },
12147  {
12148   "chips": ["gfx103"],
12149   "map": {"at": 227216, "to": "mm"},
12150   "name": "CHA_PERFCOUNTER3_SELECT",
12151   "type_ref": "SX_PERFCOUNTER2_SELECT"
12152  },
12153  {
12154   "chips": ["gfx103"],
12155   "map": {"at": 227328, "to": "mm"},
12156   "name": "GUS_PERFCOUNTER2_SELECT",
12157   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12158  },
12159  {
12160   "chips": ["gfx103"],
12161   "map": {"at": 227332, "to": "mm"},
12162   "name": "GUS_PERFCOUNTER2_SELECT1",
12163   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12164  },
12165  {
12166   "chips": ["gfx103"],
12167   "map": {"at": 227336, "to": "mm"},
12168   "name": "GUS_PERFCOUNTER2_MODE",
12169   "type_ref": "GCEA_PERFCOUNTER2_MODE"
12170  },
12171  {
12172   "chips": ["gfx103"],
12173   "map": {"at": 227340, "to": "mm"},
12174   "name": "GUS_PERFCOUNTER0_CFG",
12175   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12176  },
12177  {
12178   "chips": ["gfx103"],
12179   "map": {"at": 227344, "to": "mm"},
12180   "name": "GUS_PERFCOUNTER1_CFG",
12181   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12182  },
12183  {
12184   "chips": ["gfx103"],
12185   "map": {"at": 227348, "to": "mm"},
12186   "name": "GUS_PERFCOUNTER_RSLT_CNTL",
12187   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
12188  },
12189  {
12190   "chips": ["gfx103"],
12191   "map": {"at": 227456, "to": "mm"},
12192   "name": "SDMA0_PERFCNT_PERFCOUNTER0_CFG",
12193   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12194  },
12195  {
12196   "chips": ["gfx103"],
12197   "map": {"at": 227460, "to": "mm"},
12198   "name": "SDMA0_PERFCNT_PERFCOUNTER1_CFG",
12199   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12200  },
12201  {
12202   "chips": ["gfx103"],
12203   "map": {"at": 227464, "to": "mm"},
12204   "name": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL",
12205   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
12206  },
12207  {
12208   "chips": ["gfx103"],
12209   "map": {"at": 227468, "to": "mm"},
12210   "name": "SDMA0_PERFCNT_MISC_CNTL",
12211   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
12212  },
12213  {
12214   "chips": ["gfx103"],
12215   "map": {"at": 227472, "to": "mm"},
12216   "name": "SDMA0_PERFCOUNTER0_SELECT",
12217   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12218  },
12219  {
12220   "chips": ["gfx103"],
12221   "map": {"at": 227476, "to": "mm"},
12222   "name": "SDMA0_PERFCOUNTER0_SELECT1",
12223   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12224  },
12225  {
12226   "chips": ["gfx103"],
12227   "map": {"at": 227480, "to": "mm"},
12228   "name": "SDMA0_PERFCOUNTER1_SELECT",
12229   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12230  },
12231  {
12232   "chips": ["gfx103"],
12233   "map": {"at": 227484, "to": "mm"},
12234   "name": "SDMA0_PERFCOUNTER1_SELECT1",
12235   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12236  },
12237  {
12238   "chips": ["gfx103"],
12239   "map": {"at": 227504, "to": "mm"},
12240   "name": "SDMA1_PERFCNT_PERFCOUNTER0_CFG",
12241   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12242  },
12243  {
12244   "chips": ["gfx103"],
12245   "map": {"at": 227508, "to": "mm"},
12246   "name": "SDMA1_PERFCNT_PERFCOUNTER1_CFG",
12247   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12248  },
12249  {
12250   "chips": ["gfx103"],
12251   "map": {"at": 227512, "to": "mm"},
12252   "name": "SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL",
12253   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
12254  },
12255  {
12256   "chips": ["gfx103"],
12257   "map": {"at": 227516, "to": "mm"},
12258   "name": "SDMA1_PERFCNT_MISC_CNTL",
12259   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
12260  },
12261  {
12262   "chips": ["gfx103"],
12263   "map": {"at": 227520, "to": "mm"},
12264   "name": "SDMA1_PERFCOUNTER0_SELECT",
12265   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12266  },
12267  {
12268   "chips": ["gfx103"],
12269   "map": {"at": 227524, "to": "mm"},
12270   "name": "SDMA1_PERFCOUNTER0_SELECT1",
12271   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12272  },
12273  {
12274   "chips": ["gfx103"],
12275   "map": {"at": 227528, "to": "mm"},
12276   "name": "SDMA1_PERFCOUNTER1_SELECT",
12277   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12278  },
12279  {
12280   "chips": ["gfx103"],
12281   "map": {"at": 227532, "to": "mm"},
12282   "name": "SDMA1_PERFCOUNTER1_SELECT1",
12283   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12284  },
12285  {
12286   "chips": ["gfx103"],
12287   "map": {"at": 227552, "to": "mm"},
12288   "name": "SDMA2_PERFCNT_PERFCOUNTER0_CFG",
12289   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12290  },
12291  {
12292   "chips": ["gfx103"],
12293   "map": {"at": 227556, "to": "mm"},
12294   "name": "SDMA2_PERFCNT_PERFCOUNTER1_CFG",
12295   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12296  },
12297  {
12298   "chips": ["gfx103"],
12299   "map": {"at": 227560, "to": "mm"},
12300   "name": "SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL",
12301   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
12302  },
12303  {
12304   "chips": ["gfx103"],
12305   "map": {"at": 227564, "to": "mm"},
12306   "name": "SDMA2_PERFCNT_MISC_CNTL",
12307   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
12308  },
12309  {
12310   "chips": ["gfx103"],
12311   "map": {"at": 227568, "to": "mm"},
12312   "name": "SDMA2_PERFCOUNTER0_SELECT",
12313   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12314  },
12315  {
12316   "chips": ["gfx103"],
12317   "map": {"at": 227572, "to": "mm"},
12318   "name": "SDMA2_PERFCOUNTER0_SELECT1",
12319   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12320  },
12321  {
12322   "chips": ["gfx103"],
12323   "map": {"at": 227576, "to": "mm"},
12324   "name": "SDMA2_PERFCOUNTER1_SELECT",
12325   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12326  },
12327  {
12328   "chips": ["gfx103"],
12329   "map": {"at": 227580, "to": "mm"},
12330   "name": "SDMA2_PERFCOUNTER1_SELECT1",
12331   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12332  },
12333  {
12334   "chips": ["gfx103"],
12335   "map": {"at": 227600, "to": "mm"},
12336   "name": "SDMA3_PERFCNT_PERFCOUNTER0_CFG",
12337   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12338  },
12339  {
12340   "chips": ["gfx103"],
12341   "map": {"at": 227604, "to": "mm"},
12342   "name": "SDMA3_PERFCNT_PERFCOUNTER1_CFG",
12343   "type_ref": "GCEA_PERFCOUNTER0_CFG"
12344  },
12345  {
12346   "chips": ["gfx103"],
12347   "map": {"at": 227608, "to": "mm"},
12348   "name": "SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL",
12349   "type_ref": "GCEA_PERFCOUNTER_RSLT_CNTL"
12350  },
12351  {
12352   "chips": ["gfx103"],
12353   "map": {"at": 227612, "to": "mm"},
12354   "name": "SDMA3_PERFCNT_MISC_CNTL",
12355   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
12356  },
12357  {
12358   "chips": ["gfx103"],
12359   "map": {"at": 227616, "to": "mm"},
12360   "name": "SDMA3_PERFCOUNTER0_SELECT",
12361   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12362  },
12363  {
12364   "chips": ["gfx103"],
12365   "map": {"at": 227620, "to": "mm"},
12366   "name": "SDMA3_PERFCOUNTER0_SELECT1",
12367   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12368  },
12369  {
12370   "chips": ["gfx103"],
12371   "map": {"at": 227624, "to": "mm"},
12372   "name": "SDMA3_PERFCOUNTER1_SELECT",
12373   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
12374  },
12375  {
12376   "chips": ["gfx103"],
12377   "map": {"at": 227628, "to": "mm"},
12378   "name": "SDMA3_PERFCOUNTER1_SELECT1",
12379   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
12380  }
12381 ],
12382 "register_types": {
12383  "CB_BLEND0_CONTROL": {
12384   "fields": [
12385    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
12386    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
12387    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
12388    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
12389    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
12390    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
12391    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
12392    {"bits": [30, 30], "name": "ENABLE"},
12393    {"bits": [31, 31], "name": "DISABLE_ROP3"}
12394   ]
12395  },
12396  "CB_BLEND_ALPHA": {
12397   "fields": [
12398    {"bits": [0, 31], "name": "BLEND_ALPHA"}
12399   ]
12400  },
12401  "CB_BLEND_BLUE": {
12402   "fields": [
12403    {"bits": [0, 31], "name": "BLEND_BLUE"}
12404   ]
12405  },
12406  "CB_BLEND_GREEN": {
12407   "fields": [
12408    {"bits": [0, 31], "name": "BLEND_GREEN"}
12409   ]
12410  },
12411  "CB_BLEND_RED": {
12412   "fields": [
12413    {"bits": [0, 31], "name": "BLEND_RED"}
12414   ]
12415  },
12416  "CB_COLOR0_ATTRIB": {
12417   "fields": [
12418    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
12419    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
12420    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
12421    {"bits": [12, 14], "name": "NUM_SAMPLES"},
12422    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
12423    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"},
12424    {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"},
12425    {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"}
12426   ]
12427  },
12428  "CB_COLOR0_ATTRIB2": {
12429   "fields": [
12430    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
12431    {"bits": [14, 27], "name": "MIP0_WIDTH"},
12432    {"bits": [28, 31], "name": "MAX_MIP"}
12433   ]
12434  },
12435  "CB_COLOR0_ATTRIB3": {
12436   "fields": [
12437    {"bits": [0, 12], "name": "MIP0_DEPTH"},
12438    {"bits": [13, 13], "name": "META_LINEAR"},
12439    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
12440    {"bits": [19, 23], "name": "FMASK_SW_MODE"},
12441    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
12442    {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"},
12443    {"bits": [27, 29], "name": "RESOURCE_LEVEL"},
12444    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"},
12445    {"bits": [31, 31], "name": "VRS_RATE_HINT_ENABLE"}
12446   ]
12447  },
12448  "CB_COLOR0_BASE_EXT": {
12449   "fields": [
12450    {"bits": [0, 7], "name": "BASE_256B"}
12451   ]
12452  },
12453  "CB_COLOR0_CLEAR_WORD0": {
12454   "fields": [
12455    {"bits": [0, 31], "name": "CLEAR_WORD0"}
12456   ]
12457  },
12458  "CB_COLOR0_CLEAR_WORD1": {
12459   "fields": [
12460    {"bits": [0, 31], "name": "CLEAR_WORD1"}
12461   ]
12462  },
12463  "CB_COLOR0_CMASK_SLICE": {
12464   "fields": [
12465    {"bits": [0, 13], "name": "TILE_MAX"}
12466   ]
12467  },
12468  "CB_COLOR0_DCC_CONTROL": {
12469   "fields": [
12470    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12471    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
12472    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
12473    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
12474    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
12475    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
12476    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
12477    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
12478    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"},
12479    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12480    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
12481    {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"},
12482    {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"},
12483    {"bits": [22, 22], "name": "DCC_COMPRESS_DISABLE"}
12484   ]
12485  },
12486  "CB_COLOR0_INFO": {
12487   "fields": [
12488    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
12489    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
12490    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
12491    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
12492    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
12493    {"bits": [13, 13], "name": "FAST_CLEAR"},
12494    {"bits": [14, 14], "name": "COMPRESSION"},
12495    {"bits": [15, 15], "name": "BLEND_CLAMP"},
12496    {"bits": [16, 16], "name": "BLEND_BYPASS"},
12497    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
12498    {"bits": [18, 18], "name": "ROUND_MODE"},
12499    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
12500    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
12501    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
12502    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
12503    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
12504    {"bits": [28, 28], "name": "DCC_ENABLE"},
12505    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"},
12506    {"bits": [31, 31], "name": "NBC_TILING"}
12507   ]
12508  },
12509  "CB_COLOR0_PITCH": {
12510   "fields": [
12511    {"bits": [0, 10], "name": "TILE_MAX"},
12512    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
12513   ]
12514  },
12515  "CB_COLOR0_SLICE": {
12516   "fields": [
12517    {"bits": [0, 21], "name": "TILE_MAX"}
12518   ]
12519  },
12520  "CB_COLOR0_VIEW": {
12521   "fields": [
12522    {"bits": [0, 12], "name": "SLICE_START"},
12523    {"bits": [13, 25], "name": "SLICE_MAX"},
12524    {"bits": [26, 29], "name": "MIP_LEVEL"}
12525   ]
12526  },
12527  "CB_COLOR_CONTROL": {
12528   "fields": [
12529    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
12530    {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"},
12531    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
12532    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
12533    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
12534   ]
12535  },
12536  "CB_COVERAGE_OUT_CONTROL": {
12537   "fields": [
12538    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
12539    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
12540    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
12541    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
12542   ]
12543  },
12544  "CB_DCC_CONTROL": {
12545   "fields": [
12546    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
12547    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"},
12548    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
12549    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
12550    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
12551    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
12552    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
12553    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
12554   ]
12555  },
12556  "CB_PERFCOUNTER0_SELECT": {
12557   "fields": [
12558    {"bits": [0, 8], "name": "PERF_SEL"},
12559    {"bits": [10, 18], "name": "PERF_SEL1"},
12560    {"bits": [20, 23], "name": "CNTR_MODE"},
12561    {"bits": [24, 27], "name": "PERF_MODE1"},
12562    {"bits": [28, 31], "name": "PERF_MODE"}
12563   ]
12564  },
12565  "CB_PERFCOUNTER0_SELECT1": {
12566   "fields": [
12567    {"bits": [0, 8], "name": "PERF_SEL2"},
12568    {"bits": [10, 18], "name": "PERF_SEL3"},
12569    {"bits": [24, 27], "name": "PERF_MODE3"},
12570    {"bits": [28, 31], "name": "PERF_MODE2"}
12571   ]
12572  },
12573  "CB_PERFCOUNTER1_SELECT": {
12574   "fields": [
12575    {"bits": [0, 8], "name": "PERF_SEL"},
12576    {"bits": [28, 31], "name": "PERF_MODE"}
12577   ]
12578  },
12579  "CB_PERFCOUNTER_FILTER": {
12580   "fields": [
12581    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
12582    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
12583    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
12584    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
12585    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
12586    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
12587    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
12588    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
12589    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
12590    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
12591    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
12592    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
12593   ]
12594  },
12595  "CB_RMI_GL2_CACHE_CONTROL": {
12596   "fields": [
12597    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"},
12598    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"},
12599    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
12600    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
12601    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"},
12602    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"},
12603    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
12604    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
12605    {"bits": [24, 24], "name": "CMASK_L3_BYPASS"},
12606    {"bits": [25, 25], "name": "FMASK_L3_BYPASS"},
12607    {"bits": [26, 26], "name": "DCC_L3_BYPASS"},
12608    {"bits": [27, 27], "name": "COLOR_L3_BYPASS"},
12609    {"bits": [30, 30], "name": "FMASK_BIG_PAGE"},
12610    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
12611   ]
12612  },
12613  "CB_SHADER_MASK": {
12614   "fields": [
12615    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
12616    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
12617    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
12618    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
12619    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
12620    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
12621    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
12622    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
12623   ]
12624  },
12625  "CB_TARGET_MASK": {
12626   "fields": [
12627    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
12628    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
12629    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
12630    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
12631    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
12632    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
12633    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
12634    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
12635   ]
12636  },
12637  "COHER_DEST_BASE_2": {
12638   "fields": [
12639    {"bits": [0, 31], "name": "DEST_BASE_256B"}
12640   ]
12641  },
12642  "COHER_DEST_BASE_HI_0": {
12643   "fields": [
12644    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
12645   ]
12646  },
12647  "COMPUTE_DDID_INDEX": {
12648   "fields": [
12649    {"bits": [0, 10], "name": "INDEX"}
12650   ]
12651  },
12652  "COMPUTE_DESTINATION_EN_SE0": {
12653   "fields": [
12654    {"bits": [0, 31], "name": "CU_EN"}
12655   ]
12656  },
12657  "COMPUTE_DIM_X": {
12658   "fields": [
12659    {"bits": [0, 31], "name": "SIZE"}
12660   ]
12661  },
12662  "COMPUTE_DISPATCH_ID": {
12663   "fields": [
12664    {"bits": [0, 31], "name": "DISPATCH_ID"}
12665   ]
12666  },
12667  "COMPUTE_DISPATCH_INITIATOR": {
12668   "fields": [
12669    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
12670    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
12671    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
12672    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
12673    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
12674    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
12675    {"bits": [6, 6], "name": "ORDER_MODE"},
12676    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
12677    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
12678    {"bits": [12, 12], "name": "RESERVED"},
12679    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
12680    {"bits": [14, 14], "name": "RESTORE"},
12681    {"bits": [15, 15], "name": "CS_W32_EN"}
12682   ]
12683  },
12684  "COMPUTE_DISPATCH_TUNNEL": {
12685   "fields": [
12686    {"bits": [0, 9], "name": "OFF_DELAY"},
12687    {"bits": [10, 10], "name": "IMMEDIATE"}
12688   ]
12689  },
12690  "COMPUTE_MISC_RESERVED": {
12691   "fields": [
12692    {"bits": [0, 1], "name": "SEND_SEID"},
12693    {"bits": [2, 2], "name": "RESERVED2"},
12694    {"bits": [3, 3], "name": "RESERVED3"},
12695    {"bits": [4, 4], "name": "RESERVED4"},
12696    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
12697   ]
12698  },
12699  "COMPUTE_NUM_THREAD_X": {
12700   "fields": [
12701    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
12702    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
12703   ]
12704  },
12705  "COMPUTE_PERFCOUNT_ENABLE": {
12706   "fields": [
12707    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
12708   ]
12709  },
12710  "COMPUTE_PGM_HI": {
12711   "fields": [
12712    {"bits": [0, 7], "name": "DATA"}
12713   ]
12714  },
12715  "COMPUTE_PGM_RSRC1": {
12716   "fields": [
12717    {"bits": [0, 5], "name": "VGPRS"},
12718    {"bits": [6, 9], "name": "SGPRS"},
12719    {"bits": [10, 11], "name": "PRIORITY"},
12720    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12721    {"bits": [20, 20], "name": "PRIV"},
12722    {"bits": [21, 21], "name": "DX10_CLAMP"},
12723    {"bits": [23, 23], "name": "IEEE_MODE"},
12724    {"bits": [24, 24], "name": "BULKY"},
12725    {"bits": [26, 26], "name": "FP16_OVFL"},
12726    {"bits": [29, 29], "name": "WGP_MODE"},
12727    {"bits": [30, 30], "name": "MEM_ORDERED"},
12728    {"bits": [31, 31], "name": "FWD_PROGRESS"}
12729   ]
12730  },
12731  "COMPUTE_PGM_RSRC2": {
12732   "fields": [
12733    {"bits": [0, 0], "name": "SCRATCH_EN"},
12734    {"bits": [1, 5], "name": "USER_SGPR"},
12735    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12736    {"bits": [7, 7], "name": "TGID_X_EN"},
12737    {"bits": [8, 8], "name": "TGID_Y_EN"},
12738    {"bits": [9, 9], "name": "TGID_Z_EN"},
12739    {"bits": [10, 10], "name": "TG_SIZE_EN"},
12740    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
12741    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
12742    {"bits": [15, 23], "name": "LDS_SIZE"},
12743    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12744   ]
12745  },
12746  "COMPUTE_PGM_RSRC3": {
12747   "fields": [
12748    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"}
12749   ]
12750  },
12751  "COMPUTE_PIPELINESTAT_ENABLE": {
12752   "fields": [
12753    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
12754   ]
12755  },
12756  "COMPUTE_RELAUNCH": {
12757   "fields": [
12758    {"bits": [0, 29], "name": "PAYLOAD"},
12759    {"bits": [30, 30], "name": "IS_EVENT"},
12760    {"bits": [31, 31], "name": "IS_STATE"}
12761   ]
12762  },
12763  "COMPUTE_REQ_CTRL": {
12764   "fields": [
12765    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
12766    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
12767    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
12768    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
12769    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
12770    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
12771    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
12772    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
12773    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
12774   ]
12775  },
12776  "COMPUTE_RESOURCE_LIMITS": {
12777   "fields": [
12778    {"bits": [0, 9], "name": "WAVES_PER_SH"},
12779    {"bits": [12, 15], "name": "TG_PER_CU"},
12780    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
12781    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
12782    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
12783    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
12784   ]
12785  },
12786  "COMPUTE_RESTART_X": {
12787   "fields": [
12788    {"bits": [0, 31], "name": "RESTART"}
12789   ]
12790  },
12791  "COMPUTE_START_X": {
12792   "fields": [
12793    {"bits": [0, 31], "name": "START"}
12794   ]
12795  },
12796  "COMPUTE_THREADGROUP_ID": {
12797   "fields": [
12798    {"bits": [0, 31], "name": "THREADGROUP_ID"}
12799   ]
12800  },
12801  "COMPUTE_THREAD_TRACE_ENABLE": {
12802   "fields": [
12803    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
12804   ]
12805  },
12806  "COMPUTE_TMPRING_SIZE": {
12807   "fields": [
12808    {"bits": [0, 11], "name": "WAVES"},
12809    {"bits": [12, 24], "name": "WAVESIZE"}
12810   ]
12811  },
12812  "COMPUTE_VMID": {
12813   "fields": [
12814    {"bits": [0, 3], "name": "DATA"}
12815   ]
12816  },
12817  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
12818   "fields": [
12819    {"bits": [0, 15], "name": "ADDR"}
12820   ]
12821  },
12822  "COMPUTE_WAVE_RESTORE_ADDR_LO": {
12823   "fields": [
12824    {"bits": [0, 31], "name": "ADDR"}
12825   ]
12826  },
12827  "CPF_LATENCY_STATS_SELECT": {
12828   "fields": [
12829    {"bits": [0, 3], "name": "INDEX"},
12830    {"bits": [30, 30], "name": "CLEAR"},
12831    {"bits": [31, 31], "name": "ENABLE"}
12832   ]
12833  },
12834  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
12835   "fields": [
12836    {"bits": [0, 2], "name": "INDEX"},
12837    {"bits": [30, 30], "name": "ALWAYS"},
12838    {"bits": [31, 31], "name": "ENABLE"}
12839   ]
12840  },
12841  "CPG_LATENCY_STATS_SELECT": {
12842   "fields": [
12843    {"bits": [0, 4], "name": "INDEX"},
12844    {"bits": [30, 30], "name": "CLEAR"},
12845    {"bits": [31, 31], "name": "ENABLE"}
12846   ]
12847  },
12848  "CPG_PERFCOUNTER0_SELECT1": {
12849   "fields": [
12850    {"bits": [0, 9], "name": "PERF_SEL2"},
12851    {"bits": [10, 19], "name": "PERF_SEL3"},
12852    {"bits": [24, 27], "name": "CNTR_MODE3"},
12853    {"bits": [28, 31], "name": "CNTR_MODE2"}
12854   ]
12855  },
12856  "CPG_PERFCOUNTER1_HI": {
12857   "fields": [
12858    {"bits": [0, 31], "name": "PERFCOUNTER_HI"}
12859   ]
12860  },
12861  "CPG_PERFCOUNTER1_LO": {
12862   "fields": [
12863    {"bits": [0, 31], "name": "PERFCOUNTER_LO"}
12864   ]
12865  },
12866  "CPG_PERFCOUNTER1_SELECT": {
12867   "fields": [
12868    {"bits": [0, 9], "name": "PERF_SEL"},
12869    {"bits": [10, 19], "name": "PERF_SEL1"},
12870    {"bits": [20, 23], "name": "SPM_MODE"},
12871    {"bits": [24, 27], "name": "CNTR_MODE1"},
12872    {"bits": [28, 31], "name": "CNTR_MODE0"}
12873   ]
12874  },
12875  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
12876   "fields": [
12877    {"bits": [0, 4], "name": "INDEX"},
12878    {"bits": [30, 30], "name": "ALWAYS"},
12879    {"bits": [31, 31], "name": "ENABLE"}
12880   ]
12881  },
12882  "CP_APPEND_ADDR_HI": {
12883   "fields": [
12884    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
12885    {"bits": [16, 16], "name": "CS_PS_SEL"},
12886    {"bits": [25, 26], "name": "CACHE_POLICY"},
12887    {"bits": [29, 31], "name": "COMMAND"}
12888   ]
12889  },
12890  "CP_APPEND_ADDR_LO": {
12891   "fields": [
12892    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
12893   ]
12894  },
12895  "CP_APPEND_LAST_CS_FENCE_HI": {
12896   "fields": [
12897    {"bits": [0, 31], "name": "LAST_FENCE"}
12898   ]
12899  },
12900  "CP_CE_COUNTER": {
12901   "fields": [
12902    {"bits": [0, 31], "name": "CONST_ENGINE_COUNT"}
12903   ]
12904  },
12905  "CP_CE_IB1_BASE_HI": {
12906   "fields": [
12907    {"bits": [0, 15], "name": "IB1_BASE_HI"}
12908   ]
12909  },
12910  "CP_CE_IB1_BASE_LO": {
12911   "fields": [
12912    {"bits": [2, 31], "name": "IB1_BASE_LO"}
12913   ]
12914  },
12915  "CP_CE_IB1_BUFSZ": {
12916   "fields": [
12917    {"bits": [0, 19], "name": "IB1_BUFSZ"}
12918   ]
12919  },
12920  "CP_CE_IB1_CMD_BUFSZ": {
12921   "fields": [
12922    {"bits": [0, 19], "name": "IB1_CMD_REQSZ"}
12923   ]
12924  },
12925  "CP_CE_IB1_OFFSET": {
12926   "fields": [
12927    {"bits": [0, 19], "name": "IB1_OFFSET"}
12928   ]
12929  },
12930  "CP_CE_IB2_BASE_HI": {
12931   "fields": [
12932    {"bits": [0, 15], "name": "IB2_BASE_HI"}
12933   ]
12934  },
12935  "CP_CE_IB2_BASE_LO": {
12936   "fields": [
12937    {"bits": [2, 31], "name": "IB2_BASE_LO"}
12938   ]
12939  },
12940  "CP_CE_IB2_BUFSZ": {
12941   "fields": [
12942    {"bits": [0, 19], "name": "IB2_BUFSZ"}
12943   ]
12944  },
12945  "CP_CE_IB2_CMD_BUFSZ": {
12946   "fields": [
12947    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
12948   ]
12949  },
12950  "CP_CE_INIT_BASE_HI": {
12951   "fields": [
12952    {"bits": [0, 15], "name": "INIT_BASE_HI"}
12953   ]
12954  },
12955  "CP_CE_INIT_BASE_LO": {
12956   "fields": [
12957    {"bits": [5, 31], "name": "INIT_BASE_LO"}
12958   ]
12959  },
12960  "CP_CE_INIT_BUFSZ": {
12961   "fields": [
12962    {"bits": [0, 11], "name": "INIT_BUFSZ"}
12963   ]
12964  },
12965  "CP_CE_INIT_CMD_BUFSZ": {
12966   "fields": [
12967    {"bits": [0, 11], "name": "INIT_CMD_REQSZ"}
12968   ]
12969  },
12970  "CP_COHER_BASE": {
12971   "fields": [
12972    {"bits": [0, 31], "name": "COHER_BASE_256B"}
12973   ]
12974  },
12975  "CP_COHER_BASE_HI": {
12976   "fields": [
12977    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
12978   ]
12979  },
12980  "CP_COHER_CNTL": {
12981   "fields": [
12982    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
12983    {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"},
12984    {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"},
12985    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
12986    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
12987    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
12988    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
12989    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
12990    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
12991    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
12992    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
12993    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
12994    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"}
12995   ]
12996  },
12997  "CP_COHER_SIZE": {
12998   "fields": [
12999    {"bits": [0, 31], "name": "COHER_SIZE_256B"}
13000   ]
13001  },
13002  "CP_COHER_SIZE_HI": {
13003   "fields": [
13004    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
13005   ]
13006  },
13007  "CP_COHER_START_DELAY": {
13008   "fields": [
13009    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
13010   ]
13011  },
13012  "CP_COHER_STATUS": {
13013   "fields": [
13014    {"bits": [24, 25], "name": "MEID"},
13015    {"bits": [31, 31], "name": "STATUS"}
13016   ]
13017  },
13018  "CP_CPC_BUSY_STAT": {
13019   "fields": [
13020    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
13021    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
13022    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
13023    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
13024    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
13025    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
13026    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
13027    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
13028    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
13029    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
13030    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
13031    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
13032    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
13033    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
13034    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
13035    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
13036    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
13037    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
13038    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
13039    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
13040    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
13041    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
13042    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
13043    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
13044    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
13045    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
13046    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
13047    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
13048   ]
13049  },
13050  "CP_CPC_BUSY_STAT2": {
13051   "fields": [
13052    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
13053    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
13054    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
13055    {"bits": [7, 7], "name": "MES_TC_BUSY"},
13056    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
13057    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
13058    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
13059    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
13060    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
13061   ]
13062  },
13063  "CP_CPC_GRBM_FREE_COUNT": {
13064   "fields": [
13065    {"bits": [0, 5], "name": "FREE_COUNT"}
13066   ]
13067  },
13068  "CP_CPC_HALT_HYST_COUNT": {
13069   "fields": [
13070    {"bits": [0, 3], "name": "COUNT"}
13071   ]
13072  },
13073  "CP_CPC_PRIV_VIOLATION_ADDR": {
13074   "fields": [
13075    {"bits": [0, 15], "name": "PRIV_VIOLATION_ADDR"}
13076   ]
13077  },
13078  "CP_CPC_SCRATCH_DATA": {
13079   "fields": [
13080    {"bits": [0, 31], "name": "SCRATCH_DATA"}
13081   ]
13082  },
13083  "CP_CPC_SCRATCH_INDEX": {
13084   "fields": [
13085    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
13086    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
13087   ]
13088  },
13089  "CP_CPC_STALLED_STAT1": {
13090   "fields": [
13091    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
13092    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
13093    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
13094    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
13095    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
13096    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
13097    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
13098    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
13099    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
13100    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
13101    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
13102    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
13103    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
13104    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
13105    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
13106   ]
13107  },
13108  "CP_CPC_STATUS": {
13109   "fields": [
13110    {"bits": [0, 0], "name": "MEC1_BUSY"},
13111    {"bits": [1, 1], "name": "MEC2_BUSY"},
13112    {"bits": [2, 2], "name": "DC0_BUSY"},
13113    {"bits": [3, 3], "name": "DC1_BUSY"},
13114    {"bits": [4, 4], "name": "RCIU1_BUSY"},
13115    {"bits": [5, 5], "name": "RCIU2_BUSY"},
13116    {"bits": [6, 6], "name": "ROQ1_BUSY"},
13117    {"bits": [7, 7], "name": "ROQ2_BUSY"},
13118    {"bits": [10, 10], "name": "TCIU_BUSY"},
13119    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
13120    {"bits": [12, 12], "name": "QU_BUSY"},
13121    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
13122    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
13123    {"bits": [15, 15], "name": "GCRIU_BUSY"},
13124    {"bits": [16, 16], "name": "MES_BUSY"},
13125    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
13126    {"bits": [18, 18], "name": "RCIU3_BUSY"},
13127    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
13128    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
13129    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
13130    {"bits": [31, 31], "name": "CPC_BUSY"}
13131   ]
13132  },
13133  "CP_CPF_BUSY_STAT": {
13134   "fields": [
13135    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
13136    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
13137    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
13138    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
13139    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
13140    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
13141    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
13142    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
13143    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
13144    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
13145    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
13146    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
13147    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
13148    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
13149    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
13150    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
13151    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
13152    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
13153    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
13154    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
13155    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
13156    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
13157    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
13158    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
13159    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
13160    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
13161    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
13162    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
13163    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
13164    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
13165    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
13166    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
13167   ]
13168  },
13169  "CP_CPF_BUSY_STAT2": {
13170   "fields": [
13171    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
13172    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
13173    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
13174    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
13175    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
13176    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
13177    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
13178    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
13179    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
13180   ]
13181  },
13182  "CP_CPF_GRBM_FREE_COUNT": {
13183   "fields": [
13184    {"bits": [0, 2], "name": "FREE_COUNT"}
13185   ]
13186  },
13187  "CP_CPF_STALLED_STAT1": {
13188   "fields": [
13189    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
13190    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
13191    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
13192    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
13193    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
13194    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
13195    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
13196    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
13197    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
13198    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
13199    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
13200    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
13201    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
13202   ]
13203  },
13204  "CP_CPF_STATUS": {
13205   "fields": [
13206    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
13207    {"bits": [1, 1], "name": "CSF_BUSY"},
13208    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
13209    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
13210    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
13211    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
13212    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
13213    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
13214    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
13215    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
13216    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
13217    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
13218    {"bits": [14, 14], "name": "TCIU_BUSY"},
13219    {"bits": [15, 15], "name": "HQD_BUSY"},
13220    {"bits": [16, 16], "name": "PRT_BUSY"},
13221    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
13222    {"bits": [18, 18], "name": "RCIU_BUSY"},
13223    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
13224    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
13225    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
13226    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
13227    {"bits": [23, 23], "name": "GCRIU_BUSY"},
13228    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
13229    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
13230    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
13231    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
13232    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
13233    {"bits": [31, 31], "name": "CPF_BUSY"}
13234   ]
13235  },
13236  "CP_DB_BASE_HI": {
13237   "fields": [
13238    {"bits": [0, 15], "name": "DB_BASE_HI"}
13239   ]
13240  },
13241  "CP_DB_BASE_LO": {
13242   "fields": [
13243    {"bits": [2, 31], "name": "DB_BASE_LO"}
13244   ]
13245  },
13246  "CP_DB_BUFSZ": {
13247   "fields": [
13248    {"bits": [0, 19], "name": "DB_BUFSZ"}
13249   ]
13250  },
13251  "CP_DB_CMD_BUFSZ": {
13252   "fields": [
13253    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
13254   ]
13255  },
13256  "CP_DMA_CNTL": {
13257   "fields": [
13258    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
13259    {"bits": [1, 1], "name": "WATCH_CONTROL"},
13260    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
13261    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
13262    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
13263    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
13264    {"bits": [30, 31], "name": "PIO_COUNT"}
13265   ]
13266  },
13267  "CP_DMA_ME_CMD_ADDR_HI": {
13268   "fields": [
13269    {"bits": [0, 15], "name": "ADDR_HI"},
13270    {"bits": [16, 31], "name": "RSVD"}
13271   ]
13272  },
13273  "CP_DMA_ME_CMD_ADDR_LO": {
13274   "fields": [
13275    {"bits": [0, 1], "name": "RSVD"},
13276    {"bits": [2, 31], "name": "ADDR_LO"}
13277   ]
13278  },
13279  "CP_DMA_ME_COMMAND": {
13280   "fields": [
13281    {"bits": [0, 25], "name": "BYTE_COUNT"},
13282    {"bits": [26, 26], "name": "SAS"},
13283    {"bits": [27, 27], "name": "DAS"},
13284    {"bits": [28, 28], "name": "SAIC"},
13285    {"bits": [29, 29], "name": "DAIC"},
13286    {"bits": [30, 30], "name": "RAW_WAIT"},
13287    {"bits": [31, 31], "name": "DIS_WC"}
13288   ]
13289  },
13290  "CP_DMA_ME_DST_ADDR": {
13291   "fields": [
13292    {"bits": [0, 31], "name": "DST_ADDR"}
13293   ]
13294  },
13295  "CP_DMA_ME_DST_ADDR_HI": {
13296   "fields": [
13297    {"bits": [0, 15], "name": "DST_ADDR_HI"}
13298   ]
13299  },
13300  "CP_DMA_ME_SRC_ADDR": {
13301   "fields": [
13302    {"bits": [0, 31], "name": "SRC_ADDR"}
13303   ]
13304  },
13305  "CP_DMA_ME_SRC_ADDR_HI": {
13306   "fields": [
13307    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
13308   ]
13309  },
13310  "CP_DMA_PFP_CONTROL": {
13311   "fields": [
13312    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
13313    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
13314    {"bits": [15, 15], "name": "SRC_VOLATLE"},
13315    {"bits": [20, 21], "name": "DST_SELECT"},
13316    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
13317    {"bits": [27, 27], "name": "DST_VOLATLE"},
13318    {"bits": [29, 30], "name": "SRC_SELECT"}
13319   ]
13320  },
13321  "CP_DMA_READ_TAGS": {
13322   "fields": [
13323    {"bits": [0, 25], "name": "DMA_READ_TAG"},
13324    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
13325   ]
13326  },
13327  "CP_DRAW_OBJECT": {
13328   "fields": [
13329    {"bits": [0, 31], "name": "OBJECT"}
13330   ]
13331  },
13332  "CP_DRAW_WINDOW_CNTL": {
13333   "fields": [
13334    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
13335    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
13336    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
13337    {"bits": [8, 8], "name": "MODE"}
13338   ]
13339  },
13340  "CP_DRAW_WINDOW_HI": {
13341   "fields": [
13342    {"bits": [0, 31], "name": "WINDOW_HI"}
13343   ]
13344  },
13345  "CP_DRAW_WINDOW_LO": {
13346   "fields": [
13347    {"bits": [0, 15], "name": "MIN"},
13348    {"bits": [16, 31], "name": "MAX"}
13349   ]
13350  },
13351  "CP_DRAW_WINDOW_MASK_HI": {
13352   "fields": [
13353    {"bits": [0, 31], "name": "WINDOW_MASK_HI"}
13354   ]
13355  },
13356  "CP_EOP_DONE_ADDR_HI": {
13357   "fields": [
13358    {"bits": [0, 15], "name": "ADDR_HI"}
13359   ]
13360  },
13361  "CP_EOP_DONE_ADDR_LO": {
13362   "fields": [
13363    {"bits": [2, 31], "name": "ADDR_LO"}
13364   ]
13365  },
13366  "CP_EOP_DONE_CNTX_ID": {
13367   "fields": [
13368    {"bits": [0, 31], "name": "CNTX_ID"}
13369   ]
13370  },
13371  "CP_EOP_DONE_DATA_CNTL": {
13372   "fields": [
13373    {"bits": [16, 17], "name": "DST_SEL"},
13374    {"bits": [20, 21], "name": "ACTION_PIPE_ID"},
13375    {"bits": [22, 23], "name": "ACTION_ID"},
13376    {"bits": [24, 26], "name": "INT_SEL"},
13377    {"bits": [29, 31], "name": "DATA_SEL"}
13378   ]
13379  },
13380  "CP_EOP_DONE_DATA_HI": {
13381   "fields": [
13382    {"bits": [0, 31], "name": "DATA_HI"}
13383   ]
13384  },
13385  "CP_EOP_DONE_DATA_LO": {
13386   "fields": [
13387    {"bits": [0, 31], "name": "DATA_LO"}
13388   ]
13389  },
13390  "CP_EOP_DONE_EVENT_CNTL": {
13391   "fields": [
13392    {"bits": [12, 23], "name": "GCR_CNTL"},
13393    {"bits": [25, 26], "name": "CACHE_POLICY"},
13394    {"bits": [27, 27], "name": "EOP_VOLATILE"},
13395    {"bits": [28, 28], "name": "EXECUTE"}
13396   ]
13397  },
13398  "CP_EOP_LAST_FENCE_HI": {
13399   "fields": [
13400    {"bits": [0, 31], "name": "LAST_FENCE_HI"}
13401   ]
13402  },
13403  "CP_EOP_LAST_FENCE_LO": {
13404   "fields": [
13405    {"bits": [0, 31], "name": "LAST_FENCE_LO"}
13406   ]
13407  },
13408  "CP_IB2_OFFSET": {
13409   "fields": [
13410    {"bits": [0, 19], "name": "IB2_OFFSET"}
13411   ]
13412  },
13413  "CP_IB2_PREAMBLE_BEGIN": {
13414   "fields": [
13415    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
13416   ]
13417  },
13418  "CP_IB2_PREAMBLE_END": {
13419   "fields": [
13420    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
13421   ]
13422  },
13423  "CP_INDEX_TYPE": {
13424   "fields": [
13425    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
13426   ]
13427  },
13428  "CP_ME_COHER_CNTL": {
13429   "fields": [
13430    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
13431    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
13432    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
13433    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
13434    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
13435    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
13436    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
13437    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
13438    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
13439    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
13440    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
13441    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
13442    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
13443   ]
13444  },
13445  "CP_ME_COHER_STATUS": {
13446   "fields": [
13447    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
13448    {"bits": [31, 31], "name": "STATUS"}
13449   ]
13450  },
13451  "CP_ME_MC_RADDR_HI": {
13452   "fields": [
13453    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
13454    {"bits": [22, 23], "name": "CACHE_POLICY"}
13455   ]
13456  },
13457  "CP_ME_MC_RADDR_LO": {
13458   "fields": [
13459    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
13460   ]
13461  },
13462  "CP_ME_MC_WADDR_HI": {
13463   "fields": [
13464    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
13465    {"bits": [22, 23], "name": "CACHE_POLICY"}
13466   ]
13467  },
13468  "CP_ME_MC_WADDR_LO": {
13469   "fields": [
13470    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
13471   ]
13472  },
13473  "CP_ME_MC_WDATA_HI": {
13474   "fields": [
13475    {"bits": [0, 31], "name": "ME_MC_WDATA_HI"}
13476   ]
13477  },
13478  "CP_ME_MC_WDATA_LO": {
13479   "fields": [
13480    {"bits": [0, 31], "name": "ME_MC_WDATA_LO"}
13481   ]
13482  },
13483  "CP_NUM_PRIM_NEEDED_COUNT0_HI": {
13484   "fields": [
13485    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"}
13486   ]
13487  },
13488  "CP_NUM_PRIM_NEEDED_COUNT0_LO": {
13489   "fields": [
13490    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"}
13491   ]
13492  },
13493  "CP_NUM_PRIM_NEEDED_COUNT1_HI": {
13494   "fields": [
13495    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"}
13496   ]
13497  },
13498  "CP_NUM_PRIM_NEEDED_COUNT1_LO": {
13499   "fields": [
13500    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"}
13501   ]
13502  },
13503  "CP_NUM_PRIM_NEEDED_COUNT2_HI": {
13504   "fields": [
13505    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"}
13506   ]
13507  },
13508  "CP_NUM_PRIM_NEEDED_COUNT2_LO": {
13509   "fields": [
13510    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"}
13511   ]
13512  },
13513  "CP_NUM_PRIM_NEEDED_COUNT3_HI": {
13514   "fields": [
13515    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"}
13516   ]
13517  },
13518  "CP_NUM_PRIM_NEEDED_COUNT3_LO": {
13519   "fields": [
13520    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"}
13521   ]
13522  },
13523  "CP_NUM_PRIM_WRITTEN_COUNT0_HI": {
13524   "fields": [
13525    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"}
13526   ]
13527  },
13528  "CP_NUM_PRIM_WRITTEN_COUNT0_LO": {
13529   "fields": [
13530    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"}
13531   ]
13532  },
13533  "CP_NUM_PRIM_WRITTEN_COUNT1_HI": {
13534   "fields": [
13535    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"}
13536   ]
13537  },
13538  "CP_NUM_PRIM_WRITTEN_COUNT1_LO": {
13539   "fields": [
13540    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"}
13541   ]
13542  },
13543  "CP_NUM_PRIM_WRITTEN_COUNT2_HI": {
13544   "fields": [
13545    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"}
13546   ]
13547  },
13548  "CP_NUM_PRIM_WRITTEN_COUNT2_LO": {
13549   "fields": [
13550    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"}
13551   ]
13552  },
13553  "CP_NUM_PRIM_WRITTEN_COUNT3_HI": {
13554   "fields": [
13555    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"}
13556   ]
13557  },
13558  "CP_NUM_PRIM_WRITTEN_COUNT3_LO": {
13559   "fields": [
13560    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"}
13561   ]
13562  },
13563  "CP_PA_CINVOC_COUNT_HI": {
13564   "fields": [
13565    {"bits": [0, 31], "name": "CINVOC_COUNT_HI"}
13566   ]
13567  },
13568  "CP_PA_CINVOC_COUNT_LO": {
13569   "fields": [
13570    {"bits": [0, 31], "name": "CINVOC_COUNT_LO"}
13571   ]
13572  },
13573  "CP_PA_CPRIM_COUNT_HI": {
13574   "fields": [
13575    {"bits": [0, 31], "name": "CPRIM_COUNT_HI"}
13576   ]
13577  },
13578  "CP_PA_CPRIM_COUNT_LO": {
13579   "fields": [
13580    {"bits": [0, 31], "name": "CPRIM_COUNT_LO"}
13581   ]
13582  },
13583  "CP_PERFMON_CNTL": {
13584   "fields": [
13585    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13586    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
13587    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
13588    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13589   ]
13590  },
13591  "CP_PERFMON_CNTX_CNTL": {
13592   "fields": [
13593    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
13594   ]
13595  },
13596  "CP_PFP_ATOMIC_PREOP_HI": {
13597   "fields": [
13598    {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"}
13599   ]
13600  },
13601  "CP_PFP_ATOMIC_PREOP_LO": {
13602   "fields": [
13603    {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"}
13604   ]
13605  },
13606  "CP_PFP_COMPLETION_STATUS": {
13607   "fields": [
13608    {"bits": [0, 1], "name": "STATUS"}
13609   ]
13610  },
13611  "CP_PFP_GDS_ATOMIC0_PREOP_HI": {
13612   "fields": [
13613    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"}
13614   ]
13615  },
13616  "CP_PFP_GDS_ATOMIC0_PREOP_LO": {
13617   "fields": [
13618    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"}
13619   ]
13620  },
13621  "CP_PFP_GDS_ATOMIC1_PREOP_HI": {
13622   "fields": [
13623    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"}
13624   ]
13625  },
13626  "CP_PFP_GDS_ATOMIC1_PREOP_LO": {
13627   "fields": [
13628    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"}
13629   ]
13630  },
13631  "CP_PFP_IB_CONTROL": {
13632   "fields": [
13633    {"bits": [0, 7], "name": "IB_EN"}
13634   ]
13635  },
13636  "CP_PFP_LOAD_CONTROL": {
13637   "fields": [
13638    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
13639    {"bits": [1, 1], "name": "CNTX_REG_EN"},
13640    {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
13641    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
13642    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
13643   ]
13644  },
13645  "CP_PFP_METADATA_BASE_ADDR": {
13646   "fields": [
13647    {"bits": [0, 31], "name": "ADDR_LO"}
13648   ]
13649  },
13650  "CP_PIPEID": {
13651   "fields": [
13652    {"bits": [0, 1], "name": "PIPE_ID"}
13653   ]
13654  },
13655  "CP_PIPE_STATS_ADDR_HI": {
13656   "fields": [
13657    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
13658   ]
13659  },
13660  "CP_PIPE_STATS_ADDR_LO": {
13661   "fields": [
13662    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
13663   ]
13664  },
13665  "CP_PIPE_STATS_CONTROL": {
13666   "fields": [
13667    {"bits": [25, 26], "name": "CACHE_POLICY"}
13668   ]
13669  },
13670  "CP_PRED_NOT_VISIBLE": {
13671   "fields": [
13672    {"bits": [0, 0], "name": "NOT_VISIBLE"}
13673   ]
13674  },
13675  "CP_RB_OFFSET": {
13676   "fields": [
13677    {"bits": [0, 19], "name": "RB_OFFSET"}
13678   ]
13679  },
13680  "CP_SAMPLE_STATUS": {
13681   "fields": [
13682    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
13683    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
13684    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
13685    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
13686    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
13687    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
13688    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
13689    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
13690   ]
13691  },
13692  "CP_SC_PSINVOC_COUNT0_HI": {
13693   "fields": [
13694    {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"}
13695   ]
13696  },
13697  "CP_SC_PSINVOC_COUNT0_LO": {
13698   "fields": [
13699    {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"}
13700   ]
13701  },
13702  "CP_SC_PSINVOC_COUNT1_LO": {
13703   "fields": [
13704    {"bits": [0, 31], "name": "OBSOLETE"}
13705   ]
13706  },
13707  "CP_SEM_WAIT_TIMER": {
13708   "fields": [
13709    {"bits": [0, 31], "name": "SEM_WAIT_TIMER"}
13710   ]
13711  },
13712  "CP_SIG_SEM_ADDR_HI": {
13713   "fields": [
13714    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
13715    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
13716    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
13717    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
13718    {"bits": [29, 31], "name": "SEM_SELECT"}
13719   ]
13720  },
13721  "CP_SIG_SEM_ADDR_LO": {
13722   "fields": [
13723    {"bits": [0, 0], "name": "SEM_PRIV"},
13724    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
13725   ]
13726  },
13727  "CP_STREAM_OUT_ADDR_HI": {
13728   "fields": [
13729    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
13730   ]
13731  },
13732  "CP_STREAM_OUT_ADDR_LO": {
13733   "fields": [
13734    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
13735   ]
13736  },
13737  "CP_STRMOUT_CNTL": {
13738   "fields": [
13739    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
13740   ]
13741  },
13742  "CP_ST_BASE_HI": {
13743   "fields": [
13744    {"bits": [0, 15], "name": "ST_BASE_HI"}
13745   ]
13746  },
13747  "CP_ST_BASE_LO": {
13748   "fields": [
13749    {"bits": [2, 31], "name": "ST_BASE_LO"}
13750   ]
13751  },
13752  "CP_ST_BUFSZ": {
13753   "fields": [
13754    {"bits": [0, 19], "name": "ST_BUFSZ"}
13755   ]
13756  },
13757  "CP_ST_CMD_BUFSZ": {
13758   "fields": [
13759    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
13760   ]
13761  },
13762  "CP_VGT_CSINVOC_COUNT_HI": {
13763   "fields": [
13764    {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"}
13765   ]
13766  },
13767  "CP_VGT_CSINVOC_COUNT_LO": {
13768   "fields": [
13769    {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"}
13770   ]
13771  },
13772  "CP_VGT_DSINVOC_COUNT_HI": {
13773   "fields": [
13774    {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"}
13775   ]
13776  },
13777  "CP_VGT_DSINVOC_COUNT_LO": {
13778   "fields": [
13779    {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"}
13780   ]
13781  },
13782  "CP_VGT_GSINVOC_COUNT_HI": {
13783   "fields": [
13784    {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"}
13785   ]
13786  },
13787  "CP_VGT_GSINVOC_COUNT_LO": {
13788   "fields": [
13789    {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"}
13790   ]
13791  },
13792  "CP_VGT_GSPRIM_COUNT_HI": {
13793   "fields": [
13794    {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"}
13795   ]
13796  },
13797  "CP_VGT_GSPRIM_COUNT_LO": {
13798   "fields": [
13799    {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"}
13800   ]
13801  },
13802  "CP_VGT_HSINVOC_COUNT_HI": {
13803   "fields": [
13804    {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"}
13805   ]
13806  },
13807  "CP_VGT_HSINVOC_COUNT_LO": {
13808   "fields": [
13809    {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"}
13810   ]
13811  },
13812  "CP_VGT_IAPRIM_COUNT_HI": {
13813   "fields": [
13814    {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"}
13815   ]
13816  },
13817  "CP_VGT_IAPRIM_COUNT_LO": {
13818   "fields": [
13819    {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"}
13820   ]
13821  },
13822  "CP_VGT_IAVERT_COUNT_HI": {
13823   "fields": [
13824    {"bits": [0, 31], "name": "IAVERT_COUNT_HI"}
13825   ]
13826  },
13827  "CP_VGT_IAVERT_COUNT_LO": {
13828   "fields": [
13829    {"bits": [0, 31], "name": "IAVERT_COUNT_LO"}
13830   ]
13831  },
13832  "CP_VGT_VSINVOC_COUNT_HI": {
13833   "fields": [
13834    {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"}
13835   ]
13836  },
13837  "CP_VGT_VSINVOC_COUNT_LO": {
13838   "fields": [
13839    {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"}
13840   ]
13841  },
13842  "CP_VMID": {
13843   "fields": [
13844    {"bits": [0, 3], "name": "VMID"}
13845   ]
13846  },
13847  "CP_WAIT_REG_MEM_TIMEOUT": {
13848   "fields": [
13849    {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"}
13850   ]
13851  },
13852  "CS_COPY_STATE": {
13853   "fields": [
13854    {"bits": [0, 2], "name": "SRC_STATE_ID"}
13855   ]
13856  },
13857  "DB_ALPHA_TO_MASK": {
13858   "fields": [
13859    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
13860    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
13861    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
13862    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
13863    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
13864    {"bits": [16, 16], "name": "OFFSET_ROUND"}
13865   ]
13866  },
13867  "DB_COUNT_CONTROL": {
13868   "fields": [
13869    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
13870    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
13871    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
13872    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
13873    {"bits": [4, 6], "name": "SAMPLE_RATE"},
13874    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
13875    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
13876    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
13877    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
13878    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
13879    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
13880   ]
13881  },
13882  "DB_DEPTH_BOUNDS_MAX": {
13883   "fields": [
13884    {"bits": [0, 31], "name": "MAX"}
13885   ]
13886  },
13887  "DB_DEPTH_BOUNDS_MIN": {
13888   "fields": [
13889    {"bits": [0, 31], "name": "MIN"}
13890   ]
13891  },
13892  "DB_DEPTH_CLEAR": {
13893   "fields": [
13894    {"bits": [0, 31], "name": "DEPTH_CLEAR"}
13895   ]
13896  },
13897  "DB_DEPTH_CONTROL": {
13898   "fields": [
13899    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
13900    {"bits": [1, 1], "name": "Z_ENABLE"},
13901    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
13902    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
13903    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
13904    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
13905    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
13906    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
13907    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
13908    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
13909   ]
13910  },
13911  "DB_DEPTH_SIZE_XY": {
13912   "fields": [
13913    {"bits": [0, 13], "name": "X_MAX"},
13914    {"bits": [16, 29], "name": "Y_MAX"}
13915   ]
13916  },
13917  "DB_DEPTH_VIEW": {
13918   "fields": [
13919    {"bits": [0, 10], "name": "SLICE_START"},
13920    {"bits": [11, 12], "name": "SLICE_START_HI"},
13921    {"bits": [13, 23], "name": "SLICE_MAX"},
13922    {"bits": [24, 24], "name": "Z_READ_ONLY"},
13923    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
13924    {"bits": [26, 29], "name": "MIPID"},
13925    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
13926   ]
13927  },
13928  "DB_DFSM_CONTROL": {
13929   "fields": [
13930    {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"},
13931    {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"},
13932    {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"}
13933   ]
13934  },
13935  "DB_EQAA": {
13936   "fields": [
13937    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
13938    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
13939    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
13940    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
13941    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
13942    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
13943    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
13944    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
13945    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
13946    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
13947    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
13948    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
13949   ]
13950  },
13951  "DB_HTILE_DATA_BASE": {
13952   "fields": [
13953    {"bits": [0, 31], "name": "BASE_256B"}
13954   ]
13955  },
13956  "DB_HTILE_SURFACE": {
13957   "fields": [
13958    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
13959    {"bits": [1, 1], "name": "FULL_CACHE"},
13960    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
13961    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
13962    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
13963    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
13964    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
13965    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
13966    {"bits": [18, 18], "name": "PIPE_ALIGNED"},
13967    {"bits": [19, 20], "name": "VRS_HTILE_ENCODING"}
13968   ]
13969  },
13970  "DB_OCCLUSION_COUNT0_HI": {
13971   "fields": [
13972    {"bits": [0, 30], "name": "COUNT_HI"}
13973   ]
13974  },
13975  "DB_OCCLUSION_COUNT0_LOW": {
13976   "fields": [
13977    {"bits": [0, 31], "name": "COUNT_LOW"}
13978   ]
13979  },
13980  "DB_PRELOAD_CONTROL": {
13981   "fields": [
13982    {"bits": [0, 7], "name": "START_X"},
13983    {"bits": [8, 15], "name": "START_Y"},
13984    {"bits": [16, 23], "name": "MAX_X"},
13985    {"bits": [24, 31], "name": "MAX_Y"}
13986   ]
13987  },
13988  "DB_RENDER_CONTROL": {
13989   "fields": [
13990    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
13991    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
13992    {"bits": [2, 2], "name": "DEPTH_COPY"},
13993    {"bits": [3, 3], "name": "STENCIL_COPY"},
13994    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
13995    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
13996    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
13997    {"bits": [7, 7], "name": "COPY_CENTROID"},
13998    {"bits": [8, 11], "name": "COPY_SAMPLE"},
13999    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"},
14000    {"bits": [13, 13], "name": "PS_INVOKE_DISABLE"}
14001   ]
14002  },
14003  "DB_RENDER_OVERRIDE": {
14004   "fields": [
14005    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
14006    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
14007    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
14008    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
14009    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
14010    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
14011    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
14012    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
14013    {"bits": [11, 11], "name": "FORCE_Z_READ"},
14014    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
14015    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
14016    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
14017    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
14018    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
14019    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
14020    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
14021    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
14022    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
14023    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
14024    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
14025    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
14026    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
14027    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
14028   ]
14029  },
14030  "DB_RENDER_OVERRIDE2": {
14031   "fields": [
14032    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
14033    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
14034    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
14035    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
14036    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
14037    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
14038    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
14039    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
14040    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
14041    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
14042    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
14043    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
14044    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
14045    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
14046    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
14047    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
14048    {"bits": [26, 26], "name": "FORCE_VRS_RATE_FINE"},
14049    {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"}
14050   ]
14051  },
14052  "DB_RESERVED_REG_1": {
14053   "fields": [
14054    {"bits": [0, 10], "name": "FIELD_1"},
14055    {"bits": [11, 21], "name": "FIELD_2"}
14056   ]
14057  },
14058  "DB_RESERVED_REG_2": {
14059   "fields": [
14060    {"bits": [0, 3], "name": "FIELD_1"},
14061    {"bits": [4, 7], "name": "FIELD_2"},
14062    {"bits": [8, 12], "name": "FIELD_3"},
14063    {"bits": [13, 14], "name": "FIELD_4"},
14064    {"bits": [15, 16], "name": "FIELD_5"},
14065    {"bits": [17, 18], "name": "FIELD_6"},
14066    {"bits": [19, 20], "name": "FIELD_7"},
14067    {"bits": [28, 31], "name": "RESOURCE_LEVEL"}
14068   ]
14069  },
14070  "DB_RESERVED_REG_3": {
14071   "fields": [
14072    {"bits": [0, 21], "name": "FIELD_1"}
14073   ]
14074  },
14075  "DB_RMI_L2_CACHE_CONTROL": {
14076   "fields": [
14077    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
14078    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
14079    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
14080    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
14081    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
14082    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
14083    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
14084    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
14085    {"bits": [25, 25], "name": "S_BIG_PAGE"},
14086    {"bits": [26, 26], "name": "Z_NOALLOC"},
14087    {"bits": [27, 27], "name": "S_NOALLOC"},
14088    {"bits": [28, 28], "name": "HTILE_NOALLOC"},
14089    {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"}
14090   ]
14091  },
14092  "DB_SHADER_CONTROL": {
14093   "fields": [
14094    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
14095    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
14096    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
14097    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
14098    {"bits": [6, 6], "name": "KILL_ENABLE"},
14099    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
14100    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
14101    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
14102    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
14103    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
14104    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
14105    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
14106    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
14107    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
14108    {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"},
14109    {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"},
14110    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"}
14111   ]
14112  },
14113  "DB_SRESULTS_COMPARE_STATE0": {
14114   "fields": [
14115    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
14116    {"bits": [4, 11], "name": "COMPAREVALUE0"},
14117    {"bits": [12, 19], "name": "COMPAREMASK0"},
14118    {"bits": [24, 24], "name": "ENABLE0"}
14119   ]
14120  },
14121  "DB_SRESULTS_COMPARE_STATE1": {
14122   "fields": [
14123    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
14124    {"bits": [4, 11], "name": "COMPAREVALUE1"},
14125    {"bits": [12, 19], "name": "COMPAREMASK1"},
14126    {"bits": [24, 24], "name": "ENABLE1"}
14127   ]
14128  },
14129  "DB_STENCILREFMASK": {
14130   "fields": [
14131    {"bits": [0, 7], "name": "STENCILTESTVAL"},
14132    {"bits": [8, 15], "name": "STENCILMASK"},
14133    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
14134    {"bits": [24, 31], "name": "STENCILOPVAL"}
14135   ]
14136  },
14137  "DB_STENCILREFMASK_BF": {
14138   "fields": [
14139    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
14140    {"bits": [8, 15], "name": "STENCILMASK_BF"},
14141    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
14142    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
14143   ]
14144  },
14145  "DB_STENCIL_CLEAR": {
14146   "fields": [
14147    {"bits": [0, 7], "name": "CLEAR"}
14148   ]
14149  },
14150  "DB_STENCIL_CONTROL": {
14151   "fields": [
14152    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
14153    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
14154    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
14155    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
14156    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
14157    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
14158   ]
14159  },
14160  "DB_STENCIL_INFO": {
14161   "fields": [
14162    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
14163    {"bits": [4, 8], "name": "SW_MODE"},
14164    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14165    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14166    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14167    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14168    {"bits": [20, 20], "name": "ITERATE_256"},
14169    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14170    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
14171   ]
14172  },
14173  "DB_VRS_OVERRIDE_CNTL": {
14174   "fields": [
14175    {"bits": [0, 2], "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"},
14176    {"bits": [4, 5], "name": "VRS_OVERRIDE_RATE_X"},
14177    {"bits": [6, 7], "name": "VRS_OVERRIDE_RATE_Y"}
14178   ]
14179  },
14180  "DB_Z_INFO": {
14181   "fields": [
14182    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
14183    {"bits": [2, 3], "name": "NUM_SAMPLES"},
14184    {"bits": [4, 8], "name": "SW_MODE"},
14185    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
14186    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
14187    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
14188    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
14189    {"bits": [16, 19], "name": "MAXMIP"},
14190    {"bits": [20, 20], "name": "ITERATE_256"},
14191    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
14192    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
14193    {"bits": [28, 28], "name": "READ_SIZE"},
14194    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
14195    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
14196   ]
14197  },
14198  "DB_Z_READ_BASE_HI": {
14199   "fields": [
14200    {"bits": [0, 7], "name": "BASE_HI"}
14201   ]
14202  },
14203  "GB_ADDR_CONFIG": {
14204   "fields": [
14205    {"bits": [0, 2], "name": "NUM_PIPES"},
14206    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
14207    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
14208    {"bits": [8, 10], "name": "NUM_PKRS"},
14209    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
14210    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
14211   ]
14212  },
14213  "GCEA_PERFCOUNTER0_CFG": {
14214   "fields": [
14215    {"bits": [0, 7], "name": "PERF_SEL"},
14216    {"bits": [8, 15], "name": "PERF_SEL_END"},
14217    {"bits": [24, 27], "name": "PERF_MODE"},
14218    {"bits": [28, 28], "name": "ENABLE"},
14219    {"bits": [29, 29], "name": "CLEAR"}
14220   ]
14221  },
14222  "GCEA_PERFCOUNTER2_MODE": {
14223   "fields": [
14224    {"bits": [0, 1], "name": "COMPARE_MODE0"},
14225    {"bits": [2, 3], "name": "COMPARE_MODE1"},
14226    {"bits": [4, 5], "name": "COMPARE_MODE2"},
14227    {"bits": [6, 7], "name": "COMPARE_MODE3"},
14228    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
14229    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
14230    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
14231    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
14232   ]
14233  },
14234  "GCEA_PERFCOUNTER_HI": {
14235   "fields": [
14236    {"bits": [0, 15], "name": "COUNTER_HI"},
14237    {"bits": [16, 31], "name": "COMPARE_VALUE"}
14238   ]
14239  },
14240  "GCEA_PERFCOUNTER_LO": {
14241   "fields": [
14242    {"bits": [0, 31], "name": "COUNTER_LO"}
14243   ]
14244  },
14245  "GCEA_PERFCOUNTER_RSLT_CNTL": {
14246   "fields": [
14247    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
14248    {"bits": [8, 15], "name": "START_TRIGGER"},
14249    {"bits": [16, 23], "name": "STOP_TRIGGER"},
14250    {"bits": [24, 24], "name": "ENABLE_ANY"},
14251    {"bits": [25, 25], "name": "CLEAR_ALL"},
14252    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
14253   ]
14254  },
14255  "GCR_PERFCOUNTER1_SELECT": {
14256   "fields": [
14257    {"bits": [0, 8], "name": "PERF_SEL"},
14258    {"bits": [24, 27], "name": "PERF_MODE"},
14259    {"bits": [28, 31], "name": "CNTL_MODE"}
14260   ]
14261  },
14262  "GDS_ATOM_BASE": {
14263   "fields": [
14264    {"bits": [0, 15], "name": "BASE"},
14265    {"bits": [16, 31], "name": "UNUSED"}
14266   ]
14267  },
14268  "GDS_ATOM_CNTL": {
14269   "fields": [
14270    {"bits": [0, 5], "name": "AINC"},
14271    {"bits": [6, 7], "name": "UNUSED1"},
14272    {"bits": [8, 9], "name": "DMODE"},
14273    {"bits": [10, 31], "name": "UNUSED2"}
14274   ]
14275  },
14276  "GDS_ATOM_COMPLETE": {
14277   "fields": [
14278    {"bits": [0, 0], "name": "COMPLETE"},
14279    {"bits": [1, 31], "name": "UNUSED"}
14280   ]
14281  },
14282  "GDS_ATOM_DST": {
14283   "fields": [
14284    {"bits": [0, 31], "name": "DST"}
14285   ]
14286  },
14287  "GDS_ATOM_OFFSET0": {
14288   "fields": [
14289    {"bits": [0, 7], "name": "OFFSET0"},
14290    {"bits": [8, 31], "name": "UNUSED"}
14291   ]
14292  },
14293  "GDS_ATOM_OFFSET1": {
14294   "fields": [
14295    {"bits": [0, 7], "name": "OFFSET1"},
14296    {"bits": [8, 31], "name": "UNUSED"}
14297   ]
14298  },
14299  "GDS_ATOM_OP": {
14300   "fields": [
14301    {"bits": [0, 7], "name": "OP"},
14302    {"bits": [8, 31], "name": "UNUSED"}
14303   ]
14304  },
14305  "GDS_ATOM_SIZE": {
14306   "fields": [
14307    {"bits": [0, 15], "name": "SIZE"},
14308    {"bits": [16, 31], "name": "UNUSED"}
14309   ]
14310  },
14311  "GDS_GWS_RESOURCE": {
14312   "fields": [
14313    {"bits": [0, 0], "name": "FLAG"},
14314    {"bits": [1, 12], "name": "COUNTER"},
14315    {"bits": [13, 13], "name": "TYPE"},
14316    {"bits": [14, 14], "name": "DED"},
14317    {"bits": [15, 15], "name": "RELEASE_ALL"},
14318    {"bits": [16, 26], "name": "HEAD_QUEUE"},
14319    {"bits": [27, 27], "name": "HEAD_VALID"},
14320    {"bits": [28, 28], "name": "HEAD_FLAG"},
14321    {"bits": [29, 29], "name": "HALTED"},
14322    {"bits": [30, 30], "name": "HEAD_QUEUE1"},
14323    {"bits": [31, 31], "name": "UNUSED1"}
14324   ]
14325  },
14326  "GDS_GWS_RESOURCE_CNT": {
14327   "fields": [
14328    {"bits": [0, 15], "name": "RESOURCE_CNT"},
14329    {"bits": [16, 31], "name": "UNUSED"}
14330   ]
14331  },
14332  "GDS_GWS_RESOURCE_CNTL": {
14333   "fields": [
14334    {"bits": [0, 5], "name": "INDEX"},
14335    {"bits": [6, 31], "name": "UNUSED"}
14336   ]
14337  },
14338  "GDS_OA_ADDRESS": {
14339   "fields": [
14340    {"bits": [0, 15], "name": "DS_ADDRESS"},
14341    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
14342    {"bits": [20, 23], "name": "CRAWLER"},
14343    {"bits": [24, 29], "name": "UNUSED"},
14344    {"bits": [30, 30], "name": "NO_ALLOC"},
14345    {"bits": [31, 31], "name": "ENABLE"}
14346   ]
14347  },
14348  "GDS_OA_CNTL": {
14349   "fields": [
14350    {"bits": [0, 3], "name": "INDEX"},
14351    {"bits": [4, 31], "name": "UNUSED"}
14352   ]
14353  },
14354  "GDS_OA_COUNTER": {
14355   "fields": [
14356    {"bits": [0, 31], "name": "SPACE_AVAILABLE"}
14357   ]
14358  },
14359  "GDS_OA_INCDEC": {
14360   "fields": [
14361    {"bits": [0, 30], "name": "VALUE"},
14362    {"bits": [31, 31], "name": "INCDEC"}
14363   ]
14364  },
14365  "GDS_OA_RING_SIZE": {
14366   "fields": [
14367    {"bits": [0, 31], "name": "RING_SIZE"}
14368   ]
14369  },
14370  "GDS_RD_ADDR": {
14371   "fields": [
14372    {"bits": [0, 31], "name": "READ_ADDR"}
14373   ]
14374  },
14375  "GDS_RD_BURST_ADDR": {
14376   "fields": [
14377    {"bits": [0, 31], "name": "BURST_ADDR"}
14378   ]
14379  },
14380  "GDS_RD_BURST_COUNT": {
14381   "fields": [
14382    {"bits": [0, 31], "name": "BURST_COUNT"}
14383   ]
14384  },
14385  "GDS_RD_BURST_DATA": {
14386   "fields": [
14387    {"bits": [0, 31], "name": "BURST_DATA"}
14388   ]
14389  },
14390  "GDS_RD_DATA": {
14391   "fields": [
14392    {"bits": [0, 31], "name": "READ_DATA"}
14393   ]
14394  },
14395  "GDS_WRITE_COMPLETE": {
14396   "fields": [
14397    {"bits": [0, 31], "name": "WRITE_COMPLETE"}
14398   ]
14399  },
14400  "GDS_WR_ADDR": {
14401   "fields": [
14402    {"bits": [0, 31], "name": "WRITE_ADDR"}
14403   ]
14404  },
14405  "GDS_WR_DATA": {
14406   "fields": [
14407    {"bits": [0, 31], "name": "WRITE_DATA"}
14408   ]
14409  },
14410  "GE1_PERFCOUNTER0_SELECT": {
14411   "fields": [
14412    {"bits": [0, 9], "name": "PERF_SEL0"},
14413    {"bits": [10, 19], "name": "PERF_SEL1"},
14414    {"bits": [20, 23], "name": "CNTR_MODE"},
14415    {"bits": [24, 27], "name": "PERF_MODE0"},
14416    {"bits": [28, 31], "name": "PERF_MODE1"}
14417   ]
14418  },
14419  "GE1_PERFCOUNTER0_SELECT1": {
14420   "fields": [
14421    {"bits": [0, 9], "name": "PERF_SEL2"},
14422    {"bits": [10, 19], "name": "PERF_SEL3"},
14423    {"bits": [24, 27], "name": "PERF_MODE2"},
14424    {"bits": [28, 31], "name": "PERF_MODE3"}
14425   ]
14426  },
14427  "GE_CNTL": {
14428   "fields": [
14429    {"bits": [0, 8], "name": "PRIM_GRP_SIZE"},
14430    {"bits": [9, 17], "name": "VERT_GRP_SIZE"},
14431    {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"},
14432    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"}
14433   ]
14434  },
14435  "GE_DMA_FIRST_INDEX": {
14436   "fields": [
14437    {"bits": [0, 31], "name": "FIRST_INDEX"}
14438   ]
14439  },
14440  "GE_MAX_OUTPUT_PER_SUBGROUP": {
14441   "fields": [
14442    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
14443   ]
14444  },
14445  "GE_NGG_SUBGRP_CNTL": {
14446   "fields": [
14447    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
14448    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
14449   ]
14450  },
14451  "GE_PC_ALLOC": {
14452   "fields": [
14453    {"bits": [0, 0], "name": "OVERSUB_EN"},
14454    {"bits": [1, 10], "name": "NUM_PC_LINES"}
14455   ]
14456  },
14457  "GE_STEREO_CNTL": {
14458   "fields": [
14459    {"bits": [0, 2], "name": "RT_SLICE"},
14460    {"bits": [3, 6], "name": "VIEWPORT"},
14461    {"bits": [8, 8], "name": "EN_STEREO"}
14462   ]
14463  },
14464  "GE_USER_VGPR_EN": {
14465   "fields": [
14466    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
14467    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
14468    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
14469   ]
14470  },
14471  "GRBM_GFX_INDEX": {
14472   "fields": [
14473    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
14474    {"bits": [8, 15], "name": "SA_INDEX"},
14475    {"bits": [16, 23], "name": "SE_INDEX"},
14476    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
14477    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
14478    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
14479   ]
14480  },
14481  "GRBM_PERFCOUNTER0_SELECT": {
14482   "fields": [
14483    {"bits": [0, 5], "name": "PERF_SEL"},
14484    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14485    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14486    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
14487    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
14488    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14489    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
14490    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
14491    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
14492    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
14493    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
14494    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
14495    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
14496    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14497    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
14498    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14499    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
14500    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
14501    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
14502    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
14503   ]
14504  },
14505  "GRBM_PERFCOUNTER0_SELECT_HI": {
14506   "fields": [
14507    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14508    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
14509    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
14510    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
14511    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
14512    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
14513    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
14514    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14515   ]
14516  },
14517  "GRBM_SE0_PERFCOUNTER_SELECT": {
14518   "fields": [
14519    {"bits": [0, 5], "name": "PERF_SEL"},
14520    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
14521    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
14522    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
14523    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
14524    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
14525    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
14526    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
14527    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
14528    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
14529    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
14530    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
14531    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
14532    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
14533    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"}
14534   ]
14535  },
14536  "GRBM_STATUS": {
14537   "fields": [
14538    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
14539    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
14540    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
14541    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
14542    {"bits": [12, 12], "name": "DB_CLEAN"},
14543    {"bits": [13, 13], "name": "CB_CLEAN"},
14544    {"bits": [14, 14], "name": "TA_BUSY"},
14545    {"bits": [15, 15], "name": "GDS_BUSY"},
14546    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
14547    {"bits": [20, 20], "name": "SX_BUSY"},
14548    {"bits": [21, 21], "name": "GE_BUSY"},
14549    {"bits": [22, 22], "name": "SPI_BUSY"},
14550    {"bits": [23, 23], "name": "BCI_BUSY"},
14551    {"bits": [24, 24], "name": "SC_BUSY"},
14552    {"bits": [25, 25], "name": "PA_BUSY"},
14553    {"bits": [26, 26], "name": "DB_BUSY"},
14554    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
14555    {"bits": [29, 29], "name": "CP_BUSY"},
14556    {"bits": [30, 30], "name": "CB_BUSY"},
14557    {"bits": [31, 31], "name": "GUI_ACTIVE"}
14558   ]
14559  },
14560  "GRBM_STATUS2": {
14561   "fields": [
14562    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
14563    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
14564    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
14565    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
14566    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
14567    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
14568    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
14569    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
14570    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
14571    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
14572    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
14573    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
14574    {"bits": [15, 15], "name": "UTCL2_BUSY"},
14575    {"bits": [16, 16], "name": "EA_BUSY"},
14576    {"bits": [17, 17], "name": "RMI_BUSY"},
14577    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
14578    {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"},
14579    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
14580    {"bits": [21, 21], "name": "SDMA_BUSY"},
14581    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
14582    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
14583    {"bits": [24, 24], "name": "SDMA2_RQ_PENDING"},
14584    {"bits": [25, 25], "name": "SDMA3_RQ_PENDING"},
14585    {"bits": [26, 26], "name": "RLC_BUSY"},
14586    {"bits": [27, 27], "name": "TCP_BUSY"},
14587    {"bits": [28, 28], "name": "CPF_BUSY"},
14588    {"bits": [29, 29], "name": "CPC_BUSY"},
14589    {"bits": [30, 30], "name": "CPG_BUSY"},
14590    {"bits": [31, 31], "name": "CPAXI_BUSY"}
14591   ]
14592  },
14593  "GRBM_STATUS3": {
14594   "fields": [
14595    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
14596    {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"},
14597    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
14598    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
14599    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
14600    {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"},
14601    {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"},
14602    {"bits": [13, 13], "name": "PH_BUSY"},
14603    {"bits": [14, 14], "name": "CH_BUSY"},
14604    {"bits": [15, 15], "name": "GL2CC_BUSY"},
14605    {"bits": [16, 16], "name": "GL1CC_BUSY"},
14606    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
14607    {"bits": [29, 29], "name": "GUS_BUSY"},
14608    {"bits": [30, 30], "name": "UTCL1_BUSY"},
14609    {"bits": [31, 31], "name": "PMM_BUSY"}
14610   ]
14611  },
14612  "GRBM_STATUS_SE0": {
14613   "fields": [
14614    {"bits": [1, 1], "name": "DB_CLEAN"},
14615    {"bits": [2, 2], "name": "CB_CLEAN"},
14616    {"bits": [3, 3], "name": "UTCL1_BUSY"},
14617    {"bits": [4, 4], "name": "TCP_BUSY"},
14618    {"bits": [5, 5], "name": "GL1CC_BUSY"},
14619    {"bits": [21, 21], "name": "RMI_BUSY"},
14620    {"bits": [22, 22], "name": "BCI_BUSY"},
14621    {"bits": [24, 24], "name": "PA_BUSY"},
14622    {"bits": [25, 25], "name": "TA_BUSY"},
14623    {"bits": [26, 26], "name": "SX_BUSY"},
14624    {"bits": [27, 27], "name": "SPI_BUSY"},
14625    {"bits": [29, 29], "name": "SC_BUSY"},
14626    {"bits": [30, 30], "name": "DB_BUSY"},
14627    {"bits": [31, 31], "name": "CB_BUSY"}
14628   ]
14629  },
14630  "IA_MULTI_VGT_PARAM": {
14631   "fields": [
14632    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14633    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14634    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14635    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14636    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14637    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
14638   ]
14639  },
14640  "IA_MULTI_VGT_PARAM_PIPED": {
14641   "fields": [
14642    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
14643    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
14644    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
14645    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
14646    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
14647    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
14648    {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"},
14649    {"bits": [22, 22], "name": "EN_INST_OPT_ADV"},
14650    {"bits": [23, 23], "name": "HW_USE_ONLY"}
14651   ]
14652  },
14653  "PA_CL_CLIP_CNTL": {
14654   "fields": [
14655    {"bits": [0, 0], "name": "UCP_ENA_0"},
14656    {"bits": [1, 1], "name": "UCP_ENA_1"},
14657    {"bits": [2, 2], "name": "UCP_ENA_2"},
14658    {"bits": [3, 3], "name": "UCP_ENA_3"},
14659    {"bits": [4, 4], "name": "UCP_ENA_4"},
14660    {"bits": [5, 5], "name": "UCP_ENA_5"},
14661    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
14662    {"bits": [14, 15], "name": "PS_UCP_MODE"},
14663    {"bits": [16, 16], "name": "CLIP_DISABLE"},
14664    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
14665    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
14666    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
14667    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
14668    {"bits": [21, 21], "name": "VTX_KILL_OR"},
14669    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
14670    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
14671    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
14672    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
14673    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
14674    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
14675   ]
14676  },
14677  "PA_CL_NANINF_CNTL": {
14678   "fields": [
14679    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
14680    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
14681    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
14682    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
14683    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
14684    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
14685    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
14686    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
14687    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
14688    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
14689    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
14690    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
14691    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
14692    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
14693    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
14694    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
14695   ]
14696  },
14697  "PA_CL_NGG_CNTL": {
14698   "fields": [
14699    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
14700    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
14701    {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"}
14702   ]
14703  },
14704  "PA_CL_UCP_0_X": {
14705   "fields": [
14706    {"bits": [0, 31], "name": "DATA_REGISTER"}
14707   ]
14708  },
14709  "PA_CL_VPORT_XOFFSET": {
14710   "fields": [
14711    {"bits": [0, 31], "name": "VPORT_XOFFSET"}
14712   ]
14713  },
14714  "PA_CL_VPORT_XSCALE": {
14715   "fields": [
14716    {"bits": [0, 31], "name": "VPORT_XSCALE"}
14717   ]
14718  },
14719  "PA_CL_VPORT_YOFFSET": {
14720   "fields": [
14721    {"bits": [0, 31], "name": "VPORT_YOFFSET"}
14722   ]
14723  },
14724  "PA_CL_VPORT_YSCALE": {
14725   "fields": [
14726    {"bits": [0, 31], "name": "VPORT_YSCALE"}
14727   ]
14728  },
14729  "PA_CL_VPORT_ZOFFSET": {
14730   "fields": [
14731    {"bits": [0, 31], "name": "VPORT_ZOFFSET"}
14732   ]
14733  },
14734  "PA_CL_VPORT_ZSCALE": {
14735   "fields": [
14736    {"bits": [0, 31], "name": "VPORT_ZSCALE"}
14737   ]
14738  },
14739  "PA_CL_VRS_CNTL": {
14740   "fields": [
14741    {"bits": [0, 2], "name": "VERTEX_RATE_COMBINER_MODE"},
14742    {"bits": [3, 5], "name": "PRIMITIVE_RATE_COMBINER_MODE"},
14743    {"bits": [6, 8], "name": "HTILE_RATE_COMBINER_MODE"},
14744    {"bits": [9, 11], "name": "SAMPLE_ITER_COMBINER_MODE"},
14745    {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"},
14746    {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"}
14747   ]
14748  },
14749  "PA_CL_VS_OUT_CNTL": {
14750   "fields": [
14751    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
14752    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
14753    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
14754    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
14755    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
14756    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
14757    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
14758    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
14759    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
14760    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
14761    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
14762    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
14763    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
14764    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
14765    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
14766    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
14767    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
14768    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
14769    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
14770    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
14771    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
14772    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
14773    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
14774    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
14775    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
14776    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
14777    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
14778    {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"},
14779    {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"},
14780    {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"}
14781   ]
14782  },
14783  "PA_CL_VTE_CNTL": {
14784   "fields": [
14785    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
14786    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
14787    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
14788    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
14789    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
14790    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
14791    {"bits": [8, 8], "name": "VTX_XY_FMT"},
14792    {"bits": [9, 9], "name": "VTX_Z_FMT"},
14793    {"bits": [10, 10], "name": "VTX_W0_FMT"},
14794    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
14795   ]
14796  },
14797  "PA_SC_AA_CONFIG": {
14798   "fields": [
14799    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
14800    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
14801    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
14802    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
14803    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
14804    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
14805    {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"},
14806    {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"}
14807   ]
14808  },
14809  "PA_SC_AA_MASK_X0Y0_X1Y0": {
14810   "fields": [
14811    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
14812    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
14813   ]
14814  },
14815  "PA_SC_AA_MASK_X0Y1_X1Y1": {
14816   "fields": [
14817    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
14818    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
14819   ]
14820  },
14821  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
14822   "fields": [
14823    {"bits": [0, 3], "name": "S0_X"},
14824    {"bits": [4, 7], "name": "S0_Y"},
14825    {"bits": [8, 11], "name": "S1_X"},
14826    {"bits": [12, 15], "name": "S1_Y"},
14827    {"bits": [16, 19], "name": "S2_X"},
14828    {"bits": [20, 23], "name": "S2_Y"},
14829    {"bits": [24, 27], "name": "S3_X"},
14830    {"bits": [28, 31], "name": "S3_Y"}
14831   ]
14832  },
14833  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
14834   "fields": [
14835    {"bits": [0, 3], "name": "S4_X"},
14836    {"bits": [4, 7], "name": "S4_Y"},
14837    {"bits": [8, 11], "name": "S5_X"},
14838    {"bits": [12, 15], "name": "S5_Y"},
14839    {"bits": [16, 19], "name": "S6_X"},
14840    {"bits": [20, 23], "name": "S6_Y"},
14841    {"bits": [24, 27], "name": "S7_X"},
14842    {"bits": [28, 31], "name": "S7_Y"}
14843   ]
14844  },
14845  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
14846   "fields": [
14847    {"bits": [0, 3], "name": "S8_X"},
14848    {"bits": [4, 7], "name": "S8_Y"},
14849    {"bits": [8, 11], "name": "S9_X"},
14850    {"bits": [12, 15], "name": "S9_Y"},
14851    {"bits": [16, 19], "name": "S10_X"},
14852    {"bits": [20, 23], "name": "S10_Y"},
14853    {"bits": [24, 27], "name": "S11_X"},
14854    {"bits": [28, 31], "name": "S11_Y"}
14855   ]
14856  },
14857  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
14858   "fields": [
14859    {"bits": [0, 3], "name": "S12_X"},
14860    {"bits": [4, 7], "name": "S12_Y"},
14861    {"bits": [8, 11], "name": "S13_X"},
14862    {"bits": [12, 15], "name": "S13_Y"},
14863    {"bits": [16, 19], "name": "S14_X"},
14864    {"bits": [20, 23], "name": "S14_Y"},
14865    {"bits": [24, 27], "name": "S15_X"},
14866    {"bits": [28, 31], "name": "S15_Y"}
14867   ]
14868  },
14869  "PA_SC_BINNER_CNTL_0": {
14870   "fields": [
14871    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
14872    {"bits": [2, 2], "name": "BIN_SIZE_X"},
14873    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
14874    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
14875    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
14876    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
14877    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
14878    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
14879    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
14880    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
14881    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
14882    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
14883   ]
14884  },
14885  "PA_SC_BINNER_CNTL_1": {
14886   "fields": [
14887    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
14888    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
14889   ]
14890  },
14891  "PA_SC_CENTROID_PRIORITY_0": {
14892   "fields": [
14893    {"bits": [0, 3], "name": "DISTANCE_0"},
14894    {"bits": [4, 7], "name": "DISTANCE_1"},
14895    {"bits": [8, 11], "name": "DISTANCE_2"},
14896    {"bits": [12, 15], "name": "DISTANCE_3"},
14897    {"bits": [16, 19], "name": "DISTANCE_4"},
14898    {"bits": [20, 23], "name": "DISTANCE_5"},
14899    {"bits": [24, 27], "name": "DISTANCE_6"},
14900    {"bits": [28, 31], "name": "DISTANCE_7"}
14901   ]
14902  },
14903  "PA_SC_CENTROID_PRIORITY_1": {
14904   "fields": [
14905    {"bits": [0, 3], "name": "DISTANCE_8"},
14906    {"bits": [4, 7], "name": "DISTANCE_9"},
14907    {"bits": [8, 11], "name": "DISTANCE_10"},
14908    {"bits": [12, 15], "name": "DISTANCE_11"},
14909    {"bits": [16, 19], "name": "DISTANCE_12"},
14910    {"bits": [20, 23], "name": "DISTANCE_13"},
14911    {"bits": [24, 27], "name": "DISTANCE_14"},
14912    {"bits": [28, 31], "name": "DISTANCE_15"}
14913   ]
14914  },
14915  "PA_SC_CLIPRECT_0_TL": {
14916   "fields": [
14917    {"bits": [0, 14], "name": "TL_X"},
14918    {"bits": [16, 30], "name": "TL_Y"}
14919   ]
14920  },
14921  "PA_SC_CLIPRECT_RULE": {
14922   "fields": [
14923    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
14924   ]
14925  },
14926  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
14927   "fields": [
14928    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
14929    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
14930    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
14931    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
14932    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
14933    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
14934    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
14935    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
14936    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
14937    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
14938    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
14939    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
14940    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
14941    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
14942    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
14943    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
14944    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
14945    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
14946    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
14947    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
14948   ]
14949  },
14950  "PA_SC_EDGERULE": {
14951   "fields": [
14952    {"bits": [0, 3], "name": "ER_TRI"},
14953    {"bits": [4, 7], "name": "ER_POINT"},
14954    {"bits": [8, 11], "name": "ER_RECT"},
14955    {"bits": [12, 17], "name": "ER_LINE_LR"},
14956    {"bits": [18, 23], "name": "ER_LINE_RL"},
14957    {"bits": [24, 27], "name": "ER_LINE_TB"},
14958    {"bits": [28, 31], "name": "ER_LINE_BT"}
14959   ]
14960  },
14961  "PA_SC_LINE_CNTL": {
14962   "fields": [
14963    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
14964    {"bits": [10, 10], "name": "LAST_PIXEL"},
14965    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
14966    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
14967    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
14968   ]
14969  },
14970  "PA_SC_LINE_STIPPLE": {
14971   "fields": [
14972    {"bits": [0, 15], "name": "LINE_PATTERN"},
14973    {"bits": [16, 23], "name": "REPEAT_COUNT"},
14974    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
14975    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
14976   ]
14977  },
14978  "PA_SC_LINE_STIPPLE_STATE": {
14979   "fields": [
14980    {"bits": [0, 3], "name": "CURRENT_PTR"},
14981    {"bits": [8, 15], "name": "CURRENT_COUNT"}
14982   ]
14983  },
14984  "PA_SC_MODE_CNTL_0": {
14985   "fields": [
14986    {"bits": [0, 0], "name": "MSAA_ENABLE"},
14987    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
14988    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
14989    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
14990    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
14991    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
14992   ]
14993  },
14994  "PA_SC_MODE_CNTL_1": {
14995   "fields": [
14996    {"bits": [0, 0], "name": "WALK_SIZE"},
14997    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
14998    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
14999    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
15000    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
15001    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
15002    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
15003    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
15004    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
15005    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
15006    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
15007    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
15008    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
15009    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
15010    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
15011    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
15012    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
15013    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
15014    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
15015    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
15016    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
15017    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
15018    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
15019    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
15020   ]
15021  },
15022  "PA_SC_NGG_MODE_CNTL": {
15023   "fields": [
15024    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
15025    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"}
15026   ]
15027  },
15028  "PA_SC_P3D_TRAP_SCREEN_H": {
15029   "fields": [
15030    {"bits": [0, 13], "name": "X_COORD"}
15031   ]
15032  },
15033  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
15034   "fields": [
15035    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
15036    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
15037   ]
15038  },
15039  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
15040   "fields": [
15041    {"bits": [0, 15], "name": "COUNT"}
15042   ]
15043  },
15044  "PA_SC_P3D_TRAP_SCREEN_V": {
15045   "fields": [
15046    {"bits": [0, 13], "name": "Y_COORD"}
15047   ]
15048  },
15049  "PA_SC_PERFCOUNTER1_SELECT": {
15050   "fields": [
15051    {"bits": [0, 9], "name": "PERF_SEL"}
15052   ]
15053  },
15054  "PA_SC_RASTER_CONFIG": {
15055   "fields": [
15056    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
15057    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
15058    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
15059    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
15060    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
15061    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
15062    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
15063    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
15064    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
15065    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
15066    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
15067    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
15068    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
15069    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
15070    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
15071   ]
15072  },
15073  "PA_SC_RASTER_CONFIG_1": {
15074   "fields": [
15075    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
15076    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
15077    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
15078   ]
15079  },
15080  "PA_SC_SCREEN_EXTENT_CONTROL": {
15081   "fields": [
15082    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
15083    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
15084   ]
15085  },
15086  "PA_SC_SCREEN_EXTENT_MIN_0": {
15087   "fields": [
15088    {"bits": [0, 15], "name": "X"},
15089    {"bits": [16, 31], "name": "Y"}
15090   ]
15091  },
15092  "PA_SC_SCREEN_SCISSOR_BR": {
15093   "fields": [
15094    {"bits": [0, 15], "name": "BR_X"},
15095    {"bits": [16, 31], "name": "BR_Y"}
15096   ]
15097  },
15098  "PA_SC_SCREEN_SCISSOR_TL": {
15099   "fields": [
15100    {"bits": [0, 15], "name": "TL_X"},
15101    {"bits": [16, 31], "name": "TL_Y"}
15102   ]
15103  },
15104  "PA_SC_SHADER_CONTROL": {
15105   "fields": [
15106    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
15107    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
15108    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
15109    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"}
15110   ]
15111  },
15112  "PA_SC_TILE_STEERING_OVERRIDE": {
15113   "fields": [
15114    {"bits": [0, 0], "name": "ENABLE"},
15115    {"bits": [1, 2], "name": "NUM_SE"},
15116    {"bits": [5, 6], "name": "NUM_RB_PER_SE"},
15117    {"bits": [12, 13], "name": "NUM_SC"},
15118    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
15119    {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"}
15120   ]
15121  },
15122  "PA_SC_VPORT_ZMAX_0": {
15123   "fields": [
15124    {"bits": [0, 31], "name": "VPORT_ZMAX"}
15125   ]
15126  },
15127  "PA_SC_VPORT_ZMIN_0": {
15128   "fields": [
15129    {"bits": [0, 31], "name": "VPORT_ZMIN"}
15130   ]
15131  },
15132  "PA_SC_WINDOW_OFFSET": {
15133   "fields": [
15134    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
15135    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
15136   ]
15137  },
15138  "PA_SC_WINDOW_SCISSOR_BR": {
15139   "fields": [
15140    {"bits": [0, 14], "name": "BR_X"},
15141    {"bits": [16, 30], "name": "BR_Y"}
15142   ]
15143  },
15144  "PA_SC_WINDOW_SCISSOR_TL": {
15145   "fields": [
15146    {"bits": [0, 14], "name": "TL_X"},
15147    {"bits": [16, 30], "name": "TL_Y"},
15148    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
15149   ]
15150  },
15151  "PA_STATE_STEREO_X": {
15152   "fields": [
15153    {"bits": [0, 31], "name": "STEREO_X_OFFSET"}
15154   ]
15155  },
15156  "PA_STEREO_CNTL": {
15157   "fields": [
15158    {"bits": [1, 4], "name": "STEREO_MODE"},
15159    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
15160    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
15161    {"bits": [16, 18], "name": "VP_ID_MODE"},
15162    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
15163   ]
15164  },
15165  "PA_SU_HARDWARE_SCREEN_OFFSET": {
15166   "fields": [
15167    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
15168    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
15169   ]
15170  },
15171  "PA_SU_LINE_CNTL": {
15172   "fields": [
15173    {"bits": [0, 15], "name": "WIDTH"}
15174   ]
15175  },
15176  "PA_SU_LINE_STIPPLE_CNTL": {
15177   "fields": [
15178    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
15179    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
15180    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
15181    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
15182   ]
15183  },
15184  "PA_SU_LINE_STIPPLE_SCALE": {
15185   "fields": [
15186    {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"}
15187   ]
15188  },
15189  "PA_SU_LINE_STIPPLE_VALUE": {
15190   "fields": [
15191    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
15192   ]
15193  },
15194  "PA_SU_OVER_RASTERIZATION_CNTL": {
15195   "fields": [
15196    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
15197    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
15198    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
15199    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
15200    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
15201   ]
15202  },
15203  "PA_SU_PERFCOUNTER0_SELECT": {
15204   "fields": [
15205    {"bits": [0, 9], "name": "PERF_SEL"},
15206    {"bits": [10, 19], "name": "PERF_SEL1"},
15207    {"bits": [20, 23], "name": "CNTR_MODE"},
15208    {"bits": [24, 27], "name": "PERF_MODE1"},
15209    {"bits": [28, 31], "name": "PERF_MODE"}
15210   ]
15211  },
15212  "PA_SU_PERFCOUNTER0_SELECT1": {
15213   "fields": [
15214    {"bits": [0, 9], "name": "PERF_SEL2"},
15215    {"bits": [10, 19], "name": "PERF_SEL3"},
15216    {"bits": [24, 27], "name": "PERF_MODE3"},
15217    {"bits": [28, 31], "name": "PERF_MODE2"}
15218   ]
15219  },
15220  "PA_SU_POINT_MINMAX": {
15221   "fields": [
15222    {"bits": [0, 15], "name": "MIN_SIZE"},
15223    {"bits": [16, 31], "name": "MAX_SIZE"}
15224   ]
15225  },
15226  "PA_SU_POINT_SIZE": {
15227   "fields": [
15228    {"bits": [0, 15], "name": "HEIGHT"},
15229    {"bits": [16, 31], "name": "WIDTH"}
15230   ]
15231  },
15232  "PA_SU_POLY_OFFSET_CLAMP": {
15233   "fields": [
15234    {"bits": [0, 31], "name": "CLAMP"}
15235   ]
15236  },
15237  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
15238   "fields": [
15239    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
15240    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
15241   ]
15242  },
15243  "PA_SU_POLY_OFFSET_FRONT_SCALE": {
15244   "fields": [
15245    {"bits": [0, 31], "name": "SCALE"}
15246   ]
15247  },
15248  "PA_SU_PRIM_FILTER_CNTL": {
15249   "fields": [
15250    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
15251    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
15252    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
15253    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
15254    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
15255    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
15256    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
15257    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
15258    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
15259    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
15260    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
15261   ]
15262  },
15263  "PA_SU_SC_MODE_CNTL": {
15264   "fields": [
15265    {"bits": [0, 0], "name": "CULL_FRONT"},
15266    {"bits": [1, 1], "name": "CULL_BACK"},
15267    {"bits": [2, 2], "name": "FACE"},
15268    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
15269    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
15270    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
15271    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
15272    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
15273    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
15274    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
15275    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
15276    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
15277    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
15278    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
15279    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
15280    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
15281   ]
15282  },
15283  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
15284   "fields": [
15285    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
15286    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
15287    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
15288    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
15289    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}
15290   ]
15291  },
15292  "PA_SU_VTX_CNTL": {
15293   "fields": [
15294    {"bits": [0, 0], "name": "PIX_CENTER"},
15295    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
15296    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
15297   ]
15298  },
15299  "RLC_GPM_PERF_COUNT_0": {
15300   "fields": [
15301    {"bits": [0, 3], "name": "FEATURE_SEL"},
15302    {"bits": [4, 7], "name": "SE_INDEX"},
15303    {"bits": [8, 11], "name": "SA_INDEX"},
15304    {"bits": [12, 15], "name": "WGP_INDEX"},
15305    {"bits": [16, 17], "name": "EVENT_SEL"},
15306    {"bits": [18, 19], "name": "UNUSED"},
15307    {"bits": [20, 20], "name": "ENABLE"},
15308    {"bits": [21, 31], "name": "RESERVED"}
15309   ]
15310  },
15311  "RLC_GPU_IOV_PERF_CNT_CNTL": {
15312   "fields": [
15313    {"bits": [0, 0], "name": "ENABLE"},
15314    {"bits": [1, 1], "name": "MODE_SELECT"},
15315    {"bits": [2, 2], "name": "RESET"},
15316    {"bits": [3, 31], "name": "RESERVED"}
15317   ]
15318  },
15319  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
15320   "fields": [
15321    {"bits": [0, 3], "name": "VFID"},
15322    {"bits": [4, 5], "name": "CNT_ID"},
15323    {"bits": [6, 31], "name": "RESERVED"}
15324   ]
15325  },
15326  "RLC_PERFCOUNTER0_SELECT": {
15327   "fields": [
15328    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
15329   ]
15330  },
15331  "RLC_PERFMON_CLK_CNTL": {
15332   "fields": [
15333    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
15334   ]
15335  },
15336  "RLC_PERFMON_CNTL": {
15337   "fields": [
15338    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
15339    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
15340   ]
15341  },
15342  "RLC_SPM_ACCUM_CTRL": {
15343   "fields": [
15344    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
15345    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
15346    {"bits": [2, 2], "name": "StrobeRearmAccum"},
15347    {"bits": [3, 3], "name": "StrobeResetSpmBlock"},
15348    {"bits": [4, 7], "name": "StrobeStartSpm"},
15349    {"bits": [8, 8], "name": "StrobeRearmSwaAccum"},
15350    {"bits": [9, 9], "name": "StrobeStartSwa"},
15351    {"bits": [10, 10], "name": "StrobePerfmonSampleWires"},
15352    {"bits": [11, 31], "name": "RESERVED"}
15353   ]
15354  },
15355  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
15356   "fields": [
15357    {"bits": [0, 10], "name": "addr"},
15358    {"bits": [11, 31], "name": "RESERVED"}
15359   ]
15360  },
15361  "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET": {
15362   "fields": [
15363    {"bits": [0, 7], "name": "global_offset"},
15364    {"bits": [8, 15], "name": "spmwithaccum_se_offset"},
15365    {"bits": [16, 23], "name": "spmwithaccum_global_offset"},
15366    {"bits": [24, 31], "name": "RESERVED"}
15367   ]
15368  },
15369  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
15370   "fields": [
15371    {"bits": [0, 7], "name": "data"},
15372    {"bits": [8, 31], "name": "RESERVED"}
15373   ]
15374  },
15375  "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS": {
15376   "fields": [
15377    {"bits": [0, 7], "name": "spp_addr_region"},
15378    {"bits": [8, 15], "name": "swa_addr_region"},
15379    {"bits": [16, 31], "name": "RESERVED"}
15380   ]
15381  },
15382  "RLC_SPM_ACCUM_DATARAM_ADDR": {
15383   "fields": [
15384    {"bits": [0, 6], "name": "addr"},
15385    {"bits": [7, 31], "name": "RESERVED"}
15386   ]
15387  },
15388  "RLC_SPM_ACCUM_DATARAM_DATA": {
15389   "fields": [
15390    {"bits": [0, 31], "name": "data"}
15391   ]
15392  },
15393  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
15394   "fields": [
15395    {"bits": [0, 18], "name": "DataRamWrCount"},
15396    {"bits": [19, 31], "name": "RESERVED"}
15397   ]
15398  },
15399  "RLC_SPM_ACCUM_MODE": {
15400   "fields": [
15401    {"bits": [0, 0], "name": "EnableAccum"},
15402    {"bits": [1, 1], "name": "EnableSpmWithAccumMode"},
15403    {"bits": [2, 2], "name": "EnableSPPMode"},
15404    {"bits": [3, 3], "name": "AutoResetPerfmonDisable"},
15405    {"bits": [4, 4], "name": "SwaAutoResetPerfmonDisable"},
15406    {"bits": [5, 5], "name": "AutoAccumEn"},
15407    {"bits": [6, 6], "name": "SwaAutoAccumEn"},
15408    {"bits": [7, 7], "name": "AutoSpmEn"},
15409    {"bits": [8, 8], "name": "SwaAutoSpmEn"},
15410    {"bits": [9, 9], "name": "Globals_LoadOverride"},
15411    {"bits": [10, 10], "name": "Globals_SwaLoadOverride"},
15412    {"bits": [11, 11], "name": "SE0_LoadOverride"},
15413    {"bits": [12, 12], "name": "SE0_SwaLoadOverride"},
15414    {"bits": [13, 13], "name": "SE1_LoadOverride"},
15415    {"bits": [14, 14], "name": "SE1_SwaLoadOverride"},
15416    {"bits": [15, 15], "name": "SE2_LoadOverride"},
15417    {"bits": [16, 16], "name": "SE2_SwaLoadOverride"},
15418    {"bits": [17, 17], "name": "SE3_LoadOverride"},
15419    {"bits": [18, 18], "name": "SE3_SwaLoadOverride"}
15420   ]
15421  },
15422  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
15423   "fields": [
15424    {"bits": [0, 7], "name": "SamplesRequested"}
15425   ]
15426  },
15427  "RLC_SPM_ACCUM_STATUS": {
15428   "fields": [
15429    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
15430    {"bits": [8, 8], "name": "AccumDone"},
15431    {"bits": [9, 9], "name": "SpmDone"},
15432    {"bits": [10, 10], "name": "AccumOverflow"},
15433    {"bits": [11, 11], "name": "AccumArmed"},
15434    {"bits": [12, 12], "name": "SequenceInProgress"},
15435    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
15436    {"bits": [14, 14], "name": "AllFifosEmpty"},
15437    {"bits": [15, 15], "name": "FSMIsIdle"},
15438    {"bits": [16, 16], "name": "SwaAccumDone"},
15439    {"bits": [17, 17], "name": "SwaSpmDone"},
15440    {"bits": [18, 18], "name": "SwaAccumOverflow"},
15441    {"bits": [19, 19], "name": "SwaAccumArmed"},
15442    {"bits": [20, 20], "name": "AllSegsDone"},
15443    {"bits": [21, 21], "name": "RearmSwaPending"},
15444    {"bits": [22, 22], "name": "RearmSppPending"},
15445    {"bits": [23, 31], "name": "RESERVED"}
15446   ]
15447  },
15448  "RLC_SPM_ACCUM_THRESHOLD": {
15449   "fields": [
15450    {"bits": [0, 15], "name": "Threshold"}
15451   ]
15452  },
15453  "RLC_SPM_DESER_START_SKEW": {
15454   "fields": [
15455    {"bits": [0, 6], "name": "DESER_START_SKEW"},
15456    {"bits": [7, 31], "name": "RESERVED"}
15457   ]
15458  },
15459  "RLC_SPM_GFXCLOCK_HIGHCOUNT": {
15460   "fields": [
15461    {"bits": [0, 31], "name": "GFXCLOCK_HIGHCOUNT"}
15462   ]
15463  },
15464  "RLC_SPM_GFXCLOCK_LOWCOUNT": {
15465   "fields": [
15466    {"bits": [0, 31], "name": "GFXCLOCK_LOWCOUNT"}
15467   ]
15468  },
15469  "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR": {
15470   "fields": [
15471    {"bits": [0, 31], "name": "GLB_SAMPLEDELAY_INDEX"}
15472   ]
15473  },
15474  "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": {
15475   "fields": [
15476    {"bits": [0, 6], "name": "data"},
15477    {"bits": [7, 31], "name": "RESERVED"}
15478   ]
15479  },
15480  "RLC_SPM_GLOBALS_MUXSEL_SKEW": {
15481   "fields": [
15482    {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"},
15483    {"bits": [7, 31], "name": "RESERVED"}
15484   ]
15485  },
15486  "RLC_SPM_GLOBALS_SAMPLE_SKEW": {
15487   "fields": [
15488    {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"},
15489    {"bits": [7, 31], "name": "RESERVED"}
15490   ]
15491  },
15492  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
15493   "fields": [
15494    {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"},
15495    {"bits": [8, 31], "name": "RESERVED"}
15496   ]
15497  },
15498  "RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET": {
15499   "fields": [
15500    {"bits": [0, 15], "name": "OFFSET"},
15501    {"bits": [16, 31], "name": "RESERVED"}
15502   ]
15503  },
15504  "RLC_SPM_PERFMON_CNTL": {
15505   "fields": [
15506    {"bits": [0, 11], "name": "RESERVED1"},
15507    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
15508    {"bits": [14, 15], "name": "RESERVED"},
15509    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
15510   ]
15511  },
15512  "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": {
15513   "fields": [
15514    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15515    {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"},
15516    {"bits": [16, 31], "name": "RESERVED"}
15517   ]
15518  },
15519  "RLC_SPM_PERFMON_RING_BASE_HI": {
15520   "fields": [
15521    {"bits": [0, 15], "name": "RING_BASE_HI"},
15522    {"bits": [16, 31], "name": "RESERVED"}
15523   ]
15524  },
15525  "RLC_SPM_PERFMON_RING_BASE_LO": {
15526   "fields": [
15527    {"bits": [0, 31], "name": "RING_BASE_LO"}
15528   ]
15529  },
15530  "RLC_SPM_PERFMON_RING_SIZE": {
15531   "fields": [
15532    {"bits": [0, 31], "name": "RING_BASE_SIZE"}
15533   ]
15534  },
15535  "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": {
15536   "fields": [
15537    {"bits": [0, 7], "name": "SE0_NUM_LINE"},
15538    {"bits": [8, 15], "name": "SE1_NUM_LINE"},
15539    {"bits": [16, 23], "name": "SE2_NUM_LINE"},
15540    {"bits": [24, 31], "name": "SE3_NUM_LINE"}
15541   ]
15542  },
15543  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
15544   "fields": [
15545    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
15546    {"bits": [8, 10], "name": "RESERVED1"},
15547    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
15548    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
15549    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
15550    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
15551    {"bits": [31, 31], "name": "RESERVED"}
15552   ]
15553  },
15554  "RLC_SPM_RING_RDPTR": {
15555   "fields": [
15556    {"bits": [0, 31], "name": "PERFMON_RING_RDPTR"}
15557   ]
15558  },
15559  "RLC_SPM_RING_WRPTR": {
15560   "fields": [
15561    {"bits": [0, 4], "name": "RESERVED"},
15562    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
15563   ]
15564  },
15565  "RLC_SPM_SEGMENT_THRESHOLD": {
15566   "fields": [
15567    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
15568    {"bits": [8, 31], "name": "RESERVED"}
15569   ]
15570  },
15571  "RLC_SPM_SE_MUXSEL_ADDR": {
15572   "fields": [
15573    {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"},
15574    {"bits": [9, 31], "name": "RESERVED"}
15575   ]
15576  },
15577  "RLC_SPM_SE_MUXSEL_DATA": {
15578   "fields": [
15579    {"bits": [0, 31], "name": "PERFMON_SEL_DATA"}
15580   ]
15581  },
15582  "RLC_SPM_SE_MUXSEL_SKEW": {
15583   "fields": [
15584    {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"},
15585    {"bits": [7, 31], "name": "RESERVED"}
15586   ]
15587  },
15588  "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR": {
15589   "fields": [
15590    {"bits": [0, 31], "name": "SE_SAMPLEDELAY_INDEX"}
15591   ]
15592  },
15593  "RLC_SPM_SE_SAMPLE_SKEW": {
15594   "fields": [
15595    {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"},
15596    {"bits": [7, 31], "name": "RESERVED"}
15597   ]
15598  },
15599  "RLC_SPM_VIRT_CTRL": {
15600   "fields": [
15601    {"bits": [0, 0], "name": "PauseSpmSamplingRequest"}
15602   ]
15603  },
15604  "RLC_SPM_VIRT_STATUS": {
15605   "fields": [
15606    {"bits": [0, 0], "name": "SpmSamplingPaused"}
15607   ]
15608  },
15609  "RMI_PERF_COUNTER_CNTL": {
15610   "fields": [
15611    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
15612    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
15613    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
15614    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
15615    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
15616    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
15617    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
15618    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
15619    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
15620    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
15621   ]
15622  },
15623  "SCRATCH_ADDR": {
15624   "fields": [
15625    {"bits": [0, 31], "name": "OBSOLETE_ADDR"}
15626   ]
15627  },
15628  "SCRATCH_REG0": {
15629   "fields": [
15630    {"bits": [0, 31], "name": "SCRATCH_REG0"}
15631   ]
15632  },
15633  "SCRATCH_REG1": {
15634   "fields": [
15635    {"bits": [0, 31], "name": "SCRATCH_REG1"}
15636   ]
15637  },
15638  "SCRATCH_REG2": {
15639   "fields": [
15640    {"bits": [0, 31], "name": "SCRATCH_REG2"}
15641   ]
15642  },
15643  "SCRATCH_REG3": {
15644   "fields": [
15645    {"bits": [0, 31], "name": "SCRATCH_REG3"}
15646   ]
15647  },
15648  "SCRATCH_REG4": {
15649   "fields": [
15650    {"bits": [0, 31], "name": "SCRATCH_REG4"}
15651   ]
15652  },
15653  "SCRATCH_REG5": {
15654   "fields": [
15655    {"bits": [0, 31], "name": "SCRATCH_REG5"}
15656   ]
15657  },
15658  "SCRATCH_REG6": {
15659   "fields": [
15660    {"bits": [0, 31], "name": "SCRATCH_REG6"}
15661   ]
15662  },
15663  "SCRATCH_REG7": {
15664   "fields": [
15665    {"bits": [0, 31], "name": "SCRATCH_REG7"}
15666   ]
15667  },
15668  "SCRATCH_REG_ATOMIC": {
15669   "fields": [
15670    {"bits": [0, 23], "name": "IMMED"},
15671    {"bits": [24, 26], "name": "ID"},
15672    {"bits": [27, 27], "name": "reserved27"},
15673    {"bits": [28, 30], "name": "OP"},
15674    {"bits": [31, 31], "name": "reserved31"}
15675   ]
15676  },
15677  "SCRATCH_UMSK": {
15678   "fields": [
15679    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
15680    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
15681   ]
15682  },
15683  "SDMA0_PERFCNT_MISC_CNTL": {
15684   "fields": [
15685    {"bits": [0, 15], "name": "CMD_OP"}
15686   ]
15687  },
15688  "SPI_BARYC_CNTL": {
15689   "fields": [
15690    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
15691    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
15692    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
15693    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
15694    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
15695    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
15696    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
15697   ]
15698  },
15699  "SPI_CONFIG_CNTL": {
15700   "fields": [
15701    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
15702    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
15703    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
15704    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
15705    {"bits": [26, 26], "name": "FORCE_HALF_RATE_PC_EXP"},
15706    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"},
15707    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
15708    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
15709    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
15710   ]
15711  },
15712  "SPI_CONFIG_CNTL_REMAP": {
15713   "fields": [
15714    {"bits": [0, 31], "name": "RESERVED"}
15715   ]
15716  },
15717  "SPI_INTERP_CONTROL_0": {
15718   "fields": [
15719    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
15720    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
15721    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
15722    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
15723    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
15724    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
15725    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
15726   ]
15727  },
15728  "SPI_PERFCOUNTER_BINS": {
15729   "fields": [
15730    {"bits": [0, 3], "name": "BIN0_MIN"},
15731    {"bits": [4, 7], "name": "BIN0_MAX"},
15732    {"bits": [8, 11], "name": "BIN1_MIN"},
15733    {"bits": [12, 15], "name": "BIN1_MAX"},
15734    {"bits": [16, 19], "name": "BIN2_MIN"},
15735    {"bits": [20, 23], "name": "BIN2_MAX"},
15736    {"bits": [24, 27], "name": "BIN3_MIN"},
15737    {"bits": [28, 31], "name": "BIN3_MAX"}
15738   ]
15739  },
15740  "SPI_PS_INPUT_CNTL_0": {
15741   "fields": [
15742    {"bits": [0, 5], "name": "OFFSET"},
15743    {"bits": [8, 9], "name": "DEFAULT_VAL"},
15744    {"bits": [10, 10], "name": "FLAT_SHADE"},
15745    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
15746    {"bits": [13, 16], "name": "CYL_WRAP"},
15747    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
15748    {"bits": [18, 18], "name": "DUP"},
15749    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15750    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15751    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15752    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
15753    {"bits": [24, 24], "name": "ATTR0_VALID"},
15754    {"bits": [25, 25], "name": "ATTR1_VALID"}
15755   ]
15756  },
15757  "SPI_PS_INPUT_CNTL_20": {
15758   "fields": [
15759    {"bits": [0, 5], "name": "OFFSET"},
15760    {"bits": [8, 9], "name": "DEFAULT_VAL"},
15761    {"bits": [10, 10], "name": "FLAT_SHADE"},
15762    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
15763    {"bits": [18, 18], "name": "DUP"},
15764    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
15765    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
15766    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
15767    {"bits": [24, 24], "name": "ATTR0_VALID"},
15768    {"bits": [25, 25], "name": "ATTR1_VALID"}
15769   ]
15770  },
15771  "SPI_PS_INPUT_ENA": {
15772   "fields": [
15773    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
15774    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
15775    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
15776    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
15777    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
15778    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
15779    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
15780    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
15781    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
15782    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
15783    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
15784    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
15785    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
15786    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
15787    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
15788    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
15789   ]
15790  },
15791  "SPI_PS_IN_CONTROL": {
15792   "fields": [
15793    {"bits": [0, 5], "name": "NUM_INTERP"},
15794    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
15795    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
15796    {"bits": [9, 13], "name": "NUM_PRIM_INTERP"},
15797    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
15798    {"bits": [15, 15], "name": "PS_W32_EN"}
15799   ]
15800  },
15801  "SPI_SHADER_COL_FORMAT": {
15802   "fields": [
15803    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
15804    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
15805    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
15806    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
15807    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
15808    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
15809    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
15810    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
15811   ]
15812  },
15813  "SPI_SHADER_IDX_FORMAT": {
15814   "fields": [
15815    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
15816   ]
15817  },
15818  "SPI_SHADER_LATE_ALLOC_VS": {
15819   "fields": [
15820    {"bits": [0, 5], "name": "LIMIT"}
15821   ]
15822  },
15823  "SPI_SHADER_PGM_CHKSUM_PS": {
15824   "fields": [
15825    {"bits": [0, 31], "name": "CHECKSUM"}
15826   ]
15827  },
15828  "SPI_SHADER_PGM_HI_PS": {
15829   "fields": [
15830    {"bits": [0, 7], "name": "MEM_BASE"}
15831   ]
15832  },
15833  "SPI_SHADER_PGM_LO_PS": {
15834   "fields": [
15835    {"bits": [0, 31], "name": "MEM_BASE"}
15836   ]
15837  },
15838  "SPI_SHADER_PGM_RSRC1_GS": {
15839   "fields": [
15840    {"bits": [0, 5], "name": "VGPRS"},
15841    {"bits": [6, 9], "name": "SGPRS"},
15842    {"bits": [10, 11], "name": "PRIORITY"},
15843    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15844    {"bits": [20, 20], "name": "PRIV"},
15845    {"bits": [21, 21], "name": "DX10_CLAMP"},
15846    {"bits": [23, 23], "name": "IEEE_MODE"},
15847    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
15848    {"bits": [25, 25], "name": "MEM_ORDERED"},
15849    {"bits": [26, 26], "name": "FWD_PROGRESS"},
15850    {"bits": [27, 27], "name": "WGP_MODE"},
15851    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
15852    {"bits": [31, 31], "name": "FP16_OVFL"}
15853   ]
15854  },
15855  "SPI_SHADER_PGM_RSRC1_HS": {
15856   "fields": [
15857    {"bits": [0, 5], "name": "VGPRS"},
15858    {"bits": [6, 9], "name": "SGPRS"},
15859    {"bits": [10, 11], "name": "PRIORITY"},
15860    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15861    {"bits": [20, 20], "name": "PRIV"},
15862    {"bits": [21, 21], "name": "DX10_CLAMP"},
15863    {"bits": [23, 23], "name": "IEEE_MODE"},
15864    {"bits": [24, 24], "name": "MEM_ORDERED"},
15865    {"bits": [25, 25], "name": "FWD_PROGRESS"},
15866    {"bits": [26, 26], "name": "WGP_MODE"},
15867    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
15868    {"bits": [30, 30], "name": "FP16_OVFL"}
15869   ]
15870  },
15871  "SPI_SHADER_PGM_RSRC1_PS": {
15872   "fields": [
15873    {"bits": [0, 5], "name": "VGPRS"},
15874    {"bits": [6, 9], "name": "SGPRS"},
15875    {"bits": [10, 11], "name": "PRIORITY"},
15876    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15877    {"bits": [20, 20], "name": "PRIV"},
15878    {"bits": [21, 21], "name": "DX10_CLAMP"},
15879    {"bits": [23, 23], "name": "IEEE_MODE"},
15880    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
15881    {"bits": [25, 25], "name": "MEM_ORDERED"},
15882    {"bits": [26, 26], "name": "FWD_PROGRESS"},
15883    {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"},
15884    {"bits": [29, 29], "name": "FP16_OVFL"}
15885   ]
15886  },
15887  "SPI_SHADER_PGM_RSRC1_VS": {
15888   "fields": [
15889    {"bits": [0, 5], "name": "VGPRS"},
15890    {"bits": [6, 9], "name": "SGPRS"},
15891    {"bits": [10, 11], "name": "PRIORITY"},
15892    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
15893    {"bits": [20, 20], "name": "PRIV"},
15894    {"bits": [21, 21], "name": "DX10_CLAMP"},
15895    {"bits": [23, 23], "name": "IEEE_MODE"},
15896    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
15897    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
15898    {"bits": [27, 27], "name": "MEM_ORDERED"},
15899    {"bits": [28, 28], "name": "FWD_PROGRESS"},
15900    {"bits": [31, 31], "name": "FP16_OVFL"}
15901   ]
15902  },
15903  "SPI_SHADER_PGM_RSRC2_GS": {
15904   "fields": [
15905    {"bits": [0, 0], "name": "SCRATCH_EN"},
15906    {"bits": [1, 5], "name": "USER_SGPR"},
15907    {"bits": [6, 6], "name": "TRAP_PRESENT"},
15908    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
15909    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
15910    {"bits": [18, 18], "name": "OC_LDS_EN"},
15911    {"bits": [19, 26], "name": "LDS_SIZE"},
15912    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
15913    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
15914   ]
15915  },
15916  "SPI_SHADER_PGM_RSRC2_GS_VS": {
15917   "fields": [
15918    {"bits": [0, 0], "name": "SCRATCH_EN"},
15919    {"bits": [1, 5], "name": "USER_SGPR"},
15920    {"bits": [6, 6], "name": "TRAP_PRESENT"},
15921    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
15922    {"bits": [16, 17], "name": "VGPR_COMP_CNT"},
15923    {"bits": [18, 18], "name": "OC_LDS_EN"},
15924    {"bits": [19, 26], "name": "LDS_SIZE"},
15925    {"bits": [27, 27], "name": "SKIP_USGPR0"},
15926    {"bits": [28, 28], "name": "USER_SGPR_MSB"}
15927   ]
15928  },
15929  "SPI_SHADER_PGM_RSRC2_HS": {
15930   "fields": [
15931    {"bits": [0, 0], "name": "SCRATCH_EN"},
15932    {"bits": [1, 5], "name": "USER_SGPR"},
15933    {"bits": [6, 6], "name": "TRAP_PRESENT"},
15934    {"bits": [7, 7], "name": "OC_LDS_EN"},
15935    {"bits": [8, 8], "name": "TG_SIZE_EN"},
15936    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
15937    {"bits": [18, 26], "name": "LDS_SIZE"},
15938    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
15939    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
15940   ]
15941  },
15942  "SPI_SHADER_PGM_RSRC2_PS": {
15943   "fields": [
15944    {"bits": [0, 0], "name": "SCRATCH_EN"},
15945    {"bits": [1, 5], "name": "USER_SGPR"},
15946    {"bits": [6, 6], "name": "TRAP_PRESENT"},
15947    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
15948    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
15949    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
15950    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
15951    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
15952    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
15953    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
15954   ]
15955  },
15956  "SPI_SHADER_PGM_RSRC2_VS": {
15957   "fields": [
15958    {"bits": [0, 0], "name": "SCRATCH_EN"},
15959    {"bits": [1, 5], "name": "USER_SGPR"},
15960    {"bits": [6, 6], "name": "TRAP_PRESENT"},
15961    {"bits": [7, 7], "name": "OC_LDS_EN"},
15962    {"bits": [8, 8], "name": "SO_BASE0_EN"},
15963    {"bits": [9, 9], "name": "SO_BASE1_EN"},
15964    {"bits": [10, 10], "name": "SO_BASE2_EN"},
15965    {"bits": [11, 11], "name": "SO_BASE3_EN"},
15966    {"bits": [12, 12], "name": "SO_EN"},
15967    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
15968    {"bits": [22, 22], "name": "PC_BASE_EN"},
15969    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"},
15970    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
15971    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
15972   ]
15973  },
15974  "SPI_SHADER_PGM_RSRC3_GS": {
15975   "fields": [
15976    {"bits": [0, 15], "name": "CU_EN"},
15977    {"bits": [16, 21], "name": "WAVE_LIMIT"},
15978    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
15979    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
15980   ]
15981  },
15982  "SPI_SHADER_PGM_RSRC3_HS": {
15983   "fields": [
15984    {"bits": [0, 5], "name": "WAVE_LIMIT"},
15985    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
15986    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
15987    {"bits": [16, 31], "name": "CU_EN"}
15988   ]
15989  },
15990  "SPI_SHADER_PGM_RSRC3_PS": {
15991   "fields": [
15992    {"bits": [0, 15], "name": "CU_EN"},
15993    {"bits": [16, 21], "name": "WAVE_LIMIT"},
15994    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
15995   ]
15996  },
15997  "SPI_SHADER_PGM_RSRC4_GS": {
15998   "fields": [
15999    {"bits": [0, 15], "name": "CU_EN"},
16000    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"}
16001   ]
16002  },
16003  "SPI_SHADER_PGM_RSRC4_PS": {
16004   "fields": [
16005    {"bits": [0, 15], "name": "CU_EN"}
16006   ]
16007  },
16008  "SPI_SHADER_POS_FORMAT": {
16009   "fields": [
16010    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
16011    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
16012    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
16013    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
16014    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
16015   ]
16016  },
16017  "SPI_SHADER_REQ_CTRL_PS": {
16018   "fields": [
16019    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
16020    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
16021    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
16022    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
16023    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
16024    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
16025    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
16026    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
16027   ]
16028  },
16029  "SPI_SHADER_USER_ACCUM_PS_0": {
16030   "fields": [
16031    {"bits": [0, 6], "name": "CONTRIBUTION"}
16032   ]
16033  },
16034  "SPI_SHADER_USER_DATA_PS_0": {
16035   "fields": [
16036    {"bits": [0, 31], "name": "DATA"}
16037   ]
16038  },
16039  "SPI_SHADER_Z_FORMAT": {
16040   "fields": [
16041    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
16042   ]
16043  },
16044  "SPI_VS_OUT_CONFIG": {
16045   "fields": [
16046    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
16047    {"bits": [6, 6], "name": "VS_HALF_PACK"},
16048    {"bits": [7, 7], "name": "NO_PC_EXPORT"},
16049    {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"}
16050   ]
16051  },
16052  "SQC_CACHES": {
16053   "fields": [
16054    {"bits": [0, 0], "name": "TARGET_INST"},
16055    {"bits": [1, 1], "name": "TARGET_DATA"},
16056    {"bits": [2, 2], "name": "INVALIDATE"},
16057    {"bits": [16, 16], "name": "COMPLETE"},
16058    {"bits": [17, 18], "name": "L2_WB_POLICY"}
16059   ]
16060  },
16061  "SQ_PERFCOUNTER0_SELECT": {
16062   "fields": [
16063    {"bits": [0, 8], "name": "PERF_SEL"},
16064    {"bits": [20, 23], "name": "SPM_MODE"},
16065    {"bits": [28, 31], "name": "PERF_MODE"}
16066   ]
16067  },
16068  "SQ_PERFCOUNTER_CTRL": {
16069   "fields": [
16070    {"bits": [0, 0], "name": "PS_EN"},
16071    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16072    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16073    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16074    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16075    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16076    {"bits": [6, 6], "name": "CS_EN"},
16077    {"bits": [8, 9], "name": "CNTR_RATE"},
16078    {"bits": [13, 13], "name": "DISABLE_FLUSH"},
16079    {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"},
16080    {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"},
16081    {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"},
16082    {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"},
16083    {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"},
16084    {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"}
16085   ]
16086  },
16087  "SQ_PERFCOUNTER_CTRL2": {
16088   "fields": [
16089    {"bits": [0, 0], "name": "FORCE_EN"}
16090   ]
16091  },
16092  "SQ_THREAD_TRACE_BUF0_BASE": {
16093   "fields": [
16094    {"bits": [0, 31], "name": "BASE_LO"}
16095   ]
16096  },
16097  "SQ_THREAD_TRACE_BUF0_SIZE": {
16098   "fields": [
16099    {"bits": [0, 3], "name": "BASE_HI"},
16100    {"bits": [8, 29], "name": "SIZE"}
16101   ]
16102  },
16103  "SQ_THREAD_TRACE_CTRL": {
16104   "fields": [
16105    {"bits": [0, 1], "name": "MODE"},
16106    {"bits": [2, 2], "name": "ALL_VMID"},
16107    {"bits": [3, 3], "name": "CH_PERF_EN"},
16108    {"bits": [4, 4], "name": "INTERRUPT_EN"},
16109    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
16110    {"bits": [6, 8], "name": "HIWATER"},
16111    {"bits": [9, 9], "name": "REG_STALL_EN"},
16112    {"bits": [10, 10], "name": "SPI_STALL_EN"},
16113    {"bits": [11, 11], "name": "SQ_STALL_EN"},
16114    {"bits": [12, 12], "name": "REG_DROP_ON_STALL"},
16115    {"bits": [13, 13], "name": "UTIL_TIMER"},
16116    {"bits": [14, 15], "name": "WAVESTART_MODE"},
16117    {"bits": [16, 17], "name": "RT_FREQ"},
16118    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
16119    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
16120    {"bits": [20, 22], "name": "LOWATER_OFFSET"},
16121    {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"},
16122    {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"},
16123    {"bits": [30, 30], "name": "CAPTURE_ALL"},
16124    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
16125   ]
16126  },
16127  "SQ_THREAD_TRACE_DROPPED_CNTR": {
16128   "fields": [
16129    {"bits": [0, 31], "name": "CNTR"}
16130   ]
16131  },
16132  "SQ_THREAD_TRACE_MASK": {
16133   "fields": [
16134    {"bits": [0, 1], "name": "SIMD_SEL"},
16135    {"bits": [4, 7], "name": "WGP_SEL"},
16136    {"bits": [9, 9], "name": "SA_SEL"},
16137    {"bits": [10, 16], "name": "WTYPE_INCLUDE"}
16138   ]
16139  },
16140  "SQ_THREAD_TRACE_STATUS": {
16141   "fields": [
16142    {"bits": [0, 11], "name": "FINISH_PENDING"},
16143    {"bits": [12, 23], "name": "FINISH_DONE"},
16144    {"bits": [24, 24], "name": "UTC_ERR"},
16145    {"bits": [25, 25], "name": "BUSY"},
16146    {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"},
16147    {"bits": [27, 27], "name": "EVENT_CNTR_STALL"},
16148    {"bits": [28, 31], "name": "OWNER_VMID"}
16149   ]
16150  },
16151  "SQ_THREAD_TRACE_STATUS2": {
16152   "fields": [
16153    {"bits": [0, 0], "name": "BUF0_FULL"},
16154    {"bits": [1, 1], "name": "BUF1_FULL"},
16155    {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"}
16156   ]
16157  },
16158  "SQ_THREAD_TRACE_TOKEN_MASK": {
16159   "fields": [
16160    {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
16161    {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"},
16162    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
16163    {"bits": [24, 25], "name": "INST_EXCLUDE"},
16164    {"bits": [26, 28], "name": "REG_EXCLUDE"},
16165    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
16166   ]
16167  },
16168  "SQ_THREAD_TRACE_WPTR": {
16169   "fields": [
16170    {"bits": [0, 28], "name": "OFFSET"},
16171    {"bits": [31, 31], "name": "BUFFER_ID"}
16172   ]
16173  },
16174  "SQ_WAVE_ACTIVE": {
16175   "fields": [
16176    {"bits": [0, 19], "name": "WAVE_SLOT"}
16177   ]
16178  },
16179  "SQ_WAVE_EXEC_HI": {
16180   "fields": [
16181    {"bits": [0, 31], "name": "EXEC_HI"}
16182   ]
16183  },
16184  "SQ_WAVE_EXEC_LO": {
16185   "fields": [
16186    {"bits": [0, 31], "name": "EXEC_LO"}
16187   ]
16188  },
16189  "SQ_WAVE_FLUSH_IB": {
16190   "fields": [
16191    {"bits": [0, 31], "name": "UNUSED"}
16192   ]
16193  },
16194  "SQ_WAVE_GPR_ALLOC": {
16195   "fields": [
16196    {"bits": [0, 7], "name": "VGPR_BASE"},
16197    {"bits": [8, 15], "name": "VGPR_SIZE"},
16198    {"bits": [16, 23], "name": "SGPR_BASE"},
16199    {"bits": [24, 27], "name": "SGPR_SIZE"}
16200   ]
16201  },
16202  "SQ_WAVE_HW_ID1": {
16203   "fields": [
16204    {"bits": [0, 4], "name": "WAVE_ID"},
16205    {"bits": [8, 9], "name": "SIMD_ID"},
16206    {"bits": [10, 13], "name": "WGP_ID"},
16207    {"bits": [16, 16], "name": "SA_ID"},
16208    {"bits": [18, 19], "name": "SE_ID"}
16209   ]
16210  },
16211  "SQ_WAVE_HW_ID2": {
16212   "fields": [
16213    {"bits": [0, 3], "name": "QUEUE_ID"},
16214    {"bits": [4, 5], "name": "PIPE_ID"},
16215    {"bits": [8, 9], "name": "ME_ID"},
16216    {"bits": [12, 14], "name": "STATE_ID"},
16217    {"bits": [16, 20], "name": "WG_ID"},
16218    {"bits": [24, 27], "name": "VM_ID"}
16219   ]
16220  },
16221  "SQ_WAVE_HW_ID_LEGACY": {
16222   "fields": [
16223    {"bits": [0, 3], "name": "WAVE_ID"},
16224    {"bits": [4, 5], "name": "SIMD_ID"},
16225    {"bits": [6, 7], "name": "PIPE_ID"},
16226    {"bits": [8, 11], "name": "CU_ID"},
16227    {"bits": [12, 12], "name": "SH_ID"},
16228    {"bits": [13, 14], "name": "SE_ID"},
16229    {"bits": [15, 15], "name": "WAVE_ID_MSB"},
16230    {"bits": [16, 19], "name": "TG_ID"},
16231    {"bits": [20, 23], "name": "VM_ID"},
16232    {"bits": [24, 26], "name": "QUEUE_ID"},
16233    {"bits": [27, 29], "name": "STATE_ID"},
16234    {"bits": [30, 31], "name": "ME_ID"}
16235   ]
16236  },
16237  "SQ_WAVE_IB_DBG1": {
16238   "fields": [
16239    {"bits": [24, 24], "name": "WAVE_IDLE"},
16240    {"bits": [25, 31], "name": "MISC_CNT"}
16241   ]
16242  },
16243  "SQ_WAVE_IB_STS": {
16244   "fields": [
16245    {"bits": [0, 3], "name": "VM_CNT"},
16246    {"bits": [4, 6], "name": "EXP_CNT"},
16247    {"bits": [7, 7], "name": "LGKM_CNT_BIT4"},
16248    {"bits": [8, 11], "name": "LGKM_CNT"},
16249    {"bits": [12, 14], "name": "VALU_CNT"},
16250    {"bits": [22, 23], "name": "VM_CNT_HI"},
16251    {"bits": [24, 24], "name": "LGKM_CNT_BIT5"},
16252    {"bits": [26, 31], "name": "VS_CNT"}
16253   ]
16254  },
16255  "SQ_WAVE_IB_STS2": {
16256   "fields": [
16257    {"bits": [0, 1], "name": "INST_PREFETCH"},
16258    {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"},
16259    {"bits": [8, 9], "name": "MEM_ORDER"},
16260    {"bits": [10, 10], "name": "FWD_PROGRESS"},
16261    {"bits": [11, 11], "name": "WAVE64"}
16262   ]
16263  },
16264  "SQ_WAVE_INST_DW0": {
16265   "fields": [
16266    {"bits": [0, 31], "name": "INST_DW0"}
16267   ]
16268  },
16269  "SQ_WAVE_LDS_ALLOC": {
16270   "fields": [
16271    {"bits": [0, 8], "name": "LDS_BASE"},
16272    {"bits": [12, 20], "name": "LDS_SIZE"},
16273    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
16274   ]
16275  },
16276  "SQ_WAVE_M0": {
16277   "fields": [
16278    {"bits": [0, 31], "name": "M0"}
16279   ]
16280  },
16281  "SQ_WAVE_MODE": {
16282   "fields": [
16283    {"bits": [0, 3], "name": "FP_ROUND"},
16284    {"bits": [4, 7], "name": "FP_DENORM"},
16285    {"bits": [8, 8], "name": "DX10_CLAMP"},
16286    {"bits": [9, 9], "name": "IEEE"},
16287    {"bits": [10, 10], "name": "LOD_CLAMPED"},
16288    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
16289    {"bits": [23, 23], "name": "FP16_OVFL"},
16290    {"bits": [27, 27], "name": "DISABLE_PERF"}
16291   ]
16292  },
16293  "SQ_WAVE_PC_HI": {
16294   "fields": [
16295    {"bits": [0, 15], "name": "PC_HI"}
16296   ]
16297  },
16298  "SQ_WAVE_PC_LO": {
16299   "fields": [
16300    {"bits": [0, 31], "name": "PC_LO"}
16301   ]
16302  },
16303  "SQ_WAVE_POPS_PACKER": {
16304   "fields": [
16305    {"bits": [0, 0], "name": "POPS_EN"},
16306    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
16307   ]
16308  },
16309  "SQ_WAVE_SCHED_MODE": {
16310   "fields": [
16311    {"bits": [0, 1], "name": "DEP_MODE"}
16312   ]
16313  },
16314  "SQ_WAVE_SHADER_CYCLES": {
16315   "fields": [
16316    {"bits": [0, 19], "name": "CYCLES"}
16317   ]
16318  },
16319  "SQ_WAVE_STATUS": {
16320   "fields": [
16321    {"bits": [0, 0], "name": "SCC"},
16322    {"bits": [1, 2], "name": "SPI_PRIO"},
16323    {"bits": [3, 4], "name": "USER_PRIO"},
16324    {"bits": [5, 5], "name": "PRIV"},
16325    {"bits": [6, 6], "name": "TRAP_EN"},
16326    {"bits": [7, 7], "name": "TTRACE_EN"},
16327    {"bits": [8, 8], "name": "EXPORT_RDY"},
16328    {"bits": [9, 9], "name": "EXECZ"},
16329    {"bits": [10, 10], "name": "VCCZ"},
16330    {"bits": [11, 11], "name": "IN_TG"},
16331    {"bits": [12, 12], "name": "IN_BARRIER"},
16332    {"bits": [13, 13], "name": "HALT"},
16333    {"bits": [14, 14], "name": "TRAP"},
16334    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
16335    {"bits": [16, 16], "name": "VALID"},
16336    {"bits": [17, 17], "name": "ECC_ERR"},
16337    {"bits": [18, 18], "name": "SKIP_EXPORT"},
16338    {"bits": [19, 19], "name": "PERF_EN"},
16339    {"bits": [23, 23], "name": "FATAL_HALT"},
16340    {"bits": [27, 27], "name": "MUST_EXPORT"}
16341   ]
16342  },
16343  "SQ_WAVE_TRAPSTS": {
16344   "fields": [
16345    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
16346    {"bits": [10, 10], "name": "SAVECTX"},
16347    {"bits": [11, 11], "name": "ILLEGAL_INST"},
16348    {"bits": [12, 14], "name": "EXCP_HI"},
16349    {"bits": [15, 15], "name": "BUFFER_OOB"},
16350    {"bits": [16, 19], "name": "EXCP_CYCLE"},
16351    {"bits": [20, 23], "name": "EXCP_GROUP_MASK"},
16352    {"bits": [24, 24], "name": "EXCP_WAVE64HI"},
16353    {"bits": [28, 28], "name": "UTC_ERROR"},
16354    {"bits": [29, 31], "name": "DP_RATE"}
16355   ]
16356  },
16357  "SQ_WAVE_VGPR_OFFSET": {
16358   "fields": [
16359    {"bits": [0, 5], "name": "SRC0"},
16360    {"bits": [6, 11], "name": "SRC1"},
16361    {"bits": [12, 17], "name": "SRC2"},
16362    {"bits": [18, 23], "name": "DST"}
16363   ]
16364  },
16365  "SX_BLEND_OPT_CONTROL": {
16366   "fields": [
16367    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
16368    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
16369    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
16370    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
16371    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
16372    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
16373    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
16374    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
16375    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
16376    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
16377    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
16378    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
16379    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
16380    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
16381    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
16382    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
16383    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
16384   ]
16385  },
16386  "SX_BLEND_OPT_EPSILON": {
16387   "fields": [
16388    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
16389    {"bits": [4, 7], "name": "MRT1_EPSILON"},
16390    {"bits": [8, 11], "name": "MRT2_EPSILON"},
16391    {"bits": [12, 15], "name": "MRT3_EPSILON"},
16392    {"bits": [16, 19], "name": "MRT4_EPSILON"},
16393    {"bits": [20, 23], "name": "MRT5_EPSILON"},
16394    {"bits": [24, 27], "name": "MRT6_EPSILON"},
16395    {"bits": [28, 31], "name": "MRT7_EPSILON"}
16396   ]
16397  },
16398  "SX_MRT0_BLEND_OPT": {
16399   "fields": [
16400    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
16401    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
16402    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
16403    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
16404    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
16405    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
16406   ]
16407  },
16408  "SX_PERFCOUNTER2_SELECT": {
16409   "fields": [
16410    {"bits": [0, 9], "name": "PERF_SEL"},
16411    {"bits": [20, 23], "name": "CNTR_MODE"},
16412    {"bits": [28, 31], "name": "PERF_MODE"}
16413   ]
16414  },
16415  "SX_PS_DOWNCONVERT": {
16416   "fields": [
16417    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
16418    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
16419    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
16420    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
16421    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
16422    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
16423    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
16424    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
16425   ]
16426  },
16427  "SX_PS_DOWNCONVERT_CONTROL": {
16428   "fields": [
16429    {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
16430    {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
16431    {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
16432    {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
16433    {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
16434    {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
16435    {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
16436    {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
16437   ]
16438  },
16439  "TA_BC_BASE_ADDR": {
16440   "fields": [
16441    {"bits": [0, 31], "name": "ADDRESS"}
16442   ]
16443  },
16444  "TA_BC_BASE_ADDR_HI": {
16445   "fields": [
16446    {"bits": [0, 7], "name": "ADDRESS"}
16447   ]
16448  },
16449  "UTCL1_PERFCOUNTER0_SELECT": {
16450   "fields": [
16451    {"bits": [0, 9], "name": "PERF_SEL"},
16452    {"bits": [28, 31], "name": "COUNTER_MODE"}
16453   ]
16454  },
16455  "VGT_DISPATCH_DRAW_INDEX": {
16456   "fields": [
16457    {"bits": [0, 31], "name": "MATCH_INDEX"}
16458   ]
16459  },
16460  "VGT_DMA_BASE": {
16461   "fields": [
16462    {"bits": [0, 31], "name": "BASE_ADDR"}
16463   ]
16464  },
16465  "VGT_DMA_BASE_HI": {
16466   "fields": [
16467    {"bits": [0, 15], "name": "BASE_ADDR"}
16468   ]
16469  },
16470  "VGT_DMA_INDEX_TYPE": {
16471   "fields": [
16472    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
16473    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
16474    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
16475    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
16476    {"bits": [8, 8], "name": "ATC"},
16477    {"bits": [9, 9], "name": "NOT_EOP"},
16478    {"bits": [10, 10], "name": "REQ_PATH"},
16479    {"bits": [11, 13], "name": "MTYPE"},
16480    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
16481   ]
16482  },
16483  "VGT_DMA_MAX_SIZE": {
16484   "fields": [
16485    {"bits": [0, 31], "name": "MAX_SIZE"}
16486   ]
16487  },
16488  "VGT_DMA_NUM_INSTANCES": {
16489   "fields": [
16490    {"bits": [0, 31], "name": "NUM_INSTANCES"}
16491   ]
16492  },
16493  "VGT_DMA_SIZE": {
16494   "fields": [
16495    {"bits": [0, 31], "name": "NUM_INDICES"}
16496   ]
16497  },
16498  "VGT_DRAW_INITIATOR": {
16499   "fields": [
16500    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
16501    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
16502    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
16503    {"bits": [5, 5], "name": "NOT_EOP"},
16504    {"bits": [6, 6], "name": "USE_OPAQUE"},
16505    {"bits": [29, 31], "name": "REG_RT_INDEX"}
16506   ]
16507  },
16508  "VGT_DRAW_PAYLOAD_CNTL": {
16509   "fields": [
16510    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
16511    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
16512    {"bits": [4, 4], "name": "EN_DRAW_VP"}
16513   ]
16514  },
16515  "VGT_ENHANCE": {
16516   "fields": [
16517    {"bits": [0, 31], "name": "MISC"}
16518   ]
16519  },
16520  "VGT_ESGS_RING_ITEMSIZE": {
16521   "fields": [
16522    {"bits": [0, 14], "name": "ITEMSIZE"}
16523   ]
16524  },
16525  "VGT_ESGS_RING_SIZE_UMD": {
16526   "fields": [
16527    {"bits": [0, 31], "name": "MEM_SIZE"}
16528   ]
16529  },
16530  "VGT_ES_PER_GS": {
16531   "fields": [
16532    {"bits": [0, 10], "name": "ES_PER_GS"}
16533   ]
16534  },
16535  "VGT_EVENT_ADDRESS_REG": {
16536   "fields": [
16537    {"bits": [0, 27], "name": "ADDRESS_LOW"}
16538   ]
16539  },
16540  "VGT_EVENT_INITIATOR": {
16541   "fields": [
16542    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
16543    {"bits": [10, 26], "name": "ADDRESS_HI"},
16544    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
16545   ]
16546  },
16547  "VGT_GROUP_DECR": {
16548   "fields": [
16549    {"bits": [0, 3], "name": "DECR"}
16550   ]
16551  },
16552  "VGT_GROUP_FIRST_DECR": {
16553   "fields": [
16554    {"bits": [0, 3], "name": "FIRST_DECR"}
16555   ]
16556  },
16557  "VGT_GROUP_PRIM_TYPE": {
16558   "fields": [
16559    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
16560    {"bits": [14, 14], "name": "RETAIN_ORDER"},
16561    {"bits": [15, 15], "name": "RETAIN_QUADS"},
16562    {"bits": [16, 18], "name": "PRIM_ORDER"}
16563   ]
16564  },
16565  "VGT_GROUP_VECT_0_CNTL": {
16566   "fields": [
16567    {"bits": [0, 0], "name": "COMP_X_EN"},
16568    {"bits": [1, 1], "name": "COMP_Y_EN"},
16569    {"bits": [2, 2], "name": "COMP_Z_EN"},
16570    {"bits": [3, 3], "name": "COMP_W_EN"},
16571    {"bits": [8, 15], "name": "STRIDE"},
16572    {"bits": [16, 23], "name": "SHIFT"}
16573   ]
16574  },
16575  "VGT_GROUP_VECT_0_FMT_CNTL": {
16576   "fields": [
16577    {"bits": [0, 3], "name": "X_CONV"},
16578    {"bits": [4, 7], "name": "X_OFFSET"},
16579    {"bits": [8, 11], "name": "Y_CONV"},
16580    {"bits": [12, 15], "name": "Y_OFFSET"},
16581    {"bits": [16, 19], "name": "Z_CONV"},
16582    {"bits": [20, 23], "name": "Z_OFFSET"},
16583    {"bits": [24, 27], "name": "W_CONV"},
16584    {"bits": [28, 31], "name": "W_OFFSET"}
16585   ]
16586  },
16587  "VGT_GSVS_RING_OFFSET_1": {
16588   "fields": [
16589    {"bits": [0, 14], "name": "OFFSET"}
16590   ]
16591  },
16592  "VGT_GS_INSTANCE_CNT": {
16593   "fields": [
16594    {"bits": [0, 0], "name": "ENABLE"},
16595    {"bits": [2, 8], "name": "CNT"},
16596    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
16597   ]
16598  },
16599  "VGT_GS_MAX_VERT_OUT": {
16600   "fields": [
16601    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
16602   ]
16603  },
16604  "VGT_GS_MODE": {
16605   "fields": [
16606    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
16607    {"bits": [3, 3], "name": "RESERVED_0"},
16608    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
16609    {"bits": [6, 10], "name": "RESERVED_1"},
16610    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
16611    {"bits": [12, 12], "name": "RESERVED_2"},
16612    {"bits": [13, 13], "name": "ES_PASSTHRU"},
16613    {"bits": [14, 14], "name": "COMPUTE_MODE"},
16614    {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
16615    {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
16616    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
16617    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
16618    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
16619    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
16620    {"bits": [21, 22], "name": "ONCHIP"}
16621   ]
16622  },
16623  "VGT_GS_ONCHIP_CNTL": {
16624   "fields": [
16625    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
16626    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"},
16627    {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"}
16628   ]
16629  },
16630  "VGT_GS_OUT_PRIM_TYPE": {
16631   "fields": [
16632    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
16633    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
16634    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
16635    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
16636    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
16637   ]
16638  },
16639  "VGT_GS_PER_ES": {
16640   "fields": [
16641    {"bits": [0, 10], "name": "GS_PER_ES"}
16642   ]
16643  },
16644  "VGT_GS_PER_VS": {
16645   "fields": [
16646    {"bits": [0, 3], "name": "GS_PER_VS"}
16647   ]
16648  },
16649  "VGT_HOS_CNTL": {
16650   "fields": [
16651    {"bits": [0, 1], "name": "TESS_MODE"}
16652   ]
16653  },
16654  "VGT_HOS_MAX_TESS_LEVEL": {
16655   "fields": [
16656    {"bits": [0, 31], "name": "MAX_TESS"}
16657   ]
16658  },
16659  "VGT_HOS_MIN_TESS_LEVEL": {
16660   "fields": [
16661    {"bits": [0, 31], "name": "MIN_TESS"}
16662   ]
16663  },
16664  "VGT_HOS_REUSE_DEPTH": {
16665   "fields": [
16666    {"bits": [0, 7], "name": "REUSE_DEPTH"}
16667   ]
16668  },
16669  "VGT_HS_OFFCHIP_PARAM_UMD": {
16670   "fields": [
16671    {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
16672    {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
16673   ]
16674  },
16675  "VGT_INDEX_TYPE": {
16676   "fields": [
16677    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
16678    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
16679   ]
16680  },
16681  "VGT_INDX_OFFSET": {
16682   "fields": [
16683    {"bits": [0, 31], "name": "INDX_OFFSET"}
16684   ]
16685  },
16686  "VGT_INSTANCE_BASE_ID": {
16687   "fields": [
16688    {"bits": [0, 31], "name": "INSTANCE_BASE_ID"}
16689   ]
16690  },
16691  "VGT_INSTANCE_STEP_RATE_0": {
16692   "fields": [
16693    {"bits": [0, 31], "name": "STEP_RATE"}
16694   ]
16695  },
16696  "VGT_LS_HS_CONFIG": {
16697   "fields": [
16698    {"bits": [0, 7], "name": "NUM_PATCHES"},
16699    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
16700    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
16701   ]
16702  },
16703  "VGT_MAX_VTX_INDX": {
16704   "fields": [
16705    {"bits": [0, 31], "name": "MAX_INDX"}
16706   ]
16707  },
16708  "VGT_MIN_VTX_INDX": {
16709   "fields": [
16710    {"bits": [0, 31], "name": "MIN_INDX"}
16711   ]
16712  },
16713  "VGT_MULTI_PRIM_IB_RESET_EN": {
16714   "fields": [
16715    {"bits": [0, 0], "name": "RESET_EN"},
16716    {"bits": [1, 1], "name": "MATCH_ALL_BITS"}
16717   ]
16718  },
16719  "VGT_MULTI_PRIM_IB_RESET_INDX": {
16720   "fields": [
16721    {"bits": [0, 31], "name": "RESET_INDX"}
16722   ]
16723  },
16724  "VGT_OUTPUT_PATH_CNTL": {
16725   "fields": [
16726    {"bits": [0, 2], "name": "PATH_SELECT"}
16727   ]
16728  },
16729  "VGT_OUT_DEALLOC_CNTL": {
16730   "fields": [
16731    {"bits": [0, 6], "name": "DEALLOC_DIST"}
16732   ]
16733  },
16734  "VGT_PRIMITIVEID_EN": {
16735   "fields": [
16736    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
16737    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
16738    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
16739   ]
16740  },
16741  "VGT_PRIMITIVEID_RESET": {
16742   "fields": [
16743    {"bits": [0, 31], "name": "VALUE"}
16744   ]
16745  },
16746  "VGT_PRIMITIVE_TYPE": {
16747   "fields": [
16748    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
16749   ]
16750  },
16751  "VGT_REUSE_OFF": {
16752   "fields": [
16753    {"bits": [0, 0], "name": "REUSE_OFF"}
16754   ]
16755  },
16756  "VGT_SHADER_STAGES_EN": {
16757   "fields": [
16758    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
16759    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
16760    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
16761    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
16762    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
16763    {"bits": [8, 8], "name": "DYNAMIC_HS"},
16764    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
16765    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
16766    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
16767    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
16768    {"bits": [13, 13], "name": "PRIMGEN_EN"},
16769    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
16770    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
16771    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
16772    {"bits": [21, 21], "name": "HS_W32_EN"},
16773    {"bits": [22, 22], "name": "GS_W32_EN"},
16774    {"bits": [23, 23], "name": "VS_W32_EN"},
16775    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
16776    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"}
16777   ]
16778  },
16779  "VGT_STRMOUT_BUFFER_CONFIG": {
16780   "fields": [
16781    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
16782    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
16783    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
16784    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
16785   ]
16786  },
16787  "VGT_STRMOUT_BUFFER_OFFSET_0": {
16788   "fields": [
16789    {"bits": [0, 31], "name": "OFFSET"}
16790   ]
16791  },
16792  "VGT_STRMOUT_CONFIG": {
16793   "fields": [
16794    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
16795    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
16796    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
16797    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
16798    {"bits": [4, 6], "name": "RAST_STREAM"},
16799    {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"},
16800    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
16801    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
16802   ]
16803  },
16804  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
16805   "fields": [
16806    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
16807   ]
16808  },
16809  "VGT_STRMOUT_VTX_STRIDE_0": {
16810   "fields": [
16811    {"bits": [0, 9], "name": "STRIDE"}
16812   ]
16813  },
16814  "VGT_TESS_DISTRIBUTION": {
16815   "fields": [
16816    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
16817    {"bits": [8, 15], "name": "ACCUM_TRI"},
16818    {"bits": [16, 23], "name": "ACCUM_QUAD"},
16819    {"bits": [24, 28], "name": "DONUT_SPLIT"},
16820    {"bits": [29, 31], "name": "TRAP_SPLIT"}
16821   ]
16822  },
16823  "VGT_TF_MEMORY_BASE_UMD": {
16824   "fields": [
16825    {"bits": [0, 31], "name": "BASE"}
16826   ]
16827  },
16828  "VGT_TF_PARAM": {
16829   "fields": [
16830    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
16831    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
16832    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
16833    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
16834    {"bits": [9, 9], "name": "DEPRECATED"},
16835    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
16836    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
16837    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
16838    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
16839    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
16840    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
16841    {"bits": [23, 25], "name": "MTYPE"}
16842   ]
16843  },
16844  "VGT_TF_RING_SIZE_UMD": {
16845   "fields": [
16846    {"bits": [0, 15], "name": "SIZE"}
16847   ]
16848  },
16849  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
16850   "fields": [
16851    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
16852   ]
16853  },
16854  "VGT_VTX_CNT_EN": {
16855   "fields": [
16856    {"bits": [0, 0], "name": "VTX_CNT_EN"}
16857   ]
16858  }
16859 }
16860}
16861