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349    {"name": "IMG_DATA_FORMAT_FMASK32_S8_F8", "value": 54},
350    {"name": "IMG_DATA_FORMAT_FMASK64_S16_F4", "value": 55},
351    {"name": "IMG_DATA_FORMAT_FMASK64_S16_F8", "value": 56},
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354    {"name": "IMG_DATA_FORMAT_1", "value": 59},
355    {"name": "IMG_DATA_FORMAT_1_REVERSED", "value": 60},
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358    {"name": "IMG_DATA_FORMAT_32_AS_32_32_32_32", "value": 63}
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367    {"name": "IMG_NUM_FORMAT_UINT", "value": 4},
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370    {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},
371    {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},
372    {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},
373    {"name": "IMG_NUM_FORMAT_RESERVED_10", "value": 10},
374    {"name": "IMG_NUM_FORMAT_RESERVED_11", "value": 11},
375    {"name": "IMG_NUM_FORMAT_RESERVED_12", "value": 12},
376    {"name": "IMG_NUM_FORMAT_RESERVED_13", "value": 13},
377    {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},
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380  },
381  "MacroTileAspect": {
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384    {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
385    {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
386    {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
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388  },
389  "MicroTileMode": {
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392    {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
393    {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
394    {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
395    {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
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398  "NumBanks": {
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401    {"name": "ADDR_SURF_4_BANK", "value": 1},
402    {"name": "ADDR_SURF_8_BANK", "value": 2},
403    {"name": "ADDR_SURF_16_BANK", "value": 3}
404   ]
405  },
406  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
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409    {"name": "X_DRAW_LINES", "value": 1},
410    {"name": "X_DRAW_TRIANGLES", "value": 2}
411   ]
412  },
413  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
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416    {"name": "X_DUAL_MODE", "value": 1}
417   ]
418  },
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422    {"name": "X_ROUND", "value": 1},
423    {"name": "X_ROUND_TO_EVEN", "value": 2},
424    {"name": "X_ROUND_TO_ODD", "value": 3}
425   ]
426  },
427  "PipeConfig": {
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430    {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
431    {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
432    {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
433    {"name": "ADDR_SURF_P4_8x16", "value": 4},
434    {"name": "ADDR_SURF_P4_16x16", "value": 5},
435    {"name": "ADDR_SURF_P4_16x32", "value": 6},
436    {"name": "ADDR_SURF_P4_32x32", "value": 7},
437    {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
438    {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
439    {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
440    {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
441    {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
442    {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
443    {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
444    {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
445    {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
446    {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}
447   ]
448  },
449  "PkrMap": {
450   "entries": [
451    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
452    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
453    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
454    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
455   ]
456  },
457  "PkrXsel": {
458   "entries": [
459    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
460    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
461    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
462    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
463   ]
464  },
465  "PkrXsel2": {
466   "entries": [
467    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
468    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
469    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
470    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
471   ]
472  },
473  "PkrYsel": {
474   "entries": [
475    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
476    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
477    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
478    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
479   ]
480  },
481  "QUANT_MODE": {
482   "entries": [
483    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
484    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
485    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
486    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
487    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
488    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
489    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
490    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
491   ]
492  },
493  "ROP3": {
494   "entries": [
495    {"name": "ROP3_CLEAR", "value": 0},
496    {"name": "X_0X05", "value": 5},
497    {"name": "X_0X0A", "value": 10},
498    {"name": "X_0X0F", "value": 15},
499    {"name": "ROP3_NOR", "value": 17},
500    {"name": "ROP3_AND_INVERTED", "value": 34},
501    {"name": "ROP3_COPY_INVERTED", "value": 51},
502    {"name": "ROP3_AND_REVERSE", "value": 68},
503    {"name": "X_0X50", "value": 80},
504    {"name": "ROP3_INVERT", "value": 85},
505    {"name": "X_0X5A", "value": 90},
506    {"name": "X_0X5F", "value": 95},
507    {"name": "ROP3_XOR", "value": 102},
508    {"name": "ROP3_NAND", "value": 119},
509    {"name": "ROP3_AND", "value": 136},
510    {"name": "ROP3_EQUIVALENT", "value": 153},
511    {"name": "X_0XA0", "value": 160},
512    {"name": "X_0XA5", "value": 165},
513    {"name": "ROP3_NO_OP", "value": 170},
514    {"name": "X_0XAF", "value": 175},
515    {"name": "ROP3_OR_INVERTED", "value": 187},
516    {"name": "ROP3_COPY", "value": 204},
517    {"name": "ROP3_OR_REVERSE", "value": 221},
518    {"name": "ROP3_OR", "value": 238},
519    {"name": "X_0XF0", "value": 240},
520    {"name": "X_0XF5", "value": 245},
521    {"name": "X_0XFA", "value": 250},
522    {"name": "ROP3_SET", "value": 255}
523   ]
524  },
525  "RbMap": {
526   "entries": [
527    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
528    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
529    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
530    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
531   ]
532  },
533  "RbXsel": {
534   "entries": [
535    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
536    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
537   ]
538  },
539  "RbXsel2": {
540   "entries": [
541    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
542    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
543    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
544    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
545   ]
546  },
547  "RbYsel": {
548   "entries": [
549    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
550    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
551   ]
552  },
553  "SPI_PNT_SPRITE_OVERRIDE": {
554   "entries": [
555    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
556    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
557    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
558    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
559    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
560   ]
561  },
562  "SPI_SHADER_EX_FORMAT": {
563   "entries": [
564    {"name": "SPI_SHADER_ZERO", "value": 0},
565    {"name": "SPI_SHADER_32_R", "value": 1},
566    {"name": "SPI_SHADER_32_GR", "value": 2},
567    {"name": "SPI_SHADER_32_AR", "value": 3},
568    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
569    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
570    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
571    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
572    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
573    {"name": "SPI_SHADER_32_ABGR", "value": 9}
574   ]
575  },
576  "SPI_SHADER_FORMAT": {
577   "entries": [
578    {"name": "SPI_SHADER_NONE", "value": 0},
579    {"name": "SPI_SHADER_1COMP", "value": 1},
580    {"name": "SPI_SHADER_2COMP", "value": 2},
581    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
582    {"name": "SPI_SHADER_4COMP", "value": 4}
583   ]
584  },
585  "SPM_PERFMON_STATE": {
586   "entries": [
587    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
588    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
589    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
590    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
591    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
592    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
593   ]
594  },
595  "SQ_IMG_FILTER_TYPE": {
596   "entries": [
597    {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},
598    {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},
599    {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}
600   ]
601  },
602  "SQ_RSRC_BUF_TYPE": {
603   "entries": [
604    {"name": "SQ_RSRC_BUF", "value": 0},
605    {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},
606    {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},
607    {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}
608   ]
609  },
610  "SQ_RSRC_IMG_TYPE": {
611   "entries": [
612    {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},
613    {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},
614    {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},
615    {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},
616    {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},
617    {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},
618    {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},
619    {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},
620    {"name": "SQ_RSRC_IMG_1D", "value": 8},
621    {"name": "SQ_RSRC_IMG_2D", "value": 9},
622    {"name": "SQ_RSRC_IMG_3D", "value": 10},
623    {"name": "SQ_RSRC_IMG_CUBE", "value": 11},
624    {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},
625    {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},
626    {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},
627    {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}
628   ]
629  },
630  "SQ_SEL_XYZW01": {
631   "entries": [
632    {"name": "SQ_SEL_0", "value": 0},
633    {"name": "SQ_SEL_1", "value": 1},
634    {"name": "SQ_SEL_RESERVED_0", "value": 2},
635    {"name": "SQ_SEL_RESERVED_1", "value": 3},
636    {"name": "SQ_SEL_X", "value": 4},
637    {"name": "SQ_SEL_Y", "value": 5},
638    {"name": "SQ_SEL_Z", "value": 6},
639    {"name": "SQ_SEL_W", "value": 7}
640   ]
641  },
642  "SQ_TEX_BORDER_COLOR": {
643   "entries": [
644    {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},
645    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},
646    {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},
647    {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}
648   ]
649  },
650  "SQ_TEX_CLAMP": {
651   "entries": [
652    {"name": "SQ_TEX_WRAP", "value": 0},
653    {"name": "SQ_TEX_MIRROR", "value": 1},
654    {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},
655    {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},
656    {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},
657    {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},
658    {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},
659    {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}
660   ]
661  },
662  "SQ_TEX_DEPTH_COMPARE": {
663   "entries": [
664    {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},
665    {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},
666    {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},
667    {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},
668    {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},
669    {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},
670    {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},
671    {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}
672   ]
673  },
674  "SQ_TEX_MIP_FILTER": {
675   "entries": [
676    {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},
677    {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},
678    {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2},
679    {"name": "SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ", "value": 3}
680   ]
681  },
682  "SQ_TEX_XY_FILTER": {
683   "entries": [
684    {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},
685    {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},
686    {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},
687    {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}
688   ]
689  },
690  "SQ_TEX_Z_FILTER": {
691   "entries": [
692    {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},
693    {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},
694    {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}
695   ]
696  },
697  "SX_BLEND_OPT": {
698   "entries": [
699    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
700    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
701    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
702    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
703    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
704    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
705    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
706    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
707   ]
708  },
709  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
710   "entries": [
711    {"name": "EXACT", "value": 0},
712    {"name": "11BIT_FORMAT", "value": 1},
713    {"name": "10BIT_FORMAT", "value": 3},
714    {"name": "8BIT_FORMAT", "value": 6},
715    {"name": "6BIT_FORMAT", "value": 11},
716    {"name": "5BIT_FORMAT", "value": 13},
717    {"name": "4BIT_FORMAT", "value": 15}
718   ]
719  },
720  "SX_DOWNCONVERT_FORMAT": {
721   "entries": [
722    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
723    {"name": "SX_RT_EXPORT_32_R", "value": 1},
724    {"name": "SX_RT_EXPORT_32_A", "value": 2},
725    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
726    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
727    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
728    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
729    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
730    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
731    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
732    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}
733   ]
734  },
735  "SX_OPT_COMB_FCN": {
736   "entries": [
737    {"name": "OPT_COMB_NONE", "value": 0},
738    {"name": "OPT_COMB_ADD", "value": 1},
739    {"name": "OPT_COMB_SUBTRACT", "value": 2},
740    {"name": "OPT_COMB_MIN", "value": 3},
741    {"name": "OPT_COMB_MAX", "value": 4},
742    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
743    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
744    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
745   ]
746  },
747  "ScMap": {
748   "entries": [
749    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
750    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
751    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
752    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
753   ]
754  },
755  "ScXsel": {
756   "entries": [
757    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
758    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
759    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
760    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
761   ]
762  },
763  "ScYsel": {
764   "entries": [
765    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
766    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
767    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
768    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
769   ]
770  },
771  "SeMap": {
772   "entries": [
773    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
774    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
775    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
776    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
777   ]
778  },
779  "SePairMap": {
780   "entries": [
781    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
782    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
783    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
784    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
785   ]
786  },
787  "SePairXsel": {
788   "entries": [
789    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
790    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
791    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
792    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
793   ]
794  },
795  "SePairYsel": {
796   "entries": [
797    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
798    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
799    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
800    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
801   ]
802  },
803  "SeXsel": {
804   "entries": [
805    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
806    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
807    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
808    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
809   ]
810  },
811  "SeYsel": {
812   "entries": [
813    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
814    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
815    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
816    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
817   ]
818  },
819  "StencilFormat": {
820   "entries": [
821    {"name": "STENCIL_INVALID", "value": 0},
822    {"name": "STENCIL_8", "value": 1}
823   ]
824  },
825  "StencilOp": {
826   "entries": [
827    {"name": "STENCIL_KEEP", "value": 0},
828    {"name": "STENCIL_ZERO", "value": 1},
829    {"name": "STENCIL_ONES", "value": 2},
830    {"name": "STENCIL_REPLACE_TEST", "value": 3},
831    {"name": "STENCIL_REPLACE_OP", "value": 4},
832    {"name": "STENCIL_ADD_CLAMP", "value": 5},
833    {"name": "STENCIL_SUB_CLAMP", "value": 6},
834    {"name": "STENCIL_INVERT", "value": 7},
835    {"name": "STENCIL_ADD_WRAP", "value": 8},
836    {"name": "STENCIL_SUB_WRAP", "value": 9},
837    {"name": "STENCIL_AND", "value": 10},
838    {"name": "STENCIL_OR", "value": 11},
839    {"name": "STENCIL_XOR", "value": 12},
840    {"name": "STENCIL_NAND", "value": 13},
841    {"name": "STENCIL_NOR", "value": 14},
842    {"name": "STENCIL_XNOR", "value": 15}
843   ]
844  },
845  "SurfaceEndian": {
846   "entries": [
847    {"name": "ENDIAN_NONE", "value": 0},
848    {"name": "ENDIAN_8IN16", "value": 1},
849    {"name": "ENDIAN_8IN32", "value": 2},
850    {"name": "ENDIAN_8IN64", "value": 3}
851   ]
852  },
853  "SurfaceNumber": {
854   "entries": [
855    {"name": "NUMBER_UNORM", "value": 0},
856    {"name": "NUMBER_SNORM", "value": 1},
857    {"name": "NUMBER_USCALED", "value": 2},
858    {"name": "NUMBER_SSCALED", "value": 3},
859    {"name": "NUMBER_UINT", "value": 4},
860    {"name": "NUMBER_SINT", "value": 5},
861    {"name": "NUMBER_SRGB", "value": 6},
862    {"name": "NUMBER_FLOAT", "value": 7}
863   ]
864  },
865  "SurfaceSwap": {
866   "entries": [
867    {"name": "SWAP_STD", "value": 0},
868    {"name": "SWAP_ALT", "value": 1},
869    {"name": "SWAP_STD_REV", "value": 2},
870    {"name": "SWAP_ALT_REV", "value": 3}
871   ]
872  },
873  "TileSplit": {
874   "entries": [
875    {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
876    {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
877    {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
878    {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
879    {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
880    {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
881    {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
882   ]
883  },
884  "VGT_DIST_MODE": {
885   "entries": [
886    {"name": "NO_DIST", "value": 0},
887    {"name": "PATCHES", "value": 1},
888    {"name": "DONUTS", "value": 2}
889   ]
890  },
891  "VGT_DI_MAJOR_MODE_SELECT": {
892   "entries": [
893    {"name": "DI_MAJOR_MODE_0", "value": 0},
894    {"name": "DI_MAJOR_MODE_1", "value": 1}
895   ]
896  },
897  "VGT_DI_PRIM_TYPE": {
898   "entries": [
899    {"name": "DI_PT_NONE", "value": 0},
900    {"name": "DI_PT_POINTLIST", "value": 1},
901    {"name": "DI_PT_LINELIST", "value": 2},
902    {"name": "DI_PT_LINESTRIP", "value": 3},
903    {"name": "DI_PT_TRILIST", "value": 4},
904    {"name": "DI_PT_TRIFAN", "value": 5},
905    {"name": "DI_PT_TRISTRIP", "value": 6},
906    {"name": "DI_PT_UNUSED_0", "value": 7},
907    {"name": "DI_PT_UNUSED_1", "value": 8},
908    {"name": "DI_PT_PATCH", "value": 9},
909    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
910    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
911    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
912    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
913    {"name": "DI_PT_UNUSED_3", "value": 14},
914    {"name": "DI_PT_UNUSED_4", "value": 15},
915    {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
916    {"name": "DI_PT_RECTLIST", "value": 17},
917    {"name": "DI_PT_LINELOOP", "value": 18},
918    {"name": "DI_PT_QUADLIST", "value": 19},
919    {"name": "DI_PT_QUADSTRIP", "value": 20},
920    {"name": "DI_PT_POLYGON", "value": 21},
921    {"name": "DI_PT_2D_COPY_RECT_LIST_V0", "value": 22},
922    {"name": "DI_PT_2D_COPY_RECT_LIST_V1", "value": 23},
923    {"name": "DI_PT_2D_COPY_RECT_LIST_V2", "value": 24},
924    {"name": "DI_PT_2D_COPY_RECT_LIST_V3", "value": 25},
925    {"name": "DI_PT_2D_FILL_RECT_LIST", "value": 26},
926    {"name": "DI_PT_2D_LINE_STRIP", "value": 27},
927    {"name": "DI_PT_2D_TRI_STRIP", "value": 28}
928   ]
929  },
930  "VGT_DI_SOURCE_SELECT": {
931   "entries": [
932    {"name": "DI_SRC_SEL_DMA", "value": 0},
933    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
934    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
935    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
936   ]
937  },
938  "VGT_DMA_BUF_TYPE": {
939   "entries": [
940    {"name": "VGT_DMA_BUF_MEM", "value": 0},
941    {"name": "VGT_DMA_BUF_RING", "value": 1},
942    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
943    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
944   ]
945  },
946  "VGT_DMA_SWAP_MODE": {
947   "entries": [
948    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
949    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
950    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
951    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
952   ]
953  },
954  "VGT_EVENT_TYPE": {
955   "entries": [
956    {"name": "Reserved_0x00", "value": 0},
957    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
958    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
959    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
960    {"name": "CACHE_FLUSH_TS", "value": 4},
961    {"name": "CONTEXT_DONE", "value": 5},
962    {"name": "CACHE_FLUSH", "value": 6},
963    {"name": "CS_PARTIAL_FLUSH", "value": 7},
964    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
965    {"name": "Reserved_0x09", "value": 9},
966    {"name": "VGT_STREAMOUT_RESET", "value": 10},
967    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
968    {"name": "END_OF_PIPE_IB_END", "value": 12},
969    {"name": "RST_PIX_CNT", "value": 13},
970    {"name": "Reserved_0x0E", "value": 14},
971    {"name": "VS_PARTIAL_FLUSH", "value": 15},
972    {"name": "PS_PARTIAL_FLUSH", "value": 16},
973    {"name": "FLUSH_HS_OUTPUT", "value": 17},
974    {"name": "FLUSH_LS_OUTPUT", "value": 18},
975    {"name": "Reserved_0x13", "value": 19},
976    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
977    {"name": "ZPASS_DONE", "value": 21},
978    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
979    {"name": "PERFCOUNTER_START", "value": 23},
980    {"name": "PERFCOUNTER_STOP", "value": 24},
981    {"name": "PIPELINESTAT_START", "value": 25},
982    {"name": "PIPELINESTAT_STOP", "value": 26},
983    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
984    {"name": "FLUSH_ES_OUTPUT", "value": 28},
985    {"name": "FLUSH_GS_OUTPUT", "value": 29},
986    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
987    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
988    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
989    {"name": "RESET_VTX_CNT", "value": 33},
990    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
991    {"name": "CS_CONTEXT_DONE", "value": 35},
992    {"name": "VGT_FLUSH", "value": 36},
993    {"name": "TGID_ROLLOVER", "value": 37},
994    {"name": "SQ_NON_EVENT", "value": 38},
995    {"name": "SC_SEND_DB_VPZ", "value": 39},
996    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
997    {"name": "FLUSH_SX_TS", "value": 41},
998    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
999    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
1000    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
1001    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
1002    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
1003    {"name": "CS_DONE", "value": 47},
1004    {"name": "PS_DONE", "value": 48},
1005    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
1006    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
1007    {"name": "THREAD_TRACE_START", "value": 51},
1008    {"name": "THREAD_TRACE_STOP", "value": 52},
1009    {"name": "THREAD_TRACE_MARKER", "value": 53},
1010    {"name": "THREAD_TRACE_FLUSH", "value": 54},
1011    {"name": "THREAD_TRACE_FINISH", "value": 55},
1012    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
1013    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
1014    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
1015    {"name": "CONTEXT_SUSPEND", "value": 59},
1016    {"name": "OFFCHIP_HS_DEALLOC", "value": 60}
1017   ]
1018  },
1019  "VGT_GS_CUT_MODE": {
1020   "entries": [
1021    {"name": "GS_CUT_1024", "value": 0},
1022    {"name": "GS_CUT_512", "value": 1},
1023    {"name": "GS_CUT_256", "value": 2},
1024    {"name": "GS_CUT_128", "value": 3}
1025   ]
1026  },
1027  "VGT_GS_MODE_TYPE": {
1028   "entries": [
1029    {"name": "GS_OFF", "value": 0},
1030    {"name": "GS_SCENARIO_A", "value": 1},
1031    {"name": "GS_SCENARIO_B", "value": 2},
1032    {"name": "GS_SCENARIO_G", "value": 3},
1033    {"name": "GS_SCENARIO_C", "value": 4},
1034    {"name": "SPRITE_EN", "value": 5}
1035   ]
1036  },
1037  "VGT_GS_OUTPRIM_TYPE": {
1038   "entries": [
1039    {"name": "POINTLIST", "value": 0},
1040    {"name": "LINESTRIP", "value": 1},
1041    {"name": "TRISTRIP", "value": 2}
1042   ]
1043  },
1044  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
1045   "entries": [
1046    {"name": "X_8K_DWORDS", "value": 0},
1047    {"name": "X_4K_DWORDS", "value": 1},
1048    {"name": "X_2K_DWORDS", "value": 2},
1049    {"name": "X_1K_DWORDS", "value": 3}
1050   ]
1051  },
1052  "VGT_INDEX_TYPE_MODE": {
1053   "entries": [
1054    {"name": "VGT_INDEX_16", "value": 0},
1055    {"name": "VGT_INDEX_32", "value": 1},
1056    {"name": "VGT_INDEX_8", "value": 2}
1057   ]
1058  },
1059  "VGT_RDREQ_POLICY": {
1060   "entries": [
1061    {"name": "VGT_POLICY_LRU", "value": 0},
1062    {"name": "VGT_POLICY_STREAM", "value": 1}
1063   ]
1064  },
1065  "VGT_STAGES_ES_EN": {
1066   "entries": [
1067    {"name": "ES_STAGE_OFF", "value": 0},
1068    {"name": "ES_STAGE_DS", "value": 1},
1069    {"name": "ES_STAGE_REAL", "value": 2},
1070    {"name": "RESERVED_ES", "value": 3}
1071   ]
1072  },
1073  "VGT_STAGES_GS_EN": {
1074   "entries": [
1075    {"name": "GS_STAGE_OFF", "value": 0},
1076    {"name": "GS_STAGE_ON", "value": 1}
1077   ]
1078  },
1079  "VGT_STAGES_HS_EN": {
1080   "entries": [
1081    {"name": "HS_STAGE_OFF", "value": 0},
1082    {"name": "HS_STAGE_ON", "value": 1}
1083   ]
1084  },
1085  "VGT_STAGES_LS_EN": {
1086   "entries": [
1087    {"name": "LS_STAGE_OFF", "value": 0},
1088    {"name": "LS_STAGE_ON", "value": 1},
1089    {"name": "CS_STAGE_ON", "value": 2},
1090    {"name": "RESERVED_LS", "value": 3}
1091   ]
1092  },
1093  "VGT_STAGES_VS_EN": {
1094   "entries": [
1095    {"name": "VS_STAGE_REAL", "value": 0},
1096    {"name": "VS_STAGE_DS", "value": 1},
1097    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
1098    {"name": "RESERVED_VS", "value": 3}
1099   ]
1100  },
1101  "VGT_TESS_PARTITION": {
1102   "entries": [
1103    {"name": "PART_INTEGER", "value": 0},
1104    {"name": "PART_POW2", "value": 1},
1105    {"name": "PART_FRAC_ODD", "value": 2},
1106    {"name": "PART_FRAC_EVEN", "value": 3}
1107   ]
1108  },
1109  "VGT_TESS_TOPOLOGY": {
1110   "entries": [
1111    {"name": "OUTPUT_POINT", "value": 0},
1112    {"name": "OUTPUT_LINE", "value": 1},
1113    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
1114    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1115   ]
1116  },
1117  "VGT_TESS_TYPE": {
1118   "entries": [
1119    {"name": "TESS_ISOLINE", "value": 0},
1120    {"name": "TESS_TRIANGLE", "value": 1},
1121    {"name": "TESS_QUAD", "value": 2}
1122   ]
1123  },
1124  "ZFormat": {
1125   "entries": [
1126    {"name": "Z_INVALID", "value": 0},
1127    {"name": "Z_16", "value": 1},
1128    {"name": "Z_24", "value": 2},
1129    {"name": "Z_32_FLOAT", "value": 3}
1130   ]
1131  },
1132  "ZLimitSumm": {
1133   "entries": [
1134    {"name": "FORCE_SUMM_OFF", "value": 0},
1135    {"name": "FORCE_SUMM_MINZ", "value": 1},
1136    {"name": "FORCE_SUMM_MAXZ", "value": 2},
1137    {"name": "FORCE_SUMM_BOTH", "value": 3}
1138   ]
1139  },
1140  "ZOrder": {
1141   "entries": [
1142    {"name": "LATE_Z", "value": 0},
1143    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1144    {"name": "RE_Z", "value": 2},
1145    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1146   ]
1147  }
1148 },
1149 "register_mappings": [
1150  {
1151   "chips": ["gfx81"],
1152   "map": {"at": 68, "to": "mm"},
1153   "name": "SQ_WAVE_MODE",
1154   "type_ref": "SQ_WAVE_MODE"
1155  },
1156  {
1157   "chips": ["gfx81"],
1158   "map": {"at": 72, "to": "mm"},
1159   "name": "SQ_WAVE_STATUS",
1160   "type_ref": "SQ_WAVE_STATUS"
1161  },
1162  {
1163   "chips": ["gfx81"],
1164   "map": {"at": 76, "to": "mm"},
1165   "name": "SQ_WAVE_TRAPSTS",
1166   "type_ref": "SQ_WAVE_TRAPSTS"
1167  },
1168  {
1169   "chips": ["gfx81"],
1170   "map": {"at": 80, "to": "mm"},
1171   "name": "SQ_WAVE_HW_ID",
1172   "type_ref": "SQ_WAVE_HW_ID"
1173  },
1174  {
1175   "chips": ["gfx81"],
1176   "map": {"at": 84, "to": "mm"},
1177   "name": "SQ_WAVE_GPR_ALLOC",
1178   "type_ref": "SQ_WAVE_GPR_ALLOC"
1179  },
1180  {
1181   "chips": ["gfx81"],
1182   "map": {"at": 88, "to": "mm"},
1183   "name": "SQ_WAVE_LDS_ALLOC",
1184   "type_ref": "SQ_WAVE_LDS_ALLOC"
1185  },
1186  {
1187   "chips": ["gfx81"],
1188   "map": {"at": 92, "to": "mm"},
1189   "name": "SQ_WAVE_IB_STS",
1190   "type_ref": "SQ_WAVE_IB_STS"
1191  },
1192  {
1193   "chips": ["gfx81"],
1194   "map": {"at": 96, "to": "mm"},
1195   "name": "SQ_WAVE_PC_LO",
1196   "type_ref": "SQ_WAVE_PC_LO"
1197  },
1198  {
1199   "chips": ["gfx81"],
1200   "map": {"at": 100, "to": "mm"},
1201   "name": "SQ_WAVE_PC_HI",
1202   "type_ref": "SQ_WAVE_PC_HI"
1203  },
1204  {
1205   "chips": ["gfx81"],
1206   "map": {"at": 104, "to": "mm"},
1207   "name": "SQ_WAVE_INST_DW0",
1208   "type_ref": "SQ_WAVE_INST_DW0"
1209  },
1210  {
1211   "chips": ["gfx81"],
1212   "map": {"at": 108, "to": "mm"},
1213   "name": "SQ_WAVE_INST_DW1",
1214   "type_ref": "SQ_WAVE_INST_DW1"
1215  },
1216  {
1217   "chips": ["gfx81"],
1218   "map": {"at": 112, "to": "mm"},
1219   "name": "SQ_WAVE_IB_DBG0",
1220   "type_ref": "SQ_WAVE_IB_DBG0"
1221  },
1222  {
1223   "chips": ["gfx81"],
1224   "map": {"at": 116, "to": "mm"},
1225   "name": "SQ_WAVE_IB_DBG1",
1226   "type_ref": "SQ_WAVE_IB_DBG1"
1227  },
1228  {
1229   "chips": ["gfx81"],
1230   "map": {"at": 2480, "to": "mm"},
1231   "name": "SQ_WAVE_TBA_LO",
1232   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
1233  },
1234  {
1235   "chips": ["gfx81"],
1236   "map": {"at": 2484, "to": "mm"},
1237   "name": "SQ_WAVE_TBA_HI",
1238   "type_ref": "SQ_WAVE_TBA_HI"
1239  },
1240  {
1241   "chips": ["gfx81"],
1242   "map": {"at": 2488, "to": "mm"},
1243   "name": "SQ_WAVE_TMA_LO",
1244   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
1245  },
1246  {
1247   "chips": ["gfx81"],
1248   "map": {"at": 2492, "to": "mm"},
1249   "name": "SQ_WAVE_TMA_HI",
1250   "type_ref": "SQ_WAVE_TBA_HI"
1251  },
1252  {
1253   "chips": ["gfx81"],
1254   "map": {"at": 2496, "to": "mm"},
1255   "name": "SQ_WAVE_TTMP0",
1256   "type_ref": "CP_APPEND_DATA"
1257  },
1258  {
1259   "chips": ["gfx81"],
1260   "map": {"at": 2500, "to": "mm"},
1261   "name": "SQ_WAVE_TTMP1",
1262   "type_ref": "CP_APPEND_DATA"
1263  },
1264  {
1265   "chips": ["gfx81"],
1266   "map": {"at": 2504, "to": "mm"},
1267   "name": "SQ_WAVE_TTMP2",
1268   "type_ref": "CP_APPEND_DATA"
1269  },
1270  {
1271   "chips": ["gfx81"],
1272   "map": {"at": 2508, "to": "mm"},
1273   "name": "SQ_WAVE_TTMP3",
1274   "type_ref": "CP_APPEND_DATA"
1275  },
1276  {
1277   "chips": ["gfx81"],
1278   "map": {"at": 2512, "to": "mm"},
1279   "name": "SQ_WAVE_TTMP4",
1280   "type_ref": "CP_APPEND_DATA"
1281  },
1282  {
1283   "chips": ["gfx81"],
1284   "map": {"at": 2516, "to": "mm"},
1285   "name": "SQ_WAVE_TTMP5",
1286   "type_ref": "CP_APPEND_DATA"
1287  },
1288  {
1289   "chips": ["gfx81"],
1290   "map": {"at": 2520, "to": "mm"},
1291   "name": "SQ_WAVE_TTMP6",
1292   "type_ref": "CP_APPEND_DATA"
1293  },
1294  {
1295   "chips": ["gfx81"],
1296   "map": {"at": 2524, "to": "mm"},
1297   "name": "SQ_WAVE_TTMP7",
1298   "type_ref": "CP_APPEND_DATA"
1299  },
1300  {
1301   "chips": ["gfx81"],
1302   "map": {"at": 2528, "to": "mm"},
1303   "name": "SQ_WAVE_TTMP8",
1304   "type_ref": "CP_APPEND_DATA"
1305  },
1306  {
1307   "chips": ["gfx81"],
1308   "map": {"at": 2532, "to": "mm"},
1309   "name": "SQ_WAVE_TTMP9",
1310   "type_ref": "CP_APPEND_DATA"
1311  },
1312  {
1313   "chips": ["gfx81"],
1314   "map": {"at": 2536, "to": "mm"},
1315   "name": "SQ_WAVE_TTMP10",
1316   "type_ref": "CP_APPEND_DATA"
1317  },
1318  {
1319   "chips": ["gfx81"],
1320   "map": {"at": 2540, "to": "mm"},
1321   "name": "SQ_WAVE_TTMP11",
1322   "type_ref": "CP_APPEND_DATA"
1323  },
1324  {
1325   "chips": ["gfx81"],
1326   "map": {"at": 2544, "to": "mm"},
1327   "name": "SQ_WAVE_M0",
1328   "type_ref": "SQ_WAVE_M0"
1329  },
1330  {
1331   "chips": ["gfx81"],
1332   "map": {"at": 2552, "to": "mm"},
1333   "name": "SQ_WAVE_EXEC_LO",
1334   "type_ref": "SQ_WAVE_EXEC_LO"
1335  },
1336  {
1337   "chips": ["gfx81"],
1338   "map": {"at": 2556, "to": "mm"},
1339   "name": "SQ_WAVE_EXEC_HI",
1340   "type_ref": "SQ_WAVE_EXEC_HI"
1341  },
1342  {
1343   "chips": ["gfx81"],
1344   "map": {"at": 32776, "to": "mm"},
1345   "name": "GRBM_STATUS2",
1346   "type_ref": "GRBM_STATUS2"
1347  },
1348  {
1349   "chips": ["gfx81"],
1350   "map": {"at": 32784, "to": "mm"},
1351   "name": "GRBM_STATUS",
1352   "type_ref": "GRBM_STATUS"
1353  },
1354  {
1355   "chips": ["gfx81"],
1356   "map": {"at": 32788, "to": "mm"},
1357   "name": "GRBM_STATUS_SE0",
1358   "type_ref": "GRBM_STATUS_SE0"
1359  },
1360  {
1361   "chips": ["gfx81"],
1362   "map": {"at": 32792, "to": "mm"},
1363   "name": "GRBM_STATUS_SE1",
1364   "type_ref": "GRBM_STATUS_SE0"
1365  },
1366  {
1367   "chips": ["gfx81"],
1368   "map": {"at": 32824, "to": "mm"},
1369   "name": "GRBM_STATUS_SE2",
1370   "type_ref": "GRBM_STATUS_SE0"
1371  },
1372  {
1373   "chips": ["gfx81"],
1374   "map": {"at": 32828, "to": "mm"},
1375   "name": "GRBM_STATUS_SE3",
1376   "type_ref": "GRBM_STATUS_SE0"
1377  },
1378  {
1379   "chips": ["gfx81"],
1380   "map": {"at": 33296, "to": "mm"},
1381   "name": "CP_CPC_STATUS",
1382   "type_ref": "CP_CPC_STATUS"
1383  },
1384  {
1385   "chips": ["gfx81"],
1386   "map": {"at": 33300, "to": "mm"},
1387   "name": "CP_CPC_BUSY_STAT",
1388   "type_ref": "CP_CPC_BUSY_STAT"
1389  },
1390  {
1391   "chips": ["gfx81"],
1392   "map": {"at": 33304, "to": "mm"},
1393   "name": "CP_CPC_STALLED_STAT1",
1394   "type_ref": "CP_CPC_STALLED_STAT1"
1395  },
1396  {
1397   "chips": ["gfx81"],
1398   "map": {"at": 33308, "to": "mm"},
1399   "name": "CP_CPF_STATUS",
1400   "type_ref": "CP_CPF_STATUS"
1401  },
1402  {
1403   "chips": ["gfx81"],
1404   "map": {"at": 33312, "to": "mm"},
1405   "name": "CP_CPF_BUSY_STAT",
1406   "type_ref": "CP_CPF_BUSY_STAT"
1407  },
1408  {
1409   "chips": ["gfx81"],
1410   "map": {"at": 33316, "to": "mm"},
1411   "name": "CP_CPF_STALLED_STAT1",
1412   "type_ref": "CP_CPF_STALLED_STAT1"
1413  },
1414  {
1415   "chips": ["gfx81"],
1416   "map": {"at": 33324, "to": "mm"},
1417   "name": "CP_CPC_GRBM_FREE_COUNT",
1418   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1419  },
1420  {
1421   "chips": ["gfx81"],
1422   "map": {"at": 33344, "to": "mm"},
1423   "name": "CP_CPC_SCRATCH_INDEX",
1424   "type_ref": "CP_CPC_SCRATCH_INDEX"
1425  },
1426  {
1427   "chips": ["gfx81"],
1428   "map": {"at": 33348, "to": "mm"},
1429   "name": "CP_CPC_SCRATCH_DATA",
1430   "type_ref": "CP_CPC_SCRATCH_DATA"
1431  },
1432  {
1433   "chips": ["gfx81"],
1434   "map": {"at": 33436, "to": "mm"},
1435   "name": "CP_CPC_HALT_HYST_COUNT",
1436   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1437  },
1438  {
1439   "chips": ["gfx81"],
1440   "map": {"at": 36416, "to": "mm"},
1441   "name": "SQ_THREAD_TRACE_CNTR",
1442   "type_ref": "SQ_THREAD_TRACE_CNTR"
1443  },
1444  {
1445   "chips": ["gfx81"],
1446   "map": {"at": 36608, "to": "mm"},
1447   "name": "SQ_BUF_RSRC_WORD0",
1448   "type_ref": "SQ_BUF_RSRC_WORD0"
1449  },
1450  {
1451   "chips": ["gfx81"],
1452   "map": {"at": 36612, "to": "mm"},
1453   "name": "SQ_BUF_RSRC_WORD1",
1454   "type_ref": "SQ_BUF_RSRC_WORD1"
1455  },
1456  {
1457   "chips": ["gfx81"],
1458   "map": {"at": 36616, "to": "mm"},
1459   "name": "SQ_BUF_RSRC_WORD2",
1460   "type_ref": "SQ_BUF_RSRC_WORD2"
1461  },
1462  {
1463   "chips": ["gfx81"],
1464   "map": {"at": 36620, "to": "mm"},
1465   "name": "SQ_BUF_RSRC_WORD3",
1466   "type_ref": "SQ_BUF_RSRC_WORD3"
1467  },
1468  {
1469   "chips": ["gfx81"],
1470   "map": {"at": 36624, "to": "mm"},
1471   "name": "SQ_IMG_RSRC_WORD0",
1472   "type_ref": "SQ_BUF_RSRC_WORD0"
1473  },
1474  {
1475   "chips": ["gfx81"],
1476   "map": {"at": 36628, "to": "mm"},
1477   "name": "SQ_IMG_RSRC_WORD1",
1478   "type_ref": "SQ_IMG_RSRC_WORD1"
1479  },
1480  {
1481   "chips": ["gfx81"],
1482   "map": {"at": 36632, "to": "mm"},
1483   "name": "SQ_IMG_RSRC_WORD2",
1484   "type_ref": "SQ_IMG_RSRC_WORD2"
1485  },
1486  {
1487   "chips": ["gfx81"],
1488   "map": {"at": 36636, "to": "mm"},
1489   "name": "SQ_IMG_RSRC_WORD3",
1490   "type_ref": "SQ_IMG_RSRC_WORD3"
1491  },
1492  {
1493   "chips": ["gfx81"],
1494   "map": {"at": 36640, "to": "mm"},
1495   "name": "SQ_IMG_RSRC_WORD4",
1496   "type_ref": "SQ_IMG_RSRC_WORD4"
1497  },
1498  {
1499   "chips": ["gfx81"],
1500   "map": {"at": 36644, "to": "mm"},
1501   "name": "SQ_IMG_RSRC_WORD5",
1502   "type_ref": "SQ_IMG_RSRC_WORD5"
1503  },
1504  {
1505   "chips": ["gfx81"],
1506   "map": {"at": 36648, "to": "mm"},
1507   "name": "SQ_IMG_RSRC_WORD6",
1508   "type_ref": "SQ_IMG_RSRC_WORD6"
1509  },
1510  {
1511   "chips": ["gfx81"],
1512   "map": {"at": 36652, "to": "mm"},
1513   "name": "SQ_IMG_RSRC_WORD7",
1514   "type_ref": "SQ_IMG_RSRC_WORD7"
1515  },
1516  {
1517   "chips": ["gfx81"],
1518   "map": {"at": 36656, "to": "mm"},
1519   "name": "SQ_IMG_SAMP_WORD0",
1520   "type_ref": "SQ_IMG_SAMP_WORD0"
1521  },
1522  {
1523   "chips": ["gfx81"],
1524   "map": {"at": 36660, "to": "mm"},
1525   "name": "SQ_IMG_SAMP_WORD1",
1526   "type_ref": "SQ_IMG_SAMP_WORD1"
1527  },
1528  {
1529   "chips": ["gfx81"],
1530   "map": {"at": 36664, "to": "mm"},
1531   "name": "SQ_IMG_SAMP_WORD2",
1532   "type_ref": "SQ_IMG_SAMP_WORD2"
1533  },
1534  {
1535   "chips": ["gfx81"],
1536   "map": {"at": 36668, "to": "mm"},
1537   "name": "SQ_IMG_SAMP_WORD3",
1538   "type_ref": "SQ_IMG_SAMP_WORD3"
1539  },
1540  {
1541   "chips": ["gfx81"],
1542   "map": {"at": 37120, "to": "mm"},
1543   "name": "SPI_CONFIG_CNTL",
1544   "type_ref": "SPI_CONFIG_CNTL"
1545  },
1546  {
1547   "chips": ["gfx81"],
1548   "map": {"at": 39160, "to": "mm"},
1549   "name": "GB_ADDR_CONFIG",
1550   "type_ref": "GB_ADDR_CONFIG"
1551  },
1552  {
1553   "chips": ["gfx81"],
1554   "map": {"at": 39184, "to": "mm"},
1555   "name": "GB_TILE_MODE0",
1556   "type_ref": "GB_TILE_MODE0"
1557  },
1558  {
1559   "chips": ["gfx81"],
1560   "map": {"at": 39188, "to": "mm"},
1561   "name": "GB_TILE_MODE1",
1562   "type_ref": "GB_TILE_MODE0"
1563  },
1564  {
1565   "chips": ["gfx81"],
1566   "map": {"at": 39192, "to": "mm"},
1567   "name": "GB_TILE_MODE2",
1568   "type_ref": "GB_TILE_MODE0"
1569  },
1570  {
1571   "chips": ["gfx81"],
1572   "map": {"at": 39196, "to": "mm"},
1573   "name": "GB_TILE_MODE3",
1574   "type_ref": "GB_TILE_MODE0"
1575  },
1576  {
1577   "chips": ["gfx81"],
1578   "map": {"at": 39200, "to": "mm"},
1579   "name": "GB_TILE_MODE4",
1580   "type_ref": "GB_TILE_MODE0"
1581  },
1582  {
1583   "chips": ["gfx81"],
1584   "map": {"at": 39204, "to": "mm"},
1585   "name": "GB_TILE_MODE5",
1586   "type_ref": "GB_TILE_MODE0"
1587  },
1588  {
1589   "chips": ["gfx81"],
1590   "map": {"at": 39208, "to": "mm"},
1591   "name": "GB_TILE_MODE6",
1592   "type_ref": "GB_TILE_MODE0"
1593  },
1594  {
1595   "chips": ["gfx81"],
1596   "map": {"at": 39212, "to": "mm"},
1597   "name": "GB_TILE_MODE7",
1598   "type_ref": "GB_TILE_MODE0"
1599  },
1600  {
1601   "chips": ["gfx81"],
1602   "map": {"at": 39216, "to": "mm"},
1603   "name": "GB_TILE_MODE8",
1604   "type_ref": "GB_TILE_MODE0"
1605  },
1606  {
1607   "chips": ["gfx81"],
1608   "map": {"at": 39220, "to": "mm"},
1609   "name": "GB_TILE_MODE9",
1610   "type_ref": "GB_TILE_MODE0"
1611  },
1612  {
1613   "chips": ["gfx81"],
1614   "map": {"at": 39224, "to": "mm"},
1615   "name": "GB_TILE_MODE10",
1616   "type_ref": "GB_TILE_MODE0"
1617  },
1618  {
1619   "chips": ["gfx81"],
1620   "map": {"at": 39228, "to": "mm"},
1621   "name": "GB_TILE_MODE11",
1622   "type_ref": "GB_TILE_MODE0"
1623  },
1624  {
1625   "chips": ["gfx81"],
1626   "map": {"at": 39232, "to": "mm"},
1627   "name": "GB_TILE_MODE12",
1628   "type_ref": "GB_TILE_MODE0"
1629  },
1630  {
1631   "chips": ["gfx81"],
1632   "map": {"at": 39236, "to": "mm"},
1633   "name": "GB_TILE_MODE13",
1634   "type_ref": "GB_TILE_MODE0"
1635  },
1636  {
1637   "chips": ["gfx81"],
1638   "map": {"at": 39240, "to": "mm"},
1639   "name": "GB_TILE_MODE14",
1640   "type_ref": "GB_TILE_MODE0"
1641  },
1642  {
1643   "chips": ["gfx81"],
1644   "map": {"at": 39244, "to": "mm"},
1645   "name": "GB_TILE_MODE15",
1646   "type_ref": "GB_TILE_MODE0"
1647  },
1648  {
1649   "chips": ["gfx81"],
1650   "map": {"at": 39248, "to": "mm"},
1651   "name": "GB_TILE_MODE16",
1652   "type_ref": "GB_TILE_MODE0"
1653  },
1654  {
1655   "chips": ["gfx81"],
1656   "map": {"at": 39252, "to": "mm"},
1657   "name": "GB_TILE_MODE17",
1658   "type_ref": "GB_TILE_MODE0"
1659  },
1660  {
1661   "chips": ["gfx81"],
1662   "map": {"at": 39256, "to": "mm"},
1663   "name": "GB_TILE_MODE18",
1664   "type_ref": "GB_TILE_MODE0"
1665  },
1666  {
1667   "chips": ["gfx81"],
1668   "map": {"at": 39260, "to": "mm"},
1669   "name": "GB_TILE_MODE19",
1670   "type_ref": "GB_TILE_MODE0"
1671  },
1672  {
1673   "chips": ["gfx81"],
1674   "map": {"at": 39264, "to": "mm"},
1675   "name": "GB_TILE_MODE20",
1676   "type_ref": "GB_TILE_MODE0"
1677  },
1678  {
1679   "chips": ["gfx81"],
1680   "map": {"at": 39268, "to": "mm"},
1681   "name": "GB_TILE_MODE21",
1682   "type_ref": "GB_TILE_MODE0"
1683  },
1684  {
1685   "chips": ["gfx81"],
1686   "map": {"at": 39272, "to": "mm"},
1687   "name": "GB_TILE_MODE22",
1688   "type_ref": "GB_TILE_MODE0"
1689  },
1690  {
1691   "chips": ["gfx81"],
1692   "map": {"at": 39276, "to": "mm"},
1693   "name": "GB_TILE_MODE23",
1694   "type_ref": "GB_TILE_MODE0"
1695  },
1696  {
1697   "chips": ["gfx81"],
1698   "map": {"at": 39280, "to": "mm"},
1699   "name": "GB_TILE_MODE24",
1700   "type_ref": "GB_TILE_MODE0"
1701  },
1702  {
1703   "chips": ["gfx81"],
1704   "map": {"at": 39284, "to": "mm"},
1705   "name": "GB_TILE_MODE25",
1706   "type_ref": "GB_TILE_MODE0"
1707  },
1708  {
1709   "chips": ["gfx81"],
1710   "map": {"at": 39288, "to": "mm"},
1711   "name": "GB_TILE_MODE26",
1712   "type_ref": "GB_TILE_MODE0"
1713  },
1714  {
1715   "chips": ["gfx81"],
1716   "map": {"at": 39292, "to": "mm"},
1717   "name": "GB_TILE_MODE27",
1718   "type_ref": "GB_TILE_MODE0"
1719  },
1720  {
1721   "chips": ["gfx81"],
1722   "map": {"at": 39296, "to": "mm"},
1723   "name": "GB_TILE_MODE28",
1724   "type_ref": "GB_TILE_MODE0"
1725  },
1726  {
1727   "chips": ["gfx81"],
1728   "map": {"at": 39300, "to": "mm"},
1729   "name": "GB_TILE_MODE29",
1730   "type_ref": "GB_TILE_MODE0"
1731  },
1732  {
1733   "chips": ["gfx81"],
1734   "map": {"at": 39304, "to": "mm"},
1735   "name": "GB_TILE_MODE30",
1736   "type_ref": "GB_TILE_MODE0"
1737  },
1738  {
1739   "chips": ["gfx81"],
1740   "map": {"at": 39308, "to": "mm"},
1741   "name": "GB_TILE_MODE31",
1742   "type_ref": "GB_TILE_MODE0"
1743  },
1744  {
1745   "chips": ["gfx81"],
1746   "map": {"at": 39312, "to": "mm"},
1747   "name": "GB_MACROTILE_MODE0",
1748   "type_ref": "GB_MACROTILE_MODE0"
1749  },
1750  {
1751   "chips": ["gfx81"],
1752   "map": {"at": 39316, "to": "mm"},
1753   "name": "GB_MACROTILE_MODE1",
1754   "type_ref": "GB_MACROTILE_MODE0"
1755  },
1756  {
1757   "chips": ["gfx81"],
1758   "map": {"at": 39320, "to": "mm"},
1759   "name": "GB_MACROTILE_MODE2",
1760   "type_ref": "GB_MACROTILE_MODE0"
1761  },
1762  {
1763   "chips": ["gfx81"],
1764   "map": {"at": 39324, "to": "mm"},
1765   "name": "GB_MACROTILE_MODE3",
1766   "type_ref": "GB_MACROTILE_MODE0"
1767  },
1768  {
1769   "chips": ["gfx81"],
1770   "map": {"at": 39328, "to": "mm"},
1771   "name": "GB_MACROTILE_MODE4",
1772   "type_ref": "GB_MACROTILE_MODE0"
1773  },
1774  {
1775   "chips": ["gfx81"],
1776   "map": {"at": 39332, "to": "mm"},
1777   "name": "GB_MACROTILE_MODE5",
1778   "type_ref": "GB_MACROTILE_MODE0"
1779  },
1780  {
1781   "chips": ["gfx81"],
1782   "map": {"at": 39336, "to": "mm"},
1783   "name": "GB_MACROTILE_MODE6",
1784   "type_ref": "GB_MACROTILE_MODE0"
1785  },
1786  {
1787   "chips": ["gfx81"],
1788   "map": {"at": 39340, "to": "mm"},
1789   "name": "GB_MACROTILE_MODE7",
1790   "type_ref": "GB_MACROTILE_MODE0"
1791  },
1792  {
1793   "chips": ["gfx81"],
1794   "map": {"at": 39344, "to": "mm"},
1795   "name": "GB_MACROTILE_MODE8",
1796   "type_ref": "GB_MACROTILE_MODE0"
1797  },
1798  {
1799   "chips": ["gfx81"],
1800   "map": {"at": 39348, "to": "mm"},
1801   "name": "GB_MACROTILE_MODE9",
1802   "type_ref": "GB_MACROTILE_MODE0"
1803  },
1804  {
1805   "chips": ["gfx81"],
1806   "map": {"at": 39352, "to": "mm"},
1807   "name": "GB_MACROTILE_MODE10",
1808   "type_ref": "GB_MACROTILE_MODE0"
1809  },
1810  {
1811   "chips": ["gfx81"],
1812   "map": {"at": 39356, "to": "mm"},
1813   "name": "GB_MACROTILE_MODE11",
1814   "type_ref": "GB_MACROTILE_MODE0"
1815  },
1816  {
1817   "chips": ["gfx81"],
1818   "map": {"at": 39360, "to": "mm"},
1819   "name": "GB_MACROTILE_MODE12",
1820   "type_ref": "GB_MACROTILE_MODE0"
1821  },
1822  {
1823   "chips": ["gfx81"],
1824   "map": {"at": 39364, "to": "mm"},
1825   "name": "GB_MACROTILE_MODE13",
1826   "type_ref": "GB_MACROTILE_MODE0"
1827  },
1828  {
1829   "chips": ["gfx81"],
1830   "map": {"at": 39368, "to": "mm"},
1831   "name": "GB_MACROTILE_MODE14",
1832   "type_ref": "GB_MACROTILE_MODE0"
1833  },
1834  {
1835   "chips": ["gfx81"],
1836   "map": {"at": 39372, "to": "mm"},
1837   "name": "GB_MACROTILE_MODE15",
1838   "type_ref": "GB_MACROTILE_MODE0"
1839  },
1840  {
1841   "chips": ["gfx81"],
1842   "map": {"at": 45056, "to": "mm"},
1843   "name": "SPI_SHADER_TBA_LO_PS",
1844   "type_ref": "SPI_SHADER_TBA_LO_PS"
1845  },
1846  {
1847   "chips": ["gfx81"],
1848   "map": {"at": 45060, "to": "mm"},
1849   "name": "SPI_SHADER_TBA_HI_PS",
1850   "type_ref": "SPI_SHADER_TBA_HI_PS"
1851  },
1852  {
1853   "chips": ["gfx81"],
1854   "map": {"at": 45064, "to": "mm"},
1855   "name": "SPI_SHADER_TMA_LO_PS",
1856   "type_ref": "SPI_SHADER_TBA_LO_PS"
1857  },
1858  {
1859   "chips": ["gfx81"],
1860   "map": {"at": 45068, "to": "mm"},
1861   "name": "SPI_SHADER_TMA_HI_PS",
1862   "type_ref": "SPI_SHADER_TBA_HI_PS"
1863  },
1864  {
1865   "chips": ["gfx81"],
1866   "map": {"at": 45084, "to": "mm"},
1867   "name": "SPI_SHADER_PGM_RSRC3_PS",
1868   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1869  },
1870  {
1871   "chips": ["gfx81"],
1872   "map": {"at": 45088, "to": "mm"},
1873   "name": "SPI_SHADER_PGM_LO_PS",
1874   "type_ref": "SPI_SHADER_TBA_LO_PS"
1875  },
1876  {
1877   "chips": ["gfx81"],
1878   "map": {"at": 45092, "to": "mm"},
1879   "name": "SPI_SHADER_PGM_HI_PS",
1880   "type_ref": "SPI_SHADER_TBA_HI_PS"
1881  },
1882  {
1883   "chips": ["gfx81"],
1884   "map": {"at": 45096, "to": "mm"},
1885   "name": "SPI_SHADER_PGM_RSRC1_PS",
1886   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1887  },
1888  {
1889   "chips": ["gfx81"],
1890   "map": {"at": 45100, "to": "mm"},
1891   "name": "SPI_SHADER_PGM_RSRC2_PS",
1892   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1893  },
1894  {
1895   "chips": ["gfx81"],
1896   "map": {"at": 45104, "to": "mm"},
1897   "name": "SPI_SHADER_USER_DATA_PS_0",
1898   "type_ref": "CP_APPEND_DATA"
1899  },
1900  {
1901   "chips": ["gfx81"],
1902   "map": {"at": 45108, "to": "mm"},
1903   "name": "SPI_SHADER_USER_DATA_PS_1",
1904   "type_ref": "CP_APPEND_DATA"
1905  },
1906  {
1907   "chips": ["gfx81"],
1908   "map": {"at": 45112, "to": "mm"},
1909   "name": "SPI_SHADER_USER_DATA_PS_2",
1910   "type_ref": "CP_APPEND_DATA"
1911  },
1912  {
1913   "chips": ["gfx81"],
1914   "map": {"at": 45116, "to": "mm"},
1915   "name": "SPI_SHADER_USER_DATA_PS_3",
1916   "type_ref": "CP_APPEND_DATA"
1917  },
1918  {
1919   "chips": ["gfx81"],
1920   "map": {"at": 45120, "to": "mm"},
1921   "name": "SPI_SHADER_USER_DATA_PS_4",
1922   "type_ref": "CP_APPEND_DATA"
1923  },
1924  {
1925   "chips": ["gfx81"],
1926   "map": {"at": 45124, "to": "mm"},
1927   "name": "SPI_SHADER_USER_DATA_PS_5",
1928   "type_ref": "CP_APPEND_DATA"
1929  },
1930  {
1931   "chips": ["gfx81"],
1932   "map": {"at": 45128, "to": "mm"},
1933   "name": "SPI_SHADER_USER_DATA_PS_6",
1934   "type_ref": "CP_APPEND_DATA"
1935  },
1936  {
1937   "chips": ["gfx81"],
1938   "map": {"at": 45132, "to": "mm"},
1939   "name": "SPI_SHADER_USER_DATA_PS_7",
1940   "type_ref": "CP_APPEND_DATA"
1941  },
1942  {
1943   "chips": ["gfx81"],
1944   "map": {"at": 45136, "to": "mm"},
1945   "name": "SPI_SHADER_USER_DATA_PS_8",
1946   "type_ref": "CP_APPEND_DATA"
1947  },
1948  {
1949   "chips": ["gfx81"],
1950   "map": {"at": 45140, "to": "mm"},
1951   "name": "SPI_SHADER_USER_DATA_PS_9",
1952   "type_ref": "CP_APPEND_DATA"
1953  },
1954  {
1955   "chips": ["gfx81"],
1956   "map": {"at": 45144, "to": "mm"},
1957   "name": "SPI_SHADER_USER_DATA_PS_10",
1958   "type_ref": "CP_APPEND_DATA"
1959  },
1960  {
1961   "chips": ["gfx81"],
1962   "map": {"at": 45148, "to": "mm"},
1963   "name": "SPI_SHADER_USER_DATA_PS_11",
1964   "type_ref": "CP_APPEND_DATA"
1965  },
1966  {
1967   "chips": ["gfx81"],
1968   "map": {"at": 45152, "to": "mm"},
1969   "name": "SPI_SHADER_USER_DATA_PS_12",
1970   "type_ref": "CP_APPEND_DATA"
1971  },
1972  {
1973   "chips": ["gfx81"],
1974   "map": {"at": 45156, "to": "mm"},
1975   "name": "SPI_SHADER_USER_DATA_PS_13",
1976   "type_ref": "CP_APPEND_DATA"
1977  },
1978  {
1979   "chips": ["gfx81"],
1980   "map": {"at": 45160, "to": "mm"},
1981   "name": "SPI_SHADER_USER_DATA_PS_14",
1982   "type_ref": "CP_APPEND_DATA"
1983  },
1984  {
1985   "chips": ["gfx81"],
1986   "map": {"at": 45164, "to": "mm"},
1987   "name": "SPI_SHADER_USER_DATA_PS_15",
1988   "type_ref": "CP_APPEND_DATA"
1989  },
1990  {
1991   "chips": ["gfx81"],
1992   "map": {"at": 45312, "to": "mm"},
1993   "name": "SPI_SHADER_TBA_LO_VS",
1994   "type_ref": "SPI_SHADER_TBA_LO_PS"
1995  },
1996  {
1997   "chips": ["gfx81"],
1998   "map": {"at": 45316, "to": "mm"},
1999   "name": "SPI_SHADER_TBA_HI_VS",
2000   "type_ref": "SPI_SHADER_TBA_HI_PS"
2001  },
2002  {
2003   "chips": ["gfx81"],
2004   "map": {"at": 45320, "to": "mm"},
2005   "name": "SPI_SHADER_TMA_LO_VS",
2006   "type_ref": "SPI_SHADER_TBA_LO_PS"
2007  },
2008  {
2009   "chips": ["gfx81"],
2010   "map": {"at": 45324, "to": "mm"},
2011   "name": "SPI_SHADER_TMA_HI_VS",
2012   "type_ref": "SPI_SHADER_TBA_HI_PS"
2013  },
2014  {
2015   "chips": ["gfx81"],
2016   "map": {"at": 45336, "to": "mm"},
2017   "name": "SPI_SHADER_PGM_RSRC3_VS",
2018   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
2019  },
2020  {
2021   "chips": ["gfx81"],
2022   "map": {"at": 45340, "to": "mm"},
2023   "name": "SPI_SHADER_LATE_ALLOC_VS",
2024   "type_ref": "SPI_SHADER_LATE_ALLOC_VS"
2025  },
2026  {
2027   "chips": ["gfx81"],
2028   "map": {"at": 45344, "to": "mm"},
2029   "name": "SPI_SHADER_PGM_LO_VS",
2030   "type_ref": "SPI_SHADER_TBA_LO_PS"
2031  },
2032  {
2033   "chips": ["gfx81"],
2034   "map": {"at": 45348, "to": "mm"},
2035   "name": "SPI_SHADER_PGM_HI_VS",
2036   "type_ref": "SPI_SHADER_TBA_HI_PS"
2037  },
2038  {
2039   "chips": ["gfx81"],
2040   "map": {"at": 45352, "to": "mm"},
2041   "name": "SPI_SHADER_PGM_RSRC1_VS",
2042   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2043  },
2044  {
2045   "chips": ["gfx81"],
2046   "map": {"at": 45356, "to": "mm"},
2047   "name": "SPI_SHADER_PGM_RSRC2_VS",
2048   "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
2049  },
2050  {
2051   "chips": ["gfx81"],
2052   "map": {"at": 45360, "to": "mm"},
2053   "name": "SPI_SHADER_USER_DATA_VS_0",
2054   "type_ref": "CP_APPEND_DATA"
2055  },
2056  {
2057   "chips": ["gfx81"],
2058   "map": {"at": 45364, "to": "mm"},
2059   "name": "SPI_SHADER_USER_DATA_VS_1",
2060   "type_ref": "CP_APPEND_DATA"
2061  },
2062  {
2063   "chips": ["gfx81"],
2064   "map": {"at": 45368, "to": "mm"},
2065   "name": "SPI_SHADER_USER_DATA_VS_2",
2066   "type_ref": "CP_APPEND_DATA"
2067  },
2068  {
2069   "chips": ["gfx81"],
2070   "map": {"at": 45372, "to": "mm"},
2071   "name": "SPI_SHADER_USER_DATA_VS_3",
2072   "type_ref": "CP_APPEND_DATA"
2073  },
2074  {
2075   "chips": ["gfx81"],
2076   "map": {"at": 45376, "to": "mm"},
2077   "name": "SPI_SHADER_USER_DATA_VS_4",
2078   "type_ref": "CP_APPEND_DATA"
2079  },
2080  {
2081   "chips": ["gfx81"],
2082   "map": {"at": 45380, "to": "mm"},
2083   "name": "SPI_SHADER_USER_DATA_VS_5",
2084   "type_ref": "CP_APPEND_DATA"
2085  },
2086  {
2087   "chips": ["gfx81"],
2088   "map": {"at": 45384, "to": "mm"},
2089   "name": "SPI_SHADER_USER_DATA_VS_6",
2090   "type_ref": "CP_APPEND_DATA"
2091  },
2092  {
2093   "chips": ["gfx81"],
2094   "map": {"at": 45388, "to": "mm"},
2095   "name": "SPI_SHADER_USER_DATA_VS_7",
2096   "type_ref": "CP_APPEND_DATA"
2097  },
2098  {
2099   "chips": ["gfx81"],
2100   "map": {"at": 45392, "to": "mm"},
2101   "name": "SPI_SHADER_USER_DATA_VS_8",
2102   "type_ref": "CP_APPEND_DATA"
2103  },
2104  {
2105   "chips": ["gfx81"],
2106   "map": {"at": 45396, "to": "mm"},
2107   "name": "SPI_SHADER_USER_DATA_VS_9",
2108   "type_ref": "CP_APPEND_DATA"
2109  },
2110  {
2111   "chips": ["gfx81"],
2112   "map": {"at": 45400, "to": "mm"},
2113   "name": "SPI_SHADER_USER_DATA_VS_10",
2114   "type_ref": "CP_APPEND_DATA"
2115  },
2116  {
2117   "chips": ["gfx81"],
2118   "map": {"at": 45404, "to": "mm"},
2119   "name": "SPI_SHADER_USER_DATA_VS_11",
2120   "type_ref": "CP_APPEND_DATA"
2121  },
2122  {
2123   "chips": ["gfx81"],
2124   "map": {"at": 45408, "to": "mm"},
2125   "name": "SPI_SHADER_USER_DATA_VS_12",
2126   "type_ref": "CP_APPEND_DATA"
2127  },
2128  {
2129   "chips": ["gfx81"],
2130   "map": {"at": 45412, "to": "mm"},
2131   "name": "SPI_SHADER_USER_DATA_VS_13",
2132   "type_ref": "CP_APPEND_DATA"
2133  },
2134  {
2135   "chips": ["gfx81"],
2136   "map": {"at": 45416, "to": "mm"},
2137   "name": "SPI_SHADER_USER_DATA_VS_14",
2138   "type_ref": "CP_APPEND_DATA"
2139  },
2140  {
2141   "chips": ["gfx81"],
2142   "map": {"at": 45420, "to": "mm"},
2143   "name": "SPI_SHADER_USER_DATA_VS_15",
2144   "type_ref": "CP_APPEND_DATA"
2145  },
2146  {
2147   "chips": ["gfx81"],
2148   "map": {"at": 45552, "to": "mm"},
2149   "name": "SPI_SHADER_PGM_RSRC2_ES_VS",
2150   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2151  },
2152  {
2153   "chips": ["gfx81"],
2154   "map": {"at": 45556, "to": "mm"},
2155   "name": "SPI_SHADER_PGM_RSRC2_LS_VS",
2156   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2157  },
2158  {
2159   "chips": ["gfx81"],
2160   "map": {"at": 45568, "to": "mm"},
2161   "name": "SPI_SHADER_TBA_LO_GS",
2162   "type_ref": "SPI_SHADER_TBA_LO_PS"
2163  },
2164  {
2165   "chips": ["gfx81"],
2166   "map": {"at": 45572, "to": "mm"},
2167   "name": "SPI_SHADER_TBA_HI_GS",
2168   "type_ref": "SPI_SHADER_TBA_HI_PS"
2169  },
2170  {
2171   "chips": ["gfx81"],
2172   "map": {"at": 45576, "to": "mm"},
2173   "name": "SPI_SHADER_TMA_LO_GS",
2174   "type_ref": "SPI_SHADER_TBA_LO_PS"
2175  },
2176  {
2177   "chips": ["gfx81"],
2178   "map": {"at": 45580, "to": "mm"},
2179   "name": "SPI_SHADER_TMA_HI_GS",
2180   "type_ref": "SPI_SHADER_TBA_HI_PS"
2181  },
2182  {
2183   "chips": ["gfx81"],
2184   "map": {"at": 45596, "to": "mm"},
2185   "name": "SPI_SHADER_PGM_RSRC3_GS",
2186   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2187  },
2188  {
2189   "chips": ["gfx81"],
2190   "map": {"at": 45600, "to": "mm"},
2191   "name": "SPI_SHADER_PGM_LO_GS",
2192   "type_ref": "SPI_SHADER_TBA_LO_PS"
2193  },
2194  {
2195   "chips": ["gfx81"],
2196   "map": {"at": 45604, "to": "mm"},
2197   "name": "SPI_SHADER_PGM_HI_GS",
2198   "type_ref": "SPI_SHADER_TBA_HI_PS"
2199  },
2200  {
2201   "chips": ["gfx81"],
2202   "map": {"at": 45608, "to": "mm"},
2203   "name": "SPI_SHADER_PGM_RSRC1_GS",
2204   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
2205  },
2206  {
2207   "chips": ["gfx81"],
2208   "map": {"at": 45612, "to": "mm"},
2209   "name": "SPI_SHADER_PGM_RSRC2_GS",
2210   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
2211  },
2212  {
2213   "chips": ["gfx81"],
2214   "map": {"at": 45616, "to": "mm"},
2215   "name": "SPI_SHADER_USER_DATA_GS_0",
2216   "type_ref": "CP_APPEND_DATA"
2217  },
2218  {
2219   "chips": ["gfx81"],
2220   "map": {"at": 45620, "to": "mm"},
2221   "name": "SPI_SHADER_USER_DATA_GS_1",
2222   "type_ref": "CP_APPEND_DATA"
2223  },
2224  {
2225   "chips": ["gfx81"],
2226   "map": {"at": 45624, "to": "mm"},
2227   "name": "SPI_SHADER_USER_DATA_GS_2",
2228   "type_ref": "CP_APPEND_DATA"
2229  },
2230  {
2231   "chips": ["gfx81"],
2232   "map": {"at": 45628, "to": "mm"},
2233   "name": "SPI_SHADER_USER_DATA_GS_3",
2234   "type_ref": "CP_APPEND_DATA"
2235  },
2236  {
2237   "chips": ["gfx81"],
2238   "map": {"at": 45632, "to": "mm"},
2239   "name": "SPI_SHADER_USER_DATA_GS_4",
2240   "type_ref": "CP_APPEND_DATA"
2241  },
2242  {
2243   "chips": ["gfx81"],
2244   "map": {"at": 45636, "to": "mm"},
2245   "name": "SPI_SHADER_USER_DATA_GS_5",
2246   "type_ref": "CP_APPEND_DATA"
2247  },
2248  {
2249   "chips": ["gfx81"],
2250   "map": {"at": 45640, "to": "mm"},
2251   "name": "SPI_SHADER_USER_DATA_GS_6",
2252   "type_ref": "CP_APPEND_DATA"
2253  },
2254  {
2255   "chips": ["gfx81"],
2256   "map": {"at": 45644, "to": "mm"},
2257   "name": "SPI_SHADER_USER_DATA_GS_7",
2258   "type_ref": "CP_APPEND_DATA"
2259  },
2260  {
2261   "chips": ["gfx81"],
2262   "map": {"at": 45648, "to": "mm"},
2263   "name": "SPI_SHADER_USER_DATA_GS_8",
2264   "type_ref": "CP_APPEND_DATA"
2265  },
2266  {
2267   "chips": ["gfx81"],
2268   "map": {"at": 45652, "to": "mm"},
2269   "name": "SPI_SHADER_USER_DATA_GS_9",
2270   "type_ref": "CP_APPEND_DATA"
2271  },
2272  {
2273   "chips": ["gfx81"],
2274   "map": {"at": 45656, "to": "mm"},
2275   "name": "SPI_SHADER_USER_DATA_GS_10",
2276   "type_ref": "CP_APPEND_DATA"
2277  },
2278  {
2279   "chips": ["gfx81"],
2280   "map": {"at": 45660, "to": "mm"},
2281   "name": "SPI_SHADER_USER_DATA_GS_11",
2282   "type_ref": "CP_APPEND_DATA"
2283  },
2284  {
2285   "chips": ["gfx81"],
2286   "map": {"at": 45664, "to": "mm"},
2287   "name": "SPI_SHADER_USER_DATA_GS_12",
2288   "type_ref": "CP_APPEND_DATA"
2289  },
2290  {
2291   "chips": ["gfx81"],
2292   "map": {"at": 45668, "to": "mm"},
2293   "name": "SPI_SHADER_USER_DATA_GS_13",
2294   "type_ref": "CP_APPEND_DATA"
2295  },
2296  {
2297   "chips": ["gfx81"],
2298   "map": {"at": 45672, "to": "mm"},
2299   "name": "SPI_SHADER_USER_DATA_GS_14",
2300   "type_ref": "CP_APPEND_DATA"
2301  },
2302  {
2303   "chips": ["gfx81"],
2304   "map": {"at": 45676, "to": "mm"},
2305   "name": "SPI_SHADER_USER_DATA_GS_15",
2306   "type_ref": "CP_APPEND_DATA"
2307  },
2308  {
2309   "chips": ["gfx81"],
2310   "map": {"at": 45808, "to": "mm"},
2311   "name": "SPI_SHADER_PGM_RSRC2_ES_GS",
2312   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2313  },
2314  {
2315   "chips": ["gfx81"],
2316   "map": {"at": 45824, "to": "mm"},
2317   "name": "SPI_SHADER_TBA_LO_ES",
2318   "type_ref": "SPI_SHADER_TBA_LO_PS"
2319  },
2320  {
2321   "chips": ["gfx81"],
2322   "map": {"at": 45828, "to": "mm"},
2323   "name": "SPI_SHADER_TBA_HI_ES",
2324   "type_ref": "SPI_SHADER_TBA_HI_PS"
2325  },
2326  {
2327   "chips": ["gfx81"],
2328   "map": {"at": 45832, "to": "mm"},
2329   "name": "SPI_SHADER_TMA_LO_ES",
2330   "type_ref": "SPI_SHADER_TBA_LO_PS"
2331  },
2332  {
2333   "chips": ["gfx81"],
2334   "map": {"at": 45836, "to": "mm"},
2335   "name": "SPI_SHADER_TMA_HI_ES",
2336   "type_ref": "SPI_SHADER_TBA_HI_PS"
2337  },
2338  {
2339   "chips": ["gfx81"],
2340   "map": {"at": 45852, "to": "mm"},
2341   "name": "SPI_SHADER_PGM_RSRC3_ES",
2342   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2343  },
2344  {
2345   "chips": ["gfx81"],
2346   "map": {"at": 45856, "to": "mm"},
2347   "name": "SPI_SHADER_PGM_LO_ES",
2348   "type_ref": "SPI_SHADER_TBA_LO_PS"
2349  },
2350  {
2351   "chips": ["gfx81"],
2352   "map": {"at": 45860, "to": "mm"},
2353   "name": "SPI_SHADER_PGM_HI_ES",
2354   "type_ref": "SPI_SHADER_TBA_HI_PS"
2355  },
2356  {
2357   "chips": ["gfx81"],
2358   "map": {"at": 45864, "to": "mm"},
2359   "name": "SPI_SHADER_PGM_RSRC1_ES",
2360   "type_ref": "SPI_SHADER_PGM_RSRC1_VS"
2361  },
2362  {
2363   "chips": ["gfx81"],
2364   "map": {"at": 45868, "to": "mm"},
2365   "name": "SPI_SHADER_PGM_RSRC2_ES",
2366   "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS"
2367  },
2368  {
2369   "chips": ["gfx81"],
2370   "map": {"at": 45872, "to": "mm"},
2371   "name": "SPI_SHADER_USER_DATA_ES_0",
2372   "type_ref": "CP_APPEND_DATA"
2373  },
2374  {
2375   "chips": ["gfx81"],
2376   "map": {"at": 45876, "to": "mm"},
2377   "name": "SPI_SHADER_USER_DATA_ES_1",
2378   "type_ref": "CP_APPEND_DATA"
2379  },
2380  {
2381   "chips": ["gfx81"],
2382   "map": {"at": 45880, "to": "mm"},
2383   "name": "SPI_SHADER_USER_DATA_ES_2",
2384   "type_ref": "CP_APPEND_DATA"
2385  },
2386  {
2387   "chips": ["gfx81"],
2388   "map": {"at": 45884, "to": "mm"},
2389   "name": "SPI_SHADER_USER_DATA_ES_3",
2390   "type_ref": "CP_APPEND_DATA"
2391  },
2392  {
2393   "chips": ["gfx81"],
2394   "map": {"at": 45888, "to": "mm"},
2395   "name": "SPI_SHADER_USER_DATA_ES_4",
2396   "type_ref": "CP_APPEND_DATA"
2397  },
2398  {
2399   "chips": ["gfx81"],
2400   "map": {"at": 45892, "to": "mm"},
2401   "name": "SPI_SHADER_USER_DATA_ES_5",
2402   "type_ref": "CP_APPEND_DATA"
2403  },
2404  {
2405   "chips": ["gfx81"],
2406   "map": {"at": 45896, "to": "mm"},
2407   "name": "SPI_SHADER_USER_DATA_ES_6",
2408   "type_ref": "CP_APPEND_DATA"
2409  },
2410  {
2411   "chips": ["gfx81"],
2412   "map": {"at": 45900, "to": "mm"},
2413   "name": "SPI_SHADER_USER_DATA_ES_7",
2414   "type_ref": "CP_APPEND_DATA"
2415  },
2416  {
2417   "chips": ["gfx81"],
2418   "map": {"at": 45904, "to": "mm"},
2419   "name": "SPI_SHADER_USER_DATA_ES_8",
2420   "type_ref": "CP_APPEND_DATA"
2421  },
2422  {
2423   "chips": ["gfx81"],
2424   "map": {"at": 45908, "to": "mm"},
2425   "name": "SPI_SHADER_USER_DATA_ES_9",
2426   "type_ref": "CP_APPEND_DATA"
2427  },
2428  {
2429   "chips": ["gfx81"],
2430   "map": {"at": 45912, "to": "mm"},
2431   "name": "SPI_SHADER_USER_DATA_ES_10",
2432   "type_ref": "CP_APPEND_DATA"
2433  },
2434  {
2435   "chips": ["gfx81"],
2436   "map": {"at": 45916, "to": "mm"},
2437   "name": "SPI_SHADER_USER_DATA_ES_11",
2438   "type_ref": "CP_APPEND_DATA"
2439  },
2440  {
2441   "chips": ["gfx81"],
2442   "map": {"at": 45920, "to": "mm"},
2443   "name": "SPI_SHADER_USER_DATA_ES_12",
2444   "type_ref": "CP_APPEND_DATA"
2445  },
2446  {
2447   "chips": ["gfx81"],
2448   "map": {"at": 45924, "to": "mm"},
2449   "name": "SPI_SHADER_USER_DATA_ES_13",
2450   "type_ref": "CP_APPEND_DATA"
2451  },
2452  {
2453   "chips": ["gfx81"],
2454   "map": {"at": 45928, "to": "mm"},
2455   "name": "SPI_SHADER_USER_DATA_ES_14",
2456   "type_ref": "CP_APPEND_DATA"
2457  },
2458  {
2459   "chips": ["gfx81"],
2460   "map": {"at": 45932, "to": "mm"},
2461   "name": "SPI_SHADER_USER_DATA_ES_15",
2462   "type_ref": "CP_APPEND_DATA"
2463  },
2464  {
2465   "chips": ["gfx81"],
2466   "map": {"at": 46068, "to": "mm"},
2467   "name": "SPI_SHADER_PGM_RSRC2_LS_ES",
2468   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2469  },
2470  {
2471   "chips": ["gfx81"],
2472   "map": {"at": 46080, "to": "mm"},
2473   "name": "SPI_SHADER_TBA_LO_HS",
2474   "type_ref": "SPI_SHADER_TBA_LO_PS"
2475  },
2476  {
2477   "chips": ["gfx81"],
2478   "map": {"at": 46084, "to": "mm"},
2479   "name": "SPI_SHADER_TBA_HI_HS",
2480   "type_ref": "SPI_SHADER_TBA_HI_PS"
2481  },
2482  {
2483   "chips": ["gfx81"],
2484   "map": {"at": 46088, "to": "mm"},
2485   "name": "SPI_SHADER_TMA_LO_HS",
2486   "type_ref": "SPI_SHADER_TBA_LO_PS"
2487  },
2488  {
2489   "chips": ["gfx81"],
2490   "map": {"at": 46092, "to": "mm"},
2491   "name": "SPI_SHADER_TMA_HI_HS",
2492   "type_ref": "SPI_SHADER_TBA_HI_PS"
2493  },
2494  {
2495   "chips": ["gfx81"],
2496   "map": {"at": 46108, "to": "mm"},
2497   "name": "SPI_SHADER_PGM_RSRC3_HS",
2498   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2499  },
2500  {
2501   "chips": ["gfx81"],
2502   "map": {"at": 46112, "to": "mm"},
2503   "name": "SPI_SHADER_PGM_LO_HS",
2504   "type_ref": "SPI_SHADER_TBA_LO_PS"
2505  },
2506  {
2507   "chips": ["gfx81"],
2508   "map": {"at": 46116, "to": "mm"},
2509   "name": "SPI_SHADER_PGM_HI_HS",
2510   "type_ref": "SPI_SHADER_TBA_HI_PS"
2511  },
2512  {
2513   "chips": ["gfx81"],
2514   "map": {"at": 46120, "to": "mm"},
2515   "name": "SPI_SHADER_PGM_RSRC1_HS",
2516   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2517  },
2518  {
2519   "chips": ["gfx81"],
2520   "map": {"at": 46124, "to": "mm"},
2521   "name": "SPI_SHADER_PGM_RSRC2_HS",
2522   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2523  },
2524  {
2525   "chips": ["gfx81"],
2526   "map": {"at": 46128, "to": "mm"},
2527   "name": "SPI_SHADER_USER_DATA_HS_0",
2528   "type_ref": "CP_APPEND_DATA"
2529  },
2530  {
2531   "chips": ["gfx81"],
2532   "map": {"at": 46132, "to": "mm"},
2533   "name": "SPI_SHADER_USER_DATA_HS_1",
2534   "type_ref": "CP_APPEND_DATA"
2535  },
2536  {
2537   "chips": ["gfx81"],
2538   "map": {"at": 46136, "to": "mm"},
2539   "name": "SPI_SHADER_USER_DATA_HS_2",
2540   "type_ref": "CP_APPEND_DATA"
2541  },
2542  {
2543   "chips": ["gfx81"],
2544   "map": {"at": 46140, "to": "mm"},
2545   "name": "SPI_SHADER_USER_DATA_HS_3",
2546   "type_ref": "CP_APPEND_DATA"
2547  },
2548  {
2549   "chips": ["gfx81"],
2550   "map": {"at": 46144, "to": "mm"},
2551   "name": "SPI_SHADER_USER_DATA_HS_4",
2552   "type_ref": "CP_APPEND_DATA"
2553  },
2554  {
2555   "chips": ["gfx81"],
2556   "map": {"at": 46148, "to": "mm"},
2557   "name": "SPI_SHADER_USER_DATA_HS_5",
2558   "type_ref": "CP_APPEND_DATA"
2559  },
2560  {
2561   "chips": ["gfx81"],
2562   "map": {"at": 46152, "to": "mm"},
2563   "name": "SPI_SHADER_USER_DATA_HS_6",
2564   "type_ref": "CP_APPEND_DATA"
2565  },
2566  {
2567   "chips": ["gfx81"],
2568   "map": {"at": 46156, "to": "mm"},
2569   "name": "SPI_SHADER_USER_DATA_HS_7",
2570   "type_ref": "CP_APPEND_DATA"
2571  },
2572  {
2573   "chips": ["gfx81"],
2574   "map": {"at": 46160, "to": "mm"},
2575   "name": "SPI_SHADER_USER_DATA_HS_8",
2576   "type_ref": "CP_APPEND_DATA"
2577  },
2578  {
2579   "chips": ["gfx81"],
2580   "map": {"at": 46164, "to": "mm"},
2581   "name": "SPI_SHADER_USER_DATA_HS_9",
2582   "type_ref": "CP_APPEND_DATA"
2583  },
2584  {
2585   "chips": ["gfx81"],
2586   "map": {"at": 46168, "to": "mm"},
2587   "name": "SPI_SHADER_USER_DATA_HS_10",
2588   "type_ref": "CP_APPEND_DATA"
2589  },
2590  {
2591   "chips": ["gfx81"],
2592   "map": {"at": 46172, "to": "mm"},
2593   "name": "SPI_SHADER_USER_DATA_HS_11",
2594   "type_ref": "CP_APPEND_DATA"
2595  },
2596  {
2597   "chips": ["gfx81"],
2598   "map": {"at": 46176, "to": "mm"},
2599   "name": "SPI_SHADER_USER_DATA_HS_12",
2600   "type_ref": "CP_APPEND_DATA"
2601  },
2602  {
2603   "chips": ["gfx81"],
2604   "map": {"at": 46180, "to": "mm"},
2605   "name": "SPI_SHADER_USER_DATA_HS_13",
2606   "type_ref": "CP_APPEND_DATA"
2607  },
2608  {
2609   "chips": ["gfx81"],
2610   "map": {"at": 46184, "to": "mm"},
2611   "name": "SPI_SHADER_USER_DATA_HS_14",
2612   "type_ref": "CP_APPEND_DATA"
2613  },
2614  {
2615   "chips": ["gfx81"],
2616   "map": {"at": 46188, "to": "mm"},
2617   "name": "SPI_SHADER_USER_DATA_HS_15",
2618   "type_ref": "CP_APPEND_DATA"
2619  },
2620  {
2621   "chips": ["gfx81"],
2622   "map": {"at": 46324, "to": "mm"},
2623   "name": "SPI_SHADER_PGM_RSRC2_LS_HS",
2624   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2625  },
2626  {
2627   "chips": ["gfx81"],
2628   "map": {"at": 46336, "to": "mm"},
2629   "name": "SPI_SHADER_TBA_LO_LS",
2630   "type_ref": "SPI_SHADER_TBA_LO_PS"
2631  },
2632  {
2633   "chips": ["gfx81"],
2634   "map": {"at": 46340, "to": "mm"},
2635   "name": "SPI_SHADER_TBA_HI_LS",
2636   "type_ref": "SPI_SHADER_TBA_HI_PS"
2637  },
2638  {
2639   "chips": ["gfx81"],
2640   "map": {"at": 46344, "to": "mm"},
2641   "name": "SPI_SHADER_TMA_LO_LS",
2642   "type_ref": "SPI_SHADER_TBA_LO_PS"
2643  },
2644  {
2645   "chips": ["gfx81"],
2646   "map": {"at": 46348, "to": "mm"},
2647   "name": "SPI_SHADER_TMA_HI_LS",
2648   "type_ref": "SPI_SHADER_TBA_HI_PS"
2649  },
2650  {
2651   "chips": ["gfx81"],
2652   "map": {"at": 46364, "to": "mm"},
2653   "name": "SPI_SHADER_PGM_RSRC3_LS",
2654   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
2655  },
2656  {
2657   "chips": ["gfx81"],
2658   "map": {"at": 46368, "to": "mm"},
2659   "name": "SPI_SHADER_PGM_LO_LS",
2660   "type_ref": "SPI_SHADER_TBA_LO_PS"
2661  },
2662  {
2663   "chips": ["gfx81"],
2664   "map": {"at": 46372, "to": "mm"},
2665   "name": "SPI_SHADER_PGM_HI_LS",
2666   "type_ref": "SPI_SHADER_TBA_HI_PS"
2667  },
2668  {
2669   "chips": ["gfx81"],
2670   "map": {"at": 46376, "to": "mm"},
2671   "name": "SPI_SHADER_PGM_RSRC1_LS",
2672   "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
2673  },
2674  {
2675   "chips": ["gfx81"],
2676   "map": {"at": 46380, "to": "mm"},
2677   "name": "SPI_SHADER_PGM_RSRC2_LS",
2678   "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS"
2679  },
2680  {
2681   "chips": ["gfx81"],
2682   "map": {"at": 46384, "to": "mm"},
2683   "name": "SPI_SHADER_USER_DATA_LS_0",
2684   "type_ref": "CP_APPEND_DATA"
2685  },
2686  {
2687   "chips": ["gfx81"],
2688   "map": {"at": 46388, "to": "mm"},
2689   "name": "SPI_SHADER_USER_DATA_LS_1",
2690   "type_ref": "CP_APPEND_DATA"
2691  },
2692  {
2693   "chips": ["gfx81"],
2694   "map": {"at": 46392, "to": "mm"},
2695   "name": "SPI_SHADER_USER_DATA_LS_2",
2696   "type_ref": "CP_APPEND_DATA"
2697  },
2698  {
2699   "chips": ["gfx81"],
2700   "map": {"at": 46396, "to": "mm"},
2701   "name": "SPI_SHADER_USER_DATA_LS_3",
2702   "type_ref": "CP_APPEND_DATA"
2703  },
2704  {
2705   "chips": ["gfx81"],
2706   "map": {"at": 46400, "to": "mm"},
2707   "name": "SPI_SHADER_USER_DATA_LS_4",
2708   "type_ref": "CP_APPEND_DATA"
2709  },
2710  {
2711   "chips": ["gfx81"],
2712   "map": {"at": 46404, "to": "mm"},
2713   "name": "SPI_SHADER_USER_DATA_LS_5",
2714   "type_ref": "CP_APPEND_DATA"
2715  },
2716  {
2717   "chips": ["gfx81"],
2718   "map": {"at": 46408, "to": "mm"},
2719   "name": "SPI_SHADER_USER_DATA_LS_6",
2720   "type_ref": "CP_APPEND_DATA"
2721  },
2722  {
2723   "chips": ["gfx81"],
2724   "map": {"at": 46412, "to": "mm"},
2725   "name": "SPI_SHADER_USER_DATA_LS_7",
2726   "type_ref": "CP_APPEND_DATA"
2727  },
2728  {
2729   "chips": ["gfx81"],
2730   "map": {"at": 46416, "to": "mm"},
2731   "name": "SPI_SHADER_USER_DATA_LS_8",
2732   "type_ref": "CP_APPEND_DATA"
2733  },
2734  {
2735   "chips": ["gfx81"],
2736   "map": {"at": 46420, "to": "mm"},
2737   "name": "SPI_SHADER_USER_DATA_LS_9",
2738   "type_ref": "CP_APPEND_DATA"
2739  },
2740  {
2741   "chips": ["gfx81"],
2742   "map": {"at": 46424, "to": "mm"},
2743   "name": "SPI_SHADER_USER_DATA_LS_10",
2744   "type_ref": "CP_APPEND_DATA"
2745  },
2746  {
2747   "chips": ["gfx81"],
2748   "map": {"at": 46428, "to": "mm"},
2749   "name": "SPI_SHADER_USER_DATA_LS_11",
2750   "type_ref": "CP_APPEND_DATA"
2751  },
2752  {
2753   "chips": ["gfx81"],
2754   "map": {"at": 46432, "to": "mm"},
2755   "name": "SPI_SHADER_USER_DATA_LS_12",
2756   "type_ref": "CP_APPEND_DATA"
2757  },
2758  {
2759   "chips": ["gfx81"],
2760   "map": {"at": 46436, "to": "mm"},
2761   "name": "SPI_SHADER_USER_DATA_LS_13",
2762   "type_ref": "CP_APPEND_DATA"
2763  },
2764  {
2765   "chips": ["gfx81"],
2766   "map": {"at": 46440, "to": "mm"},
2767   "name": "SPI_SHADER_USER_DATA_LS_14",
2768   "type_ref": "CP_APPEND_DATA"
2769  },
2770  {
2771   "chips": ["gfx81"],
2772   "map": {"at": 46444, "to": "mm"},
2773   "name": "SPI_SHADER_USER_DATA_LS_15",
2774   "type_ref": "CP_APPEND_DATA"
2775  },
2776  {
2777   "chips": ["gfx81"],
2778   "map": {"at": 47104, "to": "mm"},
2779   "name": "COMPUTE_DISPATCH_INITIATOR",
2780   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2781  },
2782  {
2783   "chips": ["gfx81"],
2784   "map": {"at": 47108, "to": "mm"},
2785   "name": "COMPUTE_DIM_X",
2786   "type_ref": "COMPUTE_DIM_X"
2787  },
2788  {
2789   "chips": ["gfx81"],
2790   "map": {"at": 47112, "to": "mm"},
2791   "name": "COMPUTE_DIM_Y",
2792   "type_ref": "COMPUTE_DIM_X"
2793  },
2794  {
2795   "chips": ["gfx81"],
2796   "map": {"at": 47116, "to": "mm"},
2797   "name": "COMPUTE_DIM_Z",
2798   "type_ref": "COMPUTE_DIM_X"
2799  },
2800  {
2801   "chips": ["gfx81"],
2802   "map": {"at": 47120, "to": "mm"},
2803   "name": "COMPUTE_START_X",
2804   "type_ref": "COMPUTE_START_X"
2805  },
2806  {
2807   "chips": ["gfx81"],
2808   "map": {"at": 47124, "to": "mm"},
2809   "name": "COMPUTE_START_Y",
2810   "type_ref": "COMPUTE_START_X"
2811  },
2812  {
2813   "chips": ["gfx81"],
2814   "map": {"at": 47128, "to": "mm"},
2815   "name": "COMPUTE_START_Z",
2816   "type_ref": "COMPUTE_START_X"
2817  },
2818  {
2819   "chips": ["gfx81"],
2820   "map": {"at": 47132, "to": "mm"},
2821   "name": "COMPUTE_NUM_THREAD_X",
2822   "type_ref": "COMPUTE_NUM_THREAD_X"
2823  },
2824  {
2825   "chips": ["gfx81"],
2826   "map": {"at": 47136, "to": "mm"},
2827   "name": "COMPUTE_NUM_THREAD_Y",
2828   "type_ref": "COMPUTE_NUM_THREAD_X"
2829  },
2830  {
2831   "chips": ["gfx81"],
2832   "map": {"at": 47140, "to": "mm"},
2833   "name": "COMPUTE_NUM_THREAD_Z",
2834   "type_ref": "COMPUTE_NUM_THREAD_X"
2835  },
2836  {
2837   "chips": ["gfx81"],
2838   "map": {"at": 47144, "to": "mm"},
2839   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2840   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2841  },
2842  {
2843   "chips": ["gfx81"],
2844   "map": {"at": 47148, "to": "mm"},
2845   "name": "COMPUTE_PERFCOUNT_ENABLE",
2846   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2847  },
2848  {
2849   "chips": ["gfx81"],
2850   "map": {"at": 47152, "to": "mm"},
2851   "name": "COMPUTE_PGM_LO",
2852   "type_ref": "CP_APPEND_DATA"
2853  },
2854  {
2855   "chips": ["gfx81"],
2856   "map": {"at": 47156, "to": "mm"},
2857   "name": "COMPUTE_PGM_HI",
2858   "type_ref": "COMPUTE_PGM_HI"
2859  },
2860  {
2861   "chips": ["gfx81"],
2862   "map": {"at": 47160, "to": "mm"},
2863   "name": "COMPUTE_TBA_LO",
2864   "type_ref": "CP_APPEND_DATA"
2865  },
2866  {
2867   "chips": ["gfx81"],
2868   "map": {"at": 47164, "to": "mm"},
2869   "name": "COMPUTE_TBA_HI",
2870   "type_ref": "COMPUTE_TBA_HI"
2871  },
2872  {
2873   "chips": ["gfx81"],
2874   "map": {"at": 47168, "to": "mm"},
2875   "name": "COMPUTE_TMA_LO",
2876   "type_ref": "CP_APPEND_DATA"
2877  },
2878  {
2879   "chips": ["gfx81"],
2880   "map": {"at": 47172, "to": "mm"},
2881   "name": "COMPUTE_TMA_HI",
2882   "type_ref": "COMPUTE_TBA_HI"
2883  },
2884  {
2885   "chips": ["gfx81"],
2886   "map": {"at": 47176, "to": "mm"},
2887   "name": "COMPUTE_PGM_RSRC1",
2888   "type_ref": "COMPUTE_PGM_RSRC1"
2889  },
2890  {
2891   "chips": ["gfx81"],
2892   "map": {"at": 47180, "to": "mm"},
2893   "name": "COMPUTE_PGM_RSRC2",
2894   "type_ref": "COMPUTE_PGM_RSRC2"
2895  },
2896  {
2897   "chips": ["gfx81"],
2898   "map": {"at": 47184, "to": "mm"},
2899   "name": "COMPUTE_VMID",
2900   "type_ref": "COMPUTE_VMID"
2901  },
2902  {
2903   "chips": ["gfx81"],
2904   "map": {"at": 47188, "to": "mm"},
2905   "name": "COMPUTE_RESOURCE_LIMITS",
2906   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2907  },
2908  {
2909   "chips": ["gfx81"],
2910   "map": {"at": 47192, "to": "mm"},
2911   "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",
2912   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2913  },
2914  {
2915   "chips": ["gfx81"],
2916   "map": {"at": 47196, "to": "mm"},
2917   "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",
2918   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2919  },
2920  {
2921   "chips": ["gfx81"],
2922   "map": {"at": 47200, "to": "mm"},
2923   "name": "COMPUTE_TMPRING_SIZE",
2924   "type_ref": "COMPUTE_TMPRING_SIZE"
2925  },
2926  {
2927   "chips": ["gfx81"],
2928   "map": {"at": 47204, "to": "mm"},
2929   "name": "COMPUTE_STATIC_THREAD_MGMT_SE2",
2930   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2931  },
2932  {
2933   "chips": ["gfx81"],
2934   "map": {"at": 47208, "to": "mm"},
2935   "name": "COMPUTE_STATIC_THREAD_MGMT_SE3",
2936   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
2937  },
2938  {
2939   "chips": ["gfx81"],
2940   "map": {"at": 47212, "to": "mm"},
2941   "name": "COMPUTE_RESTART_X",
2942   "type_ref": "COMPUTE_RESTART_X"
2943  },
2944  {
2945   "chips": ["gfx81"],
2946   "map": {"at": 47216, "to": "mm"},
2947   "name": "COMPUTE_RESTART_Y",
2948   "type_ref": "COMPUTE_RESTART_X"
2949  },
2950  {
2951   "chips": ["gfx81"],
2952   "map": {"at": 47220, "to": "mm"},
2953   "name": "COMPUTE_RESTART_Z",
2954   "type_ref": "COMPUTE_RESTART_X"
2955  },
2956  {
2957   "chips": ["gfx81"],
2958   "map": {"at": 47224, "to": "mm"},
2959   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2960   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2961  },
2962  {
2963   "chips": ["gfx81"],
2964   "map": {"at": 47228, "to": "mm"},
2965   "name": "COMPUTE_MISC_RESERVED",
2966   "type_ref": "COMPUTE_MISC_RESERVED"
2967  },
2968  {
2969   "chips": ["gfx81"],
2970   "map": {"at": 47232, "to": "mm"},
2971   "name": "COMPUTE_DISPATCH_ID",
2972   "type_ref": "COMPUTE_DISPATCH_ID"
2973  },
2974  {
2975   "chips": ["gfx81"],
2976   "map": {"at": 47236, "to": "mm"},
2977   "name": "COMPUTE_THREADGROUP_ID",
2978   "type_ref": "COMPUTE_THREADGROUP_ID"
2979  },
2980  {
2981   "chips": ["gfx81"],
2982   "map": {"at": 47240, "to": "mm"},
2983   "name": "COMPUTE_RELAUNCH",
2984   "type_ref": "COMPUTE_RELAUNCH"
2985  },
2986  {
2987   "chips": ["gfx81"],
2988   "map": {"at": 47244, "to": "mm"},
2989   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO",
2990   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2991  },
2992  {
2993   "chips": ["gfx81"],
2994   "map": {"at": 47248, "to": "mm"},
2995   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2996   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2997  },
2998  {
2999   "chips": ["gfx81"],
3000   "map": {"at": 47252, "to": "mm"},
3001   "name": "COMPUTE_WAVE_RESTORE_CONTROL",
3002   "type_ref": "COMPUTE_WAVE_RESTORE_CONTROL"
3003  },
3004  {
3005   "chips": ["gfx81"],
3006   "map": {"at": 47360, "to": "mm"},
3007   "name": "COMPUTE_USER_DATA_0",
3008   "type_ref": "CP_APPEND_DATA"
3009  },
3010  {
3011   "chips": ["gfx81"],
3012   "map": {"at": 47364, "to": "mm"},
3013   "name": "COMPUTE_USER_DATA_1",
3014   "type_ref": "CP_APPEND_DATA"
3015  },
3016  {
3017   "chips": ["gfx81"],
3018   "map": {"at": 47368, "to": "mm"},
3019   "name": "COMPUTE_USER_DATA_2",
3020   "type_ref": "CP_APPEND_DATA"
3021  },
3022  {
3023   "chips": ["gfx81"],
3024   "map": {"at": 47372, "to": "mm"},
3025   "name": "COMPUTE_USER_DATA_3",
3026   "type_ref": "CP_APPEND_DATA"
3027  },
3028  {
3029   "chips": ["gfx81"],
3030   "map": {"at": 47376, "to": "mm"},
3031   "name": "COMPUTE_USER_DATA_4",
3032   "type_ref": "CP_APPEND_DATA"
3033  },
3034  {
3035   "chips": ["gfx81"],
3036   "map": {"at": 47380, "to": "mm"},
3037   "name": "COMPUTE_USER_DATA_5",
3038   "type_ref": "CP_APPEND_DATA"
3039  },
3040  {
3041   "chips": ["gfx81"],
3042   "map": {"at": 47384, "to": "mm"},
3043   "name": "COMPUTE_USER_DATA_6",
3044   "type_ref": "CP_APPEND_DATA"
3045  },
3046  {
3047   "chips": ["gfx81"],
3048   "map": {"at": 47388, "to": "mm"},
3049   "name": "COMPUTE_USER_DATA_7",
3050   "type_ref": "CP_APPEND_DATA"
3051  },
3052  {
3053   "chips": ["gfx81"],
3054   "map": {"at": 47392, "to": "mm"},
3055   "name": "COMPUTE_USER_DATA_8",
3056   "type_ref": "CP_APPEND_DATA"
3057  },
3058  {
3059   "chips": ["gfx81"],
3060   "map": {"at": 47396, "to": "mm"},
3061   "name": "COMPUTE_USER_DATA_9",
3062   "type_ref": "CP_APPEND_DATA"
3063  },
3064  {
3065   "chips": ["gfx81"],
3066   "map": {"at": 47400, "to": "mm"},
3067   "name": "COMPUTE_USER_DATA_10",
3068   "type_ref": "CP_APPEND_DATA"
3069  },
3070  {
3071   "chips": ["gfx81"],
3072   "map": {"at": 47404, "to": "mm"},
3073   "name": "COMPUTE_USER_DATA_11",
3074   "type_ref": "CP_APPEND_DATA"
3075  },
3076  {
3077   "chips": ["gfx81"],
3078   "map": {"at": 47408, "to": "mm"},
3079   "name": "COMPUTE_USER_DATA_12",
3080   "type_ref": "CP_APPEND_DATA"
3081  },
3082  {
3083   "chips": ["gfx81"],
3084   "map": {"at": 47412, "to": "mm"},
3085   "name": "COMPUTE_USER_DATA_13",
3086   "type_ref": "CP_APPEND_DATA"
3087  },
3088  {
3089   "chips": ["gfx81"],
3090   "map": {"at": 47416, "to": "mm"},
3091   "name": "COMPUTE_USER_DATA_14",
3092   "type_ref": "CP_APPEND_DATA"
3093  },
3094  {
3095   "chips": ["gfx81"],
3096   "map": {"at": 47420, "to": "mm"},
3097   "name": "COMPUTE_USER_DATA_15",
3098   "type_ref": "CP_APPEND_DATA"
3099  },
3100  {
3101   "chips": ["gfx81"],
3102   "map": {"at": 47612, "to": "mm"},
3103   "name": "COMPUTE_NOWHERE",
3104   "type_ref": "CP_APPEND_DATA"
3105  },
3106  {
3107   "chips": ["gfx81"],
3108   "map": {"at": 163840, "to": "mm"},
3109   "name": "DB_RENDER_CONTROL",
3110   "type_ref": "DB_RENDER_CONTROL"
3111  },
3112  {
3113   "chips": ["gfx81"],
3114   "map": {"at": 163844, "to": "mm"},
3115   "name": "DB_COUNT_CONTROL",
3116   "type_ref": "DB_COUNT_CONTROL"
3117  },
3118  {
3119   "chips": ["gfx81"],
3120   "map": {"at": 163848, "to": "mm"},
3121   "name": "DB_DEPTH_VIEW",
3122   "type_ref": "DB_DEPTH_VIEW"
3123  },
3124  {
3125   "chips": ["gfx81"],
3126   "map": {"at": 163852, "to": "mm"},
3127   "name": "DB_RENDER_OVERRIDE",
3128   "type_ref": "DB_RENDER_OVERRIDE"
3129  },
3130  {
3131   "chips": ["gfx81"],
3132   "map": {"at": 163856, "to": "mm"},
3133   "name": "DB_RENDER_OVERRIDE2",
3134   "type_ref": "DB_RENDER_OVERRIDE2"
3135  },
3136  {
3137   "chips": ["gfx81"],
3138   "map": {"at": 163860, "to": "mm"},
3139   "name": "DB_HTILE_DATA_BASE",
3140   "type_ref": "CB_COLOR0_BASE"
3141  },
3142  {
3143   "chips": ["gfx81"],
3144   "map": {"at": 163872, "to": "mm"},
3145   "name": "DB_DEPTH_BOUNDS_MIN",
3146   "type_ref": "DB_DEPTH_BOUNDS_MIN"
3147  },
3148  {
3149   "chips": ["gfx81"],
3150   "map": {"at": 163876, "to": "mm"},
3151   "name": "DB_DEPTH_BOUNDS_MAX",
3152   "type_ref": "DB_DEPTH_BOUNDS_MAX"
3153  },
3154  {
3155   "chips": ["gfx81"],
3156   "map": {"at": 163880, "to": "mm"},
3157   "name": "DB_STENCIL_CLEAR",
3158   "type_ref": "DB_STENCIL_CLEAR"
3159  },
3160  {
3161   "chips": ["gfx81"],
3162   "map": {"at": 163884, "to": "mm"},
3163   "name": "DB_DEPTH_CLEAR",
3164   "type_ref": "DB_DEPTH_CLEAR"
3165  },
3166  {
3167   "chips": ["gfx81"],
3168   "map": {"at": 163888, "to": "mm"},
3169   "name": "PA_SC_SCREEN_SCISSOR_TL",
3170   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
3171  },
3172  {
3173   "chips": ["gfx81"],
3174   "map": {"at": 163892, "to": "mm"},
3175   "name": "PA_SC_SCREEN_SCISSOR_BR",
3176   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
3177  },
3178  {
3179   "chips": ["gfx81"],
3180   "map": {"at": 163900, "to": "mm"},
3181   "name": "DB_DEPTH_INFO",
3182   "type_ref": "DB_DEPTH_INFO"
3183  },
3184  {
3185   "chips": ["gfx81"],
3186   "map": {"at": 163904, "to": "mm"},
3187   "name": "DB_Z_INFO",
3188   "type_ref": "DB_Z_INFO"
3189  },
3190  {
3191   "chips": ["gfx81"],
3192   "map": {"at": 163908, "to": "mm"},
3193   "name": "DB_STENCIL_INFO",
3194   "type_ref": "DB_STENCIL_INFO"
3195  },
3196  {
3197   "chips": ["gfx81"],
3198   "map": {"at": 163912, "to": "mm"},
3199   "name": "DB_Z_READ_BASE",
3200   "type_ref": "CB_COLOR0_BASE"
3201  },
3202  {
3203   "chips": ["gfx81"],
3204   "map": {"at": 163916, "to": "mm"},
3205   "name": "DB_STENCIL_READ_BASE",
3206   "type_ref": "CB_COLOR0_BASE"
3207  },
3208  {
3209   "chips": ["gfx81"],
3210   "map": {"at": 163920, "to": "mm"},
3211   "name": "DB_Z_WRITE_BASE",
3212   "type_ref": "CB_COLOR0_BASE"
3213  },
3214  {
3215   "chips": ["gfx81"],
3216   "map": {"at": 163924, "to": "mm"},
3217   "name": "DB_STENCIL_WRITE_BASE",
3218   "type_ref": "CB_COLOR0_BASE"
3219  },
3220  {
3221   "chips": ["gfx81"],
3222   "map": {"at": 163928, "to": "mm"},
3223   "name": "DB_DEPTH_SIZE",
3224   "type_ref": "DB_DEPTH_SIZE"
3225  },
3226  {
3227   "chips": ["gfx81"],
3228   "map": {"at": 163932, "to": "mm"},
3229   "name": "DB_DEPTH_SLICE",
3230   "type_ref": "DB_DEPTH_SLICE"
3231  },
3232  {
3233   "chips": ["gfx81"],
3234   "map": {"at": 163968, "to": "mm"},
3235   "name": "TA_BC_BASE_ADDR",
3236   "type_ref": "TA_BC_BASE_ADDR"
3237  },
3238  {
3239   "chips": ["gfx81"],
3240   "map": {"at": 163972, "to": "mm"},
3241   "name": "TA_BC_BASE_ADDR_HI",
3242   "type_ref": "TA_BC_BASE_ADDR_HI"
3243  },
3244  {
3245   "chips": ["gfx81"],
3246   "map": {"at": 164328, "to": "mm"},
3247   "name": "COHER_DEST_BASE_HI_0",
3248   "type_ref": "COHER_DEST_BASE_HI_0"
3249  },
3250  {
3251   "chips": ["gfx81"],
3252   "map": {"at": 164332, "to": "mm"},
3253   "name": "COHER_DEST_BASE_HI_1",
3254   "type_ref": "COHER_DEST_BASE_HI_0"
3255  },
3256  {
3257   "chips": ["gfx81"],
3258   "map": {"at": 164336, "to": "mm"},
3259   "name": "COHER_DEST_BASE_HI_2",
3260   "type_ref": "COHER_DEST_BASE_HI_0"
3261  },
3262  {
3263   "chips": ["gfx81"],
3264   "map": {"at": 164340, "to": "mm"},
3265   "name": "COHER_DEST_BASE_HI_3",
3266   "type_ref": "COHER_DEST_BASE_HI_0"
3267  },
3268  {
3269   "chips": ["gfx81"],
3270   "map": {"at": 164344, "to": "mm"},
3271   "name": "COHER_DEST_BASE_2",
3272   "type_ref": "COHER_DEST_BASE_0"
3273  },
3274  {
3275   "chips": ["gfx81"],
3276   "map": {"at": 164348, "to": "mm"},
3277   "name": "COHER_DEST_BASE_3",
3278   "type_ref": "COHER_DEST_BASE_0"
3279  },
3280  {
3281   "chips": ["gfx81"],
3282   "map": {"at": 164352, "to": "mm"},
3283   "name": "PA_SC_WINDOW_OFFSET",
3284   "type_ref": "PA_SC_WINDOW_OFFSET"
3285  },
3286  {
3287   "chips": ["gfx81"],
3288   "map": {"at": 164356, "to": "mm"},
3289   "name": "PA_SC_WINDOW_SCISSOR_TL",
3290   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3291  },
3292  {
3293   "chips": ["gfx81"],
3294   "map": {"at": 164360, "to": "mm"},
3295   "name": "PA_SC_WINDOW_SCISSOR_BR",
3296   "type_ref": "PA_SC_CLIPRECT_0_BR"
3297  },
3298  {
3299   "chips": ["gfx81"],
3300   "map": {"at": 164364, "to": "mm"},
3301   "name": "PA_SC_CLIPRECT_RULE",
3302   "type_ref": "PA_SC_CLIPRECT_RULE"
3303  },
3304  {
3305   "chips": ["gfx81"],
3306   "map": {"at": 164368, "to": "mm"},
3307   "name": "PA_SC_CLIPRECT_0_TL",
3308   "type_ref": "PA_SC_CLIPRECT_0_TL"
3309  },
3310  {
3311   "chips": ["gfx81"],
3312   "map": {"at": 164372, "to": "mm"},
3313   "name": "PA_SC_CLIPRECT_0_BR",
3314   "type_ref": "PA_SC_CLIPRECT_0_BR"
3315  },
3316  {
3317   "chips": ["gfx81"],
3318   "map": {"at": 164376, "to": "mm"},
3319   "name": "PA_SC_CLIPRECT_1_TL",
3320   "type_ref": "PA_SC_CLIPRECT_0_TL"
3321  },
3322  {
3323   "chips": ["gfx81"],
3324   "map": {"at": 164380, "to": "mm"},
3325   "name": "PA_SC_CLIPRECT_1_BR",
3326   "type_ref": "PA_SC_CLIPRECT_0_BR"
3327  },
3328  {
3329   "chips": ["gfx81"],
3330   "map": {"at": 164384, "to": "mm"},
3331   "name": "PA_SC_CLIPRECT_2_TL",
3332   "type_ref": "PA_SC_CLIPRECT_0_TL"
3333  },
3334  {
3335   "chips": ["gfx81"],
3336   "map": {"at": 164388, "to": "mm"},
3337   "name": "PA_SC_CLIPRECT_2_BR",
3338   "type_ref": "PA_SC_CLIPRECT_0_BR"
3339  },
3340  {
3341   "chips": ["gfx81"],
3342   "map": {"at": 164392, "to": "mm"},
3343   "name": "PA_SC_CLIPRECT_3_TL",
3344   "type_ref": "PA_SC_CLIPRECT_0_TL"
3345  },
3346  {
3347   "chips": ["gfx81"],
3348   "map": {"at": 164396, "to": "mm"},
3349   "name": "PA_SC_CLIPRECT_3_BR",
3350   "type_ref": "PA_SC_CLIPRECT_0_BR"
3351  },
3352  {
3353   "chips": ["gfx81"],
3354   "map": {"at": 164400, "to": "mm"},
3355   "name": "PA_SC_EDGERULE",
3356   "type_ref": "PA_SC_EDGERULE"
3357  },
3358  {
3359   "chips": ["gfx81"],
3360   "map": {"at": 164404, "to": "mm"},
3361   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3362   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3363  },
3364  {
3365   "chips": ["gfx81"],
3366   "map": {"at": 164408, "to": "mm"},
3367   "name": "CB_TARGET_MASK",
3368   "type_ref": "CB_TARGET_MASK"
3369  },
3370  {
3371   "chips": ["gfx81"],
3372   "map": {"at": 164412, "to": "mm"},
3373   "name": "CB_SHADER_MASK",
3374   "type_ref": "CB_SHADER_MASK"
3375  },
3376  {
3377   "chips": ["gfx81"],
3378   "map": {"at": 164416, "to": "mm"},
3379   "name": "PA_SC_GENERIC_SCISSOR_TL",
3380   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3381  },
3382  {
3383   "chips": ["gfx81"],
3384   "map": {"at": 164420, "to": "mm"},
3385   "name": "PA_SC_GENERIC_SCISSOR_BR",
3386   "type_ref": "PA_SC_CLIPRECT_0_BR"
3387  },
3388  {
3389   "chips": ["gfx81"],
3390   "map": {"at": 164424, "to": "mm"},
3391   "name": "COHER_DEST_BASE_0",
3392   "type_ref": "COHER_DEST_BASE_0"
3393  },
3394  {
3395   "chips": ["gfx81"],
3396   "map": {"at": 164428, "to": "mm"},
3397   "name": "COHER_DEST_BASE_1",
3398   "type_ref": "COHER_DEST_BASE_0"
3399  },
3400  {
3401   "chips": ["gfx81"],
3402   "map": {"at": 164432, "to": "mm"},
3403   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3404   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3405  },
3406  {
3407   "chips": ["gfx81"],
3408   "map": {"at": 164436, "to": "mm"},
3409   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3410   "type_ref": "PA_SC_CLIPRECT_0_BR"
3411  },
3412  {
3413   "chips": ["gfx81"],
3414   "map": {"at": 164440, "to": "mm"},
3415   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3416   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3417  },
3418  {
3419   "chips": ["gfx81"],
3420   "map": {"at": 164444, "to": "mm"},
3421   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3422   "type_ref": "PA_SC_CLIPRECT_0_BR"
3423  },
3424  {
3425   "chips": ["gfx81"],
3426   "map": {"at": 164448, "to": "mm"},
3427   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3428   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3429  },
3430  {
3431   "chips": ["gfx81"],
3432   "map": {"at": 164452, "to": "mm"},
3433   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3434   "type_ref": "PA_SC_CLIPRECT_0_BR"
3435  },
3436  {
3437   "chips": ["gfx81"],
3438   "map": {"at": 164456, "to": "mm"},
3439   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3440   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3441  },
3442  {
3443   "chips": ["gfx81"],
3444   "map": {"at": 164460, "to": "mm"},
3445   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3446   "type_ref": "PA_SC_CLIPRECT_0_BR"
3447  },
3448  {
3449   "chips": ["gfx81"],
3450   "map": {"at": 164464, "to": "mm"},
3451   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3452   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3453  },
3454  {
3455   "chips": ["gfx81"],
3456   "map": {"at": 164468, "to": "mm"},
3457   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3458   "type_ref": "PA_SC_CLIPRECT_0_BR"
3459  },
3460  {
3461   "chips": ["gfx81"],
3462   "map": {"at": 164472, "to": "mm"},
3463   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3464   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3465  },
3466  {
3467   "chips": ["gfx81"],
3468   "map": {"at": 164476, "to": "mm"},
3469   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3470   "type_ref": "PA_SC_CLIPRECT_0_BR"
3471  },
3472  {
3473   "chips": ["gfx81"],
3474   "map": {"at": 164480, "to": "mm"},
3475   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3476   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3477  },
3478  {
3479   "chips": ["gfx81"],
3480   "map": {"at": 164484, "to": "mm"},
3481   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3482   "type_ref": "PA_SC_CLIPRECT_0_BR"
3483  },
3484  {
3485   "chips": ["gfx81"],
3486   "map": {"at": 164488, "to": "mm"},
3487   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3488   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3489  },
3490  {
3491   "chips": ["gfx81"],
3492   "map": {"at": 164492, "to": "mm"},
3493   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3494   "type_ref": "PA_SC_CLIPRECT_0_BR"
3495  },
3496  {
3497   "chips": ["gfx81"],
3498   "map": {"at": 164496, "to": "mm"},
3499   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3500   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3501  },
3502  {
3503   "chips": ["gfx81"],
3504   "map": {"at": 164500, "to": "mm"},
3505   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3506   "type_ref": "PA_SC_CLIPRECT_0_BR"
3507  },
3508  {
3509   "chips": ["gfx81"],
3510   "map": {"at": 164504, "to": "mm"},
3511   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3512   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3513  },
3514  {
3515   "chips": ["gfx81"],
3516   "map": {"at": 164508, "to": "mm"},
3517   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3518   "type_ref": "PA_SC_CLIPRECT_0_BR"
3519  },
3520  {
3521   "chips": ["gfx81"],
3522   "map": {"at": 164512, "to": "mm"},
3523   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3524   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3525  },
3526  {
3527   "chips": ["gfx81"],
3528   "map": {"at": 164516, "to": "mm"},
3529   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3530   "type_ref": "PA_SC_CLIPRECT_0_BR"
3531  },
3532  {
3533   "chips": ["gfx81"],
3534   "map": {"at": 164520, "to": "mm"},
3535   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3536   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3537  },
3538  {
3539   "chips": ["gfx81"],
3540   "map": {"at": 164524, "to": "mm"},
3541   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3542   "type_ref": "PA_SC_CLIPRECT_0_BR"
3543  },
3544  {
3545   "chips": ["gfx81"],
3546   "map": {"at": 164528, "to": "mm"},
3547   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3548   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3549  },
3550  {
3551   "chips": ["gfx81"],
3552   "map": {"at": 164532, "to": "mm"},
3553   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3554   "type_ref": "PA_SC_CLIPRECT_0_BR"
3555  },
3556  {
3557   "chips": ["gfx81"],
3558   "map": {"at": 164536, "to": "mm"},
3559   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3560   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3561  },
3562  {
3563   "chips": ["gfx81"],
3564   "map": {"at": 164540, "to": "mm"},
3565   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3566   "type_ref": "PA_SC_CLIPRECT_0_BR"
3567  },
3568  {
3569   "chips": ["gfx81"],
3570   "map": {"at": 164544, "to": "mm"},
3571   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3572   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3573  },
3574  {
3575   "chips": ["gfx81"],
3576   "map": {"at": 164548, "to": "mm"},
3577   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3578   "type_ref": "PA_SC_CLIPRECT_0_BR"
3579  },
3580  {
3581   "chips": ["gfx81"],
3582   "map": {"at": 164552, "to": "mm"},
3583   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3584   "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
3585  },
3586  {
3587   "chips": ["gfx81"],
3588   "map": {"at": 164556, "to": "mm"},
3589   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3590   "type_ref": "PA_SC_CLIPRECT_0_BR"
3591  },
3592  {
3593   "chips": ["gfx81"],
3594   "map": {"at": 164560, "to": "mm"},
3595   "name": "PA_SC_VPORT_ZMIN_0",
3596   "type_ref": "PA_SC_VPORT_ZMIN_0"
3597  },
3598  {
3599   "chips": ["gfx81"],
3600   "map": {"at": 164564, "to": "mm"},
3601   "name": "PA_SC_VPORT_ZMAX_0",
3602   "type_ref": "PA_SC_VPORT_ZMAX_0"
3603  },
3604  {
3605   "chips": ["gfx81"],
3606   "map": {"at": 164568, "to": "mm"},
3607   "name": "PA_SC_VPORT_ZMIN_1",
3608   "type_ref": "PA_SC_VPORT_ZMIN_0"
3609  },
3610  {
3611   "chips": ["gfx81"],
3612   "map": {"at": 164572, "to": "mm"},
3613   "name": "PA_SC_VPORT_ZMAX_1",
3614   "type_ref": "PA_SC_VPORT_ZMAX_0"
3615  },
3616  {
3617   "chips": ["gfx81"],
3618   "map": {"at": 164576, "to": "mm"},
3619   "name": "PA_SC_VPORT_ZMIN_2",
3620   "type_ref": "PA_SC_VPORT_ZMIN_0"
3621  },
3622  {
3623   "chips": ["gfx81"],
3624   "map": {"at": 164580, "to": "mm"},
3625   "name": "PA_SC_VPORT_ZMAX_2",
3626   "type_ref": "PA_SC_VPORT_ZMAX_0"
3627  },
3628  {
3629   "chips": ["gfx81"],
3630   "map": {"at": 164584, "to": "mm"},
3631   "name": "PA_SC_VPORT_ZMIN_3",
3632   "type_ref": "PA_SC_VPORT_ZMIN_0"
3633  },
3634  {
3635   "chips": ["gfx81"],
3636   "map": {"at": 164588, "to": "mm"},
3637   "name": "PA_SC_VPORT_ZMAX_3",
3638   "type_ref": "PA_SC_VPORT_ZMAX_0"
3639  },
3640  {
3641   "chips": ["gfx81"],
3642   "map": {"at": 164592, "to": "mm"},
3643   "name": "PA_SC_VPORT_ZMIN_4",
3644   "type_ref": "PA_SC_VPORT_ZMIN_0"
3645  },
3646  {
3647   "chips": ["gfx81"],
3648   "map": {"at": 164596, "to": "mm"},
3649   "name": "PA_SC_VPORT_ZMAX_4",
3650   "type_ref": "PA_SC_VPORT_ZMAX_0"
3651  },
3652  {
3653   "chips": ["gfx81"],
3654   "map": {"at": 164600, "to": "mm"},
3655   "name": "PA_SC_VPORT_ZMIN_5",
3656   "type_ref": "PA_SC_VPORT_ZMIN_0"
3657  },
3658  {
3659   "chips": ["gfx81"],
3660   "map": {"at": 164604, "to": "mm"},
3661   "name": "PA_SC_VPORT_ZMAX_5",
3662   "type_ref": "PA_SC_VPORT_ZMAX_0"
3663  },
3664  {
3665   "chips": ["gfx81"],
3666   "map": {"at": 164608, "to": "mm"},
3667   "name": "PA_SC_VPORT_ZMIN_6",
3668   "type_ref": "PA_SC_VPORT_ZMIN_0"
3669  },
3670  {
3671   "chips": ["gfx81"],
3672   "map": {"at": 164612, "to": "mm"},
3673   "name": "PA_SC_VPORT_ZMAX_6",
3674   "type_ref": "PA_SC_VPORT_ZMAX_0"
3675  },
3676  {
3677   "chips": ["gfx81"],
3678   "map": {"at": 164616, "to": "mm"},
3679   "name": "PA_SC_VPORT_ZMIN_7",
3680   "type_ref": "PA_SC_VPORT_ZMIN_0"
3681  },
3682  {
3683   "chips": ["gfx81"],
3684   "map": {"at": 164620, "to": "mm"},
3685   "name": "PA_SC_VPORT_ZMAX_7",
3686   "type_ref": "PA_SC_VPORT_ZMAX_0"
3687  },
3688  {
3689   "chips": ["gfx81"],
3690   "map": {"at": 164624, "to": "mm"},
3691   "name": "PA_SC_VPORT_ZMIN_8",
3692   "type_ref": "PA_SC_VPORT_ZMIN_0"
3693  },
3694  {
3695   "chips": ["gfx81"],
3696   "map": {"at": 164628, "to": "mm"},
3697   "name": "PA_SC_VPORT_ZMAX_8",
3698   "type_ref": "PA_SC_VPORT_ZMAX_0"
3699  },
3700  {
3701   "chips": ["gfx81"],
3702   "map": {"at": 164632, "to": "mm"},
3703   "name": "PA_SC_VPORT_ZMIN_9",
3704   "type_ref": "PA_SC_VPORT_ZMIN_0"
3705  },
3706  {
3707   "chips": ["gfx81"],
3708   "map": {"at": 164636, "to": "mm"},
3709   "name": "PA_SC_VPORT_ZMAX_9",
3710   "type_ref": "PA_SC_VPORT_ZMAX_0"
3711  },
3712  {
3713   "chips": ["gfx81"],
3714   "map": {"at": 164640, "to": "mm"},
3715   "name": "PA_SC_VPORT_ZMIN_10",
3716   "type_ref": "PA_SC_VPORT_ZMIN_0"
3717  },
3718  {
3719   "chips": ["gfx81"],
3720   "map": {"at": 164644, "to": "mm"},
3721   "name": "PA_SC_VPORT_ZMAX_10",
3722   "type_ref": "PA_SC_VPORT_ZMAX_0"
3723  },
3724  {
3725   "chips": ["gfx81"],
3726   "map": {"at": 164648, "to": "mm"},
3727   "name": "PA_SC_VPORT_ZMIN_11",
3728   "type_ref": "PA_SC_VPORT_ZMIN_0"
3729  },
3730  {
3731   "chips": ["gfx81"],
3732   "map": {"at": 164652, "to": "mm"},
3733   "name": "PA_SC_VPORT_ZMAX_11",
3734   "type_ref": "PA_SC_VPORT_ZMAX_0"
3735  },
3736  {
3737   "chips": ["gfx81"],
3738   "map": {"at": 164656, "to": "mm"},
3739   "name": "PA_SC_VPORT_ZMIN_12",
3740   "type_ref": "PA_SC_VPORT_ZMIN_0"
3741  },
3742  {
3743   "chips": ["gfx81"],
3744   "map": {"at": 164660, "to": "mm"},
3745   "name": "PA_SC_VPORT_ZMAX_12",
3746   "type_ref": "PA_SC_VPORT_ZMAX_0"
3747  },
3748  {
3749   "chips": ["gfx81"],
3750   "map": {"at": 164664, "to": "mm"},
3751   "name": "PA_SC_VPORT_ZMIN_13",
3752   "type_ref": "PA_SC_VPORT_ZMIN_0"
3753  },
3754  {
3755   "chips": ["gfx81"],
3756   "map": {"at": 164668, "to": "mm"},
3757   "name": "PA_SC_VPORT_ZMAX_13",
3758   "type_ref": "PA_SC_VPORT_ZMAX_0"
3759  },
3760  {
3761   "chips": ["gfx81"],
3762   "map": {"at": 164672, "to": "mm"},
3763   "name": "PA_SC_VPORT_ZMIN_14",
3764   "type_ref": "PA_SC_VPORT_ZMIN_0"
3765  },
3766  {
3767   "chips": ["gfx81"],
3768   "map": {"at": 164676, "to": "mm"},
3769   "name": "PA_SC_VPORT_ZMAX_14",
3770   "type_ref": "PA_SC_VPORT_ZMAX_0"
3771  },
3772  {
3773   "chips": ["gfx81"],
3774   "map": {"at": 164680, "to": "mm"},
3775   "name": "PA_SC_VPORT_ZMIN_15",
3776   "type_ref": "PA_SC_VPORT_ZMIN_0"
3777  },
3778  {
3779   "chips": ["gfx81"],
3780   "map": {"at": 164684, "to": "mm"},
3781   "name": "PA_SC_VPORT_ZMAX_15",
3782   "type_ref": "PA_SC_VPORT_ZMAX_0"
3783  },
3784  {
3785   "chips": ["gfx81"],
3786   "map": {"at": 164688, "to": "mm"},
3787   "name": "PA_SC_RASTER_CONFIG",
3788   "type_ref": "PA_SC_RASTER_CONFIG"
3789  },
3790  {
3791   "chips": ["gfx81"],
3792   "map": {"at": 164692, "to": "mm"},
3793   "name": "PA_SC_RASTER_CONFIG_1",
3794   "type_ref": "PA_SC_RASTER_CONFIG_1"
3795  },
3796  {
3797   "chips": ["gfx81"],
3798   "map": {"at": 164696, "to": "mm"},
3799   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3800   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3801  },
3802  {
3803   "chips": ["gfx81"],
3804   "map": {"at": 164704, "to": "mm"},
3805   "name": "CP_PERFMON_CNTX_CNTL",
3806   "type_ref": "CP_PERFMON_CNTX_CNTL"
3807  },
3808  {
3809   "chips": ["gfx81"],
3810   "map": {"at": 164708, "to": "mm"},
3811   "name": "CP_RINGID",
3812   "type_ref": "CP_RINGID"
3813  },
3814  {
3815   "chips": ["gfx81"],
3816   "map": {"at": 164712, "to": "mm"},
3817   "name": "CP_VMID",
3818   "type_ref": "CP_VMID"
3819  },
3820  {
3821   "chips": ["gfx81"],
3822   "map": {"at": 164864, "to": "mm"},
3823   "name": "VGT_MAX_VTX_INDX",
3824   "type_ref": "VGT_MAX_VTX_INDX"
3825  },
3826  {
3827   "chips": ["gfx81"],
3828   "map": {"at": 164868, "to": "mm"},
3829   "name": "VGT_MIN_VTX_INDX",
3830   "type_ref": "VGT_MIN_VTX_INDX"
3831  },
3832  {
3833   "chips": ["gfx81"],
3834   "map": {"at": 164872, "to": "mm"},
3835   "name": "VGT_INDX_OFFSET",
3836   "type_ref": "VGT_INDX_OFFSET"
3837  },
3838  {
3839   "chips": ["gfx81"],
3840   "map": {"at": 164876, "to": "mm"},
3841   "name": "VGT_MULTI_PRIM_IB_RESET_INDX",
3842   "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX"
3843  },
3844  {
3845   "chips": ["gfx81"],
3846   "map": {"at": 164884, "to": "mm"},
3847   "name": "CB_BLEND_RED",
3848   "type_ref": "CB_BLEND_RED"
3849  },
3850  {
3851   "chips": ["gfx81"],
3852   "map": {"at": 164888, "to": "mm"},
3853   "name": "CB_BLEND_GREEN",
3854   "type_ref": "CB_BLEND_GREEN"
3855  },
3856  {
3857   "chips": ["gfx81"],
3858   "map": {"at": 164892, "to": "mm"},
3859   "name": "CB_BLEND_BLUE",
3860   "type_ref": "CB_BLEND_BLUE"
3861  },
3862  {
3863   "chips": ["gfx81"],
3864   "map": {"at": 164896, "to": "mm"},
3865   "name": "CB_BLEND_ALPHA",
3866   "type_ref": "CB_BLEND_ALPHA"
3867  },
3868  {
3869   "chips": ["gfx81"],
3870   "map": {"at": 164900, "to": "mm"},
3871   "name": "CB_DCC_CONTROL",
3872   "type_ref": "CB_DCC_CONTROL"
3873  },
3874  {
3875   "chips": ["gfx81"],
3876   "map": {"at": 164908, "to": "mm"},
3877   "name": "DB_STENCIL_CONTROL",
3878   "type_ref": "DB_STENCIL_CONTROL"
3879  },
3880  {
3881   "chips": ["gfx81"],
3882   "map": {"at": 164912, "to": "mm"},
3883   "name": "DB_STENCILREFMASK",
3884   "type_ref": "DB_STENCILREFMASK"
3885  },
3886  {
3887   "chips": ["gfx81"],
3888   "map": {"at": 164916, "to": "mm"},
3889   "name": "DB_STENCILREFMASK_BF",
3890   "type_ref": "DB_STENCILREFMASK_BF"
3891  },
3892  {
3893   "chips": ["gfx81"],
3894   "map": {"at": 164924, "to": "mm"},
3895   "name": "PA_CL_VPORT_XSCALE",
3896   "type_ref": "PA_CL_VPORT_XSCALE"
3897  },
3898  {
3899   "chips": ["gfx81"],
3900   "map": {"at": 164928, "to": "mm"},
3901   "name": "PA_CL_VPORT_XOFFSET",
3902   "type_ref": "PA_CL_VPORT_XOFFSET"
3903  },
3904  {
3905   "chips": ["gfx81"],
3906   "map": {"at": 164932, "to": "mm"},
3907   "name": "PA_CL_VPORT_YSCALE",
3908   "type_ref": "PA_CL_VPORT_YSCALE"
3909  },
3910  {
3911   "chips": ["gfx81"],
3912   "map": {"at": 164936, "to": "mm"},
3913   "name": "PA_CL_VPORT_YOFFSET",
3914   "type_ref": "PA_CL_VPORT_YOFFSET"
3915  },
3916  {
3917   "chips": ["gfx81"],
3918   "map": {"at": 164940, "to": "mm"},
3919   "name": "PA_CL_VPORT_ZSCALE",
3920   "type_ref": "PA_CL_VPORT_ZSCALE"
3921  },
3922  {
3923   "chips": ["gfx81"],
3924   "map": {"at": 164944, "to": "mm"},
3925   "name": "PA_CL_VPORT_ZOFFSET",
3926   "type_ref": "PA_CL_VPORT_ZOFFSET"
3927  },
3928  {
3929   "chips": ["gfx81"],
3930   "map": {"at": 164948, "to": "mm"},
3931   "name": "PA_CL_VPORT_XSCALE_1",
3932   "type_ref": "PA_CL_VPORT_XSCALE"
3933  },
3934  {
3935   "chips": ["gfx81"],
3936   "map": {"at": 164952, "to": "mm"},
3937   "name": "PA_CL_VPORT_XOFFSET_1",
3938   "type_ref": "PA_CL_VPORT_XOFFSET"
3939  },
3940  {
3941   "chips": ["gfx81"],
3942   "map": {"at": 164956, "to": "mm"},
3943   "name": "PA_CL_VPORT_YSCALE_1",
3944   "type_ref": "PA_CL_VPORT_YSCALE"
3945  },
3946  {
3947   "chips": ["gfx81"],
3948   "map": {"at": 164960, "to": "mm"},
3949   "name": "PA_CL_VPORT_YOFFSET_1",
3950   "type_ref": "PA_CL_VPORT_YOFFSET"
3951  },
3952  {
3953   "chips": ["gfx81"],
3954   "map": {"at": 164964, "to": "mm"},
3955   "name": "PA_CL_VPORT_ZSCALE_1",
3956   "type_ref": "PA_CL_VPORT_ZSCALE"
3957  },
3958  {
3959   "chips": ["gfx81"],
3960   "map": {"at": 164968, "to": "mm"},
3961   "name": "PA_CL_VPORT_ZOFFSET_1",
3962   "type_ref": "PA_CL_VPORT_ZOFFSET"
3963  },
3964  {
3965   "chips": ["gfx81"],
3966   "map": {"at": 164972, "to": "mm"},
3967   "name": "PA_CL_VPORT_XSCALE_2",
3968   "type_ref": "PA_CL_VPORT_XSCALE"
3969  },
3970  {
3971   "chips": ["gfx81"],
3972   "map": {"at": 164976, "to": "mm"},
3973   "name": "PA_CL_VPORT_XOFFSET_2",
3974   "type_ref": "PA_CL_VPORT_XOFFSET"
3975  },
3976  {
3977   "chips": ["gfx81"],
3978   "map": {"at": 164980, "to": "mm"},
3979   "name": "PA_CL_VPORT_YSCALE_2",
3980   "type_ref": "PA_CL_VPORT_YSCALE"
3981  },
3982  {
3983   "chips": ["gfx81"],
3984   "map": {"at": 164984, "to": "mm"},
3985   "name": "PA_CL_VPORT_YOFFSET_2",
3986   "type_ref": "PA_CL_VPORT_YOFFSET"
3987  },
3988  {
3989   "chips": ["gfx81"],
3990   "map": {"at": 164988, "to": "mm"},
3991   "name": "PA_CL_VPORT_ZSCALE_2",
3992   "type_ref": "PA_CL_VPORT_ZSCALE"
3993  },
3994  {
3995   "chips": ["gfx81"],
3996   "map": {"at": 164992, "to": "mm"},
3997   "name": "PA_CL_VPORT_ZOFFSET_2",
3998   "type_ref": "PA_CL_VPORT_ZOFFSET"
3999  },
4000  {
4001   "chips": ["gfx81"],
4002   "map": {"at": 164996, "to": "mm"},
4003   "name": "PA_CL_VPORT_XSCALE_3",
4004   "type_ref": "PA_CL_VPORT_XSCALE"
4005  },
4006  {
4007   "chips": ["gfx81"],
4008   "map": {"at": 165000, "to": "mm"},
4009   "name": "PA_CL_VPORT_XOFFSET_3",
4010   "type_ref": "PA_CL_VPORT_XOFFSET"
4011  },
4012  {
4013   "chips": ["gfx81"],
4014   "map": {"at": 165004, "to": "mm"},
4015   "name": "PA_CL_VPORT_YSCALE_3",
4016   "type_ref": "PA_CL_VPORT_YSCALE"
4017  },
4018  {
4019   "chips": ["gfx81"],
4020   "map": {"at": 165008, "to": "mm"},
4021   "name": "PA_CL_VPORT_YOFFSET_3",
4022   "type_ref": "PA_CL_VPORT_YOFFSET"
4023  },
4024  {
4025   "chips": ["gfx81"],
4026   "map": {"at": 165012, "to": "mm"},
4027   "name": "PA_CL_VPORT_ZSCALE_3",
4028   "type_ref": "PA_CL_VPORT_ZSCALE"
4029  },
4030  {
4031   "chips": ["gfx81"],
4032   "map": {"at": 165016, "to": "mm"},
4033   "name": "PA_CL_VPORT_ZOFFSET_3",
4034   "type_ref": "PA_CL_VPORT_ZOFFSET"
4035  },
4036  {
4037   "chips": ["gfx81"],
4038   "map": {"at": 165020, "to": "mm"},
4039   "name": "PA_CL_VPORT_XSCALE_4",
4040   "type_ref": "PA_CL_VPORT_XSCALE"
4041  },
4042  {
4043   "chips": ["gfx81"],
4044   "map": {"at": 165024, "to": "mm"},
4045   "name": "PA_CL_VPORT_XOFFSET_4",
4046   "type_ref": "PA_CL_VPORT_XOFFSET"
4047  },
4048  {
4049   "chips": ["gfx81"],
4050   "map": {"at": 165028, "to": "mm"},
4051   "name": "PA_CL_VPORT_YSCALE_4",
4052   "type_ref": "PA_CL_VPORT_YSCALE"
4053  },
4054  {
4055   "chips": ["gfx81"],
4056   "map": {"at": 165032, "to": "mm"},
4057   "name": "PA_CL_VPORT_YOFFSET_4",
4058   "type_ref": "PA_CL_VPORT_YOFFSET"
4059  },
4060  {
4061   "chips": ["gfx81"],
4062   "map": {"at": 165036, "to": "mm"},
4063   "name": "PA_CL_VPORT_ZSCALE_4",
4064   "type_ref": "PA_CL_VPORT_ZSCALE"
4065  },
4066  {
4067   "chips": ["gfx81"],
4068   "map": {"at": 165040, "to": "mm"},
4069   "name": "PA_CL_VPORT_ZOFFSET_4",
4070   "type_ref": "PA_CL_VPORT_ZOFFSET"
4071  },
4072  {
4073   "chips": ["gfx81"],
4074   "map": {"at": 165044, "to": "mm"},
4075   "name": "PA_CL_VPORT_XSCALE_5",
4076   "type_ref": "PA_CL_VPORT_XSCALE"
4077  },
4078  {
4079   "chips": ["gfx81"],
4080   "map": {"at": 165048, "to": "mm"},
4081   "name": "PA_CL_VPORT_XOFFSET_5",
4082   "type_ref": "PA_CL_VPORT_XOFFSET"
4083  },
4084  {
4085   "chips": ["gfx81"],
4086   "map": {"at": 165052, "to": "mm"},
4087   "name": "PA_CL_VPORT_YSCALE_5",
4088   "type_ref": "PA_CL_VPORT_YSCALE"
4089  },
4090  {
4091   "chips": ["gfx81"],
4092   "map": {"at": 165056, "to": "mm"},
4093   "name": "PA_CL_VPORT_YOFFSET_5",
4094   "type_ref": "PA_CL_VPORT_YOFFSET"
4095  },
4096  {
4097   "chips": ["gfx81"],
4098   "map": {"at": 165060, "to": "mm"},
4099   "name": "PA_CL_VPORT_ZSCALE_5",
4100   "type_ref": "PA_CL_VPORT_ZSCALE"
4101  },
4102  {
4103   "chips": ["gfx81"],
4104   "map": {"at": 165064, "to": "mm"},
4105   "name": "PA_CL_VPORT_ZOFFSET_5",
4106   "type_ref": "PA_CL_VPORT_ZOFFSET"
4107  },
4108  {
4109   "chips": ["gfx81"],
4110   "map": {"at": 165068, "to": "mm"},
4111   "name": "PA_CL_VPORT_XSCALE_6",
4112   "type_ref": "PA_CL_VPORT_XSCALE"
4113  },
4114  {
4115   "chips": ["gfx81"],
4116   "map": {"at": 165072, "to": "mm"},
4117   "name": "PA_CL_VPORT_XOFFSET_6",
4118   "type_ref": "PA_CL_VPORT_XOFFSET"
4119  },
4120  {
4121   "chips": ["gfx81"],
4122   "map": {"at": 165076, "to": "mm"},
4123   "name": "PA_CL_VPORT_YSCALE_6",
4124   "type_ref": "PA_CL_VPORT_YSCALE"
4125  },
4126  {
4127   "chips": ["gfx81"],
4128   "map": {"at": 165080, "to": "mm"},
4129   "name": "PA_CL_VPORT_YOFFSET_6",
4130   "type_ref": "PA_CL_VPORT_YOFFSET"
4131  },
4132  {
4133   "chips": ["gfx81"],
4134   "map": {"at": 165084, "to": "mm"},
4135   "name": "PA_CL_VPORT_ZSCALE_6",
4136   "type_ref": "PA_CL_VPORT_ZSCALE"
4137  },
4138  {
4139   "chips": ["gfx81"],
4140   "map": {"at": 165088, "to": "mm"},
4141   "name": "PA_CL_VPORT_ZOFFSET_6",
4142   "type_ref": "PA_CL_VPORT_ZOFFSET"
4143  },
4144  {
4145   "chips": ["gfx81"],
4146   "map": {"at": 165092, "to": "mm"},
4147   "name": "PA_CL_VPORT_XSCALE_7",
4148   "type_ref": "PA_CL_VPORT_XSCALE"
4149  },
4150  {
4151   "chips": ["gfx81"],
4152   "map": {"at": 165096, "to": "mm"},
4153   "name": "PA_CL_VPORT_XOFFSET_7",
4154   "type_ref": "PA_CL_VPORT_XOFFSET"
4155  },
4156  {
4157   "chips": ["gfx81"],
4158   "map": {"at": 165100, "to": "mm"},
4159   "name": "PA_CL_VPORT_YSCALE_7",
4160   "type_ref": "PA_CL_VPORT_YSCALE"
4161  },
4162  {
4163   "chips": ["gfx81"],
4164   "map": {"at": 165104, "to": "mm"},
4165   "name": "PA_CL_VPORT_YOFFSET_7",
4166   "type_ref": "PA_CL_VPORT_YOFFSET"
4167  },
4168  {
4169   "chips": ["gfx81"],
4170   "map": {"at": 165108, "to": "mm"},
4171   "name": "PA_CL_VPORT_ZSCALE_7",
4172   "type_ref": "PA_CL_VPORT_ZSCALE"
4173  },
4174  {
4175   "chips": ["gfx81"],
4176   "map": {"at": 165112, "to": "mm"},
4177   "name": "PA_CL_VPORT_ZOFFSET_7",
4178   "type_ref": "PA_CL_VPORT_ZOFFSET"
4179  },
4180  {
4181   "chips": ["gfx81"],
4182   "map": {"at": 165116, "to": "mm"},
4183   "name": "PA_CL_VPORT_XSCALE_8",
4184   "type_ref": "PA_CL_VPORT_XSCALE"
4185  },
4186  {
4187   "chips": ["gfx81"],
4188   "map": {"at": 165120, "to": "mm"},
4189   "name": "PA_CL_VPORT_XOFFSET_8",
4190   "type_ref": "PA_CL_VPORT_XOFFSET"
4191  },
4192  {
4193   "chips": ["gfx81"],
4194   "map": {"at": 165124, "to": "mm"},
4195   "name": "PA_CL_VPORT_YSCALE_8",
4196   "type_ref": "PA_CL_VPORT_YSCALE"
4197  },
4198  {
4199   "chips": ["gfx81"],
4200   "map": {"at": 165128, "to": "mm"},
4201   "name": "PA_CL_VPORT_YOFFSET_8",
4202   "type_ref": "PA_CL_VPORT_YOFFSET"
4203  },
4204  {
4205   "chips": ["gfx81"],
4206   "map": {"at": 165132, "to": "mm"},
4207   "name": "PA_CL_VPORT_ZSCALE_8",
4208   "type_ref": "PA_CL_VPORT_ZSCALE"
4209  },
4210  {
4211   "chips": ["gfx81"],
4212   "map": {"at": 165136, "to": "mm"},
4213   "name": "PA_CL_VPORT_ZOFFSET_8",
4214   "type_ref": "PA_CL_VPORT_ZOFFSET"
4215  },
4216  {
4217   "chips": ["gfx81"],
4218   "map": {"at": 165140, "to": "mm"},
4219   "name": "PA_CL_VPORT_XSCALE_9",
4220   "type_ref": "PA_CL_VPORT_XSCALE"
4221  },
4222  {
4223   "chips": ["gfx81"],
4224   "map": {"at": 165144, "to": "mm"},
4225   "name": "PA_CL_VPORT_XOFFSET_9",
4226   "type_ref": "PA_CL_VPORT_XOFFSET"
4227  },
4228  {
4229   "chips": ["gfx81"],
4230   "map": {"at": 165148, "to": "mm"},
4231   "name": "PA_CL_VPORT_YSCALE_9",
4232   "type_ref": "PA_CL_VPORT_YSCALE"
4233  },
4234  {
4235   "chips": ["gfx81"],
4236   "map": {"at": 165152, "to": "mm"},
4237   "name": "PA_CL_VPORT_YOFFSET_9",
4238   "type_ref": "PA_CL_VPORT_YOFFSET"
4239  },
4240  {
4241   "chips": ["gfx81"],
4242   "map": {"at": 165156, "to": "mm"},
4243   "name": "PA_CL_VPORT_ZSCALE_9",
4244   "type_ref": "PA_CL_VPORT_ZSCALE"
4245  },
4246  {
4247   "chips": ["gfx81"],
4248   "map": {"at": 165160, "to": "mm"},
4249   "name": "PA_CL_VPORT_ZOFFSET_9",
4250   "type_ref": "PA_CL_VPORT_ZOFFSET"
4251  },
4252  {
4253   "chips": ["gfx81"],
4254   "map": {"at": 165164, "to": "mm"},
4255   "name": "PA_CL_VPORT_XSCALE_10",
4256   "type_ref": "PA_CL_VPORT_XSCALE"
4257  },
4258  {
4259   "chips": ["gfx81"],
4260   "map": {"at": 165168, "to": "mm"},
4261   "name": "PA_CL_VPORT_XOFFSET_10",
4262   "type_ref": "PA_CL_VPORT_XOFFSET"
4263  },
4264  {
4265   "chips": ["gfx81"],
4266   "map": {"at": 165172, "to": "mm"},
4267   "name": "PA_CL_VPORT_YSCALE_10",
4268   "type_ref": "PA_CL_VPORT_YSCALE"
4269  },
4270  {
4271   "chips": ["gfx81"],
4272   "map": {"at": 165176, "to": "mm"},
4273   "name": "PA_CL_VPORT_YOFFSET_10",
4274   "type_ref": "PA_CL_VPORT_YOFFSET"
4275  },
4276  {
4277   "chips": ["gfx81"],
4278   "map": {"at": 165180, "to": "mm"},
4279   "name": "PA_CL_VPORT_ZSCALE_10",
4280   "type_ref": "PA_CL_VPORT_ZSCALE"
4281  },
4282  {
4283   "chips": ["gfx81"],
4284   "map": {"at": 165184, "to": "mm"},
4285   "name": "PA_CL_VPORT_ZOFFSET_10",
4286   "type_ref": "PA_CL_VPORT_ZOFFSET"
4287  },
4288  {
4289   "chips": ["gfx81"],
4290   "map": {"at": 165188, "to": "mm"},
4291   "name": "PA_CL_VPORT_XSCALE_11",
4292   "type_ref": "PA_CL_VPORT_XSCALE"
4293  },
4294  {
4295   "chips": ["gfx81"],
4296   "map": {"at": 165192, "to": "mm"},
4297   "name": "PA_CL_VPORT_XOFFSET_11",
4298   "type_ref": "PA_CL_VPORT_XOFFSET"
4299  },
4300  {
4301   "chips": ["gfx81"],
4302   "map": {"at": 165196, "to": "mm"},
4303   "name": "PA_CL_VPORT_YSCALE_11",
4304   "type_ref": "PA_CL_VPORT_YSCALE"
4305  },
4306  {
4307   "chips": ["gfx81"],
4308   "map": {"at": 165200, "to": "mm"},
4309   "name": "PA_CL_VPORT_YOFFSET_11",
4310   "type_ref": "PA_CL_VPORT_YOFFSET"
4311  },
4312  {
4313   "chips": ["gfx81"],
4314   "map": {"at": 165204, "to": "mm"},
4315   "name": "PA_CL_VPORT_ZSCALE_11",
4316   "type_ref": "PA_CL_VPORT_ZSCALE"
4317  },
4318  {
4319   "chips": ["gfx81"],
4320   "map": {"at": 165208, "to": "mm"},
4321   "name": "PA_CL_VPORT_ZOFFSET_11",
4322   "type_ref": "PA_CL_VPORT_ZOFFSET"
4323  },
4324  {
4325   "chips": ["gfx81"],
4326   "map": {"at": 165212, "to": "mm"},
4327   "name": "PA_CL_VPORT_XSCALE_12",
4328   "type_ref": "PA_CL_VPORT_XSCALE"
4329  },
4330  {
4331   "chips": ["gfx81"],
4332   "map": {"at": 165216, "to": "mm"},
4333   "name": "PA_CL_VPORT_XOFFSET_12",
4334   "type_ref": "PA_CL_VPORT_XOFFSET"
4335  },
4336  {
4337   "chips": ["gfx81"],
4338   "map": {"at": 165220, "to": "mm"},
4339   "name": "PA_CL_VPORT_YSCALE_12",
4340   "type_ref": "PA_CL_VPORT_YSCALE"
4341  },
4342  {
4343   "chips": ["gfx81"],
4344   "map": {"at": 165224, "to": "mm"},
4345   "name": "PA_CL_VPORT_YOFFSET_12",
4346   "type_ref": "PA_CL_VPORT_YOFFSET"
4347  },
4348  {
4349   "chips": ["gfx81"],
4350   "map": {"at": 165228, "to": "mm"},
4351   "name": "PA_CL_VPORT_ZSCALE_12",
4352   "type_ref": "PA_CL_VPORT_ZSCALE"
4353  },
4354  {
4355   "chips": ["gfx81"],
4356   "map": {"at": 165232, "to": "mm"},
4357   "name": "PA_CL_VPORT_ZOFFSET_12",
4358   "type_ref": "PA_CL_VPORT_ZOFFSET"
4359  },
4360  {
4361   "chips": ["gfx81"],
4362   "map": {"at": 165236, "to": "mm"},
4363   "name": "PA_CL_VPORT_XSCALE_13",
4364   "type_ref": "PA_CL_VPORT_XSCALE"
4365  },
4366  {
4367   "chips": ["gfx81"],
4368   "map": {"at": 165240, "to": "mm"},
4369   "name": "PA_CL_VPORT_XOFFSET_13",
4370   "type_ref": "PA_CL_VPORT_XOFFSET"
4371  },
4372  {
4373   "chips": ["gfx81"],
4374   "map": {"at": 165244, "to": "mm"},
4375   "name": "PA_CL_VPORT_YSCALE_13",
4376   "type_ref": "PA_CL_VPORT_YSCALE"
4377  },
4378  {
4379   "chips": ["gfx81"],
4380   "map": {"at": 165248, "to": "mm"},
4381   "name": "PA_CL_VPORT_YOFFSET_13",
4382   "type_ref": "PA_CL_VPORT_YOFFSET"
4383  },
4384  {
4385   "chips": ["gfx81"],
4386   "map": {"at": 165252, "to": "mm"},
4387   "name": "PA_CL_VPORT_ZSCALE_13",
4388   "type_ref": "PA_CL_VPORT_ZSCALE"
4389  },
4390  {
4391   "chips": ["gfx81"],
4392   "map": {"at": 165256, "to": "mm"},
4393   "name": "PA_CL_VPORT_ZOFFSET_13",
4394   "type_ref": "PA_CL_VPORT_ZOFFSET"
4395  },
4396  {
4397   "chips": ["gfx81"],
4398   "map": {"at": 165260, "to": "mm"},
4399   "name": "PA_CL_VPORT_XSCALE_14",
4400   "type_ref": "PA_CL_VPORT_XSCALE"
4401  },
4402  {
4403   "chips": ["gfx81"],
4404   "map": {"at": 165264, "to": "mm"},
4405   "name": "PA_CL_VPORT_XOFFSET_14",
4406   "type_ref": "PA_CL_VPORT_XOFFSET"
4407  },
4408  {
4409   "chips": ["gfx81"],
4410   "map": {"at": 165268, "to": "mm"},
4411   "name": "PA_CL_VPORT_YSCALE_14",
4412   "type_ref": "PA_CL_VPORT_YSCALE"
4413  },
4414  {
4415   "chips": ["gfx81"],
4416   "map": {"at": 165272, "to": "mm"},
4417   "name": "PA_CL_VPORT_YOFFSET_14",
4418   "type_ref": "PA_CL_VPORT_YOFFSET"
4419  },
4420  {
4421   "chips": ["gfx81"],
4422   "map": {"at": 165276, "to": "mm"},
4423   "name": "PA_CL_VPORT_ZSCALE_14",
4424   "type_ref": "PA_CL_VPORT_ZSCALE"
4425  },
4426  {
4427   "chips": ["gfx81"],
4428   "map": {"at": 165280, "to": "mm"},
4429   "name": "PA_CL_VPORT_ZOFFSET_14",
4430   "type_ref": "PA_CL_VPORT_ZOFFSET"
4431  },
4432  {
4433   "chips": ["gfx81"],
4434   "map": {"at": 165284, "to": "mm"},
4435   "name": "PA_CL_VPORT_XSCALE_15",
4436   "type_ref": "PA_CL_VPORT_XSCALE"
4437  },
4438  {
4439   "chips": ["gfx81"],
4440   "map": {"at": 165288, "to": "mm"},
4441   "name": "PA_CL_VPORT_XOFFSET_15",
4442   "type_ref": "PA_CL_VPORT_XOFFSET"
4443  },
4444  {
4445   "chips": ["gfx81"],
4446   "map": {"at": 165292, "to": "mm"},
4447   "name": "PA_CL_VPORT_YSCALE_15",
4448   "type_ref": "PA_CL_VPORT_YSCALE"
4449  },
4450  {
4451   "chips": ["gfx81"],
4452   "map": {"at": 165296, "to": "mm"},
4453   "name": "PA_CL_VPORT_YOFFSET_15",
4454   "type_ref": "PA_CL_VPORT_YOFFSET"
4455  },
4456  {
4457   "chips": ["gfx81"],
4458   "map": {"at": 165300, "to": "mm"},
4459   "name": "PA_CL_VPORT_ZSCALE_15",
4460   "type_ref": "PA_CL_VPORT_ZSCALE"
4461  },
4462  {
4463   "chips": ["gfx81"],
4464   "map": {"at": 165304, "to": "mm"},
4465   "name": "PA_CL_VPORT_ZOFFSET_15",
4466   "type_ref": "PA_CL_VPORT_ZOFFSET"
4467  },
4468  {
4469   "chips": ["gfx81"],
4470   "map": {"at": 165308, "to": "mm"},
4471   "name": "PA_CL_UCP_0_X",
4472   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4473  },
4474  {
4475   "chips": ["gfx81"],
4476   "map": {"at": 165312, "to": "mm"},
4477   "name": "PA_CL_UCP_0_Y",
4478   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4479  },
4480  {
4481   "chips": ["gfx81"],
4482   "map": {"at": 165316, "to": "mm"},
4483   "name": "PA_CL_UCP_0_Z",
4484   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4485  },
4486  {
4487   "chips": ["gfx81"],
4488   "map": {"at": 165320, "to": "mm"},
4489   "name": "PA_CL_UCP_0_W",
4490   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4491  },
4492  {
4493   "chips": ["gfx81"],
4494   "map": {"at": 165324, "to": "mm"},
4495   "name": "PA_CL_UCP_1_X",
4496   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4497  },
4498  {
4499   "chips": ["gfx81"],
4500   "map": {"at": 165328, "to": "mm"},
4501   "name": "PA_CL_UCP_1_Y",
4502   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4503  },
4504  {
4505   "chips": ["gfx81"],
4506   "map": {"at": 165332, "to": "mm"},
4507   "name": "PA_CL_UCP_1_Z",
4508   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4509  },
4510  {
4511   "chips": ["gfx81"],
4512   "map": {"at": 165336, "to": "mm"},
4513   "name": "PA_CL_UCP_1_W",
4514   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4515  },
4516  {
4517   "chips": ["gfx81"],
4518   "map": {"at": 165340, "to": "mm"},
4519   "name": "PA_CL_UCP_2_X",
4520   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4521  },
4522  {
4523   "chips": ["gfx81"],
4524   "map": {"at": 165344, "to": "mm"},
4525   "name": "PA_CL_UCP_2_Y",
4526   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4527  },
4528  {
4529   "chips": ["gfx81"],
4530   "map": {"at": 165348, "to": "mm"},
4531   "name": "PA_CL_UCP_2_Z",
4532   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4533  },
4534  {
4535   "chips": ["gfx81"],
4536   "map": {"at": 165352, "to": "mm"},
4537   "name": "PA_CL_UCP_2_W",
4538   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4539  },
4540  {
4541   "chips": ["gfx81"],
4542   "map": {"at": 165356, "to": "mm"},
4543   "name": "PA_CL_UCP_3_X",
4544   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4545  },
4546  {
4547   "chips": ["gfx81"],
4548   "map": {"at": 165360, "to": "mm"},
4549   "name": "PA_CL_UCP_3_Y",
4550   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4551  },
4552  {
4553   "chips": ["gfx81"],
4554   "map": {"at": 165364, "to": "mm"},
4555   "name": "PA_CL_UCP_3_Z",
4556   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4557  },
4558  {
4559   "chips": ["gfx81"],
4560   "map": {"at": 165368, "to": "mm"},
4561   "name": "PA_CL_UCP_3_W",
4562   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4563  },
4564  {
4565   "chips": ["gfx81"],
4566   "map": {"at": 165372, "to": "mm"},
4567   "name": "PA_CL_UCP_4_X",
4568   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4569  },
4570  {
4571   "chips": ["gfx81"],
4572   "map": {"at": 165376, "to": "mm"},
4573   "name": "PA_CL_UCP_4_Y",
4574   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4575  },
4576  {
4577   "chips": ["gfx81"],
4578   "map": {"at": 165380, "to": "mm"},
4579   "name": "PA_CL_UCP_4_Z",
4580   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4581  },
4582  {
4583   "chips": ["gfx81"],
4584   "map": {"at": 165384, "to": "mm"},
4585   "name": "PA_CL_UCP_4_W",
4586   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4587  },
4588  {
4589   "chips": ["gfx81"],
4590   "map": {"at": 165388, "to": "mm"},
4591   "name": "PA_CL_UCP_5_X",
4592   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4593  },
4594  {
4595   "chips": ["gfx81"],
4596   "map": {"at": 165392, "to": "mm"},
4597   "name": "PA_CL_UCP_5_Y",
4598   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4599  },
4600  {
4601   "chips": ["gfx81"],
4602   "map": {"at": 165396, "to": "mm"},
4603   "name": "PA_CL_UCP_5_Z",
4604   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4605  },
4606  {
4607   "chips": ["gfx81"],
4608   "map": {"at": 165400, "to": "mm"},
4609   "name": "PA_CL_UCP_5_W",
4610   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4611  },
4612  {
4613   "chips": ["gfx81"],
4614   "map": {"at": 165444, "to": "mm"},
4615   "name": "SPI_PS_INPUT_CNTL_0",
4616   "type_ref": "SPI_PS_INPUT_CNTL_0"
4617  },
4618  {
4619   "chips": ["gfx81"],
4620   "map": {"at": 165448, "to": "mm"},
4621   "name": "SPI_PS_INPUT_CNTL_1",
4622   "type_ref": "SPI_PS_INPUT_CNTL_0"
4623  },
4624  {
4625   "chips": ["gfx81"],
4626   "map": {"at": 165452, "to": "mm"},
4627   "name": "SPI_PS_INPUT_CNTL_2",
4628   "type_ref": "SPI_PS_INPUT_CNTL_0"
4629  },
4630  {
4631   "chips": ["gfx81"],
4632   "map": {"at": 165456, "to": "mm"},
4633   "name": "SPI_PS_INPUT_CNTL_3",
4634   "type_ref": "SPI_PS_INPUT_CNTL_0"
4635  },
4636  {
4637   "chips": ["gfx81"],
4638   "map": {"at": 165460, "to": "mm"},
4639   "name": "SPI_PS_INPUT_CNTL_4",
4640   "type_ref": "SPI_PS_INPUT_CNTL_0"
4641  },
4642  {
4643   "chips": ["gfx81"],
4644   "map": {"at": 165464, "to": "mm"},
4645   "name": "SPI_PS_INPUT_CNTL_5",
4646   "type_ref": "SPI_PS_INPUT_CNTL_0"
4647  },
4648  {
4649   "chips": ["gfx81"],
4650   "map": {"at": 165468, "to": "mm"},
4651   "name": "SPI_PS_INPUT_CNTL_6",
4652   "type_ref": "SPI_PS_INPUT_CNTL_0"
4653  },
4654  {
4655   "chips": ["gfx81"],
4656   "map": {"at": 165472, "to": "mm"},
4657   "name": "SPI_PS_INPUT_CNTL_7",
4658   "type_ref": "SPI_PS_INPUT_CNTL_0"
4659  },
4660  {
4661   "chips": ["gfx81"],
4662   "map": {"at": 165476, "to": "mm"},
4663   "name": "SPI_PS_INPUT_CNTL_8",
4664   "type_ref": "SPI_PS_INPUT_CNTL_0"
4665  },
4666  {
4667   "chips": ["gfx81"],
4668   "map": {"at": 165480, "to": "mm"},
4669   "name": "SPI_PS_INPUT_CNTL_9",
4670   "type_ref": "SPI_PS_INPUT_CNTL_0"
4671  },
4672  {
4673   "chips": ["gfx81"],
4674   "map": {"at": 165484, "to": "mm"},
4675   "name": "SPI_PS_INPUT_CNTL_10",
4676   "type_ref": "SPI_PS_INPUT_CNTL_0"
4677  },
4678  {
4679   "chips": ["gfx81"],
4680   "map": {"at": 165488, "to": "mm"},
4681   "name": "SPI_PS_INPUT_CNTL_11",
4682   "type_ref": "SPI_PS_INPUT_CNTL_0"
4683  },
4684  {
4685   "chips": ["gfx81"],
4686   "map": {"at": 165492, "to": "mm"},
4687   "name": "SPI_PS_INPUT_CNTL_12",
4688   "type_ref": "SPI_PS_INPUT_CNTL_0"
4689  },
4690  {
4691   "chips": ["gfx81"],
4692   "map": {"at": 165496, "to": "mm"},
4693   "name": "SPI_PS_INPUT_CNTL_13",
4694   "type_ref": "SPI_PS_INPUT_CNTL_0"
4695  },
4696  {
4697   "chips": ["gfx81"],
4698   "map": {"at": 165500, "to": "mm"},
4699   "name": "SPI_PS_INPUT_CNTL_14",
4700   "type_ref": "SPI_PS_INPUT_CNTL_0"
4701  },
4702  {
4703   "chips": ["gfx81"],
4704   "map": {"at": 165504, "to": "mm"},
4705   "name": "SPI_PS_INPUT_CNTL_15",
4706   "type_ref": "SPI_PS_INPUT_CNTL_0"
4707  },
4708  {
4709   "chips": ["gfx81"],
4710   "map": {"at": 165508, "to": "mm"},
4711   "name": "SPI_PS_INPUT_CNTL_16",
4712   "type_ref": "SPI_PS_INPUT_CNTL_0"
4713  },
4714  {
4715   "chips": ["gfx81"],
4716   "map": {"at": 165512, "to": "mm"},
4717   "name": "SPI_PS_INPUT_CNTL_17",
4718   "type_ref": "SPI_PS_INPUT_CNTL_0"
4719  },
4720  {
4721   "chips": ["gfx81"],
4722   "map": {"at": 165516, "to": "mm"},
4723   "name": "SPI_PS_INPUT_CNTL_18",
4724   "type_ref": "SPI_PS_INPUT_CNTL_0"
4725  },
4726  {
4727   "chips": ["gfx81"],
4728   "map": {"at": 165520, "to": "mm"},
4729   "name": "SPI_PS_INPUT_CNTL_19",
4730   "type_ref": "SPI_PS_INPUT_CNTL_0"
4731  },
4732  {
4733   "chips": ["gfx81"],
4734   "map": {"at": 165524, "to": "mm"},
4735   "name": "SPI_PS_INPUT_CNTL_20",
4736   "type_ref": "SPI_PS_INPUT_CNTL_20"
4737  },
4738  {
4739   "chips": ["gfx81"],
4740   "map": {"at": 165528, "to": "mm"},
4741   "name": "SPI_PS_INPUT_CNTL_21",
4742   "type_ref": "SPI_PS_INPUT_CNTL_20"
4743  },
4744  {
4745   "chips": ["gfx81"],
4746   "map": {"at": 165532, "to": "mm"},
4747   "name": "SPI_PS_INPUT_CNTL_22",
4748   "type_ref": "SPI_PS_INPUT_CNTL_20"
4749  },
4750  {
4751   "chips": ["gfx81"],
4752   "map": {"at": 165536, "to": "mm"},
4753   "name": "SPI_PS_INPUT_CNTL_23",
4754   "type_ref": "SPI_PS_INPUT_CNTL_20"
4755  },
4756  {
4757   "chips": ["gfx81"],
4758   "map": {"at": 165540, "to": "mm"},
4759   "name": "SPI_PS_INPUT_CNTL_24",
4760   "type_ref": "SPI_PS_INPUT_CNTL_20"
4761  },
4762  {
4763   "chips": ["gfx81"],
4764   "map": {"at": 165544, "to": "mm"},
4765   "name": "SPI_PS_INPUT_CNTL_25",
4766   "type_ref": "SPI_PS_INPUT_CNTL_20"
4767  },
4768  {
4769   "chips": ["gfx81"],
4770   "map": {"at": 165548, "to": "mm"},
4771   "name": "SPI_PS_INPUT_CNTL_26",
4772   "type_ref": "SPI_PS_INPUT_CNTL_20"
4773  },
4774  {
4775   "chips": ["gfx81"],
4776   "map": {"at": 165552, "to": "mm"},
4777   "name": "SPI_PS_INPUT_CNTL_27",
4778   "type_ref": "SPI_PS_INPUT_CNTL_20"
4779  },
4780  {
4781   "chips": ["gfx81"],
4782   "map": {"at": 165556, "to": "mm"},
4783   "name": "SPI_PS_INPUT_CNTL_28",
4784   "type_ref": "SPI_PS_INPUT_CNTL_20"
4785  },
4786  {
4787   "chips": ["gfx81"],
4788   "map": {"at": 165560, "to": "mm"},
4789   "name": "SPI_PS_INPUT_CNTL_29",
4790   "type_ref": "SPI_PS_INPUT_CNTL_20"
4791  },
4792  {
4793   "chips": ["gfx81"],
4794   "map": {"at": 165564, "to": "mm"},
4795   "name": "SPI_PS_INPUT_CNTL_30",
4796   "type_ref": "SPI_PS_INPUT_CNTL_20"
4797  },
4798  {
4799   "chips": ["gfx81"],
4800   "map": {"at": 165568, "to": "mm"},
4801   "name": "SPI_PS_INPUT_CNTL_31",
4802   "type_ref": "SPI_PS_INPUT_CNTL_20"
4803  },
4804  {
4805   "chips": ["gfx81"],
4806   "map": {"at": 165572, "to": "mm"},
4807   "name": "SPI_VS_OUT_CONFIG",
4808   "type_ref": "SPI_VS_OUT_CONFIG"
4809  },
4810  {
4811   "chips": ["gfx81"],
4812   "map": {"at": 165580, "to": "mm"},
4813   "name": "SPI_PS_INPUT_ENA",
4814   "type_ref": "SPI_PS_INPUT_ENA"
4815  },
4816  {
4817   "chips": ["gfx81"],
4818   "map": {"at": 165584, "to": "mm"},
4819   "name": "SPI_PS_INPUT_ADDR",
4820   "type_ref": "SPI_PS_INPUT_ENA"
4821  },
4822  {
4823   "chips": ["gfx81"],
4824   "map": {"at": 165588, "to": "mm"},
4825   "name": "SPI_INTERP_CONTROL_0",
4826   "type_ref": "SPI_INTERP_CONTROL_0"
4827  },
4828  {
4829   "chips": ["gfx81"],
4830   "map": {"at": 165592, "to": "mm"},
4831   "name": "SPI_PS_IN_CONTROL",
4832   "type_ref": "SPI_PS_IN_CONTROL"
4833  },
4834  {
4835   "chips": ["gfx81"],
4836   "map": {"at": 165600, "to": "mm"},
4837   "name": "SPI_BARYC_CNTL",
4838   "type_ref": "SPI_BARYC_CNTL"
4839  },
4840  {
4841   "chips": ["gfx81"],
4842   "map": {"at": 165608, "to": "mm"},
4843   "name": "SPI_TMPRING_SIZE",
4844   "type_ref": "COMPUTE_TMPRING_SIZE"
4845  },
4846  {
4847   "chips": ["gfx81"],
4848   "map": {"at": 165644, "to": "mm"},
4849   "name": "SPI_SHADER_POS_FORMAT",
4850   "type_ref": "SPI_SHADER_POS_FORMAT"
4851  },
4852  {
4853   "chips": ["gfx81"],
4854   "map": {"at": 165648, "to": "mm"},
4855   "name": "SPI_SHADER_Z_FORMAT",
4856   "type_ref": "SPI_SHADER_Z_FORMAT"
4857  },
4858  {
4859   "chips": ["gfx81"],
4860   "map": {"at": 165652, "to": "mm"},
4861   "name": "SPI_SHADER_COL_FORMAT",
4862   "type_ref": "SPI_SHADER_COL_FORMAT"
4863  },
4864  {
4865   "chips": ["gfx81"],
4866   "map": {"at": 165716, "to": "mm"},
4867   "name": "SX_PS_DOWNCONVERT",
4868   "type_ref": "SX_PS_DOWNCONVERT"
4869  },
4870  {
4871   "chips": ["gfx81"],
4872   "map": {"at": 165720, "to": "mm"},
4873   "name": "SX_BLEND_OPT_EPSILON",
4874   "type_ref": "SX_BLEND_OPT_EPSILON"
4875  },
4876  {
4877   "chips": ["gfx81"],
4878   "map": {"at": 165724, "to": "mm"},
4879   "name": "SX_BLEND_OPT_CONTROL",
4880   "type_ref": "SX_BLEND_OPT_CONTROL"
4881  },
4882  {
4883   "chips": ["gfx81"],
4884   "map": {"at": 165728, "to": "mm"},
4885   "name": "SX_MRT0_BLEND_OPT",
4886   "type_ref": "SX_MRT0_BLEND_OPT"
4887  },
4888  {
4889   "chips": ["gfx81"],
4890   "map": {"at": 165732, "to": "mm"},
4891   "name": "SX_MRT1_BLEND_OPT",
4892   "type_ref": "SX_MRT0_BLEND_OPT"
4893  },
4894  {
4895   "chips": ["gfx81"],
4896   "map": {"at": 165736, "to": "mm"},
4897   "name": "SX_MRT2_BLEND_OPT",
4898   "type_ref": "SX_MRT0_BLEND_OPT"
4899  },
4900  {
4901   "chips": ["gfx81"],
4902   "map": {"at": 165740, "to": "mm"},
4903   "name": "SX_MRT3_BLEND_OPT",
4904   "type_ref": "SX_MRT0_BLEND_OPT"
4905  },
4906  {
4907   "chips": ["gfx81"],
4908   "map": {"at": 165744, "to": "mm"},
4909   "name": "SX_MRT4_BLEND_OPT",
4910   "type_ref": "SX_MRT0_BLEND_OPT"
4911  },
4912  {
4913   "chips": ["gfx81"],
4914   "map": {"at": 165748, "to": "mm"},
4915   "name": "SX_MRT5_BLEND_OPT",
4916   "type_ref": "SX_MRT0_BLEND_OPT"
4917  },
4918  {
4919   "chips": ["gfx81"],
4920   "map": {"at": 165752, "to": "mm"},
4921   "name": "SX_MRT6_BLEND_OPT",
4922   "type_ref": "SX_MRT0_BLEND_OPT"
4923  },
4924  {
4925   "chips": ["gfx81"],
4926   "map": {"at": 165756, "to": "mm"},
4927   "name": "SX_MRT7_BLEND_OPT",
4928   "type_ref": "SX_MRT0_BLEND_OPT"
4929  },
4930  {
4931   "chips": ["gfx81"],
4932   "map": {"at": 165760, "to": "mm"},
4933   "name": "CB_BLEND0_CONTROL",
4934   "type_ref": "CB_BLEND0_CONTROL"
4935  },
4936  {
4937   "chips": ["gfx81"],
4938   "map": {"at": 165764, "to": "mm"},
4939   "name": "CB_BLEND1_CONTROL",
4940   "type_ref": "CB_BLEND0_CONTROL"
4941  },
4942  {
4943   "chips": ["gfx81"],
4944   "map": {"at": 165768, "to": "mm"},
4945   "name": "CB_BLEND2_CONTROL",
4946   "type_ref": "CB_BLEND0_CONTROL"
4947  },
4948  {
4949   "chips": ["gfx81"],
4950   "map": {"at": 165772, "to": "mm"},
4951   "name": "CB_BLEND3_CONTROL",
4952   "type_ref": "CB_BLEND0_CONTROL"
4953  },
4954  {
4955   "chips": ["gfx81"],
4956   "map": {"at": 165776, "to": "mm"},
4957   "name": "CB_BLEND4_CONTROL",
4958   "type_ref": "CB_BLEND0_CONTROL"
4959  },
4960  {
4961   "chips": ["gfx81"],
4962   "map": {"at": 165780, "to": "mm"},
4963   "name": "CB_BLEND5_CONTROL",
4964   "type_ref": "CB_BLEND0_CONTROL"
4965  },
4966  {
4967   "chips": ["gfx81"],
4968   "map": {"at": 165784, "to": "mm"},
4969   "name": "CB_BLEND6_CONTROL",
4970   "type_ref": "CB_BLEND0_CONTROL"
4971  },
4972  {
4973   "chips": ["gfx81"],
4974   "map": {"at": 165788, "to": "mm"},
4975   "name": "CB_BLEND7_CONTROL",
4976   "type_ref": "CB_BLEND0_CONTROL"
4977  },
4978  {
4979   "chips": ["gfx81"],
4980   "map": {"at": 165836, "to": "mm"},
4981   "name": "CS_COPY_STATE",
4982   "type_ref": "CS_COPY_STATE"
4983  },
4984  {
4985   "chips": ["gfx81"],
4986   "map": {"at": 165840, "to": "mm"},
4987   "name": "GFX_COPY_STATE",
4988   "type_ref": "CS_COPY_STATE"
4989  },
4990  {
4991   "chips": ["gfx81"],
4992   "map": {"at": 165844, "to": "mm"},
4993   "name": "PA_CL_POINT_X_RAD",
4994   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
4995  },
4996  {
4997   "chips": ["gfx81"],
4998   "map": {"at": 165848, "to": "mm"},
4999   "name": "PA_CL_POINT_Y_RAD",
5000   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5001  },
5002  {
5003   "chips": ["gfx81"],
5004   "map": {"at": 165852, "to": "mm"},
5005   "name": "PA_CL_POINT_SIZE",
5006   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5007  },
5008  {
5009   "chips": ["gfx81"],
5010   "map": {"at": 165856, "to": "mm"},
5011   "name": "PA_CL_POINT_CULL_RAD",
5012   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5013  },
5014  {
5015   "chips": ["gfx81"],
5016   "map": {"at": 165860, "to": "mm"},
5017   "name": "VGT_DMA_BASE_HI",
5018   "type_ref": "VGT_DMA_BASE_HI"
5019  },
5020  {
5021   "chips": ["gfx81"],
5022   "map": {"at": 165864, "to": "mm"},
5023   "name": "VGT_DMA_BASE",
5024   "type_ref": "VGT_DMA_BASE"
5025  },
5026  {
5027   "chips": ["gfx81"],
5028   "map": {"at": 165872, "to": "mm"},
5029   "name": "VGT_DRAW_INITIATOR",
5030   "type_ref": "VGT_DRAW_INITIATOR"
5031  },
5032  {
5033   "chips": ["gfx81"],
5034   "map": {"at": 165876, "to": "mm"},
5035   "name": "VGT_IMMED_DATA",
5036   "type_ref": "CP_APPEND_DATA"
5037  },
5038  {
5039   "chips": ["gfx81"],
5040   "map": {"at": 165880, "to": "mm"},
5041   "name": "VGT_EVENT_ADDRESS_REG",
5042   "type_ref": "VGT_EVENT_ADDRESS_REG"
5043  },
5044  {
5045   "chips": ["gfx81"],
5046   "map": {"at": 165888, "to": "mm"},
5047   "name": "DB_DEPTH_CONTROL",
5048   "type_ref": "DB_DEPTH_CONTROL"
5049  },
5050  {
5051   "chips": ["gfx81"],
5052   "map": {"at": 165892, "to": "mm"},
5053   "name": "DB_EQAA",
5054   "type_ref": "DB_EQAA"
5055  },
5056  {
5057   "chips": ["gfx81"],
5058   "map": {"at": 165896, "to": "mm"},
5059   "name": "CB_COLOR_CONTROL",
5060   "type_ref": "CB_COLOR_CONTROL"
5061  },
5062  {
5063   "chips": ["gfx81"],
5064   "map": {"at": 165900, "to": "mm"},
5065   "name": "DB_SHADER_CONTROL",
5066   "type_ref": "DB_SHADER_CONTROL"
5067  },
5068  {
5069   "chips": ["gfx81"],
5070   "map": {"at": 165904, "to": "mm"},
5071   "name": "PA_CL_CLIP_CNTL",
5072   "type_ref": "PA_CL_CLIP_CNTL"
5073  },
5074  {
5075   "chips": ["gfx81"],
5076   "map": {"at": 165908, "to": "mm"},
5077   "name": "PA_SU_SC_MODE_CNTL",
5078   "type_ref": "PA_SU_SC_MODE_CNTL"
5079  },
5080  {
5081   "chips": ["gfx81"],
5082   "map": {"at": 165912, "to": "mm"},
5083   "name": "PA_CL_VTE_CNTL",
5084   "type_ref": "PA_CL_VTE_CNTL"
5085  },
5086  {
5087   "chips": ["gfx81"],
5088   "map": {"at": 165916, "to": "mm"},
5089   "name": "PA_CL_VS_OUT_CNTL",
5090   "type_ref": "PA_CL_VS_OUT_CNTL"
5091  },
5092  {
5093   "chips": ["gfx81"],
5094   "map": {"at": 165920, "to": "mm"},
5095   "name": "PA_CL_NANINF_CNTL",
5096   "type_ref": "PA_CL_NANINF_CNTL"
5097  },
5098  {
5099   "chips": ["gfx81"],
5100   "map": {"at": 165924, "to": "mm"},
5101   "name": "PA_SU_LINE_STIPPLE_CNTL",
5102   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
5103  },
5104  {
5105   "chips": ["gfx81"],
5106   "map": {"at": 165928, "to": "mm"},
5107   "name": "PA_SU_LINE_STIPPLE_SCALE",
5108   "type_ref": "PA_SU_LINE_STIPPLE_SCALE"
5109  },
5110  {
5111   "chips": ["gfx81"],
5112   "map": {"at": 165932, "to": "mm"},
5113   "name": "PA_SU_PRIM_FILTER_CNTL",
5114   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
5115  },
5116  {
5117   "chips": ["gfx81"],
5118   "map": {"at": 166400, "to": "mm"},
5119   "name": "PA_SU_POINT_SIZE",
5120   "type_ref": "PA_SU_POINT_SIZE"
5121  },
5122  {
5123   "chips": ["gfx81"],
5124   "map": {"at": 166404, "to": "mm"},
5125   "name": "PA_SU_POINT_MINMAX",
5126   "type_ref": "PA_SU_POINT_MINMAX"
5127  },
5128  {
5129   "chips": ["gfx81"],
5130   "map": {"at": 166408, "to": "mm"},
5131   "name": "PA_SU_LINE_CNTL",
5132   "type_ref": "PA_SU_LINE_CNTL"
5133  },
5134  {
5135   "chips": ["gfx81"],
5136   "map": {"at": 166412, "to": "mm"},
5137   "name": "PA_SC_LINE_STIPPLE",
5138   "type_ref": "PA_SC_LINE_STIPPLE"
5139  },
5140  {
5141   "chips": ["gfx81"],
5142   "map": {"at": 166416, "to": "mm"},
5143   "name": "VGT_OUTPUT_PATH_CNTL",
5144   "type_ref": "VGT_OUTPUT_PATH_CNTL"
5145  },
5146  {
5147   "chips": ["gfx81"],
5148   "map": {"at": 166420, "to": "mm"},
5149   "name": "VGT_HOS_CNTL",
5150   "type_ref": "VGT_HOS_CNTL"
5151  },
5152  {
5153   "chips": ["gfx81"],
5154   "map": {"at": 166424, "to": "mm"},
5155   "name": "VGT_HOS_MAX_TESS_LEVEL",
5156   "type_ref": "VGT_HOS_MAX_TESS_LEVEL"
5157  },
5158  {
5159   "chips": ["gfx81"],
5160   "map": {"at": 166428, "to": "mm"},
5161   "name": "VGT_HOS_MIN_TESS_LEVEL",
5162   "type_ref": "VGT_HOS_MIN_TESS_LEVEL"
5163  },
5164  {
5165   "chips": ["gfx81"],
5166   "map": {"at": 166432, "to": "mm"},
5167   "name": "VGT_HOS_REUSE_DEPTH",
5168   "type_ref": "VGT_HOS_REUSE_DEPTH"
5169  },
5170  {
5171   "chips": ["gfx81"],
5172   "map": {"at": 166436, "to": "mm"},
5173   "name": "VGT_GROUP_PRIM_TYPE",
5174   "type_ref": "VGT_GROUP_PRIM_TYPE"
5175  },
5176  {
5177   "chips": ["gfx81"],
5178   "map": {"at": 166440, "to": "mm"},
5179   "name": "VGT_GROUP_FIRST_DECR",
5180   "type_ref": "VGT_GROUP_FIRST_DECR"
5181  },
5182  {
5183   "chips": ["gfx81"],
5184   "map": {"at": 166444, "to": "mm"},
5185   "name": "VGT_GROUP_DECR",
5186   "type_ref": "VGT_GROUP_DECR"
5187  },
5188  {
5189   "chips": ["gfx81"],
5190   "map": {"at": 166448, "to": "mm"},
5191   "name": "VGT_GROUP_VECT_0_CNTL",
5192   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5193  },
5194  {
5195   "chips": ["gfx81"],
5196   "map": {"at": 166452, "to": "mm"},
5197   "name": "VGT_GROUP_VECT_1_CNTL",
5198   "type_ref": "VGT_GROUP_VECT_0_CNTL"
5199  },
5200  {
5201   "chips": ["gfx81"],
5202   "map": {"at": 166456, "to": "mm"},
5203   "name": "VGT_GROUP_VECT_0_FMT_CNTL",
5204   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5205  },
5206  {
5207   "chips": ["gfx81"],
5208   "map": {"at": 166460, "to": "mm"},
5209   "name": "VGT_GROUP_VECT_1_FMT_CNTL",
5210   "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
5211  },
5212  {
5213   "chips": ["gfx81"],
5214   "map": {"at": 166464, "to": "mm"},
5215   "name": "VGT_GS_MODE",
5216   "type_ref": "VGT_GS_MODE"
5217  },
5218  {
5219   "chips": ["gfx81"],
5220   "map": {"at": 166468, "to": "mm"},
5221   "name": "VGT_GS_ONCHIP_CNTL",
5222   "type_ref": "VGT_GS_ONCHIP_CNTL"
5223  },
5224  {
5225   "chips": ["gfx81"],
5226   "map": {"at": 166472, "to": "mm"},
5227   "name": "PA_SC_MODE_CNTL_0",
5228   "type_ref": "PA_SC_MODE_CNTL_0"
5229  },
5230  {
5231   "chips": ["gfx81"],
5232   "map": {"at": 166476, "to": "mm"},
5233   "name": "PA_SC_MODE_CNTL_1",
5234   "type_ref": "PA_SC_MODE_CNTL_1"
5235  },
5236  {
5237   "chips": ["gfx81"],
5238   "map": {"at": 166480, "to": "mm"},
5239   "name": "VGT_ENHANCE",
5240   "type_ref": "IA_ENHANCE"
5241  },
5242  {
5243   "chips": ["gfx81"],
5244   "map": {"at": 166484, "to": "mm"},
5245   "name": "VGT_GS_PER_ES",
5246   "type_ref": "VGT_GS_PER_ES"
5247  },
5248  {
5249   "chips": ["gfx81"],
5250   "map": {"at": 166488, "to": "mm"},
5251   "name": "VGT_ES_PER_GS",
5252   "type_ref": "VGT_ES_PER_GS"
5253  },
5254  {
5255   "chips": ["gfx81"],
5256   "map": {"at": 166492, "to": "mm"},
5257   "name": "VGT_GS_PER_VS",
5258   "type_ref": "VGT_GS_PER_VS"
5259  },
5260  {
5261   "chips": ["gfx81"],
5262   "map": {"at": 166496, "to": "mm"},
5263   "name": "VGT_GSVS_RING_OFFSET_1",
5264   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5265  },
5266  {
5267   "chips": ["gfx81"],
5268   "map": {"at": 166500, "to": "mm"},
5269   "name": "VGT_GSVS_RING_OFFSET_2",
5270   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5271  },
5272  {
5273   "chips": ["gfx81"],
5274   "map": {"at": 166504, "to": "mm"},
5275   "name": "VGT_GSVS_RING_OFFSET_3",
5276   "type_ref": "VGT_GSVS_RING_OFFSET_1"
5277  },
5278  {
5279   "chips": ["gfx81"],
5280   "map": {"at": 166508, "to": "mm"},
5281   "name": "VGT_GS_OUT_PRIM_TYPE",
5282   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
5283  },
5284  {
5285   "chips": ["gfx81"],
5286   "map": {"at": 166512, "to": "mm"},
5287   "name": "IA_ENHANCE",
5288   "type_ref": "IA_ENHANCE"
5289  },
5290  {
5291   "chips": ["gfx81"],
5292   "map": {"at": 166516, "to": "mm"},
5293   "name": "VGT_DMA_SIZE",
5294   "type_ref": "VGT_DMA_SIZE"
5295  },
5296  {
5297   "chips": ["gfx81"],
5298   "map": {"at": 166520, "to": "mm"},
5299   "name": "VGT_DMA_MAX_SIZE",
5300   "type_ref": "VGT_DMA_MAX_SIZE"
5301  },
5302  {
5303   "chips": ["gfx81"],
5304   "map": {"at": 166524, "to": "mm"},
5305   "name": "VGT_DMA_INDEX_TYPE",
5306   "type_ref": "VGT_DMA_INDEX_TYPE"
5307  },
5308  {
5309   "chips": ["gfx81"],
5310   "map": {"at": 166528, "to": "mm"},
5311   "name": "WD_ENHANCE",
5312   "type_ref": "IA_ENHANCE"
5313  },
5314  {
5315   "chips": ["gfx81"],
5316   "map": {"at": 166532, "to": "mm"},
5317   "name": "VGT_PRIMITIVEID_EN",
5318   "type_ref": "VGT_PRIMITIVEID_EN"
5319  },
5320  {
5321   "chips": ["gfx81"],
5322   "map": {"at": 166536, "to": "mm"},
5323   "name": "VGT_DMA_NUM_INSTANCES",
5324   "type_ref": "VGT_DMA_NUM_INSTANCES"
5325  },
5326  {
5327   "chips": ["gfx81"],
5328   "map": {"at": 166540, "to": "mm"},
5329   "name": "VGT_PRIMITIVEID_RESET",
5330   "type_ref": "VGT_PRIMITIVEID_RESET"
5331  },
5332  {
5333   "chips": ["gfx81"],
5334   "map": {"at": 166544, "to": "mm"},
5335   "name": "VGT_EVENT_INITIATOR",
5336   "type_ref": "VGT_EVENT_INITIATOR"
5337  },
5338  {
5339   "chips": ["gfx81"],
5340   "map": {"at": 166548, "to": "mm"},
5341   "name": "VGT_MULTI_PRIM_IB_RESET_EN",
5342   "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
5343  },
5344  {
5345   "chips": ["gfx81"],
5346   "map": {"at": 166560, "to": "mm"},
5347   "name": "VGT_INSTANCE_STEP_RATE_0",
5348   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5349  },
5350  {
5351   "chips": ["gfx81"],
5352   "map": {"at": 166564, "to": "mm"},
5353   "name": "VGT_INSTANCE_STEP_RATE_1",
5354   "type_ref": "VGT_INSTANCE_STEP_RATE_0"
5355  },
5356  {
5357   "chips": ["gfx81"],
5358   "map": {"at": 166568, "to": "mm"},
5359   "name": "IA_MULTI_VGT_PARAM",
5360   "type_ref": "IA_MULTI_VGT_PARAM"
5361  },
5362  {
5363   "chips": ["gfx81"],
5364   "map": {"at": 166572, "to": "mm"},
5365   "name": "VGT_ESGS_RING_ITEMSIZE",
5366   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5367  },
5368  {
5369   "chips": ["gfx81"],
5370   "map": {"at": 166576, "to": "mm"},
5371   "name": "VGT_GSVS_RING_ITEMSIZE",
5372   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5373  },
5374  {
5375   "chips": ["gfx81"],
5376   "map": {"at": 166580, "to": "mm"},
5377   "name": "VGT_REUSE_OFF",
5378   "type_ref": "VGT_REUSE_OFF"
5379  },
5380  {
5381   "chips": ["gfx81"],
5382   "map": {"at": 166584, "to": "mm"},
5383   "name": "VGT_VTX_CNT_EN",
5384   "type_ref": "VGT_VTX_CNT_EN"
5385  },
5386  {
5387   "chips": ["gfx81"],
5388   "map": {"at": 166588, "to": "mm"},
5389   "name": "DB_HTILE_SURFACE",
5390   "type_ref": "DB_HTILE_SURFACE"
5391  },
5392  {
5393   "chips": ["gfx81"],
5394   "map": {"at": 166592, "to": "mm"},
5395   "name": "DB_SRESULTS_COMPARE_STATE0",
5396   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
5397  },
5398  {
5399   "chips": ["gfx81"],
5400   "map": {"at": 166596, "to": "mm"},
5401   "name": "DB_SRESULTS_COMPARE_STATE1",
5402   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
5403  },
5404  {
5405   "chips": ["gfx81"],
5406   "map": {"at": 166600, "to": "mm"},
5407   "name": "DB_PRELOAD_CONTROL",
5408   "type_ref": "DB_PRELOAD_CONTROL"
5409  },
5410  {
5411   "chips": ["gfx81"],
5412   "map": {"at": 166608, "to": "mm"},
5413   "name": "VGT_STRMOUT_BUFFER_SIZE_0",
5414   "type_ref": "COMPUTE_DIM_X"
5415  },
5416  {
5417   "chips": ["gfx81"],
5418   "map": {"at": 166612, "to": "mm"},
5419   "name": "VGT_STRMOUT_VTX_STRIDE_0",
5420   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5421  },
5422  {
5423   "chips": ["gfx81"],
5424   "map": {"at": 166620, "to": "mm"},
5425   "name": "VGT_STRMOUT_BUFFER_OFFSET_0",
5426   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5427  },
5428  {
5429   "chips": ["gfx81"],
5430   "map": {"at": 166624, "to": "mm"},
5431   "name": "VGT_STRMOUT_BUFFER_SIZE_1",
5432   "type_ref": "COMPUTE_DIM_X"
5433  },
5434  {
5435   "chips": ["gfx81"],
5436   "map": {"at": 166628, "to": "mm"},
5437   "name": "VGT_STRMOUT_VTX_STRIDE_1",
5438   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5439  },
5440  {
5441   "chips": ["gfx81"],
5442   "map": {"at": 166636, "to": "mm"},
5443   "name": "VGT_STRMOUT_BUFFER_OFFSET_1",
5444   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5445  },
5446  {
5447   "chips": ["gfx81"],
5448   "map": {"at": 166640, "to": "mm"},
5449   "name": "VGT_STRMOUT_BUFFER_SIZE_2",
5450   "type_ref": "COMPUTE_DIM_X"
5451  },
5452  {
5453   "chips": ["gfx81"],
5454   "map": {"at": 166644, "to": "mm"},
5455   "name": "VGT_STRMOUT_VTX_STRIDE_2",
5456   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5457  },
5458  {
5459   "chips": ["gfx81"],
5460   "map": {"at": 166652, "to": "mm"},
5461   "name": "VGT_STRMOUT_BUFFER_OFFSET_2",
5462   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5463  },
5464  {
5465   "chips": ["gfx81"],
5466   "map": {"at": 166656, "to": "mm"},
5467   "name": "VGT_STRMOUT_BUFFER_SIZE_3",
5468   "type_ref": "COMPUTE_DIM_X"
5469  },
5470  {
5471   "chips": ["gfx81"],
5472   "map": {"at": 166660, "to": "mm"},
5473   "name": "VGT_STRMOUT_VTX_STRIDE_3",
5474   "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
5475  },
5476  {
5477   "chips": ["gfx81"],
5478   "map": {"at": 166668, "to": "mm"},
5479   "name": "VGT_STRMOUT_BUFFER_OFFSET_3",
5480   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5481  },
5482  {
5483   "chips": ["gfx81"],
5484   "map": {"at": 166696, "to": "mm"},
5485   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET",
5486   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5487  },
5488  {
5489   "chips": ["gfx81"],
5490   "map": {"at": 166700, "to": "mm"},
5491   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE",
5492   "type_ref": "COMPUTE_DIM_X"
5493  },
5494  {
5495   "chips": ["gfx81"],
5496   "map": {"at": 166704, "to": "mm"},
5497   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5498   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5499  },
5500  {
5501   "chips": ["gfx81"],
5502   "map": {"at": 166712, "to": "mm"},
5503   "name": "VGT_GS_MAX_VERT_OUT",
5504   "type_ref": "VGT_GS_MAX_VERT_OUT"
5505  },
5506  {
5507   "chips": ["gfx81"],
5508   "map": {"at": 166736, "to": "mm"},
5509   "name": "VGT_TESS_DISTRIBUTION",
5510   "type_ref": "VGT_TESS_DISTRIBUTION"
5511  },
5512  {
5513   "chips": ["gfx81"],
5514   "map": {"at": 166740, "to": "mm"},
5515   "name": "VGT_SHADER_STAGES_EN",
5516   "type_ref": "VGT_SHADER_STAGES_EN"
5517  },
5518  {
5519   "chips": ["gfx81"],
5520   "map": {"at": 166744, "to": "mm"},
5521   "name": "VGT_LS_HS_CONFIG",
5522   "type_ref": "VGT_LS_HS_CONFIG"
5523  },
5524  {
5525   "chips": ["gfx81"],
5526   "map": {"at": 166748, "to": "mm"},
5527   "name": "VGT_GS_VERT_ITEMSIZE",
5528   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5529  },
5530  {
5531   "chips": ["gfx81"],
5532   "map": {"at": 166752, "to": "mm"},
5533   "name": "VGT_GS_VERT_ITEMSIZE_1",
5534   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5535  },
5536  {
5537   "chips": ["gfx81"],
5538   "map": {"at": 166756, "to": "mm"},
5539   "name": "VGT_GS_VERT_ITEMSIZE_2",
5540   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5541  },
5542  {
5543   "chips": ["gfx81"],
5544   "map": {"at": 166760, "to": "mm"},
5545   "name": "VGT_GS_VERT_ITEMSIZE_3",
5546   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
5547  },
5548  {
5549   "chips": ["gfx81"],
5550   "map": {"at": 166764, "to": "mm"},
5551   "name": "VGT_TF_PARAM",
5552   "type_ref": "VGT_TF_PARAM"
5553  },
5554  {
5555   "chips": ["gfx81"],
5556   "map": {"at": 166768, "to": "mm"},
5557   "name": "DB_ALPHA_TO_MASK",
5558   "type_ref": "DB_ALPHA_TO_MASK"
5559  },
5560  {
5561   "chips": ["gfx81"],
5562   "map": {"at": 166772, "to": "mm"},
5563   "name": "VGT_DISPATCH_DRAW_INDEX",
5564   "type_ref": "VGT_DISPATCH_DRAW_INDEX"
5565  },
5566  {
5567   "chips": ["gfx81"],
5568   "map": {"at": 166776, "to": "mm"},
5569   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5570   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5571  },
5572  {
5573   "chips": ["gfx81"],
5574   "map": {"at": 166780, "to": "mm"},
5575   "name": "PA_SU_POLY_OFFSET_CLAMP",
5576   "type_ref": "PA_SU_POLY_OFFSET_CLAMP"
5577  },
5578  {
5579   "chips": ["gfx81"],
5580   "map": {"at": 166784, "to": "mm"},
5581   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE",
5582   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5583  },
5584  {
5585   "chips": ["gfx81"],
5586   "map": {"at": 166788, "to": "mm"},
5587   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET",
5588   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5589  },
5590  {
5591   "chips": ["gfx81"],
5592   "map": {"at": 166792, "to": "mm"},
5593   "name": "PA_SU_POLY_OFFSET_BACK_SCALE",
5594   "type_ref": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5595  },
5596  {
5597   "chips": ["gfx81"],
5598   "map": {"at": 166796, "to": "mm"},
5599   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET",
5600   "type_ref": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5601  },
5602  {
5603   "chips": ["gfx81"],
5604   "map": {"at": 166800, "to": "mm"},
5605   "name": "VGT_GS_INSTANCE_CNT",
5606   "type_ref": "VGT_GS_INSTANCE_CNT"
5607  },
5608  {
5609   "chips": ["gfx81"],
5610   "map": {"at": 166804, "to": "mm"},
5611   "name": "VGT_STRMOUT_CONFIG",
5612   "type_ref": "VGT_STRMOUT_CONFIG"
5613  },
5614  {
5615   "chips": ["gfx81"],
5616   "map": {"at": 166808, "to": "mm"},
5617   "name": "VGT_STRMOUT_BUFFER_CONFIG",
5618   "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
5619  },
5620  {
5621   "chips": ["gfx81"],
5622   "map": {"at": 166868, "to": "mm"},
5623   "name": "PA_SC_CENTROID_PRIORITY_0",
5624   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5625  },
5626  {
5627   "chips": ["gfx81"],
5628   "map": {"at": 166872, "to": "mm"},
5629   "name": "PA_SC_CENTROID_PRIORITY_1",
5630   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5631  },
5632  {
5633   "chips": ["gfx81"],
5634   "map": {"at": 166876, "to": "mm"},
5635   "name": "PA_SC_LINE_CNTL",
5636   "type_ref": "PA_SC_LINE_CNTL"
5637  },
5638  {
5639   "chips": ["gfx81"],
5640   "map": {"at": 166880, "to": "mm"},
5641   "name": "PA_SC_AA_CONFIG",
5642   "type_ref": "PA_SC_AA_CONFIG"
5643  },
5644  {
5645   "chips": ["gfx81"],
5646   "map": {"at": 166884, "to": "mm"},
5647   "name": "PA_SU_VTX_CNTL",
5648   "type_ref": "PA_SU_VTX_CNTL"
5649  },
5650  {
5651   "chips": ["gfx81"],
5652   "map": {"at": 166888, "to": "mm"},
5653   "name": "PA_CL_GB_VERT_CLIP_ADJ",
5654   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5655  },
5656  {
5657   "chips": ["gfx81"],
5658   "map": {"at": 166892, "to": "mm"},
5659   "name": "PA_CL_GB_VERT_DISC_ADJ",
5660   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5661  },
5662  {
5663   "chips": ["gfx81"],
5664   "map": {"at": 166896, "to": "mm"},
5665   "name": "PA_CL_GB_HORZ_CLIP_ADJ",
5666   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5667  },
5668  {
5669   "chips": ["gfx81"],
5670   "map": {"at": 166900, "to": "mm"},
5671   "name": "PA_CL_GB_HORZ_DISC_ADJ",
5672   "type_ref": "PA_CL_GB_VERT_CLIP_ADJ"
5673  },
5674  {
5675   "chips": ["gfx81"],
5676   "map": {"at": 166904, "to": "mm"},
5677   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5678   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5679  },
5680  {
5681   "chips": ["gfx81"],
5682   "map": {"at": 166908, "to": "mm"},
5683   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5684   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5685  },
5686  {
5687   "chips": ["gfx81"],
5688   "map": {"at": 166912, "to": "mm"},
5689   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5690   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5691  },
5692  {
5693   "chips": ["gfx81"],
5694   "map": {"at": 166916, "to": "mm"},
5695   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5696   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5697  },
5698  {
5699   "chips": ["gfx81"],
5700   "map": {"at": 166920, "to": "mm"},
5701   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5702   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5703  },
5704  {
5705   "chips": ["gfx81"],
5706   "map": {"at": 166924, "to": "mm"},
5707   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5708   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5709  },
5710  {
5711   "chips": ["gfx81"],
5712   "map": {"at": 166928, "to": "mm"},
5713   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5714   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5715  },
5716  {
5717   "chips": ["gfx81"],
5718   "map": {"at": 166932, "to": "mm"},
5719   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5720   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5721  },
5722  {
5723   "chips": ["gfx81"],
5724   "map": {"at": 166936, "to": "mm"},
5725   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5726   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5727  },
5728  {
5729   "chips": ["gfx81"],
5730   "map": {"at": 166940, "to": "mm"},
5731   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5732   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5733  },
5734  {
5735   "chips": ["gfx81"],
5736   "map": {"at": 166944, "to": "mm"},
5737   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5738   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5739  },
5740  {
5741   "chips": ["gfx81"],
5742   "map": {"at": 166948, "to": "mm"},
5743   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5744   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5745  },
5746  {
5747   "chips": ["gfx81"],
5748   "map": {"at": 166952, "to": "mm"},
5749   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5750   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5751  },
5752  {
5753   "chips": ["gfx81"],
5754   "map": {"at": 166956, "to": "mm"},
5755   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5756   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5757  },
5758  {
5759   "chips": ["gfx81"],
5760   "map": {"at": 166960, "to": "mm"},
5761   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5762   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5763  },
5764  {
5765   "chips": ["gfx81"],
5766   "map": {"at": 166964, "to": "mm"},
5767   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5768   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5769  },
5770  {
5771   "chips": ["gfx81"],
5772   "map": {"at": 166968, "to": "mm"},
5773   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5774   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5775  },
5776  {
5777   "chips": ["gfx81"],
5778   "map": {"at": 166972, "to": "mm"},
5779   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5780   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5781  },
5782  {
5783   "chips": ["gfx81"],
5784   "map": {"at": 166976, "to": "mm"},
5785   "name": "PA_SC_SHADER_CONTROL",
5786   "type_ref": "PA_SC_SHADER_CONTROL"
5787  },
5788  {
5789   "chips": ["gfx81"],
5790   "map": {"at": 167000, "to": "mm"},
5791   "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
5792   "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
5793  },
5794  {
5795   "chips": ["gfx81"],
5796   "map": {"at": 167004, "to": "mm"},
5797   "name": "VGT_OUT_DEALLOC_CNTL",
5798   "type_ref": "VGT_OUT_DEALLOC_CNTL"
5799  },
5800  {
5801   "chips": ["gfx81"],
5802   "map": {"at": 167008, "to": "mm"},
5803   "name": "CB_COLOR0_BASE",
5804   "type_ref": "CB_COLOR0_BASE"
5805  },
5806  {
5807   "chips": ["gfx81"],
5808   "map": {"at": 167012, "to": "mm"},
5809   "name": "CB_COLOR0_PITCH",
5810   "type_ref": "CB_COLOR0_PITCH"
5811  },
5812  {
5813   "chips": ["gfx81"],
5814   "map": {"at": 167016, "to": "mm"},
5815   "name": "CB_COLOR0_SLICE",
5816   "type_ref": "CB_COLOR0_SLICE"
5817  },
5818  {
5819   "chips": ["gfx81"],
5820   "map": {"at": 167020, "to": "mm"},
5821   "name": "CB_COLOR0_VIEW",
5822   "type_ref": "CB_COLOR0_VIEW"
5823  },
5824  {
5825   "chips": ["gfx81"],
5826   "map": {"at": 167024, "to": "mm"},
5827   "name": "CB_COLOR0_INFO",
5828   "type_ref": "CB_COLOR0_INFO"
5829  },
5830  {
5831   "chips": ["gfx81"],
5832   "map": {"at": 167028, "to": "mm"},
5833   "name": "CB_COLOR0_ATTRIB",
5834   "type_ref": "CB_COLOR0_ATTRIB"
5835  },
5836  {
5837   "chips": ["gfx81"],
5838   "map": {"at": 167032, "to": "mm"},
5839   "name": "CB_COLOR0_DCC_CONTROL",
5840   "type_ref": "CB_COLOR0_DCC_CONTROL"
5841  },
5842  {
5843   "chips": ["gfx81"],
5844   "map": {"at": 167036, "to": "mm"},
5845   "name": "CB_COLOR0_CMASK",
5846   "type_ref": "CB_COLOR0_BASE"
5847  },
5848  {
5849   "chips": ["gfx81"],
5850   "map": {"at": 167040, "to": "mm"},
5851   "name": "CB_COLOR0_CMASK_SLICE",
5852   "type_ref": "CB_COLOR0_CMASK_SLICE"
5853  },
5854  {
5855   "chips": ["gfx81"],
5856   "map": {"at": 167044, "to": "mm"},
5857   "name": "CB_COLOR0_FMASK",
5858   "type_ref": "CB_COLOR0_BASE"
5859  },
5860  {
5861   "chips": ["gfx81"],
5862   "map": {"at": 167048, "to": "mm"},
5863   "name": "CB_COLOR0_FMASK_SLICE",
5864   "type_ref": "CB_COLOR0_SLICE"
5865  },
5866  {
5867   "chips": ["gfx81"],
5868   "map": {"at": 167052, "to": "mm"},
5869   "name": "CB_COLOR0_CLEAR_WORD0",
5870   "type_ref": "CB_COLOR0_CLEAR_WORD0"
5871  },
5872  {
5873   "chips": ["gfx81"],
5874   "map": {"at": 167056, "to": "mm"},
5875   "name": "CB_COLOR0_CLEAR_WORD1",
5876   "type_ref": "CB_COLOR0_CLEAR_WORD1"
5877  },
5878  {
5879   "chips": ["gfx81"],
5880   "map": {"at": 167060, "to": "mm"},
5881   "name": "CB_COLOR0_DCC_BASE",
5882   "type_ref": "CB_COLOR0_BASE"
5883  },
5884  {
5885   "chips": ["gfx81"],
5886   "map": {"at": 167068, "to": "mm"},
5887   "name": "CB_COLOR1_BASE",
5888   "type_ref": "CB_COLOR0_BASE"
5889  },
5890  {
5891   "chips": ["gfx81"],
5892   "map": {"at": 167072, "to": "mm"},
5893   "name": "CB_COLOR1_PITCH",
5894   "type_ref": "CB_COLOR0_PITCH"
5895  },
5896  {
5897   "chips": ["gfx81"],
5898   "map": {"at": 167076, "to": "mm"},
5899   "name": "CB_COLOR1_SLICE",
5900   "type_ref": "CB_COLOR0_SLICE"
5901  },
5902  {
5903   "chips": ["gfx81"],
5904   "map": {"at": 167080, "to": "mm"},
5905   "name": "CB_COLOR1_VIEW",
5906   "type_ref": "CB_COLOR0_VIEW"
5907  },
5908  {
5909   "chips": ["gfx81"],
5910   "map": {"at": 167084, "to": "mm"},
5911   "name": "CB_COLOR1_INFO",
5912   "type_ref": "CB_COLOR0_INFO"
5913  },
5914  {
5915   "chips": ["gfx81"],
5916   "map": {"at": 167088, "to": "mm"},
5917   "name": "CB_COLOR1_ATTRIB",
5918   "type_ref": "CB_COLOR0_ATTRIB"
5919  },
5920  {
5921   "chips": ["gfx81"],
5922   "map": {"at": 167092, "to": "mm"},
5923   "name": "CB_COLOR1_DCC_CONTROL",
5924   "type_ref": "CB_COLOR0_DCC_CONTROL"
5925  },
5926  {
5927   "chips": ["gfx81"],
5928   "map": {"at": 167096, "to": "mm"},
5929   "name": "CB_COLOR1_CMASK",
5930   "type_ref": "CB_COLOR0_BASE"
5931  },
5932  {
5933   "chips": ["gfx81"],
5934   "map": {"at": 167100, "to": "mm"},
5935   "name": "CB_COLOR1_CMASK_SLICE",
5936   "type_ref": "CB_COLOR0_CMASK_SLICE"
5937  },
5938  {
5939   "chips": ["gfx81"],
5940   "map": {"at": 167104, "to": "mm"},
5941   "name": "CB_COLOR1_FMASK",
5942   "type_ref": "CB_COLOR0_BASE"
5943  },
5944  {
5945   "chips": ["gfx81"],
5946   "map": {"at": 167108, "to": "mm"},
5947   "name": "CB_COLOR1_FMASK_SLICE",
5948   "type_ref": "CB_COLOR0_SLICE"
5949  },
5950  {
5951   "chips": ["gfx81"],
5952   "map": {"at": 167112, "to": "mm"},
5953   "name": "CB_COLOR1_CLEAR_WORD0",
5954   "type_ref": "CB_COLOR0_CLEAR_WORD0"
5955  },
5956  {
5957   "chips": ["gfx81"],
5958   "map": {"at": 167116, "to": "mm"},
5959   "name": "CB_COLOR1_CLEAR_WORD1",
5960   "type_ref": "CB_COLOR0_CLEAR_WORD1"
5961  },
5962  {
5963   "chips": ["gfx81"],
5964   "map": {"at": 167120, "to": "mm"},
5965   "name": "CB_COLOR1_DCC_BASE",
5966   "type_ref": "CB_COLOR0_BASE"
5967  },
5968  {
5969   "chips": ["gfx81"],
5970   "map": {"at": 167128, "to": "mm"},
5971   "name": "CB_COLOR2_BASE",
5972   "type_ref": "CB_COLOR0_BASE"
5973  },
5974  {
5975   "chips": ["gfx81"],
5976   "map": {"at": 167132, "to": "mm"},
5977   "name": "CB_COLOR2_PITCH",
5978   "type_ref": "CB_COLOR0_PITCH"
5979  },
5980  {
5981   "chips": ["gfx81"],
5982   "map": {"at": 167136, "to": "mm"},
5983   "name": "CB_COLOR2_SLICE",
5984   "type_ref": "CB_COLOR0_SLICE"
5985  },
5986  {
5987   "chips": ["gfx81"],
5988   "map": {"at": 167140, "to": "mm"},
5989   "name": "CB_COLOR2_VIEW",
5990   "type_ref": "CB_COLOR0_VIEW"
5991  },
5992  {
5993   "chips": ["gfx81"],
5994   "map": {"at": 167144, "to": "mm"},
5995   "name": "CB_COLOR2_INFO",
5996   "type_ref": "CB_COLOR0_INFO"
5997  },
5998  {
5999   "chips": ["gfx81"],
6000   "map": {"at": 167148, "to": "mm"},
6001   "name": "CB_COLOR2_ATTRIB",
6002   "type_ref": "CB_COLOR0_ATTRIB"
6003  },
6004  {
6005   "chips": ["gfx81"],
6006   "map": {"at": 167152, "to": "mm"},
6007   "name": "CB_COLOR2_DCC_CONTROL",
6008   "type_ref": "CB_COLOR0_DCC_CONTROL"
6009  },
6010  {
6011   "chips": ["gfx81"],
6012   "map": {"at": 167156, "to": "mm"},
6013   "name": "CB_COLOR2_CMASK",
6014   "type_ref": "CB_COLOR0_BASE"
6015  },
6016  {
6017   "chips": ["gfx81"],
6018   "map": {"at": 167160, "to": "mm"},
6019   "name": "CB_COLOR2_CMASK_SLICE",
6020   "type_ref": "CB_COLOR0_CMASK_SLICE"
6021  },
6022  {
6023   "chips": ["gfx81"],
6024   "map": {"at": 167164, "to": "mm"},
6025   "name": "CB_COLOR2_FMASK",
6026   "type_ref": "CB_COLOR0_BASE"
6027  },
6028  {
6029   "chips": ["gfx81"],
6030   "map": {"at": 167168, "to": "mm"},
6031   "name": "CB_COLOR2_FMASK_SLICE",
6032   "type_ref": "CB_COLOR0_SLICE"
6033  },
6034  {
6035   "chips": ["gfx81"],
6036   "map": {"at": 167172, "to": "mm"},
6037   "name": "CB_COLOR2_CLEAR_WORD0",
6038   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6039  },
6040  {
6041   "chips": ["gfx81"],
6042   "map": {"at": 167176, "to": "mm"},
6043   "name": "CB_COLOR2_CLEAR_WORD1",
6044   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6045  },
6046  {
6047   "chips": ["gfx81"],
6048   "map": {"at": 167180, "to": "mm"},
6049   "name": "CB_COLOR2_DCC_BASE",
6050   "type_ref": "CB_COLOR0_BASE"
6051  },
6052  {
6053   "chips": ["gfx81"],
6054   "map": {"at": 167188, "to": "mm"},
6055   "name": "CB_COLOR3_BASE",
6056   "type_ref": "CB_COLOR0_BASE"
6057  },
6058  {
6059   "chips": ["gfx81"],
6060   "map": {"at": 167192, "to": "mm"},
6061   "name": "CB_COLOR3_PITCH",
6062   "type_ref": "CB_COLOR0_PITCH"
6063  },
6064  {
6065   "chips": ["gfx81"],
6066   "map": {"at": 167196, "to": "mm"},
6067   "name": "CB_COLOR3_SLICE",
6068   "type_ref": "CB_COLOR0_SLICE"
6069  },
6070  {
6071   "chips": ["gfx81"],
6072   "map": {"at": 167200, "to": "mm"},
6073   "name": "CB_COLOR3_VIEW",
6074   "type_ref": "CB_COLOR0_VIEW"
6075  },
6076  {
6077   "chips": ["gfx81"],
6078   "map": {"at": 167204, "to": "mm"},
6079   "name": "CB_COLOR3_INFO",
6080   "type_ref": "CB_COLOR0_INFO"
6081  },
6082  {
6083   "chips": ["gfx81"],
6084   "map": {"at": 167208, "to": "mm"},
6085   "name": "CB_COLOR3_ATTRIB",
6086   "type_ref": "CB_COLOR0_ATTRIB"
6087  },
6088  {
6089   "chips": ["gfx81"],
6090   "map": {"at": 167212, "to": "mm"},
6091   "name": "CB_COLOR3_DCC_CONTROL",
6092   "type_ref": "CB_COLOR0_DCC_CONTROL"
6093  },
6094  {
6095   "chips": ["gfx81"],
6096   "map": {"at": 167216, "to": "mm"},
6097   "name": "CB_COLOR3_CMASK",
6098   "type_ref": "CB_COLOR0_BASE"
6099  },
6100  {
6101   "chips": ["gfx81"],
6102   "map": {"at": 167220, "to": "mm"},
6103   "name": "CB_COLOR3_CMASK_SLICE",
6104   "type_ref": "CB_COLOR0_CMASK_SLICE"
6105  },
6106  {
6107   "chips": ["gfx81"],
6108   "map": {"at": 167224, "to": "mm"},
6109   "name": "CB_COLOR3_FMASK",
6110   "type_ref": "CB_COLOR0_BASE"
6111  },
6112  {
6113   "chips": ["gfx81"],
6114   "map": {"at": 167228, "to": "mm"},
6115   "name": "CB_COLOR3_FMASK_SLICE",
6116   "type_ref": "CB_COLOR0_SLICE"
6117  },
6118  {
6119   "chips": ["gfx81"],
6120   "map": {"at": 167232, "to": "mm"},
6121   "name": "CB_COLOR3_CLEAR_WORD0",
6122   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6123  },
6124  {
6125   "chips": ["gfx81"],
6126   "map": {"at": 167236, "to": "mm"},
6127   "name": "CB_COLOR3_CLEAR_WORD1",
6128   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6129  },
6130  {
6131   "chips": ["gfx81"],
6132   "map": {"at": 167240, "to": "mm"},
6133   "name": "CB_COLOR3_DCC_BASE",
6134   "type_ref": "CB_COLOR0_BASE"
6135  },
6136  {
6137   "chips": ["gfx81"],
6138   "map": {"at": 167248, "to": "mm"},
6139   "name": "CB_COLOR4_BASE",
6140   "type_ref": "CB_COLOR0_BASE"
6141  },
6142  {
6143   "chips": ["gfx81"],
6144   "map": {"at": 167252, "to": "mm"},
6145   "name": "CB_COLOR4_PITCH",
6146   "type_ref": "CB_COLOR0_PITCH"
6147  },
6148  {
6149   "chips": ["gfx81"],
6150   "map": {"at": 167256, "to": "mm"},
6151   "name": "CB_COLOR4_SLICE",
6152   "type_ref": "CB_COLOR0_SLICE"
6153  },
6154  {
6155   "chips": ["gfx81"],
6156   "map": {"at": 167260, "to": "mm"},
6157   "name": "CB_COLOR4_VIEW",
6158   "type_ref": "CB_COLOR0_VIEW"
6159  },
6160  {
6161   "chips": ["gfx81"],
6162   "map": {"at": 167264, "to": "mm"},
6163   "name": "CB_COLOR4_INFO",
6164   "type_ref": "CB_COLOR0_INFO"
6165  },
6166  {
6167   "chips": ["gfx81"],
6168   "map": {"at": 167268, "to": "mm"},
6169   "name": "CB_COLOR4_ATTRIB",
6170   "type_ref": "CB_COLOR0_ATTRIB"
6171  },
6172  {
6173   "chips": ["gfx81"],
6174   "map": {"at": 167272, "to": "mm"},
6175   "name": "CB_COLOR4_DCC_CONTROL",
6176   "type_ref": "CB_COLOR0_DCC_CONTROL"
6177  },
6178  {
6179   "chips": ["gfx81"],
6180   "map": {"at": 167276, "to": "mm"},
6181   "name": "CB_COLOR4_CMASK",
6182   "type_ref": "CB_COLOR0_BASE"
6183  },
6184  {
6185   "chips": ["gfx81"],
6186   "map": {"at": 167280, "to": "mm"},
6187   "name": "CB_COLOR4_CMASK_SLICE",
6188   "type_ref": "CB_COLOR0_CMASK_SLICE"
6189  },
6190  {
6191   "chips": ["gfx81"],
6192   "map": {"at": 167284, "to": "mm"},
6193   "name": "CB_COLOR4_FMASK",
6194   "type_ref": "CB_COLOR0_BASE"
6195  },
6196  {
6197   "chips": ["gfx81"],
6198   "map": {"at": 167288, "to": "mm"},
6199   "name": "CB_COLOR4_FMASK_SLICE",
6200   "type_ref": "CB_COLOR0_SLICE"
6201  },
6202  {
6203   "chips": ["gfx81"],
6204   "map": {"at": 167292, "to": "mm"},
6205   "name": "CB_COLOR4_CLEAR_WORD0",
6206   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6207  },
6208  {
6209   "chips": ["gfx81"],
6210   "map": {"at": 167296, "to": "mm"},
6211   "name": "CB_COLOR4_CLEAR_WORD1",
6212   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6213  },
6214  {
6215   "chips": ["gfx81"],
6216   "map": {"at": 167300, "to": "mm"},
6217   "name": "CB_COLOR4_DCC_BASE",
6218   "type_ref": "CB_COLOR0_BASE"
6219  },
6220  {
6221   "chips": ["gfx81"],
6222   "map": {"at": 167308, "to": "mm"},
6223   "name": "CB_COLOR5_BASE",
6224   "type_ref": "CB_COLOR0_BASE"
6225  },
6226  {
6227   "chips": ["gfx81"],
6228   "map": {"at": 167312, "to": "mm"},
6229   "name": "CB_COLOR5_PITCH",
6230   "type_ref": "CB_COLOR0_PITCH"
6231  },
6232  {
6233   "chips": ["gfx81"],
6234   "map": {"at": 167316, "to": "mm"},
6235   "name": "CB_COLOR5_SLICE",
6236   "type_ref": "CB_COLOR0_SLICE"
6237  },
6238  {
6239   "chips": ["gfx81"],
6240   "map": {"at": 167320, "to": "mm"},
6241   "name": "CB_COLOR5_VIEW",
6242   "type_ref": "CB_COLOR0_VIEW"
6243  },
6244  {
6245   "chips": ["gfx81"],
6246   "map": {"at": 167324, "to": "mm"},
6247   "name": "CB_COLOR5_INFO",
6248   "type_ref": "CB_COLOR0_INFO"
6249  },
6250  {
6251   "chips": ["gfx81"],
6252   "map": {"at": 167328, "to": "mm"},
6253   "name": "CB_COLOR5_ATTRIB",
6254   "type_ref": "CB_COLOR0_ATTRIB"
6255  },
6256  {
6257   "chips": ["gfx81"],
6258   "map": {"at": 167332, "to": "mm"},
6259   "name": "CB_COLOR5_DCC_CONTROL",
6260   "type_ref": "CB_COLOR0_DCC_CONTROL"
6261  },
6262  {
6263   "chips": ["gfx81"],
6264   "map": {"at": 167336, "to": "mm"},
6265   "name": "CB_COLOR5_CMASK",
6266   "type_ref": "CB_COLOR0_BASE"
6267  },
6268  {
6269   "chips": ["gfx81"],
6270   "map": {"at": 167340, "to": "mm"},
6271   "name": "CB_COLOR5_CMASK_SLICE",
6272   "type_ref": "CB_COLOR0_CMASK_SLICE"
6273  },
6274  {
6275   "chips": ["gfx81"],
6276   "map": {"at": 167344, "to": "mm"},
6277   "name": "CB_COLOR5_FMASK",
6278   "type_ref": "CB_COLOR0_BASE"
6279  },
6280  {
6281   "chips": ["gfx81"],
6282   "map": {"at": 167348, "to": "mm"},
6283   "name": "CB_COLOR5_FMASK_SLICE",
6284   "type_ref": "CB_COLOR0_SLICE"
6285  },
6286  {
6287   "chips": ["gfx81"],
6288   "map": {"at": 167352, "to": "mm"},
6289   "name": "CB_COLOR5_CLEAR_WORD0",
6290   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6291  },
6292  {
6293   "chips": ["gfx81"],
6294   "map": {"at": 167356, "to": "mm"},
6295   "name": "CB_COLOR5_CLEAR_WORD1",
6296   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6297  },
6298  {
6299   "chips": ["gfx81"],
6300   "map": {"at": 167360, "to": "mm"},
6301   "name": "CB_COLOR5_DCC_BASE",
6302   "type_ref": "CB_COLOR0_BASE"
6303  },
6304  {
6305   "chips": ["gfx81"],
6306   "map": {"at": 167368, "to": "mm"},
6307   "name": "CB_COLOR6_BASE",
6308   "type_ref": "CB_COLOR0_BASE"
6309  },
6310  {
6311   "chips": ["gfx81"],
6312   "map": {"at": 167372, "to": "mm"},
6313   "name": "CB_COLOR6_PITCH",
6314   "type_ref": "CB_COLOR0_PITCH"
6315  },
6316  {
6317   "chips": ["gfx81"],
6318   "map": {"at": 167376, "to": "mm"},
6319   "name": "CB_COLOR6_SLICE",
6320   "type_ref": "CB_COLOR0_SLICE"
6321  },
6322  {
6323   "chips": ["gfx81"],
6324   "map": {"at": 167380, "to": "mm"},
6325   "name": "CB_COLOR6_VIEW",
6326   "type_ref": "CB_COLOR0_VIEW"
6327  },
6328  {
6329   "chips": ["gfx81"],
6330   "map": {"at": 167384, "to": "mm"},
6331   "name": "CB_COLOR6_INFO",
6332   "type_ref": "CB_COLOR0_INFO"
6333  },
6334  {
6335   "chips": ["gfx81"],
6336   "map": {"at": 167388, "to": "mm"},
6337   "name": "CB_COLOR6_ATTRIB",
6338   "type_ref": "CB_COLOR0_ATTRIB"
6339  },
6340  {
6341   "chips": ["gfx81"],
6342   "map": {"at": 167392, "to": "mm"},
6343   "name": "CB_COLOR6_DCC_CONTROL",
6344   "type_ref": "CB_COLOR0_DCC_CONTROL"
6345  },
6346  {
6347   "chips": ["gfx81"],
6348   "map": {"at": 167396, "to": "mm"},
6349   "name": "CB_COLOR6_CMASK",
6350   "type_ref": "CB_COLOR0_BASE"
6351  },
6352  {
6353   "chips": ["gfx81"],
6354   "map": {"at": 167400, "to": "mm"},
6355   "name": "CB_COLOR6_CMASK_SLICE",
6356   "type_ref": "CB_COLOR0_CMASK_SLICE"
6357  },
6358  {
6359   "chips": ["gfx81"],
6360   "map": {"at": 167404, "to": "mm"},
6361   "name": "CB_COLOR6_FMASK",
6362   "type_ref": "CB_COLOR0_BASE"
6363  },
6364  {
6365   "chips": ["gfx81"],
6366   "map": {"at": 167408, "to": "mm"},
6367   "name": "CB_COLOR6_FMASK_SLICE",
6368   "type_ref": "CB_COLOR0_SLICE"
6369  },
6370  {
6371   "chips": ["gfx81"],
6372   "map": {"at": 167412, "to": "mm"},
6373   "name": "CB_COLOR6_CLEAR_WORD0",
6374   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6375  },
6376  {
6377   "chips": ["gfx81"],
6378   "map": {"at": 167416, "to": "mm"},
6379   "name": "CB_COLOR6_CLEAR_WORD1",
6380   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6381  },
6382  {
6383   "chips": ["gfx81"],
6384   "map": {"at": 167420, "to": "mm"},
6385   "name": "CB_COLOR6_DCC_BASE",
6386   "type_ref": "CB_COLOR0_BASE"
6387  },
6388  {
6389   "chips": ["gfx81"],
6390   "map": {"at": 167428, "to": "mm"},
6391   "name": "CB_COLOR7_BASE",
6392   "type_ref": "CB_COLOR0_BASE"
6393  },
6394  {
6395   "chips": ["gfx81"],
6396   "map": {"at": 167432, "to": "mm"},
6397   "name": "CB_COLOR7_PITCH",
6398   "type_ref": "CB_COLOR0_PITCH"
6399  },
6400  {
6401   "chips": ["gfx81"],
6402   "map": {"at": 167436, "to": "mm"},
6403   "name": "CB_COLOR7_SLICE",
6404   "type_ref": "CB_COLOR0_SLICE"
6405  },
6406  {
6407   "chips": ["gfx81"],
6408   "map": {"at": 167440, "to": "mm"},
6409   "name": "CB_COLOR7_VIEW",
6410   "type_ref": "CB_COLOR0_VIEW"
6411  },
6412  {
6413   "chips": ["gfx81"],
6414   "map": {"at": 167444, "to": "mm"},
6415   "name": "CB_COLOR7_INFO",
6416   "type_ref": "CB_COLOR0_INFO"
6417  },
6418  {
6419   "chips": ["gfx81"],
6420   "map": {"at": 167448, "to": "mm"},
6421   "name": "CB_COLOR7_ATTRIB",
6422   "type_ref": "CB_COLOR0_ATTRIB"
6423  },
6424  {
6425   "chips": ["gfx81"],
6426   "map": {"at": 167452, "to": "mm"},
6427   "name": "CB_COLOR7_DCC_CONTROL",
6428   "type_ref": "CB_COLOR0_DCC_CONTROL"
6429  },
6430  {
6431   "chips": ["gfx81"],
6432   "map": {"at": 167456, "to": "mm"},
6433   "name": "CB_COLOR7_CMASK",
6434   "type_ref": "CB_COLOR0_BASE"
6435  },
6436  {
6437   "chips": ["gfx81"],
6438   "map": {"at": 167460, "to": "mm"},
6439   "name": "CB_COLOR7_CMASK_SLICE",
6440   "type_ref": "CB_COLOR0_CMASK_SLICE"
6441  },
6442  {
6443   "chips": ["gfx81"],
6444   "map": {"at": 167464, "to": "mm"},
6445   "name": "CB_COLOR7_FMASK",
6446   "type_ref": "CB_COLOR0_BASE"
6447  },
6448  {
6449   "chips": ["gfx81"],
6450   "map": {"at": 167468, "to": "mm"},
6451   "name": "CB_COLOR7_FMASK_SLICE",
6452   "type_ref": "CB_COLOR0_SLICE"
6453  },
6454  {
6455   "chips": ["gfx81"],
6456   "map": {"at": 167472, "to": "mm"},
6457   "name": "CB_COLOR7_CLEAR_WORD0",
6458   "type_ref": "CB_COLOR0_CLEAR_WORD0"
6459  },
6460  {
6461   "chips": ["gfx81"],
6462   "map": {"at": 167476, "to": "mm"},
6463   "name": "CB_COLOR7_CLEAR_WORD1",
6464   "type_ref": "CB_COLOR0_CLEAR_WORD1"
6465  },
6466  {
6467   "chips": ["gfx81"],
6468   "map": {"at": 167480, "to": "mm"},
6469   "name": "CB_COLOR7_DCC_BASE",
6470   "type_ref": "CB_COLOR0_BASE"
6471  },
6472  {
6473   "chips": ["gfx81"],
6474   "map": {"at": 196608, "to": "mm"},
6475   "name": "CP_EOP_DONE_ADDR_LO",
6476   "type_ref": "CP_EOP_DONE_ADDR_LO"
6477  },
6478  {
6479   "chips": ["gfx81"],
6480   "map": {"at": 196612, "to": "mm"},
6481   "name": "CP_EOP_DONE_ADDR_HI",
6482   "type_ref": "CP_EOP_DONE_ADDR_HI"
6483  },
6484  {
6485   "chips": ["gfx81"],
6486   "map": {"at": 196616, "to": "mm"},
6487   "name": "CP_EOP_DONE_DATA_LO",
6488   "type_ref": "CP_EOP_DONE_DATA_LO"
6489  },
6490  {
6491   "chips": ["gfx81"],
6492   "map": {"at": 196620, "to": "mm"},
6493   "name": "CP_EOP_DONE_DATA_HI",
6494   "type_ref": "CP_EOP_DONE_DATA_HI"
6495  },
6496  {
6497   "chips": ["gfx81"],
6498   "map": {"at": 196624, "to": "mm"},
6499   "name": "CP_EOP_LAST_FENCE_LO",
6500   "type_ref": "CP_EOP_LAST_FENCE_LO"
6501  },
6502  {
6503   "chips": ["gfx81"],
6504   "map": {"at": 196628, "to": "mm"},
6505   "name": "CP_EOP_LAST_FENCE_HI",
6506   "type_ref": "CP_EOP_LAST_FENCE_HI"
6507  },
6508  {
6509   "chips": ["gfx81"],
6510   "map": {"at": 196632, "to": "mm"},
6511   "name": "CP_STREAM_OUT_ADDR_LO",
6512   "type_ref": "CP_STREAM_OUT_ADDR_LO"
6513  },
6514  {
6515   "chips": ["gfx81"],
6516   "map": {"at": 196636, "to": "mm"},
6517   "name": "CP_STREAM_OUT_ADDR_HI",
6518   "type_ref": "CP_STREAM_OUT_ADDR_HI"
6519  },
6520  {
6521   "chips": ["gfx81"],
6522   "map": {"at": 196640, "to": "mm"},
6523   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO",
6524   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
6525  },
6526  {
6527   "chips": ["gfx81"],
6528   "map": {"at": 196644, "to": "mm"},
6529   "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI",
6530   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
6531  },
6532  {
6533   "chips": ["gfx81"],
6534   "map": {"at": 196648, "to": "mm"},
6535   "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO",
6536   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
6537  },
6538  {
6539   "chips": ["gfx81"],
6540   "map": {"at": 196652, "to": "mm"},
6541   "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI",
6542   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
6543  },
6544  {
6545   "chips": ["gfx81"],
6546   "map": {"at": 196656, "to": "mm"},
6547   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO",
6548   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
6549  },
6550  {
6551   "chips": ["gfx81"],
6552   "map": {"at": 196660, "to": "mm"},
6553   "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI",
6554   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
6555  },
6556  {
6557   "chips": ["gfx81"],
6558   "map": {"at": 196664, "to": "mm"},
6559   "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO",
6560   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
6561  },
6562  {
6563   "chips": ["gfx81"],
6564   "map": {"at": 196668, "to": "mm"},
6565   "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI",
6566   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
6567  },
6568  {
6569   "chips": ["gfx81"],
6570   "map": {"at": 196672, "to": "mm"},
6571   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO",
6572   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
6573  },
6574  {
6575   "chips": ["gfx81"],
6576   "map": {"at": 196676, "to": "mm"},
6577   "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI",
6578   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
6579  },
6580  {
6581   "chips": ["gfx81"],
6582   "map": {"at": 196680, "to": "mm"},
6583   "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO",
6584   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
6585  },
6586  {
6587   "chips": ["gfx81"],
6588   "map": {"at": 196684, "to": "mm"},
6589   "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI",
6590   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
6591  },
6592  {
6593   "chips": ["gfx81"],
6594   "map": {"at": 196688, "to": "mm"},
6595   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO",
6596   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
6597  },
6598  {
6599   "chips": ["gfx81"],
6600   "map": {"at": 196692, "to": "mm"},
6601   "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI",
6602   "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
6603  },
6604  {
6605   "chips": ["gfx81"],
6606   "map": {"at": 196696, "to": "mm"},
6607   "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO",
6608   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
6609  },
6610  {
6611   "chips": ["gfx81"],
6612   "map": {"at": 196700, "to": "mm"},
6613   "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI",
6614   "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
6615  },
6616  {
6617   "chips": ["gfx81"],
6618   "map": {"at": 196704, "to": "mm"},
6619   "name": "CP_PIPE_STATS_ADDR_LO",
6620   "type_ref": "CP_PIPE_STATS_ADDR_LO"
6621  },
6622  {
6623   "chips": ["gfx81"],
6624   "map": {"at": 196708, "to": "mm"},
6625   "name": "CP_PIPE_STATS_ADDR_HI",
6626   "type_ref": "CP_PIPE_STATS_ADDR_HI"
6627  },
6628  {
6629   "chips": ["gfx81"],
6630   "map": {"at": 196712, "to": "mm"},
6631   "name": "CP_VGT_IAVERT_COUNT_LO",
6632   "type_ref": "CP_VGT_IAVERT_COUNT_LO"
6633  },
6634  {
6635   "chips": ["gfx81"],
6636   "map": {"at": 196716, "to": "mm"},
6637   "name": "CP_VGT_IAVERT_COUNT_HI",
6638   "type_ref": "CP_VGT_IAVERT_COUNT_HI"
6639  },
6640  {
6641   "chips": ["gfx81"],
6642   "map": {"at": 196720, "to": "mm"},
6643   "name": "CP_VGT_IAPRIM_COUNT_LO",
6644   "type_ref": "CP_VGT_IAPRIM_COUNT_LO"
6645  },
6646  {
6647   "chips": ["gfx81"],
6648   "map": {"at": 196724, "to": "mm"},
6649   "name": "CP_VGT_IAPRIM_COUNT_HI",
6650   "type_ref": "CP_VGT_IAPRIM_COUNT_HI"
6651  },
6652  {
6653   "chips": ["gfx81"],
6654   "map": {"at": 196728, "to": "mm"},
6655   "name": "CP_VGT_GSPRIM_COUNT_LO",
6656   "type_ref": "CP_VGT_GSPRIM_COUNT_LO"
6657  },
6658  {
6659   "chips": ["gfx81"],
6660   "map": {"at": 196732, "to": "mm"},
6661   "name": "CP_VGT_GSPRIM_COUNT_HI",
6662   "type_ref": "CP_VGT_GSPRIM_COUNT_HI"
6663  },
6664  {
6665   "chips": ["gfx81"],
6666   "map": {"at": 196736, "to": "mm"},
6667   "name": "CP_VGT_VSINVOC_COUNT_LO",
6668   "type_ref": "CP_VGT_VSINVOC_COUNT_LO"
6669  },
6670  {
6671   "chips": ["gfx81"],
6672   "map": {"at": 196740, "to": "mm"},
6673   "name": "CP_VGT_VSINVOC_COUNT_HI",
6674   "type_ref": "CP_VGT_VSINVOC_COUNT_HI"
6675  },
6676  {
6677   "chips": ["gfx81"],
6678   "map": {"at": 196744, "to": "mm"},
6679   "name": "CP_VGT_GSINVOC_COUNT_LO",
6680   "type_ref": "CP_VGT_GSINVOC_COUNT_LO"
6681  },
6682  {
6683   "chips": ["gfx81"],
6684   "map": {"at": 196748, "to": "mm"},
6685   "name": "CP_VGT_GSINVOC_COUNT_HI",
6686   "type_ref": "CP_VGT_GSINVOC_COUNT_HI"
6687  },
6688  {
6689   "chips": ["gfx81"],
6690   "map": {"at": 196752, "to": "mm"},
6691   "name": "CP_VGT_HSINVOC_COUNT_LO",
6692   "type_ref": "CP_VGT_HSINVOC_COUNT_LO"
6693  },
6694  {
6695   "chips": ["gfx81"],
6696   "map": {"at": 196756, "to": "mm"},
6697   "name": "CP_VGT_HSINVOC_COUNT_HI",
6698   "type_ref": "CP_VGT_HSINVOC_COUNT_HI"
6699  },
6700  {
6701   "chips": ["gfx81"],
6702   "map": {"at": 196760, "to": "mm"},
6703   "name": "CP_VGT_DSINVOC_COUNT_LO",
6704   "type_ref": "CP_VGT_DSINVOC_COUNT_LO"
6705  },
6706  {
6707   "chips": ["gfx81"],
6708   "map": {"at": 196764, "to": "mm"},
6709   "name": "CP_VGT_DSINVOC_COUNT_HI",
6710   "type_ref": "CP_VGT_DSINVOC_COUNT_HI"
6711  },
6712  {
6713   "chips": ["gfx81"],
6714   "map": {"at": 196768, "to": "mm"},
6715   "name": "CP_PA_CINVOC_COUNT_LO",
6716   "type_ref": "CP_PA_CINVOC_COUNT_LO"
6717  },
6718  {
6719   "chips": ["gfx81"],
6720   "map": {"at": 196772, "to": "mm"},
6721   "name": "CP_PA_CINVOC_COUNT_HI",
6722   "type_ref": "CP_PA_CINVOC_COUNT_HI"
6723  },
6724  {
6725   "chips": ["gfx81"],
6726   "map": {"at": 196776, "to": "mm"},
6727   "name": "CP_PA_CPRIM_COUNT_LO",
6728   "type_ref": "CP_PA_CPRIM_COUNT_LO"
6729  },
6730  {
6731   "chips": ["gfx81"],
6732   "map": {"at": 196780, "to": "mm"},
6733   "name": "CP_PA_CPRIM_COUNT_HI",
6734   "type_ref": "CP_PA_CPRIM_COUNT_HI"
6735  },
6736  {
6737   "chips": ["gfx81"],
6738   "map": {"at": 196784, "to": "mm"},
6739   "name": "CP_SC_PSINVOC_COUNT0_LO",
6740   "type_ref": "CP_SC_PSINVOC_COUNT0_LO"
6741  },
6742  {
6743   "chips": ["gfx81"],
6744   "map": {"at": 196788, "to": "mm"},
6745   "name": "CP_SC_PSINVOC_COUNT0_HI",
6746   "type_ref": "CP_SC_PSINVOC_COUNT0_HI"
6747  },
6748  {
6749   "chips": ["gfx81"],
6750   "map": {"at": 196792, "to": "mm"},
6751   "name": "CP_SC_PSINVOC_COUNT1_LO",
6752   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
6753  },
6754  {
6755   "chips": ["gfx81"],
6756   "map": {"at": 196796, "to": "mm"},
6757   "name": "CP_SC_PSINVOC_COUNT1_HI",
6758   "type_ref": "CP_SC_PSINVOC_COUNT1_LO"
6759  },
6760  {
6761   "chips": ["gfx81"],
6762   "map": {"at": 196800, "to": "mm"},
6763   "name": "CP_VGT_CSINVOC_COUNT_LO",
6764   "type_ref": "CP_VGT_CSINVOC_COUNT_LO"
6765  },
6766  {
6767   "chips": ["gfx81"],
6768   "map": {"at": 196804, "to": "mm"},
6769   "name": "CP_VGT_CSINVOC_COUNT_HI",
6770   "type_ref": "CP_VGT_CSINVOC_COUNT_HI"
6771  },
6772  {
6773   "chips": ["gfx81"],
6774   "map": {"at": 196852, "to": "mm"},
6775   "name": "CP_PIPE_STATS_CONTROL",
6776   "type_ref": "CP_PIPE_STATS_CONTROL"
6777  },
6778  {
6779   "chips": ["gfx81"],
6780   "map": {"at": 196856, "to": "mm"},
6781   "name": "CP_STREAM_OUT_CONTROL",
6782   "type_ref": "CP_PIPE_STATS_CONTROL"
6783  },
6784  {
6785   "chips": ["gfx81"],
6786   "map": {"at": 196860, "to": "mm"},
6787   "name": "CP_STRMOUT_CNTL",
6788   "type_ref": "CP_STRMOUT_CNTL"
6789  },
6790  {
6791   "chips": ["gfx81"],
6792   "map": {"at": 196864, "to": "mm"},
6793   "name": "SCRATCH_REG0",
6794   "type_ref": "SCRATCH_REG0"
6795  },
6796  {
6797   "chips": ["gfx81"],
6798   "map": {"at": 196868, "to": "mm"},
6799   "name": "SCRATCH_REG1",
6800   "type_ref": "SCRATCH_REG1"
6801  },
6802  {
6803   "chips": ["gfx81"],
6804   "map": {"at": 196872, "to": "mm"},
6805   "name": "SCRATCH_REG2",
6806   "type_ref": "SCRATCH_REG2"
6807  },
6808  {
6809   "chips": ["gfx81"],
6810   "map": {"at": 196876, "to": "mm"},
6811   "name": "SCRATCH_REG3",
6812   "type_ref": "SCRATCH_REG3"
6813  },
6814  {
6815   "chips": ["gfx81"],
6816   "map": {"at": 196880, "to": "mm"},
6817   "name": "SCRATCH_REG4",
6818   "type_ref": "SCRATCH_REG4"
6819  },
6820  {
6821   "chips": ["gfx81"],
6822   "map": {"at": 196884, "to": "mm"},
6823   "name": "SCRATCH_REG5",
6824   "type_ref": "SCRATCH_REG5"
6825  },
6826  {
6827   "chips": ["gfx81"],
6828   "map": {"at": 196888, "to": "mm"},
6829   "name": "SCRATCH_REG6",
6830   "type_ref": "SCRATCH_REG6"
6831  },
6832  {
6833   "chips": ["gfx81"],
6834   "map": {"at": 196892, "to": "mm"},
6835   "name": "SCRATCH_REG7",
6836   "type_ref": "SCRATCH_REG7"
6837  },
6838  {
6839   "chips": ["gfx81"],
6840   "map": {"at": 196928, "to": "mm"},
6841   "name": "SCRATCH_UMSK",
6842   "type_ref": "SCRATCH_UMSK"
6843  },
6844  {
6845   "chips": ["gfx81"],
6846   "map": {"at": 196932, "to": "mm"},
6847   "name": "SCRATCH_ADDR",
6848   "type_ref": "SCRATCH_ADDR"
6849  },
6850  {
6851   "chips": ["gfx81"],
6852   "map": {"at": 196936, "to": "mm"},
6853   "name": "CP_PFP_ATOMIC_PREOP_LO",
6854   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
6855  },
6856  {
6857   "chips": ["gfx81"],
6858   "map": {"at": 196940, "to": "mm"},
6859   "name": "CP_PFP_ATOMIC_PREOP_HI",
6860   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
6861  },
6862  {
6863   "chips": ["gfx81"],
6864   "map": {"at": 196944, "to": "mm"},
6865   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO",
6866   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6867  },
6868  {
6869   "chips": ["gfx81"],
6870   "map": {"at": 196948, "to": "mm"},
6871   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI",
6872   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6873  },
6874  {
6875   "chips": ["gfx81"],
6876   "map": {"at": 196952, "to": "mm"},
6877   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO",
6878   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6879  },
6880  {
6881   "chips": ["gfx81"],
6882   "map": {"at": 196956, "to": "mm"},
6883   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI",
6884   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6885  },
6886  {
6887   "chips": ["gfx81"],
6888   "map": {"at": 196960, "to": "mm"},
6889   "name": "CP_APPEND_ADDR_LO",
6890   "type_ref": "CP_APPEND_ADDR_LO"
6891  },
6892  {
6893   "chips": ["gfx81"],
6894   "map": {"at": 196964, "to": "mm"},
6895   "name": "CP_APPEND_ADDR_HI",
6896   "type_ref": "CP_APPEND_ADDR_HI"
6897  },
6898  {
6899   "chips": ["gfx81"],
6900   "map": {"at": 196968, "to": "mm"},
6901   "name": "CP_APPEND_DATA",
6902   "type_ref": "CP_APPEND_DATA"
6903  },
6904  {
6905   "chips": ["gfx81"],
6906   "map": {"at": 196972, "to": "mm"},
6907   "name": "CP_APPEND_LAST_CS_FENCE",
6908   "type_ref": "CP_APPEND_LAST_CS_FENCE"
6909  },
6910  {
6911   "chips": ["gfx81"],
6912   "map": {"at": 196976, "to": "mm"},
6913   "name": "CP_APPEND_LAST_PS_FENCE",
6914   "type_ref": "CP_APPEND_LAST_CS_FENCE"
6915  },
6916  {
6917   "chips": ["gfx81"],
6918   "map": {"at": 196980, "to": "mm"},
6919   "name": "CP_ATOMIC_PREOP_LO",
6920   "type_ref": "CP_PFP_ATOMIC_PREOP_LO"
6921  },
6922  {
6923   "chips": ["gfx81"],
6924   "map": {"at": 196984, "to": "mm"},
6925   "name": "CP_ATOMIC_PREOP_HI",
6926   "type_ref": "CP_PFP_ATOMIC_PREOP_HI"
6927  },
6928  {
6929   "chips": ["gfx81"],
6930   "map": {"at": 196988, "to": "mm"},
6931   "name": "CP_GDS_ATOMIC0_PREOP_LO",
6932   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6933  },
6934  {
6935   "chips": ["gfx81"],
6936   "map": {"at": 196992, "to": "mm"},
6937   "name": "CP_GDS_ATOMIC0_PREOP_HI",
6938   "type_ref": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6939  },
6940  {
6941   "chips": ["gfx81"],
6942   "map": {"at": 196996, "to": "mm"},
6943   "name": "CP_GDS_ATOMIC1_PREOP_LO",
6944   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6945  },
6946  {
6947   "chips": ["gfx81"],
6948   "map": {"at": 197000, "to": "mm"},
6949   "name": "CP_GDS_ATOMIC1_PREOP_HI",
6950   "type_ref": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6951  },
6952  {
6953   "chips": ["gfx81"],
6954   "map": {"at": 197028, "to": "mm"},
6955   "name": "CP_ME_MC_WADDR_LO",
6956   "type_ref": "CP_ME_MC_WADDR_LO"
6957  },
6958  {
6959   "chips": ["gfx81"],
6960   "map": {"at": 197032, "to": "mm"},
6961   "name": "CP_ME_MC_WADDR_HI",
6962   "type_ref": "CP_ME_MC_WADDR_HI"
6963  },
6964  {
6965   "chips": ["gfx81"],
6966   "map": {"at": 197036, "to": "mm"},
6967   "name": "CP_ME_MC_WDATA_LO",
6968   "type_ref": "CP_ME_MC_WDATA_LO"
6969  },
6970  {
6971   "chips": ["gfx81"],
6972   "map": {"at": 197040, "to": "mm"},
6973   "name": "CP_ME_MC_WDATA_HI",
6974   "type_ref": "CP_ME_MC_WDATA_HI"
6975  },
6976  {
6977   "chips": ["gfx81"],
6978   "map": {"at": 197044, "to": "mm"},
6979   "name": "CP_ME_MC_RADDR_LO",
6980   "type_ref": "CP_ME_MC_RADDR_LO"
6981  },
6982  {
6983   "chips": ["gfx81"],
6984   "map": {"at": 197048, "to": "mm"},
6985   "name": "CP_ME_MC_RADDR_HI",
6986   "type_ref": "CP_ME_MC_RADDR_HI"
6987  },
6988  {
6989   "chips": ["gfx81"],
6990   "map": {"at": 197052, "to": "mm"},
6991   "name": "CP_SEM_WAIT_TIMER",
6992   "type_ref": "CP_SEM_WAIT_TIMER"
6993  },
6994  {
6995   "chips": ["gfx81"],
6996   "map": {"at": 197056, "to": "mm"},
6997   "name": "CP_SIG_SEM_ADDR_LO",
6998   "type_ref": "CP_SIG_SEM_ADDR_LO"
6999  },
7000  {
7001   "chips": ["gfx81"],
7002   "map": {"at": 197060, "to": "mm"},
7003   "name": "CP_SIG_SEM_ADDR_HI",
7004   "type_ref": "CP_SIG_SEM_ADDR_HI"
7005  },
7006  {
7007   "chips": ["gfx81"],
7008   "map": {"at": 197072, "to": "mm"},
7009   "name": "CP_WAIT_REG_MEM_TIMEOUT",
7010   "type_ref": "CP_WAIT_REG_MEM_TIMEOUT"
7011  },
7012  {
7013   "chips": ["gfx81"],
7014   "map": {"at": 197076, "to": "mm"},
7015   "name": "CP_WAIT_SEM_ADDR_LO",
7016   "type_ref": "CP_SIG_SEM_ADDR_LO"
7017  },
7018  {
7019   "chips": ["gfx81"],
7020   "map": {"at": 197080, "to": "mm"},
7021   "name": "CP_WAIT_SEM_ADDR_HI",
7022   "type_ref": "CP_SIG_SEM_ADDR_HI"
7023  },
7024  {
7025   "chips": ["gfx81"],
7026   "map": {"at": 197084, "to": "mm"},
7027   "name": "CP_DMA_PFP_CONTROL",
7028   "type_ref": "CP_DMA_ME_CONTROL"
7029  },
7030  {
7031   "chips": ["gfx81"],
7032   "map": {"at": 197088, "to": "mm"},
7033   "name": "CP_DMA_ME_CONTROL",
7034   "type_ref": "CP_DMA_ME_CONTROL"
7035  },
7036  {
7037   "chips": ["gfx81"],
7038   "map": {"at": 197092, "to": "mm"},
7039   "name": "CP_COHER_BASE_HI",
7040   "type_ref": "CP_COHER_BASE_HI"
7041  },
7042  {
7043   "chips": ["gfx81"],
7044   "map": {"at": 197100, "to": "mm"},
7045   "name": "CP_COHER_START_DELAY",
7046   "type_ref": "CP_COHER_START_DELAY"
7047  },
7048  {
7049   "chips": ["gfx81"],
7050   "map": {"at": 197104, "to": "mm"},
7051   "name": "CP_COHER_CNTL",
7052   "type_ref": "CP_COHER_CNTL"
7053  },
7054  {
7055   "chips": ["gfx81"],
7056   "map": {"at": 197108, "to": "mm"},
7057   "name": "CP_COHER_SIZE",
7058   "type_ref": "CP_COHER_SIZE"
7059  },
7060  {
7061   "chips": ["gfx81"],
7062   "map": {"at": 197112, "to": "mm"},
7063   "name": "CP_COHER_BASE",
7064   "type_ref": "CP_COHER_BASE"
7065  },
7066  {
7067   "chips": ["gfx81"],
7068   "map": {"at": 197116, "to": "mm"},
7069   "name": "CP_COHER_STATUS",
7070   "type_ref": "CP_COHER_STATUS"
7071  },
7072  {
7073   "chips": ["gfx81"],
7074   "map": {"at": 197120, "to": "mm"},
7075   "name": "CP_DMA_ME_SRC_ADDR",
7076   "type_ref": "CP_DMA_ME_SRC_ADDR"
7077  },
7078  {
7079   "chips": ["gfx81"],
7080   "map": {"at": 197124, "to": "mm"},
7081   "name": "CP_DMA_ME_SRC_ADDR_HI",
7082   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7083  },
7084  {
7085   "chips": ["gfx81"],
7086   "map": {"at": 197128, "to": "mm"},
7087   "name": "CP_DMA_ME_DST_ADDR",
7088   "type_ref": "CP_DMA_ME_DST_ADDR"
7089  },
7090  {
7091   "chips": ["gfx81"],
7092   "map": {"at": 197132, "to": "mm"},
7093   "name": "CP_DMA_ME_DST_ADDR_HI",
7094   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7095  },
7096  {
7097   "chips": ["gfx81"],
7098   "map": {"at": 197136, "to": "mm"},
7099   "name": "CP_DMA_ME_COMMAND",
7100   "type_ref": "CP_DMA_ME_COMMAND"
7101  },
7102  {
7103   "chips": ["gfx81"],
7104   "map": {"at": 197140, "to": "mm"},
7105   "name": "CP_DMA_PFP_SRC_ADDR",
7106   "type_ref": "CP_DMA_ME_SRC_ADDR"
7107  },
7108  {
7109   "chips": ["gfx81"],
7110   "map": {"at": 197144, "to": "mm"},
7111   "name": "CP_DMA_PFP_SRC_ADDR_HI",
7112   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
7113  },
7114  {
7115   "chips": ["gfx81"],
7116   "map": {"at": 197148, "to": "mm"},
7117   "name": "CP_DMA_PFP_DST_ADDR",
7118   "type_ref": "CP_DMA_ME_DST_ADDR"
7119  },
7120  {
7121   "chips": ["gfx81"],
7122   "map": {"at": 197152, "to": "mm"},
7123   "name": "CP_DMA_PFP_DST_ADDR_HI",
7124   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
7125  },
7126  {
7127   "chips": ["gfx81"],
7128   "map": {"at": 197156, "to": "mm"},
7129   "name": "CP_DMA_PFP_COMMAND",
7130   "type_ref": "CP_DMA_ME_COMMAND"
7131  },
7132  {
7133   "chips": ["gfx81"],
7134   "map": {"at": 197160, "to": "mm"},
7135   "name": "CP_DMA_CNTL",
7136   "type_ref": "CP_DMA_CNTL"
7137  },
7138  {
7139   "chips": ["gfx81"],
7140   "map": {"at": 197164, "to": "mm"},
7141   "name": "CP_DMA_READ_TAGS",
7142   "type_ref": "CP_DMA_READ_TAGS"
7143  },
7144  {
7145   "chips": ["gfx81"],
7146   "map": {"at": 197168, "to": "mm"},
7147   "name": "CP_COHER_SIZE_HI",
7148   "type_ref": "CP_COHER_SIZE_HI"
7149  },
7150  {
7151   "chips": ["gfx81"],
7152   "map": {"at": 197172, "to": "mm"},
7153   "name": "CP_PFP_IB_CONTROL",
7154   "type_ref": "CP_PFP_IB_CONTROL"
7155  },
7156  {
7157   "chips": ["gfx81"],
7158   "map": {"at": 197176, "to": "mm"},
7159   "name": "CP_PFP_LOAD_CONTROL",
7160   "type_ref": "CP_PFP_LOAD_CONTROL"
7161  },
7162  {
7163   "chips": ["gfx81"],
7164   "map": {"at": 197180, "to": "mm"},
7165   "name": "CP_SCRATCH_INDEX",
7166   "type_ref": "CP_SCRATCH_INDEX"
7167  },
7168  {
7169   "chips": ["gfx81"],
7170   "map": {"at": 197184, "to": "mm"},
7171   "name": "CP_SCRATCH_DATA",
7172   "type_ref": "CP_CPC_SCRATCH_DATA"
7173  },
7174  {
7175   "chips": ["gfx81"],
7176   "map": {"at": 197188, "to": "mm"},
7177   "name": "CP_RB_OFFSET",
7178   "type_ref": "CP_RB_OFFSET"
7179  },
7180  {
7181   "chips": ["gfx81"],
7182   "map": {"at": 197192, "to": "mm"},
7183   "name": "CP_IB1_OFFSET",
7184   "type_ref": "CP_IB1_OFFSET"
7185  },
7186  {
7187   "chips": ["gfx81"],
7188   "map": {"at": 197196, "to": "mm"},
7189   "name": "CP_IB2_OFFSET",
7190   "type_ref": "CP_IB2_OFFSET"
7191  },
7192  {
7193   "chips": ["gfx81"],
7194   "map": {"at": 197200, "to": "mm"},
7195   "name": "CP_IB1_PREAMBLE_BEGIN",
7196   "type_ref": "CP_IB1_PREAMBLE_BEGIN"
7197  },
7198  {
7199   "chips": ["gfx81"],
7200   "map": {"at": 197204, "to": "mm"},
7201   "name": "CP_IB1_PREAMBLE_END",
7202   "type_ref": "CP_IB1_PREAMBLE_END"
7203  },
7204  {
7205   "chips": ["gfx81"],
7206   "map": {"at": 197208, "to": "mm"},
7207   "name": "CP_IB2_PREAMBLE_BEGIN",
7208   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
7209  },
7210  {
7211   "chips": ["gfx81"],
7212   "map": {"at": 197212, "to": "mm"},
7213   "name": "CP_IB2_PREAMBLE_END",
7214   "type_ref": "CP_IB2_PREAMBLE_END"
7215  },
7216  {
7217   "chips": ["gfx81"],
7218   "map": {"at": 197216, "to": "mm"},
7219   "name": "CP_CE_IB1_OFFSET",
7220   "type_ref": "CP_IB1_OFFSET"
7221  },
7222  {
7223   "chips": ["gfx81"],
7224   "map": {"at": 197220, "to": "mm"},
7225   "name": "CP_CE_IB2_OFFSET",
7226   "type_ref": "CP_IB2_OFFSET"
7227  },
7228  {
7229   "chips": ["gfx81"],
7230   "map": {"at": 197224, "to": "mm"},
7231   "name": "CP_CE_COUNTER",
7232   "type_ref": "CP_CE_COUNTER"
7233  },
7234  {
7235   "chips": ["gfx81"],
7236   "map": {"at": 197228, "to": "mm"},
7237   "name": "CP_CE_RB_OFFSET",
7238   "type_ref": "CP_RB_OFFSET"
7239  },
7240  {
7241   "chips": ["gfx81"],
7242   "map": {"at": 197388, "to": "mm"},
7243   "name": "CP_CE_INIT_BASE_LO",
7244   "type_ref": "CP_CE_INIT_BASE_LO"
7245  },
7246  {
7247   "chips": ["gfx81"],
7248   "map": {"at": 197392, "to": "mm"},
7249   "name": "CP_CE_INIT_BASE_HI",
7250   "type_ref": "CP_CE_INIT_BASE_HI"
7251  },
7252  {
7253   "chips": ["gfx81"],
7254   "map": {"at": 197396, "to": "mm"},
7255   "name": "CP_CE_INIT_BUFSZ",
7256   "type_ref": "CP_CE_INIT_BUFSZ"
7257  },
7258  {
7259   "chips": ["gfx81"],
7260   "map": {"at": 197400, "to": "mm"},
7261   "name": "CP_CE_IB1_BASE_LO",
7262   "type_ref": "CP_CE_IB1_BASE_LO"
7263  },
7264  {
7265   "chips": ["gfx81"],
7266   "map": {"at": 197404, "to": "mm"},
7267   "name": "CP_CE_IB1_BASE_HI",
7268   "type_ref": "CP_CE_IB1_BASE_HI"
7269  },
7270  {
7271   "chips": ["gfx81"],
7272   "map": {"at": 197408, "to": "mm"},
7273   "name": "CP_CE_IB1_BUFSZ",
7274   "type_ref": "CP_CE_IB1_BUFSZ"
7275  },
7276  {
7277   "chips": ["gfx81"],
7278   "map": {"at": 197412, "to": "mm"},
7279   "name": "CP_CE_IB2_BASE_LO",
7280   "type_ref": "CP_CE_IB2_BASE_LO"
7281  },
7282  {
7283   "chips": ["gfx81"],
7284   "map": {"at": 197416, "to": "mm"},
7285   "name": "CP_CE_IB2_BASE_HI",
7286   "type_ref": "CP_CE_IB2_BASE_HI"
7287  },
7288  {
7289   "chips": ["gfx81"],
7290   "map": {"at": 197420, "to": "mm"},
7291   "name": "CP_CE_IB2_BUFSZ",
7292   "type_ref": "CP_CE_IB2_BUFSZ"
7293  },
7294  {
7295   "chips": ["gfx81"],
7296   "map": {"at": 197424, "to": "mm"},
7297   "name": "CP_IB1_BASE_LO",
7298   "type_ref": "CP_CE_IB1_BASE_LO"
7299  },
7300  {
7301   "chips": ["gfx81"],
7302   "map": {"at": 197428, "to": "mm"},
7303   "name": "CP_IB1_BASE_HI",
7304   "type_ref": "CP_CE_IB1_BASE_HI"
7305  },
7306  {
7307   "chips": ["gfx81"],
7308   "map": {"at": 197432, "to": "mm"},
7309   "name": "CP_IB1_BUFSZ",
7310   "type_ref": "CP_CE_IB1_BUFSZ"
7311  },
7312  {
7313   "chips": ["gfx81"],
7314   "map": {"at": 197436, "to": "mm"},
7315   "name": "CP_IB2_BASE_LO",
7316   "type_ref": "CP_CE_IB2_BASE_LO"
7317  },
7318  {
7319   "chips": ["gfx81"],
7320   "map": {"at": 197440, "to": "mm"},
7321   "name": "CP_IB2_BASE_HI",
7322   "type_ref": "CP_CE_IB2_BASE_HI"
7323  },
7324  {
7325   "chips": ["gfx81"],
7326   "map": {"at": 197444, "to": "mm"},
7327   "name": "CP_IB2_BUFSZ",
7328   "type_ref": "CP_CE_IB2_BUFSZ"
7329  },
7330  {
7331   "chips": ["gfx81"],
7332   "map": {"at": 197448, "to": "mm"},
7333   "name": "CP_ST_BASE_LO",
7334   "type_ref": "CP_ST_BASE_LO"
7335  },
7336  {
7337   "chips": ["gfx81"],
7338   "map": {"at": 197452, "to": "mm"},
7339   "name": "CP_ST_BASE_HI",
7340   "type_ref": "CP_ST_BASE_HI"
7341  },
7342  {
7343   "chips": ["gfx81"],
7344   "map": {"at": 197456, "to": "mm"},
7345   "name": "CP_ST_BUFSZ",
7346   "type_ref": "CP_ST_BUFSZ"
7347  },
7348  {
7349   "chips": ["gfx81"],
7350   "map": {"at": 197460, "to": "mm"},
7351   "name": "CP_EOP_DONE_EVENT_CNTL",
7352   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
7353  },
7354  {
7355   "chips": ["gfx81"],
7356   "map": {"at": 197464, "to": "mm"},
7357   "name": "CP_EOP_DONE_DATA_CNTL",
7358   "type_ref": "CP_EOP_DONE_DATA_CNTL"
7359  },
7360  {
7361   "chips": ["gfx81"],
7362   "map": {"at": 197468, "to": "mm"},
7363   "name": "CP_EOP_DONE_CNTX_ID",
7364   "type_ref": "CP_EOP_DONE_CNTX_ID"
7365  },
7366  {
7367   "chips": ["gfx81"],
7368   "map": {"at": 197552, "to": "mm"},
7369   "name": "CP_PFP_COMPLETION_STATUS",
7370   "type_ref": "CP_PFP_COMPLETION_STATUS"
7371  },
7372  {
7373   "chips": ["gfx81"],
7374   "map": {"at": 197556, "to": "mm"},
7375   "name": "CP_CE_COMPLETION_STATUS",
7376   "type_ref": "CP_PFP_COMPLETION_STATUS"
7377  },
7378  {
7379   "chips": ["gfx81"],
7380   "map": {"at": 197560, "to": "mm"},
7381   "name": "CP_PRED_NOT_VISIBLE",
7382   "type_ref": "CP_PRED_NOT_VISIBLE"
7383  },
7384  {
7385   "chips": ["gfx81"],
7386   "map": {"at": 197568, "to": "mm"},
7387   "name": "CP_PFP_METADATA_BASE_ADDR",
7388   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7389  },
7390  {
7391   "chips": ["gfx81"],
7392   "map": {"at": 197572, "to": "mm"},
7393   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
7394   "type_ref": "CP_EOP_DONE_ADDR_HI"
7395  },
7396  {
7397   "chips": ["gfx81"],
7398   "map": {"at": 197576, "to": "mm"},
7399   "name": "CP_CE_METADATA_BASE_ADDR",
7400   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7401  },
7402  {
7403   "chips": ["gfx81"],
7404   "map": {"at": 197580, "to": "mm"},
7405   "name": "CP_CE_METADATA_BASE_ADDR_HI",
7406   "type_ref": "CP_EOP_DONE_ADDR_HI"
7407  },
7408  {
7409   "chips": ["gfx81"],
7410   "map": {"at": 197584, "to": "mm"},
7411   "name": "CP_DRAW_INDX_INDR_ADDR",
7412   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7413  },
7414  {
7415   "chips": ["gfx81"],
7416   "map": {"at": 197588, "to": "mm"},
7417   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
7418   "type_ref": "CP_EOP_DONE_ADDR_HI"
7419  },
7420  {
7421   "chips": ["gfx81"],
7422   "map": {"at": 197592, "to": "mm"},
7423   "name": "CP_DISPATCH_INDR_ADDR",
7424   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7425  },
7426  {
7427   "chips": ["gfx81"],
7428   "map": {"at": 197596, "to": "mm"},
7429   "name": "CP_DISPATCH_INDR_ADDR_HI",
7430   "type_ref": "CP_EOP_DONE_ADDR_HI"
7431  },
7432  {
7433   "chips": ["gfx81"],
7434   "map": {"at": 197600, "to": "mm"},
7435   "name": "CP_INDEX_BASE_ADDR",
7436   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7437  },
7438  {
7439   "chips": ["gfx81"],
7440   "map": {"at": 197604, "to": "mm"},
7441   "name": "CP_INDEX_BASE_ADDR_HI",
7442   "type_ref": "CP_EOP_DONE_ADDR_HI"
7443  },
7444  {
7445   "chips": ["gfx81"],
7446   "map": {"at": 197608, "to": "mm"},
7447   "name": "CP_INDEX_TYPE",
7448   "type_ref": "CP_INDEX_TYPE"
7449  },
7450  {
7451   "chips": ["gfx81"],
7452   "map": {"at": 197612, "to": "mm"},
7453   "name": "CP_GDS_BKUP_ADDR",
7454   "type_ref": "CP_PFP_METADATA_BASE_ADDR"
7455  },
7456  {
7457   "chips": ["gfx81"],
7458   "map": {"at": 197616, "to": "mm"},
7459   "name": "CP_GDS_BKUP_ADDR_HI",
7460   "type_ref": "CP_EOP_DONE_ADDR_HI"
7461  },
7462  {
7463   "chips": ["gfx81"],
7464   "map": {"at": 197620, "to": "mm"},
7465   "name": "CP_SAMPLE_STATUS",
7466   "type_ref": "CP_SAMPLE_STATUS"
7467  },
7468  {
7469   "chips": ["gfx81"],
7470   "map": {"at": 198656, "to": "mm"},
7471   "name": "GRBM_GFX_INDEX",
7472   "type_ref": "GRBM_GFX_INDEX"
7473  },
7474  {
7475   "chips": ["gfx81"],
7476   "map": {"at": 198912, "to": "mm"},
7477   "name": "VGT_ESGS_RING_SIZE",
7478   "type_ref": "VGT_ESGS_RING_SIZE"
7479  },
7480  {
7481   "chips": ["gfx81"],
7482   "map": {"at": 198916, "to": "mm"},
7483   "name": "VGT_GSVS_RING_SIZE",
7484   "type_ref": "VGT_ESGS_RING_SIZE"
7485  },
7486  {
7487   "chips": ["gfx81"],
7488   "map": {"at": 198920, "to": "mm"},
7489   "name": "VGT_PRIMITIVE_TYPE",
7490   "type_ref": "VGT_PRIMITIVE_TYPE"
7491  },
7492  {
7493   "chips": ["gfx81"],
7494   "map": {"at": 198924, "to": "mm"},
7495   "name": "VGT_INDEX_TYPE",
7496   "type_ref": "CP_INDEX_TYPE"
7497  },
7498  {
7499   "chips": ["gfx81"],
7500   "map": {"at": 198928, "to": "mm"},
7501   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0",
7502   "type_ref": "COMPUTE_DIM_X"
7503  },
7504  {
7505   "chips": ["gfx81"],
7506   "map": {"at": 198932, "to": "mm"},
7507   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1",
7508   "type_ref": "COMPUTE_DIM_X"
7509  },
7510  {
7511   "chips": ["gfx81"],
7512   "map": {"at": 198936, "to": "mm"},
7513   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2",
7514   "type_ref": "COMPUTE_DIM_X"
7515  },
7516  {
7517   "chips": ["gfx81"],
7518   "map": {"at": 198940, "to": "mm"},
7519   "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3",
7520   "type_ref": "COMPUTE_DIM_X"
7521  },
7522  {
7523   "chips": ["gfx81"],
7524   "map": {"at": 198960, "to": "mm"},
7525   "name": "VGT_NUM_INDICES",
7526   "type_ref": "VGT_DMA_SIZE"
7527  },
7528  {
7529   "chips": ["gfx81"],
7530   "map": {"at": 198964, "to": "mm"},
7531   "name": "VGT_NUM_INSTANCES",
7532   "type_ref": "VGT_DMA_NUM_INSTANCES"
7533  },
7534  {
7535   "chips": ["gfx81"],
7536   "map": {"at": 198968, "to": "mm"},
7537   "name": "VGT_TF_RING_SIZE",
7538   "type_ref": "VGT_TF_RING_SIZE"
7539  },
7540  {
7541   "chips": ["gfx81"],
7542   "map": {"at": 198972, "to": "mm"},
7543   "name": "VGT_HS_OFFCHIP_PARAM",
7544   "type_ref": "VGT_HS_OFFCHIP_PARAM"
7545  },
7546  {
7547   "chips": ["gfx81"],
7548   "map": {"at": 198976, "to": "mm"},
7549   "name": "VGT_TF_MEMORY_BASE",
7550   "type_ref": "VGT_TF_MEMORY_BASE"
7551  },
7552  {
7553   "chips": ["gfx81"],
7554   "map": {"at": 199168, "to": "mm"},
7555   "name": "PA_SU_LINE_STIPPLE_VALUE",
7556   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
7557  },
7558  {
7559   "chips": ["gfx81"],
7560   "map": {"at": 199172, "to": "mm"},
7561   "name": "PA_SC_LINE_STIPPLE_STATE",
7562   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
7563  },
7564  {
7565   "chips": ["gfx81"],
7566   "map": {"at": 199184, "to": "mm"},
7567   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
7568   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7569  },
7570  {
7571   "chips": ["gfx81"],
7572   "map": {"at": 199188, "to": "mm"},
7573   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
7574   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7575  },
7576  {
7577   "chips": ["gfx81"],
7578   "map": {"at": 199192, "to": "mm"},
7579   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
7580   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7581  },
7582  {
7583   "chips": ["gfx81"],
7584   "map": {"at": 199212, "to": "mm"},
7585   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
7586   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
7587  },
7588  {
7589   "chips": ["gfx81"],
7590   "map": {"at": 199296, "to": "mm"},
7591   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
7592   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7593  },
7594  {
7595   "chips": ["gfx81"],
7596   "map": {"at": 199300, "to": "mm"},
7597   "name": "PA_SC_P3D_TRAP_SCREEN_H",
7598   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7599  },
7600  {
7601   "chips": ["gfx81"],
7602   "map": {"at": 199304, "to": "mm"},
7603   "name": "PA_SC_P3D_TRAP_SCREEN_V",
7604   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7605  },
7606  {
7607   "chips": ["gfx81"],
7608   "map": {"at": 199308, "to": "mm"},
7609   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
7610   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7611  },
7612  {
7613   "chips": ["gfx81"],
7614   "map": {"at": 199312, "to": "mm"},
7615   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
7616   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7617  },
7618  {
7619   "chips": ["gfx81"],
7620   "map": {"at": 199328, "to": "mm"},
7621   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
7622   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7623  },
7624  {
7625   "chips": ["gfx81"],
7626   "map": {"at": 199332, "to": "mm"},
7627   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
7628   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7629  },
7630  {
7631   "chips": ["gfx81"],
7632   "map": {"at": 199336, "to": "mm"},
7633   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
7634   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7635  },
7636  {
7637   "chips": ["gfx81"],
7638   "map": {"at": 199340, "to": "mm"},
7639   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
7640   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7641  },
7642  {
7643   "chips": ["gfx81"],
7644   "map": {"at": 199344, "to": "mm"},
7645   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
7646   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7647  },
7648  {
7649   "chips": ["gfx81"],
7650   "map": {"at": 199360, "to": "mm"},
7651   "name": "PA_SC_TRAP_SCREEN_HV_EN",
7652   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
7653  },
7654  {
7655   "chips": ["gfx81"],
7656   "map": {"at": 199364, "to": "mm"},
7657   "name": "PA_SC_TRAP_SCREEN_H",
7658   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
7659  },
7660  {
7661   "chips": ["gfx81"],
7662   "map": {"at": 199368, "to": "mm"},
7663   "name": "PA_SC_TRAP_SCREEN_V",
7664   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
7665  },
7666  {
7667   "chips": ["gfx81"],
7668   "map": {"at": 199372, "to": "mm"},
7669   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
7670   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7671  },
7672  {
7673   "chips": ["gfx81"],
7674   "map": {"at": 199376, "to": "mm"},
7675   "name": "PA_SC_TRAP_SCREEN_COUNT",
7676   "type_ref": "CP_DRAW_OBJECT_COUNTER"
7677  },
7678  {
7679   "chips": ["gfx81"],
7680   "map": {"at": 199872, "to": "mm"},
7681   "name": "SQ_THREAD_TRACE_BASE",
7682   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_LO"
7683  },
7684  {
7685   "chips": ["gfx81"],
7686   "map": {"at": 199876, "to": "mm"},
7687   "name": "SQ_THREAD_TRACE_SIZE",
7688   "type_ref": "SQ_THREAD_TRACE_SIZE"
7689  },
7690  {
7691   "chips": ["gfx81"],
7692   "map": {"at": 199880, "to": "mm"},
7693   "name": "SQ_THREAD_TRACE_MASK",
7694   "type_ref": "SQ_THREAD_TRACE_MASK"
7695  },
7696  {
7697   "chips": ["gfx81"],
7698   "map": {"at": 199884, "to": "mm"},
7699   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
7700   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
7701  },
7702  {
7703   "chips": ["gfx81"],
7704   "map": {"at": 199888, "to": "mm"},
7705   "name": "SQ_THREAD_TRACE_PERF_MASK",
7706   "type_ref": "SQ_PERFCOUNTER_MASK"
7707  },
7708  {
7709   "chips": ["gfx81"],
7710   "map": {"at": 199892, "to": "mm"},
7711   "name": "SQ_THREAD_TRACE_CTRL",
7712   "type_ref": "SQ_THREAD_TRACE_CTRL"
7713  },
7714  {
7715   "chips": ["gfx81"],
7716   "map": {"at": 199896, "to": "mm"},
7717   "name": "SQ_THREAD_TRACE_MODE",
7718   "type_ref": "SQ_THREAD_TRACE_MODE"
7719  },
7720  {
7721   "chips": ["gfx81"],
7722   "map": {"at": 199900, "to": "mm"},
7723   "name": "SQ_THREAD_TRACE_BASE2",
7724   "type_ref": "SQ_THREAD_TRACE_BASE2"
7725  },
7726  {
7727   "chips": ["gfx81"],
7728   "map": {"at": 199904, "to": "mm"},
7729   "name": "SQ_THREAD_TRACE_TOKEN_MASK2",
7730   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK2"
7731  },
7732  {
7733   "chips": ["gfx81"],
7734   "map": {"at": 199908, "to": "mm"},
7735   "name": "SQ_THREAD_TRACE_WPTR",
7736   "type_ref": "SQ_THREAD_TRACE_WPTR"
7737  },
7738  {
7739   "chips": ["gfx81"],
7740   "map": {"at": 199912, "to": "mm"},
7741   "name": "SQ_THREAD_TRACE_STATUS",
7742   "type_ref": "SQ_THREAD_TRACE_STATUS"
7743  },
7744  {
7745   "chips": ["gfx81"],
7746   "map": {"at": 199916, "to": "mm"},
7747   "name": "SQ_THREAD_TRACE_HIWATER",
7748   "type_ref": "SQ_THREAD_TRACE_HIWATER"
7749  },
7750  {
7751   "chips": ["gfx81"],
7752   "map": {"at": 199936, "to": "mm"},
7753   "name": "SQ_THREAD_TRACE_USERDATA_0",
7754   "type_ref": "CP_APPEND_DATA"
7755  },
7756  {
7757   "chips": ["gfx81"],
7758   "map": {"at": 199940, "to": "mm"},
7759   "name": "SQ_THREAD_TRACE_USERDATA_1",
7760   "type_ref": "CP_APPEND_DATA"
7761  },
7762  {
7763   "chips": ["gfx81"],
7764   "map": {"at": 199944, "to": "mm"},
7765   "name": "SQ_THREAD_TRACE_USERDATA_2",
7766   "type_ref": "CP_APPEND_DATA"
7767  },
7768  {
7769   "chips": ["gfx81"],
7770   "map": {"at": 199948, "to": "mm"},
7771   "name": "SQ_THREAD_TRACE_USERDATA_3",
7772   "type_ref": "CP_APPEND_DATA"
7773  },
7774  {
7775   "chips": ["gfx81"],
7776   "map": {"at": 199968, "to": "mm"},
7777   "name": "SQC_CACHES",
7778   "type_ref": "SQC_CACHES"
7779  },
7780  {
7781   "chips": ["gfx81"],
7782   "map": {"at": 199972, "to": "mm"},
7783   "name": "SQC_WRITEBACK",
7784   "type_ref": "SQC_WRITEBACK"
7785  },
7786  {
7787   "chips": ["gfx81"],
7788   "map": {"at": 200192, "to": "mm"},
7789   "name": "TA_CS_BC_BASE_ADDR",
7790   "type_ref": "TA_BC_BASE_ADDR"
7791  },
7792  {
7793   "chips": ["gfx81"],
7794   "map": {"at": 200196, "to": "mm"},
7795   "name": "TA_CS_BC_BASE_ADDR_HI",
7796   "type_ref": "TA_BC_BASE_ADDR_HI"
7797  },
7798  {
7799   "chips": ["gfx81"],
7800   "map": {"at": 200448, "to": "mm"},
7801   "name": "DB_OCCLUSION_COUNT0_LOW",
7802   "type_ref": "DB_ZPASS_COUNT_LOW"
7803  },
7804  {
7805   "chips": ["gfx81"],
7806   "map": {"at": 200452, "to": "mm"},
7807   "name": "DB_OCCLUSION_COUNT0_HI",
7808   "type_ref": "DB_ZPASS_COUNT_HI"
7809  },
7810  {
7811   "chips": ["gfx81"],
7812   "map": {"at": 200456, "to": "mm"},
7813   "name": "DB_OCCLUSION_COUNT1_LOW",
7814   "type_ref": "DB_ZPASS_COUNT_LOW"
7815  },
7816  {
7817   "chips": ["gfx81"],
7818   "map": {"at": 200460, "to": "mm"},
7819   "name": "DB_OCCLUSION_COUNT1_HI",
7820   "type_ref": "DB_ZPASS_COUNT_HI"
7821  },
7822  {
7823   "chips": ["gfx81"],
7824   "map": {"at": 200464, "to": "mm"},
7825   "name": "DB_OCCLUSION_COUNT2_LOW",
7826   "type_ref": "DB_ZPASS_COUNT_LOW"
7827  },
7828  {
7829   "chips": ["gfx81"],
7830   "map": {"at": 200468, "to": "mm"},
7831   "name": "DB_OCCLUSION_COUNT2_HI",
7832   "type_ref": "DB_ZPASS_COUNT_HI"
7833  },
7834  {
7835   "chips": ["gfx81"],
7836   "map": {"at": 200472, "to": "mm"},
7837   "name": "DB_OCCLUSION_COUNT3_LOW",
7838   "type_ref": "DB_ZPASS_COUNT_LOW"
7839  },
7840  {
7841   "chips": ["gfx81"],
7842   "map": {"at": 200476, "to": "mm"},
7843   "name": "DB_OCCLUSION_COUNT3_HI",
7844   "type_ref": "DB_ZPASS_COUNT_HI"
7845  },
7846  {
7847   "chips": ["gfx81"],
7848   "map": {"at": 200696, "to": "mm"},
7849   "name": "DB_ZPASS_COUNT_LOW",
7850   "type_ref": "DB_ZPASS_COUNT_LOW"
7851  },
7852  {
7853   "chips": ["gfx81"],
7854   "map": {"at": 200700, "to": "mm"},
7855   "name": "DB_ZPASS_COUNT_HI",
7856   "type_ref": "DB_ZPASS_COUNT_HI"
7857  },
7858  {
7859   "chips": ["gfx81"],
7860   "map": {"at": 200704, "to": "mm"},
7861   "name": "GDS_RD_ADDR",
7862   "type_ref": "GDS_RD_ADDR"
7863  },
7864  {
7865   "chips": ["gfx81"],
7866   "map": {"at": 200708, "to": "mm"},
7867   "name": "GDS_RD_DATA",
7868   "type_ref": "GDS_RD_DATA"
7869  },
7870  {
7871   "chips": ["gfx81"],
7872   "map": {"at": 200712, "to": "mm"},
7873   "name": "GDS_RD_BURST_ADDR",
7874   "type_ref": "GDS_RD_BURST_ADDR"
7875  },
7876  {
7877   "chips": ["gfx81"],
7878   "map": {"at": 200716, "to": "mm"},
7879   "name": "GDS_RD_BURST_COUNT",
7880   "type_ref": "GDS_RD_BURST_COUNT"
7881  },
7882  {
7883   "chips": ["gfx81"],
7884   "map": {"at": 200720, "to": "mm"},
7885   "name": "GDS_RD_BURST_DATA",
7886   "type_ref": "GDS_RD_BURST_DATA"
7887  },
7888  {
7889   "chips": ["gfx81"],
7890   "map": {"at": 200724, "to": "mm"},
7891   "name": "GDS_WR_ADDR",
7892   "type_ref": "GDS_WR_ADDR"
7893  },
7894  {
7895   "chips": ["gfx81"],
7896   "map": {"at": 200728, "to": "mm"},
7897   "name": "GDS_WR_DATA",
7898   "type_ref": "GDS_WR_DATA"
7899  },
7900  {
7901   "chips": ["gfx81"],
7902   "map": {"at": 200732, "to": "mm"},
7903   "name": "GDS_WR_BURST_ADDR",
7904   "type_ref": "GDS_WR_ADDR"
7905  },
7906  {
7907   "chips": ["gfx81"],
7908   "map": {"at": 200736, "to": "mm"},
7909   "name": "GDS_WR_BURST_DATA",
7910   "type_ref": "GDS_WR_DATA"
7911  },
7912  {
7913   "chips": ["gfx81"],
7914   "map": {"at": 200740, "to": "mm"},
7915   "name": "GDS_WRITE_COMPLETE",
7916   "type_ref": "GDS_WRITE_COMPLETE"
7917  },
7918  {
7919   "chips": ["gfx81"],
7920   "map": {"at": 200744, "to": "mm"},
7921   "name": "GDS_ATOM_CNTL",
7922   "type_ref": "GDS_ATOM_CNTL"
7923  },
7924  {
7925   "chips": ["gfx81"],
7926   "map": {"at": 200748, "to": "mm"},
7927   "name": "GDS_ATOM_COMPLETE",
7928   "type_ref": "GDS_ATOM_COMPLETE"
7929  },
7930  {
7931   "chips": ["gfx81"],
7932   "map": {"at": 200752, "to": "mm"},
7933   "name": "GDS_ATOM_BASE",
7934   "type_ref": "GDS_ATOM_BASE"
7935  },
7936  {
7937   "chips": ["gfx81"],
7938   "map": {"at": 200756, "to": "mm"},
7939   "name": "GDS_ATOM_SIZE",
7940   "type_ref": "GDS_ATOM_SIZE"
7941  },
7942  {
7943   "chips": ["gfx81"],
7944   "map": {"at": 200760, "to": "mm"},
7945   "name": "GDS_ATOM_OFFSET0",
7946   "type_ref": "GDS_ATOM_OFFSET0"
7947  },
7948  {
7949   "chips": ["gfx81"],
7950   "map": {"at": 200764, "to": "mm"},
7951   "name": "GDS_ATOM_OFFSET1",
7952   "type_ref": "GDS_ATOM_OFFSET1"
7953  },
7954  {
7955   "chips": ["gfx81"],
7956   "map": {"at": 200768, "to": "mm"},
7957   "name": "GDS_ATOM_DST",
7958   "type_ref": "GDS_ATOM_DST"
7959  },
7960  {
7961   "chips": ["gfx81"],
7962   "map": {"at": 200772, "to": "mm"},
7963   "name": "GDS_ATOM_OP",
7964   "type_ref": "GDS_ATOM_OP"
7965  },
7966  {
7967   "chips": ["gfx81"],
7968   "map": {"at": 200776, "to": "mm"},
7969   "name": "GDS_ATOM_SRC0",
7970   "type_ref": "CP_APPEND_DATA"
7971  },
7972  {
7973   "chips": ["gfx81"],
7974   "map": {"at": 200780, "to": "mm"},
7975   "name": "GDS_ATOM_SRC0_U",
7976   "type_ref": "CP_APPEND_DATA"
7977  },
7978  {
7979   "chips": ["gfx81"],
7980   "map": {"at": 200784, "to": "mm"},
7981   "name": "GDS_ATOM_SRC1",
7982   "type_ref": "CP_APPEND_DATA"
7983  },
7984  {
7985   "chips": ["gfx81"],
7986   "map": {"at": 200788, "to": "mm"},
7987   "name": "GDS_ATOM_SRC1_U",
7988   "type_ref": "CP_APPEND_DATA"
7989  },
7990  {
7991   "chips": ["gfx81"],
7992   "map": {"at": 200792, "to": "mm"},
7993   "name": "GDS_ATOM_READ0",
7994   "type_ref": "CP_APPEND_DATA"
7995  },
7996  {
7997   "chips": ["gfx81"],
7998   "map": {"at": 200796, "to": "mm"},
7999   "name": "GDS_ATOM_READ0_U",
8000   "type_ref": "CP_APPEND_DATA"
8001  },
8002  {
8003   "chips": ["gfx81"],
8004   "map": {"at": 200800, "to": "mm"},
8005   "name": "GDS_ATOM_READ1",
8006   "type_ref": "CP_APPEND_DATA"
8007  },
8008  {
8009   "chips": ["gfx81"],
8010   "map": {"at": 200804, "to": "mm"},
8011   "name": "GDS_ATOM_READ1_U",
8012   "type_ref": "CP_APPEND_DATA"
8013  },
8014  {
8015   "chips": ["gfx81"],
8016   "map": {"at": 200808, "to": "mm"},
8017   "name": "GDS_GWS_RESOURCE_CNTL",
8018   "type_ref": "GDS_GWS_RESOURCE_CNTL"
8019  },
8020  {
8021   "chips": ["gfx81"],
8022   "map": {"at": 200812, "to": "mm"},
8023   "name": "GDS_GWS_RESOURCE",
8024   "type_ref": "GDS_GWS_RESOURCE"
8025  },
8026  {
8027   "chips": ["gfx81"],
8028   "map": {"at": 200816, "to": "mm"},
8029   "name": "GDS_GWS_RESOURCE_CNT",
8030   "type_ref": "GDS_GWS_RESOURCE_CNT"
8031  },
8032  {
8033   "chips": ["gfx81"],
8034   "map": {"at": 200820, "to": "mm"},
8035   "name": "GDS_OA_CNTL",
8036   "type_ref": "GDS_OA_CNTL"
8037  },
8038  {
8039   "chips": ["gfx81"],
8040   "map": {"at": 200824, "to": "mm"},
8041   "name": "GDS_OA_COUNTER",
8042   "type_ref": "GDS_OA_COUNTER"
8043  },
8044  {
8045   "chips": ["gfx81"],
8046   "map": {"at": 200828, "to": "mm"},
8047   "name": "GDS_OA_ADDRESS",
8048   "type_ref": "GDS_OA_ADDRESS"
8049  },
8050  {
8051   "chips": ["gfx81"],
8052   "map": {"at": 200832, "to": "mm"},
8053   "name": "GDS_OA_INCDEC",
8054   "type_ref": "GDS_OA_INCDEC"
8055  },
8056  {
8057   "chips": ["gfx81"],
8058   "map": {"at": 200836, "to": "mm"},
8059   "name": "GDS_OA_RING_SIZE",
8060   "type_ref": "GDS_OA_RING_SIZE"
8061  },
8062  {
8063   "chips": ["gfx81"],
8064   "map": {"at": 212992, "to": "mm"},
8065   "name": "CPG_PERFCOUNTER1_LO",
8066   "type_ref": "CB_PERFCOUNTER0_LO"
8067  },
8068  {
8069   "chips": ["gfx81"],
8070   "map": {"at": 212996, "to": "mm"},
8071   "name": "CPG_PERFCOUNTER1_HI",
8072   "type_ref": "CB_PERFCOUNTER0_HI"
8073  },
8074  {
8075   "chips": ["gfx81"],
8076   "map": {"at": 213000, "to": "mm"},
8077   "name": "CPG_PERFCOUNTER0_LO",
8078   "type_ref": "CB_PERFCOUNTER0_LO"
8079  },
8080  {
8081   "chips": ["gfx81"],
8082   "map": {"at": 213004, "to": "mm"},
8083   "name": "CPG_PERFCOUNTER0_HI",
8084   "type_ref": "CB_PERFCOUNTER0_HI"
8085  },
8086  {
8087   "chips": ["gfx81"],
8088   "map": {"at": 213008, "to": "mm"},
8089   "name": "CPC_PERFCOUNTER1_LO",
8090   "type_ref": "CB_PERFCOUNTER0_LO"
8091  },
8092  {
8093   "chips": ["gfx81"],
8094   "map": {"at": 213012, "to": "mm"},
8095   "name": "CPC_PERFCOUNTER1_HI",
8096   "type_ref": "CB_PERFCOUNTER0_HI"
8097  },
8098  {
8099   "chips": ["gfx81"],
8100   "map": {"at": 213016, "to": "mm"},
8101   "name": "CPC_PERFCOUNTER0_LO",
8102   "type_ref": "CB_PERFCOUNTER0_LO"
8103  },
8104  {
8105   "chips": ["gfx81"],
8106   "map": {"at": 213020, "to": "mm"},
8107   "name": "CPC_PERFCOUNTER0_HI",
8108   "type_ref": "CB_PERFCOUNTER0_HI"
8109  },
8110  {
8111   "chips": ["gfx81"],
8112   "map": {"at": 213024, "to": "mm"},
8113   "name": "CPF_PERFCOUNTER1_LO",
8114   "type_ref": "CB_PERFCOUNTER0_LO"
8115  },
8116  {
8117   "chips": ["gfx81"],
8118   "map": {"at": 213028, "to": "mm"},
8119   "name": "CPF_PERFCOUNTER1_HI",
8120   "type_ref": "CB_PERFCOUNTER0_HI"
8121  },
8122  {
8123   "chips": ["gfx81"],
8124   "map": {"at": 213032, "to": "mm"},
8125   "name": "CPF_PERFCOUNTER0_LO",
8126   "type_ref": "CB_PERFCOUNTER0_LO"
8127  },
8128  {
8129   "chips": ["gfx81"],
8130   "map": {"at": 213036, "to": "mm"},
8131   "name": "CPF_PERFCOUNTER0_HI",
8132   "type_ref": "CB_PERFCOUNTER0_HI"
8133  },
8134  {
8135   "chips": ["gfx81"],
8136   "map": {"at": 213248, "to": "mm"},
8137   "name": "GRBM_PERFCOUNTER0_LO",
8138   "type_ref": "CB_PERFCOUNTER0_LO"
8139  },
8140  {
8141   "chips": ["gfx81"],
8142   "map": {"at": 213252, "to": "mm"},
8143   "name": "GRBM_PERFCOUNTER0_HI",
8144   "type_ref": "CB_PERFCOUNTER0_HI"
8145  },
8146  {
8147   "chips": ["gfx81"],
8148   "map": {"at": 213260, "to": "mm"},
8149   "name": "GRBM_PERFCOUNTER1_LO",
8150   "type_ref": "CB_PERFCOUNTER0_LO"
8151  },
8152  {
8153   "chips": ["gfx81"],
8154   "map": {"at": 213264, "to": "mm"},
8155   "name": "GRBM_PERFCOUNTER1_HI",
8156   "type_ref": "CB_PERFCOUNTER0_HI"
8157  },
8158  {
8159   "chips": ["gfx81"],
8160   "map": {"at": 213268, "to": "mm"},
8161   "name": "GRBM_SE0_PERFCOUNTER_LO",
8162   "type_ref": "CB_PERFCOUNTER0_LO"
8163  },
8164  {
8165   "chips": ["gfx81"],
8166   "map": {"at": 213272, "to": "mm"},
8167   "name": "GRBM_SE0_PERFCOUNTER_HI",
8168   "type_ref": "CB_PERFCOUNTER0_HI"
8169  },
8170  {
8171   "chips": ["gfx81"],
8172   "map": {"at": 213276, "to": "mm"},
8173   "name": "GRBM_SE1_PERFCOUNTER_LO",
8174   "type_ref": "CB_PERFCOUNTER0_LO"
8175  },
8176  {
8177   "chips": ["gfx81"],
8178   "map": {"at": 213280, "to": "mm"},
8179   "name": "GRBM_SE1_PERFCOUNTER_HI",
8180   "type_ref": "CB_PERFCOUNTER0_HI"
8181  },
8182  {
8183   "chips": ["gfx81"],
8184   "map": {"at": 213284, "to": "mm"},
8185   "name": "GRBM_SE2_PERFCOUNTER_LO",
8186   "type_ref": "CB_PERFCOUNTER0_LO"
8187  },
8188  {
8189   "chips": ["gfx81"],
8190   "map": {"at": 213288, "to": "mm"},
8191   "name": "GRBM_SE2_PERFCOUNTER_HI",
8192   "type_ref": "CB_PERFCOUNTER0_HI"
8193  },
8194  {
8195   "chips": ["gfx81"],
8196   "map": {"at": 213292, "to": "mm"},
8197   "name": "GRBM_SE3_PERFCOUNTER_LO",
8198   "type_ref": "CB_PERFCOUNTER0_LO"
8199  },
8200  {
8201   "chips": ["gfx81"],
8202   "map": {"at": 213296, "to": "mm"},
8203   "name": "GRBM_SE3_PERFCOUNTER_HI",
8204   "type_ref": "CB_PERFCOUNTER0_HI"
8205  },
8206  {
8207   "chips": ["gfx81"],
8208   "map": {"at": 213504, "to": "mm"},
8209   "name": "WD_PERFCOUNTER0_LO",
8210   "type_ref": "CB_PERFCOUNTER0_LO"
8211  },
8212  {
8213   "chips": ["gfx81"],
8214   "map": {"at": 213508, "to": "mm"},
8215   "name": "WD_PERFCOUNTER0_HI",
8216   "type_ref": "CB_PERFCOUNTER0_HI"
8217  },
8218  {
8219   "chips": ["gfx81"],
8220   "map": {"at": 213512, "to": "mm"},
8221   "name": "WD_PERFCOUNTER1_LO",
8222   "type_ref": "CB_PERFCOUNTER0_LO"
8223  },
8224  {
8225   "chips": ["gfx81"],
8226   "map": {"at": 213516, "to": "mm"},
8227   "name": "WD_PERFCOUNTER1_HI",
8228   "type_ref": "CB_PERFCOUNTER0_HI"
8229  },
8230  {
8231   "chips": ["gfx81"],
8232   "map": {"at": 213520, "to": "mm"},
8233   "name": "WD_PERFCOUNTER2_LO",
8234   "type_ref": "CB_PERFCOUNTER0_LO"
8235  },
8236  {
8237   "chips": ["gfx81"],
8238   "map": {"at": 213524, "to": "mm"},
8239   "name": "WD_PERFCOUNTER2_HI",
8240   "type_ref": "CB_PERFCOUNTER0_HI"
8241  },
8242  {
8243   "chips": ["gfx81"],
8244   "map": {"at": 213528, "to": "mm"},
8245   "name": "WD_PERFCOUNTER3_LO",
8246   "type_ref": "CB_PERFCOUNTER0_LO"
8247  },
8248  {
8249   "chips": ["gfx81"],
8250   "map": {"at": 213532, "to": "mm"},
8251   "name": "WD_PERFCOUNTER3_HI",
8252   "type_ref": "CB_PERFCOUNTER0_HI"
8253  },
8254  {
8255   "chips": ["gfx81"],
8256   "map": {"at": 213536, "to": "mm"},
8257   "name": "IA_PERFCOUNTER0_LO",
8258   "type_ref": "CB_PERFCOUNTER0_LO"
8259  },
8260  {
8261   "chips": ["gfx81"],
8262   "map": {"at": 213540, "to": "mm"},
8263   "name": "IA_PERFCOUNTER0_HI",
8264   "type_ref": "CB_PERFCOUNTER0_HI"
8265  },
8266  {
8267   "chips": ["gfx81"],
8268   "map": {"at": 213544, "to": "mm"},
8269   "name": "IA_PERFCOUNTER1_LO",
8270   "type_ref": "CB_PERFCOUNTER0_LO"
8271  },
8272  {
8273   "chips": ["gfx81"],
8274   "map": {"at": 213548, "to": "mm"},
8275   "name": "IA_PERFCOUNTER1_HI",
8276   "type_ref": "CB_PERFCOUNTER0_HI"
8277  },
8278  {
8279   "chips": ["gfx81"],
8280   "map": {"at": 213552, "to": "mm"},
8281   "name": "IA_PERFCOUNTER2_LO",
8282   "type_ref": "CB_PERFCOUNTER0_LO"
8283  },
8284  {
8285   "chips": ["gfx81"],
8286   "map": {"at": 213556, "to": "mm"},
8287   "name": "IA_PERFCOUNTER2_HI",
8288   "type_ref": "CB_PERFCOUNTER0_HI"
8289  },
8290  {
8291   "chips": ["gfx81"],
8292   "map": {"at": 213560, "to": "mm"},
8293   "name": "IA_PERFCOUNTER3_LO",
8294   "type_ref": "CB_PERFCOUNTER0_LO"
8295  },
8296  {
8297   "chips": ["gfx81"],
8298   "map": {"at": 213564, "to": "mm"},
8299   "name": "IA_PERFCOUNTER3_HI",
8300   "type_ref": "CB_PERFCOUNTER0_HI"
8301  },
8302  {
8303   "chips": ["gfx81"],
8304   "map": {"at": 213568, "to": "mm"},
8305   "name": "VGT_PERFCOUNTER0_LO",
8306   "type_ref": "CB_PERFCOUNTER0_LO"
8307  },
8308  {
8309   "chips": ["gfx81"],
8310   "map": {"at": 213572, "to": "mm"},
8311   "name": "VGT_PERFCOUNTER0_HI",
8312   "type_ref": "CB_PERFCOUNTER0_HI"
8313  },
8314  {
8315   "chips": ["gfx81"],
8316   "map": {"at": 213576, "to": "mm"},
8317   "name": "VGT_PERFCOUNTER1_LO",
8318   "type_ref": "CB_PERFCOUNTER0_LO"
8319  },
8320  {
8321   "chips": ["gfx81"],
8322   "map": {"at": 213580, "to": "mm"},
8323   "name": "VGT_PERFCOUNTER1_HI",
8324   "type_ref": "CB_PERFCOUNTER0_HI"
8325  },
8326  {
8327   "chips": ["gfx81"],
8328   "map": {"at": 213584, "to": "mm"},
8329   "name": "VGT_PERFCOUNTER2_LO",
8330   "type_ref": "CB_PERFCOUNTER0_LO"
8331  },
8332  {
8333   "chips": ["gfx81"],
8334   "map": {"at": 213588, "to": "mm"},
8335   "name": "VGT_PERFCOUNTER2_HI",
8336   "type_ref": "CB_PERFCOUNTER0_HI"
8337  },
8338  {
8339   "chips": ["gfx81"],
8340   "map": {"at": 213592, "to": "mm"},
8341   "name": "VGT_PERFCOUNTER3_LO",
8342   "type_ref": "CB_PERFCOUNTER0_LO"
8343  },
8344  {
8345   "chips": ["gfx81"],
8346   "map": {"at": 213596, "to": "mm"},
8347   "name": "VGT_PERFCOUNTER3_HI",
8348   "type_ref": "CB_PERFCOUNTER0_HI"
8349  },
8350  {
8351   "chips": ["gfx81"],
8352   "map": {"at": 214016, "to": "mm"},
8353   "name": "PA_SU_PERFCOUNTER0_LO",
8354   "type_ref": "CB_PERFCOUNTER0_LO"
8355  },
8356  {
8357   "chips": ["gfx81"],
8358   "map": {"at": 214020, "to": "mm"},
8359   "name": "PA_SU_PERFCOUNTER0_HI",
8360   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8361  },
8362  {
8363   "chips": ["gfx81"],
8364   "map": {"at": 214024, "to": "mm"},
8365   "name": "PA_SU_PERFCOUNTER1_LO",
8366   "type_ref": "CB_PERFCOUNTER0_LO"
8367  },
8368  {
8369   "chips": ["gfx81"],
8370   "map": {"at": 214028, "to": "mm"},
8371   "name": "PA_SU_PERFCOUNTER1_HI",
8372   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8373  },
8374  {
8375   "chips": ["gfx81"],
8376   "map": {"at": 214032, "to": "mm"},
8377   "name": "PA_SU_PERFCOUNTER2_LO",
8378   "type_ref": "CB_PERFCOUNTER0_LO"
8379  },
8380  {
8381   "chips": ["gfx81"],
8382   "map": {"at": 214036, "to": "mm"},
8383   "name": "PA_SU_PERFCOUNTER2_HI",
8384   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8385  },
8386  {
8387   "chips": ["gfx81"],
8388   "map": {"at": 214040, "to": "mm"},
8389   "name": "PA_SU_PERFCOUNTER3_LO",
8390   "type_ref": "CB_PERFCOUNTER0_LO"
8391  },
8392  {
8393   "chips": ["gfx81"],
8394   "map": {"at": 214044, "to": "mm"},
8395   "name": "PA_SU_PERFCOUNTER3_HI",
8396   "type_ref": "PA_SU_PERFCOUNTER0_HI"
8397  },
8398  {
8399   "chips": ["gfx81"],
8400   "map": {"at": 214272, "to": "mm"},
8401   "name": "PA_SC_PERFCOUNTER0_LO",
8402   "type_ref": "CB_PERFCOUNTER0_LO"
8403  },
8404  {
8405   "chips": ["gfx81"],
8406   "map": {"at": 214276, "to": "mm"},
8407   "name": "PA_SC_PERFCOUNTER0_HI",
8408   "type_ref": "CB_PERFCOUNTER0_HI"
8409  },
8410  {
8411   "chips": ["gfx81"],
8412   "map": {"at": 214280, "to": "mm"},
8413   "name": "PA_SC_PERFCOUNTER1_LO",
8414   "type_ref": "CB_PERFCOUNTER0_LO"
8415  },
8416  {
8417   "chips": ["gfx81"],
8418   "map": {"at": 214284, "to": "mm"},
8419   "name": "PA_SC_PERFCOUNTER1_HI",
8420   "type_ref": "CB_PERFCOUNTER0_HI"
8421  },
8422  {
8423   "chips": ["gfx81"],
8424   "map": {"at": 214288, "to": "mm"},
8425   "name": "PA_SC_PERFCOUNTER2_LO",
8426   "type_ref": "CB_PERFCOUNTER0_LO"
8427  },
8428  {
8429   "chips": ["gfx81"],
8430   "map": {"at": 214292, "to": "mm"},
8431   "name": "PA_SC_PERFCOUNTER2_HI",
8432   "type_ref": "CB_PERFCOUNTER0_HI"
8433  },
8434  {
8435   "chips": ["gfx81"],
8436   "map": {"at": 214296, "to": "mm"},
8437   "name": "PA_SC_PERFCOUNTER3_LO",
8438   "type_ref": "CB_PERFCOUNTER0_LO"
8439  },
8440  {
8441   "chips": ["gfx81"],
8442   "map": {"at": 214300, "to": "mm"},
8443   "name": "PA_SC_PERFCOUNTER3_HI",
8444   "type_ref": "CB_PERFCOUNTER0_HI"
8445  },
8446  {
8447   "chips": ["gfx81"],
8448   "map": {"at": 214304, "to": "mm"},
8449   "name": "PA_SC_PERFCOUNTER4_LO",
8450   "type_ref": "CB_PERFCOUNTER0_LO"
8451  },
8452  {
8453   "chips": ["gfx81"],
8454   "map": {"at": 214308, "to": "mm"},
8455   "name": "PA_SC_PERFCOUNTER4_HI",
8456   "type_ref": "CB_PERFCOUNTER0_HI"
8457  },
8458  {
8459   "chips": ["gfx81"],
8460   "map": {"at": 214312, "to": "mm"},
8461   "name": "PA_SC_PERFCOUNTER5_LO",
8462   "type_ref": "CB_PERFCOUNTER0_LO"
8463  },
8464  {
8465   "chips": ["gfx81"],
8466   "map": {"at": 214316, "to": "mm"},
8467   "name": "PA_SC_PERFCOUNTER5_HI",
8468   "type_ref": "CB_PERFCOUNTER0_HI"
8469  },
8470  {
8471   "chips": ["gfx81"],
8472   "map": {"at": 214320, "to": "mm"},
8473   "name": "PA_SC_PERFCOUNTER6_LO",
8474   "type_ref": "CB_PERFCOUNTER0_LO"
8475  },
8476  {
8477   "chips": ["gfx81"],
8478   "map": {"at": 214324, "to": "mm"},
8479   "name": "PA_SC_PERFCOUNTER6_HI",
8480   "type_ref": "CB_PERFCOUNTER0_HI"
8481  },
8482  {
8483   "chips": ["gfx81"],
8484   "map": {"at": 214328, "to": "mm"},
8485   "name": "PA_SC_PERFCOUNTER7_LO",
8486   "type_ref": "CB_PERFCOUNTER0_LO"
8487  },
8488  {
8489   "chips": ["gfx81"],
8490   "map": {"at": 214332, "to": "mm"},
8491   "name": "PA_SC_PERFCOUNTER7_HI",
8492   "type_ref": "CB_PERFCOUNTER0_HI"
8493  },
8494  {
8495   "chips": ["gfx81"],
8496   "map": {"at": 214528, "to": "mm"},
8497   "name": "SPI_PERFCOUNTER0_HI",
8498   "type_ref": "CB_PERFCOUNTER0_HI"
8499  },
8500  {
8501   "chips": ["gfx81"],
8502   "map": {"at": 214532, "to": "mm"},
8503   "name": "SPI_PERFCOUNTER0_LO",
8504   "type_ref": "CB_PERFCOUNTER0_LO"
8505  },
8506  {
8507   "chips": ["gfx81"],
8508   "map": {"at": 214536, "to": "mm"},
8509   "name": "SPI_PERFCOUNTER1_HI",
8510   "type_ref": "CB_PERFCOUNTER0_HI"
8511  },
8512  {
8513   "chips": ["gfx81"],
8514   "map": {"at": 214540, "to": "mm"},
8515   "name": "SPI_PERFCOUNTER1_LO",
8516   "type_ref": "CB_PERFCOUNTER0_LO"
8517  },
8518  {
8519   "chips": ["gfx81"],
8520   "map": {"at": 214544, "to": "mm"},
8521   "name": "SPI_PERFCOUNTER2_HI",
8522   "type_ref": "CB_PERFCOUNTER0_HI"
8523  },
8524  {
8525   "chips": ["gfx81"],
8526   "map": {"at": 214548, "to": "mm"},
8527   "name": "SPI_PERFCOUNTER2_LO",
8528   "type_ref": "CB_PERFCOUNTER0_LO"
8529  },
8530  {
8531   "chips": ["gfx81"],
8532   "map": {"at": 214552, "to": "mm"},
8533   "name": "SPI_PERFCOUNTER3_HI",
8534   "type_ref": "CB_PERFCOUNTER0_HI"
8535  },
8536  {
8537   "chips": ["gfx81"],
8538   "map": {"at": 214556, "to": "mm"},
8539   "name": "SPI_PERFCOUNTER3_LO",
8540   "type_ref": "CB_PERFCOUNTER0_LO"
8541  },
8542  {
8543   "chips": ["gfx81"],
8544   "map": {"at": 214560, "to": "mm"},
8545   "name": "SPI_PERFCOUNTER4_HI",
8546   "type_ref": "CB_PERFCOUNTER0_HI"
8547  },
8548  {
8549   "chips": ["gfx81"],
8550   "map": {"at": 214564, "to": "mm"},
8551   "name": "SPI_PERFCOUNTER4_LO",
8552   "type_ref": "CB_PERFCOUNTER0_LO"
8553  },
8554  {
8555   "chips": ["gfx81"],
8556   "map": {"at": 214568, "to": "mm"},
8557   "name": "SPI_PERFCOUNTER5_HI",
8558   "type_ref": "CB_PERFCOUNTER0_HI"
8559  },
8560  {
8561   "chips": ["gfx81"],
8562   "map": {"at": 214572, "to": "mm"},
8563   "name": "SPI_PERFCOUNTER5_LO",
8564   "type_ref": "CB_PERFCOUNTER0_LO"
8565  },
8566  {
8567   "chips": ["gfx81"],
8568   "map": {"at": 214784, "to": "mm"},
8569   "name": "SQ_PERFCOUNTER0_LO",
8570   "type_ref": "CB_PERFCOUNTER0_LO"
8571  },
8572  {
8573   "chips": ["gfx81"],
8574   "map": {"at": 214788, "to": "mm"},
8575   "name": "SQ_PERFCOUNTER0_HI",
8576   "type_ref": "CB_PERFCOUNTER0_HI"
8577  },
8578  {
8579   "chips": ["gfx81"],
8580   "map": {"at": 214792, "to": "mm"},
8581   "name": "SQ_PERFCOUNTER1_LO",
8582   "type_ref": "CB_PERFCOUNTER0_LO"
8583  },
8584  {
8585   "chips": ["gfx81"],
8586   "map": {"at": 214796, "to": "mm"},
8587   "name": "SQ_PERFCOUNTER1_HI",
8588   "type_ref": "CB_PERFCOUNTER0_HI"
8589  },
8590  {
8591   "chips": ["gfx81"],
8592   "map": {"at": 214800, "to": "mm"},
8593   "name": "SQ_PERFCOUNTER2_LO",
8594   "type_ref": "CB_PERFCOUNTER0_LO"
8595  },
8596  {
8597   "chips": ["gfx81"],
8598   "map": {"at": 214804, "to": "mm"},
8599   "name": "SQ_PERFCOUNTER2_HI",
8600   "type_ref": "CB_PERFCOUNTER0_HI"
8601  },
8602  {
8603   "chips": ["gfx81"],
8604   "map": {"at": 214808, "to": "mm"},
8605   "name": "SQ_PERFCOUNTER3_LO",
8606   "type_ref": "CB_PERFCOUNTER0_LO"
8607  },
8608  {
8609   "chips": ["gfx81"],
8610   "map": {"at": 214812, "to": "mm"},
8611   "name": "SQ_PERFCOUNTER3_HI",
8612   "type_ref": "CB_PERFCOUNTER0_HI"
8613  },
8614  {
8615   "chips": ["gfx81"],
8616   "map": {"at": 214816, "to": "mm"},
8617   "name": "SQ_PERFCOUNTER4_LO",
8618   "type_ref": "CB_PERFCOUNTER0_LO"
8619  },
8620  {
8621   "chips": ["gfx81"],
8622   "map": {"at": 214820, "to": "mm"},
8623   "name": "SQ_PERFCOUNTER4_HI",
8624   "type_ref": "CB_PERFCOUNTER0_HI"
8625  },
8626  {
8627   "chips": ["gfx81"],
8628   "map": {"at": 214824, "to": "mm"},
8629   "name": "SQ_PERFCOUNTER5_LO",
8630   "type_ref": "CB_PERFCOUNTER0_LO"
8631  },
8632  {
8633   "chips": ["gfx81"],
8634   "map": {"at": 214828, "to": "mm"},
8635   "name": "SQ_PERFCOUNTER5_HI",
8636   "type_ref": "CB_PERFCOUNTER0_HI"
8637  },
8638  {
8639   "chips": ["gfx81"],
8640   "map": {"at": 214832, "to": "mm"},
8641   "name": "SQ_PERFCOUNTER6_LO",
8642   "type_ref": "CB_PERFCOUNTER0_LO"
8643  },
8644  {
8645   "chips": ["gfx81"],
8646   "map": {"at": 214836, "to": "mm"},
8647   "name": "SQ_PERFCOUNTER6_HI",
8648   "type_ref": "CB_PERFCOUNTER0_HI"
8649  },
8650  {
8651   "chips": ["gfx81"],
8652   "map": {"at": 214840, "to": "mm"},
8653   "name": "SQ_PERFCOUNTER7_LO",
8654   "type_ref": "CB_PERFCOUNTER0_LO"
8655  },
8656  {
8657   "chips": ["gfx81"],
8658   "map": {"at": 214844, "to": "mm"},
8659   "name": "SQ_PERFCOUNTER7_HI",
8660   "type_ref": "CB_PERFCOUNTER0_HI"
8661  },
8662  {
8663   "chips": ["gfx81"],
8664   "map": {"at": 214848, "to": "mm"},
8665   "name": "SQ_PERFCOUNTER8_LO",
8666   "type_ref": "CB_PERFCOUNTER0_LO"
8667  },
8668  {
8669   "chips": ["gfx81"],
8670   "map": {"at": 214852, "to": "mm"},
8671   "name": "SQ_PERFCOUNTER8_HI",
8672   "type_ref": "CB_PERFCOUNTER0_HI"
8673  },
8674  {
8675   "chips": ["gfx81"],
8676   "map": {"at": 214856, "to": "mm"},
8677   "name": "SQ_PERFCOUNTER9_LO",
8678   "type_ref": "CB_PERFCOUNTER0_LO"
8679  },
8680  {
8681   "chips": ["gfx81"],
8682   "map": {"at": 214860, "to": "mm"},
8683   "name": "SQ_PERFCOUNTER9_HI",
8684   "type_ref": "CB_PERFCOUNTER0_HI"
8685  },
8686  {
8687   "chips": ["gfx81"],
8688   "map": {"at": 214864, "to": "mm"},
8689   "name": "SQ_PERFCOUNTER10_LO",
8690   "type_ref": "CB_PERFCOUNTER0_LO"
8691  },
8692  {
8693   "chips": ["gfx81"],
8694   "map": {"at": 214868, "to": "mm"},
8695   "name": "SQ_PERFCOUNTER10_HI",
8696   "type_ref": "CB_PERFCOUNTER0_HI"
8697  },
8698  {
8699   "chips": ["gfx81"],
8700   "map": {"at": 214872, "to": "mm"},
8701   "name": "SQ_PERFCOUNTER11_LO",
8702   "type_ref": "CB_PERFCOUNTER0_LO"
8703  },
8704  {
8705   "chips": ["gfx81"],
8706   "map": {"at": 214876, "to": "mm"},
8707   "name": "SQ_PERFCOUNTER11_HI",
8708   "type_ref": "CB_PERFCOUNTER0_HI"
8709  },
8710  {
8711   "chips": ["gfx81"],
8712   "map": {"at": 214880, "to": "mm"},
8713   "name": "SQ_PERFCOUNTER12_LO",
8714   "type_ref": "CB_PERFCOUNTER0_LO"
8715  },
8716  {
8717   "chips": ["gfx81"],
8718   "map": {"at": 214884, "to": "mm"},
8719   "name": "SQ_PERFCOUNTER12_HI",
8720   "type_ref": "CB_PERFCOUNTER0_HI"
8721  },
8722  {
8723   "chips": ["gfx81"],
8724   "map": {"at": 214888, "to": "mm"},
8725   "name": "SQ_PERFCOUNTER13_LO",
8726   "type_ref": "CB_PERFCOUNTER0_LO"
8727  },
8728  {
8729   "chips": ["gfx81"],
8730   "map": {"at": 214892, "to": "mm"},
8731   "name": "SQ_PERFCOUNTER13_HI",
8732   "type_ref": "CB_PERFCOUNTER0_HI"
8733  },
8734  {
8735   "chips": ["gfx81"],
8736   "map": {"at": 214896, "to": "mm"},
8737   "name": "SQ_PERFCOUNTER14_LO",
8738   "type_ref": "CB_PERFCOUNTER0_LO"
8739  },
8740  {
8741   "chips": ["gfx81"],
8742   "map": {"at": 214900, "to": "mm"},
8743   "name": "SQ_PERFCOUNTER14_HI",
8744   "type_ref": "CB_PERFCOUNTER0_HI"
8745  },
8746  {
8747   "chips": ["gfx81"],
8748   "map": {"at": 214904, "to": "mm"},
8749   "name": "SQ_PERFCOUNTER15_LO",
8750   "type_ref": "CB_PERFCOUNTER0_LO"
8751  },
8752  {
8753   "chips": ["gfx81"],
8754   "map": {"at": 214908, "to": "mm"},
8755   "name": "SQ_PERFCOUNTER15_HI",
8756   "type_ref": "CB_PERFCOUNTER0_HI"
8757  },
8758  {
8759   "chips": ["gfx81"],
8760   "map": {"at": 215296, "to": "mm"},
8761   "name": "SX_PERFCOUNTER0_LO",
8762   "type_ref": "CB_PERFCOUNTER0_LO"
8763  },
8764  {
8765   "chips": ["gfx81"],
8766   "map": {"at": 215300, "to": "mm"},
8767   "name": "SX_PERFCOUNTER0_HI",
8768   "type_ref": "CB_PERFCOUNTER0_HI"
8769  },
8770  {
8771   "chips": ["gfx81"],
8772   "map": {"at": 215304, "to": "mm"},
8773   "name": "SX_PERFCOUNTER1_LO",
8774   "type_ref": "CB_PERFCOUNTER0_LO"
8775  },
8776  {
8777   "chips": ["gfx81"],
8778   "map": {"at": 215308, "to": "mm"},
8779   "name": "SX_PERFCOUNTER1_HI",
8780   "type_ref": "CB_PERFCOUNTER0_HI"
8781  },
8782  {
8783   "chips": ["gfx81"],
8784   "map": {"at": 215312, "to": "mm"},
8785   "name": "SX_PERFCOUNTER2_LO",
8786   "type_ref": "CB_PERFCOUNTER0_LO"
8787  },
8788  {
8789   "chips": ["gfx81"],
8790   "map": {"at": 215316, "to": "mm"},
8791   "name": "SX_PERFCOUNTER2_HI",
8792   "type_ref": "CB_PERFCOUNTER0_HI"
8793  },
8794  {
8795   "chips": ["gfx81"],
8796   "map": {"at": 215320, "to": "mm"},
8797   "name": "SX_PERFCOUNTER3_LO",
8798   "type_ref": "CB_PERFCOUNTER0_LO"
8799  },
8800  {
8801   "chips": ["gfx81"],
8802   "map": {"at": 215324, "to": "mm"},
8803   "name": "SX_PERFCOUNTER3_HI",
8804   "type_ref": "CB_PERFCOUNTER0_HI"
8805  },
8806  {
8807   "chips": ["gfx81"],
8808   "map": {"at": 215552, "to": "mm"},
8809   "name": "GDS_PERFCOUNTER0_LO",
8810   "type_ref": "CB_PERFCOUNTER0_LO"
8811  },
8812  {
8813   "chips": ["gfx81"],
8814   "map": {"at": 215556, "to": "mm"},
8815   "name": "GDS_PERFCOUNTER0_HI",
8816   "type_ref": "CB_PERFCOUNTER0_HI"
8817  },
8818  {
8819   "chips": ["gfx81"],
8820   "map": {"at": 215560, "to": "mm"},
8821   "name": "GDS_PERFCOUNTER1_LO",
8822   "type_ref": "CB_PERFCOUNTER0_LO"
8823  },
8824  {
8825   "chips": ["gfx81"],
8826   "map": {"at": 215564, "to": "mm"},
8827   "name": "GDS_PERFCOUNTER1_HI",
8828   "type_ref": "CB_PERFCOUNTER0_HI"
8829  },
8830  {
8831   "chips": ["gfx81"],
8832   "map": {"at": 215568, "to": "mm"},
8833   "name": "GDS_PERFCOUNTER2_LO",
8834   "type_ref": "CB_PERFCOUNTER0_LO"
8835  },
8836  {
8837   "chips": ["gfx81"],
8838   "map": {"at": 215572, "to": "mm"},
8839   "name": "GDS_PERFCOUNTER2_HI",
8840   "type_ref": "CB_PERFCOUNTER0_HI"
8841  },
8842  {
8843   "chips": ["gfx81"],
8844   "map": {"at": 215576, "to": "mm"},
8845   "name": "GDS_PERFCOUNTER3_LO",
8846   "type_ref": "CB_PERFCOUNTER0_LO"
8847  },
8848  {
8849   "chips": ["gfx81"],
8850   "map": {"at": 215580, "to": "mm"},
8851   "name": "GDS_PERFCOUNTER3_HI",
8852   "type_ref": "CB_PERFCOUNTER0_HI"
8853  },
8854  {
8855   "chips": ["gfx81"],
8856   "map": {"at": 215808, "to": "mm"},
8857   "name": "TA_PERFCOUNTER0_LO",
8858   "type_ref": "CB_PERFCOUNTER0_LO"
8859  },
8860  {
8861   "chips": ["gfx81"],
8862   "map": {"at": 215812, "to": "mm"},
8863   "name": "TA_PERFCOUNTER0_HI",
8864   "type_ref": "CB_PERFCOUNTER0_HI"
8865  },
8866  {
8867   "chips": ["gfx81"],
8868   "map": {"at": 215816, "to": "mm"},
8869   "name": "TA_PERFCOUNTER1_LO",
8870   "type_ref": "CB_PERFCOUNTER0_LO"
8871  },
8872  {
8873   "chips": ["gfx81"],
8874   "map": {"at": 215820, "to": "mm"},
8875   "name": "TA_PERFCOUNTER1_HI",
8876   "type_ref": "CB_PERFCOUNTER0_HI"
8877  },
8878  {
8879   "chips": ["gfx81"],
8880   "map": {"at": 216064, "to": "mm"},
8881   "name": "TD_PERFCOUNTER0_LO",
8882   "type_ref": "CB_PERFCOUNTER0_LO"
8883  },
8884  {
8885   "chips": ["gfx81"],
8886   "map": {"at": 216068, "to": "mm"},
8887   "name": "TD_PERFCOUNTER0_HI",
8888   "type_ref": "CB_PERFCOUNTER0_HI"
8889  },
8890  {
8891   "chips": ["gfx81"],
8892   "map": {"at": 216072, "to": "mm"},
8893   "name": "TD_PERFCOUNTER1_LO",
8894   "type_ref": "CB_PERFCOUNTER0_LO"
8895  },
8896  {
8897   "chips": ["gfx81"],
8898   "map": {"at": 216076, "to": "mm"},
8899   "name": "TD_PERFCOUNTER1_HI",
8900   "type_ref": "CB_PERFCOUNTER0_HI"
8901  },
8902  {
8903   "chips": ["gfx81"],
8904   "map": {"at": 216320, "to": "mm"},
8905   "name": "TCP_PERFCOUNTER0_LO",
8906   "type_ref": "CB_PERFCOUNTER0_LO"
8907  },
8908  {
8909   "chips": ["gfx81"],
8910   "map": {"at": 216324, "to": "mm"},
8911   "name": "TCP_PERFCOUNTER0_HI",
8912   "type_ref": "CB_PERFCOUNTER0_HI"
8913  },
8914  {
8915   "chips": ["gfx81"],
8916   "map": {"at": 216328, "to": "mm"},
8917   "name": "TCP_PERFCOUNTER1_LO",
8918   "type_ref": "CB_PERFCOUNTER0_LO"
8919  },
8920  {
8921   "chips": ["gfx81"],
8922   "map": {"at": 216332, "to": "mm"},
8923   "name": "TCP_PERFCOUNTER1_HI",
8924   "type_ref": "CB_PERFCOUNTER0_HI"
8925  },
8926  {
8927   "chips": ["gfx81"],
8928   "map": {"at": 216336, "to": "mm"},
8929   "name": "TCP_PERFCOUNTER2_LO",
8930   "type_ref": "CB_PERFCOUNTER0_LO"
8931  },
8932  {
8933   "chips": ["gfx81"],
8934   "map": {"at": 216340, "to": "mm"},
8935   "name": "TCP_PERFCOUNTER2_HI",
8936   "type_ref": "CB_PERFCOUNTER0_HI"
8937  },
8938  {
8939   "chips": ["gfx81"],
8940   "map": {"at": 216344, "to": "mm"},
8941   "name": "TCP_PERFCOUNTER3_LO",
8942   "type_ref": "CB_PERFCOUNTER0_LO"
8943  },
8944  {
8945   "chips": ["gfx81"],
8946   "map": {"at": 216348, "to": "mm"},
8947   "name": "TCP_PERFCOUNTER3_HI",
8948   "type_ref": "CB_PERFCOUNTER0_HI"
8949  },
8950  {
8951   "chips": ["gfx81"],
8952   "map": {"at": 216576, "to": "mm"},
8953   "name": "TCC_PERFCOUNTER0_LO",
8954   "type_ref": "CB_PERFCOUNTER0_LO"
8955  },
8956  {
8957   "chips": ["gfx81"],
8958   "map": {"at": 216580, "to": "mm"},
8959   "name": "TCC_PERFCOUNTER0_HI",
8960   "type_ref": "CB_PERFCOUNTER0_HI"
8961  },
8962  {
8963   "chips": ["gfx81"],
8964   "map": {"at": 216584, "to": "mm"},
8965   "name": "TCC_PERFCOUNTER1_LO",
8966   "type_ref": "CB_PERFCOUNTER0_LO"
8967  },
8968  {
8969   "chips": ["gfx81"],
8970   "map": {"at": 216588, "to": "mm"},
8971   "name": "TCC_PERFCOUNTER1_HI",
8972   "type_ref": "CB_PERFCOUNTER0_HI"
8973  },
8974  {
8975   "chips": ["gfx81"],
8976   "map": {"at": 216592, "to": "mm"},
8977   "name": "TCC_PERFCOUNTER2_LO",
8978   "type_ref": "CB_PERFCOUNTER0_LO"
8979  },
8980  {
8981   "chips": ["gfx81"],
8982   "map": {"at": 216596, "to": "mm"},
8983   "name": "TCC_PERFCOUNTER2_HI",
8984   "type_ref": "CB_PERFCOUNTER0_HI"
8985  },
8986  {
8987   "chips": ["gfx81"],
8988   "map": {"at": 216600, "to": "mm"},
8989   "name": "TCC_PERFCOUNTER3_LO",
8990   "type_ref": "CB_PERFCOUNTER0_LO"
8991  },
8992  {
8993   "chips": ["gfx81"],
8994   "map": {"at": 216604, "to": "mm"},
8995   "name": "TCC_PERFCOUNTER3_HI",
8996   "type_ref": "CB_PERFCOUNTER0_HI"
8997  },
8998  {
8999   "chips": ["gfx81"],
9000   "map": {"at": 216640, "to": "mm"},
9001   "name": "TCA_PERFCOUNTER0_LO",
9002   "type_ref": "CB_PERFCOUNTER0_LO"
9003  },
9004  {
9005   "chips": ["gfx81"],
9006   "map": {"at": 216644, "to": "mm"},
9007   "name": "TCA_PERFCOUNTER0_HI",
9008   "type_ref": "CB_PERFCOUNTER0_HI"
9009  },
9010  {
9011   "chips": ["gfx81"],
9012   "map": {"at": 216648, "to": "mm"},
9013   "name": "TCA_PERFCOUNTER1_LO",
9014   "type_ref": "CB_PERFCOUNTER0_LO"
9015  },
9016  {
9017   "chips": ["gfx81"],
9018   "map": {"at": 216652, "to": "mm"},
9019   "name": "TCA_PERFCOUNTER1_HI",
9020   "type_ref": "CB_PERFCOUNTER0_HI"
9021  },
9022  {
9023   "chips": ["gfx81"],
9024   "map": {"at": 216656, "to": "mm"},
9025   "name": "TCA_PERFCOUNTER2_LO",
9026   "type_ref": "CB_PERFCOUNTER0_LO"
9027  },
9028  {
9029   "chips": ["gfx81"],
9030   "map": {"at": 216660, "to": "mm"},
9031   "name": "TCA_PERFCOUNTER2_HI",
9032   "type_ref": "CB_PERFCOUNTER0_HI"
9033  },
9034  {
9035   "chips": ["gfx81"],
9036   "map": {"at": 216664, "to": "mm"},
9037   "name": "TCA_PERFCOUNTER3_LO",
9038   "type_ref": "CB_PERFCOUNTER0_LO"
9039  },
9040  {
9041   "chips": ["gfx81"],
9042   "map": {"at": 216668, "to": "mm"},
9043   "name": "TCA_PERFCOUNTER3_HI",
9044   "type_ref": "CB_PERFCOUNTER0_HI"
9045  },
9046  {
9047   "chips": ["gfx81"],
9048   "map": {"at": 217112, "to": "mm"},
9049   "name": "CB_PERFCOUNTER0_LO",
9050   "type_ref": "CB_PERFCOUNTER0_LO"
9051  },
9052  {
9053   "chips": ["gfx81"],
9054   "map": {"at": 217116, "to": "mm"},
9055   "name": "CB_PERFCOUNTER0_HI",
9056   "type_ref": "CB_PERFCOUNTER0_HI"
9057  },
9058  {
9059   "chips": ["gfx81"],
9060   "map": {"at": 217120, "to": "mm"},
9061   "name": "CB_PERFCOUNTER1_LO",
9062   "type_ref": "CB_PERFCOUNTER0_LO"
9063  },
9064  {
9065   "chips": ["gfx81"],
9066   "map": {"at": 217124, "to": "mm"},
9067   "name": "CB_PERFCOUNTER1_HI",
9068   "type_ref": "CB_PERFCOUNTER0_HI"
9069  },
9070  {
9071   "chips": ["gfx81"],
9072   "map": {"at": 217128, "to": "mm"},
9073   "name": "CB_PERFCOUNTER2_LO",
9074   "type_ref": "CB_PERFCOUNTER0_LO"
9075  },
9076  {
9077   "chips": ["gfx81"],
9078   "map": {"at": 217132, "to": "mm"},
9079   "name": "CB_PERFCOUNTER2_HI",
9080   "type_ref": "CB_PERFCOUNTER0_HI"
9081  },
9082  {
9083   "chips": ["gfx81"],
9084   "map": {"at": 217136, "to": "mm"},
9085   "name": "CB_PERFCOUNTER3_LO",
9086   "type_ref": "CB_PERFCOUNTER0_LO"
9087  },
9088  {
9089   "chips": ["gfx81"],
9090   "map": {"at": 217140, "to": "mm"},
9091   "name": "CB_PERFCOUNTER3_HI",
9092   "type_ref": "CB_PERFCOUNTER0_HI"
9093  },
9094  {
9095   "chips": ["gfx81"],
9096   "map": {"at": 217344, "to": "mm"},
9097   "name": "DB_PERFCOUNTER0_LO",
9098   "type_ref": "CB_PERFCOUNTER0_LO"
9099  },
9100  {
9101   "chips": ["gfx81"],
9102   "map": {"at": 217348, "to": "mm"},
9103   "name": "DB_PERFCOUNTER0_HI",
9104   "type_ref": "CB_PERFCOUNTER0_HI"
9105  },
9106  {
9107   "chips": ["gfx81"],
9108   "map": {"at": 217352, "to": "mm"},
9109   "name": "DB_PERFCOUNTER1_LO",
9110   "type_ref": "CB_PERFCOUNTER0_LO"
9111  },
9112  {
9113   "chips": ["gfx81"],
9114   "map": {"at": 217356, "to": "mm"},
9115   "name": "DB_PERFCOUNTER1_HI",
9116   "type_ref": "CB_PERFCOUNTER0_HI"
9117  },
9118  {
9119   "chips": ["gfx81"],
9120   "map": {"at": 217360, "to": "mm"},
9121   "name": "DB_PERFCOUNTER2_LO",
9122   "type_ref": "CB_PERFCOUNTER0_LO"
9123  },
9124  {
9125   "chips": ["gfx81"],
9126   "map": {"at": 217364, "to": "mm"},
9127   "name": "DB_PERFCOUNTER2_HI",
9128   "type_ref": "CB_PERFCOUNTER0_HI"
9129  },
9130  {
9131   "chips": ["gfx81"],
9132   "map": {"at": 217368, "to": "mm"},
9133   "name": "DB_PERFCOUNTER3_LO",
9134   "type_ref": "CB_PERFCOUNTER0_LO"
9135  },
9136  {
9137   "chips": ["gfx81"],
9138   "map": {"at": 217372, "to": "mm"},
9139   "name": "DB_PERFCOUNTER3_HI",
9140   "type_ref": "CB_PERFCOUNTER0_HI"
9141  },
9142  {
9143   "chips": ["gfx81"],
9144   "map": {"at": 217600, "to": "mm"},
9145   "name": "RLC_PERFCOUNTER0_LO",
9146   "type_ref": "CB_PERFCOUNTER0_LO"
9147  },
9148  {
9149   "chips": ["gfx81"],
9150   "map": {"at": 217604, "to": "mm"},
9151   "name": "RLC_PERFCOUNTER0_HI",
9152   "type_ref": "CB_PERFCOUNTER0_HI"
9153  },
9154  {
9155   "chips": ["gfx81"],
9156   "map": {"at": 217608, "to": "mm"},
9157   "name": "RLC_PERFCOUNTER1_LO",
9158   "type_ref": "CB_PERFCOUNTER0_LO"
9159  },
9160  {
9161   "chips": ["gfx81"],
9162   "map": {"at": 217612, "to": "mm"},
9163   "name": "RLC_PERFCOUNTER1_HI",
9164   "type_ref": "CB_PERFCOUNTER0_HI"
9165  },
9166  {
9167   "chips": ["gfx81"],
9168   "map": {"at": 221184, "to": "mm"},
9169   "name": "CPG_PERFCOUNTER1_SELECT",
9170   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9171  },
9172  {
9173   "chips": ["gfx81"],
9174   "map": {"at": 221188, "to": "mm"},
9175   "name": "CPG_PERFCOUNTER0_SELECT1",
9176   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9177  },
9178  {
9179   "chips": ["gfx81"],
9180   "map": {"at": 221192, "to": "mm"},
9181   "name": "CPG_PERFCOUNTER0_SELECT",
9182   "type_ref": "CPG_PERFCOUNTER0_SELECT"
9183  },
9184  {
9185   "chips": ["gfx81"],
9186   "map": {"at": 221196, "to": "mm"},
9187   "name": "CPC_PERFCOUNTER1_SELECT",
9188   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9189  },
9190  {
9191   "chips": ["gfx81"],
9192   "map": {"at": 221200, "to": "mm"},
9193   "name": "CPC_PERFCOUNTER0_SELECT1",
9194   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9195  },
9196  {
9197   "chips": ["gfx81"],
9198   "map": {"at": 221204, "to": "mm"},
9199   "name": "CPF_PERFCOUNTER1_SELECT",
9200   "type_ref": "CPG_PERFCOUNTER1_SELECT"
9201  },
9202  {
9203   "chips": ["gfx81"],
9204   "map": {"at": 221208, "to": "mm"},
9205   "name": "CPF_PERFCOUNTER0_SELECT1",
9206   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
9207  },
9208  {
9209   "chips": ["gfx81"],
9210   "map": {"at": 221212, "to": "mm"},
9211   "name": "CPF_PERFCOUNTER0_SELECT",
9212   "type_ref": "CPG_PERFCOUNTER0_SELECT"
9213  },
9214  {
9215   "chips": ["gfx81"],
9216   "map": {"at": 221216, "to": "mm"},
9217   "name": "CP_PERFMON_CNTL",
9218   "type_ref": "CP_PERFMON_CNTL"
9219  },
9220  {
9221   "chips": ["gfx81"],
9222   "map": {"at": 221220, "to": "mm"},
9223   "name": "CPC_PERFCOUNTER0_SELECT",
9224   "type_ref": "CPG_PERFCOUNTER0_SELECT"
9225  },
9226  {
9227   "chips": ["gfx81"],
9228   "map": {"at": 221248, "to": "mm"},
9229   "name": "CP_DRAW_OBJECT",
9230   "type_ref": "CP_DRAW_OBJECT"
9231  },
9232  {
9233   "chips": ["gfx81"],
9234   "map": {"at": 221252, "to": "mm"},
9235   "name": "CP_DRAW_OBJECT_COUNTER",
9236   "type_ref": "CP_DRAW_OBJECT_COUNTER"
9237  },
9238  {
9239   "chips": ["gfx81"],
9240   "map": {"at": 221256, "to": "mm"},
9241   "name": "CP_DRAW_WINDOW_MASK_HI",
9242   "type_ref": "CP_DRAW_WINDOW_MASK_HI"
9243  },
9244  {
9245   "chips": ["gfx81"],
9246   "map": {"at": 221260, "to": "mm"},
9247   "name": "CP_DRAW_WINDOW_HI",
9248   "type_ref": "CP_DRAW_WINDOW_HI"
9249  },
9250  {
9251   "chips": ["gfx81"],
9252   "map": {"at": 221264, "to": "mm"},
9253   "name": "CP_DRAW_WINDOW_LO",
9254   "type_ref": "CP_DRAW_WINDOW_LO"
9255  },
9256  {
9257   "chips": ["gfx81"],
9258   "map": {"at": 221268, "to": "mm"},
9259   "name": "CP_DRAW_WINDOW_CNTL",
9260   "type_ref": "CP_DRAW_WINDOW_CNTL"
9261  },
9262  {
9263   "chips": ["gfx81"],
9264   "map": {"at": 221440, "to": "mm"},
9265   "name": "GRBM_PERFCOUNTER0_SELECT",
9266   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9267  },
9268  {
9269   "chips": ["gfx81"],
9270   "map": {"at": 221444, "to": "mm"},
9271   "name": "GRBM_PERFCOUNTER1_SELECT",
9272   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
9273  },
9274  {
9275   "chips": ["gfx81"],
9276   "map": {"at": 221448, "to": "mm"},
9277   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
9278   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9279  },
9280  {
9281   "chips": ["gfx81"],
9282   "map": {"at": 221452, "to": "mm"},
9283   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
9284   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9285  },
9286  {
9287   "chips": ["gfx81"],
9288   "map": {"at": 221456, "to": "mm"},
9289   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
9290   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9291  },
9292  {
9293   "chips": ["gfx81"],
9294   "map": {"at": 221460, "to": "mm"},
9295   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
9296   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9297  },
9298  {
9299   "chips": ["gfx81"],
9300   "map": {"at": 221696, "to": "mm"},
9301   "name": "WD_PERFCOUNTER0_SELECT",
9302   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9303  },
9304  {
9305   "chips": ["gfx81"],
9306   "map": {"at": 221700, "to": "mm"},
9307   "name": "WD_PERFCOUNTER1_SELECT",
9308   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9309  },
9310  {
9311   "chips": ["gfx81"],
9312   "map": {"at": 221704, "to": "mm"},
9313   "name": "WD_PERFCOUNTER2_SELECT",
9314   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9315  },
9316  {
9317   "chips": ["gfx81"],
9318   "map": {"at": 221708, "to": "mm"},
9319   "name": "WD_PERFCOUNTER3_SELECT",
9320   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9321  },
9322  {
9323   "chips": ["gfx81"],
9324   "map": {"at": 221712, "to": "mm"},
9325   "name": "IA_PERFCOUNTER0_SELECT",
9326   "type_ref": "DB_PERFCOUNTER0_SELECT"
9327  },
9328  {
9329   "chips": ["gfx81"],
9330   "map": {"at": 221716, "to": "mm"},
9331   "name": "IA_PERFCOUNTER1_SELECT",
9332   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9333  },
9334  {
9335   "chips": ["gfx81"],
9336   "map": {"at": 221720, "to": "mm"},
9337   "name": "IA_PERFCOUNTER2_SELECT",
9338   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9339  },
9340  {
9341   "chips": ["gfx81"],
9342   "map": {"at": 221724, "to": "mm"},
9343   "name": "IA_PERFCOUNTER3_SELECT",
9344   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9345  },
9346  {
9347   "chips": ["gfx81"],
9348   "map": {"at": 221728, "to": "mm"},
9349   "name": "IA_PERFCOUNTER0_SELECT1",
9350   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9351  },
9352  {
9353   "chips": ["gfx81"],
9354   "map": {"at": 221744, "to": "mm"},
9355   "name": "VGT_PERFCOUNTER0_SELECT",
9356   "type_ref": "DB_PERFCOUNTER0_SELECT"
9357  },
9358  {
9359   "chips": ["gfx81"],
9360   "map": {"at": 221748, "to": "mm"},
9361   "name": "VGT_PERFCOUNTER1_SELECT",
9362   "type_ref": "DB_PERFCOUNTER0_SELECT"
9363  },
9364  {
9365   "chips": ["gfx81"],
9366   "map": {"at": 221752, "to": "mm"},
9367   "name": "VGT_PERFCOUNTER2_SELECT",
9368   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9369  },
9370  {
9371   "chips": ["gfx81"],
9372   "map": {"at": 221756, "to": "mm"},
9373   "name": "VGT_PERFCOUNTER3_SELECT",
9374   "type_ref": "VGT_PERFCOUNTER2_SELECT"
9375  },
9376  {
9377   "chips": ["gfx81"],
9378   "map": {"at": 221760, "to": "mm"},
9379   "name": "VGT_PERFCOUNTER0_SELECT1",
9380   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9381  },
9382  {
9383   "chips": ["gfx81"],
9384   "map": {"at": 221764, "to": "mm"},
9385   "name": "VGT_PERFCOUNTER1_SELECT1",
9386   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9387  },
9388  {
9389   "chips": ["gfx81"],
9390   "map": {"at": 221776, "to": "mm"},
9391   "name": "VGT_PERFCOUNTER_SEID_MASK",
9392   "type_ref": "VGT_PERFCOUNTER_SEID_MASK"
9393  },
9394  {
9395   "chips": ["gfx81"],
9396   "map": {"at": 222208, "to": "mm"},
9397   "name": "PA_SU_PERFCOUNTER0_SELECT",
9398   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9399  },
9400  {
9401   "chips": ["gfx81"],
9402   "map": {"at": 222212, "to": "mm"},
9403   "name": "PA_SU_PERFCOUNTER0_SELECT1",
9404   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9405  },
9406  {
9407   "chips": ["gfx81"],
9408   "map": {"at": 222216, "to": "mm"},
9409   "name": "PA_SU_PERFCOUNTER1_SELECT",
9410   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9411  },
9412  {
9413   "chips": ["gfx81"],
9414   "map": {"at": 222220, "to": "mm"},
9415   "name": "PA_SU_PERFCOUNTER1_SELECT1",
9416   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9417  },
9418  {
9419   "chips": ["gfx81"],
9420   "map": {"at": 222224, "to": "mm"},
9421   "name": "PA_SU_PERFCOUNTER2_SELECT",
9422   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9423  },
9424  {
9425   "chips": ["gfx81"],
9426   "map": {"at": 222228, "to": "mm"},
9427   "name": "PA_SU_PERFCOUNTER3_SELECT",
9428   "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
9429  },
9430  {
9431   "chips": ["gfx81"],
9432   "map": {"at": 222464, "to": "mm"},
9433   "name": "PA_SC_PERFCOUNTER0_SELECT",
9434   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9435  },
9436  {
9437   "chips": ["gfx81"],
9438   "map": {"at": 222468, "to": "mm"},
9439   "name": "PA_SC_PERFCOUNTER0_SELECT1",
9440   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9441  },
9442  {
9443   "chips": ["gfx81"],
9444   "map": {"at": 222472, "to": "mm"},
9445   "name": "PA_SC_PERFCOUNTER1_SELECT",
9446   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9447  },
9448  {
9449   "chips": ["gfx81"],
9450   "map": {"at": 222476, "to": "mm"},
9451   "name": "PA_SC_PERFCOUNTER2_SELECT",
9452   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9453  },
9454  {
9455   "chips": ["gfx81"],
9456   "map": {"at": 222480, "to": "mm"},
9457   "name": "PA_SC_PERFCOUNTER3_SELECT",
9458   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9459  },
9460  {
9461   "chips": ["gfx81"],
9462   "map": {"at": 222484, "to": "mm"},
9463   "name": "PA_SC_PERFCOUNTER4_SELECT",
9464   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9465  },
9466  {
9467   "chips": ["gfx81"],
9468   "map": {"at": 222488, "to": "mm"},
9469   "name": "PA_SC_PERFCOUNTER5_SELECT",
9470   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9471  },
9472  {
9473   "chips": ["gfx81"],
9474   "map": {"at": 222492, "to": "mm"},
9475   "name": "PA_SC_PERFCOUNTER6_SELECT",
9476   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9477  },
9478  {
9479   "chips": ["gfx81"],
9480   "map": {"at": 222496, "to": "mm"},
9481   "name": "PA_SC_PERFCOUNTER7_SELECT",
9482   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9483  },
9484  {
9485   "chips": ["gfx81"],
9486   "map": {"at": 222720, "to": "mm"},
9487   "name": "SPI_PERFCOUNTER0_SELECT",
9488   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9489  },
9490  {
9491   "chips": ["gfx81"],
9492   "map": {"at": 222724, "to": "mm"},
9493   "name": "SPI_PERFCOUNTER1_SELECT",
9494   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9495  },
9496  {
9497   "chips": ["gfx81"],
9498   "map": {"at": 222728, "to": "mm"},
9499   "name": "SPI_PERFCOUNTER2_SELECT",
9500   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9501  },
9502  {
9503   "chips": ["gfx81"],
9504   "map": {"at": 222732, "to": "mm"},
9505   "name": "SPI_PERFCOUNTER3_SELECT",
9506   "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
9507  },
9508  {
9509   "chips": ["gfx81"],
9510   "map": {"at": 222736, "to": "mm"},
9511   "name": "SPI_PERFCOUNTER0_SELECT1",
9512   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9513  },
9514  {
9515   "chips": ["gfx81"],
9516   "map": {"at": 222740, "to": "mm"},
9517   "name": "SPI_PERFCOUNTER1_SELECT1",
9518   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9519  },
9520  {
9521   "chips": ["gfx81"],
9522   "map": {"at": 222744, "to": "mm"},
9523   "name": "SPI_PERFCOUNTER2_SELECT1",
9524   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9525  },
9526  {
9527   "chips": ["gfx81"],
9528   "map": {"at": 222748, "to": "mm"},
9529   "name": "SPI_PERFCOUNTER3_SELECT1",
9530   "type_ref": "PA_SU_PERFCOUNTER0_SELECT1"
9531  },
9532  {
9533   "chips": ["gfx81"],
9534   "map": {"at": 222752, "to": "mm"},
9535   "name": "SPI_PERFCOUNTER4_SELECT",
9536   "type_ref": "SPI_PERFCOUNTER4_SELECT"
9537  },
9538  {
9539   "chips": ["gfx81"],
9540   "map": {"at": 222756, "to": "mm"},
9541   "name": "SPI_PERFCOUNTER5_SELECT",
9542   "type_ref": "SPI_PERFCOUNTER4_SELECT"
9543  },
9544  {
9545   "chips": ["gfx81"],
9546   "map": {"at": 222760, "to": "mm"},
9547   "name": "SPI_PERFCOUNTER_BINS",
9548   "type_ref": "SPI_PERFCOUNTER_BINS"
9549  },
9550  {
9551   "chips": ["gfx81"],
9552   "map": {"at": 222976, "to": "mm"},
9553   "name": "SQ_PERFCOUNTER0_SELECT",
9554   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9555  },
9556  {
9557   "chips": ["gfx81"],
9558   "map": {"at": 222980, "to": "mm"},
9559   "name": "SQ_PERFCOUNTER1_SELECT",
9560   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9561  },
9562  {
9563   "chips": ["gfx81"],
9564   "map": {"at": 222984, "to": "mm"},
9565   "name": "SQ_PERFCOUNTER2_SELECT",
9566   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9567  },
9568  {
9569   "chips": ["gfx81"],
9570   "map": {"at": 222988, "to": "mm"},
9571   "name": "SQ_PERFCOUNTER3_SELECT",
9572   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9573  },
9574  {
9575   "chips": ["gfx81"],
9576   "map": {"at": 222992, "to": "mm"},
9577   "name": "SQ_PERFCOUNTER4_SELECT",
9578   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9579  },
9580  {
9581   "chips": ["gfx81"],
9582   "map": {"at": 222996, "to": "mm"},
9583   "name": "SQ_PERFCOUNTER5_SELECT",
9584   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9585  },
9586  {
9587   "chips": ["gfx81"],
9588   "map": {"at": 223000, "to": "mm"},
9589   "name": "SQ_PERFCOUNTER6_SELECT",
9590   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9591  },
9592  {
9593   "chips": ["gfx81"],
9594   "map": {"at": 223004, "to": "mm"},
9595   "name": "SQ_PERFCOUNTER7_SELECT",
9596   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9597  },
9598  {
9599   "chips": ["gfx81"],
9600   "map": {"at": 223008, "to": "mm"},
9601   "name": "SQ_PERFCOUNTER8_SELECT",
9602   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9603  },
9604  {
9605   "chips": ["gfx81"],
9606   "map": {"at": 223012, "to": "mm"},
9607   "name": "SQ_PERFCOUNTER9_SELECT",
9608   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9609  },
9610  {
9611   "chips": ["gfx81"],
9612   "map": {"at": 223016, "to": "mm"},
9613   "name": "SQ_PERFCOUNTER10_SELECT",
9614   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9615  },
9616  {
9617   "chips": ["gfx81"],
9618   "map": {"at": 223020, "to": "mm"},
9619   "name": "SQ_PERFCOUNTER11_SELECT",
9620   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9621  },
9622  {
9623   "chips": ["gfx81"],
9624   "map": {"at": 223024, "to": "mm"},
9625   "name": "SQ_PERFCOUNTER12_SELECT",
9626   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9627  },
9628  {
9629   "chips": ["gfx81"],
9630   "map": {"at": 223028, "to": "mm"},
9631   "name": "SQ_PERFCOUNTER13_SELECT",
9632   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9633  },
9634  {
9635   "chips": ["gfx81"],
9636   "map": {"at": 223032, "to": "mm"},
9637   "name": "SQ_PERFCOUNTER14_SELECT",
9638   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9639  },
9640  {
9641   "chips": ["gfx81"],
9642   "map": {"at": 223036, "to": "mm"},
9643   "name": "SQ_PERFCOUNTER15_SELECT",
9644   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9645  },
9646  {
9647   "chips": ["gfx81"],
9648   "map": {"at": 223104, "to": "mm"},
9649   "name": "SQ_PERFCOUNTER_CTRL",
9650   "type_ref": "SQ_PERFCOUNTER_CTRL"
9651  },
9652  {
9653   "chips": ["gfx81"],
9654   "map": {"at": 223108, "to": "mm"},
9655   "name": "SQ_PERFCOUNTER_MASK",
9656   "type_ref": "SQ_PERFCOUNTER_MASK"
9657  },
9658  {
9659   "chips": ["gfx81"],
9660   "map": {"at": 223112, "to": "mm"},
9661   "name": "SQ_PERFCOUNTER_CTRL2",
9662   "type_ref": "SQ_PERFCOUNTER_CTRL2"
9663  },
9664  {
9665   "chips": ["gfx81"],
9666   "map": {"at": 223488, "to": "mm"},
9667   "name": "SX_PERFCOUNTER0_SELECT",
9668   "type_ref": "SX_PERFCOUNTER0_SELECT"
9669  },
9670  {
9671   "chips": ["gfx81"],
9672   "map": {"at": 223492, "to": "mm"},
9673   "name": "SX_PERFCOUNTER1_SELECT",
9674   "type_ref": "SX_PERFCOUNTER0_SELECT"
9675  },
9676  {
9677   "chips": ["gfx81"],
9678   "map": {"at": 223496, "to": "mm"},
9679   "name": "SX_PERFCOUNTER2_SELECT",
9680   "type_ref": "SX_PERFCOUNTER0_SELECT"
9681  },
9682  {
9683   "chips": ["gfx81"],
9684   "map": {"at": 223500, "to": "mm"},
9685   "name": "SX_PERFCOUNTER3_SELECT",
9686   "type_ref": "SX_PERFCOUNTER0_SELECT"
9687  },
9688  {
9689   "chips": ["gfx81"],
9690   "map": {"at": 223504, "to": "mm"},
9691   "name": "SX_PERFCOUNTER0_SELECT1",
9692   "type_ref": "SX_PERFCOUNTER0_SELECT1"
9693  },
9694  {
9695   "chips": ["gfx81"],
9696   "map": {"at": 223508, "to": "mm"},
9697   "name": "SX_PERFCOUNTER1_SELECT1",
9698   "type_ref": "SX_PERFCOUNTER0_SELECT1"
9699  },
9700  {
9701   "chips": ["gfx81"],
9702   "map": {"at": 223744, "to": "mm"},
9703   "name": "GDS_PERFCOUNTER0_SELECT",
9704   "type_ref": "SX_PERFCOUNTER0_SELECT"
9705  },
9706  {
9707   "chips": ["gfx81"],
9708   "map": {"at": 223748, "to": "mm"},
9709   "name": "GDS_PERFCOUNTER1_SELECT",
9710   "type_ref": "SX_PERFCOUNTER0_SELECT"
9711  },
9712  {
9713   "chips": ["gfx81"],
9714   "map": {"at": 223752, "to": "mm"},
9715   "name": "GDS_PERFCOUNTER2_SELECT",
9716   "type_ref": "SX_PERFCOUNTER0_SELECT"
9717  },
9718  {
9719   "chips": ["gfx81"],
9720   "map": {"at": 223756, "to": "mm"},
9721   "name": "GDS_PERFCOUNTER3_SELECT",
9722   "type_ref": "SX_PERFCOUNTER0_SELECT"
9723  },
9724  {
9725   "chips": ["gfx81"],
9726   "map": {"at": 223760, "to": "mm"},
9727   "name": "GDS_PERFCOUNTER0_SELECT1",
9728   "type_ref": "SX_PERFCOUNTER0_SELECT1"
9729  },
9730  {
9731   "chips": ["gfx81"],
9732   "map": {"at": 224000, "to": "mm"},
9733   "name": "TA_PERFCOUNTER0_SELECT",
9734   "type_ref": "TD_PERFCOUNTER0_SELECT"
9735  },
9736  {
9737   "chips": ["gfx81"],
9738   "map": {"at": 224004, "to": "mm"},
9739   "name": "TA_PERFCOUNTER0_SELECT1",
9740   "type_ref": "TD_PERFCOUNTER0_SELECT1"
9741  },
9742  {
9743   "chips": ["gfx81"],
9744   "map": {"at": 224008, "to": "mm"},
9745   "name": "TA_PERFCOUNTER1_SELECT",
9746   "type_ref": "TD_PERFCOUNTER0_SELECT"
9747  },
9748  {
9749   "chips": ["gfx81"],
9750   "map": {"at": 224256, "to": "mm"},
9751   "name": "TD_PERFCOUNTER0_SELECT",
9752   "type_ref": "TD_PERFCOUNTER0_SELECT"
9753  },
9754  {
9755   "chips": ["gfx81"],
9756   "map": {"at": 224260, "to": "mm"},
9757   "name": "TD_PERFCOUNTER0_SELECT1",
9758   "type_ref": "TD_PERFCOUNTER0_SELECT1"
9759  },
9760  {
9761   "chips": ["gfx81"],
9762   "map": {"at": 224264, "to": "mm"},
9763   "name": "TD_PERFCOUNTER1_SELECT",
9764   "type_ref": "TD_PERFCOUNTER0_SELECT"
9765  },
9766  {
9767   "chips": ["gfx81"],
9768   "map": {"at": 224512, "to": "mm"},
9769   "name": "TCP_PERFCOUNTER0_SELECT",
9770   "type_ref": "DB_PERFCOUNTER0_SELECT"
9771  },
9772  {
9773   "chips": ["gfx81"],
9774   "map": {"at": 224516, "to": "mm"},
9775   "name": "TCP_PERFCOUNTER0_SELECT1",
9776   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9777  },
9778  {
9779   "chips": ["gfx81"],
9780   "map": {"at": 224520, "to": "mm"},
9781   "name": "TCP_PERFCOUNTER1_SELECT",
9782   "type_ref": "DB_PERFCOUNTER0_SELECT"
9783  },
9784  {
9785   "chips": ["gfx81"],
9786   "map": {"at": 224524, "to": "mm"},
9787   "name": "TCP_PERFCOUNTER1_SELECT1",
9788   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9789  },
9790  {
9791   "chips": ["gfx81"],
9792   "map": {"at": 224528, "to": "mm"},
9793   "name": "TCP_PERFCOUNTER2_SELECT",
9794   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9795  },
9796  {
9797   "chips": ["gfx81"],
9798   "map": {"at": 224532, "to": "mm"},
9799   "name": "TCP_PERFCOUNTER3_SELECT",
9800   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9801  },
9802  {
9803   "chips": ["gfx81"],
9804   "map": {"at": 224768, "to": "mm"},
9805   "name": "TCC_PERFCOUNTER0_SELECT",
9806   "type_ref": "DB_PERFCOUNTER0_SELECT"
9807  },
9808  {
9809   "chips": ["gfx81"],
9810   "map": {"at": 224772, "to": "mm"},
9811   "name": "TCC_PERFCOUNTER0_SELECT1",
9812   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9813  },
9814  {
9815   "chips": ["gfx81"],
9816   "map": {"at": 224776, "to": "mm"},
9817   "name": "TCC_PERFCOUNTER1_SELECT",
9818   "type_ref": "DB_PERFCOUNTER0_SELECT"
9819  },
9820  {
9821   "chips": ["gfx81"],
9822   "map": {"at": 224780, "to": "mm"},
9823   "name": "TCC_PERFCOUNTER1_SELECT1",
9824   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9825  },
9826  {
9827   "chips": ["gfx81"],
9828   "map": {"at": 224784, "to": "mm"},
9829   "name": "TCC_PERFCOUNTER2_SELECT",
9830   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9831  },
9832  {
9833   "chips": ["gfx81"],
9834   "map": {"at": 224788, "to": "mm"},
9835   "name": "TCC_PERFCOUNTER3_SELECT",
9836   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9837  },
9838  {
9839   "chips": ["gfx81"],
9840   "map": {"at": 224832, "to": "mm"},
9841   "name": "TCA_PERFCOUNTER0_SELECT",
9842   "type_ref": "DB_PERFCOUNTER0_SELECT"
9843  },
9844  {
9845   "chips": ["gfx81"],
9846   "map": {"at": 224836, "to": "mm"},
9847   "name": "TCA_PERFCOUNTER0_SELECT1",
9848   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9849  },
9850  {
9851   "chips": ["gfx81"],
9852   "map": {"at": 224840, "to": "mm"},
9853   "name": "TCA_PERFCOUNTER1_SELECT",
9854   "type_ref": "DB_PERFCOUNTER0_SELECT"
9855  },
9856  {
9857   "chips": ["gfx81"],
9858   "map": {"at": 224844, "to": "mm"},
9859   "name": "TCA_PERFCOUNTER1_SELECT1",
9860   "type_ref": "TCC_PERFCOUNTER0_SELECT1"
9861  },
9862  {
9863   "chips": ["gfx81"],
9864   "map": {"at": 224848, "to": "mm"},
9865   "name": "TCA_PERFCOUNTER2_SELECT",
9866   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9867  },
9868  {
9869   "chips": ["gfx81"],
9870   "map": {"at": 224852, "to": "mm"},
9871   "name": "TCA_PERFCOUNTER3_SELECT",
9872   "type_ref": "TCC_PERFCOUNTER2_SELECT"
9873  },
9874  {
9875   "chips": ["gfx81"],
9876   "map": {"at": 225280, "to": "mm"},
9877   "name": "CB_PERFCOUNTER_FILTER",
9878   "type_ref": "CB_PERFCOUNTER_FILTER"
9879  },
9880  {
9881   "chips": ["gfx81"],
9882   "map": {"at": 225284, "to": "mm"},
9883   "name": "CB_PERFCOUNTER0_SELECT",
9884   "type_ref": "CB_PERFCOUNTER0_SELECT"
9885  },
9886  {
9887   "chips": ["gfx81"],
9888   "map": {"at": 225288, "to": "mm"},
9889   "name": "CB_PERFCOUNTER0_SELECT1",
9890   "type_ref": "CB_PERFCOUNTER0_SELECT1"
9891  },
9892  {
9893   "chips": ["gfx81"],
9894   "map": {"at": 225292, "to": "mm"},
9895   "name": "CB_PERFCOUNTER1_SELECT",
9896   "type_ref": "CB_PERFCOUNTER1_SELECT"
9897  },
9898  {
9899   "chips": ["gfx81"],
9900   "map": {"at": 225296, "to": "mm"},
9901   "name": "CB_PERFCOUNTER2_SELECT",
9902   "type_ref": "CB_PERFCOUNTER1_SELECT"
9903  },
9904  {
9905   "chips": ["gfx81"],
9906   "map": {"at": 225300, "to": "mm"},
9907   "name": "CB_PERFCOUNTER3_SELECT",
9908   "type_ref": "CB_PERFCOUNTER1_SELECT"
9909  },
9910  {
9911   "chips": ["gfx81"],
9912   "map": {"at": 225536, "to": "mm"},
9913   "name": "DB_PERFCOUNTER0_SELECT",
9914   "type_ref": "DB_PERFCOUNTER0_SELECT"
9915  },
9916  {
9917   "chips": ["gfx81"],
9918   "map": {"at": 225540, "to": "mm"},
9919   "name": "DB_PERFCOUNTER0_SELECT1",
9920   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9921  },
9922  {
9923   "chips": ["gfx81"],
9924   "map": {"at": 225544, "to": "mm"},
9925   "name": "DB_PERFCOUNTER1_SELECT",
9926   "type_ref": "DB_PERFCOUNTER0_SELECT"
9927  },
9928  {
9929   "chips": ["gfx81"],
9930   "map": {"at": 225548, "to": "mm"},
9931   "name": "DB_PERFCOUNTER1_SELECT1",
9932   "type_ref": "DB_PERFCOUNTER0_SELECT1"
9933  },
9934  {
9935   "chips": ["gfx81"],
9936   "map": {"at": 225552, "to": "mm"},
9937   "name": "DB_PERFCOUNTER2_SELECT",
9938   "type_ref": "DB_PERFCOUNTER0_SELECT"
9939  },
9940  {
9941   "chips": ["gfx81"],
9942   "map": {"at": 225560, "to": "mm"},
9943   "name": "DB_PERFCOUNTER3_SELECT",
9944   "type_ref": "DB_PERFCOUNTER0_SELECT"
9945  },
9946  {
9947   "chips": ["gfx81"],
9948   "map": {"at": 225792, "to": "mm"},
9949   "name": "RLC_SPM_PERFMON_CNTL",
9950   "type_ref": "RLC_SPM_PERFMON_CNTL"
9951  },
9952  {
9953   "chips": ["gfx81"],
9954   "map": {"at": 225796, "to": "mm"},
9955   "name": "RLC_SPM_PERFMON_RING_BASE_LO",
9956   "type_ref": "RLC_SPM_PERFMON_RING_BASE_LO"
9957  },
9958  {
9959   "chips": ["gfx81"],
9960   "map": {"at": 225800, "to": "mm"},
9961   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
9962   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
9963  },
9964  {
9965   "chips": ["gfx81"],
9966   "map": {"at": 225804, "to": "mm"},
9967   "name": "RLC_SPM_PERFMON_RING_SIZE",
9968   "type_ref": "RLC_SPM_PERFMON_RING_SIZE"
9969  },
9970  {
9971   "chips": ["gfx81"],
9972   "map": {"at": 225808, "to": "mm"},
9973   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
9974   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
9975  },
9976  {
9977   "chips": ["gfx81"],
9978   "map": {"at": 225812, "to": "mm"},
9979   "name": "RLC_SPM_SE_MUXSEL_ADDR",
9980   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
9981  },
9982  {
9983   "chips": ["gfx81"],
9984   "map": {"at": 225816, "to": "mm"},
9985   "name": "RLC_SPM_SE_MUXSEL_DATA",
9986   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
9987  },
9988  {
9989   "chips": ["gfx81"],
9990   "map": {"at": 225820, "to": "mm"},
9991   "name": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY",
9992   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9993  },
9994  {
9995   "chips": ["gfx81"],
9996   "map": {"at": 225824, "to": "mm"},
9997   "name": "RLC_SPM_CPC_PERFMON_SAMPLE_DELAY",
9998   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
9999  },
10000  {
10001   "chips": ["gfx81"],
10002   "map": {"at": 225828, "to": "mm"},
10003   "name": "RLC_SPM_CPF_PERFMON_SAMPLE_DELAY",
10004   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10005  },
10006  {
10007   "chips": ["gfx81"],
10008   "map": {"at": 225832, "to": "mm"},
10009   "name": "RLC_SPM_CB_PERFMON_SAMPLE_DELAY",
10010   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10011  },
10012  {
10013   "chips": ["gfx81"],
10014   "map": {"at": 225836, "to": "mm"},
10015   "name": "RLC_SPM_DB_PERFMON_SAMPLE_DELAY",
10016   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10017  },
10018  {
10019   "chips": ["gfx81"],
10020   "map": {"at": 225840, "to": "mm"},
10021   "name": "RLC_SPM_PA_PERFMON_SAMPLE_DELAY",
10022   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10023  },
10024  {
10025   "chips": ["gfx81"],
10026   "map": {"at": 225844, "to": "mm"},
10027   "name": "RLC_SPM_GDS_PERFMON_SAMPLE_DELAY",
10028   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10029  },
10030  {
10031   "chips": ["gfx81"],
10032   "map": {"at": 225848, "to": "mm"},
10033   "name": "RLC_SPM_IA_PERFMON_SAMPLE_DELAY",
10034   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10035  },
10036  {
10037   "chips": ["gfx81"],
10038   "map": {"at": 225856, "to": "mm"},
10039   "name": "RLC_SPM_SC_PERFMON_SAMPLE_DELAY",
10040   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10041  },
10042  {
10043   "chips": ["gfx81"],
10044   "map": {"at": 225860, "to": "mm"},
10045   "name": "RLC_SPM_TCC_PERFMON_SAMPLE_DELAY",
10046   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10047  },
10048  {
10049   "chips": ["gfx81"],
10050   "map": {"at": 225864, "to": "mm"},
10051   "name": "RLC_SPM_TCA_PERFMON_SAMPLE_DELAY",
10052   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10053  },
10054  {
10055   "chips": ["gfx81"],
10056   "map": {"at": 225868, "to": "mm"},
10057   "name": "RLC_SPM_TCP_PERFMON_SAMPLE_DELAY",
10058   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10059  },
10060  {
10061   "chips": ["gfx81"],
10062   "map": {"at": 225872, "to": "mm"},
10063   "name": "RLC_SPM_TA_PERFMON_SAMPLE_DELAY",
10064   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10065  },
10066  {
10067   "chips": ["gfx81"],
10068   "map": {"at": 225876, "to": "mm"},
10069   "name": "RLC_SPM_TD_PERFMON_SAMPLE_DELAY",
10070   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10071  },
10072  {
10073   "chips": ["gfx81"],
10074   "map": {"at": 225880, "to": "mm"},
10075   "name": "RLC_SPM_VGT_PERFMON_SAMPLE_DELAY",
10076   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10077  },
10078  {
10079   "chips": ["gfx81"],
10080   "map": {"at": 225884, "to": "mm"},
10081   "name": "RLC_SPM_SPI_PERFMON_SAMPLE_DELAY",
10082   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10083  },
10084  {
10085   "chips": ["gfx81"],
10086   "map": {"at": 225888, "to": "mm"},
10087   "name": "RLC_SPM_SQG_PERFMON_SAMPLE_DELAY",
10088   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10089  },
10090  {
10091   "chips": ["gfx81"],
10092   "map": {"at": 225896, "to": "mm"},
10093   "name": "RLC_SPM_SX_PERFMON_SAMPLE_DELAY",
10094   "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY"
10095  },
10096  {
10097   "chips": ["gfx81"],
10098   "map": {"at": 225900, "to": "mm"},
10099   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
10100   "type_ref": "RLC_SPM_SE_MUXSEL_ADDR"
10101  },
10102  {
10103   "chips": ["gfx81"],
10104   "map": {"at": 225904, "to": "mm"},
10105   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA",
10106   "type_ref": "RLC_SPM_SE_MUXSEL_DATA"
10107  },
10108  {
10109   "chips": ["gfx81"],
10110   "map": {"at": 225908, "to": "mm"},
10111   "name": "RLC_SPM_RING_RDPTR",
10112   "type_ref": "RLC_SPM_RING_RDPTR"
10113  },
10114  {
10115   "chips": ["gfx81"],
10116   "map": {"at": 225912, "to": "mm"},
10117   "name": "RLC_SPM_SEGMENT_THRESHOLD",
10118   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
10119  },
10120  {
10121   "chips": ["gfx81"],
10122   "map": {"at": 226044, "to": "mm"},
10123   "name": "RLC_PERFMON_CLK_CNTL",
10124   "type_ref": "RLC_PERFMON_CLK_CNTL"
10125  },
10126  {
10127   "chips": ["gfx81"],
10128   "map": {"at": 226048, "to": "mm"},
10129   "name": "RLC_PERFMON_CNTL",
10130   "type_ref": "RLC_PERFMON_CNTL"
10131  },
10132  {
10133   "chips": ["gfx81"],
10134   "map": {"at": 226052, "to": "mm"},
10135   "name": "RLC_PERFCOUNTER0_SELECT",
10136   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10137  },
10138  {
10139   "chips": ["gfx81"],
10140   "map": {"at": 226056, "to": "mm"},
10141   "name": "RLC_PERFCOUNTER1_SELECT",
10142   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10143  }
10144 ],
10145 "register_types": {
10146  "CB_BLEND0_CONTROL": {
10147   "fields": [
10148    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
10149    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
10150    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
10151    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
10152    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
10153    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
10154    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
10155    {"bits": [30, 30], "name": "ENABLE"},
10156    {"bits": [31, 31], "name": "DISABLE_ROP3"}
10157   ]
10158  },
10159  "CB_BLEND_ALPHA": {
10160   "fields": [
10161    {"bits": [0, 31], "name": "BLEND_ALPHA"}
10162   ]
10163  },
10164  "CB_BLEND_BLUE": {
10165   "fields": [
10166    {"bits": [0, 31], "name": "BLEND_BLUE"}
10167   ]
10168  },
10169  "CB_BLEND_GREEN": {
10170   "fields": [
10171    {"bits": [0, 31], "name": "BLEND_GREEN"}
10172   ]
10173  },
10174  "CB_BLEND_RED": {
10175   "fields": [
10176    {"bits": [0, 31], "name": "BLEND_RED"}
10177   ]
10178  },
10179  "CB_COLOR0_ATTRIB": {
10180   "fields": [
10181    {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
10182    {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
10183    {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
10184    {"bits": [12, 14], "name": "NUM_SAMPLES"},
10185    {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
10186    {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}
10187   ]
10188  },
10189  "CB_COLOR0_BASE": {
10190   "fields": [
10191    {"bits": [0, 31], "name": "BASE_256B"}
10192   ]
10193  },
10194  "CB_COLOR0_CLEAR_WORD0": {
10195   "fields": [
10196    {"bits": [0, 31], "name": "CLEAR_WORD0"}
10197   ]
10198  },
10199  "CB_COLOR0_CLEAR_WORD1": {
10200   "fields": [
10201    {"bits": [0, 31], "name": "CLEAR_WORD1"}
10202   ]
10203  },
10204  "CB_COLOR0_CMASK_SLICE": {
10205   "fields": [
10206    {"bits": [0, 13], "name": "TILE_MAX"}
10207   ]
10208  },
10209  "CB_COLOR0_DCC_CONTROL": {
10210   "fields": [
10211    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
10212    {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"},
10213    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
10214    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
10215    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
10216    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
10217    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
10218    {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"},
10219    {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}
10220   ]
10221  },
10222  "CB_COLOR0_INFO": {
10223   "fields": [
10224    {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
10225    {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
10226    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
10227    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
10228    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
10229    {"bits": [13, 13], "name": "FAST_CLEAR"},
10230    {"bits": [14, 14], "name": "COMPRESSION"},
10231    {"bits": [15, 15], "name": "BLEND_CLAMP"},
10232    {"bits": [16, 16], "name": "BLEND_BYPASS"},
10233    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
10234    {"bits": [18, 18], "name": "ROUND_MODE"},
10235    {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
10236    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
10237    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
10238    {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"},
10239    {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"},
10240    {"bits": [28, 28], "name": "DCC_ENABLE"},
10241    {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}
10242   ]
10243  },
10244  "CB_COLOR0_PITCH": {
10245   "fields": [
10246    {"bits": [0, 10], "name": "TILE_MAX"},
10247    {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
10248   ]
10249  },
10250  "CB_COLOR0_SLICE": {
10251   "fields": [
10252    {"bits": [0, 21], "name": "TILE_MAX"}
10253   ]
10254  },
10255  "CB_COLOR0_VIEW": {
10256   "fields": [
10257    {"bits": [0, 10], "name": "SLICE_START"},
10258    {"bits": [13, 23], "name": "SLICE_MAX"}
10259   ]
10260  },
10261  "CB_COLOR_CONTROL": {
10262   "fields": [
10263    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
10264    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
10265    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
10266    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
10267   ]
10268  },
10269  "CB_DCC_CONTROL": {
10270   "fields": [
10271    {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"},
10272    {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"},
10273    {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}
10274   ]
10275  },
10276  "CB_PERFCOUNTER0_HI": {
10277   "fields": [
10278    {"bits": [0, 31], "name": "PERFCOUNTER_HI"}
10279   ]
10280  },
10281  "CB_PERFCOUNTER0_LO": {
10282   "fields": [
10283    {"bits": [0, 31], "name": "PERFCOUNTER_LO"}
10284   ]
10285  },
10286  "CB_PERFCOUNTER0_SELECT": {
10287   "fields": [
10288    {"bits": [0, 8], "name": "PERF_SEL"},
10289    {"bits": [10, 18], "name": "PERF_SEL1"},
10290    {"bits": [20, 23], "name": "CNTR_MODE"},
10291    {"bits": [24, 27], "name": "PERF_MODE1"},
10292    {"bits": [28, 31], "name": "PERF_MODE"}
10293   ]
10294  },
10295  "CB_PERFCOUNTER0_SELECT1": {
10296   "fields": [
10297    {"bits": [0, 8], "name": "PERF_SEL2"},
10298    {"bits": [10, 18], "name": "PERF_SEL3"},
10299    {"bits": [24, 27], "name": "PERF_MODE3"},
10300    {"bits": [28, 31], "name": "PERF_MODE2"}
10301   ]
10302  },
10303  "CB_PERFCOUNTER1_SELECT": {
10304   "fields": [
10305    {"bits": [0, 8], "name": "PERF_SEL"},
10306    {"bits": [28, 31], "name": "PERF_MODE"}
10307   ]
10308  },
10309  "CB_PERFCOUNTER_FILTER": {
10310   "fields": [
10311    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
10312    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
10313    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
10314    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
10315    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
10316    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
10317    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
10318    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
10319    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
10320    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
10321    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
10322    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
10323   ]
10324  },
10325  "CB_SHADER_MASK": {
10326   "fields": [
10327    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
10328    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
10329    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
10330    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
10331    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
10332    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
10333    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
10334    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
10335   ]
10336  },
10337  "CB_TARGET_MASK": {
10338   "fields": [
10339    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
10340    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
10341    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
10342    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
10343    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
10344    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
10345    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
10346    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
10347   ]
10348  },
10349  "COHER_DEST_BASE_0": {
10350   "fields": [
10351    {"bits": [0, 31], "name": "DEST_BASE_256B"}
10352   ]
10353  },
10354  "COHER_DEST_BASE_HI_0": {
10355   "fields": [
10356    {"bits": [0, 31], "name": "DEST_BASE_HI_256B"}
10357   ]
10358  },
10359  "COMPUTE_DIM_X": {
10360   "fields": [
10361    {"bits": [0, 31], "name": "SIZE"}
10362   ]
10363  },
10364  "COMPUTE_DISPATCH_ID": {
10365   "fields": [
10366    {"bits": [0, 31], "name": "DISPATCH_ID"}
10367   ]
10368  },
10369  "COMPUTE_DISPATCH_INITIATOR": {
10370   "fields": [
10371    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
10372    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
10373    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
10374    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
10375    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
10376    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
10377    {"bits": [6, 6], "name": "ORDER_MODE"},
10378    {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},
10379    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
10380    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
10381    {"bits": [12, 12], "name": "DATA_ATC"},
10382    {"bits": [14, 14], "name": "RESTORE"}
10383   ]
10384  },
10385  "COMPUTE_MISC_RESERVED": {
10386   "fields": [
10387    {"bits": [0, 1], "name": "SEND_SEID"},
10388    {"bits": [2, 2], "name": "RESERVED2"},
10389    {"bits": [3, 3], "name": "RESERVED3"},
10390    {"bits": [4, 4], "name": "RESERVED4"},
10391    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
10392   ]
10393  },
10394  "COMPUTE_NUM_THREAD_X": {
10395   "fields": [
10396    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
10397    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
10398   ]
10399  },
10400  "COMPUTE_PERFCOUNT_ENABLE": {
10401   "fields": [
10402    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
10403   ]
10404  },
10405  "COMPUTE_PGM_HI": {
10406   "fields": [
10407    {"bits": [0, 7], "name": "DATA"},
10408    {"bits": [8, 8], "name": "INST_ATC"}
10409   ]
10410  },
10411  "COMPUTE_PGM_RSRC1": {
10412   "fields": [
10413    {"bits": [0, 5], "name": "VGPRS"},
10414    {"bits": [6, 9], "name": "SGPRS"},
10415    {"bits": [10, 11], "name": "PRIORITY"},
10416    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10417    {"bits": [20, 20], "name": "PRIV"},
10418    {"bits": [21, 21], "name": "DX10_CLAMP"},
10419    {"bits": [22, 22], "name": "DEBUG_MODE"},
10420    {"bits": [23, 23], "name": "IEEE_MODE"},
10421    {"bits": [24, 24], "name": "BULKY"},
10422    {"bits": [25, 25], "name": "CDBG_USER"}
10423   ]
10424  },
10425  "COMPUTE_PGM_RSRC2": {
10426   "fields": [
10427    {"bits": [0, 0], "name": "SCRATCH_EN"},
10428    {"bits": [1, 5], "name": "USER_SGPR"},
10429    {"bits": [6, 6], "name": "TRAP_PRESENT"},
10430    {"bits": [7, 7], "name": "TGID_X_EN"},
10431    {"bits": [8, 8], "name": "TGID_Y_EN"},
10432    {"bits": [9, 9], "name": "TGID_Z_EN"},
10433    {"bits": [10, 10], "name": "TG_SIZE_EN"},
10434    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
10435    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
10436    {"bits": [15, 23], "name": "LDS_SIZE"},
10437    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10438   ]
10439  },
10440  "COMPUTE_PIPELINESTAT_ENABLE": {
10441   "fields": [
10442    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
10443   ]
10444  },
10445  "COMPUTE_RELAUNCH": {
10446   "fields": [
10447    {"bits": [0, 29], "name": "PAYLOAD"},
10448    {"bits": [30, 30], "name": "IS_EVENT"},
10449    {"bits": [31, 31], "name": "IS_STATE"}
10450   ]
10451  },
10452  "COMPUTE_RESOURCE_LIMITS": {
10453   "fields": [
10454    {"bits": [0, 9], "name": "WAVES_PER_SH"},
10455    {"bits": [12, 15], "name": "TG_PER_CU"},
10456    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
10457    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
10458    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
10459    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
10460   ]
10461  },
10462  "COMPUTE_RESTART_X": {
10463   "fields": [
10464    {"bits": [0, 31], "name": "RESTART"}
10465   ]
10466  },
10467  "COMPUTE_START_X": {
10468   "fields": [
10469    {"bits": [0, 31], "name": "START"}
10470   ]
10471  },
10472  "COMPUTE_STATIC_THREAD_MGMT_SE0": {
10473   "fields": [
10474    {"bits": [0, 15], "name": "SH0_CU_EN"},
10475    {"bits": [16, 31], "name": "SH1_CU_EN"}
10476   ]
10477  },
10478  "COMPUTE_TBA_HI": {
10479   "fields": [
10480    {"bits": [0, 7], "name": "DATA"}
10481   ]
10482  },
10483  "COMPUTE_THREADGROUP_ID": {
10484   "fields": [
10485    {"bits": [0, 31], "name": "THREADGROUP_ID"}
10486   ]
10487  },
10488  "COMPUTE_THREAD_TRACE_ENABLE": {
10489   "fields": [
10490    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
10491   ]
10492  },
10493  "COMPUTE_TMPRING_SIZE": {
10494   "fields": [
10495    {"bits": [0, 11], "name": "WAVES"},
10496    {"bits": [12, 24], "name": "WAVESIZE"}
10497   ]
10498  },
10499  "COMPUTE_VMID": {
10500   "fields": [
10501    {"bits": [0, 3], "name": "DATA"}
10502   ]
10503  },
10504  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
10505   "fields": [
10506    {"bits": [0, 15], "name": "ADDR"}
10507   ]
10508  },
10509  "COMPUTE_WAVE_RESTORE_ADDR_LO": {
10510   "fields": [
10511    {"bits": [0, 31], "name": "ADDR"}
10512   ]
10513  },
10514  "COMPUTE_WAVE_RESTORE_CONTROL": {
10515   "fields": [
10516    {"bits": [0, 0], "name": "ATC"},
10517    {"bits": [1, 2], "name": "MTYPE"}
10518   ]
10519  },
10520  "CPG_PERFCOUNTER0_SELECT": {
10521   "fields": [
10522    {"bits": [0, 5], "name": "PERF_SEL"},
10523    {"bits": [10, 15], "name": "PERF_SEL1"},
10524    {"bits": [20, 23], "name": "CNTR_MODE"}
10525   ]
10526  },
10527  "CPG_PERFCOUNTER0_SELECT1": {
10528   "fields": [
10529    {"bits": [0, 5], "name": "PERF_SEL2"},
10530    {"bits": [10, 15], "name": "PERF_SEL3"}
10531   ]
10532  },
10533  "CPG_PERFCOUNTER1_SELECT": {
10534   "fields": [
10535    {"bits": [0, 5], "name": "PERF_SEL"}
10536   ]
10537  },
10538  "CP_APPEND_ADDR_HI": {
10539   "fields": [
10540    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
10541    {"bits": [16, 16], "name": "CS_PS_SEL"},
10542    {"bits": [25, 25], "name": "CACHE_POLICY"},
10543    {"bits": [27, 28], "name": "MTYPE"},
10544    {"bits": [29, 31], "name": "COMMAND"}
10545   ]
10546  },
10547  "CP_APPEND_ADDR_LO": {
10548   "fields": [
10549    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
10550   ]
10551  },
10552  "CP_APPEND_DATA": {
10553   "fields": [
10554    {"bits": [0, 31], "name": "DATA"}
10555   ]
10556  },
10557  "CP_APPEND_LAST_CS_FENCE": {
10558   "fields": [
10559    {"bits": [0, 31], "name": "LAST_FENCE"}
10560   ]
10561  },
10562  "CP_CE_COUNTER": {
10563   "fields": [
10564    {"bits": [0, 31], "name": "CONST_ENGINE_COUNT"}
10565   ]
10566  },
10567  "CP_CE_IB1_BASE_HI": {
10568   "fields": [
10569    {"bits": [0, 15], "name": "IB1_BASE_HI"}
10570   ]
10571  },
10572  "CP_CE_IB1_BASE_LO": {
10573   "fields": [
10574    {"bits": [2, 31], "name": "IB1_BASE_LO"}
10575   ]
10576  },
10577  "CP_CE_IB1_BUFSZ": {
10578   "fields": [
10579    {"bits": [0, 19], "name": "IB1_BUFSZ"}
10580   ]
10581  },
10582  "CP_CE_IB2_BASE_HI": {
10583   "fields": [
10584    {"bits": [0, 15], "name": "IB2_BASE_HI"}
10585   ]
10586  },
10587  "CP_CE_IB2_BASE_LO": {
10588   "fields": [
10589    {"bits": [2, 31], "name": "IB2_BASE_LO"}
10590   ]
10591  },
10592  "CP_CE_IB2_BUFSZ": {
10593   "fields": [
10594    {"bits": [0, 19], "name": "IB2_BUFSZ"}
10595   ]
10596  },
10597  "CP_CE_INIT_BASE_HI": {
10598   "fields": [
10599    {"bits": [0, 15], "name": "INIT_BASE_HI"}
10600   ]
10601  },
10602  "CP_CE_INIT_BASE_LO": {
10603   "fields": [
10604    {"bits": [5, 31], "name": "INIT_BASE_LO"}
10605   ]
10606  },
10607  "CP_CE_INIT_BUFSZ": {
10608   "fields": [
10609    {"bits": [0, 11], "name": "INIT_BUFSZ"}
10610   ]
10611  },
10612  "CP_COHER_BASE": {
10613   "fields": [
10614    {"bits": [0, 31], "name": "COHER_BASE_256B"}
10615   ]
10616  },
10617  "CP_COHER_BASE_HI": {
10618   "fields": [
10619    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
10620   ]
10621  },
10622  "CP_COHER_CNTL": {
10623   "fields": [
10624    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
10625    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
10626    {"bits": [2, 2], "name": "TC_SD_ACTION_ENA"},
10627    {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"},
10628    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
10629    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
10630    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
10631    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
10632    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
10633    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
10634    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
10635    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
10636    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
10637    {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
10638    {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
10639    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
10640    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},
10641    {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
10642    {"bits": [23, 23], "name": "TC_ACTION_ENA"},
10643    {"bits": [25, 25], "name": "CB_ACTION_ENA"},
10644    {"bits": [26, 26], "name": "DB_ACTION_ENA"},
10645    {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
10646    {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
10647    {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"},
10648    {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"},
10649    {"bits": [31, 31], "name": "SH_SD_ACTION_ENA"}
10650   ]
10651  },
10652  "CP_COHER_SIZE": {
10653   "fields": [
10654    {"bits": [0, 31], "name": "COHER_SIZE_256B"}
10655   ]
10656  },
10657  "CP_COHER_SIZE_HI": {
10658   "fields": [
10659    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
10660   ]
10661  },
10662  "CP_COHER_START_DELAY": {
10663   "fields": [
10664    {"bits": [0, 5], "name": "START_DELAY_COUNT"}
10665   ]
10666  },
10667  "CP_COHER_STATUS": {
10668   "fields": [
10669    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
10670    {"bits": [24, 25], "name": "MEID"},
10671    {"bits": [30, 30], "name": "PHASE1_STATUS"},
10672    {"bits": [31, 31], "name": "STATUS"}
10673   ]
10674  },
10675  "CP_CPC_BUSY_STAT": {
10676   "fields": [
10677    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
10678    {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"},
10679    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
10680    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
10681    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
10682    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
10683    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
10684    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
10685    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
10686    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
10687    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
10688    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
10689    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
10690    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
10691    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
10692    {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"},
10693    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
10694    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
10695    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
10696    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
10697    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
10698    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
10699    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
10700    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
10701    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
10702    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
10703    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
10704    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
10705   ]
10706  },
10707  "CP_CPC_GRBM_FREE_COUNT": {
10708   "fields": [
10709    {"bits": [0, 5], "name": "FREE_COUNT"}
10710   ]
10711  },
10712  "CP_CPC_HALT_HYST_COUNT": {
10713   "fields": [
10714    {"bits": [0, 3], "name": "COUNT"}
10715   ]
10716  },
10717  "CP_CPC_SCRATCH_DATA": {
10718   "fields": [
10719    {"bits": [0, 31], "name": "SCRATCH_DATA"}
10720   ]
10721  },
10722  "CP_CPC_SCRATCH_INDEX": {
10723   "fields": [
10724    {"bits": [0, 8], "name": "SCRATCH_INDEX"}
10725   ]
10726  },
10727  "CP_CPC_STALLED_STAT1": {
10728   "fields": [
10729    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
10730    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
10731    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
10732    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
10733    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
10734    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
10735    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
10736    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
10737    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
10738    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
10739    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
10740    {"bits": [22, 22], "name": "ATCL2IU_WAITING_ON_FREE"},
10741    {"bits": [23, 23], "name": "ATCL2IU_WAITING_ON_TAGS"},
10742    {"bits": [24, 24], "name": "ATCL1_WAITING_ON_TRANS"}
10743   ]
10744  },
10745  "CP_CPC_STATUS": {
10746   "fields": [
10747    {"bits": [0, 0], "name": "MEC1_BUSY"},
10748    {"bits": [1, 1], "name": "MEC2_BUSY"},
10749    {"bits": [2, 2], "name": "DC0_BUSY"},
10750    {"bits": [3, 3], "name": "DC1_BUSY"},
10751    {"bits": [4, 4], "name": "RCIU1_BUSY"},
10752    {"bits": [5, 5], "name": "RCIU2_BUSY"},
10753    {"bits": [6, 6], "name": "ROQ1_BUSY"},
10754    {"bits": [7, 7], "name": "ROQ2_BUSY"},
10755    {"bits": [10, 10], "name": "TCIU_BUSY"},
10756    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
10757    {"bits": [12, 12], "name": "QU_BUSY"},
10758    {"bits": [13, 13], "name": "ATCL2IU_BUSY"},
10759    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
10760    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
10761    {"bits": [31, 31], "name": "CPC_BUSY"}
10762   ]
10763  },
10764  "CP_CPF_BUSY_STAT": {
10765   "fields": [
10766    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
10767    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
10768    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
10769    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
10770    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
10771    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
10772    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
10773    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
10774    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
10775    {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"},
10776    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
10777    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
10778    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
10779    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
10780    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
10781    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
10782    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
10783    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
10784    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
10785    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
10786    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
10787    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
10788    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
10789    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
10790    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
10791    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
10792    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
10793    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
10794    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
10795    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
10796    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
10797   ]
10798  },
10799  "CP_CPF_STALLED_STAT1": {
10800   "fields": [
10801    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
10802    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
10803    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
10804    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
10805    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
10806    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
10807    {"bits": [7, 7], "name": "ATCL2IU_WAITING_ON_FREE"},
10808    {"bits": [8, 8], "name": "ATCL2IU_WAITING_ON_TAGS"},
10809    {"bits": [9, 9], "name": "ATCL1_WAITING_ON_TRANS"}
10810   ]
10811  },
10812  "CP_CPF_STATUS": {
10813   "fields": [
10814    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
10815    {"bits": [1, 1], "name": "CSF_BUSY"},
10816    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
10817    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
10818    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
10819    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
10820    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
10821    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
10822    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
10823    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
10824    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
10825    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
10826    {"bits": [14, 14], "name": "TCIU_BUSY"},
10827    {"bits": [15, 15], "name": "HQD_BUSY"},
10828    {"bits": [16, 16], "name": "PRT_BUSY"},
10829    {"bits": [17, 17], "name": "ATCL2IU_BUSY"},
10830    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
10831    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
10832    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
10833    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
10834    {"bits": [31, 31], "name": "CPF_BUSY"}
10835   ]
10836  },
10837  "CP_DMA_CNTL": {
10838   "fields": [
10839    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
10840    {"bits": [16, 19], "name": "BUFFER_DEPTH"},
10841    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
10842    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
10843    {"bits": [30, 31], "name": "PIO_COUNT"}
10844   ]
10845  },
10846  "CP_DMA_ME_COMMAND": {
10847   "fields": [
10848    {"bits": [0, 20], "name": "BYTE_COUNT"},
10849    {"bits": [21, 21], "name": "DIS_WC"},
10850    {"bits": [22, 23], "name": "SRC_SWAP"},
10851    {"bits": [24, 25], "name": "DST_SWAP"},
10852    {"bits": [26, 26], "name": "SAS"},
10853    {"bits": [27, 27], "name": "DAS"},
10854    {"bits": [28, 28], "name": "SAIC"},
10855    {"bits": [29, 29], "name": "DAIC"},
10856    {"bits": [30, 30], "name": "RAW_WAIT"}
10857   ]
10858  },
10859  "CP_DMA_ME_CONTROL": {
10860   "fields": [
10861    {"bits": [10, 11], "name": "SRC_MTYPE"},
10862    {"bits": [12, 12], "name": "SRC_ATC"},
10863    {"bits": [13, 13], "name": "SRC_CACHE_POLICY"},
10864    {"bits": [20, 21], "name": "DST_SELECT"},
10865    {"bits": [22, 23], "name": "DST_MTYPE"},
10866    {"bits": [24, 24], "name": "DST_ATC"},
10867    {"bits": [25, 25], "name": "DST_CACHE_POLICY"},
10868    {"bits": [29, 30], "name": "SRC_SELECT"}
10869   ]
10870  },
10871  "CP_DMA_ME_DST_ADDR": {
10872   "fields": [
10873    {"bits": [0, 31], "name": "DST_ADDR"}
10874   ]
10875  },
10876  "CP_DMA_ME_DST_ADDR_HI": {
10877   "fields": [
10878    {"bits": [0, 15], "name": "DST_ADDR_HI"}
10879   ]
10880  },
10881  "CP_DMA_ME_SRC_ADDR": {
10882   "fields": [
10883    {"bits": [0, 31], "name": "SRC_ADDR"}
10884   ]
10885  },
10886  "CP_DMA_ME_SRC_ADDR_HI": {
10887   "fields": [
10888    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
10889   ]
10890  },
10891  "CP_DMA_READ_TAGS": {
10892   "fields": [
10893    {"bits": [0, 25], "name": "DMA_READ_TAG"},
10894    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
10895   ]
10896  },
10897  "CP_DRAW_OBJECT": {
10898   "fields": [
10899    {"bits": [0, 31], "name": "OBJECT"}
10900   ]
10901  },
10902  "CP_DRAW_OBJECT_COUNTER": {
10903   "fields": [
10904    {"bits": [0, 15], "name": "COUNT"}
10905   ]
10906  },
10907  "CP_DRAW_WINDOW_CNTL": {
10908   "fields": [
10909    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
10910    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
10911    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
10912    {"bits": [8, 8], "name": "MODE"}
10913   ]
10914  },
10915  "CP_DRAW_WINDOW_HI": {
10916   "fields": [
10917    {"bits": [0, 31], "name": "WINDOW_HI"}
10918   ]
10919  },
10920  "CP_DRAW_WINDOW_LO": {
10921   "fields": [
10922    {"bits": [0, 15], "name": "MIN"},
10923    {"bits": [16, 31], "name": "MAX"}
10924   ]
10925  },
10926  "CP_DRAW_WINDOW_MASK_HI": {
10927   "fields": [
10928    {"bits": [0, 31], "name": "WINDOW_MASK_HI"}
10929   ]
10930  },
10931  "CP_EOP_DONE_ADDR_HI": {
10932   "fields": [
10933    {"bits": [0, 15], "name": "ADDR_HI"}
10934   ]
10935  },
10936  "CP_EOP_DONE_ADDR_LO": {
10937   "fields": [
10938    {"bits": [2, 31], "name": "ADDR_LO"}
10939   ]
10940  },
10941  "CP_EOP_DONE_CNTX_ID": {
10942   "fields": [
10943    {"bits": [0, 27], "name": "CNTX_ID"}
10944   ]
10945  },
10946  "CP_EOP_DONE_DATA_CNTL": {
10947   "fields": [
10948    {"bits": [0, 15], "name": "CNTX_ID"},
10949    {"bits": [16, 17], "name": "DST_SEL"},
10950    {"bits": [24, 26], "name": "INT_SEL"},
10951    {"bits": [29, 31], "name": "DATA_SEL"}
10952   ]
10953  },
10954  "CP_EOP_DONE_DATA_HI": {
10955   "fields": [
10956    {"bits": [0, 31], "name": "DATA_HI"}
10957   ]
10958  },
10959  "CP_EOP_DONE_DATA_LO": {
10960   "fields": [
10961    {"bits": [0, 31], "name": "DATA_LO"}
10962   ]
10963  },
10964  "CP_EOP_DONE_EVENT_CNTL": {
10965   "fields": [
10966    {"bits": [0, 6], "name": "WBINV_TC_OP"},
10967    {"bits": [12, 17], "name": "WBINV_ACTION_ENA"},
10968    {"bits": [25, 25], "name": "CACHE_CONTROL"},
10969    {"bits": [27, 28], "name": "MTYPE"}
10970   ]
10971  },
10972  "CP_EOP_LAST_FENCE_HI": {
10973   "fields": [
10974    {"bits": [0, 31], "name": "LAST_FENCE_HI"}
10975   ]
10976  },
10977  "CP_EOP_LAST_FENCE_LO": {
10978   "fields": [
10979    {"bits": [0, 31], "name": "LAST_FENCE_LO"}
10980   ]
10981  },
10982  "CP_IB1_OFFSET": {
10983   "fields": [
10984    {"bits": [0, 19], "name": "IB1_OFFSET"}
10985   ]
10986  },
10987  "CP_IB1_PREAMBLE_BEGIN": {
10988   "fields": [
10989    {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
10990   ]
10991  },
10992  "CP_IB1_PREAMBLE_END": {
10993   "fields": [
10994    {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
10995   ]
10996  },
10997  "CP_IB2_OFFSET": {
10998   "fields": [
10999    {"bits": [0, 19], "name": "IB2_OFFSET"}
11000   ]
11001  },
11002  "CP_IB2_PREAMBLE_BEGIN": {
11003   "fields": [
11004    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
11005   ]
11006  },
11007  "CP_IB2_PREAMBLE_END": {
11008   "fields": [
11009    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
11010   ]
11011  },
11012  "CP_INDEX_TYPE": {
11013   "fields": [
11014    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
11015   ]
11016  },
11017  "CP_ME_MC_RADDR_HI": {
11018   "fields": [
11019    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
11020    {"bits": [20, 21], "name": "MTYPE"},
11021    {"bits": [22, 22], "name": "CACHE_POLICY"}
11022   ]
11023  },
11024  "CP_ME_MC_RADDR_LO": {
11025   "fields": [
11026    {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},
11027    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
11028   ]
11029  },
11030  "CP_ME_MC_WADDR_HI": {
11031   "fields": [
11032    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
11033    {"bits": [20, 21], "name": "MTYPE"},
11034    {"bits": [22, 22], "name": "CACHE_POLICY"}
11035   ]
11036  },
11037  "CP_ME_MC_WADDR_LO": {
11038   "fields": [
11039    {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},
11040    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
11041   ]
11042  },
11043  "CP_ME_MC_WDATA_HI": {
11044   "fields": [
11045    {"bits": [0, 31], "name": "ME_MC_WDATA_HI"}
11046   ]
11047  },
11048  "CP_ME_MC_WDATA_LO": {
11049   "fields": [
11050    {"bits": [0, 31], "name": "ME_MC_WDATA_LO"}
11051   ]
11052  },
11053  "CP_NUM_PRIM_NEEDED_COUNT0_HI": {
11054   "fields": [
11055    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"}
11056   ]
11057  },
11058  "CP_NUM_PRIM_NEEDED_COUNT0_LO": {
11059   "fields": [
11060    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"}
11061   ]
11062  },
11063  "CP_NUM_PRIM_NEEDED_COUNT1_HI": {
11064   "fields": [
11065    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"}
11066   ]
11067  },
11068  "CP_NUM_PRIM_NEEDED_COUNT1_LO": {
11069   "fields": [
11070    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"}
11071   ]
11072  },
11073  "CP_NUM_PRIM_NEEDED_COUNT2_HI": {
11074   "fields": [
11075    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"}
11076   ]
11077  },
11078  "CP_NUM_PRIM_NEEDED_COUNT2_LO": {
11079   "fields": [
11080    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"}
11081   ]
11082  },
11083  "CP_NUM_PRIM_NEEDED_COUNT3_HI": {
11084   "fields": [
11085    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"}
11086   ]
11087  },
11088  "CP_NUM_PRIM_NEEDED_COUNT3_LO": {
11089   "fields": [
11090    {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"}
11091   ]
11092  },
11093  "CP_NUM_PRIM_WRITTEN_COUNT0_HI": {
11094   "fields": [
11095    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"}
11096   ]
11097  },
11098  "CP_NUM_PRIM_WRITTEN_COUNT0_LO": {
11099   "fields": [
11100    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"}
11101   ]
11102  },
11103  "CP_NUM_PRIM_WRITTEN_COUNT1_HI": {
11104   "fields": [
11105    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"}
11106   ]
11107  },
11108  "CP_NUM_PRIM_WRITTEN_COUNT1_LO": {
11109   "fields": [
11110    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"}
11111   ]
11112  },
11113  "CP_NUM_PRIM_WRITTEN_COUNT2_HI": {
11114   "fields": [
11115    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"}
11116   ]
11117  },
11118  "CP_NUM_PRIM_WRITTEN_COUNT2_LO": {
11119   "fields": [
11120    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"}
11121   ]
11122  },
11123  "CP_NUM_PRIM_WRITTEN_COUNT3_HI": {
11124   "fields": [
11125    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"}
11126   ]
11127  },
11128  "CP_NUM_PRIM_WRITTEN_COUNT3_LO": {
11129   "fields": [
11130    {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"}
11131   ]
11132  },
11133  "CP_PA_CINVOC_COUNT_HI": {
11134   "fields": [
11135    {"bits": [0, 31], "name": "CINVOC_COUNT_HI"}
11136   ]
11137  },
11138  "CP_PA_CINVOC_COUNT_LO": {
11139   "fields": [
11140    {"bits": [0, 31], "name": "CINVOC_COUNT_LO"}
11141   ]
11142  },
11143  "CP_PA_CPRIM_COUNT_HI": {
11144   "fields": [
11145    {"bits": [0, 31], "name": "CPRIM_COUNT_HI"}
11146   ]
11147  },
11148  "CP_PA_CPRIM_COUNT_LO": {
11149   "fields": [
11150    {"bits": [0, 31], "name": "CPRIM_COUNT_LO"}
11151   ]
11152  },
11153  "CP_PERFMON_CNTL": {
11154   "fields": [
11155    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
11156    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
11157    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
11158    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
11159   ]
11160  },
11161  "CP_PERFMON_CNTX_CNTL": {
11162   "fields": [
11163    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
11164   ]
11165  },
11166  "CP_PFP_ATOMIC_PREOP_HI": {
11167   "fields": [
11168    {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"}
11169   ]
11170  },
11171  "CP_PFP_ATOMIC_PREOP_LO": {
11172   "fields": [
11173    {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"}
11174   ]
11175  },
11176  "CP_PFP_COMPLETION_STATUS": {
11177   "fields": [
11178    {"bits": [0, 1], "name": "STATUS"}
11179   ]
11180  },
11181  "CP_PFP_GDS_ATOMIC0_PREOP_HI": {
11182   "fields": [
11183    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"}
11184   ]
11185  },
11186  "CP_PFP_GDS_ATOMIC0_PREOP_LO": {
11187   "fields": [
11188    {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"}
11189   ]
11190  },
11191  "CP_PFP_GDS_ATOMIC1_PREOP_HI": {
11192   "fields": [
11193    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"}
11194   ]
11195  },
11196  "CP_PFP_GDS_ATOMIC1_PREOP_LO": {
11197   "fields": [
11198    {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"}
11199   ]
11200  },
11201  "CP_PFP_IB_CONTROL": {
11202   "fields": [
11203    {"bits": [0, 7], "name": "IB_EN"}
11204   ]
11205  },
11206  "CP_PFP_LOAD_CONTROL": {
11207   "fields": [
11208    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
11209    {"bits": [1, 1], "name": "CNTX_REG_EN"},
11210    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
11211    {"bits": [24, 24], "name": "SH_CS_REG_EN"}
11212   ]
11213  },
11214  "CP_PFP_METADATA_BASE_ADDR": {
11215   "fields": [
11216    {"bits": [0, 31], "name": "ADDR_LO"}
11217   ]
11218  },
11219  "CP_PIPE_STATS_ADDR_HI": {
11220   "fields": [
11221    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
11222   ]
11223  },
11224  "CP_PIPE_STATS_ADDR_LO": {
11225   "fields": [
11226    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
11227   ]
11228  },
11229  "CP_PIPE_STATS_CONTROL": {
11230   "fields": [
11231    {"bits": [25, 25], "name": "CACHE_CONTROL"},
11232    {"bits": [27, 28], "name": "MTYPE"}
11233   ]
11234  },
11235  "CP_PRED_NOT_VISIBLE": {
11236   "fields": [
11237    {"bits": [0, 0], "name": "NOT_VISIBLE"}
11238   ]
11239  },
11240  "CP_RB_OFFSET": {
11241   "fields": [
11242    {"bits": [0, 19], "name": "RB_OFFSET"}
11243   ]
11244  },
11245  "CP_RINGID": {
11246   "fields": [
11247    {"bits": [0, 1], "name": "RINGID"}
11248   ]
11249  },
11250  "CP_SAMPLE_STATUS": {
11251   "fields": [
11252    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
11253    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
11254    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
11255    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
11256    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
11257    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
11258    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
11259    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
11260   ]
11261  },
11262  "CP_SCRATCH_INDEX": {
11263   "fields": [
11264    {"bits": [0, 7], "name": "SCRATCH_INDEX"}
11265   ]
11266  },
11267  "CP_SC_PSINVOC_COUNT0_HI": {
11268   "fields": [
11269    {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"}
11270   ]
11271  },
11272  "CP_SC_PSINVOC_COUNT0_LO": {
11273   "fields": [
11274    {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"}
11275   ]
11276  },
11277  "CP_SC_PSINVOC_COUNT1_LO": {
11278   "fields": [
11279    {"bits": [0, 31], "name": "OBSOLETE"}
11280   ]
11281  },
11282  "CP_SEM_WAIT_TIMER": {
11283   "fields": [
11284    {"bits": [0, 31], "name": "SEM_WAIT_TIMER"}
11285   ]
11286  },
11287  "CP_SIG_SEM_ADDR_HI": {
11288   "fields": [
11289    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
11290    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
11291    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
11292    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
11293    {"bits": [29, 31], "name": "SEM_SELECT"}
11294   ]
11295  },
11296  "CP_SIG_SEM_ADDR_LO": {
11297   "fields": [
11298    {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
11299    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
11300   ]
11301  },
11302  "CP_STREAM_OUT_ADDR_HI": {
11303   "fields": [
11304    {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"}
11305   ]
11306  },
11307  "CP_STREAM_OUT_ADDR_LO": {
11308   "fields": [
11309    {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
11310   ]
11311  },
11312  "CP_STRMOUT_CNTL": {
11313   "fields": [
11314    {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
11315   ]
11316  },
11317  "CP_ST_BASE_HI": {
11318   "fields": [
11319    {"bits": [0, 15], "name": "ST_BASE_HI"}
11320   ]
11321  },
11322  "CP_ST_BASE_LO": {
11323   "fields": [
11324    {"bits": [2, 31], "name": "ST_BASE_LO"}
11325   ]
11326  },
11327  "CP_ST_BUFSZ": {
11328   "fields": [
11329    {"bits": [0, 19], "name": "ST_BUFSZ"}
11330   ]
11331  },
11332  "CP_VGT_CSINVOC_COUNT_HI": {
11333   "fields": [
11334    {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"}
11335   ]
11336  },
11337  "CP_VGT_CSINVOC_COUNT_LO": {
11338   "fields": [
11339    {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"}
11340   ]
11341  },
11342  "CP_VGT_DSINVOC_COUNT_HI": {
11343   "fields": [
11344    {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"}
11345   ]
11346  },
11347  "CP_VGT_DSINVOC_COUNT_LO": {
11348   "fields": [
11349    {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"}
11350   ]
11351  },
11352  "CP_VGT_GSINVOC_COUNT_HI": {
11353   "fields": [
11354    {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"}
11355   ]
11356  },
11357  "CP_VGT_GSINVOC_COUNT_LO": {
11358   "fields": [
11359    {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"}
11360   ]
11361  },
11362  "CP_VGT_GSPRIM_COUNT_HI": {
11363   "fields": [
11364    {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"}
11365   ]
11366  },
11367  "CP_VGT_GSPRIM_COUNT_LO": {
11368   "fields": [
11369    {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"}
11370   ]
11371  },
11372  "CP_VGT_HSINVOC_COUNT_HI": {
11373   "fields": [
11374    {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"}
11375   ]
11376  },
11377  "CP_VGT_HSINVOC_COUNT_LO": {
11378   "fields": [
11379    {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"}
11380   ]
11381  },
11382  "CP_VGT_IAPRIM_COUNT_HI": {
11383   "fields": [
11384    {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"}
11385   ]
11386  },
11387  "CP_VGT_IAPRIM_COUNT_LO": {
11388   "fields": [
11389    {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"}
11390   ]
11391  },
11392  "CP_VGT_IAVERT_COUNT_HI": {
11393   "fields": [
11394    {"bits": [0, 31], "name": "IAVERT_COUNT_HI"}
11395   ]
11396  },
11397  "CP_VGT_IAVERT_COUNT_LO": {
11398   "fields": [
11399    {"bits": [0, 31], "name": "IAVERT_COUNT_LO"}
11400   ]
11401  },
11402  "CP_VGT_VSINVOC_COUNT_HI": {
11403   "fields": [
11404    {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"}
11405   ]
11406  },
11407  "CP_VGT_VSINVOC_COUNT_LO": {
11408   "fields": [
11409    {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"}
11410   ]
11411  },
11412  "CP_VMID": {
11413   "fields": [
11414    {"bits": [0, 3], "name": "VMID"}
11415   ]
11416  },
11417  "CP_WAIT_REG_MEM_TIMEOUT": {
11418   "fields": [
11419    {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"}
11420   ]
11421  },
11422  "CS_COPY_STATE": {
11423   "fields": [
11424    {"bits": [0, 2], "name": "SRC_STATE_ID"}
11425   ]
11426  },
11427  "DB_ALPHA_TO_MASK": {
11428   "fields": [
11429    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
11430    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
11431    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
11432    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
11433    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
11434    {"bits": [16, 16], "name": "OFFSET_ROUND"}
11435   ]
11436  },
11437  "DB_COUNT_CONTROL": {
11438   "fields": [
11439    {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
11440    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
11441    {"bits": [4, 6], "name": "SAMPLE_RATE"},
11442    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
11443    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
11444    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
11445    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
11446    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
11447    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
11448   ]
11449  },
11450  "DB_DEPTH_BOUNDS_MAX": {
11451   "fields": [
11452    {"bits": [0, 31], "name": "MAX"}
11453   ]
11454  },
11455  "DB_DEPTH_BOUNDS_MIN": {
11456   "fields": [
11457    {"bits": [0, 31], "name": "MIN"}
11458   ]
11459  },
11460  "DB_DEPTH_CLEAR": {
11461   "fields": [
11462    {"bits": [0, 31], "name": "DEPTH_CLEAR"}
11463   ]
11464  },
11465  "DB_DEPTH_CONTROL": {
11466   "fields": [
11467    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
11468    {"bits": [1, 1], "name": "Z_ENABLE"},
11469    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
11470    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
11471    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
11472    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
11473    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
11474    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
11475    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
11476    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
11477   ]
11478  },
11479  "DB_DEPTH_INFO": {
11480   "fields": [
11481    {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},
11482    {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
11483    {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
11484    {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
11485    {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
11486    {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
11487    {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
11488   ]
11489  },
11490  "DB_DEPTH_SIZE": {
11491   "fields": [
11492    {"bits": [0, 10], "name": "PITCH_TILE_MAX"},
11493    {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}
11494   ]
11495  },
11496  "DB_DEPTH_SLICE": {
11497   "fields": [
11498    {"bits": [0, 21], "name": "SLICE_TILE_MAX"}
11499   ]
11500  },
11501  "DB_DEPTH_VIEW": {
11502   "fields": [
11503    {"bits": [0, 10], "name": "SLICE_START"},
11504    {"bits": [13, 23], "name": "SLICE_MAX"},
11505    {"bits": [24, 24], "name": "Z_READ_ONLY"},
11506    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}
11507   ]
11508  },
11509  "DB_EQAA": {
11510   "fields": [
11511    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
11512    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
11513    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
11514    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
11515    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
11516    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
11517    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
11518    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
11519    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
11520    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
11521    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
11522    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
11523   ]
11524  },
11525  "DB_HTILE_SURFACE": {
11526   "fields": [
11527    {"bits": [0, 0], "name": "LINEAR"},
11528    {"bits": [1, 1], "name": "FULL_CACHE"},
11529    {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
11530    {"bits": [3, 3], "name": "PRELOAD"},
11531    {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
11532    {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
11533    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
11534    {"bits": [17, 17], "name": "TC_COMPATIBLE"}
11535   ]
11536  },
11537  "DB_PERFCOUNTER0_SELECT": {
11538   "fields": [
11539    {"bits": [0, 9], "name": "PERF_SEL"},
11540    {"bits": [10, 19], "name": "PERF_SEL1"},
11541    {"bits": [20, 23], "name": "CNTR_MODE"},
11542    {"bits": [24, 27], "name": "PERF_MODE1"},
11543    {"bits": [28, 31], "name": "PERF_MODE"}
11544   ]
11545  },
11546  "DB_PERFCOUNTER0_SELECT1": {
11547   "fields": [
11548    {"bits": [0, 9], "name": "PERF_SEL2"},
11549    {"bits": [10, 19], "name": "PERF_SEL3"},
11550    {"bits": [24, 27], "name": "PERF_MODE3"},
11551    {"bits": [28, 31], "name": "PERF_MODE2"}
11552   ]
11553  },
11554  "DB_PRELOAD_CONTROL": {
11555   "fields": [
11556    {"bits": [0, 7], "name": "START_X"},
11557    {"bits": [8, 15], "name": "START_Y"},
11558    {"bits": [16, 23], "name": "MAX_X"},
11559    {"bits": [24, 31], "name": "MAX_Y"}
11560   ]
11561  },
11562  "DB_RENDER_CONTROL": {
11563   "fields": [
11564    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
11565    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
11566    {"bits": [2, 2], "name": "DEPTH_COPY"},
11567    {"bits": [3, 3], "name": "STENCIL_COPY"},
11568    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
11569    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
11570    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
11571    {"bits": [7, 7], "name": "COPY_CENTROID"},
11572    {"bits": [8, 11], "name": "COPY_SAMPLE"},
11573    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"}
11574   ]
11575  },
11576  "DB_RENDER_OVERRIDE": {
11577   "fields": [
11578    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
11579    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
11580    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
11581    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
11582    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
11583    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
11584    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
11585    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
11586    {"bits": [11, 11], "name": "FORCE_Z_READ"},
11587    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
11588    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
11589    {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
11590    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
11591    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
11592    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
11593    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
11594    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
11595    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
11596    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
11597    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
11598    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
11599    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
11600    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
11601   ]
11602  },
11603  "DB_RENDER_OVERRIDE2": {
11604   "fields": [
11605    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
11606    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
11607    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
11608    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
11609    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
11610    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
11611    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
11612    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
11613    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
11614    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
11615    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
11616    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
11617    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
11618    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
11619    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}
11620   ]
11621  },
11622  "DB_SHADER_CONTROL": {
11623   "fields": [
11624    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
11625    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
11626    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
11627    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
11628    {"bits": [6, 6], "name": "KILL_ENABLE"},
11629    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
11630    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
11631    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
11632    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
11633    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
11634    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
11635    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
11636    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}
11637   ]
11638  },
11639  "DB_SRESULTS_COMPARE_STATE0": {
11640   "fields": [
11641    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
11642    {"bits": [4, 11], "name": "COMPAREVALUE0"},
11643    {"bits": [12, 19], "name": "COMPAREMASK0"},
11644    {"bits": [24, 24], "name": "ENABLE0"}
11645   ]
11646  },
11647  "DB_SRESULTS_COMPARE_STATE1": {
11648   "fields": [
11649    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
11650    {"bits": [4, 11], "name": "COMPAREVALUE1"},
11651    {"bits": [12, 19], "name": "COMPAREMASK1"},
11652    {"bits": [24, 24], "name": "ENABLE1"}
11653   ]
11654  },
11655  "DB_STENCILREFMASK": {
11656   "fields": [
11657    {"bits": [0, 7], "name": "STENCILTESTVAL"},
11658    {"bits": [8, 15], "name": "STENCILMASK"},
11659    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
11660    {"bits": [24, 31], "name": "STENCILOPVAL"}
11661   ]
11662  },
11663  "DB_STENCILREFMASK_BF": {
11664   "fields": [
11665    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
11666    {"bits": [8, 15], "name": "STENCILMASK_BF"},
11667    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
11668    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
11669   ]
11670  },
11671  "DB_STENCIL_CLEAR": {
11672   "fields": [
11673    {"bits": [0, 7], "name": "CLEAR"}
11674   ]
11675  },
11676  "DB_STENCIL_CONTROL": {
11677   "fields": [
11678    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
11679    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
11680    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
11681    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
11682    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
11683    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
11684   ]
11685  },
11686  "DB_STENCIL_INFO": {
11687   "fields": [
11688    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
11689    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
11690    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
11691    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
11692    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"},
11693    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}
11694   ]
11695  },
11696  "DB_ZPASS_COUNT_HI": {
11697   "fields": [
11698    {"bits": [0, 30], "name": "COUNT_HI"}
11699   ]
11700  },
11701  "DB_ZPASS_COUNT_LOW": {
11702   "fields": [
11703    {"bits": [0, 31], "name": "COUNT_LOW"}
11704   ]
11705  },
11706  "DB_Z_INFO": {
11707   "fields": [
11708    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
11709    {"bits": [2, 3], "name": "NUM_SAMPLES"},
11710    {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
11711    {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
11712    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
11713    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
11714    {"bits": [28, 28], "name": "READ_SIZE"},
11715    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
11716    {"bits": [30, 30], "name": "CLEAR_DISALLOWED"},
11717    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
11718   ]
11719  },
11720  "GB_ADDR_CONFIG": {
11721   "fields": [
11722    {"bits": [0, 2], "name": "NUM_PIPES"},
11723    {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},
11724    {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
11725    {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},
11726    {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
11727    {"bits": [20, 22], "name": "NUM_GPUS"},
11728    {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
11729    {"bits": [28, 29], "name": "ROW_SIZE"},
11730    {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}
11731   ]
11732  },
11733  "GB_MACROTILE_MODE0": {
11734   "fields": [
11735    {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
11736    {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
11737    {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
11738    {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
11739   ]
11740  },
11741  "GB_TILE_MODE0": {
11742   "fields": [
11743    {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
11744    {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
11745    {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
11746    {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
11747    {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
11748   ]
11749  },
11750  "GDS_ATOM_BASE": {
11751   "fields": [
11752    {"bits": [0, 15], "name": "BASE"},
11753    {"bits": [16, 31], "name": "UNUSED"}
11754   ]
11755  },
11756  "GDS_ATOM_CNTL": {
11757   "fields": [
11758    {"bits": [0, 5], "name": "AINC"},
11759    {"bits": [6, 7], "name": "UNUSED1"},
11760    {"bits": [8, 9], "name": "DMODE"},
11761    {"bits": [10, 31], "name": "UNUSED2"}
11762   ]
11763  },
11764  "GDS_ATOM_COMPLETE": {
11765   "fields": [
11766    {"bits": [0, 0], "name": "COMPLETE"},
11767    {"bits": [1, 31], "name": "UNUSED"}
11768   ]
11769  },
11770  "GDS_ATOM_DST": {
11771   "fields": [
11772    {"bits": [0, 31], "name": "DST"}
11773   ]
11774  },
11775  "GDS_ATOM_OFFSET0": {
11776   "fields": [
11777    {"bits": [0, 7], "name": "OFFSET0"},
11778    {"bits": [8, 31], "name": "UNUSED"}
11779   ]
11780  },
11781  "GDS_ATOM_OFFSET1": {
11782   "fields": [
11783    {"bits": [0, 7], "name": "OFFSET1"},
11784    {"bits": [8, 31], "name": "UNUSED"}
11785   ]
11786  },
11787  "GDS_ATOM_OP": {
11788   "fields": [
11789    {"bits": [0, 7], "name": "OP"},
11790    {"bits": [8, 31], "name": "UNUSED"}
11791   ]
11792  },
11793  "GDS_ATOM_SIZE": {
11794   "fields": [
11795    {"bits": [0, 15], "name": "SIZE"},
11796    {"bits": [16, 31], "name": "UNUSED"}
11797   ]
11798  },
11799  "GDS_GWS_RESOURCE": {
11800   "fields": [
11801    {"bits": [0, 0], "name": "FLAG"},
11802    {"bits": [1, 12], "name": "COUNTER"},
11803    {"bits": [13, 13], "name": "TYPE"},
11804    {"bits": [14, 14], "name": "DED"},
11805    {"bits": [15, 15], "name": "RELEASE_ALL"},
11806    {"bits": [16, 27], "name": "HEAD_QUEUE"},
11807    {"bits": [28, 28], "name": "HEAD_VALID"},
11808    {"bits": [29, 29], "name": "HEAD_FLAG"},
11809    {"bits": [30, 31], "name": "UNUSED1"}
11810   ]
11811  },
11812  "GDS_GWS_RESOURCE_CNT": {
11813   "fields": [
11814    {"bits": [0, 15], "name": "RESOURCE_CNT"},
11815    {"bits": [16, 31], "name": "UNUSED"}
11816   ]
11817  },
11818  "GDS_GWS_RESOURCE_CNTL": {
11819   "fields": [
11820    {"bits": [0, 5], "name": "INDEX"},
11821    {"bits": [6, 31], "name": "UNUSED"}
11822   ]
11823  },
11824  "GDS_OA_ADDRESS": {
11825   "fields": [
11826    {"bits": [0, 15], "name": "DS_ADDRESS"},
11827    {"bits": [16, 19], "name": "CRAWLER"},
11828    {"bits": [20, 21], "name": "CRAWLER_TYPE"},
11829    {"bits": [22, 29], "name": "UNUSED"},
11830    {"bits": [30, 30], "name": "NO_ALLOC"},
11831    {"bits": [31, 31], "name": "ENABLE"}
11832   ]
11833  },
11834  "GDS_OA_CNTL": {
11835   "fields": [
11836    {"bits": [0, 3], "name": "INDEX"},
11837    {"bits": [4, 31], "name": "UNUSED"}
11838   ]
11839  },
11840  "GDS_OA_COUNTER": {
11841   "fields": [
11842    {"bits": [0, 31], "name": "SPACE_AVAILABLE"}
11843   ]
11844  },
11845  "GDS_OA_INCDEC": {
11846   "fields": [
11847    {"bits": [0, 30], "name": "VALUE"},
11848    {"bits": [31, 31], "name": "INCDEC"}
11849   ]
11850  },
11851  "GDS_OA_RING_SIZE": {
11852   "fields": [
11853    {"bits": [0, 31], "name": "RING_SIZE"}
11854   ]
11855  },
11856  "GDS_RD_ADDR": {
11857   "fields": [
11858    {"bits": [0, 31], "name": "READ_ADDR"}
11859   ]
11860  },
11861  "GDS_RD_BURST_ADDR": {
11862   "fields": [
11863    {"bits": [0, 31], "name": "BURST_ADDR"}
11864   ]
11865  },
11866  "GDS_RD_BURST_COUNT": {
11867   "fields": [
11868    {"bits": [0, 31], "name": "BURST_COUNT"}
11869   ]
11870  },
11871  "GDS_RD_BURST_DATA": {
11872   "fields": [
11873    {"bits": [0, 31], "name": "BURST_DATA"}
11874   ]
11875  },
11876  "GDS_RD_DATA": {
11877   "fields": [
11878    {"bits": [0, 31], "name": "READ_DATA"}
11879   ]
11880  },
11881  "GDS_WRITE_COMPLETE": {
11882   "fields": [
11883    {"bits": [0, 31], "name": "WRITE_COMPLETE"}
11884   ]
11885  },
11886  "GDS_WR_ADDR": {
11887   "fields": [
11888    {"bits": [0, 31], "name": "WRITE_ADDR"}
11889   ]
11890  },
11891  "GDS_WR_DATA": {
11892   "fields": [
11893    {"bits": [0, 31], "name": "WRITE_DATA"}
11894   ]
11895  },
11896  "GRBM_GFX_INDEX": {
11897   "fields": [
11898    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
11899    {"bits": [8, 15], "name": "SH_INDEX"},
11900    {"bits": [16, 23], "name": "SE_INDEX"},
11901    {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
11902    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
11903    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
11904   ]
11905  },
11906  "GRBM_PERFCOUNTER0_SELECT": {
11907   "fields": [
11908    {"bits": [0, 5], "name": "PERF_SEL"},
11909    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
11910    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
11911    {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
11912    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
11913    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
11914    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
11915    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
11916    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
11917    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
11918    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
11919    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
11920    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
11921    {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
11922    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
11923    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
11924    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
11925    {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
11926    {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}
11927   ]
11928  },
11929  "GRBM_SE0_PERFCOUNTER_SELECT": {
11930   "fields": [
11931    {"bits": [0, 5], "name": "PERF_SEL"},
11932    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
11933    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
11934    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
11935    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
11936    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
11937    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
11938    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
11939    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
11940    {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
11941    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
11942    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}
11943   ]
11944  },
11945  "GRBM_STATUS": {
11946   "fields": [
11947    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
11948    {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},
11949    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
11950    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
11951    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
11952    {"bits": [12, 12], "name": "DB_CLEAN"},
11953    {"bits": [13, 13], "name": "CB_CLEAN"},
11954    {"bits": [14, 14], "name": "TA_BUSY"},
11955    {"bits": [15, 15], "name": "GDS_BUSY"},
11956    {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
11957    {"bits": [17, 17], "name": "VGT_BUSY"},
11958    {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
11959    {"bits": [19, 19], "name": "IA_BUSY"},
11960    {"bits": [20, 20], "name": "SX_BUSY"},
11961    {"bits": [21, 21], "name": "WD_BUSY"},
11962    {"bits": [22, 22], "name": "SPI_BUSY"},
11963    {"bits": [23, 23], "name": "BCI_BUSY"},
11964    {"bits": [24, 24], "name": "SC_BUSY"},
11965    {"bits": [25, 25], "name": "PA_BUSY"},
11966    {"bits": [26, 26], "name": "DB_BUSY"},
11967    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
11968    {"bits": [29, 29], "name": "CP_BUSY"},
11969    {"bits": [30, 30], "name": "CB_BUSY"},
11970    {"bits": [31, 31], "name": "GUI_ACTIVE"}
11971   ]
11972  },
11973  "GRBM_STATUS2": {
11974   "fields": [
11975    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
11976    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
11977    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
11978    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
11979    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
11980    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
11981    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
11982    {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
11983    {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
11984    {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
11985    {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
11986    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
11987    {"bits": [24, 24], "name": "RLC_BUSY"},
11988    {"bits": [25, 25], "name": "TC_BUSY"},
11989    {"bits": [26, 26], "name": "TCC_CC_RESIDENT"},
11990    {"bits": [28, 28], "name": "CPF_BUSY"},
11991    {"bits": [29, 29], "name": "CPC_BUSY"},
11992    {"bits": [30, 30], "name": "CPG_BUSY"}
11993   ]
11994  },
11995  "GRBM_STATUS_SE0": {
11996   "fields": [
11997    {"bits": [1, 1], "name": "DB_CLEAN"},
11998    {"bits": [2, 2], "name": "CB_CLEAN"},
11999    {"bits": [22, 22], "name": "BCI_BUSY"},
12000    {"bits": [23, 23], "name": "VGT_BUSY"},
12001    {"bits": [24, 24], "name": "PA_BUSY"},
12002    {"bits": [25, 25], "name": "TA_BUSY"},
12003    {"bits": [26, 26], "name": "SX_BUSY"},
12004    {"bits": [27, 27], "name": "SPI_BUSY"},
12005    {"bits": [29, 29], "name": "SC_BUSY"},
12006    {"bits": [30, 30], "name": "DB_BUSY"},
12007    {"bits": [31, 31], "name": "CB_BUSY"}
12008   ]
12009  },
12010  "IA_ENHANCE": {
12011   "fields": [
12012    {"bits": [0, 31], "name": "MISC"}
12013   ]
12014  },
12015  "IA_MULTI_VGT_PARAM": {
12016   "fields": [
12017    {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
12018    {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
12019    {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
12020    {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
12021    {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
12022    {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"},
12023    {"bits": [28, 31], "name": "MAX_PRIMGRP_IN_WAVE"}
12024   ]
12025  },
12026  "PA_CL_CLIP_CNTL": {
12027   "fields": [
12028    {"bits": [0, 0], "name": "UCP_ENA_0"},
12029    {"bits": [1, 1], "name": "UCP_ENA_1"},
12030    {"bits": [2, 2], "name": "UCP_ENA_2"},
12031    {"bits": [3, 3], "name": "UCP_ENA_3"},
12032    {"bits": [4, 4], "name": "UCP_ENA_4"},
12033    {"bits": [5, 5], "name": "UCP_ENA_5"},
12034    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
12035    {"bits": [14, 15], "name": "PS_UCP_MODE"},
12036    {"bits": [16, 16], "name": "CLIP_DISABLE"},
12037    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
12038    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
12039    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
12040    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
12041    {"bits": [21, 21], "name": "VTX_KILL_OR"},
12042    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
12043    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
12044    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
12045    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
12046    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}
12047   ]
12048  },
12049  "PA_CL_GB_VERT_CLIP_ADJ": {
12050   "fields": [
12051    {"bits": [0, 31], "name": "DATA_REGISTER"}
12052   ]
12053  },
12054  "PA_CL_NANINF_CNTL": {
12055   "fields": [
12056    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
12057    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
12058    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
12059    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
12060    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
12061    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
12062    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
12063    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
12064    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
12065    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
12066    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
12067    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
12068    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
12069    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
12070    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
12071    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
12072   ]
12073  },
12074  "PA_CL_VPORT_XOFFSET": {
12075   "fields": [
12076    {"bits": [0, 31], "name": "VPORT_XOFFSET"}
12077   ]
12078  },
12079  "PA_CL_VPORT_XSCALE": {
12080   "fields": [
12081    {"bits": [0, 31], "name": "VPORT_XSCALE"}
12082   ]
12083  },
12084  "PA_CL_VPORT_YOFFSET": {
12085   "fields": [
12086    {"bits": [0, 31], "name": "VPORT_YOFFSET"}
12087   ]
12088  },
12089  "PA_CL_VPORT_YSCALE": {
12090   "fields": [
12091    {"bits": [0, 31], "name": "VPORT_YSCALE"}
12092   ]
12093  },
12094  "PA_CL_VPORT_ZOFFSET": {
12095   "fields": [
12096    {"bits": [0, 31], "name": "VPORT_ZOFFSET"}
12097   ]
12098  },
12099  "PA_CL_VPORT_ZSCALE": {
12100   "fields": [
12101    {"bits": [0, 31], "name": "VPORT_ZSCALE"}
12102   ]
12103  },
12104  "PA_CL_VS_OUT_CNTL": {
12105   "fields": [
12106    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
12107    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
12108    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
12109    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
12110    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
12111    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
12112    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
12113    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
12114    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
12115    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
12116    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
12117    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
12118    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
12119    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
12120    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
12121    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
12122    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
12123    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
12124    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
12125    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
12126    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
12127    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
12128    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
12129    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
12130    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
12131    {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"},
12132    {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}
12133   ]
12134  },
12135  "PA_CL_VTE_CNTL": {
12136   "fields": [
12137    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
12138    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
12139    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
12140    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
12141    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
12142    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
12143    {"bits": [8, 8], "name": "VTX_XY_FMT"},
12144    {"bits": [9, 9], "name": "VTX_Z_FMT"},
12145    {"bits": [10, 10], "name": "VTX_W0_FMT"},
12146    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
12147   ]
12148  },
12149  "PA_SC_AA_CONFIG": {
12150   "fields": [
12151    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
12152    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
12153    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
12154    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
12155    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}
12156   ]
12157  },
12158  "PA_SC_AA_MASK_X0Y0_X1Y0": {
12159   "fields": [
12160    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
12161    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
12162   ]
12163  },
12164  "PA_SC_AA_MASK_X0Y1_X1Y1": {
12165   "fields": [
12166    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
12167    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
12168   ]
12169  },
12170  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
12171   "fields": [
12172    {"bits": [0, 3], "name": "S0_X"},
12173    {"bits": [4, 7], "name": "S0_Y"},
12174    {"bits": [8, 11], "name": "S1_X"},
12175    {"bits": [12, 15], "name": "S1_Y"},
12176    {"bits": [16, 19], "name": "S2_X"},
12177    {"bits": [20, 23], "name": "S2_Y"},
12178    {"bits": [24, 27], "name": "S3_X"},
12179    {"bits": [28, 31], "name": "S3_Y"}
12180   ]
12181  },
12182  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
12183   "fields": [
12184    {"bits": [0, 3], "name": "S4_X"},
12185    {"bits": [4, 7], "name": "S4_Y"},
12186    {"bits": [8, 11], "name": "S5_X"},
12187    {"bits": [12, 15], "name": "S5_Y"},
12188    {"bits": [16, 19], "name": "S6_X"},
12189    {"bits": [20, 23], "name": "S6_Y"},
12190    {"bits": [24, 27], "name": "S7_X"},
12191    {"bits": [28, 31], "name": "S7_Y"}
12192   ]
12193  },
12194  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
12195   "fields": [
12196    {"bits": [0, 3], "name": "S8_X"},
12197    {"bits": [4, 7], "name": "S8_Y"},
12198    {"bits": [8, 11], "name": "S9_X"},
12199    {"bits": [12, 15], "name": "S9_Y"},
12200    {"bits": [16, 19], "name": "S10_X"},
12201    {"bits": [20, 23], "name": "S10_Y"},
12202    {"bits": [24, 27], "name": "S11_X"},
12203    {"bits": [28, 31], "name": "S11_Y"}
12204   ]
12205  },
12206  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
12207   "fields": [
12208    {"bits": [0, 3], "name": "S12_X"},
12209    {"bits": [4, 7], "name": "S12_Y"},
12210    {"bits": [8, 11], "name": "S13_X"},
12211    {"bits": [12, 15], "name": "S13_Y"},
12212    {"bits": [16, 19], "name": "S14_X"},
12213    {"bits": [20, 23], "name": "S14_Y"},
12214    {"bits": [24, 27], "name": "S15_X"},
12215    {"bits": [28, 31], "name": "S15_Y"}
12216   ]
12217  },
12218  "PA_SC_CENTROID_PRIORITY_0": {
12219   "fields": [
12220    {"bits": [0, 3], "name": "DISTANCE_0"},
12221    {"bits": [4, 7], "name": "DISTANCE_1"},
12222    {"bits": [8, 11], "name": "DISTANCE_2"},
12223    {"bits": [12, 15], "name": "DISTANCE_3"},
12224    {"bits": [16, 19], "name": "DISTANCE_4"},
12225    {"bits": [20, 23], "name": "DISTANCE_5"},
12226    {"bits": [24, 27], "name": "DISTANCE_6"},
12227    {"bits": [28, 31], "name": "DISTANCE_7"}
12228   ]
12229  },
12230  "PA_SC_CENTROID_PRIORITY_1": {
12231   "fields": [
12232    {"bits": [0, 3], "name": "DISTANCE_8"},
12233    {"bits": [4, 7], "name": "DISTANCE_9"},
12234    {"bits": [8, 11], "name": "DISTANCE_10"},
12235    {"bits": [12, 15], "name": "DISTANCE_11"},
12236    {"bits": [16, 19], "name": "DISTANCE_12"},
12237    {"bits": [20, 23], "name": "DISTANCE_13"},
12238    {"bits": [24, 27], "name": "DISTANCE_14"},
12239    {"bits": [28, 31], "name": "DISTANCE_15"}
12240   ]
12241  },
12242  "PA_SC_CLIPRECT_0_BR": {
12243   "fields": [
12244    {"bits": [0, 14], "name": "BR_X"},
12245    {"bits": [16, 30], "name": "BR_Y"}
12246   ]
12247  },
12248  "PA_SC_CLIPRECT_0_TL": {
12249   "fields": [
12250    {"bits": [0, 14], "name": "TL_X"},
12251    {"bits": [16, 30], "name": "TL_Y"}
12252   ]
12253  },
12254  "PA_SC_CLIPRECT_RULE": {
12255   "fields": [
12256    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
12257   ]
12258  },
12259  "PA_SC_EDGERULE": {
12260   "fields": [
12261    {"bits": [0, 3], "name": "ER_TRI"},
12262    {"bits": [4, 7], "name": "ER_POINT"},
12263    {"bits": [8, 11], "name": "ER_RECT"},
12264    {"bits": [12, 17], "name": "ER_LINE_LR"},
12265    {"bits": [18, 23], "name": "ER_LINE_RL"},
12266    {"bits": [24, 27], "name": "ER_LINE_TB"},
12267    {"bits": [28, 31], "name": "ER_LINE_BT"}
12268   ]
12269  },
12270  "PA_SC_GENERIC_SCISSOR_TL": {
12271   "fields": [
12272    {"bits": [0, 14], "name": "TL_X"},
12273    {"bits": [16, 30], "name": "TL_Y"},
12274    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
12275   ]
12276  },
12277  "PA_SC_LINE_CNTL": {
12278   "fields": [
12279    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
12280    {"bits": [10, 10], "name": "LAST_PIXEL"},
12281    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
12282    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}
12283   ]
12284  },
12285  "PA_SC_LINE_STIPPLE": {
12286   "fields": [
12287    {"bits": [0, 15], "name": "LINE_PATTERN"},
12288    {"bits": [16, 23], "name": "REPEAT_COUNT"},
12289    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
12290    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
12291   ]
12292  },
12293  "PA_SC_LINE_STIPPLE_STATE": {
12294   "fields": [
12295    {"bits": [0, 3], "name": "CURRENT_PTR"},
12296    {"bits": [8, 15], "name": "CURRENT_COUNT"}
12297   ]
12298  },
12299  "PA_SC_MODE_CNTL_0": {
12300   "fields": [
12301    {"bits": [0, 0], "name": "MSAA_ENABLE"},
12302    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
12303    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
12304    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}
12305   ]
12306  },
12307  "PA_SC_MODE_CNTL_1": {
12308   "fields": [
12309    {"bits": [0, 0], "name": "WALK_SIZE"},
12310    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
12311    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
12312    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
12313    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
12314    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
12315    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
12316    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
12317    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
12318    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
12319    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
12320    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
12321    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
12322    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
12323    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
12324    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
12325    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
12326    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
12327    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
12328    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
12329    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
12330    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
12331    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
12332    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
12333   ]
12334  },
12335  "PA_SC_P3D_TRAP_SCREEN_H": {
12336   "fields": [
12337    {"bits": [0, 13], "name": "X_COORD"}
12338   ]
12339  },
12340  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
12341   "fields": [
12342    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
12343    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
12344   ]
12345  },
12346  "PA_SC_P3D_TRAP_SCREEN_V": {
12347   "fields": [
12348    {"bits": [0, 13], "name": "Y_COORD"}
12349   ]
12350  },
12351  "PA_SC_PERFCOUNTER1_SELECT": {
12352   "fields": [
12353    {"bits": [0, 9], "name": "PERF_SEL"}
12354   ]
12355  },
12356  "PA_SC_RASTER_CONFIG": {
12357   "fields": [
12358    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
12359    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
12360    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
12361    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
12362    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
12363    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
12364    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
12365    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
12366    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
12367    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
12368    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
12369    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
12370    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
12371    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
12372    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
12373   ]
12374  },
12375  "PA_SC_RASTER_CONFIG_1": {
12376   "fields": [
12377    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
12378    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
12379    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
12380   ]
12381  },
12382  "PA_SC_SCREEN_EXTENT_CONTROL": {
12383   "fields": [
12384    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
12385    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
12386   ]
12387  },
12388  "PA_SC_SCREEN_EXTENT_MIN_0": {
12389   "fields": [
12390    {"bits": [0, 15], "name": "X"},
12391    {"bits": [16, 31], "name": "Y"}
12392   ]
12393  },
12394  "PA_SC_SCREEN_SCISSOR_BR": {
12395   "fields": [
12396    {"bits": [0, 15], "name": "BR_X"},
12397    {"bits": [16, 31], "name": "BR_Y"}
12398   ]
12399  },
12400  "PA_SC_SCREEN_SCISSOR_TL": {
12401   "fields": [
12402    {"bits": [0, 15], "name": "TL_X"},
12403    {"bits": [16, 31], "name": "TL_Y"}
12404   ]
12405  },
12406  "PA_SC_SHADER_CONTROL": {
12407   "fields": [
12408    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}
12409   ]
12410  },
12411  "PA_SC_VPORT_ZMAX_0": {
12412   "fields": [
12413    {"bits": [0, 31], "name": "VPORT_ZMAX"}
12414   ]
12415  },
12416  "PA_SC_VPORT_ZMIN_0": {
12417   "fields": [
12418    {"bits": [0, 31], "name": "VPORT_ZMIN"}
12419   ]
12420  },
12421  "PA_SC_WINDOW_OFFSET": {
12422   "fields": [
12423    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
12424    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
12425   ]
12426  },
12427  "PA_SU_HARDWARE_SCREEN_OFFSET": {
12428   "fields": [
12429    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
12430    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
12431   ]
12432  },
12433  "PA_SU_LINE_CNTL": {
12434   "fields": [
12435    {"bits": [0, 15], "name": "WIDTH"}
12436   ]
12437  },
12438  "PA_SU_LINE_STIPPLE_CNTL": {
12439   "fields": [
12440    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
12441    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
12442    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
12443    {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
12444   ]
12445  },
12446  "PA_SU_LINE_STIPPLE_SCALE": {
12447   "fields": [
12448    {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"}
12449   ]
12450  },
12451  "PA_SU_LINE_STIPPLE_VALUE": {
12452   "fields": [
12453    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
12454   ]
12455  },
12456  "PA_SU_PERFCOUNTER0_HI": {
12457   "fields": [
12458    {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
12459   ]
12460  },
12461  "PA_SU_PERFCOUNTER0_SELECT": {
12462   "fields": [
12463    {"bits": [0, 9], "name": "PERF_SEL"},
12464    {"bits": [10, 19], "name": "PERF_SEL1"},
12465    {"bits": [20, 23], "name": "CNTR_MODE"}
12466   ]
12467  },
12468  "PA_SU_PERFCOUNTER0_SELECT1": {
12469   "fields": [
12470    {"bits": [0, 9], "name": "PERF_SEL2"},
12471    {"bits": [10, 19], "name": "PERF_SEL3"}
12472   ]
12473  },
12474  "PA_SU_PERFCOUNTER2_SELECT": {
12475   "fields": [
12476    {"bits": [0, 9], "name": "PERF_SEL"},
12477    {"bits": [20, 23], "name": "CNTR_MODE"}
12478   ]
12479  },
12480  "PA_SU_POINT_MINMAX": {
12481   "fields": [
12482    {"bits": [0, 15], "name": "MIN_SIZE"},
12483    {"bits": [16, 31], "name": "MAX_SIZE"}
12484   ]
12485  },
12486  "PA_SU_POINT_SIZE": {
12487   "fields": [
12488    {"bits": [0, 15], "name": "HEIGHT"},
12489    {"bits": [16, 31], "name": "WIDTH"}
12490   ]
12491  },
12492  "PA_SU_POLY_OFFSET_CLAMP": {
12493   "fields": [
12494    {"bits": [0, 31], "name": "CLAMP"}
12495   ]
12496  },
12497  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
12498   "fields": [
12499    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
12500    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
12501   ]
12502  },
12503  "PA_SU_POLY_OFFSET_FRONT_OFFSET": {
12504   "fields": [
12505    {"bits": [0, 31], "name": "OFFSET"}
12506   ]
12507  },
12508  "PA_SU_POLY_OFFSET_FRONT_SCALE": {
12509   "fields": [
12510    {"bits": [0, 31], "name": "SCALE"}
12511   ]
12512  },
12513  "PA_SU_PRIM_FILTER_CNTL": {
12514   "fields": [
12515    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
12516    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
12517    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
12518    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
12519    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
12520    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
12521    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
12522    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
12523    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
12524    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
12525    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
12526   ]
12527  },
12528  "PA_SU_SC_MODE_CNTL": {
12529   "fields": [
12530    {"bits": [0, 0], "name": "CULL_FRONT"},
12531    {"bits": [1, 1], "name": "CULL_BACK"},
12532    {"bits": [2, 2], "name": "FACE"},
12533    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
12534    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
12535    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
12536    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
12537    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
12538    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
12539    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
12540    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
12541    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
12542    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}
12543   ]
12544  },
12545  "PA_SU_VTX_CNTL": {
12546   "fields": [
12547    {"bits": [0, 0], "name": "PIX_CENTER"},
12548    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
12549    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
12550   ]
12551  },
12552  "RLC_PERFCOUNTER0_SELECT": {
12553   "fields": [
12554    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
12555   ]
12556  },
12557  "RLC_PERFMON_CLK_CNTL": {
12558   "fields": [
12559    {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"}
12560   ]
12561  },
12562  "RLC_PERFMON_CNTL": {
12563   "fields": [
12564    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
12565    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
12566   ]
12567  },
12568  "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY": {
12569   "fields": [
12570    {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"},
12571    {"bits": [8, 31], "name": "RESERVED"}
12572   ]
12573  },
12574  "RLC_SPM_PERFMON_CNTL": {
12575   "fields": [
12576    {"bits": [0, 11], "name": "RESERVED1"},
12577    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
12578    {"bits": [14, 15], "name": "RESERVED"},
12579    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
12580   ]
12581  },
12582  "RLC_SPM_PERFMON_RING_BASE_HI": {
12583   "fields": [
12584    {"bits": [0, 15], "name": "RING_BASE_HI"},
12585    {"bits": [16, 31], "name": "RESERVED"}
12586   ]
12587  },
12588  "RLC_SPM_PERFMON_RING_BASE_LO": {
12589   "fields": [
12590    {"bits": [0, 31], "name": "RING_BASE_LO"}
12591   ]
12592  },
12593  "RLC_SPM_PERFMON_RING_SIZE": {
12594   "fields": [
12595    {"bits": [0, 31], "name": "RING_BASE_SIZE"}
12596   ]
12597  },
12598  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
12599   "fields": [
12600    {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"},
12601    {"bits": [8, 10], "name": "RESERVED1"},
12602    {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"},
12603    {"bits": [16, 20], "name": "SE0_NUM_LINE"},
12604    {"bits": [21, 25], "name": "SE1_NUM_LINE"},
12605    {"bits": [26, 30], "name": "SE2_NUM_LINE"},
12606    {"bits": [31, 31], "name": "RESERVED"}
12607   ]
12608  },
12609  "RLC_SPM_RING_RDPTR": {
12610   "fields": [
12611    {"bits": [0, 31], "name": "PERFMON_RING_RDPTR"}
12612   ]
12613  },
12614  "RLC_SPM_SEGMENT_THRESHOLD": {
12615   "fields": [
12616    {"bits": [0, 31], "name": "NUM_SEGMENT_THRESHOLD"}
12617   ]
12618  },
12619  "RLC_SPM_SE_MUXSEL_ADDR": {
12620   "fields": [
12621    {"bits": [0, 31], "name": "PERFMON_SEL_ADDR"}
12622   ]
12623  },
12624  "RLC_SPM_SE_MUXSEL_DATA": {
12625   "fields": [
12626    {"bits": [0, 31], "name": "PERFMON_SEL_DATA"}
12627   ]
12628  },
12629  "SCRATCH_ADDR": {
12630   "fields": [
12631    {"bits": [0, 31], "name": "OBSOLETE_ADDR"}
12632   ]
12633  },
12634  "SCRATCH_REG0": {
12635   "fields": [
12636    {"bits": [0, 31], "name": "SCRATCH_REG0"}
12637   ]
12638  },
12639  "SCRATCH_REG1": {
12640   "fields": [
12641    {"bits": [0, 31], "name": "SCRATCH_REG1"}
12642   ]
12643  },
12644  "SCRATCH_REG2": {
12645   "fields": [
12646    {"bits": [0, 31], "name": "SCRATCH_REG2"}
12647   ]
12648  },
12649  "SCRATCH_REG3": {
12650   "fields": [
12651    {"bits": [0, 31], "name": "SCRATCH_REG3"}
12652   ]
12653  },
12654  "SCRATCH_REG4": {
12655   "fields": [
12656    {"bits": [0, 31], "name": "SCRATCH_REG4"}
12657   ]
12658  },
12659  "SCRATCH_REG5": {
12660   "fields": [
12661    {"bits": [0, 31], "name": "SCRATCH_REG5"}
12662   ]
12663  },
12664  "SCRATCH_REG6": {
12665   "fields": [
12666    {"bits": [0, 31], "name": "SCRATCH_REG6"}
12667   ]
12668  },
12669  "SCRATCH_REG7": {
12670   "fields": [
12671    {"bits": [0, 31], "name": "SCRATCH_REG7"}
12672   ]
12673  },
12674  "SCRATCH_UMSK": {
12675   "fields": [
12676    {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
12677    {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
12678   ]
12679  },
12680  "SPI_BARYC_CNTL": {
12681   "fields": [
12682    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
12683    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
12684    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
12685    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
12686    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
12687    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
12688    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
12689   ]
12690  },
12691  "SPI_CONFIG_CNTL": {
12692   "fields": [
12693    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
12694    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
12695    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
12696    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
12697    {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
12698    {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}
12699   ]
12700  },
12701  "SPI_INTERP_CONTROL_0": {
12702   "fields": [
12703    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
12704    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
12705    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
12706    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
12707    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
12708    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
12709    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
12710   ]
12711  },
12712  "SPI_PERFCOUNTER4_SELECT": {
12713   "fields": [
12714    {"bits": [0, 7], "name": "PERF_SEL"}
12715   ]
12716  },
12717  "SPI_PERFCOUNTER_BINS": {
12718   "fields": [
12719    {"bits": [0, 3], "name": "BIN0_MIN"},
12720    {"bits": [4, 7], "name": "BIN0_MAX"},
12721    {"bits": [8, 11], "name": "BIN1_MIN"},
12722    {"bits": [12, 15], "name": "BIN1_MAX"},
12723    {"bits": [16, 19], "name": "BIN2_MIN"},
12724    {"bits": [20, 23], "name": "BIN2_MAX"},
12725    {"bits": [24, 27], "name": "BIN3_MIN"},
12726    {"bits": [28, 31], "name": "BIN3_MAX"}
12727   ]
12728  },
12729  "SPI_PS_INPUT_CNTL_0": {
12730   "fields": [
12731    {"bits": [0, 5], "name": "OFFSET"},
12732    {"bits": [8, 9], "name": "DEFAULT_VAL"},
12733    {"bits": [10, 10], "name": "FLAT_SHADE"},
12734    {"bits": [13, 16], "name": "CYL_WRAP"},
12735    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
12736    {"bits": [18, 18], "name": "DUP"},
12737    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
12738    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
12739    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
12740    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
12741    {"bits": [24, 24], "name": "ATTR0_VALID"},
12742    {"bits": [25, 25], "name": "ATTR1_VALID"}
12743   ]
12744  },
12745  "SPI_PS_INPUT_CNTL_20": {
12746   "fields": [
12747    {"bits": [0, 5], "name": "OFFSET"},
12748    {"bits": [8, 9], "name": "DEFAULT_VAL"},
12749    {"bits": [10, 10], "name": "FLAT_SHADE"},
12750    {"bits": [18, 18], "name": "DUP"},
12751    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
12752    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
12753    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
12754    {"bits": [24, 24], "name": "ATTR0_VALID"},
12755    {"bits": [25, 25], "name": "ATTR1_VALID"}
12756   ]
12757  },
12758  "SPI_PS_INPUT_ENA": {
12759   "fields": [
12760    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
12761    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
12762    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
12763    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
12764    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
12765    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
12766    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
12767    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
12768    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
12769    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
12770    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
12771    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
12772    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
12773    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
12774    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
12775    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
12776   ]
12777  },
12778  "SPI_PS_IN_CONTROL": {
12779   "fields": [
12780    {"bits": [0, 5], "name": "NUM_INTERP"},
12781    {"bits": [6, 6], "name": "PARAM_GEN"},
12782    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
12783   ]
12784  },
12785  "SPI_SHADER_COL_FORMAT": {
12786   "fields": [
12787    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
12788    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
12789    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
12790    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
12791    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
12792    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
12793    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
12794    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
12795   ]
12796  },
12797  "SPI_SHADER_LATE_ALLOC_VS": {
12798   "fields": [
12799    {"bits": [0, 5], "name": "LIMIT"}
12800   ]
12801  },
12802  "SPI_SHADER_PGM_RSRC1_GS": {
12803   "fields": [
12804    {"bits": [0, 5], "name": "VGPRS"},
12805    {"bits": [6, 9], "name": "SGPRS"},
12806    {"bits": [10, 11], "name": "PRIORITY"},
12807    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12808    {"bits": [20, 20], "name": "PRIV"},
12809    {"bits": [21, 21], "name": "DX10_CLAMP"},
12810    {"bits": [22, 22], "name": "DEBUG_MODE"},
12811    {"bits": [23, 23], "name": "IEEE_MODE"},
12812    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
12813    {"bits": [25, 27], "name": "CACHE_CTL"},
12814    {"bits": [28, 28], "name": "CDBG_USER"}
12815   ]
12816  },
12817  "SPI_SHADER_PGM_RSRC1_HS": {
12818   "fields": [
12819    {"bits": [0, 5], "name": "VGPRS"},
12820    {"bits": [6, 9], "name": "SGPRS"},
12821    {"bits": [10, 11], "name": "PRIORITY"},
12822    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12823    {"bits": [20, 20], "name": "PRIV"},
12824    {"bits": [21, 21], "name": "DX10_CLAMP"},
12825    {"bits": [22, 22], "name": "DEBUG_MODE"},
12826    {"bits": [23, 23], "name": "IEEE_MODE"},
12827    {"bits": [24, 26], "name": "CACHE_CTL"},
12828    {"bits": [27, 27], "name": "CDBG_USER"}
12829   ]
12830  },
12831  "SPI_SHADER_PGM_RSRC1_LS": {
12832   "fields": [
12833    {"bits": [0, 5], "name": "VGPRS"},
12834    {"bits": [6, 9], "name": "SGPRS"},
12835    {"bits": [10, 11], "name": "PRIORITY"},
12836    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12837    {"bits": [20, 20], "name": "PRIV"},
12838    {"bits": [21, 21], "name": "DX10_CLAMP"},
12839    {"bits": [22, 22], "name": "DEBUG_MODE"},
12840    {"bits": [23, 23], "name": "IEEE_MODE"},
12841    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
12842    {"bits": [26, 28], "name": "CACHE_CTL"},
12843    {"bits": [29, 29], "name": "CDBG_USER"}
12844   ]
12845  },
12846  "SPI_SHADER_PGM_RSRC1_PS": {
12847   "fields": [
12848    {"bits": [0, 5], "name": "VGPRS"},
12849    {"bits": [6, 9], "name": "SGPRS"},
12850    {"bits": [10, 11], "name": "PRIORITY"},
12851    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12852    {"bits": [20, 20], "name": "PRIV"},
12853    {"bits": [21, 21], "name": "DX10_CLAMP"},
12854    {"bits": [22, 22], "name": "DEBUG_MODE"},
12855    {"bits": [23, 23], "name": "IEEE_MODE"},
12856    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
12857    {"bits": [25, 27], "name": "CACHE_CTL"},
12858    {"bits": [28, 28], "name": "CDBG_USER"}
12859   ]
12860  },
12861  "SPI_SHADER_PGM_RSRC1_VS": {
12862   "fields": [
12863    {"bits": [0, 5], "name": "VGPRS"},
12864    {"bits": [6, 9], "name": "SGPRS"},
12865    {"bits": [10, 11], "name": "PRIORITY"},
12866    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
12867    {"bits": [20, 20], "name": "PRIV"},
12868    {"bits": [21, 21], "name": "DX10_CLAMP"},
12869    {"bits": [22, 22], "name": "DEBUG_MODE"},
12870    {"bits": [23, 23], "name": "IEEE_MODE"},
12871    {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
12872    {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
12873    {"bits": [27, 29], "name": "CACHE_CTL"},
12874    {"bits": [30, 30], "name": "CDBG_USER"}
12875   ]
12876  },
12877  "SPI_SHADER_PGM_RSRC2_ES_VS": {
12878   "fields": [
12879    {"bits": [0, 0], "name": "SCRATCH_EN"},
12880    {"bits": [1, 5], "name": "USER_SGPR"},
12881    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12882    {"bits": [7, 7], "name": "OC_LDS_EN"},
12883    {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12884    {"bits": [20, 28], "name": "LDS_SIZE"}
12885   ]
12886  },
12887  "SPI_SHADER_PGM_RSRC2_GS": {
12888   "fields": [
12889    {"bits": [0, 0], "name": "SCRATCH_EN"},
12890    {"bits": [1, 5], "name": "USER_SGPR"},
12891    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12892    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12893   ]
12894  },
12895  "SPI_SHADER_PGM_RSRC2_HS": {
12896   "fields": [
12897    {"bits": [0, 0], "name": "SCRATCH_EN"},
12898    {"bits": [1, 5], "name": "USER_SGPR"},
12899    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12900    {"bits": [7, 7], "name": "OC_LDS_EN"},
12901    {"bits": [8, 8], "name": "TG_SIZE_EN"},
12902    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12903   ]
12904  },
12905  "SPI_SHADER_PGM_RSRC2_LS_VS": {
12906   "fields": [
12907    {"bits": [0, 0], "name": "SCRATCH_EN"},
12908    {"bits": [1, 5], "name": "USER_SGPR"},
12909    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12910    {"bits": [7, 15], "name": "LDS_SIZE"},
12911    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12912   ]
12913  },
12914  "SPI_SHADER_PGM_RSRC2_PS": {
12915   "fields": [
12916    {"bits": [0, 0], "name": "SCRATCH_EN"},
12917    {"bits": [1, 5], "name": "USER_SGPR"},
12918    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12919    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
12920    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
12921    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
12922   ]
12923  },
12924  "SPI_SHADER_PGM_RSRC2_VS": {
12925   "fields": [
12926    {"bits": [0, 0], "name": "SCRATCH_EN"},
12927    {"bits": [1, 5], "name": "USER_SGPR"},
12928    {"bits": [6, 6], "name": "TRAP_PRESENT"},
12929    {"bits": [7, 7], "name": "OC_LDS_EN"},
12930    {"bits": [8, 8], "name": "SO_BASE0_EN"},
12931    {"bits": [9, 9], "name": "SO_BASE1_EN"},
12932    {"bits": [10, 10], "name": "SO_BASE2_EN"},
12933    {"bits": [11, 11], "name": "SO_BASE3_EN"},
12934    {"bits": [12, 12], "name": "SO_EN"},
12935    {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
12936    {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}
12937   ]
12938  },
12939  "SPI_SHADER_PGM_RSRC3_GS": {
12940   "fields": [
12941    {"bits": [0, 15], "name": "CU_EN"},
12942    {"bits": [16, 21], "name": "WAVE_LIMIT"},
12943    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
12944    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
12945   ]
12946  },
12947  "SPI_SHADER_PGM_RSRC3_HS": {
12948   "fields": [
12949    {"bits": [0, 5], "name": "WAVE_LIMIT"},
12950    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
12951    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}
12952   ]
12953  },
12954  "SPI_SHADER_PGM_RSRC3_PS": {
12955   "fields": [
12956    {"bits": [0, 15], "name": "CU_EN"},
12957    {"bits": [16, 21], "name": "WAVE_LIMIT"},
12958    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}
12959   ]
12960  },
12961  "SPI_SHADER_POS_FORMAT": {
12962   "fields": [
12963    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
12964    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
12965    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
12966    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
12967   ]
12968  },
12969  "SPI_SHADER_TBA_HI_PS": {
12970   "fields": [
12971    {"bits": [0, 7], "name": "MEM_BASE"}
12972   ]
12973  },
12974  "SPI_SHADER_TBA_LO_PS": {
12975   "fields": [
12976    {"bits": [0, 31], "name": "MEM_BASE"}
12977   ]
12978  },
12979  "SPI_SHADER_Z_FORMAT": {
12980   "fields": [
12981    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
12982   ]
12983  },
12984  "SPI_VS_OUT_CONFIG": {
12985   "fields": [
12986    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
12987    {"bits": [6, 6], "name": "VS_HALF_PACK"}
12988   ]
12989  },
12990  "SQC_CACHES": {
12991   "fields": [
12992    {"bits": [0, 0], "name": "TARGET_INST"},
12993    {"bits": [1, 1], "name": "TARGET_DATA"},
12994    {"bits": [2, 2], "name": "INVALIDATE"},
12995    {"bits": [3, 3], "name": "WRITEBACK"},
12996    {"bits": [4, 4], "name": "VOL"},
12997    {"bits": [16, 16], "name": "COMPLETE"}
12998   ]
12999  },
13000  "SQC_WRITEBACK": {
13001   "fields": [
13002    {"bits": [0, 0], "name": "DWB"},
13003    {"bits": [1, 1], "name": "DIRTY"}
13004   ]
13005  },
13006  "SQ_BUF_RSRC_WORD0": {
13007   "fields": [
13008    {"bits": [0, 31], "name": "BASE_ADDRESS"}
13009   ]
13010  },
13011  "SQ_BUF_RSRC_WORD1": {
13012   "fields": [
13013    {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
13014    {"bits": [16, 29], "name": "STRIDE"},
13015    {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
13016    {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
13017   ]
13018  },
13019  "SQ_BUF_RSRC_WORD2": {
13020   "fields": [
13021    {"bits": [0, 31], "name": "NUM_RECORDS"}
13022   ]
13023  },
13024  "SQ_BUF_RSRC_WORD3": {
13025   "fields": [
13026    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
13027    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
13028    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
13029    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
13030    {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
13031    {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
13032    {"bits": [19, 20], "name": "ELEMENT_SIZE"},
13033    {"bits": [21, 22], "name": "INDEX_STRIDE"},
13034    {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
13035    {"bits": [24, 24], "name": "ATC"},
13036    {"bits": [25, 25], "name": "HASH_ENABLE"},
13037    {"bits": [26, 26], "name": "HEAP"},
13038    {"bits": [27, 29], "name": "MTYPE"},
13039    {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
13040   ]
13041  },
13042  "SQ_IMG_RSRC_WORD1": {
13043   "fields": [
13044    {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
13045    {"bits": [8, 19], "name": "MIN_LOD"},
13046    {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
13047    {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
13048    {"bits": [30, 31], "name": "MTYPE"}
13049   ]
13050  },
13051  "SQ_IMG_RSRC_WORD2": {
13052   "fields": [
13053    {"bits": [0, 13], "name": "WIDTH"},
13054    {"bits": [14, 27], "name": "HEIGHT"},
13055    {"bits": [28, 30], "name": "PERF_MOD"},
13056    {"bits": [31, 31], "name": "INTERLACED"}
13057   ]
13058  },
13059  "SQ_IMG_RSRC_WORD3": {
13060   "fields": [
13061    {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
13062    {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
13063    {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
13064    {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
13065    {"bits": [12, 15], "name": "BASE_LEVEL"},
13066    {"bits": [16, 19], "name": "LAST_LEVEL"},
13067    {"bits": [20, 24], "name": "TILING_INDEX"},
13068    {"bits": [25, 25], "name": "POW2_PAD"},
13069    {"bits": [26, 26], "name": "MTYPE"},
13070    {"bits": [27, 27], "name": "ATC"},
13071    {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
13072   ]
13073  },
13074  "SQ_IMG_RSRC_WORD4": {
13075   "fields": [
13076    {"bits": [0, 12], "name": "DEPTH"},
13077    {"bits": [13, 26], "name": "PITCH"}
13078   ]
13079  },
13080  "SQ_IMG_RSRC_WORD5": {
13081   "fields": [
13082    {"bits": [0, 12], "name": "BASE_ARRAY"},
13083    {"bits": [13, 25], "name": "LAST_ARRAY"}
13084   ]
13085  },
13086  "SQ_IMG_RSRC_WORD6": {
13087   "fields": [
13088    {"bits": [0, 11], "name": "MIN_LOD_WARN"},
13089    {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
13090    {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
13091    {"bits": [21, 21], "name": "COMPRESSION_EN"},
13092    {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"},
13093    {"bits": [23, 23], "name": "COLOR_TRANSFORM"},
13094    {"bits": [24, 27], "name": "LOST_ALPHA_BITS"},
13095    {"bits": [28, 31], "name": "LOST_COLOR_BITS"}
13096   ]
13097  },
13098  "SQ_IMG_RSRC_WORD7": {
13099   "fields": [
13100    {"bits": [0, 31], "name": "META_DATA_ADDRESS"}
13101   ]
13102  },
13103  "SQ_IMG_SAMP_WORD0": {
13104   "fields": [
13105    {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
13106    {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
13107    {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
13108    {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
13109    {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
13110    {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
13111    {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
13112    {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
13113    {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
13114    {"bits": [21, 26], "name": "ANISO_BIAS"},
13115    {"bits": [27, 27], "name": "TRUNC_COORD"},
13116    {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
13117    {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"},
13118    {"bits": [31, 31], "name": "COMPAT_MODE"}
13119   ]
13120  },
13121  "SQ_IMG_SAMP_WORD1": {
13122   "fields": [
13123    {"bits": [0, 11], "name": "MIN_LOD"},
13124    {"bits": [12, 23], "name": "MAX_LOD"},
13125    {"bits": [24, 27], "name": "PERF_MIP"},
13126    {"bits": [28, 31], "name": "PERF_Z"}
13127   ]
13128  },
13129  "SQ_IMG_SAMP_WORD2": {
13130   "fields": [
13131    {"bits": [0, 13], "name": "LOD_BIAS"},
13132    {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
13133    {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
13134    {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
13135    {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
13136    {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
13137    {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
13138    {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},
13139    {"bits": [30, 30], "name": "FILTER_PREC_FIX"},
13140    {"bits": [31, 31], "name": "ANISO_OVERRIDE"}
13141   ]
13142  },
13143  "SQ_IMG_SAMP_WORD3": {
13144   "fields": [
13145    {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
13146    {"bits": [29, 29], "name": "UPGRADED_DEPTH"},
13147    {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
13148   ]
13149  },
13150  "SQ_PERFCOUNTER0_SELECT": {
13151   "fields": [
13152    {"bits": [0, 8], "name": "PERF_SEL"},
13153    {"bits": [12, 15], "name": "SQC_BANK_MASK"},
13154    {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
13155    {"bits": [20, 23], "name": "SPM_MODE"},
13156    {"bits": [24, 27], "name": "SIMD_MASK"},
13157    {"bits": [28, 31], "name": "PERF_MODE"}
13158   ]
13159  },
13160  "SQ_PERFCOUNTER_CTRL": {
13161   "fields": [
13162    {"bits": [0, 0], "name": "PS_EN"},
13163    {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
13164    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
13165    {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
13166    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
13167    {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
13168    {"bits": [6, 6], "name": "CS_EN"},
13169    {"bits": [8, 12], "name": "CNTR_RATE"},
13170    {"bits": [13, 13], "name": "DISABLE_FLUSH"}
13171   ]
13172  },
13173  "SQ_PERFCOUNTER_CTRL2": {
13174   "fields": [
13175    {"bits": [0, 0], "name": "FORCE_EN"}
13176   ]
13177  },
13178  "SQ_PERFCOUNTER_MASK": {
13179   "fields": [
13180    {"bits": [0, 15], "name": "SH0_MASK"},
13181    {"bits": [16, 31], "name": "SH1_MASK"}
13182   ]
13183  },
13184  "SQ_THREAD_TRACE_BASE2": {
13185   "fields": [
13186    {"bits": [0, 3], "name": "ADDR_HI"}
13187   ]
13188  },
13189  "SQ_THREAD_TRACE_CNTR": {
13190   "fields": [
13191    {"bits": [0, 31], "name": "CNTR"}
13192   ]
13193  },
13194  "SQ_THREAD_TRACE_CTRL": {
13195   "fields": [
13196    {"bits": [31, 31], "name": "RESET_BUFFER"}
13197   ]
13198  },
13199  "SQ_THREAD_TRACE_HIWATER": {
13200   "fields": [
13201    {"bits": [0, 2], "name": "HIWATER"}
13202   ]
13203  },
13204  "SQ_THREAD_TRACE_MASK": {
13205   "fields": [
13206    {"bits": [0, 4], "name": "CU_SEL"},
13207    {"bits": [5, 5], "name": "SH_SEL"},
13208    {"bits": [7, 7], "name": "REG_STALL_EN"},
13209    {"bits": [8, 11], "name": "SIMD_EN"},
13210    {"bits": [12, 13], "name": "VM_ID_MASK"},
13211    {"bits": [14, 14], "name": "SPI_STALL_EN"},
13212    {"bits": [15, 15], "name": "SQ_STALL_EN"},
13213    {"bits": [16, 31], "name": "RANDOM_SEED"}
13214   ]
13215  },
13216  "SQ_THREAD_TRACE_MODE": {
13217   "fields": [
13218    {"bits": [0, 2], "name": "MASK_PS"},
13219    {"bits": [3, 5], "name": "MASK_VS"},
13220    {"bits": [6, 8], "name": "MASK_GS"},
13221    {"bits": [9, 11], "name": "MASK_ES"},
13222    {"bits": [12, 14], "name": "MASK_HS"},
13223    {"bits": [15, 17], "name": "MASK_LS"},
13224    {"bits": [18, 20], "name": "MASK_CS"},
13225    {"bits": [21, 22], "name": "MODE"},
13226    {"bits": [23, 24], "name": "CAPTURE_MODE"},
13227    {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
13228    {"bits": [26, 26], "name": "PRIV"},
13229    {"bits": [27, 28], "name": "ISSUE_MASK"},
13230    {"bits": [29, 29], "name": "TEST_MODE"},
13231    {"bits": [30, 30], "name": "INTERRUPT_EN"},
13232    {"bits": [31, 31], "name": "WRAP"}
13233   ]
13234  },
13235  "SQ_THREAD_TRACE_SIZE": {
13236   "fields": [
13237    {"bits": [0, 21], "name": "SIZE"}
13238   ]
13239  },
13240  "SQ_THREAD_TRACE_STATUS": {
13241   "fields": [
13242    {"bits": [0, 9], "name": "FINISH_PENDING"},
13243    {"bits": [16, 25], "name": "FINISH_DONE"},
13244    {"bits": [29, 29], "name": "NEW_BUF"},
13245    {"bits": [30, 30], "name": "BUSY"},
13246    {"bits": [31, 31], "name": "FULL"}
13247   ]
13248  },
13249  "SQ_THREAD_TRACE_TOKEN_MASK": {
13250   "fields": [
13251    {"bits": [0, 15], "name": "TOKEN_MASK"},
13252    {"bits": [16, 23], "name": "REG_MASK"},
13253    {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
13254   ]
13255  },
13256  "SQ_THREAD_TRACE_TOKEN_MASK2": {
13257   "fields": [
13258    {"bits": [0, 31], "name": "INST_MASK"}
13259   ]
13260  },
13261  "SQ_THREAD_TRACE_WPTR": {
13262   "fields": [
13263    {"bits": [0, 29], "name": "WPTR"},
13264    {"bits": [30, 31], "name": "READ_OFFSET"}
13265   ]
13266  },
13267  "SQ_WAVE_EXEC_HI": {
13268   "fields": [
13269    {"bits": [0, 31], "name": "EXEC_HI"}
13270   ]
13271  },
13272  "SQ_WAVE_EXEC_LO": {
13273   "fields": [
13274    {"bits": [0, 31], "name": "EXEC_LO"}
13275   ]
13276  },
13277  "SQ_WAVE_GPR_ALLOC": {
13278   "fields": [
13279    {"bits": [0, 5], "name": "VGPR_BASE"},
13280    {"bits": [8, 13], "name": "VGPR_SIZE"},
13281    {"bits": [16, 21], "name": "SGPR_BASE"},
13282    {"bits": [24, 27], "name": "SGPR_SIZE"}
13283   ]
13284  },
13285  "SQ_WAVE_HW_ID": {
13286   "fields": [
13287    {"bits": [0, 3], "name": "WAVE_ID"},
13288    {"bits": [4, 5], "name": "SIMD_ID"},
13289    {"bits": [6, 7], "name": "PIPE_ID"},
13290    {"bits": [8, 11], "name": "CU_ID"},
13291    {"bits": [12, 12], "name": "SH_ID"},
13292    {"bits": [13, 14], "name": "SE_ID"},
13293    {"bits": [16, 19], "name": "TG_ID"},
13294    {"bits": [20, 23], "name": "VM_ID"},
13295    {"bits": [24, 26], "name": "QUEUE_ID"},
13296    {"bits": [27, 29], "name": "STATE_ID"},
13297    {"bits": [30, 31], "name": "ME_ID"}
13298   ]
13299  },
13300  "SQ_WAVE_IB_DBG0": {
13301   "fields": [
13302    {"bits": [0, 2], "name": "IBUF_ST"},
13303    {"bits": [3, 3], "name": "PC_INVALID"},
13304    {"bits": [4, 4], "name": "NEED_NEXT_DW"},
13305    {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
13306    {"bits": [8, 9], "name": "IBUF_RPTR"},
13307    {"bits": [10, 11], "name": "IBUF_WPTR"},
13308    {"bits": [16, 19], "name": "INST_STR_ST"},
13309    {"bits": [20, 23], "name": "MISC_CNT"},
13310    {"bits": [24, 25], "name": "ECC_ST"},
13311    {"bits": [26, 26], "name": "IS_HYB"},
13312    {"bits": [27, 28], "name": "HYB_CNT"},
13313    {"bits": [29, 29], "name": "KILL"},
13314    {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}
13315   ]
13316  },
13317  "SQ_WAVE_IB_DBG1": {
13318   "fields": [
13319    {"bits": [0, 0], "name": "IXNACK"},
13320    {"bits": [1, 1], "name": "XNACK"},
13321    {"bits": [2, 2], "name": "TA_NEED_RESET"},
13322    {"bits": [4, 7], "name": "XCNT"},
13323    {"bits": [8, 11], "name": "QCNT"}
13324   ]
13325  },
13326  "SQ_WAVE_IB_STS": {
13327   "fields": [
13328    {"bits": [0, 3], "name": "VM_CNT"},
13329    {"bits": [4, 6], "name": "EXP_CNT"},
13330    {"bits": [8, 11], "name": "LGKM_CNT"},
13331    {"bits": [12, 14], "name": "VALU_CNT"},
13332    {"bits": [15, 15], "name": "FIRST_REPLAY"},
13333    {"bits": [16, 19], "name": "RCNT"}
13334   ]
13335  },
13336  "SQ_WAVE_INST_DW0": {
13337   "fields": [
13338    {"bits": [0, 31], "name": "INST_DW0"}
13339   ]
13340  },
13341  "SQ_WAVE_INST_DW1": {
13342   "fields": [
13343    {"bits": [0, 31], "name": "INST_DW1"}
13344   ]
13345  },
13346  "SQ_WAVE_LDS_ALLOC": {
13347   "fields": [
13348    {"bits": [0, 7], "name": "LDS_BASE"},
13349    {"bits": [12, 20], "name": "LDS_SIZE"}
13350   ]
13351  },
13352  "SQ_WAVE_M0": {
13353   "fields": [
13354    {"bits": [0, 31], "name": "M0"}
13355   ]
13356  },
13357  "SQ_WAVE_MODE": {
13358   "fields": [
13359    {"bits": [0, 3], "name": "FP_ROUND"},
13360    {"bits": [4, 7], "name": "FP_DENORM"},
13361    {"bits": [8, 8], "name": "DX10_CLAMP"},
13362    {"bits": [9, 9], "name": "IEEE"},
13363    {"bits": [10, 10], "name": "LOD_CLAMPED"},
13364    {"bits": [11, 11], "name": "DEBUG_EN"},
13365    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
13366    {"bits": [27, 27], "name": "GPR_IDX_EN"},
13367    {"bits": [28, 28], "name": "VSKIP"},
13368    {"bits": [29, 31], "name": "CSP"}
13369   ]
13370  },
13371  "SQ_WAVE_PC_HI": {
13372   "fields": [
13373    {"bits": [0, 15], "name": "PC_HI"}
13374   ]
13375  },
13376  "SQ_WAVE_PC_LO": {
13377   "fields": [
13378    {"bits": [0, 31], "name": "PC_LO"}
13379   ]
13380  },
13381  "SQ_WAVE_STATUS": {
13382   "fields": [
13383    {"bits": [0, 0], "name": "SCC"},
13384    {"bits": [1, 2], "name": "SPI_PRIO"},
13385    {"bits": [3, 4], "name": "USER_PRIO"},
13386    {"bits": [5, 5], "name": "PRIV"},
13387    {"bits": [6, 6], "name": "TRAP_EN"},
13388    {"bits": [7, 7], "name": "TTRACE_EN"},
13389    {"bits": [8, 8], "name": "EXPORT_RDY"},
13390    {"bits": [9, 9], "name": "EXECZ"},
13391    {"bits": [10, 10], "name": "VCCZ"},
13392    {"bits": [11, 11], "name": "IN_TG"},
13393    {"bits": [12, 12], "name": "IN_BARRIER"},
13394    {"bits": [13, 13], "name": "HALT"},
13395    {"bits": [14, 14], "name": "TRAP"},
13396    {"bits": [15, 15], "name": "TTRACE_CU_EN"},
13397    {"bits": [16, 16], "name": "VALID"},
13398    {"bits": [17, 17], "name": "ECC_ERR"},
13399    {"bits": [18, 18], "name": "SKIP_EXPORT"},
13400    {"bits": [19, 19], "name": "PERF_EN"},
13401    {"bits": [20, 20], "name": "COND_DBG_USER"},
13402    {"bits": [21, 21], "name": "COND_DBG_SYS"},
13403    {"bits": [22, 22], "name": "ALLOW_REPLAY"},
13404    {"bits": [23, 23], "name": "INST_ATC"},
13405    {"bits": [27, 27], "name": "MUST_EXPORT"}
13406   ]
13407  },
13408  "SQ_WAVE_TBA_HI": {
13409   "fields": [
13410    {"bits": [0, 7], "name": "ADDR_HI"}
13411   ]
13412  },
13413  "SQ_WAVE_TRAPSTS": {
13414   "fields": [
13415    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
13416    {"bits": [10, 10], "name": "SAVECTX"},
13417    {"bits": [16, 21], "name": "EXCP_CYCLE"},
13418    {"bits": [29, 31], "name": "DP_RATE"}
13419   ]
13420  },
13421  "SX_BLEND_OPT_CONTROL": {
13422   "fields": [
13423    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
13424    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
13425    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
13426    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
13427    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
13428    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
13429    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
13430    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
13431    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
13432    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
13433    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
13434    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
13435    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
13436    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
13437    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
13438    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
13439    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
13440   ]
13441  },
13442  "SX_BLEND_OPT_EPSILON": {
13443   "fields": [
13444    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
13445    {"bits": [4, 7], "name": "MRT1_EPSILON"},
13446    {"bits": [8, 11], "name": "MRT2_EPSILON"},
13447    {"bits": [12, 15], "name": "MRT3_EPSILON"},
13448    {"bits": [16, 19], "name": "MRT4_EPSILON"},
13449    {"bits": [20, 23], "name": "MRT5_EPSILON"},
13450    {"bits": [24, 27], "name": "MRT6_EPSILON"},
13451    {"bits": [28, 31], "name": "MRT7_EPSILON"}
13452   ]
13453  },
13454  "SX_MRT0_BLEND_OPT": {
13455   "fields": [
13456    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
13457    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
13458    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
13459    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
13460    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
13461    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
13462   ]
13463  },
13464  "SX_PERFCOUNTER0_SELECT": {
13465   "fields": [
13466    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"},
13467    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"},
13468    {"bits": [20, 23], "name": "CNTR_MODE"}
13469   ]
13470  },
13471  "SX_PERFCOUNTER0_SELECT1": {
13472   "fields": [
13473    {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"},
13474    {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"}
13475   ]
13476  },
13477  "SX_PS_DOWNCONVERT": {
13478   "fields": [
13479    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
13480    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
13481    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
13482    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
13483    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
13484    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
13485    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
13486    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
13487   ]
13488  },
13489  "TA_BC_BASE_ADDR": {
13490   "fields": [
13491    {"bits": [0, 31], "name": "ADDRESS"}
13492   ]
13493  },
13494  "TA_BC_BASE_ADDR_HI": {
13495   "fields": [
13496    {"bits": [0, 7], "name": "ADDRESS"}
13497   ]
13498  },
13499  "TCC_PERFCOUNTER0_SELECT1": {
13500   "fields": [
13501    {"bits": [0, 9], "name": "PERF_SEL2"},
13502    {"bits": [10, 19], "name": "PERF_SEL3"},
13503    {"bits": [24, 27], "name": "PERF_MODE2"},
13504    {"bits": [28, 31], "name": "PERF_MODE3"}
13505   ]
13506  },
13507  "TCC_PERFCOUNTER2_SELECT": {
13508   "fields": [
13509    {"bits": [0, 9], "name": "PERF_SEL"},
13510    {"bits": [20, 23], "name": "CNTR_MODE"},
13511    {"bits": [28, 31], "name": "PERF_MODE"}
13512   ]
13513  },
13514  "TD_PERFCOUNTER0_SELECT": {
13515   "fields": [
13516    {"bits": [0, 7], "name": "PERF_SEL"},
13517    {"bits": [10, 17], "name": "PERF_SEL1"},
13518    {"bits": [20, 23], "name": "CNTR_MODE"},
13519    {"bits": [24, 27], "name": "PERF_MODE1"},
13520    {"bits": [28, 31], "name": "PERF_MODE"}
13521   ]
13522  },
13523  "TD_PERFCOUNTER0_SELECT1": {
13524   "fields": [
13525    {"bits": [0, 7], "name": "PERF_SEL2"},
13526    {"bits": [10, 17], "name": "PERF_SEL3"},
13527    {"bits": [24, 27], "name": "PERF_MODE3"},
13528    {"bits": [28, 31], "name": "PERF_MODE2"}
13529   ]
13530  },
13531  "VGT_DISPATCH_DRAW_INDEX": {
13532   "fields": [
13533    {"bits": [0, 31], "name": "MATCH_INDEX"}
13534   ]
13535  },
13536  "VGT_DMA_BASE": {
13537   "fields": [
13538    {"bits": [0, 31], "name": "BASE_ADDR"}
13539   ]
13540  },
13541  "VGT_DMA_BASE_HI": {
13542   "fields": [
13543    {"bits": [0, 7], "name": "BASE_ADDR"}
13544   ]
13545  },
13546  "VGT_DMA_INDEX_TYPE": {
13547   "fields": [
13548    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
13549    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
13550    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
13551    {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
13552    {"bits": [9, 9], "name": "NOT_EOP"},
13553    {"bits": [10, 10], "name": "REQ_PATH"},
13554    {"bits": [11, 12], "name": "MTYPE"}
13555   ]
13556  },
13557  "VGT_DMA_MAX_SIZE": {
13558   "fields": [
13559    {"bits": [0, 31], "name": "MAX_SIZE"}
13560   ]
13561  },
13562  "VGT_DMA_NUM_INSTANCES": {
13563   "fields": [
13564    {"bits": [0, 31], "name": "NUM_INSTANCES"}
13565   ]
13566  },
13567  "VGT_DMA_SIZE": {
13568   "fields": [
13569    {"bits": [0, 31], "name": "NUM_INDICES"}
13570   ]
13571  },
13572  "VGT_DRAW_INITIATOR": {
13573   "fields": [
13574    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
13575    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
13576    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
13577    {"bits": [5, 5], "name": "NOT_EOP"},
13578    {"bits": [6, 6], "name": "USE_OPAQUE"}
13579   ]
13580  },
13581  "VGT_ESGS_RING_ITEMSIZE": {
13582   "fields": [
13583    {"bits": [0, 14], "name": "ITEMSIZE"}
13584   ]
13585  },
13586  "VGT_ESGS_RING_SIZE": {
13587   "fields": [
13588    {"bits": [0, 31], "name": "MEM_SIZE"}
13589   ]
13590  },
13591  "VGT_ES_PER_GS": {
13592   "fields": [
13593    {"bits": [0, 10], "name": "ES_PER_GS"}
13594   ]
13595  },
13596  "VGT_EVENT_ADDRESS_REG": {
13597   "fields": [
13598    {"bits": [0, 27], "name": "ADDRESS_LOW"}
13599   ]
13600  },
13601  "VGT_EVENT_INITIATOR": {
13602   "fields": [
13603    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
13604    {"bits": [18, 26], "name": "ADDRESS_HI"},
13605    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
13606   ]
13607  },
13608  "VGT_GROUP_DECR": {
13609   "fields": [
13610    {"bits": [0, 3], "name": "DECR"}
13611   ]
13612  },
13613  "VGT_GROUP_FIRST_DECR": {
13614   "fields": [
13615    {"bits": [0, 3], "name": "FIRST_DECR"}
13616   ]
13617  },
13618  "VGT_GROUP_PRIM_TYPE": {
13619   "fields": [
13620    {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
13621    {"bits": [14, 14], "name": "RETAIN_ORDER"},
13622    {"bits": [15, 15], "name": "RETAIN_QUADS"},
13623    {"bits": [16, 18], "name": "PRIM_ORDER"}
13624   ]
13625  },
13626  "VGT_GROUP_VECT_0_CNTL": {
13627   "fields": [
13628    {"bits": [0, 0], "name": "COMP_X_EN"},
13629    {"bits": [1, 1], "name": "COMP_Y_EN"},
13630    {"bits": [2, 2], "name": "COMP_Z_EN"},
13631    {"bits": [3, 3], "name": "COMP_W_EN"},
13632    {"bits": [8, 15], "name": "STRIDE"},
13633    {"bits": [16, 23], "name": "SHIFT"}
13634   ]
13635  },
13636  "VGT_GROUP_VECT_0_FMT_CNTL": {
13637   "fields": [
13638    {"bits": [0, 3], "name": "X_CONV"},
13639    {"bits": [4, 7], "name": "X_OFFSET"},
13640    {"bits": [8, 11], "name": "Y_CONV"},
13641    {"bits": [12, 15], "name": "Y_OFFSET"},
13642    {"bits": [16, 19], "name": "Z_CONV"},
13643    {"bits": [20, 23], "name": "Z_OFFSET"},
13644    {"bits": [24, 27], "name": "W_CONV"},
13645    {"bits": [28, 31], "name": "W_OFFSET"}
13646   ]
13647  },
13648  "VGT_GSVS_RING_OFFSET_1": {
13649   "fields": [
13650    {"bits": [0, 14], "name": "OFFSET"}
13651   ]
13652  },
13653  "VGT_GS_INSTANCE_CNT": {
13654   "fields": [
13655    {"bits": [0, 0], "name": "ENABLE"},
13656    {"bits": [2, 8], "name": "CNT"}
13657   ]
13658  },
13659  "VGT_GS_MAX_VERT_OUT": {
13660   "fields": [
13661    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
13662   ]
13663  },
13664  "VGT_GS_MODE": {
13665   "fields": [
13666    {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
13667    {"bits": [3, 3], "name": "RESERVED_0"},
13668    {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
13669    {"bits": [6, 10], "name": "RESERVED_1"},
13670    {"bits": [11, 11], "name": "GS_C_PACK_EN"},
13671    {"bits": [12, 12], "name": "RESERVED_2"},
13672    {"bits": [13, 13], "name": "ES_PASSTHRU"},
13673    {"bits": [14, 14], "name": "RESERVED_3"},
13674    {"bits": [15, 15], "name": "RESERVED_4"},
13675    {"bits": [16, 16], "name": "RESERVED_5"},
13676    {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
13677    {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
13678    {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
13679    {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
13680    {"bits": [21, 22], "name": "ONCHIP"}
13681   ]
13682  },
13683  "VGT_GS_ONCHIP_CNTL": {
13684   "fields": [
13685    {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"},
13686    {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}
13687   ]
13688  },
13689  "VGT_GS_OUT_PRIM_TYPE": {
13690   "fields": [
13691    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
13692    {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
13693    {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
13694    {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
13695    {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
13696   ]
13697  },
13698  "VGT_GS_PER_ES": {
13699   "fields": [
13700    {"bits": [0, 10], "name": "GS_PER_ES"}
13701   ]
13702  },
13703  "VGT_GS_PER_VS": {
13704   "fields": [
13705    {"bits": [0, 3], "name": "GS_PER_VS"}
13706   ]
13707  },
13708  "VGT_HOS_CNTL": {
13709   "fields": [
13710    {"bits": [0, 1], "name": "TESS_MODE"}
13711   ]
13712  },
13713  "VGT_HOS_MAX_TESS_LEVEL": {
13714   "fields": [
13715    {"bits": [0, 31], "name": "MAX_TESS"}
13716   ]
13717  },
13718  "VGT_HOS_MIN_TESS_LEVEL": {
13719   "fields": [
13720    {"bits": [0, 31], "name": "MIN_TESS"}
13721   ]
13722  },
13723  "VGT_HOS_REUSE_DEPTH": {
13724   "fields": [
13725    {"bits": [0, 7], "name": "REUSE_DEPTH"}
13726   ]
13727  },
13728  "VGT_HS_OFFCHIP_PARAM": {
13729   "fields": [
13730    {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"},
13731    {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
13732   ]
13733  },
13734  "VGT_INDX_OFFSET": {
13735   "fields": [
13736    {"bits": [0, 31], "name": "INDX_OFFSET"}
13737   ]
13738  },
13739  "VGT_INSTANCE_STEP_RATE_0": {
13740   "fields": [
13741    {"bits": [0, 31], "name": "STEP_RATE"}
13742   ]
13743  },
13744  "VGT_LS_HS_CONFIG": {
13745   "fields": [
13746    {"bits": [0, 7], "name": "NUM_PATCHES"},
13747    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
13748    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
13749   ]
13750  },
13751  "VGT_MAX_VTX_INDX": {
13752   "fields": [
13753    {"bits": [0, 31], "name": "MAX_INDX"}
13754   ]
13755  },
13756  "VGT_MIN_VTX_INDX": {
13757   "fields": [
13758    {"bits": [0, 31], "name": "MIN_INDX"}
13759   ]
13760  },
13761  "VGT_MULTI_PRIM_IB_RESET_EN": {
13762   "fields": [
13763    {"bits": [0, 0], "name": "RESET_EN"}
13764   ]
13765  },
13766  "VGT_MULTI_PRIM_IB_RESET_INDX": {
13767   "fields": [
13768    {"bits": [0, 31], "name": "RESET_INDX"}
13769   ]
13770  },
13771  "VGT_OUTPUT_PATH_CNTL": {
13772   "fields": [
13773    {"bits": [0, 2], "name": "PATH_SELECT"}
13774   ]
13775  },
13776  "VGT_OUT_DEALLOC_CNTL": {
13777   "fields": [
13778    {"bits": [0, 6], "name": "DEALLOC_DIST"}
13779   ]
13780  },
13781  "VGT_PERFCOUNTER2_SELECT": {
13782   "fields": [
13783    {"bits": [0, 7], "name": "PERF_SEL"},
13784    {"bits": [28, 31], "name": "PERF_MODE"}
13785   ]
13786  },
13787  "VGT_PERFCOUNTER_SEID_MASK": {
13788   "fields": [
13789    {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
13790   ]
13791  },
13792  "VGT_PRIMITIVEID_EN": {
13793   "fields": [
13794    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
13795    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}
13796   ]
13797  },
13798  "VGT_PRIMITIVEID_RESET": {
13799   "fields": [
13800    {"bits": [0, 31], "name": "VALUE"}
13801   ]
13802  },
13803  "VGT_PRIMITIVE_TYPE": {
13804   "fields": [
13805    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
13806   ]
13807  },
13808  "VGT_REUSE_OFF": {
13809   "fields": [
13810    {"bits": [0, 0], "name": "REUSE_OFF"}
13811   ]
13812  },
13813  "VGT_SHADER_STAGES_EN": {
13814   "fields": [
13815    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
13816    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
13817    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
13818    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
13819    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
13820    {"bits": [8, 8], "name": "DYNAMIC_HS"},
13821    {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"},
13822    {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"},
13823    {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"},
13824    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}
13825   ]
13826  },
13827  "VGT_STRMOUT_BUFFER_CONFIG": {
13828   "fields": [
13829    {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
13830    {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
13831    {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
13832    {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
13833   ]
13834  },
13835  "VGT_STRMOUT_CONFIG": {
13836   "fields": [
13837    {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
13838    {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
13839    {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
13840    {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
13841    {"bits": [4, 6], "name": "RAST_STREAM"},
13842    {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
13843    {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
13844   ]
13845  },
13846  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
13847   "fields": [
13848    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
13849   ]
13850  },
13851  "VGT_STRMOUT_VTX_STRIDE_0": {
13852   "fields": [
13853    {"bits": [0, 9], "name": "STRIDE"}
13854   ]
13855  },
13856  "VGT_TESS_DISTRIBUTION": {
13857   "fields": [
13858    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
13859    {"bits": [8, 15], "name": "ACCUM_TRI"},
13860    {"bits": [16, 23], "name": "ACCUM_QUAD"},
13861    {"bits": [24, 31], "name": "DONUT_SPLIT"}
13862   ]
13863  },
13864  "VGT_TF_MEMORY_BASE": {
13865   "fields": [
13866    {"bits": [0, 31], "name": "BASE"}
13867   ]
13868  },
13869  "VGT_TF_PARAM": {
13870   "fields": [
13871    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
13872    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
13873    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
13874    {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
13875    {"bits": [9, 9], "name": "DEPRECATED"},
13876    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
13877    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
13878    {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
13879    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
13880    {"bits": [19, 20], "name": "MTYPE"}
13881   ]
13882  },
13883  "VGT_TF_RING_SIZE": {
13884   "fields": [
13885    {"bits": [0, 15], "name": "SIZE"}
13886   ]
13887  },
13888  "VGT_VERTEX_REUSE_BLOCK_CNTL": {
13889   "fields": [
13890    {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
13891   ]
13892  },
13893  "VGT_VTX_CNT_EN": {
13894   "fields": [
13895    {"bits": [0, 0], "name": "VTX_CNT_EN"}
13896   ]
13897  }
13898 }
13899}
13900