1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(0), 241 UINT64_C(0), 242 UINT64_C(0), 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(0), 247 UINT64_C(0), 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(0), 251 UINT64_C(0), 252 UINT64_C(0), 253 UINT64_C(0), 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(0), 257 UINT64_C(0), 258 UINT64_C(0), 259 UINT64_C(0), 260 UINT64_C(0), 261 UINT64_C(0), 262 UINT64_C(0), 263 UINT64_C(0), 264 UINT64_C(0), 265 UINT64_C(0), 266 UINT64_C(0), 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(0), 270 UINT64_C(0), 271 UINT64_C(0), 272 UINT64_C(0), 273 UINT64_C(0), 274 UINT64_C(0), 275 UINT64_C(0), 276 UINT64_C(0), 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(0), 287 UINT64_C(0), 288 UINT64_C(0), 289 UINT64_C(0), 290 UINT64_C(0), 291 UINT64_C(0), 292 UINT64_C(0), 293 UINT64_C(0), 294 UINT64_C(0), 295 UINT64_C(0), 296 UINT64_C(0), 297 UINT64_C(0), 298 UINT64_C(0), 299 UINT64_C(0), 300 UINT64_C(0), 301 UINT64_C(0), 302 UINT64_C(0), 303 UINT64_C(0), 304 UINT64_C(0), 305 UINT64_C(0), 306 UINT64_C(0), 307 UINT64_C(0), 308 UINT64_C(0), 309 UINT64_C(0), 310 UINT64_C(0), 311 UINT64_C(0), 312 UINT64_C(0), 313 UINT64_C(0), 314 UINT64_C(0), 315 UINT64_C(0), 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(0), 324 UINT64_C(0), 325 UINT64_C(0), 326 UINT64_C(0), 327 UINT64_C(0), 328 UINT64_C(0), 329 UINT64_C(0), 330 UINT64_C(0), 331 UINT64_C(0), 332 UINT64_C(0), 333 UINT64_C(0), 334 UINT64_C(0), 335 UINT64_C(0), 336 UINT64_C(0), 337 UINT64_C(0), 338 UINT64_C(0), 339 UINT64_C(0), 340 UINT64_C(0), 341 UINT64_C(0), 342 UINT64_C(0), 343 UINT64_C(0), 344 UINT64_C(0), 345 UINT64_C(0), 346 UINT64_C(0), 347 UINT64_C(0), 348 UINT64_C(0), 349 UINT64_C(0), 350 UINT64_C(0), 351 UINT64_C(0), 352 UINT64_C(0), 353 UINT64_C(0), 354 UINT64_C(0), 355 UINT64_C(0), 356 UINT64_C(0), 357 UINT64_C(0), 358 UINT64_C(0), 359 UINT64_C(0), 360 UINT64_C(0), 361 UINT64_C(0), 362 UINT64_C(0), 363 UINT64_C(0), 364 UINT64_C(0), 365 UINT64_C(0), 366 UINT64_C(0), 367 UINT64_C(0), 368 UINT64_C(0), 369 UINT64_C(0), 370 UINT64_C(0), 371 UINT64_C(0), 372 UINT64_C(0), 373 UINT64_C(0), 374 UINT64_C(0), 375 UINT64_C(0), 376 UINT64_C(0), 377 UINT64_C(0), 378 UINT64_C(0), 379 UINT64_C(0), 380 UINT64_C(0), 381 UINT64_C(0), 382 UINT64_C(0), 383 UINT64_C(0), 384 UINT64_C(0), 385 UINT64_C(0), 386 UINT64_C(0), 387 UINT64_C(0), 388 UINT64_C(0), 389 UINT64_C(0), 390 UINT64_C(0), 391 UINT64_C(0), 392 UINT64_C(0), 393 UINT64_C(0), 394 UINT64_C(0), 395 UINT64_C(0), 396 UINT64_C(0), 397 UINT64_C(0), 398 UINT64_C(0), 399 UINT64_C(0), 400 UINT64_C(0), 401 UINT64_C(0), 402 UINT64_C(0), 403 UINT64_C(0), 404 UINT64_C(0), 405 UINT64_C(0), 406 UINT64_C(0), 407 UINT64_C(0), 408 UINT64_C(0), 409 UINT64_C(0), 410 UINT64_C(0), 411 UINT64_C(0), 412 UINT64_C(0), 413 UINT64_C(0), 414 UINT64_C(0), 415 UINT64_C(0), 416 UINT64_C(0), 417 UINT64_C(0), 418 UINT64_C(0), 419 UINT64_C(0), 420 UINT64_C(0), 421 UINT64_C(0), 422 UINT64_C(0), 423 UINT64_C(0), 424 UINT64_C(0), 425 UINT64_C(0), 426 UINT64_C(0), 427 UINT64_C(0), 428 UINT64_C(0), 429 UINT64_C(0), 430 UINT64_C(0), 431 UINT64_C(0), 432 UINT64_C(0), 433 UINT64_C(0), 434 UINT64_C(0), 435 UINT64_C(0), 436 UINT64_C(0), 437 UINT64_C(0), 438 UINT64_C(0), 439 UINT64_C(0), 440 UINT64_C(0), 441 UINT64_C(0), 442 UINT64_C(0), 443 UINT64_C(0), 444 UINT64_C(0), 445 UINT64_C(0), 446 UINT64_C(0), 447 UINT64_C(0), 448 UINT64_C(0), 449 UINT64_C(0), 450 UINT64_C(0), 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(0), 454 UINT64_C(0), 455 UINT64_C(0), 456 UINT64_C(0), 457 UINT64_C(0), 458 UINT64_C(0), 459 UINT64_C(0), 460 UINT64_C(0), 461 UINT64_C(0), 462 UINT64_C(0), 463 UINT64_C(0), 464 UINT64_C(0), 465 UINT64_C(0), 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(0), 469 UINT64_C(0), 470 UINT64_C(0), 471 UINT64_C(0), 472 UINT64_C(0), 473 UINT64_C(0), 474 UINT64_C(0), 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(0), 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(0), 484 UINT64_C(0), 485 UINT64_C(0), 486 UINT64_C(0), 487 UINT64_C(0), 488 UINT64_C(0), 489 UINT64_C(0), 490 UINT64_C(0), 491 UINT64_C(0), 492 UINT64_C(0), 493 UINT64_C(0), 494 UINT64_C(0), 495 UINT64_C(0), 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(0), 501 UINT64_C(0), 502 UINT64_C(0), 503 UINT64_C(0), 504 UINT64_C(0), 505 UINT64_C(0), 506 UINT64_C(0), 507 UINT64_C(0), 508 UINT64_C(0), 509 UINT64_C(0), 510 UINT64_C(0), 511 UINT64_C(0), 512 UINT64_C(0), 513 UINT64_C(0), 514 UINT64_C(0), 515 UINT64_C(0), 516 UINT64_C(0), 517 UINT64_C(0), 518 UINT64_C(0), 519 UINT64_C(0), 520 UINT64_C(0), 521 UINT64_C(0), 522 UINT64_C(0), 523 UINT64_C(0), 524 UINT64_C(0), 525 UINT64_C(0), 526 UINT64_C(0), 527 UINT64_C(0), 528 UINT64_C(0), 529 UINT64_C(0), 530 UINT64_C(0), 531 UINT64_C(0), 532 UINT64_C(0), 533 UINT64_C(0), 534 UINT64_C(0), 535 UINT64_C(0), 536 UINT64_C(0), 537 UINT64_C(0), 538 UINT64_C(0), 539 UINT64_C(0), 540 UINT64_C(0), 541 UINT64_C(0), 542 UINT64_C(0), 543 UINT64_C(0), 544 UINT64_C(0), 545 UINT64_C(0), 546 UINT64_C(0), 547 UINT64_C(0), 548 UINT64_C(0), 549 UINT64_C(0), 550 UINT64_C(0), 551 UINT64_C(0), 552 UINT64_C(0), 553 UINT64_C(0), 554 UINT64_C(0), 555 UINT64_C(0), 556 UINT64_C(0), 557 UINT64_C(0), 558 UINT64_C(0), 559 UINT64_C(0), 560 UINT64_C(0), 561 UINT64_C(0), 562 UINT64_C(0), 563 UINT64_C(0), 564 UINT64_C(0), 565 UINT64_C(0), 566 UINT64_C(0), 567 UINT64_C(0), 568 UINT64_C(0), 569 UINT64_C(0), 570 UINT64_C(0), 571 UINT64_C(0), 572 UINT64_C(0), 573 UINT64_C(0), 574 UINT64_C(0), 575 UINT64_C(0), 576 UINT64_C(0), 577 UINT64_C(0), 578 UINT64_C(0), 579 UINT64_C(0), 580 UINT64_C(0), 581 UINT64_C(0), 582 UINT64_C(0), 583 UINT64_C(0), 584 UINT64_C(0), 585 UINT64_C(0), 586 UINT64_C(0), 587 UINT64_C(0), 588 UINT64_C(0), 589 UINT64_C(0), 590 UINT64_C(0), 591 UINT64_C(0), 592 UINT64_C(0), 593 UINT64_C(0), 594 UINT64_C(0), 595 UINT64_C(0), 596 UINT64_C(0), 597 UINT64_C(0), 598 UINT64_C(0), 599 UINT64_C(0), 600 UINT64_C(0), 601 UINT64_C(0), 602 UINT64_C(0), 603 UINT64_C(0), 604 UINT64_C(0), 605 UINT64_C(0), 606 UINT64_C(0), 607 UINT64_C(0), 608 UINT64_C(0), 609 UINT64_C(0), 610 UINT64_C(0), 611 UINT64_C(0), 612 UINT64_C(0), 613 UINT64_C(0), 614 UINT64_C(0), 615 UINT64_C(44040192), // ADCri 616 UINT64_C(10485760), // ADCrr 617 UINT64_C(10485760), // ADCrsi 618 UINT64_C(10485776), // ADCrsr 619 UINT64_C(41943040), // ADDri 620 UINT64_C(8388608), // ADDrr 621 UINT64_C(8388608), // ADDrsi 622 UINT64_C(8388624), // ADDrsr 623 UINT64_C(34537472), // ADR 624 UINT64_C(4088398656), // AESD 625 UINT64_C(4088398592), // AESE 626 UINT64_C(4088398784), // AESIMC 627 UINT64_C(4088398720), // AESMC 628 UINT64_C(33554432), // ANDri 629 UINT64_C(0), // ANDrr 630 UINT64_C(0), // ANDrsi 631 UINT64_C(16), // ANDrsr 632 UINT64_C(130023455), // BFC 633 UINT64_C(130023440), // BFI 634 UINT64_C(62914560), // BICri 635 UINT64_C(29360128), // BICrr 636 UINT64_C(29360128), // BICrsi 637 UINT64_C(29360144), // BICrsr 638 UINT64_C(3776970864), // BKPT 639 UINT64_C(3942645760), // BL 640 UINT64_C(3778019120), // BLX 641 UINT64_C(19922736), // BLX_pred 642 UINT64_C(4194304000), // BLXi 643 UINT64_C(184549376), // BL_pred 644 UINT64_C(3778019088), // BX 645 UINT64_C(19922720), // BXJ 646 UINT64_C(19922718), // BX_RET 647 UINT64_C(19922704), // BX_pred 648 UINT64_C(167772160), // Bcc 649 UINT64_C(234881024), // CDP 650 UINT64_C(4261412864), // CDP2 651 UINT64_C(4118802463), // CLREX 652 UINT64_C(24055568), // CLZ 653 UINT64_C(57671680), // CMNri 654 UINT64_C(24117248), // CMNzrr 655 UINT64_C(24117248), // CMNzrsi 656 UINT64_C(24117264), // CMNzrsr 657 UINT64_C(55574528), // CMPri 658 UINT64_C(22020096), // CMPrr 659 UINT64_C(22020096), // CMPrsi 660 UINT64_C(22020112), // CMPrsr 661 UINT64_C(4043440128), // CPS1p 662 UINT64_C(4043309056), // CPS2p 663 UINT64_C(4043440128), // CPS3p 664 UINT64_C(3774873664), // CRC32B 665 UINT64_C(3774874176), // CRC32CB 666 UINT64_C(3776971328), // CRC32CH 667 UINT64_C(3779068480), // CRC32CW 668 UINT64_C(3776970816), // CRC32H 669 UINT64_C(3779067968), // CRC32W 670 UINT64_C(52490480), // DBG 671 UINT64_C(4118802512), // DMB 672 UINT64_C(4118802496), // DSB 673 UINT64_C(35651584), // EORri 674 UINT64_C(2097152), // EORrr 675 UINT64_C(2097152), // EORrsi 676 UINT64_C(2097168), // EORrsr 677 UINT64_C(23068782), // ERET 678 UINT64_C(246418176), // FCONSTD 679 UINT64_C(246417664), // FCONSTH 680 UINT64_C(246417920), // FCONSTS 681 UINT64_C(221252353), // FLDMXDB_UPD 682 UINT64_C(210766593), // FLDMXIA 683 UINT64_C(212863745), // FLDMXIA_UPD 684 UINT64_C(250739216), // FMSTAT 685 UINT64_C(220203777), // FSTMXDB_UPD 686 UINT64_C(209718017), // FSTMXIA 687 UINT64_C(211815169), // FSTMXIA_UPD 688 UINT64_C(52490240), // HINT 689 UINT64_C(3774873712), // HLT 690 UINT64_C(3779068016), // HVC 691 UINT64_C(4118802528), // ISB 692 UINT64_C(26217631), // LDA 693 UINT64_C(30411935), // LDAB 694 UINT64_C(26218143), // LDAEX 695 UINT64_C(30412447), // LDAEXB 696 UINT64_C(28315295), // LDAEXD 697 UINT64_C(32509599), // LDAEXH 698 UINT64_C(32509087), // LDAH 699 UINT64_C(4249878528), // LDC2L_OFFSET 700 UINT64_C(4241489920), // LDC2L_OPTION 701 UINT64_C(4235198464), // LDC2L_POST 702 UINT64_C(4251975680), // LDC2L_PRE 703 UINT64_C(4245684224), // LDC2_OFFSET 704 UINT64_C(4237295616), // LDC2_OPTION 705 UINT64_C(4231004160), // LDC2_POST 706 UINT64_C(4247781376), // LDC2_PRE 707 UINT64_C(223346688), // LDCL_OFFSET 708 UINT64_C(214958080), // LDCL_OPTION 709 UINT64_C(208666624), // LDCL_POST 710 UINT64_C(225443840), // LDCL_PRE 711 UINT64_C(219152384), // LDC_OFFSET 712 UINT64_C(210763776), // LDC_OPTION 713 UINT64_C(204472320), // LDC_POST 714 UINT64_C(221249536), // LDC_PRE 715 UINT64_C(135266304), // LDMDA 716 UINT64_C(137363456), // LDMDA_UPD 717 UINT64_C(152043520), // LDMDB 718 UINT64_C(154140672), // LDMDB_UPD 719 UINT64_C(143654912), // LDMIA 720 UINT64_C(145752064), // LDMIA_UPD 721 UINT64_C(160432128), // LDMIB 722 UINT64_C(162529280), // LDMIB_UPD 723 UINT64_C(74448896), // LDRBT_POST_IMM 724 UINT64_C(108003328), // LDRBT_POST_REG 725 UINT64_C(72351744), // LDRB_POST_IMM 726 UINT64_C(105906176), // LDRB_POST_REG 727 UINT64_C(91226112), // LDRB_PRE_IMM 728 UINT64_C(124780544), // LDRB_PRE_REG 729 UINT64_C(89128960), // LDRBi12 730 UINT64_C(122683392), // LDRBrs 731 UINT64_C(16777424), // LDRD 732 UINT64_C(208), // LDRD_POST 733 UINT64_C(18874576), // LDRD_PRE 734 UINT64_C(26218399), // LDREX 735 UINT64_C(30412703), // LDREXB 736 UINT64_C(28315551), // LDREXD 737 UINT64_C(32509855), // LDREXH 738 UINT64_C(17825968), // LDRH 739 UINT64_C(7340208), // LDRHTi 740 UINT64_C(3145904), // LDRHTr 741 UINT64_C(1048752), // LDRH_POST 742 UINT64_C(19923120), // LDRH_PRE 743 UINT64_C(17826000), // LDRSB 744 UINT64_C(7340240), // LDRSBTi 745 UINT64_C(3145936), // LDRSBTr 746 UINT64_C(1048784), // LDRSB_POST 747 UINT64_C(19923152), // LDRSB_PRE 748 UINT64_C(17826032), // LDRSH 749 UINT64_C(7340272), // LDRSHTi 750 UINT64_C(3145968), // LDRSHTr 751 UINT64_C(1048816), // LDRSH_POST 752 UINT64_C(19923184), // LDRSH_PRE 753 UINT64_C(70254592), // LDRT_POST_IMM 754 UINT64_C(103809024), // LDRT_POST_REG 755 UINT64_C(68157440), // LDR_POST_IMM 756 UINT64_C(101711872), // LDR_POST_REG 757 UINT64_C(87031808), // LDR_PRE_IMM 758 UINT64_C(120586240), // LDR_PRE_REG 759 UINT64_C(85917696), // LDRcp 760 UINT64_C(84934656), // LDRi12 761 UINT64_C(118489088), // LDRrs 762 UINT64_C(234881040), // MCR 763 UINT64_C(4261412880), // MCR2 764 UINT64_C(205520896), // MCRR 765 UINT64_C(4232052736), // MCRR2 766 UINT64_C(2097296), // MLA 767 UINT64_C(6291600), // MLS 768 UINT64_C(27324430), // MOVPCLR 769 UINT64_C(54525952), // MOVTi16 770 UINT64_C(60817408), // MOVi 771 UINT64_C(50331648), // MOVi16 772 UINT64_C(27262976), // MOVr 773 UINT64_C(27262976), // MOVr_TC 774 UINT64_C(27262976), // MOVsi 775 UINT64_C(27262992), // MOVsr 776 UINT64_C(235929616), // MRC 777 UINT64_C(4262461456), // MRC2 778 UINT64_C(206569472), // MRRC 779 UINT64_C(4233101312), // MRRC2 780 UINT64_C(17760256), // MRS 781 UINT64_C(16777728), // MRSbanked 782 UINT64_C(21954560), // MRSsys 783 UINT64_C(18935808), // MSR 784 UINT64_C(18936320), // MSRbanked 785 UINT64_C(52490240), // MSRi 786 UINT64_C(144), // MUL 787 UINT64_C(3931111727), // MVE_ASRLi 788 UINT64_C(3931111725), // MVE_ASRLr 789 UINT64_C(4027637761), // MVE_DLSTP_16 790 UINT64_C(4028686337), // MVE_DLSTP_32 791 UINT64_C(4029734913), // MVE_DLSTP_64 792 UINT64_C(4026589185), // MVE_DLSTP_8 793 UINT64_C(4027572225), // MVE_LCTP 794 UINT64_C(4028612609), // MVE_LETP 795 UINT64_C(3931111695), // MVE_LSLLi 796 UINT64_C(3931111693), // MVE_LSLLr 797 UINT64_C(3931111711), // MVE_LSRL 798 UINT64_C(3931115309), // MVE_SQRSHR 799 UINT64_C(3931177261), // MVE_SQRSHRL 800 UINT64_C(3931115327), // MVE_SQSHL 801 UINT64_C(3931177279), // MVE_SQSHLL 802 UINT64_C(3931115311), // MVE_SRSHR 803 UINT64_C(3931177263), // MVE_SRSHRL 804 UINT64_C(3931115277), // MVE_UQRSHL 805 UINT64_C(3931177229), // MVE_UQRSHLL 806 UINT64_C(3931115279), // MVE_UQSHL 807 UINT64_C(3931177231), // MVE_UQSHLL 808 UINT64_C(3931115295), // MVE_URSHR 809 UINT64_C(3931177247), // MVE_URSHRL 810 UINT64_C(4002418433), // MVE_VABAVs16 811 UINT64_C(4003467009), // MVE_VABAVs32 812 UINT64_C(4001369857), // MVE_VABAVs8 813 UINT64_C(4270853889), // MVE_VABAVu16 814 UINT64_C(4271902465), // MVE_VABAVu32 815 UINT64_C(4269805313), // MVE_VABAVu8 816 UINT64_C(4281339200), // MVE_VABDf16 817 UINT64_C(4280290624), // MVE_VABDf32 818 UINT64_C(4010805056), // MVE_VABDs16 819 UINT64_C(4011853632), // MVE_VABDs32 820 UINT64_C(4009756480), // MVE_VABDs8 821 UINT64_C(4279240512), // MVE_VABDu16 822 UINT64_C(4280289088), // MVE_VABDu32 823 UINT64_C(4278191936), // MVE_VABDu8 824 UINT64_C(4290053952), // MVE_VABSf16 825 UINT64_C(4290316096), // MVE_VABSf32 826 UINT64_C(4290052928), // MVE_VABSs16 827 UINT64_C(4290315072), // MVE_VABSs32 828 UINT64_C(4289790784), // MVE_VABSs8 829 UINT64_C(3996126976), // MVE_VADC 830 UINT64_C(3996131072), // MVE_VADCI 831 UINT64_C(4001959712), // MVE_VADDLVs32acc 832 UINT64_C(4001959680), // MVE_VADDLVs32no_acc 833 UINT64_C(4270395168), // MVE_VADDLVu32acc 834 UINT64_C(4270395136), // MVE_VADDLVu32no_acc 835 UINT64_C(4009037600), // MVE_VADDVs16acc 836 UINT64_C(4009037568), // MVE_VADDVs16no_acc 837 UINT64_C(4009299744), // MVE_VADDVs32acc 838 UINT64_C(4009299712), // MVE_VADDVs32no_acc 839 UINT64_C(4008775456), // MVE_VADDVs8acc 840 UINT64_C(4008775424), // MVE_VADDVs8no_acc 841 UINT64_C(4277473056), // MVE_VADDVu16acc 842 UINT64_C(4277473024), // MVE_VADDVu16no_acc 843 UINT64_C(4277735200), // MVE_VADDVu32acc 844 UINT64_C(4277735168), // MVE_VADDVu32no_acc 845 UINT64_C(4277210912), // MVE_VADDVu8acc 846 UINT64_C(4277210880), // MVE_VADDVu8no_acc 847 UINT64_C(4264562496), // MVE_VADD_qr_f16 848 UINT64_C(3996127040), // MVE_VADD_qr_f32 849 UINT64_C(3994095424), // MVE_VADD_qr_i16 850 UINT64_C(3995144000), // MVE_VADD_qr_i32 851 UINT64_C(3993046848), // MVE_VADD_qr_i8 852 UINT64_C(4010806592), // MVE_VADDf16 853 UINT64_C(4009758016), // MVE_VADDf32 854 UINT64_C(4010805312), // MVE_VADDi16 855 UINT64_C(4011853888), // MVE_VADDi32 856 UINT64_C(4009756736), // MVE_VADDi8 857 UINT64_C(4009754960), // MVE_VAND 858 UINT64_C(4010803536), // MVE_VBIC 859 UINT64_C(4018143600), // MVE_VBICIZ0v4i32 860 UINT64_C(4018145648), // MVE_VBICIZ0v8i16 861 UINT64_C(4018144624), // MVE_VBICIZ16v4i32 862 UINT64_C(4018145136), // MVE_VBICIZ24v4i32 863 UINT64_C(4018144112), // MVE_VBICIZ8v4i32 864 UINT64_C(4018146160), // MVE_VBICIZ8v8i16 865 UINT64_C(4262534752), // MVE_VBRSR16 866 UINT64_C(4263583328), // MVE_VBRSR32 867 UINT64_C(4261486176), // MVE_VBRSR8 868 UINT64_C(4236249152), // MVE_VCADDf16 869 UINT64_C(4237297728), // MVE_VCADDf32 870 UINT64_C(4262465280), // MVE_VCADDi16 871 UINT64_C(4263513856), // MVE_VCADDi32 872 UINT64_C(4261416704), // MVE_VCADDi8 873 UINT64_C(4289987648), // MVE_VCLSs16 874 UINT64_C(4290249792), // MVE_VCLSs32 875 UINT64_C(4289725504), // MVE_VCLSs8 876 UINT64_C(4289987776), // MVE_VCLZs16 877 UINT64_C(4290249920), // MVE_VCLZs32 878 UINT64_C(4289725632), // MVE_VCLZs8 879 UINT64_C(4229957696), // MVE_VCMLAf16 880 UINT64_C(4231006272), // MVE_VCMLAf32 881 UINT64_C(4264627968), // MVE_VCMPf16 882 UINT64_C(4264628032), // MVE_VCMPf16r 883 UINT64_C(3996192512), // MVE_VCMPf32 884 UINT64_C(3996192576), // MVE_VCMPf32r 885 UINT64_C(4262530816), // MVE_VCMPi16 886 UINT64_C(4262530880), // MVE_VCMPi16r 887 UINT64_C(4263579392), // MVE_VCMPi32 888 UINT64_C(4263579456), // MVE_VCMPi32r 889 UINT64_C(4261482240), // MVE_VCMPi8 890 UINT64_C(4261482304), // MVE_VCMPi8r 891 UINT64_C(4262534912), // MVE_VCMPs16 892 UINT64_C(4262534976), // MVE_VCMPs16r 893 UINT64_C(4263583488), // MVE_VCMPs32 894 UINT64_C(4263583552), // MVE_VCMPs32r 895 UINT64_C(4261486336), // MVE_VCMPs8 896 UINT64_C(4261486400), // MVE_VCMPs8r 897 UINT64_C(4262530817), // MVE_VCMPu16 898 UINT64_C(4262530912), // MVE_VCMPu16r 899 UINT64_C(4263579393), // MVE_VCMPu32 900 UINT64_C(4263579488), // MVE_VCMPu32r 901 UINT64_C(4261482241), // MVE_VCMPu8 902 UINT64_C(4261482336), // MVE_VCMPu8r 903 UINT64_C(3996126720), // MVE_VCMULf16 904 UINT64_C(4264562176), // MVE_VCMULf32 905 UINT64_C(4027639809), // MVE_VCTP16 906 UINT64_C(4028688385), // MVE_VCTP32 907 UINT64_C(4029736961), // MVE_VCTP64 908 UINT64_C(4026591233), // MVE_VCTP8 909 UINT64_C(3997109761), // MVE_VCVTf16f32bh 910 UINT64_C(3997113857), // MVE_VCVTf16f32th 911 UINT64_C(4021292112), // MVE_VCVTf16s16_fix 912 UINT64_C(4290184768), // MVE_VCVTf16s16n 913 UINT64_C(4289727568), // MVE_VCVTf16u16_fix 914 UINT64_C(4290184896), // MVE_VCVTf16u16n 915 UINT64_C(4265545217), // MVE_VCVTf32f16bh 916 UINT64_C(4265549313), // MVE_VCVTf32f16th 917 UINT64_C(4020244048), // MVE_VCVTf32s32_fix 918 UINT64_C(4290446912), // MVE_VCVTf32s32n 919 UINT64_C(4288679504), // MVE_VCVTf32u32_fix 920 UINT64_C(4290447040), // MVE_VCVTf32u32n 921 UINT64_C(4021292368), // MVE_VCVTs16f16_fix 922 UINT64_C(4290183232), // MVE_VCVTs16f16a 923 UINT64_C(4290184000), // MVE_VCVTs16f16m 924 UINT64_C(4290183488), // MVE_VCVTs16f16n 925 UINT64_C(4290183744), // MVE_VCVTs16f16p 926 UINT64_C(4290185024), // MVE_VCVTs16f16z 927 UINT64_C(4020244304), // MVE_VCVTs32f32_fix 928 UINT64_C(4290445376), // MVE_VCVTs32f32a 929 UINT64_C(4290446144), // MVE_VCVTs32f32m 930 UINT64_C(4290445632), // MVE_VCVTs32f32n 931 UINT64_C(4290445888), // MVE_VCVTs32f32p 932 UINT64_C(4290447168), // MVE_VCVTs32f32z 933 UINT64_C(4289727824), // MVE_VCVTu16f16_fix 934 UINT64_C(4290183360), // MVE_VCVTu16f16a 935 UINT64_C(4290184128), // MVE_VCVTu16f16m 936 UINT64_C(4290183616), // MVE_VCVTu16f16n 937 UINT64_C(4290183872), // MVE_VCVTu16f16p 938 UINT64_C(4290185152), // MVE_VCVTu16f16z 939 UINT64_C(4288679760), // MVE_VCVTu32f32_fix 940 UINT64_C(4290445504), // MVE_VCVTu32f32a 941 UINT64_C(4290446272), // MVE_VCVTu32f32m 942 UINT64_C(4290445760), // MVE_VCVTu32f32n 943 UINT64_C(4290446016), // MVE_VCVTu32f32p 944 UINT64_C(4290447296), // MVE_VCVTu32f32z 945 UINT64_C(3994099566), // MVE_VDDUPu16 946 UINT64_C(3995148142), // MVE_VDDUPu32 947 UINT64_C(3993050990), // MVE_VDDUPu8 948 UINT64_C(4003466032), // MVE_VDUP16 949 UINT64_C(4003466000), // MVE_VDUP32 950 UINT64_C(4007660304), // MVE_VDUP8 951 UINT64_C(3994099552), // MVE_VDWDUPu16 952 UINT64_C(3995148128), // MVE_VDWDUPu32 953 UINT64_C(3993050976), // MVE_VDWDUPu8 954 UINT64_C(4278190416), // MVE_VEOR 955 UINT64_C(4264631872), // MVE_VFMA_qr_Sf16 956 UINT64_C(3996196416), // MVE_VFMA_qr_Sf32 957 UINT64_C(4264627776), // MVE_VFMA_qr_f16 958 UINT64_C(3996192320), // MVE_VFMA_qr_f32 959 UINT64_C(4010806352), // MVE_VFMAf16 960 UINT64_C(4009757776), // MVE_VFMAf32 961 UINT64_C(4012903504), // MVE_VFMSf16 962 UINT64_C(4011854928), // MVE_VFMSf32 963 UINT64_C(3994029888), // MVE_VHADD_qr_s16 964 UINT64_C(3995078464), // MVE_VHADD_qr_s32 965 UINT64_C(3992981312), // MVE_VHADD_qr_s8 966 UINT64_C(4262465344), // MVE_VHADD_qr_u16 967 UINT64_C(4263513920), // MVE_VHADD_qr_u32 968 UINT64_C(4261416768), // MVE_VHADD_qr_u8 969 UINT64_C(4010803264), // MVE_VHADDs16 970 UINT64_C(4011851840), // MVE_VHADDs32 971 UINT64_C(4009754688), // MVE_VHADDs8 972 UINT64_C(4279238720), // MVE_VHADDu16 973 UINT64_C(4280287296), // MVE_VHADDu32 974 UINT64_C(4278190144), // MVE_VHADDu8 975 UINT64_C(3994029824), // MVE_VHCADDs16 976 UINT64_C(3995078400), // MVE_VHCADDs32 977 UINT64_C(3992981248), // MVE_VHCADDs8 978 UINT64_C(3994033984), // MVE_VHSUB_qr_s16 979 UINT64_C(3995082560), // MVE_VHSUB_qr_s32 980 UINT64_C(3992985408), // MVE_VHSUB_qr_s8 981 UINT64_C(4262469440), // MVE_VHSUB_qr_u16 982 UINT64_C(4263518016), // MVE_VHSUB_qr_u32 983 UINT64_C(4261420864), // MVE_VHSUB_qr_u8 984 UINT64_C(4010803776), // MVE_VHSUBs16 985 UINT64_C(4011852352), // MVE_VHSUBs32 986 UINT64_C(4009755200), // MVE_VHSUBs8 987 UINT64_C(4279239232), // MVE_VHSUBu16 988 UINT64_C(4280287808), // MVE_VHSUBu32 989 UINT64_C(4278190656), // MVE_VHSUBu8 990 UINT64_C(3994095470), // MVE_VIDUPu16 991 UINT64_C(3995144046), // MVE_VIDUPu32 992 UINT64_C(3993046894), // MVE_VIDUPu8 993 UINT64_C(3994095456), // MVE_VIWDUPu16 994 UINT64_C(3995144032), // MVE_VIWDUPu32 995 UINT64_C(3993046880), // MVE_VIWDUPu8 996 UINT64_C(4237303424), // MVE_VLD20_16 997 UINT64_C(4239400576), // MVE_VLD20_16_wb 998 UINT64_C(4237303552), // MVE_VLD20_32 999 UINT64_C(4239400704), // MVE_VLD20_32_wb 1000 UINT64_C(4237303296), // MVE_VLD20_8 1001 UINT64_C(4239400448), // MVE_VLD20_8_wb 1002 UINT64_C(4237303456), // MVE_VLD21_16 1003 UINT64_C(4239400608), // MVE_VLD21_16_wb 1004 UINT64_C(4237303584), // MVE_VLD21_32 1005 UINT64_C(4239400736), // MVE_VLD21_32_wb 1006 UINT64_C(4237303328), // MVE_VLD21_8 1007 UINT64_C(4239400480), // MVE_VLD21_8_wb 1008 UINT64_C(4237303425), // MVE_VLD40_16 1009 UINT64_C(4239400577), // MVE_VLD40_16_wb 1010 UINT64_C(4237303553), // MVE_VLD40_32 1011 UINT64_C(4239400705), // MVE_VLD40_32_wb 1012 UINT64_C(4237303297), // MVE_VLD40_8 1013 UINT64_C(4239400449), // MVE_VLD40_8_wb 1014 UINT64_C(4237303457), // MVE_VLD41_16 1015 UINT64_C(4239400609), // MVE_VLD41_16_wb 1016 UINT64_C(4237303585), // MVE_VLD41_32 1017 UINT64_C(4239400737), // MVE_VLD41_32_wb 1018 UINT64_C(4237303329), // MVE_VLD41_8 1019 UINT64_C(4239400481), // MVE_VLD41_8_wb 1020 UINT64_C(4237303489), // MVE_VLD42_16 1021 UINT64_C(4239400641), // MVE_VLD42_16_wb 1022 UINT64_C(4237303617), // MVE_VLD42_32 1023 UINT64_C(4239400769), // MVE_VLD42_32_wb 1024 UINT64_C(4237303361), // MVE_VLD42_8 1025 UINT64_C(4239400513), // MVE_VLD42_8_wb 1026 UINT64_C(4237303521), // MVE_VLD43_16 1027 UINT64_C(4239400673), // MVE_VLD43_16_wb 1028 UINT64_C(4237303649), // MVE_VLD43_32 1029 UINT64_C(4239400801), // MVE_VLD43_32_wb 1030 UINT64_C(4237303393), // MVE_VLD43_8 1031 UINT64_C(4239400545), // MVE_VLD43_8_wb 1032 UINT64_C(3977252480), // MVE_VLDRBS16 1033 UINT64_C(3962572416), // MVE_VLDRBS16_post 1034 UINT64_C(3979349632), // MVE_VLDRBS16_pre 1035 UINT64_C(3968863872), // MVE_VLDRBS16_rq 1036 UINT64_C(3977252608), // MVE_VLDRBS32 1037 UINT64_C(3962572544), // MVE_VLDRBS32_post 1038 UINT64_C(3979349760), // MVE_VLDRBS32_pre 1039 UINT64_C(3968864000), // MVE_VLDRBS32_rq 1040 UINT64_C(4245687936), // MVE_VLDRBU16 1041 UINT64_C(4231007872), // MVE_VLDRBU16_post 1042 UINT64_C(4247785088), // MVE_VLDRBU16_pre 1043 UINT64_C(4237299328), // MVE_VLDRBU16_rq 1044 UINT64_C(4245688064), // MVE_VLDRBU32 1045 UINT64_C(4231008000), // MVE_VLDRBU32_post 1046 UINT64_C(4247785216), // MVE_VLDRBU32_pre 1047 UINT64_C(4237299456), // MVE_VLDRBU32_rq 1048 UINT64_C(3977256448), // MVE_VLDRBU8 1049 UINT64_C(3962576384), // MVE_VLDRBU8_post 1050 UINT64_C(3979353600), // MVE_VLDRBU8_pre 1051 UINT64_C(4237299200), // MVE_VLDRBU8_rq 1052 UINT64_C(4245692160), // MVE_VLDRDU64_qi 1053 UINT64_C(4247789312), // MVE_VLDRDU64_qi_pre 1054 UINT64_C(4237299665), // MVE_VLDRDU64_rq 1055 UINT64_C(4237299664), // MVE_VLDRDU64_rq_u 1056 UINT64_C(3977776896), // MVE_VLDRHS32 1057 UINT64_C(3963096832), // MVE_VLDRHS32_post 1058 UINT64_C(3979874048), // MVE_VLDRHS32_pre 1059 UINT64_C(3968864017), // MVE_VLDRHS32_rq 1060 UINT64_C(3968864016), // MVE_VLDRHS32_rq_u 1061 UINT64_C(3977256576), // MVE_VLDRHU16 1062 UINT64_C(3962576512), // MVE_VLDRHU16_post 1063 UINT64_C(3979353728), // MVE_VLDRHU16_pre 1064 UINT64_C(4237299345), // MVE_VLDRHU16_rq 1065 UINT64_C(4237299344), // MVE_VLDRHU16_rq_u 1066 UINT64_C(4246212352), // MVE_VLDRHU32 1067 UINT64_C(4231532288), // MVE_VLDRHU32_post 1068 UINT64_C(4248309504), // MVE_VLDRHU32_pre 1069 UINT64_C(4237299473), // MVE_VLDRHU32_rq 1070 UINT64_C(4237299472), // MVE_VLDRHU32_rq_u 1071 UINT64_C(3977256704), // MVE_VLDRWU32 1072 UINT64_C(3962576640), // MVE_VLDRWU32_post 1073 UINT64_C(3979353856), // MVE_VLDRWU32_pre 1074 UINT64_C(4245691904), // MVE_VLDRWU32_qi 1075 UINT64_C(4247789056), // MVE_VLDRWU32_qi_pre 1076 UINT64_C(4237299521), // MVE_VLDRWU32_rq 1077 UINT64_C(4237299520), // MVE_VLDRWU32_rq_u 1078 UINT64_C(4007923456), // MVE_VMAXAVs16 1079 UINT64_C(4008185600), // MVE_VMAXAVs32 1080 UINT64_C(4007661312), // MVE_VMAXAVs8 1081 UINT64_C(3996585601), // MVE_VMAXAs16 1082 UINT64_C(3996847745), // MVE_VMAXAs32 1083 UINT64_C(3996323457), // MVE_VMAXAs8 1084 UINT64_C(4276883200), // MVE_VMAXNMAVf16 1085 UINT64_C(4008447744), // MVE_VMAXNMAVf32 1086 UINT64_C(4265545345), // MVE_VMAXNMAf16 1087 UINT64_C(3997109889), // MVE_VMAXNMAf32 1088 UINT64_C(4277014272), // MVE_VMAXNMVf16 1089 UINT64_C(4008578816), // MVE_VMAXNMVf32 1090 UINT64_C(4279242576), // MVE_VMAXNMf16 1091 UINT64_C(4278194000), // MVE_VMAXNMf32 1092 UINT64_C(4008054528), // MVE_VMAXVs16 1093 UINT64_C(4008316672), // MVE_VMAXVs32 1094 UINT64_C(4007792384), // MVE_VMAXVs8 1095 UINT64_C(4276489984), // MVE_VMAXVu16 1096 UINT64_C(4276752128), // MVE_VMAXVu32 1097 UINT64_C(4276227840), // MVE_VMAXVu8 1098 UINT64_C(4010804800), // MVE_VMAXs16 1099 UINT64_C(4011853376), // MVE_VMAXs32 1100 UINT64_C(4009756224), // MVE_VMAXs8 1101 UINT64_C(4279240256), // MVE_VMAXu16 1102 UINT64_C(4280288832), // MVE_VMAXu32 1103 UINT64_C(4278191680), // MVE_VMAXu8 1104 UINT64_C(4007923584), // MVE_VMINAVs16 1105 UINT64_C(4008185728), // MVE_VMINAVs32 1106 UINT64_C(4007661440), // MVE_VMINAVs8 1107 UINT64_C(3996589697), // MVE_VMINAs16 1108 UINT64_C(3996851841), // MVE_VMINAs32 1109 UINT64_C(3996327553), // MVE_VMINAs8 1110 UINT64_C(4276883328), // MVE_VMINNMAVf16 1111 UINT64_C(4008447872), // MVE_VMINNMAVf32 1112 UINT64_C(4265549441), // MVE_VMINNMAf16 1113 UINT64_C(3997113985), // MVE_VMINNMAf32 1114 UINT64_C(4277014400), // MVE_VMINNMVf16 1115 UINT64_C(4008578944), // MVE_VMINNMVf32 1116 UINT64_C(4281339728), // MVE_VMINNMf16 1117 UINT64_C(4280291152), // MVE_VMINNMf32 1118 UINT64_C(4008054656), // MVE_VMINVs16 1119 UINT64_C(4008316800), // MVE_VMINVs32 1120 UINT64_C(4007792512), // MVE_VMINVs8 1121 UINT64_C(4276490112), // MVE_VMINVu16 1122 UINT64_C(4276752256), // MVE_VMINVu32 1123 UINT64_C(4276227968), // MVE_VMINVu8 1124 UINT64_C(4010804816), // MVE_VMINs16 1125 UINT64_C(4011853392), // MVE_VMINs32 1126 UINT64_C(4009756240), // MVE_VMINs8 1127 UINT64_C(4279240272), // MVE_VMINu16 1128 UINT64_C(4280288848), // MVE_VMINu32 1129 UINT64_C(4278191696), // MVE_VMINu8 1130 UINT64_C(4008709664), // MVE_VMLADAVas16 1131 UINT64_C(4008775200), // MVE_VMLADAVas32 1132 UINT64_C(4008709920), // MVE_VMLADAVas8 1133 UINT64_C(4277145120), // MVE_VMLADAVau16 1134 UINT64_C(4277210656), // MVE_VMLADAVau32 1135 UINT64_C(4277145376), // MVE_VMLADAVau8 1136 UINT64_C(4008713760), // MVE_VMLADAVaxs16 1137 UINT64_C(4008779296), // MVE_VMLADAVaxs32 1138 UINT64_C(4008714016), // MVE_VMLADAVaxs8 1139 UINT64_C(4008709632), // MVE_VMLADAVs16 1140 UINT64_C(4008775168), // MVE_VMLADAVs32 1141 UINT64_C(4008709888), // MVE_VMLADAVs8 1142 UINT64_C(4277145088), // MVE_VMLADAVu16 1143 UINT64_C(4277210624), // MVE_VMLADAVu32 1144 UINT64_C(4277145344), // MVE_VMLADAVu8 1145 UINT64_C(4008713728), // MVE_VMLADAVxs16 1146 UINT64_C(4008779264), // MVE_VMLADAVxs32 1147 UINT64_C(4008713984), // MVE_VMLADAVxs8 1148 UINT64_C(4001369632), // MVE_VMLALDAVas16 1149 UINT64_C(4001435168), // MVE_VMLALDAVas32 1150 UINT64_C(4269805088), // MVE_VMLALDAVau16 1151 UINT64_C(4269870624), // MVE_VMLALDAVau32 1152 UINT64_C(4001373728), // MVE_VMLALDAVaxs16 1153 UINT64_C(4001439264), // MVE_VMLALDAVaxs32 1154 UINT64_C(4001369600), // MVE_VMLALDAVs16 1155 UINT64_C(4001435136), // MVE_VMLALDAVs32 1156 UINT64_C(4269805056), // MVE_VMLALDAVu16 1157 UINT64_C(4269870592), // MVE_VMLALDAVu32 1158 UINT64_C(4001373696), // MVE_VMLALDAVxs16 1159 UINT64_C(4001439232), // MVE_VMLALDAVxs32 1160 UINT64_C(3994099264), // MVE_VMLAS_qr_s16 1161 UINT64_C(3995147840), // MVE_VMLAS_qr_s32 1162 UINT64_C(3993050688), // MVE_VMLAS_qr_s8 1163 UINT64_C(4262534720), // MVE_VMLAS_qr_u16 1164 UINT64_C(4263583296), // MVE_VMLAS_qr_u32 1165 UINT64_C(4261486144), // MVE_VMLAS_qr_u8 1166 UINT64_C(3994095168), // MVE_VMLA_qr_s16 1167 UINT64_C(3995143744), // MVE_VMLA_qr_s32 1168 UINT64_C(3993046592), // MVE_VMLA_qr_s8 1169 UINT64_C(4262530624), // MVE_VMLA_qr_u16 1170 UINT64_C(4263579200), // MVE_VMLA_qr_u32 1171 UINT64_C(4261482048), // MVE_VMLA_qr_u8 1172 UINT64_C(4008709665), // MVE_VMLSDAVas16 1173 UINT64_C(4008775201), // MVE_VMLSDAVas32 1174 UINT64_C(4277145121), // MVE_VMLSDAVas8 1175 UINT64_C(4008713761), // MVE_VMLSDAVaxs16 1176 UINT64_C(4008779297), // MVE_VMLSDAVaxs32 1177 UINT64_C(4277149217), // MVE_VMLSDAVaxs8 1178 UINT64_C(4008709633), // MVE_VMLSDAVs16 1179 UINT64_C(4008775169), // MVE_VMLSDAVs32 1180 UINT64_C(4277145089), // MVE_VMLSDAVs8 1181 UINT64_C(4008713729), // MVE_VMLSDAVxs16 1182 UINT64_C(4008779265), // MVE_VMLSDAVxs32 1183 UINT64_C(4277149185), // MVE_VMLSDAVxs8 1184 UINT64_C(4001369633), // MVE_VMLSLDAVas16 1185 UINT64_C(4001435169), // MVE_VMLSLDAVas32 1186 UINT64_C(4001373729), // MVE_VMLSLDAVaxs16 1187 UINT64_C(4001439265), // MVE_VMLSLDAVaxs32 1188 UINT64_C(4001369601), // MVE_VMLSLDAVs16 1189 UINT64_C(4001435137), // MVE_VMLSLDAVs32 1190 UINT64_C(4001373697), // MVE_VMLSLDAVxs16 1191 UINT64_C(4001439233), // MVE_VMLSLDAVxs32 1192 UINT64_C(4004515648), // MVE_VMOVLs16bh 1193 UINT64_C(4004519744), // MVE_VMOVLs16th 1194 UINT64_C(4003991360), // MVE_VMOVLs8bh 1195 UINT64_C(4003995456), // MVE_VMOVLs8th 1196 UINT64_C(4272951104), // MVE_VMOVLu16bh 1197 UINT64_C(4272955200), // MVE_VMOVLu16th 1198 UINT64_C(4272426816), // MVE_VMOVLu8bh 1199 UINT64_C(4272430912), // MVE_VMOVLu8th 1200 UINT64_C(4264627841), // MVE_VMOVNi16bh 1201 UINT64_C(4264631937), // MVE_VMOVNi16th 1202 UINT64_C(4264889985), // MVE_VMOVNi32bh 1203 UINT64_C(4264894081), // MVE_VMOVNi32th 1204 UINT64_C(3994028816), // MVE_VMOV_from_lane_32 1205 UINT64_C(3994028848), // MVE_VMOV_from_lane_s16 1206 UINT64_C(3998223120), // MVE_VMOV_from_lane_s8 1207 UINT64_C(4002417456), // MVE_VMOV_from_lane_u16 1208 UINT64_C(4006611728), // MVE_VMOV_from_lane_u8 1209 UINT64_C(3960475392), // MVE_VMOV_q_rr 1210 UINT64_C(3959426816), // MVE_VMOV_rr_q 1211 UINT64_C(3992980272), // MVE_VMOV_to_lane_16 1212 UINT64_C(3992980240), // MVE_VMOV_to_lane_32 1213 UINT64_C(3997174544), // MVE_VMOV_to_lane_8 1214 UINT64_C(4018147152), // MVE_VMOVimmf32 1215 UINT64_C(4018145360), // MVE_VMOVimmi16 1216 UINT64_C(4018143312), // MVE_VMOVimmi32 1217 UINT64_C(4018146928), // MVE_VMOVimmi64 1218 UINT64_C(4018146896), // MVE_VMOVimmi8 1219 UINT64_C(3994095105), // MVE_VMULHs16 1220 UINT64_C(3995143681), // MVE_VMULHs32 1221 UINT64_C(3993046529), // MVE_VMULHs8 1222 UINT64_C(4262530561), // MVE_VMULHu16 1223 UINT64_C(4263579137), // MVE_VMULHu32 1224 UINT64_C(4261481985), // MVE_VMULHu8 1225 UINT64_C(4264627712), // MVE_VMULLBp16 1226 UINT64_C(3996192256), // MVE_VMULLBp8 1227 UINT64_C(3994095104), // MVE_VMULLBs16 1228 UINT64_C(3995143680), // MVE_VMULLBs32 1229 UINT64_C(3993046528), // MVE_VMULLBs8 1230 UINT64_C(4262530560), // MVE_VMULLBu16 1231 UINT64_C(4263579136), // MVE_VMULLBu32 1232 UINT64_C(4261481984), // MVE_VMULLBu8 1233 UINT64_C(4264631808), // MVE_VMULLTp16 1234 UINT64_C(3996196352), // MVE_VMULLTp8 1235 UINT64_C(3994099200), // MVE_VMULLTs16 1236 UINT64_C(3995147776), // MVE_VMULLTs32 1237 UINT64_C(3993050624), // MVE_VMULLTs8 1238 UINT64_C(4262534656), // MVE_VMULLTu16 1239 UINT64_C(4263583232), // MVE_VMULLTu32 1240 UINT64_C(4261486080), // MVE_VMULLTu8 1241 UINT64_C(4264627808), // MVE_VMUL_qr_f16 1242 UINT64_C(3996192352), // MVE_VMUL_qr_f32 1243 UINT64_C(3994099296), // MVE_VMUL_qr_i16 1244 UINT64_C(3995147872), // MVE_VMUL_qr_i32 1245 UINT64_C(3993050720), // MVE_VMUL_qr_i8 1246 UINT64_C(4279242064), // MVE_VMULf16 1247 UINT64_C(4278193488), // MVE_VMULf32 1248 UINT64_C(4010805584), // MVE_VMULi16 1249 UINT64_C(4011854160), // MVE_VMULi32 1250 UINT64_C(4009757008), // MVE_VMULi8 1251 UINT64_C(4289725888), // MVE_VMVN 1252 UINT64_C(4018145392), // MVE_VMVNimmi16 1253 UINT64_C(4018143344), // MVE_VMVNimmi32 1254 UINT64_C(4290054080), // MVE_VNEGf16 1255 UINT64_C(4290316224), // MVE_VNEGf32 1256 UINT64_C(4290053056), // MVE_VNEGs16 1257 UINT64_C(4290315200), // MVE_VNEGs32 1258 UINT64_C(4289790912), // MVE_VNEGs8 1259 UINT64_C(4012900688), // MVE_VORN 1260 UINT64_C(4011852112), // MVE_VORR 1261 UINT64_C(4018143568), // MVE_VORRIZ0v4i32 1262 UINT64_C(4018145616), // MVE_VORRIZ0v8i16 1263 UINT64_C(4018144592), // MVE_VORRIZ16v4i32 1264 UINT64_C(4018145104), // MVE_VORRIZ24v4i32 1265 UINT64_C(4018144080), // MVE_VORRIZ8v4i32 1266 UINT64_C(4018146128), // MVE_VORRIZ8v8i16 1267 UINT64_C(4264628045), // MVE_VPNOT 1268 UINT64_C(4264627969), // MVE_VPSEL 1269 UINT64_C(4264628045), // MVE_VPST 1270 UINT64_C(4261482240), // MVE_VPTv16i8 1271 UINT64_C(4261482304), // MVE_VPTv16i8r 1272 UINT64_C(4261486336), // MVE_VPTv16s8 1273 UINT64_C(4261486400), // MVE_VPTv16s8r 1274 UINT64_C(4261482241), // MVE_VPTv16u8 1275 UINT64_C(4261482336), // MVE_VPTv16u8r 1276 UINT64_C(3996192512), // MVE_VPTv4f32 1277 UINT64_C(3996192576), // MVE_VPTv4f32r 1278 UINT64_C(4263579392), // MVE_VPTv4i32 1279 UINT64_C(4263579456), // MVE_VPTv4i32r 1280 UINT64_C(4263583488), // MVE_VPTv4s32 1281 UINT64_C(4263583552), // MVE_VPTv4s32r 1282 UINT64_C(4263579393), // MVE_VPTv4u32 1283 UINT64_C(4263579488), // MVE_VPTv4u32r 1284 UINT64_C(4264627968), // MVE_VPTv8f16 1285 UINT64_C(4264628032), // MVE_VPTv8f16r 1286 UINT64_C(4262530816), // MVE_VPTv8i16 1287 UINT64_C(4262530880), // MVE_VPTv8i16r 1288 UINT64_C(4262534912), // MVE_VPTv8s16 1289 UINT64_C(4262534976), // MVE_VPTv8s16r 1290 UINT64_C(4262530817), // MVE_VPTv8u16 1291 UINT64_C(4262530912), // MVE_VPTv8u16r 1292 UINT64_C(4289988416), // MVE_VQABSs16 1293 UINT64_C(4290250560), // MVE_VQABSs32 1294 UINT64_C(4289726272), // MVE_VQABSs8 1295 UINT64_C(3994029920), // MVE_VQADD_qr_s16 1296 UINT64_C(3995078496), // MVE_VQADD_qr_s32 1297 UINT64_C(3992981344), // MVE_VQADD_qr_s8 1298 UINT64_C(4262465376), // MVE_VQADD_qr_u16 1299 UINT64_C(4263513952), // MVE_VQADD_qr_u32 1300 UINT64_C(4261416800), // MVE_VQADD_qr_u8 1301 UINT64_C(4010803280), // MVE_VQADDs16 1302 UINT64_C(4011851856), // MVE_VQADDs32 1303 UINT64_C(4009754704), // MVE_VQADDs8 1304 UINT64_C(4279238736), // MVE_VQADDu16 1305 UINT64_C(4280287312), // MVE_VQADDu32 1306 UINT64_C(4278190160), // MVE_VQADDu8 1307 UINT64_C(3994033664), // MVE_VQDMLADHXs16 1308 UINT64_C(3995082240), // MVE_VQDMLADHXs32 1309 UINT64_C(3992985088), // MVE_VQDMLADHXs8 1310 UINT64_C(3994029568), // MVE_VQDMLADHs16 1311 UINT64_C(3995078144), // MVE_VQDMLADHs32 1312 UINT64_C(3992980992), // MVE_VQDMLADHs8 1313 UINT64_C(3994029664), // MVE_VQDMLAH_qrs16 1314 UINT64_C(3995078240), // MVE_VQDMLAH_qrs32 1315 UINT64_C(3992981088), // MVE_VQDMLAH_qrs8 1316 UINT64_C(3994033760), // MVE_VQDMLASH_qrs16 1317 UINT64_C(3995082336), // MVE_VQDMLASH_qrs32 1318 UINT64_C(3992985184), // MVE_VQDMLASH_qrs8 1319 UINT64_C(4262469120), // MVE_VQDMLSDHXs16 1320 UINT64_C(4263517696), // MVE_VQDMLSDHXs32 1321 UINT64_C(4261420544), // MVE_VQDMLSDHXs8 1322 UINT64_C(4262465024), // MVE_VQDMLSDHs16 1323 UINT64_C(4263513600), // MVE_VQDMLSDHs32 1324 UINT64_C(4261416448), // MVE_VQDMLSDHs8 1325 UINT64_C(3994095200), // MVE_VQDMULH_qr_s16 1326 UINT64_C(3995143776), // MVE_VQDMULH_qr_s32 1327 UINT64_C(3993046624), // MVE_VQDMULH_qr_s8 1328 UINT64_C(4010806080), // MVE_VQDMULHi16 1329 UINT64_C(4011854656), // MVE_VQDMULHi32 1330 UINT64_C(4009757504), // MVE_VQDMULHi8 1331 UINT64_C(3996127072), // MVE_VQDMULL_qr_s16bh 1332 UINT64_C(3996131168), // MVE_VQDMULL_qr_s16th 1333 UINT64_C(4264562528), // MVE_VQDMULL_qr_s32bh 1334 UINT64_C(4264566624), // MVE_VQDMULL_qr_s32th 1335 UINT64_C(3996126977), // MVE_VQDMULLs16bh 1336 UINT64_C(3996131073), // MVE_VQDMULLs16th 1337 UINT64_C(4264562433), // MVE_VQDMULLs32bh 1338 UINT64_C(4264566529), // MVE_VQDMULLs32th 1339 UINT64_C(3996323329), // MVE_VQMOVNs16bh 1340 UINT64_C(3996327425), // MVE_VQMOVNs16th 1341 UINT64_C(3996585473), // MVE_VQMOVNs32bh 1342 UINT64_C(3996589569), // MVE_VQMOVNs32th 1343 UINT64_C(4264758785), // MVE_VQMOVNu16bh 1344 UINT64_C(4264762881), // MVE_VQMOVNu16th 1345 UINT64_C(4265020929), // MVE_VQMOVNu32bh 1346 UINT64_C(4265025025), // MVE_VQMOVNu32th 1347 UINT64_C(3996192385), // MVE_VQMOVUNs16bh 1348 UINT64_C(3996196481), // MVE_VQMOVUNs16th 1349 UINT64_C(3996454529), // MVE_VQMOVUNs32bh 1350 UINT64_C(3996458625), // MVE_VQMOVUNs32th 1351 UINT64_C(4289988544), // MVE_VQNEGs16 1352 UINT64_C(4290250688), // MVE_VQNEGs32 1353 UINT64_C(4289726400), // MVE_VQNEGs8 1354 UINT64_C(3994033665), // MVE_VQRDMLADHXs16 1355 UINT64_C(3995082241), // MVE_VQRDMLADHXs32 1356 UINT64_C(3992985089), // MVE_VQRDMLADHXs8 1357 UINT64_C(3994029569), // MVE_VQRDMLADHs16 1358 UINT64_C(3995078145), // MVE_VQRDMLADHs32 1359 UINT64_C(3992980993), // MVE_VQRDMLADHs8 1360 UINT64_C(3994029632), // MVE_VQRDMLAH_qrs16 1361 UINT64_C(3995078208), // MVE_VQRDMLAH_qrs32 1362 UINT64_C(3992981056), // MVE_VQRDMLAH_qrs8 1363 UINT64_C(3994033728), // MVE_VQRDMLASH_qrs16 1364 UINT64_C(3995082304), // MVE_VQRDMLASH_qrs32 1365 UINT64_C(3992985152), // MVE_VQRDMLASH_qrs8 1366 UINT64_C(4262469121), // MVE_VQRDMLSDHXs16 1367 UINT64_C(4263517697), // MVE_VQRDMLSDHXs32 1368 UINT64_C(4261420545), // MVE_VQRDMLSDHXs8 1369 UINT64_C(4262465025), // MVE_VQRDMLSDHs16 1370 UINT64_C(4263513601), // MVE_VQRDMLSDHs32 1371 UINT64_C(4261416449), // MVE_VQRDMLSDHs8 1372 UINT64_C(4262530656), // MVE_VQRDMULH_qr_s16 1373 UINT64_C(4263579232), // MVE_VQRDMULH_qr_s32 1374 UINT64_C(4261482080), // MVE_VQRDMULH_qr_s8 1375 UINT64_C(4279241536), // MVE_VQRDMULHi16 1376 UINT64_C(4280290112), // MVE_VQRDMULHi32 1377 UINT64_C(4278192960), // MVE_VQRDMULHi8 1378 UINT64_C(4010804560), // MVE_VQRSHL_by_vecs16 1379 UINT64_C(4011853136), // MVE_VQRSHL_by_vecs32 1380 UINT64_C(4009755984), // MVE_VQRSHL_by_vecs8 1381 UINT64_C(4279240016), // MVE_VQRSHL_by_vecu16 1382 UINT64_C(4280288592), // MVE_VQRSHL_by_vecu32 1383 UINT64_C(4278191440), // MVE_VQRSHL_by_vecu8 1384 UINT64_C(3996589792), // MVE_VQRSHL_qrs16 1385 UINT64_C(3996851936), // MVE_VQRSHL_qrs32 1386 UINT64_C(3996327648), // MVE_VQRSHL_qrs8 1387 UINT64_C(4265025248), // MVE_VQRSHL_qru16 1388 UINT64_C(4265287392), // MVE_VQRSHL_qru32 1389 UINT64_C(4264763104), // MVE_VQRSHL_qru8 1390 UINT64_C(4001894209), // MVE_VQRSHRNbhs16 1391 UINT64_C(4002418497), // MVE_VQRSHRNbhs32 1392 UINT64_C(4270329665), // MVE_VQRSHRNbhu16 1393 UINT64_C(4270853953), // MVE_VQRSHRNbhu32 1394 UINT64_C(4001898305), // MVE_VQRSHRNths16 1395 UINT64_C(4002422593), // MVE_VQRSHRNths32 1396 UINT64_C(4270333761), // MVE_VQRSHRNthu16 1397 UINT64_C(4270858049), // MVE_VQRSHRNthu32 1398 UINT64_C(4270329792), // MVE_VQRSHRUNs16bh 1399 UINT64_C(4270333888), // MVE_VQRSHRUNs16th 1400 UINT64_C(4270854080), // MVE_VQRSHRUNs32bh 1401 UINT64_C(4270858176), // MVE_VQRSHRUNs32th 1402 UINT64_C(4287628880), // MVE_VQSHLU_imms16 1403 UINT64_C(4288677456), // MVE_VQSHLU_imms32 1404 UINT64_C(4287104592), // MVE_VQSHLU_imms8 1405 UINT64_C(4010804304), // MVE_VQSHL_by_vecs16 1406 UINT64_C(4011852880), // MVE_VQSHL_by_vecs32 1407 UINT64_C(4009755728), // MVE_VQSHL_by_vecs8 1408 UINT64_C(4279239760), // MVE_VQSHL_by_vecu16 1409 UINT64_C(4280288336), // MVE_VQSHL_by_vecu32 1410 UINT64_C(4278191184), // MVE_VQSHL_by_vecu8 1411 UINT64_C(3996458720), // MVE_VQSHL_qrs16 1412 UINT64_C(3996720864), // MVE_VQSHL_qrs32 1413 UINT64_C(3996196576), // MVE_VQSHL_qrs8 1414 UINT64_C(4264894176), // MVE_VQSHL_qru16 1415 UINT64_C(4265156320), // MVE_VQSHL_qru32 1416 UINT64_C(4264632032), // MVE_VQSHL_qru8 1417 UINT64_C(4019193680), // MVE_VQSHLimms16 1418 UINT64_C(4020242256), // MVE_VQSHLimms32 1419 UINT64_C(4018669392), // MVE_VQSHLimms8 1420 UINT64_C(4287629136), // MVE_VQSHLimmu16 1421 UINT64_C(4288677712), // MVE_VQSHLimmu32 1422 UINT64_C(4287104848), // MVE_VQSHLimmu8 1423 UINT64_C(4001894208), // MVE_VQSHRNbhs16 1424 UINT64_C(4002418496), // MVE_VQSHRNbhs32 1425 UINT64_C(4270329664), // MVE_VQSHRNbhu16 1426 UINT64_C(4270853952), // MVE_VQSHRNbhu32 1427 UINT64_C(4001898304), // MVE_VQSHRNths16 1428 UINT64_C(4002422592), // MVE_VQSHRNths32 1429 UINT64_C(4270333760), // MVE_VQSHRNthu16 1430 UINT64_C(4270858048), // MVE_VQSHRNthu32 1431 UINT64_C(4001894336), // MVE_VQSHRUNs16bh 1432 UINT64_C(4001898432), // MVE_VQSHRUNs16th 1433 UINT64_C(4002418624), // MVE_VQSHRUNs32bh 1434 UINT64_C(4002422720), // MVE_VQSHRUNs32th 1435 UINT64_C(3994034016), // MVE_VQSUB_qr_s16 1436 UINT64_C(3995082592), // MVE_VQSUB_qr_s32 1437 UINT64_C(3992985440), // MVE_VQSUB_qr_s8 1438 UINT64_C(4262469472), // MVE_VQSUB_qr_u16 1439 UINT64_C(4263518048), // MVE_VQSUB_qr_u32 1440 UINT64_C(4261420896), // MVE_VQSUB_qr_u8 1441 UINT64_C(4010803792), // MVE_VQSUBs16 1442 UINT64_C(4011852368), // MVE_VQSUBs32 1443 UINT64_C(4009755216), // MVE_VQSUBs8 1444 UINT64_C(4279239248), // MVE_VQSUBu16 1445 UINT64_C(4280287824), // MVE_VQSUBu32 1446 UINT64_C(4278190672), // MVE_VQSUBu8 1447 UINT64_C(4289724736), // MVE_VREV16_8 1448 UINT64_C(4289986752), // MVE_VREV32_16 1449 UINT64_C(4289724608), // MVE_VREV32_8 1450 UINT64_C(4289986624), // MVE_VREV64_16 1451 UINT64_C(4290248768), // MVE_VREV64_32 1452 UINT64_C(4289724480), // MVE_VREV64_8 1453 UINT64_C(4010803520), // MVE_VRHADDs16 1454 UINT64_C(4011852096), // MVE_VRHADDs32 1455 UINT64_C(4009754944), // MVE_VRHADDs8 1456 UINT64_C(4279238976), // MVE_VRHADDu16 1457 UINT64_C(4280287552), // MVE_VRHADDu32 1458 UINT64_C(4278190400), // MVE_VRHADDu8 1459 UINT64_C(4290118976), // MVE_VRINTf16A 1460 UINT64_C(4290119360), // MVE_VRINTf16M 1461 UINT64_C(4290118720), // MVE_VRINTf16N 1462 UINT64_C(4290119616), // MVE_VRINTf16P 1463 UINT64_C(4290118848), // MVE_VRINTf16X 1464 UINT64_C(4290119104), // MVE_VRINTf16Z 1465 UINT64_C(4290381120), // MVE_VRINTf32A 1466 UINT64_C(4290381504), // MVE_VRINTf32M 1467 UINT64_C(4290380864), // MVE_VRINTf32N 1468 UINT64_C(4290381760), // MVE_VRINTf32P 1469 UINT64_C(4290380992), // MVE_VRINTf32X 1470 UINT64_C(4290381248), // MVE_VRINTf32Z 1471 UINT64_C(4001369888), // MVE_VRMLALDAVHas32 1472 UINT64_C(4269805344), // MVE_VRMLALDAVHau32 1473 UINT64_C(4001373984), // MVE_VRMLALDAVHaxs32 1474 UINT64_C(4001369856), // MVE_VRMLALDAVHs32 1475 UINT64_C(4269805312), // MVE_VRMLALDAVHu32 1476 UINT64_C(4001373952), // MVE_VRMLALDAVHxs32 1477 UINT64_C(4269805089), // MVE_VRMLSLDAVHas32 1478 UINT64_C(4269809185), // MVE_VRMLSLDAVHaxs32 1479 UINT64_C(4269805057), // MVE_VRMLSLDAVHs32 1480 UINT64_C(4269809153), // MVE_VRMLSLDAVHxs32 1481 UINT64_C(3994099201), // MVE_VRMULHs16 1482 UINT64_C(3995147777), // MVE_VRMULHs32 1483 UINT64_C(3993050625), // MVE_VRMULHs8 1484 UINT64_C(4262534657), // MVE_VRMULHu16 1485 UINT64_C(4263583233), // MVE_VRMULHu32 1486 UINT64_C(4261486081), // MVE_VRMULHu8 1487 UINT64_C(4010804544), // MVE_VRSHL_by_vecs16 1488 UINT64_C(4011853120), // MVE_VRSHL_by_vecs32 1489 UINT64_C(4009755968), // MVE_VRSHL_by_vecs8 1490 UINT64_C(4279240000), // MVE_VRSHL_by_vecu16 1491 UINT64_C(4280288576), // MVE_VRSHL_by_vecu32 1492 UINT64_C(4278191424), // MVE_VRSHL_by_vecu8 1493 UINT64_C(3996589664), // MVE_VRSHL_qrs16 1494 UINT64_C(3996851808), // MVE_VRSHL_qrs32 1495 UINT64_C(3996327520), // MVE_VRSHL_qrs8 1496 UINT64_C(4265025120), // MVE_VRSHL_qru16 1497 UINT64_C(4265287264), // MVE_VRSHL_qru32 1498 UINT64_C(4264762976), // MVE_VRSHL_qru8 1499 UINT64_C(4270329793), // MVE_VRSHRNi16bh 1500 UINT64_C(4270333889), // MVE_VRSHRNi16th 1501 UINT64_C(4270854081), // MVE_VRSHRNi32bh 1502 UINT64_C(4270858177), // MVE_VRSHRNi32th 1503 UINT64_C(4019192400), // MVE_VRSHR_imms16 1504 UINT64_C(4020240976), // MVE_VRSHR_imms32 1505 UINT64_C(4018668112), // MVE_VRSHR_imms8 1506 UINT64_C(4287627856), // MVE_VRSHR_immu16 1507 UINT64_C(4288676432), // MVE_VRSHR_immu32 1508 UINT64_C(4287103568), // MVE_VRSHR_immu8 1509 UINT64_C(4264562432), // MVE_VSBC 1510 UINT64_C(4264566528), // MVE_VSBCI 1511 UINT64_C(4003467200), // MVE_VSHLC 1512 UINT64_C(4004515648), // MVE_VSHLL_imms16bh 1513 UINT64_C(4004519744), // MVE_VSHLL_imms16th 1514 UINT64_C(4003991360), // MVE_VSHLL_imms8bh 1515 UINT64_C(4003995456), // MVE_VSHLL_imms8th 1516 UINT64_C(4272951104), // MVE_VSHLL_immu16bh 1517 UINT64_C(4272955200), // MVE_VSHLL_immu16th 1518 UINT64_C(4272426816), // MVE_VSHLL_immu8bh 1519 UINT64_C(4272430912), // MVE_VSHLL_immu8th 1520 UINT64_C(3996454401), // MVE_VSHLL_lws16bh 1521 UINT64_C(3996458497), // MVE_VSHLL_lws16th 1522 UINT64_C(3996192257), // MVE_VSHLL_lws8bh 1523 UINT64_C(3996196353), // MVE_VSHLL_lws8th 1524 UINT64_C(4264889857), // MVE_VSHLL_lwu16bh 1525 UINT64_C(4264893953), // MVE_VSHLL_lwu16th 1526 UINT64_C(4264627713), // MVE_VSHLL_lwu8bh 1527 UINT64_C(4264631809), // MVE_VSHLL_lwu8th 1528 UINT64_C(4010804288), // MVE_VSHL_by_vecs16 1529 UINT64_C(4011852864), // MVE_VSHL_by_vecs32 1530 UINT64_C(4009755712), // MVE_VSHL_by_vecs8 1531 UINT64_C(4279239744), // MVE_VSHL_by_vecu16 1532 UINT64_C(4280288320), // MVE_VSHL_by_vecu32 1533 UINT64_C(4278191168), // MVE_VSHL_by_vecu8 1534 UINT64_C(4019193168), // MVE_VSHL_immi16 1535 UINT64_C(4020241744), // MVE_VSHL_immi32 1536 UINT64_C(4018668880), // MVE_VSHL_immi8 1537 UINT64_C(3996458592), // MVE_VSHL_qrs16 1538 UINT64_C(3996720736), // MVE_VSHL_qrs32 1539 UINT64_C(3996196448), // MVE_VSHL_qrs8 1540 UINT64_C(4264894048), // MVE_VSHL_qru16 1541 UINT64_C(4265156192), // MVE_VSHL_qru32 1542 UINT64_C(4264631904), // MVE_VSHL_qru8 1543 UINT64_C(4001894337), // MVE_VSHRNi16bh 1544 UINT64_C(4001898433), // MVE_VSHRNi16th 1545 UINT64_C(4002418625), // MVE_VSHRNi32bh 1546 UINT64_C(4002422721), // MVE_VSHRNi32th 1547 UINT64_C(4019191888), // MVE_VSHR_imms16 1548 UINT64_C(4020240464), // MVE_VSHR_imms32 1549 UINT64_C(4018667600), // MVE_VSHR_imms8 1550 UINT64_C(4287627344), // MVE_VSHR_immu16 1551 UINT64_C(4288675920), // MVE_VSHR_immu32 1552 UINT64_C(4287103056), // MVE_VSHR_immu8 1553 UINT64_C(4287628624), // MVE_VSLIimm16 1554 UINT64_C(4288677200), // MVE_VSLIimm32 1555 UINT64_C(4287104336), // MVE_VSLIimm8 1556 UINT64_C(4287628368), // MVE_VSRIimm16 1557 UINT64_C(4288676944), // MVE_VSRIimm32 1558 UINT64_C(4287104080), // MVE_VSRIimm8 1559 UINT64_C(4236254848), // MVE_VST20_16 1560 UINT64_C(4238352000), // MVE_VST20_16_wb 1561 UINT64_C(4236254976), // MVE_VST20_32 1562 UINT64_C(4238352128), // MVE_VST20_32_wb 1563 UINT64_C(4236254720), // MVE_VST20_8 1564 UINT64_C(4238351872), // MVE_VST20_8_wb 1565 UINT64_C(4236254880), // MVE_VST21_16 1566 UINT64_C(4238352032), // MVE_VST21_16_wb 1567 UINT64_C(4236255008), // MVE_VST21_32 1568 UINT64_C(4238352160), // MVE_VST21_32_wb 1569 UINT64_C(4236254752), // MVE_VST21_8 1570 UINT64_C(4238351904), // MVE_VST21_8_wb 1571 UINT64_C(4236254849), // MVE_VST40_16 1572 UINT64_C(4238352001), // MVE_VST40_16_wb 1573 UINT64_C(4236254977), // MVE_VST40_32 1574 UINT64_C(4238352129), // MVE_VST40_32_wb 1575 UINT64_C(4236254721), // MVE_VST40_8 1576 UINT64_C(4238351873), // MVE_VST40_8_wb 1577 UINT64_C(4236254881), // MVE_VST41_16 1578 UINT64_C(4238352033), // MVE_VST41_16_wb 1579 UINT64_C(4236255009), // MVE_VST41_32 1580 UINT64_C(4238352161), // MVE_VST41_32_wb 1581 UINT64_C(4236254753), // MVE_VST41_8 1582 UINT64_C(4238351905), // MVE_VST41_8_wb 1583 UINT64_C(4236254913), // MVE_VST42_16 1584 UINT64_C(4238352065), // MVE_VST42_16_wb 1585 UINT64_C(4236255041), // MVE_VST42_32 1586 UINT64_C(4238352193), // MVE_VST42_32_wb 1587 UINT64_C(4236254785), // MVE_VST42_8 1588 UINT64_C(4238351937), // MVE_VST42_8_wb 1589 UINT64_C(4236254945), // MVE_VST43_16 1590 UINT64_C(4238352097), // MVE_VST43_16_wb 1591 UINT64_C(4236255073), // MVE_VST43_32 1592 UINT64_C(4238352225), // MVE_VST43_32_wb 1593 UINT64_C(4236254817), // MVE_VST43_8 1594 UINT64_C(4238351969), // MVE_VST43_8_wb 1595 UINT64_C(3976203904), // MVE_VSTRB16 1596 UINT64_C(3961523840), // MVE_VSTRB16_post 1597 UINT64_C(3978301056), // MVE_VSTRB16_pre 1598 UINT64_C(3967815296), // MVE_VSTRB16_rq 1599 UINT64_C(3976204032), // MVE_VSTRB32 1600 UINT64_C(3961523968), // MVE_VSTRB32_post 1601 UINT64_C(3978301184), // MVE_VSTRB32_pre 1602 UINT64_C(3967815424), // MVE_VSTRB32_rq 1603 UINT64_C(3967815168), // MVE_VSTRB8_rq 1604 UINT64_C(3976207872), // MVE_VSTRBU8 1605 UINT64_C(3961527808), // MVE_VSTRBU8_post 1606 UINT64_C(3978305024), // MVE_VSTRBU8_pre 1607 UINT64_C(4244643584), // MVE_VSTRD64_qi 1608 UINT64_C(4246740736), // MVE_VSTRD64_qi_pre 1609 UINT64_C(3967815633), // MVE_VSTRD64_rq 1610 UINT64_C(3967815632), // MVE_VSTRD64_rq_u 1611 UINT64_C(3967815313), // MVE_VSTRH16_rq 1612 UINT64_C(3967815312), // MVE_VSTRH16_rq_u 1613 UINT64_C(3976728320), // MVE_VSTRH32 1614 UINT64_C(3962048256), // MVE_VSTRH32_post 1615 UINT64_C(3978825472), // MVE_VSTRH32_pre 1616 UINT64_C(3967815441), // MVE_VSTRH32_rq 1617 UINT64_C(3967815440), // MVE_VSTRH32_rq_u 1618 UINT64_C(3976208000), // MVE_VSTRHU16 1619 UINT64_C(3961527936), // MVE_VSTRHU16_post 1620 UINT64_C(3978305152), // MVE_VSTRHU16_pre 1621 UINT64_C(4244643328), // MVE_VSTRW32_qi 1622 UINT64_C(4246740480), // MVE_VSTRW32_qi_pre 1623 UINT64_C(3967815489), // MVE_VSTRW32_rq 1624 UINT64_C(3967815488), // MVE_VSTRW32_rq_u 1625 UINT64_C(3976208128), // MVE_VSTRWU32 1626 UINT64_C(3961528064), // MVE_VSTRWU32_post 1627 UINT64_C(3978305280), // MVE_VSTRWU32_pre 1628 UINT64_C(4264566592), // MVE_VSUB_qr_f16 1629 UINT64_C(3996131136), // MVE_VSUB_qr_f32 1630 UINT64_C(3994099520), // MVE_VSUB_qr_i16 1631 UINT64_C(3995148096), // MVE_VSUB_qr_i32 1632 UINT64_C(3993050944), // MVE_VSUB_qr_i8 1633 UINT64_C(4012903744), // MVE_VSUBf16 1634 UINT64_C(4011855168), // MVE_VSUBf32 1635 UINT64_C(4279240768), // MVE_VSUBi16 1636 UINT64_C(4280289344), // MVE_VSUBi32 1637 UINT64_C(4278192192), // MVE_VSUBi8 1638 UINT64_C(4027629569), // MVE_WLSTP_16 1639 UINT64_C(4028678145), // MVE_WLSTP_32 1640 UINT64_C(4029726721), // MVE_WLSTP_64 1641 UINT64_C(4026580993), // MVE_WLSTP_8 1642 UINT64_C(65011712), // MVNi 1643 UINT64_C(31457280), // MVNr 1644 UINT64_C(31457280), // MVNsi 1645 UINT64_C(31457296), // MVNsr 1646 UINT64_C(4076867344), // NEON_VMAXNMNDf 1647 UINT64_C(4077915920), // NEON_VMAXNMNDh 1648 UINT64_C(4076867408), // NEON_VMAXNMNQf 1649 UINT64_C(4077915984), // NEON_VMAXNMNQh 1650 UINT64_C(4078964496), // NEON_VMINNMNDf 1651 UINT64_C(4080013072), // NEON_VMINNMNDh 1652 UINT64_C(4078964560), // NEON_VMINNMNQf 1653 UINT64_C(4080013136), // NEON_VMINNMNQh 1654 UINT64_C(58720256), // ORRri 1655 UINT64_C(25165824), // ORRrr 1656 UINT64_C(25165824), // ORRrsi 1657 UINT64_C(25165840), // ORRrsr 1658 UINT64_C(109051920), // PKHBT 1659 UINT64_C(109051984), // PKHTB 1660 UINT64_C(4111527936), // PLDWi12 1661 UINT64_C(4145082368), // PLDWrs 1662 UINT64_C(4115722240), // PLDi12 1663 UINT64_C(4149276672), // PLDrs 1664 UINT64_C(4098945024), // PLIi12 1665 UINT64_C(4132499456), // PLIrs 1666 UINT64_C(16777296), // QADD 1667 UINT64_C(102764304), // QADD16 1668 UINT64_C(102764432), // QADD8 1669 UINT64_C(102764336), // QASX 1670 UINT64_C(20971600), // QDADD 1671 UINT64_C(23068752), // QDSUB 1672 UINT64_C(102764368), // QSAX 1673 UINT64_C(18874448), // QSUB 1674 UINT64_C(102764400), // QSUB16 1675 UINT64_C(102764528), // QSUB8 1676 UINT64_C(117378864), // RBIT 1677 UINT64_C(113184560), // REV 1678 UINT64_C(113184688), // REV16 1679 UINT64_C(117378992), // REVSH 1680 UINT64_C(4161800704), // RFEDA 1681 UINT64_C(4163897856), // RFEDA_UPD 1682 UINT64_C(4178577920), // RFEDB 1683 UINT64_C(4180675072), // RFEDB_UPD 1684 UINT64_C(4170189312), // RFEIA 1685 UINT64_C(4172286464), // RFEIA_UPD 1686 UINT64_C(4186966528), // RFEIB 1687 UINT64_C(4189063680), // RFEIB_UPD 1688 UINT64_C(39845888), // RSBri 1689 UINT64_C(6291456), // RSBrr 1690 UINT64_C(6291456), // RSBrsi 1691 UINT64_C(6291472), // RSBrsr 1692 UINT64_C(48234496), // RSCri 1693 UINT64_C(14680064), // RSCrr 1694 UINT64_C(14680064), // RSCrsi 1695 UINT64_C(14680080), // RSCrsr 1696 UINT64_C(101715728), // SADD16 1697 UINT64_C(101715856), // SADD8 1698 UINT64_C(101715760), // SASX 1699 UINT64_C(4118802544), // SB 1700 UINT64_C(46137344), // SBCri 1701 UINT64_C(12582912), // SBCrr 1702 UINT64_C(12582912), // SBCrsi 1703 UINT64_C(12582928), // SBCrsr 1704 UINT64_C(127926352), // SBFX 1705 UINT64_C(118550544), // SDIV 1706 UINT64_C(109055920), // SEL 1707 UINT64_C(4043374592), // SETEND 1708 UINT64_C(4044357632), // SETPAN 1709 UINT64_C(4060089408), // SHA1C 1710 UINT64_C(4088988352), // SHA1H 1711 UINT64_C(4062186560), // SHA1M 1712 UINT64_C(4061137984), // SHA1P 1713 UINT64_C(4063235136), // SHA1SU0 1714 UINT64_C(4089054080), // SHA1SU1 1715 UINT64_C(4076866624), // SHA256H 1716 UINT64_C(4077915200), // SHA256H2 1717 UINT64_C(4089054144), // SHA256SU0 1718 UINT64_C(4078963776), // SHA256SU1 1719 UINT64_C(103812880), // SHADD16 1720 UINT64_C(103813008), // SHADD8 1721 UINT64_C(103812912), // SHASX 1722 UINT64_C(103812944), // SHSAX 1723 UINT64_C(103812976), // SHSUB16 1724 UINT64_C(103813104), // SHSUB8 1725 UINT64_C(23068784), // SMC 1726 UINT64_C(16777344), // SMLABB 1727 UINT64_C(16777408), // SMLABT 1728 UINT64_C(117440528), // SMLAD 1729 UINT64_C(117440560), // SMLADX 1730 UINT64_C(14680208), // SMLAL 1731 UINT64_C(20971648), // SMLALBB 1732 UINT64_C(20971712), // SMLALBT 1733 UINT64_C(121634832), // SMLALD 1734 UINT64_C(121634864), // SMLALDX 1735 UINT64_C(20971680), // SMLALTB 1736 UINT64_C(20971744), // SMLALTT 1737 UINT64_C(16777376), // SMLATB 1738 UINT64_C(16777440), // SMLATT 1739 UINT64_C(18874496), // SMLAWB 1740 UINT64_C(18874560), // SMLAWT 1741 UINT64_C(117440592), // SMLSD 1742 UINT64_C(117440624), // SMLSDX 1743 UINT64_C(121634896), // SMLSLD 1744 UINT64_C(121634928), // SMLSLDX 1745 UINT64_C(122683408), // SMMLA 1746 UINT64_C(122683440), // SMMLAR 1747 UINT64_C(122683600), // SMMLS 1748 UINT64_C(122683632), // SMMLSR 1749 UINT64_C(122744848), // SMMUL 1750 UINT64_C(122744880), // SMMULR 1751 UINT64_C(117501968), // SMUAD 1752 UINT64_C(117502000), // SMUADX 1753 UINT64_C(23068800), // SMULBB 1754 UINT64_C(23068864), // SMULBT 1755 UINT64_C(12583056), // SMULL 1756 UINT64_C(23068832), // SMULTB 1757 UINT64_C(23068896), // SMULTT 1758 UINT64_C(18874528), // SMULWB 1759 UINT64_C(18874592), // SMULWT 1760 UINT64_C(117502032), // SMUSD 1761 UINT64_C(117502064), // SMUSDX 1762 UINT64_C(4165797120), // SRSDA 1763 UINT64_C(4167894272), // SRSDA_UPD 1764 UINT64_C(4182574336), // SRSDB 1765 UINT64_C(4184671488), // SRSDB_UPD 1766 UINT64_C(4174185728), // SRSIA 1767 UINT64_C(4176282880), // SRSIA_UPD 1768 UINT64_C(4190962944), // SRSIB 1769 UINT64_C(4193060096), // SRSIB_UPD 1770 UINT64_C(111149072), // SSAT 1771 UINT64_C(111152944), // SSAT16 1772 UINT64_C(101715792), // SSAX 1773 UINT64_C(101715824), // SSUB16 1774 UINT64_C(101715952), // SSUB8 1775 UINT64_C(4248829952), // STC2L_OFFSET 1776 UINT64_C(4240441344), // STC2L_OPTION 1777 UINT64_C(4234149888), // STC2L_POST 1778 UINT64_C(4250927104), // STC2L_PRE 1779 UINT64_C(4244635648), // STC2_OFFSET 1780 UINT64_C(4236247040), // STC2_OPTION 1781 UINT64_C(4229955584), // STC2_POST 1782 UINT64_C(4246732800), // STC2_PRE 1783 UINT64_C(222298112), // STCL_OFFSET 1784 UINT64_C(213909504), // STCL_OPTION 1785 UINT64_C(207618048), // STCL_POST 1786 UINT64_C(224395264), // STCL_PRE 1787 UINT64_C(218103808), // STC_OFFSET 1788 UINT64_C(209715200), // STC_OPTION 1789 UINT64_C(203423744), // STC_POST 1790 UINT64_C(220200960), // STC_PRE 1791 UINT64_C(25230480), // STL 1792 UINT64_C(29424784), // STLB 1793 UINT64_C(25169552), // STLEX 1794 UINT64_C(29363856), // STLEXB 1795 UINT64_C(27266704), // STLEXD 1796 UINT64_C(31461008), // STLEXH 1797 UINT64_C(31521936), // STLH 1798 UINT64_C(134217728), // STMDA 1799 UINT64_C(136314880), // STMDA_UPD 1800 UINT64_C(150994944), // STMDB 1801 UINT64_C(153092096), // STMDB_UPD 1802 UINT64_C(142606336), // STMIA 1803 UINT64_C(144703488), // STMIA_UPD 1804 UINT64_C(159383552), // STMIB 1805 UINT64_C(161480704), // STMIB_UPD 1806 UINT64_C(73400320), // STRBT_POST_IMM 1807 UINT64_C(106954752), // STRBT_POST_REG 1808 UINT64_C(71303168), // STRB_POST_IMM 1809 UINT64_C(104857600), // STRB_POST_REG 1810 UINT64_C(90177536), // STRB_PRE_IMM 1811 UINT64_C(123731968), // STRB_PRE_REG 1812 UINT64_C(88080384), // STRBi12 1813 UINT64_C(121634816), // STRBrs 1814 UINT64_C(16777456), // STRD 1815 UINT64_C(240), // STRD_POST 1816 UINT64_C(18874608), // STRD_PRE 1817 UINT64_C(25169808), // STREX 1818 UINT64_C(29364112), // STREXB 1819 UINT64_C(27266960), // STREXD 1820 UINT64_C(31461264), // STREXH 1821 UINT64_C(16777392), // STRH 1822 UINT64_C(6291632), // STRHTi 1823 UINT64_C(2097328), // STRHTr 1824 UINT64_C(176), // STRH_POST 1825 UINT64_C(18874544), // STRH_PRE 1826 UINT64_C(69206016), // STRT_POST_IMM 1827 UINT64_C(102760448), // STRT_POST_REG 1828 UINT64_C(67108864), // STR_POST_IMM 1829 UINT64_C(100663296), // STR_POST_REG 1830 UINT64_C(85983232), // STR_PRE_IMM 1831 UINT64_C(119537664), // STR_PRE_REG 1832 UINT64_C(83886080), // STRi12 1833 UINT64_C(117440512), // STRrs 1834 UINT64_C(37748736), // SUBri 1835 UINT64_C(4194304), // SUBrr 1836 UINT64_C(4194304), // SUBrsi 1837 UINT64_C(4194320), // SUBrsr 1838 UINT64_C(251658240), // SVC 1839 UINT64_C(16777360), // SWP 1840 UINT64_C(20971664), // SWPB 1841 UINT64_C(111149168), // SXTAB 1842 UINT64_C(109052016), // SXTAB16 1843 UINT64_C(112197744), // SXTAH 1844 UINT64_C(112132208), // SXTB 1845 UINT64_C(110035056), // SXTB16 1846 UINT64_C(113180784), // SXTH 1847 UINT64_C(53477376), // TEQri 1848 UINT64_C(19922944), // TEQrr 1849 UINT64_C(19922944), // TEQrsi 1850 UINT64_C(19922960), // TEQrsr 1851 UINT64_C(3892305662), // TRAP 1852 UINT64_C(3892240112), // TRAPNaCl 1853 UINT64_C(3810586642), // TSB 1854 UINT64_C(51380224), // TSTri 1855 UINT64_C(17825792), // TSTrr 1856 UINT64_C(17825792), // TSTrsi 1857 UINT64_C(17825808), // TSTrsr 1858 UINT64_C(105910032), // UADD16 1859 UINT64_C(105910160), // UADD8 1860 UINT64_C(105910064), // UASX 1861 UINT64_C(132120656), // UBFX 1862 UINT64_C(3891265776), // UDF 1863 UINT64_C(120647696), // UDIV 1864 UINT64_C(108007184), // UHADD16 1865 UINT64_C(108007312), // UHADD8 1866 UINT64_C(108007216), // UHASX 1867 UINT64_C(108007248), // UHSAX 1868 UINT64_C(108007280), // UHSUB16 1869 UINT64_C(108007408), // UHSUB8 1870 UINT64_C(4194448), // UMAAL 1871 UINT64_C(10485904), // UMLAL 1872 UINT64_C(8388752), // UMULL 1873 UINT64_C(106958608), // UQADD16 1874 UINT64_C(106958736), // UQADD8 1875 UINT64_C(106958640), // UQASX 1876 UINT64_C(106958672), // UQSAX 1877 UINT64_C(106958704), // UQSUB16 1878 UINT64_C(106958832), // UQSUB8 1879 UINT64_C(125890576), // USAD8 1880 UINT64_C(125829136), // USADA8 1881 UINT64_C(115343376), // USAT 1882 UINT64_C(115347248), // USAT16 1883 UINT64_C(105910096), // USAX 1884 UINT64_C(105910128), // USUB16 1885 UINT64_C(105910256), // USUB8 1886 UINT64_C(115343472), // UXTAB 1887 UINT64_C(113246320), // UXTAB16 1888 UINT64_C(116392048), // UXTAH 1889 UINT64_C(116326512), // UXTB 1890 UINT64_C(114229360), // UXTB16 1891 UINT64_C(117375088), // UXTH 1892 UINT64_C(4070573312), // VABALsv2i64 1893 UINT64_C(4069524736), // VABALsv4i32 1894 UINT64_C(4068476160), // VABALsv8i16 1895 UINT64_C(4087350528), // VABALuv2i64 1896 UINT64_C(4086301952), // VABALuv4i32 1897 UINT64_C(4085253376), // VABALuv8i16 1898 UINT64_C(4060088144), // VABAsv16i8 1899 UINT64_C(4062185232), // VABAsv2i32 1900 UINT64_C(4061136656), // VABAsv4i16 1901 UINT64_C(4062185296), // VABAsv4i32 1902 UINT64_C(4061136720), // VABAsv8i16 1903 UINT64_C(4060088080), // VABAsv8i8 1904 UINT64_C(4076865360), // VABAuv16i8 1905 UINT64_C(4078962448), // VABAuv2i32 1906 UINT64_C(4077913872), // VABAuv4i16 1907 UINT64_C(4078962512), // VABAuv4i32 1908 UINT64_C(4077913936), // VABAuv8i16 1909 UINT64_C(4076865296), // VABAuv8i8 1910 UINT64_C(4070573824), // VABDLsv2i64 1911 UINT64_C(4069525248), // VABDLsv4i32 1912 UINT64_C(4068476672), // VABDLsv8i16 1913 UINT64_C(4087351040), // VABDLuv2i64 1914 UINT64_C(4086302464), // VABDLuv4i32 1915 UINT64_C(4085253888), // VABDLuv8i16 1916 UINT64_C(4078963968), // VABDfd 1917 UINT64_C(4078964032), // VABDfq 1918 UINT64_C(4080012544), // VABDhd 1919 UINT64_C(4080012608), // VABDhq 1920 UINT64_C(4060088128), // VABDsv16i8 1921 UINT64_C(4062185216), // VABDsv2i32 1922 UINT64_C(4061136640), // VABDsv4i16 1923 UINT64_C(4062185280), // VABDsv4i32 1924 UINT64_C(4061136704), // VABDsv8i16 1925 UINT64_C(4060088064), // VABDsv8i8 1926 UINT64_C(4076865344), // VABDuv16i8 1927 UINT64_C(4078962432), // VABDuv2i32 1928 UINT64_C(4077913856), // VABDuv4i16 1929 UINT64_C(4078962496), // VABDuv4i32 1930 UINT64_C(4077913920), // VABDuv8i16 1931 UINT64_C(4076865280), // VABDuv8i8 1932 UINT64_C(246418368), // VABSD 1933 UINT64_C(246417856), // VABSH 1934 UINT64_C(246418112), // VABSS 1935 UINT64_C(4088989440), // VABSfd 1936 UINT64_C(4088989504), // VABSfq 1937 UINT64_C(4088727296), // VABShd 1938 UINT64_C(4088727360), // VABShq 1939 UINT64_C(4088464192), // VABSv16i8 1940 UINT64_C(4088988416), // VABSv2i32 1941 UINT64_C(4088726272), // VABSv4i16 1942 UINT64_C(4088988480), // VABSv4i32 1943 UINT64_C(4088726336), // VABSv8i16 1944 UINT64_C(4088464128), // VABSv8i8 1945 UINT64_C(4076867088), // VACGEfd 1946 UINT64_C(4076867152), // VACGEfq 1947 UINT64_C(4077915664), // VACGEhd 1948 UINT64_C(4077915728), // VACGEhq 1949 UINT64_C(4078964240), // VACGTfd 1950 UINT64_C(4078964304), // VACGTfq 1951 UINT64_C(4080012816), // VACGThd 1952 UINT64_C(4080012880), // VACGThq 1953 UINT64_C(238029568), // VADDD 1954 UINT64_C(238029056), // VADDH 1955 UINT64_C(4070573056), // VADDHNv2i32 1956 UINT64_C(4069524480), // VADDHNv4i16 1957 UINT64_C(4068475904), // VADDHNv8i8 1958 UINT64_C(4070572032), // VADDLsv2i64 1959 UINT64_C(4069523456), // VADDLsv4i32 1960 UINT64_C(4068474880), // VADDLsv8i16 1961 UINT64_C(4087349248), // VADDLuv2i64 1962 UINT64_C(4086300672), // VADDLuv4i32 1963 UINT64_C(4085252096), // VADDLuv8i16 1964 UINT64_C(238029312), // VADDS 1965 UINT64_C(4070572288), // VADDWsv2i64 1966 UINT64_C(4069523712), // VADDWsv4i32 1967 UINT64_C(4068475136), // VADDWsv8i16 1968 UINT64_C(4087349504), // VADDWuv2i64 1969 UINT64_C(4086300928), // VADDWuv4i32 1970 UINT64_C(4085252352), // VADDWuv8i16 1971 UINT64_C(4060089600), // VADDfd 1972 UINT64_C(4060089664), // VADDfq 1973 UINT64_C(4061138176), // VADDhd 1974 UINT64_C(4061138240), // VADDhq 1975 UINT64_C(4060088384), // VADDv16i8 1976 UINT64_C(4063234048), // VADDv1i64 1977 UINT64_C(4062185472), // VADDv2i32 1978 UINT64_C(4063234112), // VADDv2i64 1979 UINT64_C(4061136896), // VADDv4i16 1980 UINT64_C(4062185536), // VADDv4i32 1981 UINT64_C(4061136960), // VADDv8i16 1982 UINT64_C(4060088320), // VADDv8i8 1983 UINT64_C(4060086544), // VANDd 1984 UINT64_C(4060086608), // VANDq 1985 UINT64_C(4061135120), // VBICd 1986 UINT64_C(4068475184), // VBICiv2i32 1987 UINT64_C(4068477232), // VBICiv4i16 1988 UINT64_C(4068475248), // VBICiv4i32 1989 UINT64_C(4068477296), // VBICiv8i16 1990 UINT64_C(4061135184), // VBICq 1991 UINT64_C(4080009488), // VBIFd 1992 UINT64_C(4080009552), // VBIFq 1993 UINT64_C(4078960912), // VBITd 1994 UINT64_C(4078960976), // VBITq 1995 UINT64_C(4077912336), // VBSLd 1996 UINT64_C(4077912400), // VBSLq 1997 UINT64_C(4237297664), // VCADDv2f32 1998 UINT64_C(4236249088), // VCADDv4f16 1999 UINT64_C(4237297728), // VCADDv4f32 2000 UINT64_C(4236249152), // VCADDv8f16 2001 UINT64_C(4060089856), // VCEQfd 2002 UINT64_C(4060089920), // VCEQfq 2003 UINT64_C(4061138432), // VCEQhd 2004 UINT64_C(4061138496), // VCEQhq 2005 UINT64_C(4076865616), // VCEQv16i8 2006 UINT64_C(4078962704), // VCEQv2i32 2007 UINT64_C(4077914128), // VCEQv4i16 2008 UINT64_C(4078962768), // VCEQv4i32 2009 UINT64_C(4077914192), // VCEQv8i16 2010 UINT64_C(4076865552), // VCEQv8i8 2011 UINT64_C(4088463680), // VCEQzv16i8 2012 UINT64_C(4088988928), // VCEQzv2f32 2013 UINT64_C(4088987904), // VCEQzv2i32 2014 UINT64_C(4088726784), // VCEQzv4f16 2015 UINT64_C(4088988992), // VCEQzv4f32 2016 UINT64_C(4088725760), // VCEQzv4i16 2017 UINT64_C(4088987968), // VCEQzv4i32 2018 UINT64_C(4088726848), // VCEQzv8f16 2019 UINT64_C(4088725824), // VCEQzv8i16 2020 UINT64_C(4088463616), // VCEQzv8i8 2021 UINT64_C(4076867072), // VCGEfd 2022 UINT64_C(4076867136), // VCGEfq 2023 UINT64_C(4077915648), // VCGEhd 2024 UINT64_C(4077915712), // VCGEhq 2025 UINT64_C(4060087120), // VCGEsv16i8 2026 UINT64_C(4062184208), // VCGEsv2i32 2027 UINT64_C(4061135632), // VCGEsv4i16 2028 UINT64_C(4062184272), // VCGEsv4i32 2029 UINT64_C(4061135696), // VCGEsv8i16 2030 UINT64_C(4060087056), // VCGEsv8i8 2031 UINT64_C(4076864336), // VCGEuv16i8 2032 UINT64_C(4078961424), // VCGEuv2i32 2033 UINT64_C(4077912848), // VCGEuv4i16 2034 UINT64_C(4078961488), // VCGEuv4i32 2035 UINT64_C(4077912912), // VCGEuv8i16 2036 UINT64_C(4076864272), // VCGEuv8i8 2037 UINT64_C(4088463552), // VCGEzv16i8 2038 UINT64_C(4088988800), // VCGEzv2f32 2039 UINT64_C(4088987776), // VCGEzv2i32 2040 UINT64_C(4088726656), // VCGEzv4f16 2041 UINT64_C(4088988864), // VCGEzv4f32 2042 UINT64_C(4088725632), // VCGEzv4i16 2043 UINT64_C(4088987840), // VCGEzv4i32 2044 UINT64_C(4088726720), // VCGEzv8f16 2045 UINT64_C(4088725696), // VCGEzv8i16 2046 UINT64_C(4088463488), // VCGEzv8i8 2047 UINT64_C(4078964224), // VCGTfd 2048 UINT64_C(4078964288), // VCGTfq 2049 UINT64_C(4080012800), // VCGThd 2050 UINT64_C(4080012864), // VCGThq 2051 UINT64_C(4060087104), // VCGTsv16i8 2052 UINT64_C(4062184192), // VCGTsv2i32 2053 UINT64_C(4061135616), // VCGTsv4i16 2054 UINT64_C(4062184256), // VCGTsv4i32 2055 UINT64_C(4061135680), // VCGTsv8i16 2056 UINT64_C(4060087040), // VCGTsv8i8 2057 UINT64_C(4076864320), // VCGTuv16i8 2058 UINT64_C(4078961408), // VCGTuv2i32 2059 UINT64_C(4077912832), // VCGTuv4i16 2060 UINT64_C(4078961472), // VCGTuv4i32 2061 UINT64_C(4077912896), // VCGTuv8i16 2062 UINT64_C(4076864256), // VCGTuv8i8 2063 UINT64_C(4088463424), // VCGTzv16i8 2064 UINT64_C(4088988672), // VCGTzv2f32 2065 UINT64_C(4088987648), // VCGTzv2i32 2066 UINT64_C(4088726528), // VCGTzv4f16 2067 UINT64_C(4088988736), // VCGTzv4f32 2068 UINT64_C(4088725504), // VCGTzv4i16 2069 UINT64_C(4088987712), // VCGTzv4i32 2070 UINT64_C(4088726592), // VCGTzv8f16 2071 UINT64_C(4088725568), // VCGTzv8i16 2072 UINT64_C(4088463360), // VCGTzv8i8 2073 UINT64_C(4088463808), // VCLEzv16i8 2074 UINT64_C(4088989056), // VCLEzv2f32 2075 UINT64_C(4088988032), // VCLEzv2i32 2076 UINT64_C(4088726912), // VCLEzv4f16 2077 UINT64_C(4088989120), // VCLEzv4f32 2078 UINT64_C(4088725888), // VCLEzv4i16 2079 UINT64_C(4088988096), // VCLEzv4i32 2080 UINT64_C(4088726976), // VCLEzv8f16 2081 UINT64_C(4088725952), // VCLEzv8i16 2082 UINT64_C(4088463744), // VCLEzv8i8 2083 UINT64_C(4088398912), // VCLSv16i8 2084 UINT64_C(4088923136), // VCLSv2i32 2085 UINT64_C(4088660992), // VCLSv4i16 2086 UINT64_C(4088923200), // VCLSv4i32 2087 UINT64_C(4088661056), // VCLSv8i16 2088 UINT64_C(4088398848), // VCLSv8i8 2089 UINT64_C(4088463936), // VCLTzv16i8 2090 UINT64_C(4088989184), // VCLTzv2f32 2091 UINT64_C(4088988160), // VCLTzv2i32 2092 UINT64_C(4088727040), // VCLTzv4f16 2093 UINT64_C(4088989248), // VCLTzv4f32 2094 UINT64_C(4088726016), // VCLTzv4i16 2095 UINT64_C(4088988224), // VCLTzv4i32 2096 UINT64_C(4088727104), // VCLTzv8f16 2097 UINT64_C(4088726080), // VCLTzv8i16 2098 UINT64_C(4088463872), // VCLTzv8i8 2099 UINT64_C(4088399040), // VCLZv16i8 2100 UINT64_C(4088923264), // VCLZv2i32 2101 UINT64_C(4088661120), // VCLZv4i16 2102 UINT64_C(4088923328), // VCLZv4i32 2103 UINT64_C(4088661184), // VCLZv8i16 2104 UINT64_C(4088398976), // VCLZv8i8 2105 UINT64_C(4231006208), // VCMLAv2f32 2106 UINT64_C(4269803520), // VCMLAv2f32_indexed 2107 UINT64_C(4229957632), // VCMLAv4f16 2108 UINT64_C(4261414912), // VCMLAv4f16_indexed 2109 UINT64_C(4231006272), // VCMLAv4f32 2110 UINT64_C(4269803584), // VCMLAv4f32_indexed 2111 UINT64_C(4229957696), // VCMLAv8f16 2112 UINT64_C(4261414976), // VCMLAv8f16_indexed 2113 UINT64_C(246680384), // VCMPD 2114 UINT64_C(246680512), // VCMPED 2115 UINT64_C(246680000), // VCMPEH 2116 UINT64_C(246680256), // VCMPES 2117 UINT64_C(246746048), // VCMPEZD 2118 UINT64_C(246745536), // VCMPEZH 2119 UINT64_C(246745792), // VCMPEZS 2120 UINT64_C(246679872), // VCMPH 2121 UINT64_C(246680128), // VCMPS 2122 UINT64_C(246745920), // VCMPZD 2123 UINT64_C(246745408), // VCMPZH 2124 UINT64_C(246745664), // VCMPZS 2125 UINT64_C(4088399104), // VCNTd 2126 UINT64_C(4088399168), // VCNTq 2127 UINT64_C(4089118720), // VCVTANSDf 2128 UINT64_C(4088856576), // VCVTANSDh 2129 UINT64_C(4089118784), // VCVTANSQf 2130 UINT64_C(4088856640), // VCVTANSQh 2131 UINT64_C(4089118848), // VCVTANUDf 2132 UINT64_C(4088856704), // VCVTANUDh 2133 UINT64_C(4089118912), // VCVTANUQf 2134 UINT64_C(4088856768), // VCVTANUQh 2135 UINT64_C(4273736640), // VCVTASD 2136 UINT64_C(4273736128), // VCVTASH 2137 UINT64_C(4273736384), // VCVTASS 2138 UINT64_C(4273736512), // VCVTAUD 2139 UINT64_C(4273736000), // VCVTAUH 2140 UINT64_C(4273736256), // VCVTAUS 2141 UINT64_C(246614848), // VCVTBDH 2142 UINT64_C(246549312), // VCVTBHD 2143 UINT64_C(246549056), // VCVTBHS 2144 UINT64_C(246614592), // VCVTBSH 2145 UINT64_C(246876864), // VCVTDS 2146 UINT64_C(4089119488), // VCVTMNSDf 2147 UINT64_C(4088857344), // VCVTMNSDh 2148 UINT64_C(4089119552), // VCVTMNSQf 2149 UINT64_C(4088857408), // VCVTMNSQh 2150 UINT64_C(4089119616), // VCVTMNUDf 2151 UINT64_C(4088857472), // VCVTMNUDh 2152 UINT64_C(4089119680), // VCVTMNUQf 2153 UINT64_C(4088857536), // VCVTMNUQh 2154 UINT64_C(4273933248), // VCVTMSD 2155 UINT64_C(4273932736), // VCVTMSH 2156 UINT64_C(4273932992), // VCVTMSS 2157 UINT64_C(4273933120), // VCVTMUD 2158 UINT64_C(4273932608), // VCVTMUH 2159 UINT64_C(4273932864), // VCVTMUS 2160 UINT64_C(4089118976), // VCVTNNSDf 2161 UINT64_C(4088856832), // VCVTNNSDh 2162 UINT64_C(4089119040), // VCVTNNSQf 2163 UINT64_C(4088856896), // VCVTNNSQh 2164 UINT64_C(4089119104), // VCVTNNUDf 2165 UINT64_C(4088856960), // VCVTNNUDh 2166 UINT64_C(4089119168), // VCVTNNUQf 2167 UINT64_C(4088857024), // VCVTNNUQh 2168 UINT64_C(4273802176), // VCVTNSD 2169 UINT64_C(4273801664), // VCVTNSH 2170 UINT64_C(4273801920), // VCVTNSS 2171 UINT64_C(4273802048), // VCVTNUD 2172 UINT64_C(4273801536), // VCVTNUH 2173 UINT64_C(4273801792), // VCVTNUS 2174 UINT64_C(4089119232), // VCVTPNSDf 2175 UINT64_C(4088857088), // VCVTPNSDh 2176 UINT64_C(4089119296), // VCVTPNSQf 2177 UINT64_C(4088857152), // VCVTPNSQh 2178 UINT64_C(4089119360), // VCVTPNUDf 2179 UINT64_C(4088857216), // VCVTPNUDh 2180 UINT64_C(4089119424), // VCVTPNUQf 2181 UINT64_C(4088857280), // VCVTPNUQh 2182 UINT64_C(4273867712), // VCVTPSD 2183 UINT64_C(4273867200), // VCVTPSH 2184 UINT64_C(4273867456), // VCVTPSS 2185 UINT64_C(4273867584), // VCVTPUD 2186 UINT64_C(4273867072), // VCVTPUH 2187 UINT64_C(4273867328), // VCVTPUS 2188 UINT64_C(246877120), // VCVTSD 2189 UINT64_C(246614976), // VCVTTDH 2190 UINT64_C(246549440), // VCVTTHD 2191 UINT64_C(246549184), // VCVTTHS 2192 UINT64_C(246614720), // VCVTTSH 2193 UINT64_C(4088792576), // VCVTf2h 2194 UINT64_C(4089120512), // VCVTf2sd 2195 UINT64_C(4089120576), // VCVTf2sq 2196 UINT64_C(4089120640), // VCVTf2ud 2197 UINT64_C(4089120704), // VCVTf2uq 2198 UINT64_C(4068478736), // VCVTf2xsd 2199 UINT64_C(4068478800), // VCVTf2xsq 2200 UINT64_C(4085255952), // VCVTf2xud 2201 UINT64_C(4085256016), // VCVTf2xuq 2202 UINT64_C(4088792832), // VCVTh2f 2203 UINT64_C(4088858368), // VCVTh2sd 2204 UINT64_C(4088858432), // VCVTh2sq 2205 UINT64_C(4088858496), // VCVTh2ud 2206 UINT64_C(4088858560), // VCVTh2uq 2207 UINT64_C(4068478224), // VCVTh2xsd 2208 UINT64_C(4068478288), // VCVTh2xsq 2209 UINT64_C(4085255440), // VCVTh2xud 2210 UINT64_C(4085255504), // VCVTh2xuq 2211 UINT64_C(4089120256), // VCVTs2fd 2212 UINT64_C(4089120320), // VCVTs2fq 2213 UINT64_C(4088858112), // VCVTs2hd 2214 UINT64_C(4088858176), // VCVTs2hq 2215 UINT64_C(4089120384), // VCVTu2fd 2216 UINT64_C(4089120448), // VCVTu2fq 2217 UINT64_C(4088858240), // VCVTu2hd 2218 UINT64_C(4088858304), // VCVTu2hq 2219 UINT64_C(4068478480), // VCVTxs2fd 2220 UINT64_C(4068478544), // VCVTxs2fq 2221 UINT64_C(4068477968), // VCVTxs2hd 2222 UINT64_C(4068478032), // VCVTxs2hq 2223 UINT64_C(4085255696), // VCVTxu2fd 2224 UINT64_C(4085255760), // VCVTxu2fq 2225 UINT64_C(4085255184), // VCVTxu2hd 2226 UINT64_C(4085255248), // VCVTxu2hq 2227 UINT64_C(243272448), // VDIVD 2228 UINT64_C(243271936), // VDIVH 2229 UINT64_C(243272192), // VDIVS 2230 UINT64_C(243272496), // VDUP16d 2231 UINT64_C(245369648), // VDUP16q 2232 UINT64_C(243272464), // VDUP32d 2233 UINT64_C(245369616), // VDUP32q 2234 UINT64_C(247466768), // VDUP8d 2235 UINT64_C(249563920), // VDUP8q 2236 UINT64_C(4088531968), // VDUPLN16d 2237 UINT64_C(4088532032), // VDUPLN16q 2238 UINT64_C(4088663040), // VDUPLN32d 2239 UINT64_C(4088663104), // VDUPLN32q 2240 UINT64_C(4088466432), // VDUPLN8d 2241 UINT64_C(4088466496), // VDUPLN8q 2242 UINT64_C(4076863760), // VEORd 2243 UINT64_C(4076863824), // VEORq 2244 UINT64_C(4071620608), // VEXTd16 2245 UINT64_C(4071620608), // VEXTd32 2246 UINT64_C(4071620608), // VEXTd8 2247 UINT64_C(4071620672), // VEXTq16 2248 UINT64_C(4071620672), // VEXTq32 2249 UINT64_C(4071620672), // VEXTq64 2250 UINT64_C(4071620672), // VEXTq8 2251 UINT64_C(245369600), // VFMAD 2252 UINT64_C(245369088), // VFMAH 2253 UINT64_C(4229957648), // VFMALD 2254 UINT64_C(4261414928), // VFMALDI 2255 UINT64_C(4229957712), // VFMALQ 2256 UINT64_C(4261414992), // VFMALQI 2257 UINT64_C(245369344), // VFMAS 2258 UINT64_C(4060089360), // VFMAfd 2259 UINT64_C(4060089424), // VFMAfq 2260 UINT64_C(4061137936), // VFMAhd 2261 UINT64_C(4061138000), // VFMAhq 2262 UINT64_C(245369664), // VFMSD 2263 UINT64_C(245369152), // VFMSH 2264 UINT64_C(4238346256), // VFMSLD 2265 UINT64_C(4262463504), // VFMSLDI 2266 UINT64_C(4238346320), // VFMSLQ 2267 UINT64_C(4262463568), // VFMSLQI 2268 UINT64_C(245369408), // VFMSS 2269 UINT64_C(4062186512), // VFMSfd 2270 UINT64_C(4062186576), // VFMSfq 2271 UINT64_C(4063235088), // VFMShd 2272 UINT64_C(4063235152), // VFMShq 2273 UINT64_C(244321088), // VFNMAD 2274 UINT64_C(244320576), // VFNMAH 2275 UINT64_C(244320832), // VFNMAS 2276 UINT64_C(244321024), // VFNMSD 2277 UINT64_C(244320512), // VFNMSH 2278 UINT64_C(244320768), // VFNMSS 2279 UINT64_C(4269804288), // VFP_VMAXNMD 2280 UINT64_C(4269803776), // VFP_VMAXNMH 2281 UINT64_C(4269804032), // VFP_VMAXNMS 2282 UINT64_C(4269804352), // VFP_VMINNMD 2283 UINT64_C(4269803840), // VFP_VMINNMH 2284 UINT64_C(4269804096), // VFP_VMINNMS 2285 UINT64_C(235932432), // VGETLNi32 2286 UINT64_C(235932464), // VGETLNs16 2287 UINT64_C(240126736), // VGETLNs8 2288 UINT64_C(244321072), // VGETLNu16 2289 UINT64_C(248515344), // VGETLNu8 2290 UINT64_C(4060086336), // VHADDsv16i8 2291 UINT64_C(4062183424), // VHADDsv2i32 2292 UINT64_C(4061134848), // VHADDsv4i16 2293 UINT64_C(4062183488), // VHADDsv4i32 2294 UINT64_C(4061134912), // VHADDsv8i16 2295 UINT64_C(4060086272), // VHADDsv8i8 2296 UINT64_C(4076863552), // VHADDuv16i8 2297 UINT64_C(4078960640), // VHADDuv2i32 2298 UINT64_C(4077912064), // VHADDuv4i16 2299 UINT64_C(4078960704), // VHADDuv4i32 2300 UINT64_C(4077912128), // VHADDuv8i16 2301 UINT64_C(4076863488), // VHADDuv8i8 2302 UINT64_C(4060086848), // VHSUBsv16i8 2303 UINT64_C(4062183936), // VHSUBsv2i32 2304 UINT64_C(4061135360), // VHSUBsv4i16 2305 UINT64_C(4062184000), // VHSUBsv4i32 2306 UINT64_C(4061135424), // VHSUBsv8i16 2307 UINT64_C(4060086784), // VHSUBsv8i8 2308 UINT64_C(4076864064), // VHSUBuv16i8 2309 UINT64_C(4078961152), // VHSUBuv2i32 2310 UINT64_C(4077912576), // VHSUBuv4i16 2311 UINT64_C(4078961216), // VHSUBuv4i32 2312 UINT64_C(4077912640), // VHSUBuv8i16 2313 UINT64_C(4076864000), // VHSUBuv8i8 2314 UINT64_C(4272949952), // VINSH 2315 UINT64_C(247008192), // VJCVT 2316 UINT64_C(4104129615), // VLD1DUPd16 2317 UINT64_C(4104129613), // VLD1DUPd16wb_fixed 2318 UINT64_C(4104129600), // VLD1DUPd16wb_register 2319 UINT64_C(4104129679), // VLD1DUPd32 2320 UINT64_C(4104129677), // VLD1DUPd32wb_fixed 2321 UINT64_C(4104129664), // VLD1DUPd32wb_register 2322 UINT64_C(4104129551), // VLD1DUPd8 2323 UINT64_C(4104129549), // VLD1DUPd8wb_fixed 2324 UINT64_C(4104129536), // VLD1DUPd8wb_register 2325 UINT64_C(4104129647), // VLD1DUPq16 2326 UINT64_C(4104129645), // VLD1DUPq16wb_fixed 2327 UINT64_C(4104129632), // VLD1DUPq16wb_register 2328 UINT64_C(4104129711), // VLD1DUPq32 2329 UINT64_C(4104129709), // VLD1DUPq32wb_fixed 2330 UINT64_C(4104129696), // VLD1DUPq32wb_register 2331 UINT64_C(4104129583), // VLD1DUPq8 2332 UINT64_C(4104129581), // VLD1DUPq8wb_fixed 2333 UINT64_C(4104129568), // VLD1DUPq8wb_register 2334 UINT64_C(4104127503), // VLD1LNd16 2335 UINT64_C(4104127488), // VLD1LNd16_UPD 2336 UINT64_C(4104128527), // VLD1LNd32 2337 UINT64_C(4104128512), // VLD1LNd32_UPD 2338 UINT64_C(4104126479), // VLD1LNd8 2339 UINT64_C(4104126464), // VLD1LNd8_UPD 2340 UINT64_C(0), // VLD1LNq16Pseudo 2341 UINT64_C(0), // VLD1LNq16Pseudo_UPD 2342 UINT64_C(0), // VLD1LNq32Pseudo 2343 UINT64_C(0), // VLD1LNq32Pseudo_UPD 2344 UINT64_C(0), // VLD1LNq8Pseudo 2345 UINT64_C(0), // VLD1LNq8Pseudo_UPD 2346 UINT64_C(4095739727), // VLD1d16 2347 UINT64_C(4095738447), // VLD1d16Q 2348 UINT64_C(0), // VLD1d16QPseudo 2349 UINT64_C(4095738445), // VLD1d16Qwb_fixed 2350 UINT64_C(4095738432), // VLD1d16Qwb_register 2351 UINT64_C(4095739471), // VLD1d16T 2352 UINT64_C(0), // VLD1d16TPseudo 2353 UINT64_C(4095739469), // VLD1d16Twb_fixed 2354 UINT64_C(4095739456), // VLD1d16Twb_register 2355 UINT64_C(4095739725), // VLD1d16wb_fixed 2356 UINT64_C(4095739712), // VLD1d16wb_register 2357 UINT64_C(4095739791), // VLD1d32 2358 UINT64_C(4095738511), // VLD1d32Q 2359 UINT64_C(0), // VLD1d32QPseudo 2360 UINT64_C(4095738509), // VLD1d32Qwb_fixed 2361 UINT64_C(4095738496), // VLD1d32Qwb_register 2362 UINT64_C(4095739535), // VLD1d32T 2363 UINT64_C(0), // VLD1d32TPseudo 2364 UINT64_C(4095739533), // VLD1d32Twb_fixed 2365 UINT64_C(4095739520), // VLD1d32Twb_register 2366 UINT64_C(4095739789), // VLD1d32wb_fixed 2367 UINT64_C(4095739776), // VLD1d32wb_register 2368 UINT64_C(4095739855), // VLD1d64 2369 UINT64_C(4095738575), // VLD1d64Q 2370 UINT64_C(0), // VLD1d64QPseudo 2371 UINT64_C(0), // VLD1d64QPseudoWB_fixed 2372 UINT64_C(0), // VLD1d64QPseudoWB_register 2373 UINT64_C(4095738573), // VLD1d64Qwb_fixed 2374 UINT64_C(4095738560), // VLD1d64Qwb_register 2375 UINT64_C(4095739599), // VLD1d64T 2376 UINT64_C(0), // VLD1d64TPseudo 2377 UINT64_C(0), // VLD1d64TPseudoWB_fixed 2378 UINT64_C(0), // VLD1d64TPseudoWB_register 2379 UINT64_C(4095739597), // VLD1d64Twb_fixed 2380 UINT64_C(4095739584), // VLD1d64Twb_register 2381 UINT64_C(4095739853), // VLD1d64wb_fixed 2382 UINT64_C(4095739840), // VLD1d64wb_register 2383 UINT64_C(4095739663), // VLD1d8 2384 UINT64_C(4095738383), // VLD1d8Q 2385 UINT64_C(0), // VLD1d8QPseudo 2386 UINT64_C(4095738381), // VLD1d8Qwb_fixed 2387 UINT64_C(4095738368), // VLD1d8Qwb_register 2388 UINT64_C(4095739407), // VLD1d8T 2389 UINT64_C(0), // VLD1d8TPseudo 2390 UINT64_C(4095739405), // VLD1d8Twb_fixed 2391 UINT64_C(4095739392), // VLD1d8Twb_register 2392 UINT64_C(4095739661), // VLD1d8wb_fixed 2393 UINT64_C(4095739648), // VLD1d8wb_register 2394 UINT64_C(4095740495), // VLD1q16 2395 UINT64_C(0), // VLD1q16HighQPseudo 2396 UINT64_C(0), // VLD1q16HighTPseudo 2397 UINT64_C(0), // VLD1q16LowQPseudo_UPD 2398 UINT64_C(0), // VLD1q16LowTPseudo_UPD 2399 UINT64_C(4095740493), // VLD1q16wb_fixed 2400 UINT64_C(4095740480), // VLD1q16wb_register 2401 UINT64_C(4095740559), // VLD1q32 2402 UINT64_C(0), // VLD1q32HighQPseudo 2403 UINT64_C(0), // VLD1q32HighTPseudo 2404 UINT64_C(0), // VLD1q32LowQPseudo_UPD 2405 UINT64_C(0), // VLD1q32LowTPseudo_UPD 2406 UINT64_C(4095740557), // VLD1q32wb_fixed 2407 UINT64_C(4095740544), // VLD1q32wb_register 2408 UINT64_C(4095740623), // VLD1q64 2409 UINT64_C(0), // VLD1q64HighQPseudo 2410 UINT64_C(0), // VLD1q64HighTPseudo 2411 UINT64_C(0), // VLD1q64LowQPseudo_UPD 2412 UINT64_C(0), // VLD1q64LowTPseudo_UPD 2413 UINT64_C(4095740621), // VLD1q64wb_fixed 2414 UINT64_C(4095740608), // VLD1q64wb_register 2415 UINT64_C(4095740431), // VLD1q8 2416 UINT64_C(0), // VLD1q8HighQPseudo 2417 UINT64_C(0), // VLD1q8HighTPseudo 2418 UINT64_C(0), // VLD1q8LowQPseudo_UPD 2419 UINT64_C(0), // VLD1q8LowTPseudo_UPD 2420 UINT64_C(4095740429), // VLD1q8wb_fixed 2421 UINT64_C(4095740416), // VLD1q8wb_register 2422 UINT64_C(4104129871), // VLD2DUPd16 2423 UINT64_C(4104129869), // VLD2DUPd16wb_fixed 2424 UINT64_C(4104129856), // VLD2DUPd16wb_register 2425 UINT64_C(4104129903), // VLD2DUPd16x2 2426 UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed 2427 UINT64_C(4104129888), // VLD2DUPd16x2wb_register 2428 UINT64_C(4104129935), // VLD2DUPd32 2429 UINT64_C(4104129933), // VLD2DUPd32wb_fixed 2430 UINT64_C(4104129920), // VLD2DUPd32wb_register 2431 UINT64_C(4104129967), // VLD2DUPd32x2 2432 UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed 2433 UINT64_C(4104129952), // VLD2DUPd32x2wb_register 2434 UINT64_C(4104129807), // VLD2DUPd8 2435 UINT64_C(4104129805), // VLD2DUPd8wb_fixed 2436 UINT64_C(4104129792), // VLD2DUPd8wb_register 2437 UINT64_C(4104129839), // VLD2DUPd8x2 2438 UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed 2439 UINT64_C(4104129824), // VLD2DUPd8x2wb_register 2440 UINT64_C(0), // VLD2DUPq16EvenPseudo 2441 UINT64_C(0), // VLD2DUPq16OddPseudo 2442 UINT64_C(0), // VLD2DUPq32EvenPseudo 2443 UINT64_C(0), // VLD2DUPq32OddPseudo 2444 UINT64_C(0), // VLD2DUPq8EvenPseudo 2445 UINT64_C(0), // VLD2DUPq8OddPseudo 2446 UINT64_C(4104127759), // VLD2LNd16 2447 UINT64_C(0), // VLD2LNd16Pseudo 2448 UINT64_C(0), // VLD2LNd16Pseudo_UPD 2449 UINT64_C(4104127744), // VLD2LNd16_UPD 2450 UINT64_C(4104128783), // VLD2LNd32 2451 UINT64_C(0), // VLD2LNd32Pseudo 2452 UINT64_C(0), // VLD2LNd32Pseudo_UPD 2453 UINT64_C(4104128768), // VLD2LNd32_UPD 2454 UINT64_C(4104126735), // VLD2LNd8 2455 UINT64_C(0), // VLD2LNd8Pseudo 2456 UINT64_C(0), // VLD2LNd8Pseudo_UPD 2457 UINT64_C(4104126720), // VLD2LNd8_UPD 2458 UINT64_C(4104127791), // VLD2LNq16 2459 UINT64_C(0), // VLD2LNq16Pseudo 2460 UINT64_C(0), // VLD2LNq16Pseudo_UPD 2461 UINT64_C(4104127776), // VLD2LNq16_UPD 2462 UINT64_C(4104128847), // VLD2LNq32 2463 UINT64_C(0), // VLD2LNq32Pseudo 2464 UINT64_C(0), // VLD2LNq32Pseudo_UPD 2465 UINT64_C(4104128832), // VLD2LNq32_UPD 2466 UINT64_C(4095740239), // VLD2b16 2467 UINT64_C(4095740237), // VLD2b16wb_fixed 2468 UINT64_C(4095740224), // VLD2b16wb_register 2469 UINT64_C(4095740303), // VLD2b32 2470 UINT64_C(4095740301), // VLD2b32wb_fixed 2471 UINT64_C(4095740288), // VLD2b32wb_register 2472 UINT64_C(4095740175), // VLD2b8 2473 UINT64_C(4095740173), // VLD2b8wb_fixed 2474 UINT64_C(4095740160), // VLD2b8wb_register 2475 UINT64_C(4095739983), // VLD2d16 2476 UINT64_C(4095739981), // VLD2d16wb_fixed 2477 UINT64_C(4095739968), // VLD2d16wb_register 2478 UINT64_C(4095740047), // VLD2d32 2479 UINT64_C(4095740045), // VLD2d32wb_fixed 2480 UINT64_C(4095740032), // VLD2d32wb_register 2481 UINT64_C(4095739919), // VLD2d8 2482 UINT64_C(4095739917), // VLD2d8wb_fixed 2483 UINT64_C(4095739904), // VLD2d8wb_register 2484 UINT64_C(4095738703), // VLD2q16 2485 UINT64_C(0), // VLD2q16Pseudo 2486 UINT64_C(0), // VLD2q16PseudoWB_fixed 2487 UINT64_C(0), // VLD2q16PseudoWB_register 2488 UINT64_C(4095738701), // VLD2q16wb_fixed 2489 UINT64_C(4095738688), // VLD2q16wb_register 2490 UINT64_C(4095738767), // VLD2q32 2491 UINT64_C(0), // VLD2q32Pseudo 2492 UINT64_C(0), // VLD2q32PseudoWB_fixed 2493 UINT64_C(0), // VLD2q32PseudoWB_register 2494 UINT64_C(4095738765), // VLD2q32wb_fixed 2495 UINT64_C(4095738752), // VLD2q32wb_register 2496 UINT64_C(4095738639), // VLD2q8 2497 UINT64_C(0), // VLD2q8Pseudo 2498 UINT64_C(0), // VLD2q8PseudoWB_fixed 2499 UINT64_C(0), // VLD2q8PseudoWB_register 2500 UINT64_C(4095738637), // VLD2q8wb_fixed 2501 UINT64_C(4095738624), // VLD2q8wb_register 2502 UINT64_C(4104130127), // VLD3DUPd16 2503 UINT64_C(0), // VLD3DUPd16Pseudo 2504 UINT64_C(0), // VLD3DUPd16Pseudo_UPD 2505 UINT64_C(4104130112), // VLD3DUPd16_UPD 2506 UINT64_C(4104130191), // VLD3DUPd32 2507 UINT64_C(0), // VLD3DUPd32Pseudo 2508 UINT64_C(0), // VLD3DUPd32Pseudo_UPD 2509 UINT64_C(4104130176), // VLD3DUPd32_UPD 2510 UINT64_C(4104130063), // VLD3DUPd8 2511 UINT64_C(0), // VLD3DUPd8Pseudo 2512 UINT64_C(0), // VLD3DUPd8Pseudo_UPD 2513 UINT64_C(4104130048), // VLD3DUPd8_UPD 2514 UINT64_C(4104130159), // VLD3DUPq16 2515 UINT64_C(0), // VLD3DUPq16EvenPseudo 2516 UINT64_C(0), // VLD3DUPq16OddPseudo 2517 UINT64_C(4104130144), // VLD3DUPq16_UPD 2518 UINT64_C(4104130223), // VLD3DUPq32 2519 UINT64_C(0), // VLD3DUPq32EvenPseudo 2520 UINT64_C(0), // VLD3DUPq32OddPseudo 2521 UINT64_C(4104130208), // VLD3DUPq32_UPD 2522 UINT64_C(4104130095), // VLD3DUPq8 2523 UINT64_C(0), // VLD3DUPq8EvenPseudo 2524 UINT64_C(0), // VLD3DUPq8OddPseudo 2525 UINT64_C(4104130080), // VLD3DUPq8_UPD 2526 UINT64_C(4104128015), // VLD3LNd16 2527 UINT64_C(0), // VLD3LNd16Pseudo 2528 UINT64_C(0), // VLD3LNd16Pseudo_UPD 2529 UINT64_C(4104128000), // VLD3LNd16_UPD 2530 UINT64_C(4104129039), // VLD3LNd32 2531 UINT64_C(0), // VLD3LNd32Pseudo 2532 UINT64_C(0), // VLD3LNd32Pseudo_UPD 2533 UINT64_C(4104129024), // VLD3LNd32_UPD 2534 UINT64_C(4104126991), // VLD3LNd8 2535 UINT64_C(0), // VLD3LNd8Pseudo 2536 UINT64_C(0), // VLD3LNd8Pseudo_UPD 2537 UINT64_C(4104126976), // VLD3LNd8_UPD 2538 UINT64_C(4104128047), // VLD3LNq16 2539 UINT64_C(0), // VLD3LNq16Pseudo 2540 UINT64_C(0), // VLD3LNq16Pseudo_UPD 2541 UINT64_C(4104128032), // VLD3LNq16_UPD 2542 UINT64_C(4104129103), // VLD3LNq32 2543 UINT64_C(0), // VLD3LNq32Pseudo 2544 UINT64_C(0), // VLD3LNq32Pseudo_UPD 2545 UINT64_C(4104129088), // VLD3LNq32_UPD 2546 UINT64_C(4095738959), // VLD3d16 2547 UINT64_C(0), // VLD3d16Pseudo 2548 UINT64_C(0), // VLD3d16Pseudo_UPD 2549 UINT64_C(4095738944), // VLD3d16_UPD 2550 UINT64_C(4095739023), // VLD3d32 2551 UINT64_C(0), // VLD3d32Pseudo 2552 UINT64_C(0), // VLD3d32Pseudo_UPD 2553 UINT64_C(4095739008), // VLD3d32_UPD 2554 UINT64_C(4095738895), // VLD3d8 2555 UINT64_C(0), // VLD3d8Pseudo 2556 UINT64_C(0), // VLD3d8Pseudo_UPD 2557 UINT64_C(4095738880), // VLD3d8_UPD 2558 UINT64_C(4095739215), // VLD3q16 2559 UINT64_C(0), // VLD3q16Pseudo_UPD 2560 UINT64_C(4095739200), // VLD3q16_UPD 2561 UINT64_C(0), // VLD3q16oddPseudo 2562 UINT64_C(0), // VLD3q16oddPseudo_UPD 2563 UINT64_C(4095739279), // VLD3q32 2564 UINT64_C(0), // VLD3q32Pseudo_UPD 2565 UINT64_C(4095739264), // VLD3q32_UPD 2566 UINT64_C(0), // VLD3q32oddPseudo 2567 UINT64_C(0), // VLD3q32oddPseudo_UPD 2568 UINT64_C(4095739151), // VLD3q8 2569 UINT64_C(0), // VLD3q8Pseudo_UPD 2570 UINT64_C(4095739136), // VLD3q8_UPD 2571 UINT64_C(0), // VLD3q8oddPseudo 2572 UINT64_C(0), // VLD3q8oddPseudo_UPD 2573 UINT64_C(4104130383), // VLD4DUPd16 2574 UINT64_C(0), // VLD4DUPd16Pseudo 2575 UINT64_C(0), // VLD4DUPd16Pseudo_UPD 2576 UINT64_C(4104130368), // VLD4DUPd16_UPD 2577 UINT64_C(4104130447), // VLD4DUPd32 2578 UINT64_C(0), // VLD4DUPd32Pseudo 2579 UINT64_C(0), // VLD4DUPd32Pseudo_UPD 2580 UINT64_C(4104130432), // VLD4DUPd32_UPD 2581 UINT64_C(4104130319), // VLD4DUPd8 2582 UINT64_C(0), // VLD4DUPd8Pseudo 2583 UINT64_C(0), // VLD4DUPd8Pseudo_UPD 2584 UINT64_C(4104130304), // VLD4DUPd8_UPD 2585 UINT64_C(4104130415), // VLD4DUPq16 2586 UINT64_C(0), // VLD4DUPq16EvenPseudo 2587 UINT64_C(0), // VLD4DUPq16OddPseudo 2588 UINT64_C(4104130400), // VLD4DUPq16_UPD 2589 UINT64_C(4104130479), // VLD4DUPq32 2590 UINT64_C(0), // VLD4DUPq32EvenPseudo 2591 UINT64_C(0), // VLD4DUPq32OddPseudo 2592 UINT64_C(4104130464), // VLD4DUPq32_UPD 2593 UINT64_C(4104130351), // VLD4DUPq8 2594 UINT64_C(0), // VLD4DUPq8EvenPseudo 2595 UINT64_C(0), // VLD4DUPq8OddPseudo 2596 UINT64_C(4104130336), // VLD4DUPq8_UPD 2597 UINT64_C(4104128271), // VLD4LNd16 2598 UINT64_C(0), // VLD4LNd16Pseudo 2599 UINT64_C(0), // VLD4LNd16Pseudo_UPD 2600 UINT64_C(4104128256), // VLD4LNd16_UPD 2601 UINT64_C(4104129295), // VLD4LNd32 2602 UINT64_C(0), // VLD4LNd32Pseudo 2603 UINT64_C(0), // VLD4LNd32Pseudo_UPD 2604 UINT64_C(4104129280), // VLD4LNd32_UPD 2605 UINT64_C(4104127247), // VLD4LNd8 2606 UINT64_C(0), // VLD4LNd8Pseudo 2607 UINT64_C(0), // VLD4LNd8Pseudo_UPD 2608 UINT64_C(4104127232), // VLD4LNd8_UPD 2609 UINT64_C(4104128303), // VLD4LNq16 2610 UINT64_C(0), // VLD4LNq16Pseudo 2611 UINT64_C(0), // VLD4LNq16Pseudo_UPD 2612 UINT64_C(4104128288), // VLD4LNq16_UPD 2613 UINT64_C(4104129359), // VLD4LNq32 2614 UINT64_C(0), // VLD4LNq32Pseudo 2615 UINT64_C(0), // VLD4LNq32Pseudo_UPD 2616 UINT64_C(4104129344), // VLD4LNq32_UPD 2617 UINT64_C(4095737935), // VLD4d16 2618 UINT64_C(0), // VLD4d16Pseudo 2619 UINT64_C(0), // VLD4d16Pseudo_UPD 2620 UINT64_C(4095737920), // VLD4d16_UPD 2621 UINT64_C(4095737999), // VLD4d32 2622 UINT64_C(0), // VLD4d32Pseudo 2623 UINT64_C(0), // VLD4d32Pseudo_UPD 2624 UINT64_C(4095737984), // VLD4d32_UPD 2625 UINT64_C(4095737871), // VLD4d8 2626 UINT64_C(0), // VLD4d8Pseudo 2627 UINT64_C(0), // VLD4d8Pseudo_UPD 2628 UINT64_C(4095737856), // VLD4d8_UPD 2629 UINT64_C(4095738191), // VLD4q16 2630 UINT64_C(0), // VLD4q16Pseudo_UPD 2631 UINT64_C(4095738176), // VLD4q16_UPD 2632 UINT64_C(0), // VLD4q16oddPseudo 2633 UINT64_C(0), // VLD4q16oddPseudo_UPD 2634 UINT64_C(4095738255), // VLD4q32 2635 UINT64_C(0), // VLD4q32Pseudo_UPD 2636 UINT64_C(4095738240), // VLD4q32_UPD 2637 UINT64_C(0), // VLD4q32oddPseudo 2638 UINT64_C(0), // VLD4q32oddPseudo_UPD 2639 UINT64_C(4095738127), // VLD4q8 2640 UINT64_C(0), // VLD4q8Pseudo_UPD 2641 UINT64_C(4095738112), // VLD4q8_UPD 2642 UINT64_C(0), // VLD4q8oddPseudo 2643 UINT64_C(0), // VLD4q8oddPseudo_UPD 2644 UINT64_C(221252352), // VLDMDDB_UPD 2645 UINT64_C(210766592), // VLDMDIA 2646 UINT64_C(212863744), // VLDMDIA_UPD 2647 UINT64_C(0), // VLDMQIA 2648 UINT64_C(221252096), // VLDMSDB_UPD 2649 UINT64_C(210766336), // VLDMSIA 2650 UINT64_C(212863488), // VLDMSIA_UPD 2651 UINT64_C(219155200), // VLDRD 2652 UINT64_C(219154688), // VLDRH 2653 UINT64_C(219154944), // VLDRS 2654 UINT64_C(223399808), // VLDR_FPCXTNS_off 2655 UINT64_C(208719744), // VLDR_FPCXTNS_post 2656 UINT64_C(225496960), // VLDR_FPCXTNS_pre 2657 UINT64_C(223408000), // VLDR_FPCXTS_off 2658 UINT64_C(208727936), // VLDR_FPCXTS_post 2659 UINT64_C(225505152), // VLDR_FPCXTS_pre 2660 UINT64_C(219172736), // VLDR_FPSCR_NZCVQC_off 2661 UINT64_C(204492672), // VLDR_FPSCR_NZCVQC_post 2662 UINT64_C(221269888), // VLDR_FPSCR_NZCVQC_pre 2663 UINT64_C(219164544), // VLDR_FPSCR_off 2664 UINT64_C(204484480), // VLDR_FPSCR_post 2665 UINT64_C(221261696), // VLDR_FPSCR_pre 2666 UINT64_C(223391616), // VLDR_P0_off 2667 UINT64_C(208711552), // VLDR_P0_post 2668 UINT64_C(225488768), // VLDR_P0_pre 2669 UINT64_C(223383424), // VLDR_VPR_off 2670 UINT64_C(208703360), // VLDR_VPR_post 2671 UINT64_C(225480576), // VLDR_VPR_pre 2672 UINT64_C(204474880), // VLLDM 2673 UINT64_C(203426304), // VLSTM 2674 UINT64_C(4060090112), // VMAXfd 2675 UINT64_C(4060090176), // VMAXfq 2676 UINT64_C(4061138688), // VMAXhd 2677 UINT64_C(4061138752), // VMAXhq 2678 UINT64_C(4060087872), // VMAXsv16i8 2679 UINT64_C(4062184960), // VMAXsv2i32 2680 UINT64_C(4061136384), // VMAXsv4i16 2681 UINT64_C(4062185024), // VMAXsv4i32 2682 UINT64_C(4061136448), // VMAXsv8i16 2683 UINT64_C(4060087808), // VMAXsv8i8 2684 UINT64_C(4076865088), // VMAXuv16i8 2685 UINT64_C(4078962176), // VMAXuv2i32 2686 UINT64_C(4077913600), // VMAXuv4i16 2687 UINT64_C(4078962240), // VMAXuv4i32 2688 UINT64_C(4077913664), // VMAXuv8i16 2689 UINT64_C(4076865024), // VMAXuv8i8 2690 UINT64_C(4062187264), // VMINfd 2691 UINT64_C(4062187328), // VMINfq 2692 UINT64_C(4063235840), // VMINhd 2693 UINT64_C(4063235904), // VMINhq 2694 UINT64_C(4060087888), // VMINsv16i8 2695 UINT64_C(4062184976), // VMINsv2i32 2696 UINT64_C(4061136400), // VMINsv4i16 2697 UINT64_C(4062185040), // VMINsv4i32 2698 UINT64_C(4061136464), // VMINsv8i16 2699 UINT64_C(4060087824), // VMINsv8i8 2700 UINT64_C(4076865104), // VMINuv16i8 2701 UINT64_C(4078962192), // VMINuv2i32 2702 UINT64_C(4077913616), // VMINuv4i16 2703 UINT64_C(4078962256), // VMINuv4i32 2704 UINT64_C(4077913680), // VMINuv8i16 2705 UINT64_C(4076865040), // VMINuv8i8 2706 UINT64_C(234883840), // VMLAD 2707 UINT64_C(234883328), // VMLAH 2708 UINT64_C(4070572608), // VMLALslsv2i32 2709 UINT64_C(4069524032), // VMLALslsv4i16 2710 UINT64_C(4087349824), // VMLALsluv2i32 2711 UINT64_C(4086301248), // VMLALsluv4i16 2712 UINT64_C(4070574080), // VMLALsv2i64 2713 UINT64_C(4069525504), // VMLALsv4i32 2714 UINT64_C(4068476928), // VMLALsv8i16 2715 UINT64_C(4087351296), // VMLALuv2i64 2716 UINT64_C(4086302720), // VMLALuv4i32 2717 UINT64_C(4085254144), // VMLALuv8i16 2718 UINT64_C(234883584), // VMLAS 2719 UINT64_C(4060089616), // VMLAfd 2720 UINT64_C(4060089680), // VMLAfq 2721 UINT64_C(4061138192), // VMLAhd 2722 UINT64_C(4061138256), // VMLAhq 2723 UINT64_C(4070572352), // VMLAslfd 2724 UINT64_C(4087349568), // VMLAslfq 2725 UINT64_C(4069523776), // VMLAslhd 2726 UINT64_C(4086300992), // VMLAslhq 2727 UINT64_C(4070572096), // VMLAslv2i32 2728 UINT64_C(4069523520), // VMLAslv4i16 2729 UINT64_C(4087349312), // VMLAslv4i32 2730 UINT64_C(4086300736), // VMLAslv8i16 2731 UINT64_C(4060088640), // VMLAv16i8 2732 UINT64_C(4062185728), // VMLAv2i32 2733 UINT64_C(4061137152), // VMLAv4i16 2734 UINT64_C(4062185792), // VMLAv4i32 2735 UINT64_C(4061137216), // VMLAv8i16 2736 UINT64_C(4060088576), // VMLAv8i8 2737 UINT64_C(234883904), // VMLSD 2738 UINT64_C(234883392), // VMLSH 2739 UINT64_C(4070573632), // VMLSLslsv2i32 2740 UINT64_C(4069525056), // VMLSLslsv4i16 2741 UINT64_C(4087350848), // VMLSLsluv2i32 2742 UINT64_C(4086302272), // VMLSLsluv4i16 2743 UINT64_C(4070574592), // VMLSLsv2i64 2744 UINT64_C(4069526016), // VMLSLsv4i32 2745 UINT64_C(4068477440), // VMLSLsv8i16 2746 UINT64_C(4087351808), // VMLSLuv2i64 2747 UINT64_C(4086303232), // VMLSLuv4i32 2748 UINT64_C(4085254656), // VMLSLuv8i16 2749 UINT64_C(234883648), // VMLSS 2750 UINT64_C(4062186768), // VMLSfd 2751 UINT64_C(4062186832), // VMLSfq 2752 UINT64_C(4063235344), // VMLShd 2753 UINT64_C(4063235408), // VMLShq 2754 UINT64_C(4070573376), // VMLSslfd 2755 UINT64_C(4087350592), // VMLSslfq 2756 UINT64_C(4069524800), // VMLSslhd 2757 UINT64_C(4086302016), // VMLSslhq 2758 UINT64_C(4070573120), // VMLSslv2i32 2759 UINT64_C(4069524544), // VMLSslv4i16 2760 UINT64_C(4087350336), // VMLSslv4i32 2761 UINT64_C(4086301760), // VMLSslv8i16 2762 UINT64_C(4076865856), // VMLSv16i8 2763 UINT64_C(4078962944), // VMLSv2i32 2764 UINT64_C(4077914368), // VMLSv4i16 2765 UINT64_C(4078963008), // VMLSv4i32 2766 UINT64_C(4077914432), // VMLSv8i16 2767 UINT64_C(4076865792), // VMLSv8i8 2768 UINT64_C(246418240), // VMOVD 2769 UINT64_C(205523728), // VMOVDRR 2770 UINT64_C(4272949824), // VMOVH 2771 UINT64_C(234883344), // VMOVHR 2772 UINT64_C(4070574608), // VMOVLsv2i64 2773 UINT64_C(4069526032), // VMOVLsv4i32 2774 UINT64_C(4069001744), // VMOVLsv8i16 2775 UINT64_C(4087351824), // VMOVLuv2i64 2776 UINT64_C(4086303248), // VMOVLuv4i32 2777 UINT64_C(4085778960), // VMOVLuv8i16 2778 UINT64_C(4089053696), // VMOVNv2i32 2779 UINT64_C(4088791552), // VMOVNv4i16 2780 UINT64_C(4088529408), // VMOVNv8i8 2781 UINT64_C(235931920), // VMOVRH 2782 UINT64_C(206572304), // VMOVRRD 2783 UINT64_C(206572048), // VMOVRRS 2784 UINT64_C(235932176), // VMOVRS 2785 UINT64_C(246417984), // VMOVS 2786 UINT64_C(234883600), // VMOVSR 2787 UINT64_C(205523472), // VMOVSRR 2788 UINT64_C(4068478544), // VMOVv16i8 2789 UINT64_C(4068478512), // VMOVv1i64 2790 UINT64_C(4068478736), // VMOVv2f32 2791 UINT64_C(4068474896), // VMOVv2i32 2792 UINT64_C(4068478576), // VMOVv2i64 2793 UINT64_C(4068478800), // VMOVv4f32 2794 UINT64_C(4068476944), // VMOVv4i16 2795 UINT64_C(4068474960), // VMOVv4i32 2796 UINT64_C(4068477008), // VMOVv8i16 2797 UINT64_C(4068478480), // VMOVv8i8 2798 UINT64_C(250677776), // VMRS 2799 UINT64_C(251529744), // VMRS_FPCXTNS 2800 UINT64_C(251595280), // VMRS_FPCXTS 2801 UINT64_C(251136528), // VMRS_FPEXC 2802 UINT64_C(251202064), // VMRS_FPINST 2803 UINT64_C(251267600), // VMRS_FPINST2 2804 UINT64_C(250743312), // VMRS_FPSCR_NZCVQC 2805 UINT64_C(250612240), // VMRS_FPSID 2806 UINT64_C(251070992), // VMRS_MVFR0 2807 UINT64_C(251005456), // VMRS_MVFR1 2808 UINT64_C(250939920), // VMRS_MVFR2 2809 UINT64_C(251464208), // VMRS_P0 2810 UINT64_C(251398672), // VMRS_VPR 2811 UINT64_C(249629200), // VMSR 2812 UINT64_C(250481168), // VMSR_FPCXTNS 2813 UINT64_C(250546704), // VMSR_FPCXTS 2814 UINT64_C(250087952), // VMSR_FPEXC 2815 UINT64_C(250153488), // VMSR_FPINST 2816 UINT64_C(250219024), // VMSR_FPINST2 2817 UINT64_C(249694736), // VMSR_FPSCR_NZCVQC 2818 UINT64_C(249563664), // VMSR_FPSID 2819 UINT64_C(250415632), // VMSR_P0 2820 UINT64_C(250350096), // VMSR_VPR 2821 UINT64_C(236980992), // VMULD 2822 UINT64_C(236980480), // VMULH 2823 UINT64_C(4070575616), // VMULLp64 2824 UINT64_C(4068478464), // VMULLp8 2825 UINT64_C(4070574656), // VMULLslsv2i32 2826 UINT64_C(4069526080), // VMULLslsv4i16 2827 UINT64_C(4087351872), // VMULLsluv2i32 2828 UINT64_C(4086303296), // VMULLsluv4i16 2829 UINT64_C(4070575104), // VMULLsv2i64 2830 UINT64_C(4069526528), // VMULLsv4i32 2831 UINT64_C(4068477952), // VMULLsv8i16 2832 UINT64_C(4087352320), // VMULLuv2i64 2833 UINT64_C(4086303744), // VMULLuv4i32 2834 UINT64_C(4085255168), // VMULLuv8i16 2835 UINT64_C(236980736), // VMULS 2836 UINT64_C(4076866832), // VMULfd 2837 UINT64_C(4076866896), // VMULfq 2838 UINT64_C(4077915408), // VMULhd 2839 UINT64_C(4077915472), // VMULhq 2840 UINT64_C(4076865808), // VMULpd 2841 UINT64_C(4076865872), // VMULpq 2842 UINT64_C(4070574400), // VMULslfd 2843 UINT64_C(4087351616), // VMULslfq 2844 UINT64_C(4069525824), // VMULslhd 2845 UINT64_C(4086303040), // VMULslhq 2846 UINT64_C(4070574144), // VMULslv2i32 2847 UINT64_C(4069525568), // VMULslv4i16 2848 UINT64_C(4087351360), // VMULslv4i32 2849 UINT64_C(4086302784), // VMULslv8i16 2850 UINT64_C(4060088656), // VMULv16i8 2851 UINT64_C(4062185744), // VMULv2i32 2852 UINT64_C(4061137168), // VMULv4i16 2853 UINT64_C(4062185808), // VMULv4i32 2854 UINT64_C(4061137232), // VMULv8i16 2855 UINT64_C(4060088592), // VMULv8i8 2856 UINT64_C(4088399232), // VMVNd 2857 UINT64_C(4088399296), // VMVNq 2858 UINT64_C(4068474928), // VMVNv2i32 2859 UINT64_C(4068476976), // VMVNv4i16 2860 UINT64_C(4068474992), // VMVNv4i32 2861 UINT64_C(4068477040), // VMVNv8i16 2862 UINT64_C(246483776), // VNEGD 2863 UINT64_C(246483264), // VNEGH 2864 UINT64_C(246483520), // VNEGS 2865 UINT64_C(4088989632), // VNEGf32q 2866 UINT64_C(4088989568), // VNEGfd 2867 UINT64_C(4088727424), // VNEGhd 2868 UINT64_C(4088727488), // VNEGhq 2869 UINT64_C(4088726400), // VNEGs16d 2870 UINT64_C(4088726464), // VNEGs16q 2871 UINT64_C(4088988544), // VNEGs32d 2872 UINT64_C(4088988608), // VNEGs32q 2873 UINT64_C(4088464256), // VNEGs8d 2874 UINT64_C(4088464320), // VNEGs8q 2875 UINT64_C(235932480), // VNMLAD 2876 UINT64_C(235931968), // VNMLAH 2877 UINT64_C(235932224), // VNMLAS 2878 UINT64_C(235932416), // VNMLSD 2879 UINT64_C(235931904), // VNMLSH 2880 UINT64_C(235932160), // VNMLSS 2881 UINT64_C(236981056), // VNMULD 2882 UINT64_C(236980544), // VNMULH 2883 UINT64_C(236980800), // VNMULS 2884 UINT64_C(4063232272), // VORNd 2885 UINT64_C(4063232336), // VORNq 2886 UINT64_C(4062183696), // VORRd 2887 UINT64_C(4068475152), // VORRiv2i32 2888 UINT64_C(4068477200), // VORRiv4i16 2889 UINT64_C(4068475216), // VORRiv4i32 2890 UINT64_C(4068477264), // VORRiv8i16 2891 UINT64_C(4062183760), // VORRq 2892 UINT64_C(4088399424), // VPADALsv16i8 2893 UINT64_C(4088923648), // VPADALsv2i32 2894 UINT64_C(4088661504), // VPADALsv4i16 2895 UINT64_C(4088923712), // VPADALsv4i32 2896 UINT64_C(4088661568), // VPADALsv8i16 2897 UINT64_C(4088399360), // VPADALsv8i8 2898 UINT64_C(4088399552), // VPADALuv16i8 2899 UINT64_C(4088923776), // VPADALuv2i32 2900 UINT64_C(4088661632), // VPADALuv4i16 2901 UINT64_C(4088923840), // VPADALuv4i32 2902 UINT64_C(4088661696), // VPADALuv8i16 2903 UINT64_C(4088399488), // VPADALuv8i8 2904 UINT64_C(4088398400), // VPADDLsv16i8 2905 UINT64_C(4088922624), // VPADDLsv2i32 2906 UINT64_C(4088660480), // VPADDLsv4i16 2907 UINT64_C(4088922688), // VPADDLsv4i32 2908 UINT64_C(4088660544), // VPADDLsv8i16 2909 UINT64_C(4088398336), // VPADDLsv8i8 2910 UINT64_C(4088398528), // VPADDLuv16i8 2911 UINT64_C(4088922752), // VPADDLuv2i32 2912 UINT64_C(4088660608), // VPADDLuv4i16 2913 UINT64_C(4088922816), // VPADDLuv4i32 2914 UINT64_C(4088660672), // VPADDLuv8i16 2915 UINT64_C(4088398464), // VPADDLuv8i8 2916 UINT64_C(4076866816), // VPADDf 2917 UINT64_C(4077915392), // VPADDh 2918 UINT64_C(4061137680), // VPADDi16 2919 UINT64_C(4062186256), // VPADDi32 2920 UINT64_C(4060089104), // VPADDi8 2921 UINT64_C(4076867328), // VPMAXf 2922 UINT64_C(4077915904), // VPMAXh 2923 UINT64_C(4061137408), // VPMAXs16 2924 UINT64_C(4062185984), // VPMAXs32 2925 UINT64_C(4060088832), // VPMAXs8 2926 UINT64_C(4077914624), // VPMAXu16 2927 UINT64_C(4078963200), // VPMAXu32 2928 UINT64_C(4076866048), // VPMAXu8 2929 UINT64_C(4078964480), // VPMINf 2930 UINT64_C(4080013056), // VPMINh 2931 UINT64_C(4061137424), // VPMINs16 2932 UINT64_C(4062186000), // VPMINs32 2933 UINT64_C(4060088848), // VPMINs8 2934 UINT64_C(4077914640), // VPMINu16 2935 UINT64_C(4078963216), // VPMINu32 2936 UINT64_C(4076866064), // VPMINu8 2937 UINT64_C(4088399680), // VQABSv16i8 2938 UINT64_C(4088923904), // VQABSv2i32 2939 UINT64_C(4088661760), // VQABSv4i16 2940 UINT64_C(4088923968), // VQABSv4i32 2941 UINT64_C(4088661824), // VQABSv8i16 2942 UINT64_C(4088399616), // VQABSv8i8 2943 UINT64_C(4060086352), // VQADDsv16i8 2944 UINT64_C(4063232016), // VQADDsv1i64 2945 UINT64_C(4062183440), // VQADDsv2i32 2946 UINT64_C(4063232080), // VQADDsv2i64 2947 UINT64_C(4061134864), // VQADDsv4i16 2948 UINT64_C(4062183504), // VQADDsv4i32 2949 UINT64_C(4061134928), // VQADDsv8i16 2950 UINT64_C(4060086288), // VQADDsv8i8 2951 UINT64_C(4076863568), // VQADDuv16i8 2952 UINT64_C(4080009232), // VQADDuv1i64 2953 UINT64_C(4078960656), // VQADDuv2i32 2954 UINT64_C(4080009296), // VQADDuv2i64 2955 UINT64_C(4077912080), // VQADDuv4i16 2956 UINT64_C(4078960720), // VQADDuv4i32 2957 UINT64_C(4077912144), // VQADDuv8i16 2958 UINT64_C(4076863504), // VQADDuv8i8 2959 UINT64_C(4070572864), // VQDMLALslv2i32 2960 UINT64_C(4069524288), // VQDMLALslv4i16 2961 UINT64_C(4070574336), // VQDMLALv2i64 2962 UINT64_C(4069525760), // VQDMLALv4i32 2963 UINT64_C(4070573888), // VQDMLSLslv2i32 2964 UINT64_C(4069525312), // VQDMLSLslv4i16 2965 UINT64_C(4070574848), // VQDMLSLv2i64 2966 UINT64_C(4069526272), // VQDMLSLv4i32 2967 UINT64_C(4070575168), // VQDMULHslv2i32 2968 UINT64_C(4069526592), // VQDMULHslv4i16 2969 UINT64_C(4087352384), // VQDMULHslv4i32 2970 UINT64_C(4086303808), // VQDMULHslv8i16 2971 UINT64_C(4062186240), // VQDMULHv2i32 2972 UINT64_C(4061137664), // VQDMULHv4i16 2973 UINT64_C(4062186304), // VQDMULHv4i32 2974 UINT64_C(4061137728), // VQDMULHv8i16 2975 UINT64_C(4070574912), // VQDMULLslv2i32 2976 UINT64_C(4069526336), // VQDMULLslv4i16 2977 UINT64_C(4070575360), // VQDMULLv2i64 2978 UINT64_C(4069526784), // VQDMULLv4i32 2979 UINT64_C(4089053760), // VQMOVNsuv2i32 2980 UINT64_C(4088791616), // VQMOVNsuv4i16 2981 UINT64_C(4088529472), // VQMOVNsuv8i8 2982 UINT64_C(4089053824), // VQMOVNsv2i32 2983 UINT64_C(4088791680), // VQMOVNsv4i16 2984 UINT64_C(4088529536), // VQMOVNsv8i8 2985 UINT64_C(4089053888), // VQMOVNuv2i32 2986 UINT64_C(4088791744), // VQMOVNuv4i16 2987 UINT64_C(4088529600), // VQMOVNuv8i8 2988 UINT64_C(4088399808), // VQNEGv16i8 2989 UINT64_C(4088924032), // VQNEGv2i32 2990 UINT64_C(4088661888), // VQNEGv4i16 2991 UINT64_C(4088924096), // VQNEGv4i32 2992 UINT64_C(4088661952), // VQNEGv8i16 2993 UINT64_C(4088399744), // VQNEGv8i8 2994 UINT64_C(4070575680), // VQRDMLAHslv2i32 2995 UINT64_C(4069527104), // VQRDMLAHslv4i16 2996 UINT64_C(4087352896), // VQRDMLAHslv4i32 2997 UINT64_C(4086304320), // VQRDMLAHslv8i16 2998 UINT64_C(4078963472), // VQRDMLAHv2i32 2999 UINT64_C(4077914896), // VQRDMLAHv4i16 3000 UINT64_C(4078963536), // VQRDMLAHv4i32 3001 UINT64_C(4077914960), // VQRDMLAHv8i16 3002 UINT64_C(4070575936), // VQRDMLSHslv2i32 3003 UINT64_C(4069527360), // VQRDMLSHslv4i16 3004 UINT64_C(4087353152), // VQRDMLSHslv4i32 3005 UINT64_C(4086304576), // VQRDMLSHslv8i16 3006 UINT64_C(4078963728), // VQRDMLSHv2i32 3007 UINT64_C(4077915152), // VQRDMLSHv4i16 3008 UINT64_C(4078963792), // VQRDMLSHv4i32 3009 UINT64_C(4077915216), // VQRDMLSHv8i16 3010 UINT64_C(4070575424), // VQRDMULHslv2i32 3011 UINT64_C(4069526848), // VQRDMULHslv4i16 3012 UINT64_C(4087352640), // VQRDMULHslv4i32 3013 UINT64_C(4086304064), // VQRDMULHslv8i16 3014 UINT64_C(4078963456), // VQRDMULHv2i32 3015 UINT64_C(4077914880), // VQRDMULHv4i16 3016 UINT64_C(4078963520), // VQRDMULHv4i32 3017 UINT64_C(4077914944), // VQRDMULHv8i16 3018 UINT64_C(4060087632), // VQRSHLsv16i8 3019 UINT64_C(4063233296), // VQRSHLsv1i64 3020 UINT64_C(4062184720), // VQRSHLsv2i32 3021 UINT64_C(4063233360), // VQRSHLsv2i64 3022 UINT64_C(4061136144), // VQRSHLsv4i16 3023 UINT64_C(4062184784), // VQRSHLsv4i32 3024 UINT64_C(4061136208), // VQRSHLsv8i16 3025 UINT64_C(4060087568), // VQRSHLsv8i8 3026 UINT64_C(4076864848), // VQRSHLuv16i8 3027 UINT64_C(4080010512), // VQRSHLuv1i64 3028 UINT64_C(4078961936), // VQRSHLuv2i32 3029 UINT64_C(4080010576), // VQRSHLuv2i64 3030 UINT64_C(4077913360), // VQRSHLuv4i16 3031 UINT64_C(4078962000), // VQRSHLuv4i32 3032 UINT64_C(4077913424), // VQRSHLuv8i16 3033 UINT64_C(4076864784), // VQRSHLuv8i8 3034 UINT64_C(4070574416), // VQRSHRNsv2i32 3035 UINT64_C(4069525840), // VQRSHRNsv4i16 3036 UINT64_C(4069001552), // VQRSHRNsv8i8 3037 UINT64_C(4087351632), // VQRSHRNuv2i32 3038 UINT64_C(4086303056), // VQRSHRNuv4i16 3039 UINT64_C(4085778768), // VQRSHRNuv8i8 3040 UINT64_C(4087351376), // VQRSHRUNv2i32 3041 UINT64_C(4086302800), // VQRSHRUNv4i16 3042 UINT64_C(4085778512), // VQRSHRUNv8i8 3043 UINT64_C(4069001040), // VQSHLsiv16i8 3044 UINT64_C(4068476816), // VQSHLsiv1i64 3045 UINT64_C(4070573840), // VQSHLsiv2i32 3046 UINT64_C(4068476880), // VQSHLsiv2i64 3047 UINT64_C(4069525264), // VQSHLsiv4i16 3048 UINT64_C(4070573904), // VQSHLsiv4i32 3049 UINT64_C(4069525328), // VQSHLsiv8i16 3050 UINT64_C(4069000976), // VQSHLsiv8i8 3051 UINT64_C(4085778000), // VQSHLsuv16i8 3052 UINT64_C(4085253776), // VQSHLsuv1i64 3053 UINT64_C(4087350800), // VQSHLsuv2i32 3054 UINT64_C(4085253840), // VQSHLsuv2i64 3055 UINT64_C(4086302224), // VQSHLsuv4i16 3056 UINT64_C(4087350864), // VQSHLsuv4i32 3057 UINT64_C(4086302288), // VQSHLsuv8i16 3058 UINT64_C(4085777936), // VQSHLsuv8i8 3059 UINT64_C(4060087376), // VQSHLsv16i8 3060 UINT64_C(4063233040), // VQSHLsv1i64 3061 UINT64_C(4062184464), // VQSHLsv2i32 3062 UINT64_C(4063233104), // VQSHLsv2i64 3063 UINT64_C(4061135888), // VQSHLsv4i16 3064 UINT64_C(4062184528), // VQSHLsv4i32 3065 UINT64_C(4061135952), // VQSHLsv8i16 3066 UINT64_C(4060087312), // VQSHLsv8i8 3067 UINT64_C(4085778256), // VQSHLuiv16i8 3068 UINT64_C(4085254032), // VQSHLuiv1i64 3069 UINT64_C(4087351056), // VQSHLuiv2i32 3070 UINT64_C(4085254096), // VQSHLuiv2i64 3071 UINT64_C(4086302480), // VQSHLuiv4i16 3072 UINT64_C(4087351120), // VQSHLuiv4i32 3073 UINT64_C(4086302544), // VQSHLuiv8i16 3074 UINT64_C(4085778192), // VQSHLuiv8i8 3075 UINT64_C(4076864592), // VQSHLuv16i8 3076 UINT64_C(4080010256), // VQSHLuv1i64 3077 UINT64_C(4078961680), // VQSHLuv2i32 3078 UINT64_C(4080010320), // VQSHLuv2i64 3079 UINT64_C(4077913104), // VQSHLuv4i16 3080 UINT64_C(4078961744), // VQSHLuv4i32 3081 UINT64_C(4077913168), // VQSHLuv8i16 3082 UINT64_C(4076864528), // VQSHLuv8i8 3083 UINT64_C(4070574352), // VQSHRNsv2i32 3084 UINT64_C(4069525776), // VQSHRNsv4i16 3085 UINT64_C(4069001488), // VQSHRNsv8i8 3086 UINT64_C(4087351568), // VQSHRNuv2i32 3087 UINT64_C(4086302992), // VQSHRNuv4i16 3088 UINT64_C(4085778704), // VQSHRNuv8i8 3089 UINT64_C(4087351312), // VQSHRUNv2i32 3090 UINT64_C(4086302736), // VQSHRUNv4i16 3091 UINT64_C(4085778448), // VQSHRUNv8i8 3092 UINT64_C(4060086864), // VQSUBsv16i8 3093 UINT64_C(4063232528), // VQSUBsv1i64 3094 UINT64_C(4062183952), // VQSUBsv2i32 3095 UINT64_C(4063232592), // VQSUBsv2i64 3096 UINT64_C(4061135376), // VQSUBsv4i16 3097 UINT64_C(4062184016), // VQSUBsv4i32 3098 UINT64_C(4061135440), // VQSUBsv8i16 3099 UINT64_C(4060086800), // VQSUBsv8i8 3100 UINT64_C(4076864080), // VQSUBuv16i8 3101 UINT64_C(4080009744), // VQSUBuv1i64 3102 UINT64_C(4078961168), // VQSUBuv2i32 3103 UINT64_C(4080009808), // VQSUBuv2i64 3104 UINT64_C(4077912592), // VQSUBuv4i16 3105 UINT64_C(4078961232), // VQSUBuv4i32 3106 UINT64_C(4077912656), // VQSUBuv8i16 3107 UINT64_C(4076864016), // VQSUBuv8i8 3108 UINT64_C(4087350272), // VRADDHNv2i32 3109 UINT64_C(4086301696), // VRADDHNv4i16 3110 UINT64_C(4085253120), // VRADDHNv8i8 3111 UINT64_C(4089119744), // VRECPEd 3112 UINT64_C(4089120000), // VRECPEfd 3113 UINT64_C(4089120064), // VRECPEfq 3114 UINT64_C(4088857856), // VRECPEhd 3115 UINT64_C(4088857920), // VRECPEhq 3116 UINT64_C(4089119808), // VRECPEq 3117 UINT64_C(4060090128), // VRECPSfd 3118 UINT64_C(4060090192), // VRECPSfq 3119 UINT64_C(4061138704), // VRECPShd 3120 UINT64_C(4061138768), // VRECPShq 3121 UINT64_C(4088398080), // VREV16d8 3122 UINT64_C(4088398144), // VREV16q8 3123 UINT64_C(4088660096), // VREV32d16 3124 UINT64_C(4088397952), // VREV32d8 3125 UINT64_C(4088660160), // VREV32q16 3126 UINT64_C(4088398016), // VREV32q8 3127 UINT64_C(4088659968), // VREV64d16 3128 UINT64_C(4088922112), // VREV64d32 3129 UINT64_C(4088397824), // VREV64d8 3130 UINT64_C(4088660032), // VREV64q16 3131 UINT64_C(4088922176), // VREV64q32 3132 UINT64_C(4088397888), // VREV64q8 3133 UINT64_C(4060086592), // VRHADDsv16i8 3134 UINT64_C(4062183680), // VRHADDsv2i32 3135 UINT64_C(4061135104), // VRHADDsv4i16 3136 UINT64_C(4062183744), // VRHADDsv4i32 3137 UINT64_C(4061135168), // VRHADDsv8i16 3138 UINT64_C(4060086528), // VRHADDsv8i8 3139 UINT64_C(4076863808), // VRHADDuv16i8 3140 UINT64_C(4078960896), // VRHADDuv2i32 3141 UINT64_C(4077912320), // VRHADDuv4i16 3142 UINT64_C(4078960960), // VRHADDuv4i32 3143 UINT64_C(4077912384), // VRHADDuv8i16 3144 UINT64_C(4076863744), // VRHADDuv8i8 3145 UINT64_C(4273474368), // VRINTAD 3146 UINT64_C(4273473856), // VRINTAH 3147 UINT64_C(4089054464), // VRINTANDf 3148 UINT64_C(4088792320), // VRINTANDh 3149 UINT64_C(4089054528), // VRINTANQf 3150 UINT64_C(4088792384), // VRINTANQh 3151 UINT64_C(4273474112), // VRINTAS 3152 UINT64_C(4273670976), // VRINTMD 3153 UINT64_C(4273670464), // VRINTMH 3154 UINT64_C(4089054848), // VRINTMNDf 3155 UINT64_C(4088792704), // VRINTMNDh 3156 UINT64_C(4089054912), // VRINTMNQf 3157 UINT64_C(4088792768), // VRINTMNQh 3158 UINT64_C(4273670720), // VRINTMS 3159 UINT64_C(4273539904), // VRINTND 3160 UINT64_C(4273539392), // VRINTNH 3161 UINT64_C(4089054208), // VRINTNNDf 3162 UINT64_C(4088792064), // VRINTNNDh 3163 UINT64_C(4089054272), // VRINTNNQf 3164 UINT64_C(4088792128), // VRINTNNQh 3165 UINT64_C(4273539648), // VRINTNS 3166 UINT64_C(4273605440), // VRINTPD 3167 UINT64_C(4273604928), // VRINTPH 3168 UINT64_C(4089055104), // VRINTPNDf 3169 UINT64_C(4088792960), // VRINTPNDh 3170 UINT64_C(4089055168), // VRINTPNQf 3171 UINT64_C(4088793024), // VRINTPNQh 3172 UINT64_C(4273605184), // VRINTPS 3173 UINT64_C(246811456), // VRINTRD 3174 UINT64_C(246810944), // VRINTRH 3175 UINT64_C(246811200), // VRINTRS 3176 UINT64_C(246876992), // VRINTXD 3177 UINT64_C(246876480), // VRINTXH 3178 UINT64_C(4089054336), // VRINTXNDf 3179 UINT64_C(4088792192), // VRINTXNDh 3180 UINT64_C(4089054400), // VRINTXNQf 3181 UINT64_C(4088792256), // VRINTXNQh 3182 UINT64_C(246876736), // VRINTXS 3183 UINT64_C(246811584), // VRINTZD 3184 UINT64_C(246811072), // VRINTZH 3185 UINT64_C(4089054592), // VRINTZNDf 3186 UINT64_C(4088792448), // VRINTZNDh 3187 UINT64_C(4089054656), // VRINTZNQf 3188 UINT64_C(4088792512), // VRINTZNQh 3189 UINT64_C(246811328), // VRINTZS 3190 UINT64_C(4060087616), // VRSHLsv16i8 3191 UINT64_C(4063233280), // VRSHLsv1i64 3192 UINT64_C(4062184704), // VRSHLsv2i32 3193 UINT64_C(4063233344), // VRSHLsv2i64 3194 UINT64_C(4061136128), // VRSHLsv4i16 3195 UINT64_C(4062184768), // VRSHLsv4i32 3196 UINT64_C(4061136192), // VRSHLsv8i16 3197 UINT64_C(4060087552), // VRSHLsv8i8 3198 UINT64_C(4076864832), // VRSHLuv16i8 3199 UINT64_C(4080010496), // VRSHLuv1i64 3200 UINT64_C(4078961920), // VRSHLuv2i32 3201 UINT64_C(4080010560), // VRSHLuv2i64 3202 UINT64_C(4077913344), // VRSHLuv4i16 3203 UINT64_C(4078961984), // VRSHLuv4i32 3204 UINT64_C(4077913408), // VRSHLuv8i16 3205 UINT64_C(4076864768), // VRSHLuv8i8 3206 UINT64_C(4070574160), // VRSHRNv2i32 3207 UINT64_C(4069525584), // VRSHRNv4i16 3208 UINT64_C(4069001296), // VRSHRNv8i8 3209 UINT64_C(4068999760), // VRSHRsv16i8 3210 UINT64_C(4068475536), // VRSHRsv1i64 3211 UINT64_C(4070572560), // VRSHRsv2i32 3212 UINT64_C(4068475600), // VRSHRsv2i64 3213 UINT64_C(4069523984), // VRSHRsv4i16 3214 UINT64_C(4070572624), // VRSHRsv4i32 3215 UINT64_C(4069524048), // VRSHRsv8i16 3216 UINT64_C(4068999696), // VRSHRsv8i8 3217 UINT64_C(4085776976), // VRSHRuv16i8 3218 UINT64_C(4085252752), // VRSHRuv1i64 3219 UINT64_C(4087349776), // VRSHRuv2i32 3220 UINT64_C(4085252816), // VRSHRuv2i64 3221 UINT64_C(4086301200), // VRSHRuv4i16 3222 UINT64_C(4087349840), // VRSHRuv4i32 3223 UINT64_C(4086301264), // VRSHRuv8i16 3224 UINT64_C(4085776912), // VRSHRuv8i8 3225 UINT64_C(4089119872), // VRSQRTEd 3226 UINT64_C(4089120128), // VRSQRTEfd 3227 UINT64_C(4089120192), // VRSQRTEfq 3228 UINT64_C(4088857984), // VRSQRTEhd 3229 UINT64_C(4088858048), // VRSQRTEhq 3230 UINT64_C(4089119936), // VRSQRTEq 3231 UINT64_C(4062187280), // VRSQRTSfd 3232 UINT64_C(4062187344), // VRSQRTSfq 3233 UINT64_C(4063235856), // VRSQRTShd 3234 UINT64_C(4063235920), // VRSQRTShq 3235 UINT64_C(4069000016), // VRSRAsv16i8 3236 UINT64_C(4068475792), // VRSRAsv1i64 3237 UINT64_C(4070572816), // VRSRAsv2i32 3238 UINT64_C(4068475856), // VRSRAsv2i64 3239 UINT64_C(4069524240), // VRSRAsv4i16 3240 UINT64_C(4070572880), // VRSRAsv4i32 3241 UINT64_C(4069524304), // VRSRAsv8i16 3242 UINT64_C(4068999952), // VRSRAsv8i8 3243 UINT64_C(4085777232), // VRSRAuv16i8 3244 UINT64_C(4085253008), // VRSRAuv1i64 3245 UINT64_C(4087350032), // VRSRAuv2i32 3246 UINT64_C(4085253072), // VRSRAuv2i64 3247 UINT64_C(4086301456), // VRSRAuv4i16 3248 UINT64_C(4087350096), // VRSRAuv4i32 3249 UINT64_C(4086301520), // VRSRAuv8i16 3250 UINT64_C(4085777168), // VRSRAuv8i8 3251 UINT64_C(4087350784), // VRSUBHNv2i32 3252 UINT64_C(4086302208), // VRSUBHNv4i16 3253 UINT64_C(4085253632), // VRSUBHNv8i8 3254 UINT64_C(3969846016), // VSCCLRMD 3255 UINT64_C(3969845760), // VSCCLRMS 3256 UINT64_C(4229958912), // VSDOTD 3257 UINT64_C(4263513344), // VSDOTDI 3258 UINT64_C(4229958976), // VSDOTQ 3259 UINT64_C(4263513408), // VSDOTQI 3260 UINT64_C(4261415680), // VSELEQD 3261 UINT64_C(4261415168), // VSELEQH 3262 UINT64_C(4261415424), // VSELEQS 3263 UINT64_C(4263512832), // VSELGED 3264 UINT64_C(4263512320), // VSELGEH 3265 UINT64_C(4263512576), // VSELGES 3266 UINT64_C(4264561408), // VSELGTD 3267 UINT64_C(4264560896), // VSELGTH 3268 UINT64_C(4264561152), // VSELGTS 3269 UINT64_C(4262464256), // VSELVSD 3270 UINT64_C(4262463744), // VSELVSH 3271 UINT64_C(4262464000), // VSELVSS 3272 UINT64_C(234883888), // VSETLNi16 3273 UINT64_C(234883856), // VSETLNi32 3274 UINT64_C(239078160), // VSETLNi8 3275 UINT64_C(4088791808), // VSHLLi16 3276 UINT64_C(4089053952), // VSHLLi32 3277 UINT64_C(4088529664), // VSHLLi8 3278 UINT64_C(4070574608), // VSHLLsv2i64 3279 UINT64_C(4069526032), // VSHLLsv4i32 3280 UINT64_C(4069001744), // VSHLLsv8i16 3281 UINT64_C(4087351824), // VSHLLuv2i64 3282 UINT64_C(4086303248), // VSHLLuv4i32 3283 UINT64_C(4085778960), // VSHLLuv8i16 3284 UINT64_C(4069000528), // VSHLiv16i8 3285 UINT64_C(4068476304), // VSHLiv1i64 3286 UINT64_C(4070573328), // VSHLiv2i32 3287 UINT64_C(4068476368), // VSHLiv2i64 3288 UINT64_C(4069524752), // VSHLiv4i16 3289 UINT64_C(4070573392), // VSHLiv4i32 3290 UINT64_C(4069524816), // VSHLiv8i16 3291 UINT64_C(4069000464), // VSHLiv8i8 3292 UINT64_C(4060087360), // VSHLsv16i8 3293 UINT64_C(4063233024), // VSHLsv1i64 3294 UINT64_C(4062184448), // VSHLsv2i32 3295 UINT64_C(4063233088), // VSHLsv2i64 3296 UINT64_C(4061135872), // VSHLsv4i16 3297 UINT64_C(4062184512), // VSHLsv4i32 3298 UINT64_C(4061135936), // VSHLsv8i16 3299 UINT64_C(4060087296), // VSHLsv8i8 3300 UINT64_C(4076864576), // VSHLuv16i8 3301 UINT64_C(4080010240), // VSHLuv1i64 3302 UINT64_C(4078961664), // VSHLuv2i32 3303 UINT64_C(4080010304), // VSHLuv2i64 3304 UINT64_C(4077913088), // VSHLuv4i16 3305 UINT64_C(4078961728), // VSHLuv4i32 3306 UINT64_C(4077913152), // VSHLuv8i16 3307 UINT64_C(4076864512), // VSHLuv8i8 3308 UINT64_C(4070574096), // VSHRNv2i32 3309 UINT64_C(4069525520), // VSHRNv4i16 3310 UINT64_C(4069001232), // VSHRNv8i8 3311 UINT64_C(4068999248), // VSHRsv16i8 3312 UINT64_C(4068475024), // VSHRsv1i64 3313 UINT64_C(4070572048), // VSHRsv2i32 3314 UINT64_C(4068475088), // VSHRsv2i64 3315 UINT64_C(4069523472), // VSHRsv4i16 3316 UINT64_C(4070572112), // VSHRsv4i32 3317 UINT64_C(4069523536), // VSHRsv8i16 3318 UINT64_C(4068999184), // VSHRsv8i8 3319 UINT64_C(4085776464), // VSHRuv16i8 3320 UINT64_C(4085252240), // VSHRuv1i64 3321 UINT64_C(4087349264), // VSHRuv2i32 3322 UINT64_C(4085252304), // VSHRuv2i64 3323 UINT64_C(4086300688), // VSHRuv4i16 3324 UINT64_C(4087349328), // VSHRuv4i32 3325 UINT64_C(4086300752), // VSHRuv8i16 3326 UINT64_C(4085776400), // VSHRuv8i8 3327 UINT64_C(247073600), // VSHTOD 3328 UINT64_C(247073088), // VSHTOH 3329 UINT64_C(247073344), // VSHTOS 3330 UINT64_C(246942656), // VSITOD 3331 UINT64_C(246942144), // VSITOH 3332 UINT64_C(246942400), // VSITOS 3333 UINT64_C(4085777744), // VSLIv16i8 3334 UINT64_C(4085253520), // VSLIv1i64 3335 UINT64_C(4087350544), // VSLIv2i32 3336 UINT64_C(4085253584), // VSLIv2i64 3337 UINT64_C(4086301968), // VSLIv4i16 3338 UINT64_C(4087350608), // VSLIv4i32 3339 UINT64_C(4086302032), // VSLIv8i16 3340 UINT64_C(4085777680), // VSLIv8i8 3341 UINT64_C(247073728), // VSLTOD 3342 UINT64_C(247073216), // VSLTOH 3343 UINT64_C(247073472), // VSLTOS 3344 UINT64_C(246483904), // VSQRTD 3345 UINT64_C(246483392), // VSQRTH 3346 UINT64_C(246483648), // VSQRTS 3347 UINT64_C(4068999504), // VSRAsv16i8 3348 UINT64_C(4068475280), // VSRAsv1i64 3349 UINT64_C(4070572304), // VSRAsv2i32 3350 UINT64_C(4068475344), // VSRAsv2i64 3351 UINT64_C(4069523728), // VSRAsv4i16 3352 UINT64_C(4070572368), // VSRAsv4i32 3353 UINT64_C(4069523792), // VSRAsv8i16 3354 UINT64_C(4068999440), // VSRAsv8i8 3355 UINT64_C(4085776720), // VSRAuv16i8 3356 UINT64_C(4085252496), // VSRAuv1i64 3357 UINT64_C(4087349520), // VSRAuv2i32 3358 UINT64_C(4085252560), // VSRAuv2i64 3359 UINT64_C(4086300944), // VSRAuv4i16 3360 UINT64_C(4087349584), // VSRAuv4i32 3361 UINT64_C(4086301008), // VSRAuv8i16 3362 UINT64_C(4085776656), // VSRAuv8i8 3363 UINT64_C(4085777488), // VSRIv16i8 3364 UINT64_C(4085253264), // VSRIv1i64 3365 UINT64_C(4087350288), // VSRIv2i32 3366 UINT64_C(4085253328), // VSRIv2i64 3367 UINT64_C(4086301712), // VSRIv4i16 3368 UINT64_C(4087350352), // VSRIv4i32 3369 UINT64_C(4086301776), // VSRIv8i16 3370 UINT64_C(4085777424), // VSRIv8i8 3371 UINT64_C(4102030351), // VST1LNd16 3372 UINT64_C(4102030336), // VST1LNd16_UPD 3373 UINT64_C(4102031375), // VST1LNd32 3374 UINT64_C(4102031360), // VST1LNd32_UPD 3375 UINT64_C(4102029327), // VST1LNd8 3376 UINT64_C(4102029312), // VST1LNd8_UPD 3377 UINT64_C(0), // VST1LNq16Pseudo 3378 UINT64_C(0), // VST1LNq16Pseudo_UPD 3379 UINT64_C(0), // VST1LNq32Pseudo 3380 UINT64_C(0), // VST1LNq32Pseudo_UPD 3381 UINT64_C(0), // VST1LNq8Pseudo 3382 UINT64_C(0), // VST1LNq8Pseudo_UPD 3383 UINT64_C(4093642575), // VST1d16 3384 UINT64_C(4093641295), // VST1d16Q 3385 UINT64_C(0), // VST1d16QPseudo 3386 UINT64_C(4093641293), // VST1d16Qwb_fixed 3387 UINT64_C(4093641280), // VST1d16Qwb_register 3388 UINT64_C(4093642319), // VST1d16T 3389 UINT64_C(0), // VST1d16TPseudo 3390 UINT64_C(4093642317), // VST1d16Twb_fixed 3391 UINT64_C(4093642304), // VST1d16Twb_register 3392 UINT64_C(4093642573), // VST1d16wb_fixed 3393 UINT64_C(4093642560), // VST1d16wb_register 3394 UINT64_C(4093642639), // VST1d32 3395 UINT64_C(4093641359), // VST1d32Q 3396 UINT64_C(0), // VST1d32QPseudo 3397 UINT64_C(4093641357), // VST1d32Qwb_fixed 3398 UINT64_C(4093641344), // VST1d32Qwb_register 3399 UINT64_C(4093642383), // VST1d32T 3400 UINT64_C(0), // VST1d32TPseudo 3401 UINT64_C(4093642381), // VST1d32Twb_fixed 3402 UINT64_C(4093642368), // VST1d32Twb_register 3403 UINT64_C(4093642637), // VST1d32wb_fixed 3404 UINT64_C(4093642624), // VST1d32wb_register 3405 UINT64_C(4093642703), // VST1d64 3406 UINT64_C(4093641423), // VST1d64Q 3407 UINT64_C(0), // VST1d64QPseudo 3408 UINT64_C(0), // VST1d64QPseudoWB_fixed 3409 UINT64_C(0), // VST1d64QPseudoWB_register 3410 UINT64_C(4093641421), // VST1d64Qwb_fixed 3411 UINT64_C(4093641408), // VST1d64Qwb_register 3412 UINT64_C(4093642447), // VST1d64T 3413 UINT64_C(0), // VST1d64TPseudo 3414 UINT64_C(0), // VST1d64TPseudoWB_fixed 3415 UINT64_C(0), // VST1d64TPseudoWB_register 3416 UINT64_C(4093642445), // VST1d64Twb_fixed 3417 UINT64_C(4093642432), // VST1d64Twb_register 3418 UINT64_C(4093642701), // VST1d64wb_fixed 3419 UINT64_C(4093642688), // VST1d64wb_register 3420 UINT64_C(4093642511), // VST1d8 3421 UINT64_C(4093641231), // VST1d8Q 3422 UINT64_C(0), // VST1d8QPseudo 3423 UINT64_C(4093641229), // VST1d8Qwb_fixed 3424 UINT64_C(4093641216), // VST1d8Qwb_register 3425 UINT64_C(4093642255), // VST1d8T 3426 UINT64_C(0), // VST1d8TPseudo 3427 UINT64_C(4093642253), // VST1d8Twb_fixed 3428 UINT64_C(4093642240), // VST1d8Twb_register 3429 UINT64_C(4093642509), // VST1d8wb_fixed 3430 UINT64_C(4093642496), // VST1d8wb_register 3431 UINT64_C(4093643343), // VST1q16 3432 UINT64_C(0), // VST1q16HighQPseudo 3433 UINT64_C(0), // VST1q16HighTPseudo 3434 UINT64_C(0), // VST1q16LowQPseudo_UPD 3435 UINT64_C(0), // VST1q16LowTPseudo_UPD 3436 UINT64_C(4093643341), // VST1q16wb_fixed 3437 UINT64_C(4093643328), // VST1q16wb_register 3438 UINT64_C(4093643407), // VST1q32 3439 UINT64_C(0), // VST1q32HighQPseudo 3440 UINT64_C(0), // VST1q32HighTPseudo 3441 UINT64_C(0), // VST1q32LowQPseudo_UPD 3442 UINT64_C(0), // VST1q32LowTPseudo_UPD 3443 UINT64_C(4093643405), // VST1q32wb_fixed 3444 UINT64_C(4093643392), // VST1q32wb_register 3445 UINT64_C(4093643471), // VST1q64 3446 UINT64_C(0), // VST1q64HighQPseudo 3447 UINT64_C(0), // VST1q64HighTPseudo 3448 UINT64_C(0), // VST1q64LowQPseudo_UPD 3449 UINT64_C(0), // VST1q64LowTPseudo_UPD 3450 UINT64_C(4093643469), // VST1q64wb_fixed 3451 UINT64_C(4093643456), // VST1q64wb_register 3452 UINT64_C(4093643279), // VST1q8 3453 UINT64_C(0), // VST1q8HighQPseudo 3454 UINT64_C(0), // VST1q8HighTPseudo 3455 UINT64_C(0), // VST1q8LowQPseudo_UPD 3456 UINT64_C(0), // VST1q8LowTPseudo_UPD 3457 UINT64_C(4093643277), // VST1q8wb_fixed 3458 UINT64_C(4093643264), // VST1q8wb_register 3459 UINT64_C(4102030607), // VST2LNd16 3460 UINT64_C(0), // VST2LNd16Pseudo 3461 UINT64_C(0), // VST2LNd16Pseudo_UPD 3462 UINT64_C(4102030592), // VST2LNd16_UPD 3463 UINT64_C(4102031631), // VST2LNd32 3464 UINT64_C(0), // VST2LNd32Pseudo 3465 UINT64_C(0), // VST2LNd32Pseudo_UPD 3466 UINT64_C(4102031616), // VST2LNd32_UPD 3467 UINT64_C(4102029583), // VST2LNd8 3468 UINT64_C(0), // VST2LNd8Pseudo 3469 UINT64_C(0), // VST2LNd8Pseudo_UPD 3470 UINT64_C(4102029568), // VST2LNd8_UPD 3471 UINT64_C(4102030639), // VST2LNq16 3472 UINT64_C(0), // VST2LNq16Pseudo 3473 UINT64_C(0), // VST2LNq16Pseudo_UPD 3474 UINT64_C(4102030624), // VST2LNq16_UPD 3475 UINT64_C(4102031695), // VST2LNq32 3476 UINT64_C(0), // VST2LNq32Pseudo 3477 UINT64_C(0), // VST2LNq32Pseudo_UPD 3478 UINT64_C(4102031680), // VST2LNq32_UPD 3479 UINT64_C(4093643087), // VST2b16 3480 UINT64_C(4093643085), // VST2b16wb_fixed 3481 UINT64_C(4093643072), // VST2b16wb_register 3482 UINT64_C(4093643151), // VST2b32 3483 UINT64_C(4093643149), // VST2b32wb_fixed 3484 UINT64_C(4093643136), // VST2b32wb_register 3485 UINT64_C(4093643023), // VST2b8 3486 UINT64_C(4093643021), // VST2b8wb_fixed 3487 UINT64_C(4093643008), // VST2b8wb_register 3488 UINT64_C(4093642831), // VST2d16 3489 UINT64_C(4093642829), // VST2d16wb_fixed 3490 UINT64_C(4093642816), // VST2d16wb_register 3491 UINT64_C(4093642895), // VST2d32 3492 UINT64_C(4093642893), // VST2d32wb_fixed 3493 UINT64_C(4093642880), // VST2d32wb_register 3494 UINT64_C(4093642767), // VST2d8 3495 UINT64_C(4093642765), // VST2d8wb_fixed 3496 UINT64_C(4093642752), // VST2d8wb_register 3497 UINT64_C(4093641551), // VST2q16 3498 UINT64_C(0), // VST2q16Pseudo 3499 UINT64_C(0), // VST2q16PseudoWB_fixed 3500 UINT64_C(0), // VST2q16PseudoWB_register 3501 UINT64_C(4093641549), // VST2q16wb_fixed 3502 UINT64_C(4093641536), // VST2q16wb_register 3503 UINT64_C(4093641615), // VST2q32 3504 UINT64_C(0), // VST2q32Pseudo 3505 UINT64_C(0), // VST2q32PseudoWB_fixed 3506 UINT64_C(0), // VST2q32PseudoWB_register 3507 UINT64_C(4093641613), // VST2q32wb_fixed 3508 UINT64_C(4093641600), // VST2q32wb_register 3509 UINT64_C(4093641487), // VST2q8 3510 UINT64_C(0), // VST2q8Pseudo 3511 UINT64_C(0), // VST2q8PseudoWB_fixed 3512 UINT64_C(0), // VST2q8PseudoWB_register 3513 UINT64_C(4093641485), // VST2q8wb_fixed 3514 UINT64_C(4093641472), // VST2q8wb_register 3515 UINT64_C(4102030863), // VST3LNd16 3516 UINT64_C(0), // VST3LNd16Pseudo 3517 UINT64_C(0), // VST3LNd16Pseudo_UPD 3518 UINT64_C(4102030848), // VST3LNd16_UPD 3519 UINT64_C(4102031887), // VST3LNd32 3520 UINT64_C(0), // VST3LNd32Pseudo 3521 UINT64_C(0), // VST3LNd32Pseudo_UPD 3522 UINT64_C(4102031872), // VST3LNd32_UPD 3523 UINT64_C(4102029839), // VST3LNd8 3524 UINT64_C(0), // VST3LNd8Pseudo 3525 UINT64_C(0), // VST3LNd8Pseudo_UPD 3526 UINT64_C(4102029824), // VST3LNd8_UPD 3527 UINT64_C(4102030895), // VST3LNq16 3528 UINT64_C(0), // VST3LNq16Pseudo 3529 UINT64_C(0), // VST3LNq16Pseudo_UPD 3530 UINT64_C(4102030880), // VST3LNq16_UPD 3531 UINT64_C(4102031951), // VST3LNq32 3532 UINT64_C(0), // VST3LNq32Pseudo 3533 UINT64_C(0), // VST3LNq32Pseudo_UPD 3534 UINT64_C(4102031936), // VST3LNq32_UPD 3535 UINT64_C(4093641807), // VST3d16 3536 UINT64_C(0), // VST3d16Pseudo 3537 UINT64_C(0), // VST3d16Pseudo_UPD 3538 UINT64_C(4093641792), // VST3d16_UPD 3539 UINT64_C(4093641871), // VST3d32 3540 UINT64_C(0), // VST3d32Pseudo 3541 UINT64_C(0), // VST3d32Pseudo_UPD 3542 UINT64_C(4093641856), // VST3d32_UPD 3543 UINT64_C(4093641743), // VST3d8 3544 UINT64_C(0), // VST3d8Pseudo 3545 UINT64_C(0), // VST3d8Pseudo_UPD 3546 UINT64_C(4093641728), // VST3d8_UPD 3547 UINT64_C(4093642063), // VST3q16 3548 UINT64_C(0), // VST3q16Pseudo_UPD 3549 UINT64_C(4093642048), // VST3q16_UPD 3550 UINT64_C(0), // VST3q16oddPseudo 3551 UINT64_C(0), // VST3q16oddPseudo_UPD 3552 UINT64_C(4093642127), // VST3q32 3553 UINT64_C(0), // VST3q32Pseudo_UPD 3554 UINT64_C(4093642112), // VST3q32_UPD 3555 UINT64_C(0), // VST3q32oddPseudo 3556 UINT64_C(0), // VST3q32oddPseudo_UPD 3557 UINT64_C(4093641999), // VST3q8 3558 UINT64_C(0), // VST3q8Pseudo_UPD 3559 UINT64_C(4093641984), // VST3q8_UPD 3560 UINT64_C(0), // VST3q8oddPseudo 3561 UINT64_C(0), // VST3q8oddPseudo_UPD 3562 UINT64_C(4102031119), // VST4LNd16 3563 UINT64_C(0), // VST4LNd16Pseudo 3564 UINT64_C(0), // VST4LNd16Pseudo_UPD 3565 UINT64_C(4102031104), // VST4LNd16_UPD 3566 UINT64_C(4102032143), // VST4LNd32 3567 UINT64_C(0), // VST4LNd32Pseudo 3568 UINT64_C(0), // VST4LNd32Pseudo_UPD 3569 UINT64_C(4102032128), // VST4LNd32_UPD 3570 UINT64_C(4102030095), // VST4LNd8 3571 UINT64_C(0), // VST4LNd8Pseudo 3572 UINT64_C(0), // VST4LNd8Pseudo_UPD 3573 UINT64_C(4102030080), // VST4LNd8_UPD 3574 UINT64_C(4102031151), // VST4LNq16 3575 UINT64_C(0), // VST4LNq16Pseudo 3576 UINT64_C(0), // VST4LNq16Pseudo_UPD 3577 UINT64_C(4102031136), // VST4LNq16_UPD 3578 UINT64_C(4102032207), // VST4LNq32 3579 UINT64_C(0), // VST4LNq32Pseudo 3580 UINT64_C(0), // VST4LNq32Pseudo_UPD 3581 UINT64_C(4102032192), // VST4LNq32_UPD 3582 UINT64_C(4093640783), // VST4d16 3583 UINT64_C(0), // VST4d16Pseudo 3584 UINT64_C(0), // VST4d16Pseudo_UPD 3585 UINT64_C(4093640768), // VST4d16_UPD 3586 UINT64_C(4093640847), // VST4d32 3587 UINT64_C(0), // VST4d32Pseudo 3588 UINT64_C(0), // VST4d32Pseudo_UPD 3589 UINT64_C(4093640832), // VST4d32_UPD 3590 UINT64_C(4093640719), // VST4d8 3591 UINT64_C(0), // VST4d8Pseudo 3592 UINT64_C(0), // VST4d8Pseudo_UPD 3593 UINT64_C(4093640704), // VST4d8_UPD 3594 UINT64_C(4093641039), // VST4q16 3595 UINT64_C(0), // VST4q16Pseudo_UPD 3596 UINT64_C(4093641024), // VST4q16_UPD 3597 UINT64_C(0), // VST4q16oddPseudo 3598 UINT64_C(0), // VST4q16oddPseudo_UPD 3599 UINT64_C(4093641103), // VST4q32 3600 UINT64_C(0), // VST4q32Pseudo_UPD 3601 UINT64_C(4093641088), // VST4q32_UPD 3602 UINT64_C(0), // VST4q32oddPseudo 3603 UINT64_C(0), // VST4q32oddPseudo_UPD 3604 UINT64_C(4093640975), // VST4q8 3605 UINT64_C(0), // VST4q8Pseudo_UPD 3606 UINT64_C(4093640960), // VST4q8_UPD 3607 UINT64_C(0), // VST4q8oddPseudo 3608 UINT64_C(0), // VST4q8oddPseudo_UPD 3609 UINT64_C(220203776), // VSTMDDB_UPD 3610 UINT64_C(209718016), // VSTMDIA 3611 UINT64_C(211815168), // VSTMDIA_UPD 3612 UINT64_C(0), // VSTMQIA 3613 UINT64_C(220203520), // VSTMSDB_UPD 3614 UINT64_C(209717760), // VSTMSIA 3615 UINT64_C(211814912), // VSTMSIA_UPD 3616 UINT64_C(218106624), // VSTRD 3617 UINT64_C(218106112), // VSTRH 3618 UINT64_C(218106368), // VSTRS 3619 UINT64_C(222351232), // VSTR_FPCXTNS_off 3620 UINT64_C(207671168), // VSTR_FPCXTNS_post 3621 UINT64_C(224448384), // VSTR_FPCXTNS_pre 3622 UINT64_C(222359424), // VSTR_FPCXTS_off 3623 UINT64_C(207679360), // VSTR_FPCXTS_post 3624 UINT64_C(224456576), // VSTR_FPCXTS_pre 3625 UINT64_C(218124160), // VSTR_FPSCR_NZCVQC_off 3626 UINT64_C(203444096), // VSTR_FPSCR_NZCVQC_post 3627 UINT64_C(220221312), // VSTR_FPSCR_NZCVQC_pre 3628 UINT64_C(218115968), // VSTR_FPSCR_off 3629 UINT64_C(203435904), // VSTR_FPSCR_post 3630 UINT64_C(220213120), // VSTR_FPSCR_pre 3631 UINT64_C(222343040), // VSTR_P0_off 3632 UINT64_C(207662976), // VSTR_P0_post 3633 UINT64_C(224440192), // VSTR_P0_pre 3634 UINT64_C(222334848), // VSTR_VPR_off 3635 UINT64_C(207654784), // VSTR_VPR_post 3636 UINT64_C(224432000), // VSTR_VPR_pre 3637 UINT64_C(238029632), // VSUBD 3638 UINT64_C(238029120), // VSUBH 3639 UINT64_C(4070573568), // VSUBHNv2i32 3640 UINT64_C(4069524992), // VSUBHNv4i16 3641 UINT64_C(4068476416), // VSUBHNv8i8 3642 UINT64_C(4070572544), // VSUBLsv2i64 3643 UINT64_C(4069523968), // VSUBLsv4i32 3644 UINT64_C(4068475392), // VSUBLsv8i16 3645 UINT64_C(4087349760), // VSUBLuv2i64 3646 UINT64_C(4086301184), // VSUBLuv4i32 3647 UINT64_C(4085252608), // VSUBLuv8i16 3648 UINT64_C(238029376), // VSUBS 3649 UINT64_C(4070572800), // VSUBWsv2i64 3650 UINT64_C(4069524224), // VSUBWsv4i32 3651 UINT64_C(4068475648), // VSUBWsv8i16 3652 UINT64_C(4087350016), // VSUBWuv2i64 3653 UINT64_C(4086301440), // VSUBWuv4i32 3654 UINT64_C(4085252864), // VSUBWuv8i16 3655 UINT64_C(4062186752), // VSUBfd 3656 UINT64_C(4062186816), // VSUBfq 3657 UINT64_C(4063235328), // VSUBhd 3658 UINT64_C(4063235392), // VSUBhq 3659 UINT64_C(4076865600), // VSUBv16i8 3660 UINT64_C(4080011264), // VSUBv1i64 3661 UINT64_C(4078962688), // VSUBv2i32 3662 UINT64_C(4080011328), // VSUBv2i64 3663 UINT64_C(4077914112), // VSUBv4i16 3664 UINT64_C(4078962752), // VSUBv4i32 3665 UINT64_C(4077914176), // VSUBv8i16 3666 UINT64_C(4076865536), // VSUBv8i8 3667 UINT64_C(4088528896), // VSWPd 3668 UINT64_C(4088528960), // VSWPq 3669 UINT64_C(4088399872), // VTBL1 3670 UINT64_C(4088400128), // VTBL2 3671 UINT64_C(4088400384), // VTBL3 3672 UINT64_C(0), // VTBL3Pseudo 3673 UINT64_C(4088400640), // VTBL4 3674 UINT64_C(0), // VTBL4Pseudo 3675 UINT64_C(4088399936), // VTBX1 3676 UINT64_C(4088400192), // VTBX2 3677 UINT64_C(4088400448), // VTBX3 3678 UINT64_C(0), // VTBX3Pseudo 3679 UINT64_C(4088400704), // VTBX4 3680 UINT64_C(0), // VTBX4Pseudo 3681 UINT64_C(247335744), // VTOSHD 3682 UINT64_C(247335232), // VTOSHH 3683 UINT64_C(247335488), // VTOSHS 3684 UINT64_C(247270208), // VTOSIRD 3685 UINT64_C(247269696), // VTOSIRH 3686 UINT64_C(247269952), // VTOSIRS 3687 UINT64_C(247270336), // VTOSIZD 3688 UINT64_C(247269824), // VTOSIZH 3689 UINT64_C(247270080), // VTOSIZS 3690 UINT64_C(247335872), // VTOSLD 3691 UINT64_C(247335360), // VTOSLH 3692 UINT64_C(247335616), // VTOSLS 3693 UINT64_C(247401280), // VTOUHD 3694 UINT64_C(247400768), // VTOUHH 3695 UINT64_C(247401024), // VTOUHS 3696 UINT64_C(247204672), // VTOUIRD 3697 UINT64_C(247204160), // VTOUIRH 3698 UINT64_C(247204416), // VTOUIRS 3699 UINT64_C(247204800), // VTOUIZD 3700 UINT64_C(247204288), // VTOUIZH 3701 UINT64_C(247204544), // VTOUIZS 3702 UINT64_C(247401408), // VTOULD 3703 UINT64_C(247400896), // VTOULH 3704 UINT64_C(247401152), // VTOULS 3705 UINT64_C(4088791168), // VTRNd16 3706 UINT64_C(4089053312), // VTRNd32 3707 UINT64_C(4088529024), // VTRNd8 3708 UINT64_C(4088791232), // VTRNq16 3709 UINT64_C(4089053376), // VTRNq32 3710 UINT64_C(4088529088), // VTRNq8 3711 UINT64_C(4060088400), // VTSTv16i8 3712 UINT64_C(4062185488), // VTSTv2i32 3713 UINT64_C(4061136912), // VTSTv4i16 3714 UINT64_C(4062185552), // VTSTv4i32 3715 UINT64_C(4061136976), // VTSTv8i16 3716 UINT64_C(4060088336), // VTSTv8i8 3717 UINT64_C(4229958928), // VUDOTD 3718 UINT64_C(4263513360), // VUDOTDI 3719 UINT64_C(4229958992), // VUDOTQ 3720 UINT64_C(4263513424), // VUDOTQI 3721 UINT64_C(247139136), // VUHTOD 3722 UINT64_C(247138624), // VUHTOH 3723 UINT64_C(247138880), // VUHTOS 3724 UINT64_C(246942528), // VUITOD 3725 UINT64_C(246942016), // VUITOH 3726 UINT64_C(246942272), // VUITOS 3727 UINT64_C(247139264), // VULTOD 3728 UINT64_C(247138752), // VULTOH 3729 UINT64_C(247139008), // VULTOS 3730 UINT64_C(4088791296), // VUZPd16 3731 UINT64_C(4088529152), // VUZPd8 3732 UINT64_C(4088791360), // VUZPq16 3733 UINT64_C(4089053504), // VUZPq32 3734 UINT64_C(4088529216), // VUZPq8 3735 UINT64_C(4088791424), // VZIPd16 3736 UINT64_C(4088529280), // VZIPd8 3737 UINT64_C(4088791488), // VZIPq16 3738 UINT64_C(4089053632), // VZIPq32 3739 UINT64_C(4088529344), // VZIPq8 3740 UINT64_C(139460608), // sysLDMDA 3741 UINT64_C(141557760), // sysLDMDA_UPD 3742 UINT64_C(156237824), // sysLDMDB 3743 UINT64_C(158334976), // sysLDMDB_UPD 3744 UINT64_C(147849216), // sysLDMIA 3745 UINT64_C(149946368), // sysLDMIA_UPD 3746 UINT64_C(164626432), // sysLDMIB 3747 UINT64_C(166723584), // sysLDMIB_UPD 3748 UINT64_C(138412032), // sysSTMDA 3749 UINT64_C(140509184), // sysSTMDA_UPD 3750 UINT64_C(155189248), // sysSTMDB 3751 UINT64_C(157286400), // sysSTMDB_UPD 3752 UINT64_C(146800640), // sysSTMIA 3753 UINT64_C(148897792), // sysSTMIA_UPD 3754 UINT64_C(163577856), // sysSTMIB 3755 UINT64_C(165675008), // sysSTMIB_UPD 3756 UINT64_C(4047503360), // t2ADCri 3757 UINT64_C(3946840064), // t2ADCrr 3758 UINT64_C(3946840064), // t2ADCrs 3759 UINT64_C(4043309056), // t2ADDri 3760 UINT64_C(4060086272), // t2ADDri12 3761 UINT64_C(3942645760), // t2ADDrr 3762 UINT64_C(3942645760), // t2ADDrs 3763 UINT64_C(4044164352), // t2ADDspImm 3764 UINT64_C(4060941568), // t2ADDspImm12 3765 UINT64_C(4061069312), // t2ADR 3766 UINT64_C(4026531840), // t2ANDri 3767 UINT64_C(3925868544), // t2ANDrr 3768 UINT64_C(3925868544), // t2ANDrs 3769 UINT64_C(3931045920), // t2ASRri 3770 UINT64_C(4198559744), // t2ASRrr 3771 UINT64_C(4026568704), // t2B 3772 UINT64_C(4084137984), // t2BFC 3773 UINT64_C(4083154944), // t2BFI 3774 UINT64_C(4026580993), // t2BFLi 3775 UINT64_C(4033929217), // t2BFLr 3776 UINT64_C(4030783489), // t2BFi 3777 UINT64_C(4026589185), // t2BFic 3778 UINT64_C(4032880641), // t2BFr 3779 UINT64_C(4028628992), // t2BICri 3780 UINT64_C(3927965696), // t2BICrr 3781 UINT64_C(3927965696), // t2BICrs 3782 UINT64_C(4089483008), // t2BXJ 3783 UINT64_C(4026564608), // t2Bcc 3784 UINT64_C(3992977408), // t2CDP 3785 UINT64_C(4261412864), // t2CDP2 3786 UINT64_C(4089417519), // t2CLREX 3787 UINT64_C(3902734336), // t2CLRM 3788 UINT64_C(4205899904), // t2CLZ 3789 UINT64_C(4044361472), // t2CMNri 3790 UINT64_C(3943698176), // t2CMNzrr 3791 UINT64_C(3943698176), // t2CMNzrs 3792 UINT64_C(4054847232), // t2CMPri 3793 UINT64_C(3954183936), // t2CMPrr 3794 UINT64_C(3954183936), // t2CMPrs 3795 UINT64_C(4088365312), // t2CPS1p 3796 UINT64_C(4088365056), // t2CPS2p 3797 UINT64_C(4088365312), // t2CPS3p 3798 UINT64_C(4206948480), // t2CRC32B 3799 UINT64_C(4207997056), // t2CRC32CB 3800 UINT64_C(4207997072), // t2CRC32CH 3801 UINT64_C(4207997088), // t2CRC32CW 3802 UINT64_C(4206948496), // t2CRC32H 3803 UINT64_C(4206948512), // t2CRC32W 3804 UINT64_C(3931144192), // t2CSEL 3805 UINT64_C(3931148288), // t2CSINC 3806 UINT64_C(3931152384), // t2CSINV 3807 UINT64_C(3931156480), // t2CSNEG 3808 UINT64_C(4088365296), // t2DBG 3809 UINT64_C(4153376769), // t2DCPS1 3810 UINT64_C(4153376770), // t2DCPS2 3811 UINT64_C(4153376771), // t2DCPS3 3812 UINT64_C(4030783489), // t2DLS 3813 UINT64_C(4089417552), // t2DMB 3814 UINT64_C(4089417536), // t2DSB 3815 UINT64_C(4034920448), // t2EORri 3816 UINT64_C(3934257152), // t2EORrr 3817 UINT64_C(3934257152), // t2EORrs 3818 UINT64_C(4088365056), // t2HINT 3819 UINT64_C(4158685184), // t2HVC 3820 UINT64_C(4089417568), // t2ISB 3821 UINT64_C(48896), // t2IT 3822 UINT64_C(0), // t2Int_eh_sjlj_setjmp 3823 UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp 3824 UINT64_C(3905949615), // t2LDA 3825 UINT64_C(3905949583), // t2LDAB 3826 UINT64_C(3905949679), // t2LDAEX 3827 UINT64_C(3905949647), // t2LDAEXB 3828 UINT64_C(3905945855), // t2LDAEXD 3829 UINT64_C(3905949663), // t2LDAEXH 3830 UINT64_C(3905949599), // t2LDAH 3831 UINT64_C(4249878528), // t2LDC2L_OFFSET 3832 UINT64_C(4241489920), // t2LDC2L_OPTION 3833 UINT64_C(4235198464), // t2LDC2L_POST 3834 UINT64_C(4251975680), // t2LDC2L_PRE 3835 UINT64_C(4245684224), // t2LDC2_OFFSET 3836 UINT64_C(4237295616), // t2LDC2_OPTION 3837 UINT64_C(4231004160), // t2LDC2_POST 3838 UINT64_C(4247781376), // t2LDC2_PRE 3839 UINT64_C(3981443072), // t2LDCL_OFFSET 3840 UINT64_C(3973054464), // t2LDCL_OPTION 3841 UINT64_C(3966763008), // t2LDCL_POST 3842 UINT64_C(3983540224), // t2LDCL_PRE 3843 UINT64_C(3977248768), // t2LDC_OFFSET 3844 UINT64_C(3968860160), // t2LDC_OPTION 3845 UINT64_C(3962568704), // t2LDC_POST 3846 UINT64_C(3979345920), // t2LDC_PRE 3847 UINT64_C(3910139904), // t2LDMDB 3848 UINT64_C(3912237056), // t2LDMDB_UPD 3849 UINT64_C(3901751296), // t2LDMIA 3850 UINT64_C(3903848448), // t2LDMIA_UPD 3851 UINT64_C(4161801728), // t2LDRBT 3852 UINT64_C(4161800448), // t2LDRB_POST 3853 UINT64_C(4161801472), // t2LDRB_PRE 3854 UINT64_C(4170186752), // t2LDRBi12 3855 UINT64_C(4161801216), // t2LDRBi8 3856 UINT64_C(4162781184), // t2LDRBpci 3857 UINT64_C(4161798144), // t2LDRBs 3858 UINT64_C(3899654144), // t2LDRD_POST 3859 UINT64_C(3916431360), // t2LDRD_PRE 3860 UINT64_C(3914334208), // t2LDRDi8 3861 UINT64_C(3897560832), // t2LDREX 3862 UINT64_C(3905949519), // t2LDREXB 3863 UINT64_C(3905945727), // t2LDREXD 3864 UINT64_C(3905949535), // t2LDREXH 3865 UINT64_C(4163898880), // t2LDRHT 3866 UINT64_C(4163897600), // t2LDRH_POST 3867 UINT64_C(4163898624), // t2LDRH_PRE 3868 UINT64_C(4172283904), // t2LDRHi12 3869 UINT64_C(4163898368), // t2LDRHi8 3870 UINT64_C(4164878336), // t2LDRHpci 3871 UINT64_C(4163895296), // t2LDRHs 3872 UINT64_C(4178578944), // t2LDRSBT 3873 UINT64_C(4178577664), // t2LDRSB_POST 3874 UINT64_C(4178578688), // t2LDRSB_PRE 3875 UINT64_C(4186963968), // t2LDRSBi12 3876 UINT64_C(4178578432), // t2LDRSBi8 3877 UINT64_C(4179558400), // t2LDRSBpci 3878 UINT64_C(4178575360), // t2LDRSBs 3879 UINT64_C(4180676096), // t2LDRSHT 3880 UINT64_C(4180674816), // t2LDRSH_POST 3881 UINT64_C(4180675840), // t2LDRSH_PRE 3882 UINT64_C(4189061120), // t2LDRSHi12 3883 UINT64_C(4180675584), // t2LDRSHi8 3884 UINT64_C(4181655552), // t2LDRSHpci 3885 UINT64_C(4180672512), // t2LDRSHs 3886 UINT64_C(4165996032), // t2LDRT 3887 UINT64_C(4165994752), // t2LDR_POST 3888 UINT64_C(4165995776), // t2LDR_PRE 3889 UINT64_C(4174381056), // t2LDRi12 3890 UINT64_C(4165995520), // t2LDRi8 3891 UINT64_C(4166975488), // t2LDRpci 3892 UINT64_C(4165992448), // t2LDRs 3893 UINT64_C(4029661185), // t2LE 3894 UINT64_C(4027564033), // t2LEUpdate 3895 UINT64_C(3931045888), // t2LSLri 3896 UINT64_C(4194365440), // t2LSLrr 3897 UINT64_C(3931045904), // t2LSRri 3898 UINT64_C(4196462592), // t2LSRrr 3899 UINT64_C(3992977424), // t2MCR 3900 UINT64_C(4261412880), // t2MCR2 3901 UINT64_C(3963617280), // t2MCRR 3902 UINT64_C(4232052736), // t2MCRR2 3903 UINT64_C(4211081216), // t2MLA 3904 UINT64_C(4211081232), // t2MLS 3905 UINT64_C(4072669184), // t2MOVTi16 3906 UINT64_C(4031709184), // t2MOVi 3907 UINT64_C(4064280576), // t2MOVi16 3908 UINT64_C(3931045888), // t2MOVr 3909 UINT64_C(3932094560), // t2MOVsra_flag 3910 UINT64_C(3932094544), // t2MOVsrl_flag 3911 UINT64_C(3994026000), // t2MRC 3912 UINT64_C(4262461456), // t2MRC2 3913 UINT64_C(3964665856), // t2MRRC 3914 UINT64_C(4233101312), // t2MRRC2 3915 UINT64_C(4092559360), // t2MRS_AR 3916 UINT64_C(4092559360), // t2MRS_M 3917 UINT64_C(4091576352), // t2MRSbanked 3918 UINT64_C(4093607936), // t2MRSsys_AR 3919 UINT64_C(4085284864), // t2MSR_AR 3920 UINT64_C(4085284864), // t2MSR_M 3921 UINT64_C(4085284896), // t2MSRbanked 3922 UINT64_C(4211142656), // t2MUL 3923 UINT64_C(4033806336), // t2MVNi 3924 UINT64_C(3933143040), // t2MVNr 3925 UINT64_C(3933143040), // t2MVNs 3926 UINT64_C(4032823296), // t2ORNri 3927 UINT64_C(3932160000), // t2ORNrr 3928 UINT64_C(3932160000), // t2ORNrs 3929 UINT64_C(4030726144), // t2ORRri 3930 UINT64_C(3930062848), // t2ORRrr 3931 UINT64_C(3930062848), // t2ORRrs 3932 UINT64_C(3938451456), // t2PKHBT 3933 UINT64_C(3938451488), // t2PKHTB 3934 UINT64_C(4172345344), // t2PLDWi12 3935 UINT64_C(4163959808), // t2PLDWi8 3936 UINT64_C(4163956736), // t2PLDWs 3937 UINT64_C(4170248192), // t2PLDi12 3938 UINT64_C(4161862656), // t2PLDi8 3939 UINT64_C(4162842624), // t2PLDpci 3940 UINT64_C(4161859584), // t2PLDs 3941 UINT64_C(4187025408), // t2PLIi12 3942 UINT64_C(4178639872), // t2PLIi8 3943 UINT64_C(4179619840), // t2PLIpci 3944 UINT64_C(4178636800), // t2PLIs 3945 UINT64_C(4202754176), // t2QADD 3946 UINT64_C(4203802640), // t2QADD16 3947 UINT64_C(4202754064), // t2QADD8 3948 UINT64_C(4204851216), // t2QASX 3949 UINT64_C(4202754192), // t2QDADD 3950 UINT64_C(4202754224), // t2QDSUB 3951 UINT64_C(4209045520), // t2QSAX 3952 UINT64_C(4202754208), // t2QSUB 3953 UINT64_C(4207996944), // t2QSUB16 3954 UINT64_C(4206948368), // t2QSUB8 3955 UINT64_C(4203802784), // t2RBIT 3956 UINT64_C(4203802752), // t2REV 3957 UINT64_C(4203802768), // t2REV16 3958 UINT64_C(4203802800), // t2REVSH 3959 UINT64_C(3893411840), // t2RFEDB 3960 UINT64_C(3895508992), // t2RFEDBW 3961 UINT64_C(3918577664), // t2RFEIA 3962 UINT64_C(3920674816), // t2RFEIAW 3963 UINT64_C(3931045936), // t2RORri 3964 UINT64_C(4200656896), // t2RORrr 3965 UINT64_C(3931045936), // t2RRX 3966 UINT64_C(4055891968), // t2RSBri 3967 UINT64_C(3955228672), // t2RSBrr 3968 UINT64_C(3955228672), // t2RSBrs 3969 UINT64_C(4203802624), // t2SADD16 3970 UINT64_C(4202754048), // t2SADD8 3971 UINT64_C(4204851200), // t2SASX 3972 UINT64_C(4089417584), // t2SB 3973 UINT64_C(4049600512), // t2SBCri 3974 UINT64_C(3948937216), // t2SBCrr 3975 UINT64_C(3948937216), // t2SBCrs 3976 UINT64_C(4081057792), // t2SBFX 3977 UINT64_C(4220580080), // t2SDIV 3978 UINT64_C(4204851328), // t2SEL 3979 UINT64_C(46608), // t2SETPAN 3980 UINT64_C(3917474175), // t2SG 3981 UINT64_C(4203802656), // t2SHADD16 3982 UINT64_C(4202754080), // t2SHADD8 3983 UINT64_C(4204851232), // t2SHASX 3984 UINT64_C(4209045536), // t2SHSAX 3985 UINT64_C(4207996960), // t2SHSUB16 3986 UINT64_C(4206948384), // t2SHSUB8 3987 UINT64_C(4159733760), // t2SMC 3988 UINT64_C(4212129792), // t2SMLABB 3989 UINT64_C(4212129808), // t2SMLABT 3990 UINT64_C(4213178368), // t2SMLAD 3991 UINT64_C(4213178384), // t2SMLADX 3992 UINT64_C(4223664128), // t2SMLAL 3993 UINT64_C(4223664256), // t2SMLALBB 3994 UINT64_C(4223664272), // t2SMLALBT 3995 UINT64_C(4223664320), // t2SMLALD 3996 UINT64_C(4223664336), // t2SMLALDX 3997 UINT64_C(4223664288), // t2SMLALTB 3998 UINT64_C(4223664304), // t2SMLALTT 3999 UINT64_C(4212129824), // t2SMLATB 4000 UINT64_C(4212129840), // t2SMLATT 4001 UINT64_C(4214226944), // t2SMLAWB 4002 UINT64_C(4214226960), // t2SMLAWT 4003 UINT64_C(4215275520), // t2SMLSD 4004 UINT64_C(4215275536), // t2SMLSDX 4005 UINT64_C(4224712896), // t2SMLSLD 4006 UINT64_C(4224712912), // t2SMLSLDX 4007 UINT64_C(4216324096), // t2SMMLA 4008 UINT64_C(4216324112), // t2SMMLAR 4009 UINT64_C(4217372672), // t2SMMLS 4010 UINT64_C(4217372688), // t2SMMLSR 4011 UINT64_C(4216385536), // t2SMMUL 4012 UINT64_C(4216385552), // t2SMMULR 4013 UINT64_C(4213239808), // t2SMUAD 4014 UINT64_C(4213239824), // t2SMUADX 4015 UINT64_C(4212191232), // t2SMULBB 4016 UINT64_C(4212191248), // t2SMULBT 4017 UINT64_C(4219469824), // t2SMULL 4018 UINT64_C(4212191264), // t2SMULTB 4019 UINT64_C(4212191280), // t2SMULTT 4020 UINT64_C(4214288384), // t2SMULWB 4021 UINT64_C(4214288400), // t2SMULWT 4022 UINT64_C(4215336960), // t2SMUSD 4023 UINT64_C(4215336976), // t2SMUSDX 4024 UINT64_C(3893215232), // t2SRSDB 4025 UINT64_C(3895312384), // t2SRSDB_UPD 4026 UINT64_C(3918381056), // t2SRSIA 4027 UINT64_C(3920478208), // t2SRSIA_UPD 4028 UINT64_C(4076863488), // t2SSAT 4029 UINT64_C(4078960640), // t2SSAT16 4030 UINT64_C(4209045504), // t2SSAX 4031 UINT64_C(4207996928), // t2SSUB16 4032 UINT64_C(4206948352), // t2SSUB8 4033 UINT64_C(4248829952), // t2STC2L_OFFSET 4034 UINT64_C(4240441344), // t2STC2L_OPTION 4035 UINT64_C(4234149888), // t2STC2L_POST 4036 UINT64_C(4250927104), // t2STC2L_PRE 4037 UINT64_C(4244635648), // t2STC2_OFFSET 4038 UINT64_C(4236247040), // t2STC2_OPTION 4039 UINT64_C(4229955584), // t2STC2_POST 4040 UINT64_C(4246732800), // t2STC2_PRE 4041 UINT64_C(3980394496), // t2STCL_OFFSET 4042 UINT64_C(3972005888), // t2STCL_OPTION 4043 UINT64_C(3965714432), // t2STCL_POST 4044 UINT64_C(3982491648), // t2STCL_PRE 4045 UINT64_C(3976200192), // t2STC_OFFSET 4046 UINT64_C(3967811584), // t2STC_OPTION 4047 UINT64_C(3961520128), // t2STC_POST 4048 UINT64_C(3978297344), // t2STC_PRE 4049 UINT64_C(3904901039), // t2STL 4050 UINT64_C(3904901007), // t2STLB 4051 UINT64_C(3904901088), // t2STLEX 4052 UINT64_C(3904901056), // t2STLEXB 4053 UINT64_C(3904897264), // t2STLEXD 4054 UINT64_C(3904901072), // t2STLEXH 4055 UINT64_C(3904901023), // t2STLH 4056 UINT64_C(3909091328), // t2STMDB 4057 UINT64_C(3911188480), // t2STMDB_UPD 4058 UINT64_C(3900702720), // t2STMIA 4059 UINT64_C(3902799872), // t2STMIA_UPD 4060 UINT64_C(4160753152), // t2STRBT 4061 UINT64_C(4160751872), // t2STRB_POST 4062 UINT64_C(4160752896), // t2STRB_PRE 4063 UINT64_C(4169138176), // t2STRBi12 4064 UINT64_C(4160752640), // t2STRBi8 4065 UINT64_C(4160749568), // t2STRBs 4066 UINT64_C(3898605568), // t2STRD_POST 4067 UINT64_C(3915382784), // t2STRD_PRE 4068 UINT64_C(3913285632), // t2STRDi8 4069 UINT64_C(3896508416), // t2STREX 4070 UINT64_C(3904900928), // t2STREXB 4071 UINT64_C(3904897136), // t2STREXD 4072 UINT64_C(3904900944), // t2STREXH 4073 UINT64_C(4162850304), // t2STRHT 4074 UINT64_C(4162849024), // t2STRH_POST 4075 UINT64_C(4162850048), // t2STRH_PRE 4076 UINT64_C(4171235328), // t2STRHi12 4077 UINT64_C(4162849792), // t2STRHi8 4078 UINT64_C(4162846720), // t2STRHs 4079 UINT64_C(4164947456), // t2STRT 4080 UINT64_C(4164946176), // t2STR_POST 4081 UINT64_C(4164947200), // t2STR_PRE 4082 UINT64_C(4173332480), // t2STRi12 4083 UINT64_C(4164946944), // t2STRi8 4084 UINT64_C(4164943872), // t2STRs 4085 UINT64_C(4091449088), // t2SUBS_PC_LR 4086 UINT64_C(4053794816), // t2SUBri 4087 UINT64_C(4070572032), // t2SUBri12 4088 UINT64_C(3953131520), // t2SUBrr 4089 UINT64_C(3953131520), // t2SUBrs 4090 UINT64_C(4054650112), // t2SUBspImm 4091 UINT64_C(4071427328), // t2SUBspImm12 4092 UINT64_C(4198559872), // t2SXTAB 4093 UINT64_C(4196462720), // t2SXTAB16 4094 UINT64_C(4194365568), // t2SXTAH 4095 UINT64_C(4199542912), // t2SXTB 4096 UINT64_C(4197445760), // t2SXTB16 4097 UINT64_C(4195348608), // t2SXTH 4098 UINT64_C(3906007040), // t2TBB 4099 UINT64_C(3906007056), // t2TBH 4100 UINT64_C(4035972864), // t2TEQri 4101 UINT64_C(3935309568), // t2TEQrr 4102 UINT64_C(3935309568), // t2TEQrs 4103 UINT64_C(4088365074), // t2TSB 4104 UINT64_C(4027584256), // t2TSTri 4105 UINT64_C(3926920960), // t2TSTrr 4106 UINT64_C(3926920960), // t2TSTrs 4107 UINT64_C(3896569856), // t2TT 4108 UINT64_C(3896569984), // t2TTA 4109 UINT64_C(3896570048), // t2TTAT 4110 UINT64_C(3896569920), // t2TTT 4111 UINT64_C(4203802688), // t2UADD16 4112 UINT64_C(4202754112), // t2UADD8 4113 UINT64_C(4204851264), // t2UASX 4114 UINT64_C(4089446400), // t2UBFX 4115 UINT64_C(4159741952), // t2UDF 4116 UINT64_C(4222677232), // t2UDIV 4117 UINT64_C(4203802720), // t2UHADD16 4118 UINT64_C(4202754144), // t2UHADD8 4119 UINT64_C(4204851296), // t2UHASX 4120 UINT64_C(4209045600), // t2UHSAX 4121 UINT64_C(4207997024), // t2UHSUB16 4122 UINT64_C(4206948448), // t2UHSUB8 4123 UINT64_C(4225761376), // t2UMAAL 4124 UINT64_C(4225761280), // t2UMLAL 4125 UINT64_C(4221566976), // t2UMULL 4126 UINT64_C(4203802704), // t2UQADD16 4127 UINT64_C(4202754128), // t2UQADD8 4128 UINT64_C(4204851280), // t2UQASX 4129 UINT64_C(4209045584), // t2UQSAX 4130 UINT64_C(4207997008), // t2UQSUB16 4131 UINT64_C(4206948432), // t2UQSUB8 4132 UINT64_C(4218482688), // t2USAD8 4133 UINT64_C(4218421248), // t2USADA8 4134 UINT64_C(4085252096), // t2USAT 4135 UINT64_C(4087349248), // t2USAT16 4136 UINT64_C(4209045568), // t2USAX 4137 UINT64_C(4207996992), // t2USUB16 4138 UINT64_C(4206948416), // t2USUB8 4139 UINT64_C(4199608448), // t2UXTAB 4140 UINT64_C(4197511296), // t2UXTAB16 4141 UINT64_C(4195414144), // t2UXTAH 4142 UINT64_C(4200591488), // t2UXTB 4143 UINT64_C(4198494336), // t2UXTB16 4144 UINT64_C(4196397184), // t2UXTH 4145 UINT64_C(4030775297), // t2WLS 4146 UINT64_C(16704), // tADC 4147 UINT64_C(17408), // tADDhirr 4148 UINT64_C(7168), // tADDi3 4149 UINT64_C(12288), // tADDi8 4150 UINT64_C(17512), // tADDrSP 4151 UINT64_C(43008), // tADDrSPi 4152 UINT64_C(6144), // tADDrr 4153 UINT64_C(45056), // tADDspi 4154 UINT64_C(17541), // tADDspr 4155 UINT64_C(40960), // tADR 4156 UINT64_C(16384), // tAND 4157 UINT64_C(4096), // tASRri 4158 UINT64_C(16640), // tASRrr 4159 UINT64_C(57344), // tB 4160 UINT64_C(17280), // tBIC 4161 UINT64_C(48640), // tBKPT 4162 UINT64_C(4026585088), // tBL 4163 UINT64_C(18308), // tBLXNSr 4164 UINT64_C(4026580992), // tBLXi 4165 UINT64_C(18304), // tBLXr 4166 UINT64_C(18176), // tBX 4167 UINT64_C(18180), // tBXNS 4168 UINT64_C(53248), // tBcc 4169 UINT64_C(47360), // tCBNZ 4170 UINT64_C(45312), // tCBZ 4171 UINT64_C(17088), // tCMNz 4172 UINT64_C(17664), // tCMPhir 4173 UINT64_C(10240), // tCMPi8 4174 UINT64_C(17024), // tCMPr 4175 UINT64_C(46688), // tCPS 4176 UINT64_C(16448), // tEOR 4177 UINT64_C(48896), // tHINT 4178 UINT64_C(47744), // tHLT 4179 UINT64_C(0), // tInt_WIN_eh_sjlj_longjmp 4180 UINT64_C(0), // tInt_eh_sjlj_longjmp 4181 UINT64_C(0), // tInt_eh_sjlj_setjmp 4182 UINT64_C(51200), // tLDMIA 4183 UINT64_C(30720), // tLDRBi 4184 UINT64_C(23552), // tLDRBr 4185 UINT64_C(34816), // tLDRHi 4186 UINT64_C(23040), // tLDRHr 4187 UINT64_C(22016), // tLDRSB 4188 UINT64_C(24064), // tLDRSH 4189 UINT64_C(26624), // tLDRi 4190 UINT64_C(18432), // tLDRpci 4191 UINT64_C(22528), // tLDRr 4192 UINT64_C(38912), // tLDRspi 4193 UINT64_C(0), // tLSLri 4194 UINT64_C(16512), // tLSLrr 4195 UINT64_C(2048), // tLSRri 4196 UINT64_C(16576), // tLSRrr 4197 UINT64_C(0), // tMOVSr 4198 UINT64_C(8192), // tMOVi8 4199 UINT64_C(17920), // tMOVr 4200 UINT64_C(17216), // tMUL 4201 UINT64_C(17344), // tMVN 4202 UINT64_C(17152), // tORR 4203 UINT64_C(17528), // tPICADD 4204 UINT64_C(48128), // tPOP 4205 UINT64_C(46080), // tPUSH 4206 UINT64_C(47616), // tREV 4207 UINT64_C(47680), // tREV16 4208 UINT64_C(47808), // tREVSH 4209 UINT64_C(16832), // tROR 4210 UINT64_C(16960), // tRSB 4211 UINT64_C(16768), // tSBC 4212 UINT64_C(46672), // tSETEND 4213 UINT64_C(49152), // tSTMIA_UPD 4214 UINT64_C(28672), // tSTRBi 4215 UINT64_C(21504), // tSTRBr 4216 UINT64_C(32768), // tSTRHi 4217 UINT64_C(20992), // tSTRHr 4218 UINT64_C(24576), // tSTRi 4219 UINT64_C(20480), // tSTRr 4220 UINT64_C(36864), // tSTRspi 4221 UINT64_C(7680), // tSUBi3 4222 UINT64_C(14336), // tSUBi8 4223 UINT64_C(6656), // tSUBrr 4224 UINT64_C(45184), // tSUBspi 4225 UINT64_C(57088), // tSVC 4226 UINT64_C(45632), // tSXTB 4227 UINT64_C(45568), // tSXTH 4228 UINT64_C(57086), // tTRAP 4229 UINT64_C(16896), // tTST 4230 UINT64_C(56832), // tUDF 4231 UINT64_C(45760), // tUXTB 4232 UINT64_C(45696), // tUXTH 4233 UINT64_C(57081), // t__brkdiv0 4234 UINT64_C(0) 4235 }; 4236 const unsigned opcode = MI.getOpcode(); 4237 uint64_t Value = InstBits[opcode]; 4238 uint64_t op = 0; 4239 (void)op; // suppress warning 4240 switch (opcode) { 4241 case ARM::CLREX: 4242 case ARM::MVE_LCTP: 4243 case ARM::MVE_VPNOT: 4244 case ARM::SB: 4245 case ARM::TRAP: 4246 case ARM::TRAPNaCl: 4247 case ARM::TSB: 4248 case ARM::VLD1LNq16Pseudo: 4249 case ARM::VLD1LNq16Pseudo_UPD: 4250 case ARM::VLD1LNq32Pseudo: 4251 case ARM::VLD1LNq32Pseudo_UPD: 4252 case ARM::VLD1LNq8Pseudo: 4253 case ARM::VLD1LNq8Pseudo_UPD: 4254 case ARM::VLD1d16QPseudo: 4255 case ARM::VLD1d16TPseudo: 4256 case ARM::VLD1d32QPseudo: 4257 case ARM::VLD1d32TPseudo: 4258 case ARM::VLD1d64QPseudo: 4259 case ARM::VLD1d64QPseudoWB_fixed: 4260 case ARM::VLD1d64QPseudoWB_register: 4261 case ARM::VLD1d64TPseudo: 4262 case ARM::VLD1d64TPseudoWB_fixed: 4263 case ARM::VLD1d64TPseudoWB_register: 4264 case ARM::VLD1d8QPseudo: 4265 case ARM::VLD1d8TPseudo: 4266 case ARM::VLD1q16HighQPseudo: 4267 case ARM::VLD1q16HighTPseudo: 4268 case ARM::VLD1q16LowQPseudo_UPD: 4269 case ARM::VLD1q16LowTPseudo_UPD: 4270 case ARM::VLD1q32HighQPseudo: 4271 case ARM::VLD1q32HighTPseudo: 4272 case ARM::VLD1q32LowQPseudo_UPD: 4273 case ARM::VLD1q32LowTPseudo_UPD: 4274 case ARM::VLD1q64HighQPseudo: 4275 case ARM::VLD1q64HighTPseudo: 4276 case ARM::VLD1q64LowQPseudo_UPD: 4277 case ARM::VLD1q64LowTPseudo_UPD: 4278 case ARM::VLD1q8HighQPseudo: 4279 case ARM::VLD1q8HighTPseudo: 4280 case ARM::VLD1q8LowQPseudo_UPD: 4281 case ARM::VLD1q8LowTPseudo_UPD: 4282 case ARM::VLD2DUPq16EvenPseudo: 4283 case ARM::VLD2DUPq16OddPseudo: 4284 case ARM::VLD2DUPq32EvenPseudo: 4285 case ARM::VLD2DUPq32OddPseudo: 4286 case ARM::VLD2DUPq8EvenPseudo: 4287 case ARM::VLD2DUPq8OddPseudo: 4288 case ARM::VLD2LNd16Pseudo: 4289 case ARM::VLD2LNd16Pseudo_UPD: 4290 case ARM::VLD2LNd32Pseudo: 4291 case ARM::VLD2LNd32Pseudo_UPD: 4292 case ARM::VLD2LNd8Pseudo: 4293 case ARM::VLD2LNd8Pseudo_UPD: 4294 case ARM::VLD2LNq16Pseudo: 4295 case ARM::VLD2LNq16Pseudo_UPD: 4296 case ARM::VLD2LNq32Pseudo: 4297 case ARM::VLD2LNq32Pseudo_UPD: 4298 case ARM::VLD2q16Pseudo: 4299 case ARM::VLD2q16PseudoWB_fixed: 4300 case ARM::VLD2q16PseudoWB_register: 4301 case ARM::VLD2q32Pseudo: 4302 case ARM::VLD2q32PseudoWB_fixed: 4303 case ARM::VLD2q32PseudoWB_register: 4304 case ARM::VLD2q8Pseudo: 4305 case ARM::VLD2q8PseudoWB_fixed: 4306 case ARM::VLD2q8PseudoWB_register: 4307 case ARM::VLD3DUPd16Pseudo: 4308 case ARM::VLD3DUPd16Pseudo_UPD: 4309 case ARM::VLD3DUPd32Pseudo: 4310 case ARM::VLD3DUPd32Pseudo_UPD: 4311 case ARM::VLD3DUPd8Pseudo: 4312 case ARM::VLD3DUPd8Pseudo_UPD: 4313 case ARM::VLD3DUPq16EvenPseudo: 4314 case ARM::VLD3DUPq16OddPseudo: 4315 case ARM::VLD3DUPq32EvenPseudo: 4316 case ARM::VLD3DUPq32OddPseudo: 4317 case ARM::VLD3DUPq8EvenPseudo: 4318 case ARM::VLD3DUPq8OddPseudo: 4319 case ARM::VLD3LNd16Pseudo: 4320 case ARM::VLD3LNd16Pseudo_UPD: 4321 case ARM::VLD3LNd32Pseudo: 4322 case ARM::VLD3LNd32Pseudo_UPD: 4323 case ARM::VLD3LNd8Pseudo: 4324 case ARM::VLD3LNd8Pseudo_UPD: 4325 case ARM::VLD3LNq16Pseudo: 4326 case ARM::VLD3LNq16Pseudo_UPD: 4327 case ARM::VLD3LNq32Pseudo: 4328 case ARM::VLD3LNq32Pseudo_UPD: 4329 case ARM::VLD3d16Pseudo: 4330 case ARM::VLD3d16Pseudo_UPD: 4331 case ARM::VLD3d32Pseudo: 4332 case ARM::VLD3d32Pseudo_UPD: 4333 case ARM::VLD3d8Pseudo: 4334 case ARM::VLD3d8Pseudo_UPD: 4335 case ARM::VLD3q16Pseudo_UPD: 4336 case ARM::VLD3q16oddPseudo: 4337 case ARM::VLD3q16oddPseudo_UPD: 4338 case ARM::VLD3q32Pseudo_UPD: 4339 case ARM::VLD3q32oddPseudo: 4340 case ARM::VLD3q32oddPseudo_UPD: 4341 case ARM::VLD3q8Pseudo_UPD: 4342 case ARM::VLD3q8oddPseudo: 4343 case ARM::VLD3q8oddPseudo_UPD: 4344 case ARM::VLD4DUPd16Pseudo: 4345 case ARM::VLD4DUPd16Pseudo_UPD: 4346 case ARM::VLD4DUPd32Pseudo: 4347 case ARM::VLD4DUPd32Pseudo_UPD: 4348 case ARM::VLD4DUPd8Pseudo: 4349 case ARM::VLD4DUPd8Pseudo_UPD: 4350 case ARM::VLD4DUPq16EvenPseudo: 4351 case ARM::VLD4DUPq16OddPseudo: 4352 case ARM::VLD4DUPq32EvenPseudo: 4353 case ARM::VLD4DUPq32OddPseudo: 4354 case ARM::VLD4DUPq8EvenPseudo: 4355 case ARM::VLD4DUPq8OddPseudo: 4356 case ARM::VLD4LNd16Pseudo: 4357 case ARM::VLD4LNd16Pseudo_UPD: 4358 case ARM::VLD4LNd32Pseudo: 4359 case ARM::VLD4LNd32Pseudo_UPD: 4360 case ARM::VLD4LNd8Pseudo: 4361 case ARM::VLD4LNd8Pseudo_UPD: 4362 case ARM::VLD4LNq16Pseudo: 4363 case ARM::VLD4LNq16Pseudo_UPD: 4364 case ARM::VLD4LNq32Pseudo: 4365 case ARM::VLD4LNq32Pseudo_UPD: 4366 case ARM::VLD4d16Pseudo: 4367 case ARM::VLD4d16Pseudo_UPD: 4368 case ARM::VLD4d32Pseudo: 4369 case ARM::VLD4d32Pseudo_UPD: 4370 case ARM::VLD4d8Pseudo: 4371 case ARM::VLD4d8Pseudo_UPD: 4372 case ARM::VLD4q16Pseudo_UPD: 4373 case ARM::VLD4q16oddPseudo: 4374 case ARM::VLD4q16oddPseudo_UPD: 4375 case ARM::VLD4q32Pseudo_UPD: 4376 case ARM::VLD4q32oddPseudo: 4377 case ARM::VLD4q32oddPseudo_UPD: 4378 case ARM::VLD4q8Pseudo_UPD: 4379 case ARM::VLD4q8oddPseudo: 4380 case ARM::VLD4q8oddPseudo_UPD: 4381 case ARM::VLDMQIA: 4382 case ARM::VST1LNq16Pseudo: 4383 case ARM::VST1LNq16Pseudo_UPD: 4384 case ARM::VST1LNq32Pseudo: 4385 case ARM::VST1LNq32Pseudo_UPD: 4386 case ARM::VST1LNq8Pseudo: 4387 case ARM::VST1LNq8Pseudo_UPD: 4388 case ARM::VST1d16QPseudo: 4389 case ARM::VST1d16TPseudo: 4390 case ARM::VST1d32QPseudo: 4391 case ARM::VST1d32TPseudo: 4392 case ARM::VST1d64QPseudo: 4393 case ARM::VST1d64QPseudoWB_fixed: 4394 case ARM::VST1d64QPseudoWB_register: 4395 case ARM::VST1d64TPseudo: 4396 case ARM::VST1d64TPseudoWB_fixed: 4397 case ARM::VST1d64TPseudoWB_register: 4398 case ARM::VST1d8QPseudo: 4399 case ARM::VST1d8TPseudo: 4400 case ARM::VST1q16HighQPseudo: 4401 case ARM::VST1q16HighTPseudo: 4402 case ARM::VST1q16LowQPseudo_UPD: 4403 case ARM::VST1q16LowTPseudo_UPD: 4404 case ARM::VST1q32HighQPseudo: 4405 case ARM::VST1q32HighTPseudo: 4406 case ARM::VST1q32LowQPseudo_UPD: 4407 case ARM::VST1q32LowTPseudo_UPD: 4408 case ARM::VST1q64HighQPseudo: 4409 case ARM::VST1q64HighTPseudo: 4410 case ARM::VST1q64LowQPseudo_UPD: 4411 case ARM::VST1q64LowTPseudo_UPD: 4412 case ARM::VST1q8HighQPseudo: 4413 case ARM::VST1q8HighTPseudo: 4414 case ARM::VST1q8LowQPseudo_UPD: 4415 case ARM::VST1q8LowTPseudo_UPD: 4416 case ARM::VST2LNd16Pseudo: 4417 case ARM::VST2LNd16Pseudo_UPD: 4418 case ARM::VST2LNd32Pseudo: 4419 case ARM::VST2LNd32Pseudo_UPD: 4420 case ARM::VST2LNd8Pseudo: 4421 case ARM::VST2LNd8Pseudo_UPD: 4422 case ARM::VST2LNq16Pseudo: 4423 case ARM::VST2LNq16Pseudo_UPD: 4424 case ARM::VST2LNq32Pseudo: 4425 case ARM::VST2LNq32Pseudo_UPD: 4426 case ARM::VST2q16Pseudo: 4427 case ARM::VST2q16PseudoWB_fixed: 4428 case ARM::VST2q16PseudoWB_register: 4429 case ARM::VST2q32Pseudo: 4430 case ARM::VST2q32PseudoWB_fixed: 4431 case ARM::VST2q32PseudoWB_register: 4432 case ARM::VST2q8Pseudo: 4433 case ARM::VST2q8PseudoWB_fixed: 4434 case ARM::VST2q8PseudoWB_register: 4435 case ARM::VST3LNd16Pseudo: 4436 case ARM::VST3LNd16Pseudo_UPD: 4437 case ARM::VST3LNd32Pseudo: 4438 case ARM::VST3LNd32Pseudo_UPD: 4439 case ARM::VST3LNd8Pseudo: 4440 case ARM::VST3LNd8Pseudo_UPD: 4441 case ARM::VST3LNq16Pseudo: 4442 case ARM::VST3LNq16Pseudo_UPD: 4443 case ARM::VST3LNq32Pseudo: 4444 case ARM::VST3LNq32Pseudo_UPD: 4445 case ARM::VST3d16Pseudo: 4446 case ARM::VST3d16Pseudo_UPD: 4447 case ARM::VST3d32Pseudo: 4448 case ARM::VST3d32Pseudo_UPD: 4449 case ARM::VST3d8Pseudo: 4450 case ARM::VST3d8Pseudo_UPD: 4451 case ARM::VST3q16Pseudo_UPD: 4452 case ARM::VST3q16oddPseudo: 4453 case ARM::VST3q16oddPseudo_UPD: 4454 case ARM::VST3q32Pseudo_UPD: 4455 case ARM::VST3q32oddPseudo: 4456 case ARM::VST3q32oddPseudo_UPD: 4457 case ARM::VST3q8Pseudo_UPD: 4458 case ARM::VST3q8oddPseudo: 4459 case ARM::VST3q8oddPseudo_UPD: 4460 case ARM::VST4LNd16Pseudo: 4461 case ARM::VST4LNd16Pseudo_UPD: 4462 case ARM::VST4LNd32Pseudo: 4463 case ARM::VST4LNd32Pseudo_UPD: 4464 case ARM::VST4LNd8Pseudo: 4465 case ARM::VST4LNd8Pseudo_UPD: 4466 case ARM::VST4LNq16Pseudo: 4467 case ARM::VST4LNq16Pseudo_UPD: 4468 case ARM::VST4LNq32Pseudo: 4469 case ARM::VST4LNq32Pseudo_UPD: 4470 case ARM::VST4d16Pseudo: 4471 case ARM::VST4d16Pseudo_UPD: 4472 case ARM::VST4d32Pseudo: 4473 case ARM::VST4d32Pseudo_UPD: 4474 case ARM::VST4d8Pseudo: 4475 case ARM::VST4d8Pseudo_UPD: 4476 case ARM::VST4q16Pseudo_UPD: 4477 case ARM::VST4q16oddPseudo: 4478 case ARM::VST4q16oddPseudo_UPD: 4479 case ARM::VST4q32Pseudo_UPD: 4480 case ARM::VST4q32oddPseudo: 4481 case ARM::VST4q32oddPseudo_UPD: 4482 case ARM::VST4q8Pseudo_UPD: 4483 case ARM::VST4q8oddPseudo: 4484 case ARM::VST4q8oddPseudo_UPD: 4485 case ARM::VSTMQIA: 4486 case ARM::VTBL3Pseudo: 4487 case ARM::VTBL4Pseudo: 4488 case ARM::VTBX3Pseudo: 4489 case ARM::VTBX4Pseudo: 4490 case ARM::t2CLREX: 4491 case ARM::t2DCPS1: 4492 case ARM::t2DCPS2: 4493 case ARM::t2DCPS3: 4494 case ARM::t2Int_eh_sjlj_setjmp: 4495 case ARM::t2Int_eh_sjlj_setjmp_nofp: 4496 case ARM::t2SB: 4497 case ARM::t2SG: 4498 case ARM::t2TSB: 4499 case ARM::tInt_WIN_eh_sjlj_longjmp: 4500 case ARM::tInt_eh_sjlj_longjmp: 4501 case ARM::tInt_eh_sjlj_setjmp: 4502 case ARM::tTRAP: 4503 case ARM::t__brkdiv0: { 4504 break; 4505 } 4506 case ARM::VRINTAD: 4507 case ARM::VRINTMD: 4508 case ARM::VRINTND: 4509 case ARM::VRINTPD: { 4510 // op: Dd 4511 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4512 Value |= (op & UINT64_C(16)) << 18; 4513 Value |= (op & UINT64_C(15)) << 12; 4514 // op: Dm 4515 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4516 Value |= (op & UINT64_C(16)) << 1; 4517 Value |= (op & UINT64_C(15)); 4518 break; 4519 } 4520 case ARM::VFP_VMAXNMD: 4521 case ARM::VFP_VMINNMD: 4522 case ARM::VSELEQD: 4523 case ARM::VSELGED: 4524 case ARM::VSELGTD: 4525 case ARM::VSELVSD: { 4526 // op: Dd 4527 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4528 Value |= (op & UINT64_C(16)) << 18; 4529 Value |= (op & UINT64_C(15)) << 12; 4530 // op: Dn 4531 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4532 Value |= (op & UINT64_C(15)) << 16; 4533 Value |= (op & UINT64_C(16)) << 3; 4534 // op: Dm 4535 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4536 Value |= (op & UINT64_C(16)) << 1; 4537 Value |= (op & UINT64_C(15)); 4538 break; 4539 } 4540 case ARM::MVE_VPST: { 4541 // op: Mk 4542 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 4543 Value |= (op & UINT64_C(8)) << 19; 4544 Value |= (op & UINT64_C(7)) << 13; 4545 break; 4546 } 4547 case ARM::MVE_VDUP16: 4548 case ARM::MVE_VDUP32: 4549 case ARM::MVE_VDUP8: { 4550 // op: Qd 4551 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4552 Value |= (op & UINT64_C(7)) << 17; 4553 Value |= (op & UINT64_C(8)) << 4; 4554 // op: Rt 4555 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4556 op &= UINT64_C(15); 4557 op <<= 12; 4558 Value |= op; 4559 break; 4560 } 4561 case ARM::MVE_VMOV_to_lane_32: { 4562 // op: Qd 4563 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4564 Value |= (op & UINT64_C(7)) << 17; 4565 Value |= (op & UINT64_C(8)) << 4; 4566 // op: Rt 4567 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4568 op &= UINT64_C(15); 4569 op <<= 12; 4570 Value |= op; 4571 // op: Idx 4572 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4573 Value |= (op & UINT64_C(1)) << 21; 4574 Value |= (op & UINT64_C(2)) << 15; 4575 break; 4576 } 4577 case ARM::MVE_VMOV_to_lane_16: { 4578 // op: Qd 4579 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4580 Value |= (op & UINT64_C(7)) << 17; 4581 Value |= (op & UINT64_C(8)) << 4; 4582 // op: Rt 4583 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4584 op &= UINT64_C(15); 4585 op <<= 12; 4586 Value |= op; 4587 // op: Idx 4588 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4589 Value |= (op & UINT64_C(2)) << 20; 4590 Value |= (op & UINT64_C(4)) << 14; 4591 Value |= (op & UINT64_C(1)) << 6; 4592 break; 4593 } 4594 case ARM::MVE_VMOV_to_lane_8: { 4595 // op: Qd 4596 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4597 Value |= (op & UINT64_C(7)) << 17; 4598 Value |= (op & UINT64_C(8)) << 4; 4599 // op: Rt 4600 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4601 op &= UINT64_C(15); 4602 op <<= 12; 4603 Value |= op; 4604 // op: Idx 4605 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4606 Value |= (op & UINT64_C(4)) << 19; 4607 Value |= (op & UINT64_C(8)) << 13; 4608 Value |= (op & UINT64_C(3)) << 5; 4609 break; 4610 } 4611 case ARM::MVE_VABSs16: 4612 case ARM::MVE_VABSs32: 4613 case ARM::MVE_VABSs8: 4614 case ARM::MVE_VCLSs16: 4615 case ARM::MVE_VCLSs32: 4616 case ARM::MVE_VCLSs8: 4617 case ARM::MVE_VCLZs16: 4618 case ARM::MVE_VCLZs32: 4619 case ARM::MVE_VCLZs8: 4620 case ARM::MVE_VMOVLs16bh: 4621 case ARM::MVE_VMOVLs16th: 4622 case ARM::MVE_VMOVLs8bh: 4623 case ARM::MVE_VMOVLs8th: 4624 case ARM::MVE_VMOVLu16bh: 4625 case ARM::MVE_VMOVLu16th: 4626 case ARM::MVE_VMOVLu8bh: 4627 case ARM::MVE_VMOVLu8th: 4628 case ARM::MVE_VMVN: 4629 case ARM::MVE_VNEGs16: 4630 case ARM::MVE_VNEGs32: 4631 case ARM::MVE_VNEGs8: 4632 case ARM::MVE_VQABSs16: 4633 case ARM::MVE_VQABSs32: 4634 case ARM::MVE_VQABSs8: 4635 case ARM::MVE_VQNEGs16: 4636 case ARM::MVE_VQNEGs32: 4637 case ARM::MVE_VQNEGs8: 4638 case ARM::MVE_VREV16_8: 4639 case ARM::MVE_VREV32_16: 4640 case ARM::MVE_VREV32_8: 4641 case ARM::MVE_VREV64_16: 4642 case ARM::MVE_VREV64_32: 4643 case ARM::MVE_VREV64_8: 4644 case ARM::MVE_VSHLL_lws16bh: 4645 case ARM::MVE_VSHLL_lws16th: 4646 case ARM::MVE_VSHLL_lws8bh: 4647 case ARM::MVE_VSHLL_lws8th: 4648 case ARM::MVE_VSHLL_lwu16bh: 4649 case ARM::MVE_VSHLL_lwu16th: 4650 case ARM::MVE_VSHLL_lwu8bh: 4651 case ARM::MVE_VSHLL_lwu8th: { 4652 // op: Qd 4653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4654 Value |= (op & UINT64_C(8)) << 19; 4655 Value |= (op & UINT64_C(7)) << 13; 4656 // op: Qm 4657 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4658 Value |= (op & UINT64_C(8)) << 2; 4659 Value |= (op & UINT64_C(7)) << 1; 4660 break; 4661 } 4662 case ARM::MVE_VQRSHL_by_vecs16: 4663 case ARM::MVE_VQRSHL_by_vecs32: 4664 case ARM::MVE_VQRSHL_by_vecs8: 4665 case ARM::MVE_VQRSHL_by_vecu16: 4666 case ARM::MVE_VQRSHL_by_vecu32: 4667 case ARM::MVE_VQRSHL_by_vecu8: 4668 case ARM::MVE_VQSHL_by_vecs16: 4669 case ARM::MVE_VQSHL_by_vecs32: 4670 case ARM::MVE_VQSHL_by_vecs8: 4671 case ARM::MVE_VQSHL_by_vecu16: 4672 case ARM::MVE_VQSHL_by_vecu32: 4673 case ARM::MVE_VQSHL_by_vecu8: 4674 case ARM::MVE_VRSHL_by_vecs16: 4675 case ARM::MVE_VRSHL_by_vecs32: 4676 case ARM::MVE_VRSHL_by_vecs8: 4677 case ARM::MVE_VRSHL_by_vecu16: 4678 case ARM::MVE_VRSHL_by_vecu32: 4679 case ARM::MVE_VRSHL_by_vecu8: 4680 case ARM::MVE_VSHL_by_vecs16: 4681 case ARM::MVE_VSHL_by_vecs32: 4682 case ARM::MVE_VSHL_by_vecs8: 4683 case ARM::MVE_VSHL_by_vecu16: 4684 case ARM::MVE_VSHL_by_vecu32: 4685 case ARM::MVE_VSHL_by_vecu8: { 4686 // op: Qd 4687 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4688 Value |= (op & UINT64_C(8)) << 19; 4689 Value |= (op & UINT64_C(7)) << 13; 4690 // op: Qm 4691 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4692 Value |= (op & UINT64_C(8)) << 2; 4693 Value |= (op & UINT64_C(7)) << 1; 4694 // op: Qn 4695 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4696 Value |= (op & UINT64_C(7)) << 17; 4697 Value |= (op & UINT64_C(8)) << 4; 4698 break; 4699 } 4700 case ARM::MVE_VSHLL_imms16bh: 4701 case ARM::MVE_VSHLL_imms16th: 4702 case ARM::MVE_VSHLL_immu16bh: 4703 case ARM::MVE_VSHLL_immu16th: { 4704 // op: Qd 4705 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4706 Value |= (op & UINT64_C(8)) << 19; 4707 Value |= (op & UINT64_C(7)) << 13; 4708 // op: Qm 4709 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4710 Value |= (op & UINT64_C(8)) << 2; 4711 Value |= (op & UINT64_C(7)) << 1; 4712 // op: imm 4713 op = getMVEShiftImmOpValue(MI, 2, Fixups, STI); 4714 op &= UINT64_C(15); 4715 op <<= 16; 4716 Value |= op; 4717 break; 4718 } 4719 case ARM::MVE_VSHLL_imms8bh: 4720 case ARM::MVE_VSHLL_imms8th: 4721 case ARM::MVE_VSHLL_immu8bh: 4722 case ARM::MVE_VSHLL_immu8th: { 4723 // op: Qd 4724 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4725 Value |= (op & UINT64_C(8)) << 19; 4726 Value |= (op & UINT64_C(7)) << 13; 4727 // op: Qm 4728 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4729 Value |= (op & UINT64_C(8)) << 2; 4730 Value |= (op & UINT64_C(7)) << 1; 4731 // op: imm 4732 op = getMVEShiftImmOpValue(MI, 2, Fixups, STI); 4733 op &= UINT64_C(7); 4734 op <<= 16; 4735 Value |= op; 4736 break; 4737 } 4738 case ARM::MVE_VQSHLU_imms16: 4739 case ARM::MVE_VQSHLimms16: 4740 case ARM::MVE_VQSHLimmu16: 4741 case ARM::MVE_VSHL_immi16: { 4742 // op: Qd 4743 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4744 Value |= (op & UINT64_C(8)) << 19; 4745 Value |= (op & UINT64_C(7)) << 13; 4746 // op: Qm 4747 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4748 Value |= (op & UINT64_C(8)) << 2; 4749 Value |= (op & UINT64_C(7)) << 1; 4750 // op: imm 4751 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4752 op &= UINT64_C(15); 4753 op <<= 16; 4754 Value |= op; 4755 break; 4756 } 4757 case ARM::MVE_VQSHLU_imms32: 4758 case ARM::MVE_VQSHLimms32: 4759 case ARM::MVE_VQSHLimmu32: 4760 case ARM::MVE_VSHL_immi32: { 4761 // op: Qd 4762 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4763 Value |= (op & UINT64_C(8)) << 19; 4764 Value |= (op & UINT64_C(7)) << 13; 4765 // op: Qm 4766 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4767 Value |= (op & UINT64_C(8)) << 2; 4768 Value |= (op & UINT64_C(7)) << 1; 4769 // op: imm 4770 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4771 op &= UINT64_C(31); 4772 op <<= 16; 4773 Value |= op; 4774 break; 4775 } 4776 case ARM::MVE_VQSHLU_imms8: 4777 case ARM::MVE_VQSHLimms8: 4778 case ARM::MVE_VQSHLimmu8: 4779 case ARM::MVE_VSHL_immi8: { 4780 // op: Qd 4781 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4782 Value |= (op & UINT64_C(8)) << 19; 4783 Value |= (op & UINT64_C(7)) << 13; 4784 // op: Qm 4785 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4786 Value |= (op & UINT64_C(8)) << 2; 4787 Value |= (op & UINT64_C(7)) << 1; 4788 // op: imm 4789 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4790 op &= UINT64_C(7); 4791 op <<= 16; 4792 Value |= op; 4793 break; 4794 } 4795 case ARM::MVE_VRSHR_imms16: 4796 case ARM::MVE_VRSHR_immu16: 4797 case ARM::MVE_VSHR_imms16: 4798 case ARM::MVE_VSHR_immu16: { 4799 // op: Qd 4800 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4801 Value |= (op & UINT64_C(8)) << 19; 4802 Value |= (op & UINT64_C(7)) << 13; 4803 // op: Qm 4804 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4805 Value |= (op & UINT64_C(8)) << 2; 4806 Value |= (op & UINT64_C(7)) << 1; 4807 // op: imm 4808 op = getShiftRight16Imm(MI, 2, Fixups, STI); 4809 op &= UINT64_C(15); 4810 op <<= 16; 4811 Value |= op; 4812 break; 4813 } 4814 case ARM::MVE_VRSHR_imms32: 4815 case ARM::MVE_VRSHR_immu32: 4816 case ARM::MVE_VSHR_imms32: 4817 case ARM::MVE_VSHR_immu32: { 4818 // op: Qd 4819 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4820 Value |= (op & UINT64_C(8)) << 19; 4821 Value |= (op & UINT64_C(7)) << 13; 4822 // op: Qm 4823 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4824 Value |= (op & UINT64_C(8)) << 2; 4825 Value |= (op & UINT64_C(7)) << 1; 4826 // op: imm 4827 op = getShiftRight32Imm(MI, 2, Fixups, STI); 4828 op &= UINT64_C(31); 4829 op <<= 16; 4830 Value |= op; 4831 break; 4832 } 4833 case ARM::MVE_VRSHR_imms8: 4834 case ARM::MVE_VRSHR_immu8: 4835 case ARM::MVE_VSHR_imms8: 4836 case ARM::MVE_VSHR_immu8: { 4837 // op: Qd 4838 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4839 Value |= (op & UINT64_C(8)) << 19; 4840 Value |= (op & UINT64_C(7)) << 13; 4841 // op: Qm 4842 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4843 Value |= (op & UINT64_C(8)) << 2; 4844 Value |= (op & UINT64_C(7)) << 1; 4845 // op: imm 4846 op = getShiftRight8Imm(MI, 2, Fixups, STI); 4847 op &= UINT64_C(7); 4848 op <<= 16; 4849 Value |= op; 4850 break; 4851 } 4852 case ARM::MVE_VCVTf16f32bh: 4853 case ARM::MVE_VCVTf16f32th: 4854 case ARM::MVE_VCVTf32f16bh: 4855 case ARM::MVE_VCVTf32f16th: 4856 case ARM::MVE_VMAXAs16: 4857 case ARM::MVE_VMAXAs32: 4858 case ARM::MVE_VMAXAs8: 4859 case ARM::MVE_VMAXNMAf16: 4860 case ARM::MVE_VMAXNMAf32: 4861 case ARM::MVE_VMINAs16: 4862 case ARM::MVE_VMINAs32: 4863 case ARM::MVE_VMINAs8: 4864 case ARM::MVE_VMINNMAf16: 4865 case ARM::MVE_VMINNMAf32: 4866 case ARM::MVE_VMOVNi16bh: 4867 case ARM::MVE_VMOVNi16th: 4868 case ARM::MVE_VMOVNi32bh: 4869 case ARM::MVE_VMOVNi32th: 4870 case ARM::MVE_VQMOVNs16bh: 4871 case ARM::MVE_VQMOVNs16th: 4872 case ARM::MVE_VQMOVNs32bh: 4873 case ARM::MVE_VQMOVNs32th: 4874 case ARM::MVE_VQMOVNu16bh: 4875 case ARM::MVE_VQMOVNu16th: 4876 case ARM::MVE_VQMOVNu32bh: 4877 case ARM::MVE_VQMOVNu32th: 4878 case ARM::MVE_VQMOVUNs16bh: 4879 case ARM::MVE_VQMOVUNs16th: 4880 case ARM::MVE_VQMOVUNs32bh: 4881 case ARM::MVE_VQMOVUNs32th: { 4882 // op: Qd 4883 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4884 Value |= (op & UINT64_C(8)) << 19; 4885 Value |= (op & UINT64_C(7)) << 13; 4886 // op: Qm 4887 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4888 Value |= (op & UINT64_C(8)) << 2; 4889 Value |= (op & UINT64_C(7)) << 1; 4890 break; 4891 } 4892 case ARM::MVE_VAND: 4893 case ARM::MVE_VBIC: 4894 case ARM::MVE_VEOR: 4895 case ARM::MVE_VMULHs16: 4896 case ARM::MVE_VMULHs32: 4897 case ARM::MVE_VMULHs8: 4898 case ARM::MVE_VMULHu16: 4899 case ARM::MVE_VMULHu32: 4900 case ARM::MVE_VMULHu8: 4901 case ARM::MVE_VMULLBp16: 4902 case ARM::MVE_VMULLBp8: 4903 case ARM::MVE_VMULLBs16: 4904 case ARM::MVE_VMULLBs32: 4905 case ARM::MVE_VMULLBs8: 4906 case ARM::MVE_VMULLBu16: 4907 case ARM::MVE_VMULLBu32: 4908 case ARM::MVE_VMULLBu8: 4909 case ARM::MVE_VMULLTp16: 4910 case ARM::MVE_VMULLTp8: 4911 case ARM::MVE_VMULLTs16: 4912 case ARM::MVE_VMULLTs32: 4913 case ARM::MVE_VMULLTs8: 4914 case ARM::MVE_VMULLTu16: 4915 case ARM::MVE_VMULLTu32: 4916 case ARM::MVE_VMULLTu8: 4917 case ARM::MVE_VORN: 4918 case ARM::MVE_VORR: 4919 case ARM::MVE_VQDMULLs16bh: 4920 case ARM::MVE_VQDMULLs16th: 4921 case ARM::MVE_VQDMULLs32bh: 4922 case ARM::MVE_VQDMULLs32th: 4923 case ARM::MVE_VRMULHs16: 4924 case ARM::MVE_VRMULHs32: 4925 case ARM::MVE_VRMULHs8: 4926 case ARM::MVE_VRMULHu16: 4927 case ARM::MVE_VRMULHu32: 4928 case ARM::MVE_VRMULHu8: { 4929 // op: Qd 4930 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4931 Value |= (op & UINT64_C(8)) << 19; 4932 Value |= (op & UINT64_C(7)) << 13; 4933 // op: Qm 4934 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4935 Value |= (op & UINT64_C(8)) << 2; 4936 Value |= (op & UINT64_C(7)) << 1; 4937 // op: Qn 4938 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4939 Value |= (op & UINT64_C(7)) << 17; 4940 Value |= (op & UINT64_C(8)) << 4; 4941 break; 4942 } 4943 case ARM::MVE_VCMULf16: 4944 case ARM::MVE_VCMULf32: { 4945 // op: Qd 4946 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4947 Value |= (op & UINT64_C(8)) << 19; 4948 Value |= (op & UINT64_C(7)) << 13; 4949 // op: Qm 4950 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4951 Value |= (op & UINT64_C(8)) << 2; 4952 Value |= (op & UINT64_C(7)) << 1; 4953 // op: Qn 4954 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4955 Value |= (op & UINT64_C(7)) << 17; 4956 Value |= (op & UINT64_C(8)) << 4; 4957 // op: rot 4958 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4959 Value |= (op & UINT64_C(2)) << 11; 4960 Value |= (op & UINT64_C(1)); 4961 break; 4962 } 4963 case ARM::MVE_VCADDi16: 4964 case ARM::MVE_VCADDi32: 4965 case ARM::MVE_VCADDi8: 4966 case ARM::MVE_VHCADDs16: 4967 case ARM::MVE_VHCADDs32: 4968 case ARM::MVE_VHCADDs8: { 4969 // op: Qd 4970 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4971 Value |= (op & UINT64_C(8)) << 19; 4972 Value |= (op & UINT64_C(7)) << 13; 4973 // op: Qm 4974 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4975 Value |= (op & UINT64_C(8)) << 2; 4976 Value |= (op & UINT64_C(7)) << 1; 4977 // op: Qn 4978 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4979 Value |= (op & UINT64_C(7)) << 17; 4980 Value |= (op & UINT64_C(8)) << 4; 4981 // op: rot 4982 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4983 op &= UINT64_C(1); 4984 op <<= 12; 4985 Value |= op; 4986 break; 4987 } 4988 case ARM::MVE_VSLIimm16: { 4989 // op: Qd 4990 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4991 Value |= (op & UINT64_C(8)) << 19; 4992 Value |= (op & UINT64_C(7)) << 13; 4993 // op: Qm 4994 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4995 Value |= (op & UINT64_C(8)) << 2; 4996 Value |= (op & UINT64_C(7)) << 1; 4997 // op: imm 4998 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4999 op &= UINT64_C(15); 5000 op <<= 16; 5001 Value |= op; 5002 break; 5003 } 5004 case ARM::MVE_VSLIimm32: { 5005 // op: Qd 5006 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5007 Value |= (op & UINT64_C(8)) << 19; 5008 Value |= (op & UINT64_C(7)) << 13; 5009 // op: Qm 5010 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5011 Value |= (op & UINT64_C(8)) << 2; 5012 Value |= (op & UINT64_C(7)) << 1; 5013 // op: imm 5014 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5015 op &= UINT64_C(31); 5016 op <<= 16; 5017 Value |= op; 5018 break; 5019 } 5020 case ARM::MVE_VSLIimm8: { 5021 // op: Qd 5022 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5023 Value |= (op & UINT64_C(8)) << 19; 5024 Value |= (op & UINT64_C(7)) << 13; 5025 // op: Qm 5026 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5027 Value |= (op & UINT64_C(8)) << 2; 5028 Value |= (op & UINT64_C(7)) << 1; 5029 // op: imm 5030 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5031 op &= UINT64_C(7); 5032 op <<= 16; 5033 Value |= op; 5034 break; 5035 } 5036 case ARM::MVE_VQRSHRNbhs32: 5037 case ARM::MVE_VQRSHRNbhu32: 5038 case ARM::MVE_VQRSHRNths32: 5039 case ARM::MVE_VQRSHRNthu32: 5040 case ARM::MVE_VQRSHRUNs32bh: 5041 case ARM::MVE_VQRSHRUNs32th: 5042 case ARM::MVE_VQSHRNbhs32: 5043 case ARM::MVE_VQSHRNbhu32: 5044 case ARM::MVE_VQSHRNths32: 5045 case ARM::MVE_VQSHRNthu32: 5046 case ARM::MVE_VQSHRUNs32bh: 5047 case ARM::MVE_VQSHRUNs32th: 5048 case ARM::MVE_VRSHRNi32bh: 5049 case ARM::MVE_VRSHRNi32th: 5050 case ARM::MVE_VSHRNi32bh: 5051 case ARM::MVE_VSHRNi32th: 5052 case ARM::MVE_VSRIimm16: { 5053 // op: Qd 5054 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5055 Value |= (op & UINT64_C(8)) << 19; 5056 Value |= (op & UINT64_C(7)) << 13; 5057 // op: Qm 5058 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5059 Value |= (op & UINT64_C(8)) << 2; 5060 Value |= (op & UINT64_C(7)) << 1; 5061 // op: imm 5062 op = getShiftRight16Imm(MI, 3, Fixups, STI); 5063 op &= UINT64_C(15); 5064 op <<= 16; 5065 Value |= op; 5066 break; 5067 } 5068 case ARM::MVE_VSRIimm32: { 5069 // op: Qd 5070 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5071 Value |= (op & UINT64_C(8)) << 19; 5072 Value |= (op & UINT64_C(7)) << 13; 5073 // op: Qm 5074 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5075 Value |= (op & UINT64_C(8)) << 2; 5076 Value |= (op & UINT64_C(7)) << 1; 5077 // op: imm 5078 op = getShiftRight32Imm(MI, 3, Fixups, STI); 5079 op &= UINT64_C(31); 5080 op <<= 16; 5081 Value |= op; 5082 break; 5083 } 5084 case ARM::MVE_VQRSHRNbhs16: 5085 case ARM::MVE_VQRSHRNbhu16: 5086 case ARM::MVE_VQRSHRNths16: 5087 case ARM::MVE_VQRSHRNthu16: 5088 case ARM::MVE_VQRSHRUNs16bh: 5089 case ARM::MVE_VQRSHRUNs16th: 5090 case ARM::MVE_VQSHRNbhs16: 5091 case ARM::MVE_VQSHRNbhu16: 5092 case ARM::MVE_VQSHRNths16: 5093 case ARM::MVE_VQSHRNthu16: 5094 case ARM::MVE_VQSHRUNs16bh: 5095 case ARM::MVE_VQSHRUNs16th: 5096 case ARM::MVE_VRSHRNi16bh: 5097 case ARM::MVE_VRSHRNi16th: 5098 case ARM::MVE_VSHRNi16bh: 5099 case ARM::MVE_VSHRNi16th: 5100 case ARM::MVE_VSRIimm8: { 5101 // op: Qd 5102 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5103 Value |= (op & UINT64_C(8)) << 19; 5104 Value |= (op & UINT64_C(7)) << 13; 5105 // op: Qm 5106 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5107 Value |= (op & UINT64_C(8)) << 2; 5108 Value |= (op & UINT64_C(7)) << 1; 5109 // op: imm 5110 op = getShiftRight8Imm(MI, 3, Fixups, STI); 5111 op &= UINT64_C(7); 5112 op <<= 16; 5113 Value |= op; 5114 break; 5115 } 5116 case ARM::MVE_VADC: 5117 case ARM::MVE_VADCI: 5118 case ARM::MVE_VQDMLADHXs16: 5119 case ARM::MVE_VQDMLADHXs32: 5120 case ARM::MVE_VQDMLADHXs8: 5121 case ARM::MVE_VQDMLADHs16: 5122 case ARM::MVE_VQDMLADHs32: 5123 case ARM::MVE_VQDMLADHs8: 5124 case ARM::MVE_VQDMLSDHXs16: 5125 case ARM::MVE_VQDMLSDHXs32: 5126 case ARM::MVE_VQDMLSDHXs8: 5127 case ARM::MVE_VQDMLSDHs16: 5128 case ARM::MVE_VQDMLSDHs32: 5129 case ARM::MVE_VQDMLSDHs8: 5130 case ARM::MVE_VQRDMLADHXs16: 5131 case ARM::MVE_VQRDMLADHXs32: 5132 case ARM::MVE_VQRDMLADHXs8: 5133 case ARM::MVE_VQRDMLADHs16: 5134 case ARM::MVE_VQRDMLADHs32: 5135 case ARM::MVE_VQRDMLADHs8: 5136 case ARM::MVE_VQRDMLSDHXs16: 5137 case ARM::MVE_VQRDMLSDHXs32: 5138 case ARM::MVE_VQRDMLSDHXs8: 5139 case ARM::MVE_VQRDMLSDHs16: 5140 case ARM::MVE_VQRDMLSDHs32: 5141 case ARM::MVE_VQRDMLSDHs8: 5142 case ARM::MVE_VSBC: 5143 case ARM::MVE_VSBCI: { 5144 // op: Qd 5145 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5146 Value |= (op & UINT64_C(8)) << 19; 5147 Value |= (op & UINT64_C(7)) << 13; 5148 // op: Qm 5149 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5150 Value |= (op & UINT64_C(8)) << 2; 5151 Value |= (op & UINT64_C(7)) << 1; 5152 // op: Qn 5153 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5154 Value |= (op & UINT64_C(7)) << 17; 5155 Value |= (op & UINT64_C(8)) << 4; 5156 break; 5157 } 5158 case ARM::MVE_VABDs16: 5159 case ARM::MVE_VABDs32: 5160 case ARM::MVE_VABDs8: 5161 case ARM::MVE_VABDu16: 5162 case ARM::MVE_VABDu32: 5163 case ARM::MVE_VABDu8: 5164 case ARM::MVE_VADDi16: 5165 case ARM::MVE_VADDi32: 5166 case ARM::MVE_VADDi8: 5167 case ARM::MVE_VHADDs16: 5168 case ARM::MVE_VHADDs32: 5169 case ARM::MVE_VHADDs8: 5170 case ARM::MVE_VHADDu16: 5171 case ARM::MVE_VHADDu32: 5172 case ARM::MVE_VHADDu8: 5173 case ARM::MVE_VHSUBs16: 5174 case ARM::MVE_VHSUBs32: 5175 case ARM::MVE_VHSUBs8: 5176 case ARM::MVE_VHSUBu16: 5177 case ARM::MVE_VHSUBu32: 5178 case ARM::MVE_VHSUBu8: 5179 case ARM::MVE_VMAXNMf16: 5180 case ARM::MVE_VMAXNMf32: 5181 case ARM::MVE_VMAXs16: 5182 case ARM::MVE_VMAXs32: 5183 case ARM::MVE_VMAXs8: 5184 case ARM::MVE_VMAXu16: 5185 case ARM::MVE_VMAXu32: 5186 case ARM::MVE_VMAXu8: 5187 case ARM::MVE_VMINNMf16: 5188 case ARM::MVE_VMINNMf32: 5189 case ARM::MVE_VMINs16: 5190 case ARM::MVE_VMINs32: 5191 case ARM::MVE_VMINs8: 5192 case ARM::MVE_VMINu16: 5193 case ARM::MVE_VMINu32: 5194 case ARM::MVE_VMINu8: 5195 case ARM::MVE_VMULi16: 5196 case ARM::MVE_VMULi32: 5197 case ARM::MVE_VMULi8: 5198 case ARM::MVE_VQADDs16: 5199 case ARM::MVE_VQADDs32: 5200 case ARM::MVE_VQADDs8: 5201 case ARM::MVE_VQADDu16: 5202 case ARM::MVE_VQADDu32: 5203 case ARM::MVE_VQADDu8: 5204 case ARM::MVE_VQDMULHi16: 5205 case ARM::MVE_VQDMULHi32: 5206 case ARM::MVE_VQDMULHi8: 5207 case ARM::MVE_VQRDMULHi16: 5208 case ARM::MVE_VQRDMULHi32: 5209 case ARM::MVE_VQRDMULHi8: 5210 case ARM::MVE_VQSUBs16: 5211 case ARM::MVE_VQSUBs32: 5212 case ARM::MVE_VQSUBs8: 5213 case ARM::MVE_VQSUBu16: 5214 case ARM::MVE_VQSUBu32: 5215 case ARM::MVE_VQSUBu8: 5216 case ARM::MVE_VRHADDs16: 5217 case ARM::MVE_VRHADDs32: 5218 case ARM::MVE_VRHADDs8: 5219 case ARM::MVE_VRHADDu16: 5220 case ARM::MVE_VRHADDu32: 5221 case ARM::MVE_VRHADDu8: 5222 case ARM::MVE_VSUBi16: 5223 case ARM::MVE_VSUBi32: 5224 case ARM::MVE_VSUBi8: { 5225 // op: Qd 5226 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5227 Value |= (op & UINT64_C(8)) << 19; 5228 Value |= (op & UINT64_C(7)) << 13; 5229 // op: Qn 5230 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5231 Value |= (op & UINT64_C(7)) << 17; 5232 Value |= (op & UINT64_C(8)) << 4; 5233 // op: Qm 5234 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5235 Value |= (op & UINT64_C(8)) << 2; 5236 Value |= (op & UINT64_C(7)) << 1; 5237 break; 5238 } 5239 case ARM::MVE_VADD_qr_f16: 5240 case ARM::MVE_VADD_qr_f32: 5241 case ARM::MVE_VADD_qr_i16: 5242 case ARM::MVE_VADD_qr_i32: 5243 case ARM::MVE_VADD_qr_i8: 5244 case ARM::MVE_VBRSR16: 5245 case ARM::MVE_VBRSR32: 5246 case ARM::MVE_VBRSR8: 5247 case ARM::MVE_VHADD_qr_s16: 5248 case ARM::MVE_VHADD_qr_s32: 5249 case ARM::MVE_VHADD_qr_s8: 5250 case ARM::MVE_VHADD_qr_u16: 5251 case ARM::MVE_VHADD_qr_u32: 5252 case ARM::MVE_VHADD_qr_u8: 5253 case ARM::MVE_VHSUB_qr_s16: 5254 case ARM::MVE_VHSUB_qr_s32: 5255 case ARM::MVE_VHSUB_qr_s8: 5256 case ARM::MVE_VHSUB_qr_u16: 5257 case ARM::MVE_VHSUB_qr_u32: 5258 case ARM::MVE_VHSUB_qr_u8: 5259 case ARM::MVE_VMUL_qr_f16: 5260 case ARM::MVE_VMUL_qr_f32: 5261 case ARM::MVE_VMUL_qr_i16: 5262 case ARM::MVE_VMUL_qr_i32: 5263 case ARM::MVE_VMUL_qr_i8: 5264 case ARM::MVE_VQADD_qr_s16: 5265 case ARM::MVE_VQADD_qr_s32: 5266 case ARM::MVE_VQADD_qr_s8: 5267 case ARM::MVE_VQADD_qr_u16: 5268 case ARM::MVE_VQADD_qr_u32: 5269 case ARM::MVE_VQADD_qr_u8: 5270 case ARM::MVE_VQDMULH_qr_s16: 5271 case ARM::MVE_VQDMULH_qr_s32: 5272 case ARM::MVE_VQDMULH_qr_s8: 5273 case ARM::MVE_VQDMULL_qr_s16bh: 5274 case ARM::MVE_VQDMULL_qr_s16th: 5275 case ARM::MVE_VQDMULL_qr_s32bh: 5276 case ARM::MVE_VQDMULL_qr_s32th: 5277 case ARM::MVE_VQRDMULH_qr_s16: 5278 case ARM::MVE_VQRDMULH_qr_s32: 5279 case ARM::MVE_VQRDMULH_qr_s8: 5280 case ARM::MVE_VQSUB_qr_s16: 5281 case ARM::MVE_VQSUB_qr_s32: 5282 case ARM::MVE_VQSUB_qr_s8: 5283 case ARM::MVE_VQSUB_qr_u16: 5284 case ARM::MVE_VQSUB_qr_u32: 5285 case ARM::MVE_VQSUB_qr_u8: 5286 case ARM::MVE_VSUB_qr_f16: 5287 case ARM::MVE_VSUB_qr_f32: 5288 case ARM::MVE_VSUB_qr_i16: 5289 case ARM::MVE_VSUB_qr_i32: 5290 case ARM::MVE_VSUB_qr_i8: { 5291 // op: Qd 5292 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5293 Value |= (op & UINT64_C(8)) << 19; 5294 Value |= (op & UINT64_C(7)) << 13; 5295 // op: Qn 5296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5297 Value |= (op & UINT64_C(7)) << 17; 5298 Value |= (op & UINT64_C(8)) << 4; 5299 // op: Rm 5300 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5301 op &= UINT64_C(15); 5302 Value |= op; 5303 break; 5304 } 5305 case ARM::MVE_VFMA_qr_Sf16: 5306 case ARM::MVE_VFMA_qr_Sf32: 5307 case ARM::MVE_VFMA_qr_f16: 5308 case ARM::MVE_VFMA_qr_f32: 5309 case ARM::MVE_VMLAS_qr_s16: 5310 case ARM::MVE_VMLAS_qr_s32: 5311 case ARM::MVE_VMLAS_qr_s8: 5312 case ARM::MVE_VMLAS_qr_u16: 5313 case ARM::MVE_VMLAS_qr_u32: 5314 case ARM::MVE_VMLAS_qr_u8: 5315 case ARM::MVE_VMLA_qr_s16: 5316 case ARM::MVE_VMLA_qr_s32: 5317 case ARM::MVE_VMLA_qr_s8: 5318 case ARM::MVE_VMLA_qr_u16: 5319 case ARM::MVE_VMLA_qr_u32: 5320 case ARM::MVE_VMLA_qr_u8: 5321 case ARM::MVE_VQDMLAH_qrs16: 5322 case ARM::MVE_VQDMLAH_qrs32: 5323 case ARM::MVE_VQDMLAH_qrs8: 5324 case ARM::MVE_VQDMLASH_qrs16: 5325 case ARM::MVE_VQDMLASH_qrs32: 5326 case ARM::MVE_VQDMLASH_qrs8: 5327 case ARM::MVE_VQRDMLAH_qrs16: 5328 case ARM::MVE_VQRDMLAH_qrs32: 5329 case ARM::MVE_VQRDMLAH_qrs8: 5330 case ARM::MVE_VQRDMLASH_qrs16: 5331 case ARM::MVE_VQRDMLASH_qrs32: 5332 case ARM::MVE_VQRDMLASH_qrs8: { 5333 // op: Qd 5334 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5335 Value |= (op & UINT64_C(8)) << 19; 5336 Value |= (op & UINT64_C(7)) << 13; 5337 // op: Qn 5338 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5339 Value |= (op & UINT64_C(7)) << 17; 5340 Value |= (op & UINT64_C(8)) << 4; 5341 // op: Rm 5342 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5343 op &= UINT64_C(15); 5344 Value |= op; 5345 break; 5346 } 5347 case ARM::MVE_VQRSHL_qrs16: 5348 case ARM::MVE_VQRSHL_qrs32: 5349 case ARM::MVE_VQRSHL_qrs8: 5350 case ARM::MVE_VQRSHL_qru16: 5351 case ARM::MVE_VQRSHL_qru32: 5352 case ARM::MVE_VQRSHL_qru8: 5353 case ARM::MVE_VQSHL_qrs16: 5354 case ARM::MVE_VQSHL_qrs32: 5355 case ARM::MVE_VQSHL_qrs8: 5356 case ARM::MVE_VQSHL_qru16: 5357 case ARM::MVE_VQSHL_qru32: 5358 case ARM::MVE_VQSHL_qru8: 5359 case ARM::MVE_VRSHL_qrs16: 5360 case ARM::MVE_VRSHL_qrs32: 5361 case ARM::MVE_VRSHL_qrs8: 5362 case ARM::MVE_VRSHL_qru16: 5363 case ARM::MVE_VRSHL_qru32: 5364 case ARM::MVE_VRSHL_qru8: 5365 case ARM::MVE_VSHL_qrs16: 5366 case ARM::MVE_VSHL_qrs32: 5367 case ARM::MVE_VSHL_qrs8: 5368 case ARM::MVE_VSHL_qru16: 5369 case ARM::MVE_VSHL_qru32: 5370 case ARM::MVE_VSHL_qru8: { 5371 // op: Qd 5372 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5373 Value |= (op & UINT64_C(8)) << 19; 5374 Value |= (op & UINT64_C(7)) << 13; 5375 // op: Rm 5376 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5377 op &= UINT64_C(15); 5378 Value |= op; 5379 break; 5380 } 5381 case ARM::MVE_VDWDUPu16: 5382 case ARM::MVE_VDWDUPu32: 5383 case ARM::MVE_VDWDUPu8: 5384 case ARM::MVE_VIWDUPu16: 5385 case ARM::MVE_VIWDUPu32: 5386 case ARM::MVE_VIWDUPu8: { 5387 // op: Qd 5388 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5389 Value |= (op & UINT64_C(8)) << 19; 5390 Value |= (op & UINT64_C(7)) << 13; 5391 // op: Rm 5392 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5393 op &= UINT64_C(14); 5394 Value |= op; 5395 // op: Rn 5396 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5397 op &= UINT64_C(14); 5398 op <<= 16; 5399 Value |= op; 5400 // op: imm 5401 op = getPowerTwoOpValue(MI, 4, Fixups, STI); 5402 Value |= (op & UINT64_C(2)) << 6; 5403 Value |= (op & UINT64_C(1)); 5404 break; 5405 } 5406 case ARM::MVE_VDDUPu16: 5407 case ARM::MVE_VDDUPu32: 5408 case ARM::MVE_VDDUPu8: 5409 case ARM::MVE_VIDUPu16: 5410 case ARM::MVE_VIDUPu32: 5411 case ARM::MVE_VIDUPu8: { 5412 // op: Qd 5413 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5414 Value |= (op & UINT64_C(8)) << 19; 5415 Value |= (op & UINT64_C(7)) << 13; 5416 // op: Rn 5417 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5418 op &= UINT64_C(14); 5419 op <<= 16; 5420 Value |= op; 5421 // op: imm 5422 op = getPowerTwoOpValue(MI, 3, Fixups, STI); 5423 Value |= (op & UINT64_C(2)) << 6; 5424 Value |= (op & UINT64_C(1)); 5425 break; 5426 } 5427 case ARM::MVE_VLDRWU32_qi: 5428 case ARM::MVE_VSTRW32_qi: { 5429 // op: Qd 5430 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5431 op &= UINT64_C(7); 5432 op <<= 13; 5433 Value |= op; 5434 // op: addr 5435 op = getMveAddrModeQOpValue<2>(MI, 1, Fixups, STI); 5436 Value |= (op & UINT64_C(128)) << 16; 5437 Value |= (op & UINT64_C(1792)) << 9; 5438 Value |= (op & UINT64_C(127)); 5439 break; 5440 } 5441 case ARM::MVE_VLDRDU64_qi: 5442 case ARM::MVE_VSTRD64_qi: { 5443 // op: Qd 5444 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5445 op &= UINT64_C(7); 5446 op <<= 13; 5447 Value |= op; 5448 // op: addr 5449 op = getMveAddrModeQOpValue<3>(MI, 1, Fixups, STI); 5450 Value |= (op & UINT64_C(128)) << 16; 5451 Value |= (op & UINT64_C(1792)) << 9; 5452 Value |= (op & UINT64_C(127)); 5453 break; 5454 } 5455 case ARM::MVE_VLDRBS16_rq: 5456 case ARM::MVE_VLDRBS32_rq: 5457 case ARM::MVE_VLDRBU16_rq: 5458 case ARM::MVE_VLDRBU32_rq: 5459 case ARM::MVE_VLDRBU8_rq: 5460 case ARM::MVE_VLDRDU64_rq: 5461 case ARM::MVE_VLDRDU64_rq_u: 5462 case ARM::MVE_VLDRHS32_rq: 5463 case ARM::MVE_VLDRHS32_rq_u: 5464 case ARM::MVE_VLDRHU16_rq: 5465 case ARM::MVE_VLDRHU16_rq_u: 5466 case ARM::MVE_VLDRHU32_rq: 5467 case ARM::MVE_VLDRHU32_rq_u: 5468 case ARM::MVE_VLDRWU32_rq: 5469 case ARM::MVE_VLDRWU32_rq_u: 5470 case ARM::MVE_VSTRB16_rq: 5471 case ARM::MVE_VSTRB32_rq: 5472 case ARM::MVE_VSTRB8_rq: 5473 case ARM::MVE_VSTRD64_rq: 5474 case ARM::MVE_VSTRD64_rq_u: 5475 case ARM::MVE_VSTRH16_rq: 5476 case ARM::MVE_VSTRH16_rq_u: 5477 case ARM::MVE_VSTRH32_rq: 5478 case ARM::MVE_VSTRH32_rq_u: 5479 case ARM::MVE_VSTRW32_rq: 5480 case ARM::MVE_VSTRW32_rq_u: { 5481 // op: Qd 5482 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5483 op &= UINT64_C(7); 5484 op <<= 13; 5485 Value |= op; 5486 // op: addr 5487 op = getMveAddrModeRQOpValue(MI, 1, Fixups, STI); 5488 Value |= (op & UINT64_C(120)) << 13; 5489 Value |= (op & UINT64_C(7)) << 1; 5490 break; 5491 } 5492 case ARM::MVE_VLDRBS16: 5493 case ARM::MVE_VLDRBS32: 5494 case ARM::MVE_VLDRBU16: 5495 case ARM::MVE_VLDRBU32: 5496 case ARM::MVE_VSTRB16: 5497 case ARM::MVE_VSTRB32: { 5498 // op: Qd 5499 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5500 op &= UINT64_C(7); 5501 op <<= 13; 5502 Value |= op; 5503 // op: addr 5504 op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI); 5505 Value |= (op & UINT64_C(128)) << 16; 5506 Value |= (op & UINT64_C(1792)) << 8; 5507 Value |= (op & UINT64_C(127)); 5508 break; 5509 } 5510 case ARM::MVE_VLDRBU8: 5511 case ARM::MVE_VSTRBU8: { 5512 // op: Qd 5513 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5514 op &= UINT64_C(7); 5515 op <<= 13; 5516 Value |= op; 5517 // op: addr 5518 op = getT2AddrModeImmOpValue<7,0>(MI, 1, Fixups, STI); 5519 Value |= (op & UINT64_C(128)) << 16; 5520 Value |= (op & UINT64_C(3840)) << 8; 5521 Value |= (op & UINT64_C(127)); 5522 break; 5523 } 5524 case ARM::MVE_VLDRHS32: 5525 case ARM::MVE_VLDRHU32: 5526 case ARM::MVE_VSTRH32: { 5527 // op: Qd 5528 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5529 op &= UINT64_C(7); 5530 op <<= 13; 5531 Value |= op; 5532 // op: addr 5533 op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI); 5534 Value |= (op & UINT64_C(128)) << 16; 5535 Value |= (op & UINT64_C(1792)) << 8; 5536 Value |= (op & UINT64_C(127)); 5537 break; 5538 } 5539 case ARM::MVE_VLDRHU16: 5540 case ARM::MVE_VSTRHU16: { 5541 // op: Qd 5542 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5543 op &= UINT64_C(7); 5544 op <<= 13; 5545 Value |= op; 5546 // op: addr 5547 op = getT2AddrModeImmOpValue<7,1>(MI, 1, Fixups, STI); 5548 Value |= (op & UINT64_C(128)) << 16; 5549 Value |= (op & UINT64_C(3840)) << 8; 5550 Value |= (op & UINT64_C(127)); 5551 break; 5552 } 5553 case ARM::MVE_VLDRWU32: 5554 case ARM::MVE_VSTRWU32: { 5555 // op: Qd 5556 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5557 op &= UINT64_C(7); 5558 op <<= 13; 5559 Value |= op; 5560 // op: addr 5561 op = getT2AddrModeImmOpValue<7,2>(MI, 1, Fixups, STI); 5562 Value |= (op & UINT64_C(128)) << 16; 5563 Value |= (op & UINT64_C(3840)) << 8; 5564 Value |= (op & UINT64_C(127)); 5565 break; 5566 } 5567 case ARM::MVE_VMOV_from_lane_32: { 5568 // op: Qd 5569 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5570 Value |= (op & UINT64_C(7)) << 17; 5571 Value |= (op & UINT64_C(8)) << 4; 5572 // op: Rt 5573 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5574 op &= UINT64_C(15); 5575 op <<= 12; 5576 Value |= op; 5577 // op: Idx 5578 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5579 Value |= (op & UINT64_C(1)) << 21; 5580 Value |= (op & UINT64_C(2)) << 15; 5581 break; 5582 } 5583 case ARM::MVE_VMOV_from_lane_s16: 5584 case ARM::MVE_VMOV_from_lane_u16: { 5585 // op: Qd 5586 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5587 Value |= (op & UINT64_C(7)) << 17; 5588 Value |= (op & UINT64_C(8)) << 4; 5589 // op: Rt 5590 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5591 op &= UINT64_C(15); 5592 op <<= 12; 5593 Value |= op; 5594 // op: Idx 5595 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5596 Value |= (op & UINT64_C(2)) << 20; 5597 Value |= (op & UINT64_C(4)) << 14; 5598 Value |= (op & UINT64_C(1)) << 6; 5599 break; 5600 } 5601 case ARM::MVE_VMOV_from_lane_s8: 5602 case ARM::MVE_VMOV_from_lane_u8: { 5603 // op: Qd 5604 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5605 Value |= (op & UINT64_C(7)) << 17; 5606 Value |= (op & UINT64_C(8)) << 4; 5607 // op: Rt 5608 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5609 op &= UINT64_C(15); 5610 op <<= 12; 5611 Value |= op; 5612 // op: Idx 5613 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5614 Value |= (op & UINT64_C(4)) << 19; 5615 Value |= (op & UINT64_C(8)) << 13; 5616 Value |= (op & UINT64_C(3)) << 5; 5617 break; 5618 } 5619 case ARM::MVE_VLDRWU32_qi_pre: 5620 case ARM::MVE_VSTRW32_qi_pre: { 5621 // op: Qd 5622 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5623 op &= UINT64_C(7); 5624 op <<= 13; 5625 Value |= op; 5626 // op: addr 5627 op = getMveAddrModeQOpValue<2>(MI, 2, Fixups, STI); 5628 Value |= (op & UINT64_C(128)) << 16; 5629 Value |= (op & UINT64_C(1792)) << 9; 5630 Value |= (op & UINT64_C(127)); 5631 break; 5632 } 5633 case ARM::MVE_VLDRDU64_qi_pre: 5634 case ARM::MVE_VSTRD64_qi_pre: { 5635 // op: Qd 5636 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5637 op &= UINT64_C(7); 5638 op <<= 13; 5639 Value |= op; 5640 // op: addr 5641 op = getMveAddrModeQOpValue<3>(MI, 2, Fixups, STI); 5642 Value |= (op & UINT64_C(128)) << 16; 5643 Value |= (op & UINT64_C(1792)) << 9; 5644 Value |= (op & UINT64_C(127)); 5645 break; 5646 } 5647 case ARM::MVE_VLDRBS16_pre: 5648 case ARM::MVE_VLDRBS32_pre: 5649 case ARM::MVE_VLDRBU16_pre: 5650 case ARM::MVE_VLDRBU32_pre: 5651 case ARM::MVE_VSTRB16_pre: 5652 case ARM::MVE_VSTRB32_pre: { 5653 // op: Qd 5654 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5655 op &= UINT64_C(7); 5656 op <<= 13; 5657 Value |= op; 5658 // op: addr 5659 op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI); 5660 Value |= (op & UINT64_C(128)) << 16; 5661 Value |= (op & UINT64_C(1792)) << 8; 5662 Value |= (op & UINT64_C(127)); 5663 break; 5664 } 5665 case ARM::MVE_VLDRBU8_pre: 5666 case ARM::MVE_VSTRBU8_pre: { 5667 // op: Qd 5668 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5669 op &= UINT64_C(7); 5670 op <<= 13; 5671 Value |= op; 5672 // op: addr 5673 op = getT2AddrModeImmOpValue<7,0>(MI, 2, Fixups, STI); 5674 Value |= (op & UINT64_C(128)) << 16; 5675 Value |= (op & UINT64_C(3840)) << 8; 5676 Value |= (op & UINT64_C(127)); 5677 break; 5678 } 5679 case ARM::MVE_VLDRHS32_pre: 5680 case ARM::MVE_VLDRHU32_pre: 5681 case ARM::MVE_VSTRH32_pre: { 5682 // op: Qd 5683 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5684 op &= UINT64_C(7); 5685 op <<= 13; 5686 Value |= op; 5687 // op: addr 5688 op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI); 5689 Value |= (op & UINT64_C(128)) << 16; 5690 Value |= (op & UINT64_C(1792)) << 8; 5691 Value |= (op & UINT64_C(127)); 5692 break; 5693 } 5694 case ARM::MVE_VLDRHU16_pre: 5695 case ARM::MVE_VSTRHU16_pre: { 5696 // op: Qd 5697 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5698 op &= UINT64_C(7); 5699 op <<= 13; 5700 Value |= op; 5701 // op: addr 5702 op = getT2AddrModeImmOpValue<7,1>(MI, 2, Fixups, STI); 5703 Value |= (op & UINT64_C(128)) << 16; 5704 Value |= (op & UINT64_C(3840)) << 8; 5705 Value |= (op & UINT64_C(127)); 5706 break; 5707 } 5708 case ARM::MVE_VLDRWU32_pre: 5709 case ARM::MVE_VSTRWU32_pre: { 5710 // op: Qd 5711 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5712 op &= UINT64_C(7); 5713 op <<= 13; 5714 Value |= op; 5715 // op: addr 5716 op = getT2AddrModeImmOpValue<7,2>(MI, 2, Fixups, STI); 5717 Value |= (op & UINT64_C(128)) << 16; 5718 Value |= (op & UINT64_C(3840)) << 8; 5719 Value |= (op & UINT64_C(127)); 5720 break; 5721 } 5722 case ARM::MVE_VLDRBU8_post: 5723 case ARM::MVE_VSTRBU8_post: { 5724 // op: Qd 5725 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5726 op &= UINT64_C(7); 5727 op <<= 13; 5728 Value |= op; 5729 // op: addr 5730 op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI); 5731 Value |= (op & UINT64_C(128)) << 16; 5732 Value |= (op & UINT64_C(127)); 5733 // op: Rn 5734 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5735 op &= UINT64_C(15); 5736 op <<= 16; 5737 Value |= op; 5738 break; 5739 } 5740 case ARM::MVE_VLDRBS16_post: 5741 case ARM::MVE_VLDRBS32_post: 5742 case ARM::MVE_VLDRBU16_post: 5743 case ARM::MVE_VLDRBU32_post: 5744 case ARM::MVE_VSTRB16_post: 5745 case ARM::MVE_VSTRB32_post: { 5746 // op: Qd 5747 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5748 op &= UINT64_C(7); 5749 op <<= 13; 5750 Value |= op; 5751 // op: addr 5752 op = getT2ScaledImmOpValue<7,0>(MI, 3, Fixups, STI); 5753 Value |= (op & UINT64_C(128)) << 16; 5754 Value |= (op & UINT64_C(127)); 5755 // op: Rn 5756 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5757 op &= UINT64_C(7); 5758 op <<= 16; 5759 Value |= op; 5760 break; 5761 } 5762 case ARM::MVE_VLDRHU16_post: 5763 case ARM::MVE_VSTRHU16_post: { 5764 // op: Qd 5765 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5766 op &= UINT64_C(7); 5767 op <<= 13; 5768 Value |= op; 5769 // op: addr 5770 op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI); 5771 Value |= (op & UINT64_C(128)) << 16; 5772 Value |= (op & UINT64_C(127)); 5773 // op: Rn 5774 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5775 op &= UINT64_C(15); 5776 op <<= 16; 5777 Value |= op; 5778 break; 5779 } 5780 case ARM::MVE_VLDRHS32_post: 5781 case ARM::MVE_VLDRHU32_post: 5782 case ARM::MVE_VSTRH32_post: { 5783 // op: Qd 5784 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5785 op &= UINT64_C(7); 5786 op <<= 13; 5787 Value |= op; 5788 // op: addr 5789 op = getT2ScaledImmOpValue<7,1>(MI, 3, Fixups, STI); 5790 Value |= (op & UINT64_C(128)) << 16; 5791 Value |= (op & UINT64_C(127)); 5792 // op: Rn 5793 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5794 op &= UINT64_C(7); 5795 op <<= 16; 5796 Value |= op; 5797 break; 5798 } 5799 case ARM::MVE_VLDRWU32_post: 5800 case ARM::MVE_VSTRWU32_post: { 5801 // op: Qd 5802 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5803 op &= UINT64_C(7); 5804 op <<= 13; 5805 Value |= op; 5806 // op: addr 5807 op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI); 5808 Value |= (op & UINT64_C(128)) << 16; 5809 Value |= (op & UINT64_C(127)); 5810 // op: Rn 5811 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5812 op &= UINT64_C(15); 5813 op <<= 16; 5814 Value |= op; 5815 break; 5816 } 5817 case ARM::MVE_VABSf16: 5818 case ARM::MVE_VABSf32: 5819 case ARM::MVE_VCVTf16s16n: 5820 case ARM::MVE_VCVTf16u16n: 5821 case ARM::MVE_VCVTf32s32n: 5822 case ARM::MVE_VCVTf32u32n: 5823 case ARM::MVE_VCVTs16f16a: 5824 case ARM::MVE_VCVTs16f16m: 5825 case ARM::MVE_VCVTs16f16n: 5826 case ARM::MVE_VCVTs16f16p: 5827 case ARM::MVE_VCVTs16f16z: 5828 case ARM::MVE_VCVTs32f32a: 5829 case ARM::MVE_VCVTs32f32m: 5830 case ARM::MVE_VCVTs32f32n: 5831 case ARM::MVE_VCVTs32f32p: 5832 case ARM::MVE_VCVTs32f32z: 5833 case ARM::MVE_VCVTu16f16a: 5834 case ARM::MVE_VCVTu16f16m: 5835 case ARM::MVE_VCVTu16f16n: 5836 case ARM::MVE_VCVTu16f16p: 5837 case ARM::MVE_VCVTu16f16z: 5838 case ARM::MVE_VCVTu32f32a: 5839 case ARM::MVE_VCVTu32f32m: 5840 case ARM::MVE_VCVTu32f32n: 5841 case ARM::MVE_VCVTu32f32p: 5842 case ARM::MVE_VCVTu32f32z: 5843 case ARM::MVE_VNEGf16: 5844 case ARM::MVE_VNEGf32: 5845 case ARM::MVE_VRINTf16A: 5846 case ARM::MVE_VRINTf16M: 5847 case ARM::MVE_VRINTf16N: 5848 case ARM::MVE_VRINTf16P: 5849 case ARM::MVE_VRINTf16X: 5850 case ARM::MVE_VRINTf16Z: 5851 case ARM::MVE_VRINTf32A: 5852 case ARM::MVE_VRINTf32M: 5853 case ARM::MVE_VRINTf32N: 5854 case ARM::MVE_VRINTf32P: 5855 case ARM::MVE_VRINTf32X: 5856 case ARM::MVE_VRINTf32Z: { 5857 // op: Qm 5858 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5859 Value |= (op & UINT64_C(8)) << 2; 5860 Value |= (op & UINT64_C(7)) << 1; 5861 // op: Qd 5862 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5863 Value |= (op & UINT64_C(8)) << 19; 5864 Value |= (op & UINT64_C(7)) << 13; 5865 break; 5866 } 5867 case ARM::MVE_VCVTf16s16_fix: 5868 case ARM::MVE_VCVTf16u16_fix: 5869 case ARM::MVE_VCVTs16f16_fix: 5870 case ARM::MVE_VCVTu16f16_fix: { 5871 // op: Qm 5872 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5873 Value |= (op & UINT64_C(8)) << 2; 5874 Value |= (op & UINT64_C(7)) << 1; 5875 // op: Qd 5876 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5877 Value |= (op & UINT64_C(8)) << 19; 5878 Value |= (op & UINT64_C(7)) << 13; 5879 // op: imm6 5880 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 5881 op &= UINT64_C(15); 5882 op <<= 16; 5883 Value |= op; 5884 break; 5885 } 5886 case ARM::MVE_VCVTf32s32_fix: 5887 case ARM::MVE_VCVTf32u32_fix: 5888 case ARM::MVE_VCVTs32f32_fix: 5889 case ARM::MVE_VCVTu32f32_fix: { 5890 // op: Qm 5891 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5892 Value |= (op & UINT64_C(8)) << 2; 5893 Value |= (op & UINT64_C(7)) << 1; 5894 // op: Qd 5895 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5896 Value |= (op & UINT64_C(8)) << 19; 5897 Value |= (op & UINT64_C(7)) << 13; 5898 // op: imm6 5899 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 5900 op &= UINT64_C(31); 5901 op <<= 16; 5902 Value |= op; 5903 break; 5904 } 5905 case ARM::MVE_VADDVs16no_acc: 5906 case ARM::MVE_VADDVs32no_acc: 5907 case ARM::MVE_VADDVs8no_acc: 5908 case ARM::MVE_VADDVu16no_acc: 5909 case ARM::MVE_VADDVu32no_acc: 5910 case ARM::MVE_VADDVu8no_acc: { 5911 // op: Qm 5912 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5913 op &= UINT64_C(7); 5914 op <<= 1; 5915 Value |= op; 5916 // op: Rda 5917 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5918 op &= UINT64_C(14); 5919 op <<= 12; 5920 Value |= op; 5921 break; 5922 } 5923 case ARM::MVE_VABDf16: 5924 case ARM::MVE_VABDf32: 5925 case ARM::MVE_VADDf16: 5926 case ARM::MVE_VADDf32: 5927 case ARM::MVE_VMULf16: 5928 case ARM::MVE_VMULf32: 5929 case ARM::MVE_VSUBf16: 5930 case ARM::MVE_VSUBf32: { 5931 // op: Qm 5932 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5933 Value |= (op & UINT64_C(8)) << 2; 5934 Value |= (op & UINT64_C(7)) << 1; 5935 // op: Qd 5936 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5937 Value |= (op & UINT64_C(8)) << 19; 5938 Value |= (op & UINT64_C(7)) << 13; 5939 // op: Qn 5940 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5941 Value |= (op & UINT64_C(7)) << 17; 5942 Value |= (op & UINT64_C(8)) << 4; 5943 break; 5944 } 5945 case ARM::MVE_VCADDf16: 5946 case ARM::MVE_VCADDf32: { 5947 // op: Qm 5948 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5949 Value |= (op & UINT64_C(8)) << 2; 5950 Value |= (op & UINT64_C(7)) << 1; 5951 // op: Qd 5952 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5953 Value |= (op & UINT64_C(8)) << 19; 5954 Value |= (op & UINT64_C(7)) << 13; 5955 // op: Qn 5956 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5957 Value |= (op & UINT64_C(7)) << 17; 5958 Value |= (op & UINT64_C(8)) << 4; 5959 // op: rot 5960 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5961 op &= UINT64_C(1); 5962 op <<= 24; 5963 Value |= op; 5964 break; 5965 } 5966 case ARM::MVE_VADDVs16acc: 5967 case ARM::MVE_VADDVs32acc: 5968 case ARM::MVE_VADDVs8acc: 5969 case ARM::MVE_VADDVu16acc: 5970 case ARM::MVE_VADDVu32acc: 5971 case ARM::MVE_VADDVu8acc: { 5972 // op: Qm 5973 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5974 op &= UINT64_C(7); 5975 op <<= 1; 5976 Value |= op; 5977 // op: Rda 5978 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5979 op &= UINT64_C(14); 5980 op <<= 12; 5981 Value |= op; 5982 break; 5983 } 5984 case ARM::MVE_VMAXAVs16: 5985 case ARM::MVE_VMAXAVs32: 5986 case ARM::MVE_VMAXAVs8: 5987 case ARM::MVE_VMAXNMAVf16: 5988 case ARM::MVE_VMAXNMAVf32: 5989 case ARM::MVE_VMAXNMVf16: 5990 case ARM::MVE_VMAXNMVf32: 5991 case ARM::MVE_VMAXVs16: 5992 case ARM::MVE_VMAXVs32: 5993 case ARM::MVE_VMAXVs8: 5994 case ARM::MVE_VMAXVu16: 5995 case ARM::MVE_VMAXVu32: 5996 case ARM::MVE_VMAXVu8: 5997 case ARM::MVE_VMINAVs16: 5998 case ARM::MVE_VMINAVs32: 5999 case ARM::MVE_VMINAVs8: 6000 case ARM::MVE_VMINNMAVf16: 6001 case ARM::MVE_VMINNMAVf32: 6002 case ARM::MVE_VMINNMVf16: 6003 case ARM::MVE_VMINNMVf32: 6004 case ARM::MVE_VMINVs16: 6005 case ARM::MVE_VMINVs32: 6006 case ARM::MVE_VMINVs8: 6007 case ARM::MVE_VMINVu16: 6008 case ARM::MVE_VMINVu32: 6009 case ARM::MVE_VMINVu8: { 6010 // op: Qm 6011 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6012 op &= UINT64_C(7); 6013 op <<= 1; 6014 Value |= op; 6015 // op: RdaDest 6016 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6017 op &= UINT64_C(15); 6018 op <<= 12; 6019 Value |= op; 6020 break; 6021 } 6022 case ARM::MVE_VADDLVs32no_acc: 6023 case ARM::MVE_VADDLVu32no_acc: { 6024 // op: Qm 6025 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6026 op &= UINT64_C(7); 6027 op <<= 1; 6028 Value |= op; 6029 // op: RdaLo 6030 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6031 op &= UINT64_C(14); 6032 op <<= 12; 6033 Value |= op; 6034 // op: RdaHi 6035 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6036 op &= UINT64_C(14); 6037 op <<= 19; 6038 Value |= op; 6039 break; 6040 } 6041 case ARM::MVE_VFMAf16: 6042 case ARM::MVE_VFMAf32: 6043 case ARM::MVE_VFMSf16: 6044 case ARM::MVE_VFMSf32: { 6045 // op: Qm 6046 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6047 Value |= (op & UINT64_C(8)) << 2; 6048 Value |= (op & UINT64_C(7)) << 1; 6049 // op: Qd 6050 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6051 Value |= (op & UINT64_C(8)) << 19; 6052 Value |= (op & UINT64_C(7)) << 13; 6053 // op: Qn 6054 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6055 Value |= (op & UINT64_C(7)) << 17; 6056 Value |= (op & UINT64_C(8)) << 4; 6057 break; 6058 } 6059 case ARM::MVE_VCMLAf16: 6060 case ARM::MVE_VCMLAf32: { 6061 // op: Qm 6062 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6063 Value |= (op & UINT64_C(8)) << 2; 6064 Value |= (op & UINT64_C(7)) << 1; 6065 // op: Qd 6066 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6067 Value |= (op & UINT64_C(8)) << 19; 6068 Value |= (op & UINT64_C(7)) << 13; 6069 // op: Qn 6070 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6071 Value |= (op & UINT64_C(7)) << 17; 6072 Value |= (op & UINT64_C(8)) << 4; 6073 // op: rot 6074 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6075 op &= UINT64_C(3); 6076 op <<= 23; 6077 Value |= op; 6078 break; 6079 } 6080 case ARM::MVE_VABAVs16: 6081 case ARM::MVE_VABAVs32: 6082 case ARM::MVE_VABAVs8: 6083 case ARM::MVE_VABAVu16: 6084 case ARM::MVE_VABAVu32: 6085 case ARM::MVE_VABAVu8: { 6086 // op: Qm 6087 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6088 Value |= (op & UINT64_C(8)) << 2; 6089 Value |= (op & UINT64_C(7)) << 1; 6090 // op: Qn 6091 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6092 Value |= (op & UINT64_C(7)) << 17; 6093 Value |= (op & UINT64_C(8)) << 4; 6094 // op: Rda 6095 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6096 op &= UINT64_C(15); 6097 op <<= 12; 6098 Value |= op; 6099 break; 6100 } 6101 case ARM::MVE_VADDLVs32acc: 6102 case ARM::MVE_VADDLVu32acc: { 6103 // op: Qm 6104 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6105 op &= UINT64_C(7); 6106 op <<= 1; 6107 Value |= op; 6108 // op: RdaLo 6109 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6110 op &= UINT64_C(14); 6111 op <<= 12; 6112 Value |= op; 6113 // op: RdaHi 6114 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6115 op &= UINT64_C(14); 6116 op <<= 19; 6117 Value |= op; 6118 break; 6119 } 6120 case ARM::MVE_VPSEL: { 6121 // op: Qn 6122 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6123 Value |= (op & UINT64_C(7)) << 17; 6124 Value |= (op & UINT64_C(8)) << 4; 6125 // op: Qd 6126 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6127 Value |= (op & UINT64_C(8)) << 19; 6128 Value |= (op & UINT64_C(7)) << 13; 6129 // op: Qm 6130 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6131 Value |= (op & UINT64_C(8)) << 2; 6132 Value |= (op & UINT64_C(7)) << 1; 6133 break; 6134 } 6135 case ARM::tMOVr: { 6136 // op: Rd 6137 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6138 Value |= (op & UINT64_C(8)) << 4; 6139 Value |= (op & UINT64_C(7)); 6140 // op: Rm 6141 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6142 op &= UINT64_C(15); 6143 op <<= 3; 6144 Value |= op; 6145 break; 6146 } 6147 case ARM::t2STLEX: { 6148 // op: Rd 6149 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6150 op &= UINT64_C(15); 6151 Value |= op; 6152 // op: Rt 6153 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6154 op &= UINT64_C(15); 6155 op <<= 12; 6156 Value |= op; 6157 // op: addr 6158 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6159 op &= UINT64_C(15); 6160 op <<= 16; 6161 Value |= op; 6162 break; 6163 } 6164 case ARM::t2STLEXB: 6165 case ARM::t2STLEXH: 6166 case ARM::t2STREXB: 6167 case ARM::t2STREXH: { 6168 // op: Rd 6169 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6170 op &= UINT64_C(15); 6171 Value |= op; 6172 // op: addr 6173 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6174 op &= UINT64_C(15); 6175 op <<= 16; 6176 Value |= op; 6177 // op: Rt 6178 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6179 op &= UINT64_C(15); 6180 op <<= 12; 6181 Value |= op; 6182 break; 6183 } 6184 case ARM::t2STLEXD: 6185 case ARM::t2STREXD: { 6186 // op: Rd 6187 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6188 op &= UINT64_C(15); 6189 Value |= op; 6190 // op: addr 6191 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6192 op &= UINT64_C(15); 6193 op <<= 16; 6194 Value |= op; 6195 // op: Rt 6196 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6197 op &= UINT64_C(15); 6198 op <<= 12; 6199 Value |= op; 6200 // op: Rt2 6201 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6202 op &= UINT64_C(15); 6203 op <<= 8; 6204 Value |= op; 6205 break; 6206 } 6207 case ARM::CRC32B: 6208 case ARM::CRC32CB: 6209 case ARM::CRC32CH: 6210 case ARM::CRC32CW: 6211 case ARM::CRC32H: 6212 case ARM::CRC32W: { 6213 // op: Rd 6214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6215 op &= UINT64_C(15); 6216 op <<= 12; 6217 Value |= op; 6218 // op: Rn 6219 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6220 op &= UINT64_C(15); 6221 op <<= 16; 6222 Value |= op; 6223 // op: Rm 6224 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6225 op &= UINT64_C(15); 6226 Value |= op; 6227 break; 6228 } 6229 case ARM::t2MRS_AR: 6230 case ARM::t2MRSsys_AR: { 6231 // op: Rd 6232 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6233 op &= UINT64_C(15); 6234 op <<= 8; 6235 Value |= op; 6236 break; 6237 } 6238 case ARM::t2CLZ: 6239 case ARM::t2RBIT: 6240 case ARM::t2REV: 6241 case ARM::t2REV16: 6242 case ARM::t2REVSH: { 6243 // op: Rd 6244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6245 op &= UINT64_C(15); 6246 op <<= 8; 6247 Value |= op; 6248 // op: Rm 6249 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6250 Value |= (op & UINT64_C(15)) << 16; 6251 Value |= (op & UINT64_C(15)); 6252 break; 6253 } 6254 case ARM::t2MOVsra_flag: 6255 case ARM::t2MOVsrl_flag: { 6256 // op: Rd 6257 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6258 op &= UINT64_C(15); 6259 op <<= 8; 6260 Value |= op; 6261 // op: Rm 6262 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6263 op &= UINT64_C(15); 6264 Value |= op; 6265 break; 6266 } 6267 case ARM::t2SXTB: 6268 case ARM::t2SXTB16: 6269 case ARM::t2SXTH: 6270 case ARM::t2UXTB: 6271 case ARM::t2UXTB16: 6272 case ARM::t2UXTH: { 6273 // op: Rd 6274 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6275 op &= UINT64_C(15); 6276 op <<= 8; 6277 Value |= op; 6278 // op: Rm 6279 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6280 op &= UINT64_C(15); 6281 Value |= op; 6282 // op: rot 6283 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6284 op &= UINT64_C(3); 6285 op <<= 4; 6286 Value |= op; 6287 break; 6288 } 6289 case ARM::t2CSEL: 6290 case ARM::t2CSINC: 6291 case ARM::t2CSINV: 6292 case ARM::t2CSNEG: { 6293 // op: Rd 6294 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6295 op &= UINT64_C(15); 6296 op <<= 8; 6297 Value |= op; 6298 // op: Rm 6299 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6300 op &= UINT64_C(15); 6301 Value |= op; 6302 // op: Rn 6303 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6304 op &= UINT64_C(15); 6305 op <<= 16; 6306 Value |= op; 6307 // op: fcond 6308 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6309 op &= UINT64_C(15); 6310 op <<= 4; 6311 Value |= op; 6312 break; 6313 } 6314 case ARM::t2CRC32B: 6315 case ARM::t2CRC32CB: 6316 case ARM::t2CRC32CH: 6317 case ARM::t2CRC32CW: 6318 case ARM::t2CRC32H: 6319 case ARM::t2CRC32W: 6320 case ARM::t2MUL: 6321 case ARM::t2QADD16: 6322 case ARM::t2QADD8: 6323 case ARM::t2QASX: 6324 case ARM::t2QSAX: 6325 case ARM::t2QSUB16: 6326 case ARM::t2QSUB8: 6327 case ARM::t2SADD16: 6328 case ARM::t2SADD8: 6329 case ARM::t2SASX: 6330 case ARM::t2SDIV: 6331 case ARM::t2SEL: 6332 case ARM::t2SHADD16: 6333 case ARM::t2SHADD8: 6334 case ARM::t2SHASX: 6335 case ARM::t2SHSAX: 6336 case ARM::t2SHSUB16: 6337 case ARM::t2SHSUB8: 6338 case ARM::t2SMMUL: 6339 case ARM::t2SMMULR: 6340 case ARM::t2SMUAD: 6341 case ARM::t2SMUADX: 6342 case ARM::t2SMULBB: 6343 case ARM::t2SMULBT: 6344 case ARM::t2SMULTB: 6345 case ARM::t2SMULTT: 6346 case ARM::t2SMULWB: 6347 case ARM::t2SMULWT: 6348 case ARM::t2SMUSD: 6349 case ARM::t2SMUSDX: 6350 case ARM::t2SSAX: 6351 case ARM::t2SSUB16: 6352 case ARM::t2SSUB8: 6353 case ARM::t2UADD16: 6354 case ARM::t2UADD8: 6355 case ARM::t2UASX: 6356 case ARM::t2UDIV: 6357 case ARM::t2UHADD16: 6358 case ARM::t2UHADD8: 6359 case ARM::t2UHASX: 6360 case ARM::t2UHSAX: 6361 case ARM::t2UHSUB16: 6362 case ARM::t2UHSUB8: 6363 case ARM::t2UQADD16: 6364 case ARM::t2UQADD8: 6365 case ARM::t2UQASX: 6366 case ARM::t2UQSAX: 6367 case ARM::t2UQSUB16: 6368 case ARM::t2UQSUB8: 6369 case ARM::t2USAD8: 6370 case ARM::t2USAX: 6371 case ARM::t2USUB16: 6372 case ARM::t2USUB8: { 6373 // op: Rd 6374 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6375 op &= UINT64_C(15); 6376 op <<= 8; 6377 Value |= op; 6378 // op: Rn 6379 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6380 op &= UINT64_C(15); 6381 op <<= 16; 6382 Value |= op; 6383 // op: Rm 6384 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6385 op &= UINT64_C(15); 6386 Value |= op; 6387 break; 6388 } 6389 case ARM::t2MLA: 6390 case ARM::t2MLS: 6391 case ARM::t2SMLABB: 6392 case ARM::t2SMLABT: 6393 case ARM::t2SMLAD: 6394 case ARM::t2SMLADX: 6395 case ARM::t2SMLATB: 6396 case ARM::t2SMLATT: 6397 case ARM::t2SMLAWB: 6398 case ARM::t2SMLAWT: 6399 case ARM::t2SMLSD: 6400 case ARM::t2SMLSDX: 6401 case ARM::t2SMMLA: 6402 case ARM::t2SMMLAR: 6403 case ARM::t2SMMLS: 6404 case ARM::t2SMMLSR: 6405 case ARM::t2USADA8: { 6406 // op: Rd 6407 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6408 op &= UINT64_C(15); 6409 op <<= 8; 6410 Value |= op; 6411 // op: Rn 6412 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6413 op &= UINT64_C(15); 6414 op <<= 16; 6415 Value |= op; 6416 // op: Rm 6417 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6418 op &= UINT64_C(15); 6419 Value |= op; 6420 // op: Ra 6421 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6422 op &= UINT64_C(15); 6423 op <<= 12; 6424 Value |= op; 6425 break; 6426 } 6427 case ARM::t2SXTAB: 6428 case ARM::t2SXTAB16: 6429 case ARM::t2SXTAH: 6430 case ARM::t2UXTAB: 6431 case ARM::t2UXTAB16: 6432 case ARM::t2UXTAH: { 6433 // op: Rd 6434 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6435 op &= UINT64_C(15); 6436 op <<= 8; 6437 Value |= op; 6438 // op: Rn 6439 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6440 op &= UINT64_C(15); 6441 op <<= 16; 6442 Value |= op; 6443 // op: Rm 6444 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6445 op &= UINT64_C(15); 6446 Value |= op; 6447 // op: rot 6448 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6449 op &= UINT64_C(3); 6450 op <<= 4; 6451 Value |= op; 6452 break; 6453 } 6454 case ARM::t2PKHBT: 6455 case ARM::t2PKHTB: { 6456 // op: Rd 6457 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6458 op &= UINT64_C(15); 6459 op <<= 8; 6460 Value |= op; 6461 // op: Rn 6462 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6463 op &= UINT64_C(15); 6464 op <<= 16; 6465 Value |= op; 6466 // op: Rm 6467 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6468 op &= UINT64_C(15); 6469 Value |= op; 6470 // op: sh 6471 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6472 Value |= (op & UINT64_C(28)) << 10; 6473 Value |= (op & UINT64_C(3)) << 6; 6474 break; 6475 } 6476 case ARM::t2ADDri12: 6477 case ARM::t2SUBri12: { 6478 // op: Rd 6479 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6480 op &= UINT64_C(15); 6481 op <<= 8; 6482 Value |= op; 6483 // op: Rn 6484 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6485 op &= UINT64_C(15); 6486 op <<= 16; 6487 Value |= op; 6488 // op: imm 6489 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6490 Value |= (op & UINT64_C(2048)) << 15; 6491 Value |= (op & UINT64_C(1792)) << 4; 6492 Value |= (op & UINT64_C(255)); 6493 break; 6494 } 6495 case ARM::t2QADD: 6496 case ARM::t2QDADD: 6497 case ARM::t2QDSUB: 6498 case ARM::t2QSUB: { 6499 // op: Rd 6500 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6501 op &= UINT64_C(15); 6502 op <<= 8; 6503 Value |= op; 6504 // op: Rn 6505 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6506 op &= UINT64_C(15); 6507 op <<= 16; 6508 Value |= op; 6509 // op: Rm 6510 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6511 op &= UINT64_C(15); 6512 Value |= op; 6513 break; 6514 } 6515 case ARM::t2BFI: { 6516 // op: Rd 6517 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6518 op &= UINT64_C(15); 6519 op <<= 8; 6520 Value |= op; 6521 // op: Rn 6522 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6523 op &= UINT64_C(15); 6524 op <<= 16; 6525 Value |= op; 6526 // op: imm 6527 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 6528 Value |= (op & UINT64_C(28)) << 10; 6529 Value |= (op & UINT64_C(3)) << 6; 6530 Value |= (op & UINT64_C(992)) >> 5; 6531 break; 6532 } 6533 case ARM::t2SSAT16: 6534 case ARM::t2USAT16: { 6535 // op: Rd 6536 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6537 op &= UINT64_C(15); 6538 op <<= 8; 6539 Value |= op; 6540 // op: Rn 6541 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6542 op &= UINT64_C(15); 6543 op <<= 16; 6544 Value |= op; 6545 // op: sat_imm 6546 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6547 op &= UINT64_C(15); 6548 Value |= op; 6549 break; 6550 } 6551 case ARM::t2SSAT: 6552 case ARM::t2USAT: { 6553 // op: Rd 6554 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6555 op &= UINT64_C(15); 6556 op <<= 8; 6557 Value |= op; 6558 // op: Rn 6559 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6560 op &= UINT64_C(15); 6561 op <<= 16; 6562 Value |= op; 6563 // op: sat_imm 6564 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6565 op &= UINT64_C(31); 6566 Value |= op; 6567 // op: sh 6568 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6569 Value |= (op & UINT64_C(32)) << 16; 6570 Value |= (op & UINT64_C(28)) << 10; 6571 Value |= (op & UINT64_C(3)) << 6; 6572 break; 6573 } 6574 case ARM::t2STREX: { 6575 // op: Rd 6576 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6577 op &= UINT64_C(15); 6578 op <<= 8; 6579 Value |= op; 6580 // op: Rt 6581 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6582 op &= UINT64_C(15); 6583 op <<= 12; 6584 Value |= op; 6585 // op: addr 6586 op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI); 6587 Value |= (op & UINT64_C(3840)) << 8; 6588 Value |= (op & UINT64_C(255)); 6589 break; 6590 } 6591 case ARM::t2MRS_M: { 6592 // op: Rd 6593 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6594 op &= UINT64_C(15); 6595 op <<= 8; 6596 Value |= op; 6597 // op: SYSm 6598 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6599 op &= UINT64_C(255); 6600 Value |= op; 6601 break; 6602 } 6603 case ARM::t2ADR: { 6604 // op: Rd 6605 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6606 op &= UINT64_C(15); 6607 op <<= 8; 6608 Value |= op; 6609 // op: addr 6610 op = getT2AdrLabelOpValue(MI, 1, Fixups, STI); 6611 Value |= (op & UINT64_C(2048)) << 15; 6612 Value |= (op & UINT64_C(4096)) << 11; 6613 Value |= (op & UINT64_C(4096)) << 9; 6614 Value |= (op & UINT64_C(1792)) << 4; 6615 Value |= (op & UINT64_C(255)); 6616 break; 6617 } 6618 case ARM::t2BFC: { 6619 // op: Rd 6620 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6621 op &= UINT64_C(15); 6622 op <<= 8; 6623 Value |= op; 6624 // op: imm 6625 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 6626 Value |= (op & UINT64_C(28)) << 10; 6627 Value |= (op & UINT64_C(3)) << 6; 6628 Value |= (op & UINT64_C(992)) >> 5; 6629 break; 6630 } 6631 case ARM::t2MOVi16: { 6632 // op: Rd 6633 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6634 op &= UINT64_C(15); 6635 op <<= 8; 6636 Value |= op; 6637 // op: imm 6638 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 6639 Value |= (op & UINT64_C(2048)) << 15; 6640 Value |= (op & UINT64_C(61440)) << 4; 6641 Value |= (op & UINT64_C(1792)) << 4; 6642 Value |= (op & UINT64_C(255)); 6643 break; 6644 } 6645 case ARM::t2MOVTi16: { 6646 // op: Rd 6647 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6648 op &= UINT64_C(15); 6649 op <<= 8; 6650 Value |= op; 6651 // op: imm 6652 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 6653 Value |= (op & UINT64_C(2048)) << 15; 6654 Value |= (op & UINT64_C(61440)) << 4; 6655 Value |= (op & UINT64_C(1792)) << 4; 6656 Value |= (op & UINT64_C(255)); 6657 break; 6658 } 6659 case ARM::t2SBFX: 6660 case ARM::t2UBFX: { 6661 // op: Rd 6662 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6663 op &= UINT64_C(15); 6664 op <<= 8; 6665 Value |= op; 6666 // op: msb 6667 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6668 op &= UINT64_C(31); 6669 Value |= op; 6670 // op: lsb 6671 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6672 Value |= (op & UINT64_C(28)) << 10; 6673 Value |= (op & UINT64_C(3)) << 6; 6674 // op: Rn 6675 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6676 op &= UINT64_C(15); 6677 op <<= 16; 6678 Value |= op; 6679 break; 6680 } 6681 case ARM::tMOVSr: { 6682 // op: Rd 6683 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6684 op &= UINT64_C(7); 6685 Value |= op; 6686 // op: Rm 6687 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6688 op &= UINT64_C(7); 6689 op <<= 3; 6690 Value |= op; 6691 break; 6692 } 6693 case ARM::tADDi3: 6694 case ARM::tSUBi3: { 6695 // op: Rd 6696 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6697 op &= UINT64_C(7); 6698 Value |= op; 6699 // op: Rm 6700 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6701 op &= UINT64_C(7); 6702 op <<= 3; 6703 Value |= op; 6704 // op: imm3 6705 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6706 op &= UINT64_C(7); 6707 op <<= 6; 6708 Value |= op; 6709 break; 6710 } 6711 case ARM::tASRri: 6712 case ARM::tLSLri: 6713 case ARM::tLSRri: { 6714 // op: Rd 6715 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6716 op &= UINT64_C(7); 6717 Value |= op; 6718 // op: Rm 6719 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6720 op &= UINT64_C(7); 6721 op <<= 3; 6722 Value |= op; 6723 // op: imm5 6724 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6725 op &= UINT64_C(31); 6726 op <<= 6; 6727 Value |= op; 6728 break; 6729 } 6730 case ARM::tMUL: 6731 case ARM::tMVN: 6732 case ARM::tRSB: { 6733 // op: Rd 6734 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6735 op &= UINT64_C(7); 6736 Value |= op; 6737 // op: Rn 6738 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6739 op &= UINT64_C(7); 6740 op <<= 3; 6741 Value |= op; 6742 break; 6743 } 6744 case ARM::tADR: { 6745 // op: Rd 6746 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6747 op &= UINT64_C(7); 6748 op <<= 8; 6749 Value |= op; 6750 // op: addr 6751 op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI); 6752 op &= UINT64_C(255); 6753 Value |= op; 6754 break; 6755 } 6756 case ARM::tMOVi8: { 6757 // op: Rd 6758 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6759 op &= UINT64_C(7); 6760 op <<= 8; 6761 Value |= op; 6762 // op: imm8 6763 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6764 op &= UINT64_C(255); 6765 Value |= op; 6766 break; 6767 } 6768 case ARM::t2SMLALD: 6769 case ARM::t2SMLALDX: 6770 case ARM::t2SMLSLD: 6771 case ARM::t2SMLSLDX: { 6772 // op: Rd 6773 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6774 op &= UINT64_C(15); 6775 op <<= 8; 6776 Value |= op; 6777 // op: Rn 6778 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6779 op &= UINT64_C(15); 6780 op <<= 16; 6781 Value |= op; 6782 // op: Rm 6783 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6784 op &= UINT64_C(15); 6785 Value |= op; 6786 // op: Ra 6787 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6788 op &= UINT64_C(15); 6789 op <<= 12; 6790 Value |= op; 6791 break; 6792 } 6793 case ARM::t2SMLAL: 6794 case ARM::t2SMLALBB: 6795 case ARM::t2SMLALBT: 6796 case ARM::t2SMLALTB: 6797 case ARM::t2SMLALTT: 6798 case ARM::t2SMULL: 6799 case ARM::t2UMAAL: 6800 case ARM::t2UMLAL: 6801 case ARM::t2UMULL: { 6802 // op: RdLo 6803 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6804 op &= UINT64_C(15); 6805 op <<= 12; 6806 Value |= op; 6807 // op: RdHi 6808 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6809 op &= UINT64_C(15); 6810 op <<= 8; 6811 Value |= op; 6812 // op: Rn 6813 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6814 op &= UINT64_C(15); 6815 op <<= 16; 6816 Value |= op; 6817 // op: Rm 6818 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6819 op &= UINT64_C(15); 6820 Value |= op; 6821 break; 6822 } 6823 case ARM::MVE_VMLADAVs16: 6824 case ARM::MVE_VMLADAVs32: 6825 case ARM::MVE_VMLADAVs8: 6826 case ARM::MVE_VMLADAVu16: 6827 case ARM::MVE_VMLADAVu32: 6828 case ARM::MVE_VMLADAVu8: 6829 case ARM::MVE_VMLADAVxs16: 6830 case ARM::MVE_VMLADAVxs32: 6831 case ARM::MVE_VMLADAVxs8: 6832 case ARM::MVE_VMLSDAVs16: 6833 case ARM::MVE_VMLSDAVs32: 6834 case ARM::MVE_VMLSDAVs8: 6835 case ARM::MVE_VMLSDAVxs16: 6836 case ARM::MVE_VMLSDAVxs32: 6837 case ARM::MVE_VMLSDAVxs8: { 6838 // op: RdaDest 6839 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6840 op &= UINT64_C(14); 6841 op <<= 12; 6842 Value |= op; 6843 // op: Qm 6844 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6845 op &= UINT64_C(7); 6846 op <<= 1; 6847 Value |= op; 6848 // op: Qn 6849 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6850 op &= UINT64_C(7); 6851 op <<= 17; 6852 Value |= op; 6853 break; 6854 } 6855 case ARM::MVE_VMLADAVas16: 6856 case ARM::MVE_VMLADAVas32: 6857 case ARM::MVE_VMLADAVas8: 6858 case ARM::MVE_VMLADAVau16: 6859 case ARM::MVE_VMLADAVau32: 6860 case ARM::MVE_VMLADAVau8: 6861 case ARM::MVE_VMLADAVaxs16: 6862 case ARM::MVE_VMLADAVaxs32: 6863 case ARM::MVE_VMLADAVaxs8: 6864 case ARM::MVE_VMLSDAVas16: 6865 case ARM::MVE_VMLSDAVas32: 6866 case ARM::MVE_VMLSDAVas8: 6867 case ARM::MVE_VMLSDAVaxs16: 6868 case ARM::MVE_VMLSDAVaxs32: 6869 case ARM::MVE_VMLSDAVaxs8: { 6870 // op: RdaDest 6871 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6872 op &= UINT64_C(14); 6873 op <<= 12; 6874 Value |= op; 6875 // op: Qm 6876 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6877 op &= UINT64_C(7); 6878 op <<= 1; 6879 Value |= op; 6880 // op: Qn 6881 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6882 op &= UINT64_C(7); 6883 op <<= 17; 6884 Value |= op; 6885 break; 6886 } 6887 case ARM::MVE_SQRSHR: 6888 case ARM::MVE_UQRSHL: { 6889 // op: RdaDest 6890 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6891 op &= UINT64_C(15); 6892 op <<= 16; 6893 Value |= op; 6894 // op: Rm 6895 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6896 op &= UINT64_C(15); 6897 op <<= 12; 6898 Value |= op; 6899 break; 6900 } 6901 case ARM::MVE_SQSHL: 6902 case ARM::MVE_SRSHR: 6903 case ARM::MVE_UQSHL: 6904 case ARM::MVE_URSHR: { 6905 // op: RdaDest 6906 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6907 op &= UINT64_C(15); 6908 op <<= 16; 6909 Value |= op; 6910 // op: imm 6911 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6912 Value |= (op & UINT64_C(28)) << 10; 6913 Value |= (op & UINT64_C(3)) << 6; 6914 break; 6915 } 6916 case ARM::MVE_ASRLr: 6917 case ARM::MVE_LSLLr: { 6918 // op: RdaLo 6919 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6920 op &= UINT64_C(14); 6921 op <<= 16; 6922 Value |= op; 6923 // op: RdaHi 6924 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6925 op &= UINT64_C(14); 6926 op <<= 8; 6927 Value |= op; 6928 // op: Rm 6929 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6930 op &= UINT64_C(15); 6931 op <<= 12; 6932 Value |= op; 6933 break; 6934 } 6935 case ARM::MVE_SQRSHRL: 6936 case ARM::MVE_UQRSHLL: { 6937 // op: RdaLo 6938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6939 op &= UINT64_C(14); 6940 op <<= 16; 6941 Value |= op; 6942 // op: RdaHi 6943 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6944 op &= UINT64_C(14); 6945 op <<= 8; 6946 Value |= op; 6947 // op: Rm 6948 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6949 op &= UINT64_C(15); 6950 op <<= 12; 6951 Value |= op; 6952 // op: sat 6953 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 6954 op &= UINT64_C(1); 6955 op <<= 7; 6956 Value |= op; 6957 break; 6958 } 6959 case ARM::MVE_ASRLi: 6960 case ARM::MVE_LSLLi: 6961 case ARM::MVE_LSRL: 6962 case ARM::MVE_SQSHLL: 6963 case ARM::MVE_SRSHRL: 6964 case ARM::MVE_UQSHLL: 6965 case ARM::MVE_URSHRL: { 6966 // op: RdaLo 6967 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6968 op &= UINT64_C(14); 6969 op <<= 16; 6970 Value |= op; 6971 // op: RdaHi 6972 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6973 op &= UINT64_C(14); 6974 op <<= 8; 6975 Value |= op; 6976 // op: imm 6977 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 6978 Value |= (op & UINT64_C(28)) << 10; 6979 Value |= (op & UINT64_C(3)) << 6; 6980 break; 6981 } 6982 case ARM::MVE_VMLALDAVs16: 6983 case ARM::MVE_VMLALDAVs32: 6984 case ARM::MVE_VMLALDAVu16: 6985 case ARM::MVE_VMLALDAVu32: 6986 case ARM::MVE_VMLALDAVxs16: 6987 case ARM::MVE_VMLALDAVxs32: 6988 case ARM::MVE_VMLSLDAVs16: 6989 case ARM::MVE_VMLSLDAVs32: 6990 case ARM::MVE_VMLSLDAVxs16: 6991 case ARM::MVE_VMLSLDAVxs32: 6992 case ARM::MVE_VRMLALDAVHs32: 6993 case ARM::MVE_VRMLALDAVHu32: 6994 case ARM::MVE_VRMLALDAVHxs32: 6995 case ARM::MVE_VRMLSLDAVHs32: 6996 case ARM::MVE_VRMLSLDAVHxs32: { 6997 // op: RdaLoDest 6998 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6999 op &= UINT64_C(14); 7000 op <<= 12; 7001 Value |= op; 7002 // op: RdaHiDest 7003 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7004 op &= UINT64_C(14); 7005 op <<= 19; 7006 Value |= op; 7007 // op: Qm 7008 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7009 op &= UINT64_C(7); 7010 op <<= 1; 7011 Value |= op; 7012 // op: Qn 7013 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7014 op &= UINT64_C(7); 7015 op <<= 17; 7016 Value |= op; 7017 break; 7018 } 7019 case ARM::MVE_VMLALDAVas16: 7020 case ARM::MVE_VMLALDAVas32: 7021 case ARM::MVE_VMLALDAVau16: 7022 case ARM::MVE_VMLALDAVau32: 7023 case ARM::MVE_VMLALDAVaxs16: 7024 case ARM::MVE_VMLALDAVaxs32: 7025 case ARM::MVE_VMLSLDAVas16: 7026 case ARM::MVE_VMLSLDAVas32: 7027 case ARM::MVE_VMLSLDAVaxs16: 7028 case ARM::MVE_VMLSLDAVaxs32: 7029 case ARM::MVE_VRMLALDAVHas32: 7030 case ARM::MVE_VRMLALDAVHau32: 7031 case ARM::MVE_VRMLALDAVHaxs32: 7032 case ARM::MVE_VRMLSLDAVHas32: 7033 case ARM::MVE_VRMLSLDAVHaxs32: { 7034 // op: RdaLoDest 7035 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7036 op &= UINT64_C(14); 7037 op <<= 12; 7038 Value |= op; 7039 // op: RdaHiDest 7040 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7041 op &= UINT64_C(14); 7042 op <<= 19; 7043 Value |= op; 7044 // op: Qm 7045 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7046 op &= UINT64_C(7); 7047 op <<= 1; 7048 Value |= op; 7049 // op: Qn 7050 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7051 op &= UINT64_C(7); 7052 op <<= 17; 7053 Value |= op; 7054 break; 7055 } 7056 case ARM::tADDrSP: { 7057 // op: Rdn 7058 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7059 Value |= (op & UINT64_C(8)) << 4; 7060 Value |= (op & UINT64_C(7)); 7061 break; 7062 } 7063 case ARM::tADDhirr: { 7064 // op: Rdn 7065 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7066 Value |= (op & UINT64_C(8)) << 4; 7067 Value |= (op & UINT64_C(7)); 7068 // op: Rm 7069 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7070 op &= UINT64_C(15); 7071 op <<= 3; 7072 Value |= op; 7073 break; 7074 } 7075 case ARM::tADC: 7076 case ARM::tAND: 7077 case ARM::tASRrr: 7078 case ARM::tBIC: 7079 case ARM::tEOR: 7080 case ARM::tLSLrr: 7081 case ARM::tLSRrr: 7082 case ARM::tORR: 7083 case ARM::tROR: 7084 case ARM::tSBC: { 7085 // op: Rdn 7086 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7087 op &= UINT64_C(7); 7088 Value |= op; 7089 // op: Rm 7090 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7091 op &= UINT64_C(7); 7092 op <<= 3; 7093 Value |= op; 7094 break; 7095 } 7096 case ARM::tADDi8: 7097 case ARM::tSUBi8: { 7098 // op: Rdn 7099 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7100 op &= UINT64_C(7); 7101 op <<= 8; 7102 Value |= op; 7103 // op: imm8 7104 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7105 op &= UINT64_C(255); 7106 Value |= op; 7107 break; 7108 } 7109 case ARM::tBX: 7110 case ARM::tBXNS: { 7111 // op: Rm 7112 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7113 op &= UINT64_C(15); 7114 op <<= 3; 7115 Value |= op; 7116 break; 7117 } 7118 case ARM::tCMPhir: { 7119 // op: Rm 7120 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7121 op &= UINT64_C(15); 7122 op <<= 3; 7123 Value |= op; 7124 // op: Rn 7125 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7126 Value |= (op & UINT64_C(8)) << 4; 7127 Value |= (op & UINT64_C(7)); 7128 break; 7129 } 7130 case ARM::tREV: 7131 case ARM::tREV16: 7132 case ARM::tREVSH: 7133 case ARM::tSXTB: 7134 case ARM::tSXTH: 7135 case ARM::tUXTB: 7136 case ARM::tUXTH: { 7137 // op: Rm 7138 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7139 op &= UINT64_C(7); 7140 op <<= 3; 7141 Value |= op; 7142 // op: Rd 7143 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7144 op &= UINT64_C(7); 7145 Value |= op; 7146 break; 7147 } 7148 case ARM::tCMNz: 7149 case ARM::tCMPr: 7150 case ARM::tTST: { 7151 // op: Rm 7152 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7153 op &= UINT64_C(7); 7154 op <<= 3; 7155 Value |= op; 7156 // op: Rn 7157 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7158 op &= UINT64_C(7); 7159 Value |= op; 7160 break; 7161 } 7162 case ARM::tADDspr: { 7163 // op: Rm 7164 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7165 op &= UINT64_C(15); 7166 op <<= 3; 7167 Value |= op; 7168 break; 7169 } 7170 case ARM::tADDrr: 7171 case ARM::tSUBrr: { 7172 // op: Rm 7173 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7174 op &= UINT64_C(7); 7175 op <<= 6; 7176 Value |= op; 7177 // op: Rn 7178 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7179 op &= UINT64_C(7); 7180 op <<= 3; 7181 Value |= op; 7182 // op: Rd 7183 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7184 op &= UINT64_C(7); 7185 Value |= op; 7186 break; 7187 } 7188 case ARM::RFEDA: 7189 case ARM::RFEDA_UPD: 7190 case ARM::RFEDB: 7191 case ARM::RFEDB_UPD: 7192 case ARM::RFEIA: 7193 case ARM::RFEIA_UPD: 7194 case ARM::RFEIB: 7195 case ARM::RFEIB_UPD: 7196 case ARM::t2RFEDB: 7197 case ARM::t2RFEDBW: 7198 case ARM::t2RFEIA: 7199 case ARM::t2RFEIAW: { 7200 // op: Rn 7201 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7202 op &= UINT64_C(15); 7203 op <<= 16; 7204 Value |= op; 7205 break; 7206 } 7207 case ARM::t2CMNzrr: 7208 case ARM::t2CMPrr: 7209 case ARM::t2TBB: 7210 case ARM::t2TBH: 7211 case ARM::t2TEQrr: 7212 case ARM::t2TSTrr: { 7213 // op: Rn 7214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7215 op &= UINT64_C(15); 7216 op <<= 16; 7217 Value |= op; 7218 // op: Rm 7219 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7220 op &= UINT64_C(15); 7221 Value |= op; 7222 break; 7223 } 7224 case ARM::t2CMNzrs: 7225 case ARM::t2CMPrs: 7226 case ARM::t2TEQrs: 7227 case ARM::t2TSTrs: { 7228 // op: Rn 7229 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7230 op &= UINT64_C(15); 7231 op <<= 16; 7232 Value |= op; 7233 // op: ShiftedRm 7234 op = getT2SORegOpValue(MI, 1, Fixups, STI); 7235 Value |= (op & UINT64_C(3584)) << 3; 7236 Value |= (op & UINT64_C(480)) >> 1; 7237 Value |= (op & UINT64_C(15)); 7238 break; 7239 } 7240 case ARM::t2CMNri: 7241 case ARM::t2CMPri: 7242 case ARM::t2TEQri: 7243 case ARM::t2TSTri: { 7244 // op: Rn 7245 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7246 op &= UINT64_C(15); 7247 op <<= 16; 7248 Value |= op; 7249 // op: imm 7250 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 7251 Value |= (op & UINT64_C(2048)) << 15; 7252 Value |= (op & UINT64_C(1792)) << 4; 7253 Value |= (op & UINT64_C(255)); 7254 break; 7255 } 7256 case ARM::t2STMDB: 7257 case ARM::t2STMIA: { 7258 // op: Rn 7259 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7260 op &= UINT64_C(15); 7261 op <<= 16; 7262 Value |= op; 7263 // op: regs 7264 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7265 Value |= (op & UINT64_C(16384)); 7266 Value |= (op & UINT64_C(8191)); 7267 break; 7268 } 7269 case ARM::t2LDMDB: 7270 case ARM::t2LDMIA: { 7271 // op: Rn 7272 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7273 op &= UINT64_C(15); 7274 op <<= 16; 7275 Value |= op; 7276 // op: regs 7277 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7278 op &= UINT64_C(65535); 7279 Value |= op; 7280 break; 7281 } 7282 case ARM::tCMPi8: { 7283 // op: Rn 7284 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7285 op &= UINT64_C(7); 7286 op <<= 8; 7287 Value |= op; 7288 // op: imm8 7289 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7290 op &= UINT64_C(255); 7291 Value |= op; 7292 break; 7293 } 7294 case ARM::tLDMIA: { 7295 // op: Rn 7296 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7297 op &= UINT64_C(7); 7298 op <<= 8; 7299 Value |= op; 7300 // op: regs 7301 op = getRegisterListOpValue(MI, 3, Fixups, STI); 7302 op &= UINT64_C(255); 7303 Value |= op; 7304 break; 7305 } 7306 case ARM::MVE_DLSTP_16: 7307 case ARM::MVE_DLSTP_32: 7308 case ARM::MVE_DLSTP_64: 7309 case ARM::MVE_DLSTP_8: 7310 case ARM::MVE_VCTP16: 7311 case ARM::MVE_VCTP32: 7312 case ARM::MVE_VCTP64: 7313 case ARM::MVE_VCTP8: 7314 case ARM::t2DLS: { 7315 // op: Rn 7316 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7317 op &= UINT64_C(15); 7318 op <<= 16; 7319 Value |= op; 7320 break; 7321 } 7322 case ARM::t2TT: 7323 case ARM::t2TTA: 7324 case ARM::t2TTAT: 7325 case ARM::t2TTT: { 7326 // op: Rn 7327 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7328 op &= UINT64_C(15); 7329 op <<= 16; 7330 Value |= op; 7331 // op: Rt 7332 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7333 op &= UINT64_C(15); 7334 op <<= 8; 7335 Value |= op; 7336 break; 7337 } 7338 case ARM::MVE_WLSTP_16: 7339 case ARM::MVE_WLSTP_32: 7340 case ARM::MVE_WLSTP_64: 7341 case ARM::MVE_WLSTP_8: 7342 case ARM::t2WLS: { 7343 // op: Rn 7344 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7345 op &= UINT64_C(15); 7346 op <<= 16; 7347 Value |= op; 7348 // op: label 7349 op = getBFTargetOpValue<false, ARM::fixup_wls>(MI, 2, Fixups, STI); 7350 Value |= (op & UINT64_C(1)) << 11; 7351 Value |= (op & UINT64_C(2046)); 7352 break; 7353 } 7354 case ARM::t2STMDB_UPD: 7355 case ARM::t2STMIA_UPD: { 7356 // op: Rn 7357 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7358 op &= UINT64_C(15); 7359 op <<= 16; 7360 Value |= op; 7361 // op: regs 7362 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7363 Value |= (op & UINT64_C(16384)); 7364 Value |= (op & UINT64_C(8191)); 7365 break; 7366 } 7367 case ARM::t2LDMDB_UPD: 7368 case ARM::t2LDMIA_UPD: { 7369 // op: Rn 7370 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7371 op &= UINT64_C(15); 7372 op <<= 16; 7373 Value |= op; 7374 // op: regs 7375 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7376 op &= UINT64_C(65535); 7377 Value |= op; 7378 break; 7379 } 7380 case ARM::tSTMIA_UPD: { 7381 // op: Rn 7382 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7383 op &= UINT64_C(7); 7384 op <<= 8; 7385 Value |= op; 7386 // op: regs 7387 op = getRegisterListOpValue(MI, 4, Fixups, STI); 7388 op &= UINT64_C(255); 7389 Value |= op; 7390 break; 7391 } 7392 case ARM::MVE_VMOV_rr_q: { 7393 // op: Rt 7394 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7395 op &= UINT64_C(15); 7396 Value |= op; 7397 // op: Rt2 7398 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7399 op &= UINT64_C(15); 7400 op <<= 16; 7401 Value |= op; 7402 // op: Qd 7403 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7404 Value |= (op & UINT64_C(8)) << 19; 7405 Value |= (op & UINT64_C(7)) << 13; 7406 // op: idx2 7407 op = getMVEPairVectorIndexOpValue<0>(MI, 4, Fixups, STI); 7408 op &= UINT64_C(1); 7409 op <<= 4; 7410 Value |= op; 7411 break; 7412 } 7413 case ARM::t2LDRB_POST: 7414 case ARM::t2LDRH_POST: 7415 case ARM::t2LDRSB_POST: 7416 case ARM::t2LDRSH_POST: 7417 case ARM::t2LDR_POST: { 7418 // op: Rt 7419 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7420 op &= UINT64_C(15); 7421 op <<= 12; 7422 Value |= op; 7423 // op: Rn 7424 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7425 op &= UINT64_C(15); 7426 op <<= 16; 7427 Value |= op; 7428 // op: offset 7429 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 7430 Value |= (op & UINT64_C(256)) << 1; 7431 Value |= (op & UINT64_C(255)); 7432 break; 7433 } 7434 case ARM::MRRC2: 7435 case ARM::t2MRRC: 7436 case ARM::t2MRRC2: { 7437 // op: Rt 7438 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7439 op &= UINT64_C(15); 7440 op <<= 12; 7441 Value |= op; 7442 // op: Rt2 7443 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7444 op &= UINT64_C(15); 7445 op <<= 16; 7446 Value |= op; 7447 // op: cop 7448 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7449 op &= UINT64_C(15); 7450 op <<= 8; 7451 Value |= op; 7452 // op: opc1 7453 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7454 op &= UINT64_C(15); 7455 op <<= 4; 7456 Value |= op; 7457 // op: CRm 7458 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7459 op &= UINT64_C(15); 7460 Value |= op; 7461 break; 7462 } 7463 case ARM::t2LDRD_POST: { 7464 // op: Rt 7465 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7466 op &= UINT64_C(15); 7467 op <<= 12; 7468 Value |= op; 7469 // op: Rt2 7470 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7471 op &= UINT64_C(15); 7472 op <<= 8; 7473 Value |= op; 7474 // op: addr 7475 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7476 op &= UINT64_C(15); 7477 op <<= 16; 7478 Value |= op; 7479 // op: imm 7480 op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI); 7481 Value |= (op & UINT64_C(256)) << 15; 7482 Value |= (op & UINT64_C(255)); 7483 break; 7484 } 7485 case ARM::t2LDRDi8: 7486 case ARM::t2STRDi8: { 7487 // op: Rt 7488 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7489 op &= UINT64_C(15); 7490 op <<= 12; 7491 Value |= op; 7492 // op: Rt2 7493 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7494 op &= UINT64_C(15); 7495 op <<= 8; 7496 Value |= op; 7497 // op: addr 7498 op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI); 7499 Value |= (op & UINT64_C(256)) << 15; 7500 Value |= (op & UINT64_C(7680)) << 7; 7501 Value |= (op & UINT64_C(255)); 7502 break; 7503 } 7504 case ARM::t2LDRD_PRE: { 7505 // op: Rt 7506 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7507 op &= UINT64_C(15); 7508 op <<= 12; 7509 Value |= op; 7510 // op: Rt2 7511 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7512 op &= UINT64_C(15); 7513 op <<= 8; 7514 Value |= op; 7515 // op: addr 7516 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 7517 Value |= (op & UINT64_C(256)) << 15; 7518 Value |= (op & UINT64_C(7680)) << 7; 7519 Value |= (op & UINT64_C(255)); 7520 break; 7521 } 7522 case ARM::t2LDRBi12: 7523 case ARM::t2LDRHi12: 7524 case ARM::t2LDRSBi12: 7525 case ARM::t2LDRSHi12: 7526 case ARM::t2LDRi12: 7527 case ARM::t2STRBi12: 7528 case ARM::t2STRHi12: 7529 case ARM::t2STRi12: { 7530 // op: Rt 7531 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7532 op &= UINT64_C(15); 7533 op <<= 12; 7534 Value |= op; 7535 // op: addr 7536 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 7537 Value |= (op & UINT64_C(122880)) << 3; 7538 Value |= (op & UINT64_C(4095)); 7539 break; 7540 } 7541 case ARM::t2LDRBpci: 7542 case ARM::t2LDRHpci: 7543 case ARM::t2LDRSBpci: 7544 case ARM::t2LDRSHpci: 7545 case ARM::t2LDRpci: { 7546 // op: Rt 7547 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7548 op &= UINT64_C(15); 7549 op <<= 12; 7550 Value |= op; 7551 // op: addr 7552 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 7553 Value |= (op & UINT64_C(4096)) << 11; 7554 Value |= (op & UINT64_C(4095)); 7555 break; 7556 } 7557 case ARM::t2LDA: 7558 case ARM::t2LDAB: 7559 case ARM::t2LDAEX: 7560 case ARM::t2LDAH: 7561 case ARM::t2STL: 7562 case ARM::t2STLB: 7563 case ARM::t2STLH: { 7564 // op: Rt 7565 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7566 op &= UINT64_C(15); 7567 op <<= 12; 7568 Value |= op; 7569 // op: addr 7570 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7571 op &= UINT64_C(15); 7572 op <<= 16; 7573 Value |= op; 7574 break; 7575 } 7576 case ARM::t2LDREX: { 7577 // op: Rt 7578 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7579 op &= UINT64_C(15); 7580 op <<= 12; 7581 Value |= op; 7582 // op: addr 7583 op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI); 7584 Value |= (op & UINT64_C(3840)) << 8; 7585 Value |= (op & UINT64_C(255)); 7586 break; 7587 } 7588 case ARM::t2LDRBT: 7589 case ARM::t2LDRHT: 7590 case ARM::t2LDRSBT: 7591 case ARM::t2LDRSHT: 7592 case ARM::t2LDRT: 7593 case ARM::t2STRBT: 7594 case ARM::t2STRHT: 7595 case ARM::t2STRT: { 7596 // op: Rt 7597 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7598 op &= UINT64_C(15); 7599 op <<= 12; 7600 Value |= op; 7601 // op: addr 7602 op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI); 7603 Value |= (op & UINT64_C(7680)) << 7; 7604 Value |= (op & UINT64_C(255)); 7605 break; 7606 } 7607 case ARM::t2LDRBi8: 7608 case ARM::t2LDRHi8: 7609 case ARM::t2LDRSBi8: 7610 case ARM::t2LDRSHi8: 7611 case ARM::t2LDRi8: 7612 case ARM::t2STRBi8: 7613 case ARM::t2STRHi8: 7614 case ARM::t2STRi8: { 7615 // op: Rt 7616 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7617 op &= UINT64_C(15); 7618 op <<= 12; 7619 Value |= op; 7620 // op: addr 7621 op = getT2AddrModeImmOpValue<8,0>(MI, 1, Fixups, STI); 7622 Value |= (op & UINT64_C(7680)) << 7; 7623 Value |= (op & UINT64_C(256)) << 1; 7624 Value |= (op & UINT64_C(255)); 7625 break; 7626 } 7627 case ARM::t2LDRB_PRE: 7628 case ARM::t2LDRH_PRE: 7629 case ARM::t2LDRSB_PRE: 7630 case ARM::t2LDRSH_PRE: 7631 case ARM::t2LDR_PRE: { 7632 // op: Rt 7633 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7634 op &= UINT64_C(15); 7635 op <<= 12; 7636 Value |= op; 7637 // op: addr 7638 op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI); 7639 Value |= (op & UINT64_C(7680)) << 7; 7640 Value |= (op & UINT64_C(256)) << 1; 7641 Value |= (op & UINT64_C(255)); 7642 break; 7643 } 7644 case ARM::t2LDRBs: 7645 case ARM::t2LDRHs: 7646 case ARM::t2LDRSBs: 7647 case ARM::t2LDRSHs: 7648 case ARM::t2LDRs: 7649 case ARM::t2STRBs: 7650 case ARM::t2STRHs: 7651 case ARM::t2STRs: { 7652 // op: Rt 7653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7654 op &= UINT64_C(15); 7655 op <<= 12; 7656 Value |= op; 7657 // op: addr 7658 op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI); 7659 Value |= (op & UINT64_C(960)) << 10; 7660 Value |= (op & UINT64_C(3)) << 4; 7661 Value |= (op & UINT64_C(60)) >> 2; 7662 break; 7663 } 7664 case ARM::MRC2: 7665 case ARM::t2MRC: 7666 case ARM::t2MRC2: { 7667 // op: Rt 7668 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7669 op &= UINT64_C(15); 7670 op <<= 12; 7671 Value |= op; 7672 // op: cop 7673 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7674 op &= UINT64_C(15); 7675 op <<= 8; 7676 Value |= op; 7677 // op: opc1 7678 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7679 op &= UINT64_C(7); 7680 op <<= 21; 7681 Value |= op; 7682 // op: opc2 7683 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7684 op &= UINT64_C(7); 7685 op <<= 5; 7686 Value |= op; 7687 // op: CRm 7688 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7689 op &= UINT64_C(15); 7690 Value |= op; 7691 // op: CRn 7692 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7693 op &= UINT64_C(15); 7694 op <<= 16; 7695 Value |= op; 7696 break; 7697 } 7698 case ARM::tLDRBi: 7699 case ARM::tLDRHi: 7700 case ARM::tLDRi: 7701 case ARM::tSTRBi: 7702 case ARM::tSTRHi: 7703 case ARM::tSTRi: { 7704 // op: Rt 7705 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7706 op &= UINT64_C(7); 7707 Value |= op; 7708 // op: addr 7709 op = getAddrModeISOpValue(MI, 1, Fixups, STI); 7710 op &= UINT64_C(255); 7711 op <<= 3; 7712 Value |= op; 7713 break; 7714 } 7715 case ARM::tLDRBr: 7716 case ARM::tLDRHr: 7717 case ARM::tLDRSB: 7718 case ARM::tLDRSH: 7719 case ARM::tLDRr: 7720 case ARM::tSTRBr: 7721 case ARM::tSTRHr: 7722 case ARM::tSTRr: { 7723 // op: Rt 7724 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7725 op &= UINT64_C(7); 7726 Value |= op; 7727 // op: addr 7728 op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI); 7729 op &= UINT64_C(63); 7730 op <<= 3; 7731 Value |= op; 7732 break; 7733 } 7734 case ARM::tLDRpci: { 7735 // op: Rt 7736 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7737 op &= UINT64_C(7); 7738 op <<= 8; 7739 Value |= op; 7740 // op: addr 7741 op = getAddrModePCOpValue(MI, 1, Fixups, STI); 7742 op &= UINT64_C(255); 7743 Value |= op; 7744 break; 7745 } 7746 case ARM::tLDRspi: 7747 case ARM::tSTRspi: { 7748 // op: Rt 7749 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7750 op &= UINT64_C(7); 7751 op <<= 8; 7752 Value |= op; 7753 // op: addr 7754 op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI); 7755 op &= UINT64_C(255); 7756 Value |= op; 7757 break; 7758 } 7759 case ARM::t2STRB_POST: 7760 case ARM::t2STRH_POST: 7761 case ARM::t2STR_POST: { 7762 // op: Rt 7763 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7764 op &= UINT64_C(15); 7765 op <<= 12; 7766 Value |= op; 7767 // op: Rn 7768 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7769 op &= UINT64_C(15); 7770 op <<= 16; 7771 Value |= op; 7772 // op: offset 7773 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 7774 Value |= (op & UINT64_C(256)) << 1; 7775 Value |= (op & UINT64_C(255)); 7776 break; 7777 } 7778 case ARM::t2STRD_POST: { 7779 // op: Rt 7780 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7781 op &= UINT64_C(15); 7782 op <<= 12; 7783 Value |= op; 7784 // op: Rt2 7785 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7786 op &= UINT64_C(15); 7787 op <<= 8; 7788 Value |= op; 7789 // op: addr 7790 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7791 op &= UINT64_C(15); 7792 op <<= 16; 7793 Value |= op; 7794 // op: imm 7795 op = getT2ScaledImmOpValue<8,2>(MI, 4, Fixups, STI); 7796 Value |= (op & UINT64_C(256)) << 15; 7797 Value |= (op & UINT64_C(255)); 7798 break; 7799 } 7800 case ARM::t2STRD_PRE: { 7801 // op: Rt 7802 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7803 op &= UINT64_C(15); 7804 op <<= 12; 7805 Value |= op; 7806 // op: Rt2 7807 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7808 op &= UINT64_C(15); 7809 op <<= 8; 7810 Value |= op; 7811 // op: addr 7812 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 7813 Value |= (op & UINT64_C(256)) << 15; 7814 Value |= (op & UINT64_C(7680)) << 7; 7815 Value |= (op & UINT64_C(255)); 7816 break; 7817 } 7818 case ARM::t2STRB_PRE: 7819 case ARM::t2STRH_PRE: 7820 case ARM::t2STR_PRE: { 7821 // op: Rt 7822 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7823 op &= UINT64_C(15); 7824 op <<= 12; 7825 Value |= op; 7826 // op: addr 7827 op = getT2AddrModeImmOpValue<8,0>(MI, 2, Fixups, STI); 7828 Value |= (op & UINT64_C(7680)) << 7; 7829 Value |= (op & UINT64_C(256)) << 1; 7830 Value |= (op & UINT64_C(255)); 7831 break; 7832 } 7833 case ARM::MVE_VMOV_q_rr: { 7834 // op: Rt 7835 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7836 op &= UINT64_C(15); 7837 Value |= op; 7838 // op: Rt2 7839 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7840 op &= UINT64_C(15); 7841 op <<= 16; 7842 Value |= op; 7843 // op: Qd 7844 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7845 Value |= (op & UINT64_C(8)) << 19; 7846 Value |= (op & UINT64_C(7)) << 13; 7847 // op: idx2 7848 op = getMVEPairVectorIndexOpValue<0>(MI, 5, Fixups, STI); 7849 op &= UINT64_C(1); 7850 op <<= 4; 7851 Value |= op; 7852 break; 7853 } 7854 case ARM::MCRR2: 7855 case ARM::t2MCRR: 7856 case ARM::t2MCRR2: { 7857 // op: Rt 7858 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7859 op &= UINT64_C(15); 7860 op <<= 12; 7861 Value |= op; 7862 // op: Rt2 7863 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7864 op &= UINT64_C(15); 7865 op <<= 16; 7866 Value |= op; 7867 // op: cop 7868 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7869 op &= UINT64_C(15); 7870 op <<= 8; 7871 Value |= op; 7872 // op: opc1 7873 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7874 op &= UINT64_C(15); 7875 op <<= 4; 7876 Value |= op; 7877 // op: CRm 7878 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7879 op &= UINT64_C(15); 7880 Value |= op; 7881 break; 7882 } 7883 case ARM::MCR2: 7884 case ARM::t2MCR: 7885 case ARM::t2MCR2: { 7886 // op: Rt 7887 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7888 op &= UINT64_C(15); 7889 op <<= 12; 7890 Value |= op; 7891 // op: cop 7892 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7893 op &= UINT64_C(15); 7894 op <<= 8; 7895 Value |= op; 7896 // op: opc1 7897 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7898 op &= UINT64_C(7); 7899 op <<= 21; 7900 Value |= op; 7901 // op: opc2 7902 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7903 op &= UINT64_C(7); 7904 op <<= 5; 7905 Value |= op; 7906 // op: CRm 7907 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7908 op &= UINT64_C(15); 7909 Value |= op; 7910 // op: CRn 7911 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7912 op &= UINT64_C(15); 7913 op <<= 16; 7914 Value |= op; 7915 break; 7916 } 7917 case ARM::t2MSR_M: { 7918 // op: SYSm 7919 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7920 Value |= (op & UINT64_C(3072)); 7921 Value |= (op & UINT64_C(255)); 7922 // op: Rn 7923 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7924 op &= UINT64_C(15); 7925 op <<= 16; 7926 Value |= op; 7927 break; 7928 } 7929 case ARM::VCVTASD: 7930 case ARM::VCVTAUD: 7931 case ARM::VCVTMSD: 7932 case ARM::VCVTMUD: 7933 case ARM::VCVTNSD: 7934 case ARM::VCVTNUD: 7935 case ARM::VCVTPSD: 7936 case ARM::VCVTPUD: { 7937 // op: Sd 7938 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7939 Value |= (op & UINT64_C(1)) << 22; 7940 Value |= (op & UINT64_C(30)) << 11; 7941 // op: Dm 7942 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7943 Value |= (op & UINT64_C(16)) << 1; 7944 Value |= (op & UINT64_C(15)); 7945 break; 7946 } 7947 case ARM::VCVTASH: 7948 case ARM::VCVTASS: 7949 case ARM::VCVTAUH: 7950 case ARM::VCVTAUS: 7951 case ARM::VCVTMSH: 7952 case ARM::VCVTMSS: 7953 case ARM::VCVTMUH: 7954 case ARM::VCVTMUS: 7955 case ARM::VCVTNSH: 7956 case ARM::VCVTNSS: 7957 case ARM::VCVTNUH: 7958 case ARM::VCVTNUS: 7959 case ARM::VCVTPSH: 7960 case ARM::VCVTPSS: 7961 case ARM::VCVTPUH: 7962 case ARM::VCVTPUS: 7963 case ARM::VINSH: 7964 case ARM::VMOVH: 7965 case ARM::VRINTAH: 7966 case ARM::VRINTAS: 7967 case ARM::VRINTMH: 7968 case ARM::VRINTMS: 7969 case ARM::VRINTNH: 7970 case ARM::VRINTNS: 7971 case ARM::VRINTPH: 7972 case ARM::VRINTPS: { 7973 // op: Sd 7974 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7975 Value |= (op & UINT64_C(1)) << 22; 7976 Value |= (op & UINT64_C(30)) << 11; 7977 // op: Sm 7978 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7979 Value |= (op & UINT64_C(1)) << 5; 7980 Value |= (op & UINT64_C(30)) >> 1; 7981 break; 7982 } 7983 case ARM::VFP_VMAXNMH: 7984 case ARM::VFP_VMAXNMS: 7985 case ARM::VFP_VMINNMH: 7986 case ARM::VFP_VMINNMS: 7987 case ARM::VSELEQH: 7988 case ARM::VSELEQS: 7989 case ARM::VSELGEH: 7990 case ARM::VSELGES: 7991 case ARM::VSELGTH: 7992 case ARM::VSELGTS: 7993 case ARM::VSELVSH: 7994 case ARM::VSELVSS: { 7995 // op: Sd 7996 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7997 Value |= (op & UINT64_C(1)) << 22; 7998 Value |= (op & UINT64_C(30)) << 11; 7999 // op: Sn 8000 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8001 Value |= (op & UINT64_C(30)) << 15; 8002 Value |= (op & UINT64_C(1)) << 7; 8003 // op: Sm 8004 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8005 Value |= (op & UINT64_C(1)) << 5; 8006 Value |= (op & UINT64_C(30)) >> 1; 8007 break; 8008 } 8009 case ARM::VDUP16d: 8010 case ARM::VDUP16q: 8011 case ARM::VDUP32d: 8012 case ARM::VDUP32q: 8013 case ARM::VDUP8d: 8014 case ARM::VDUP8q: { 8015 // op: V 8016 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8017 Value |= (op & UINT64_C(15)) << 16; 8018 Value |= (op & UINT64_C(16)) << 3; 8019 // op: R 8020 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8021 op &= UINT64_C(15); 8022 op <<= 12; 8023 Value |= op; 8024 // op: p 8025 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8026 op &= UINT64_C(15); 8027 op <<= 28; 8028 Value |= op; 8029 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8030 break; 8031 } 8032 case ARM::VSETLNi16: { 8033 // op: V 8034 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8035 Value |= (op & UINT64_C(15)) << 16; 8036 Value |= (op & UINT64_C(16)) << 3; 8037 // op: R 8038 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8039 op &= UINT64_C(15); 8040 op <<= 12; 8041 Value |= op; 8042 // op: p 8043 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8044 op &= UINT64_C(15); 8045 op <<= 28; 8046 Value |= op; 8047 // op: lane 8048 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8049 Value |= (op & UINT64_C(2)) << 20; 8050 Value |= (op & UINT64_C(1)) << 6; 8051 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8052 break; 8053 } 8054 case ARM::VSETLNi8: { 8055 // op: V 8056 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8057 Value |= (op & UINT64_C(15)) << 16; 8058 Value |= (op & UINT64_C(16)) << 3; 8059 // op: R 8060 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8061 op &= UINT64_C(15); 8062 op <<= 12; 8063 Value |= op; 8064 // op: p 8065 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8066 op &= UINT64_C(15); 8067 op <<= 28; 8068 Value |= op; 8069 // op: lane 8070 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8071 Value |= (op & UINT64_C(4)) << 19; 8072 Value |= (op & UINT64_C(3)) << 5; 8073 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8074 break; 8075 } 8076 case ARM::VSETLNi32: { 8077 // op: V 8078 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8079 Value |= (op & UINT64_C(15)) << 16; 8080 Value |= (op & UINT64_C(16)) << 3; 8081 // op: R 8082 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8083 op &= UINT64_C(15); 8084 op <<= 12; 8085 Value |= op; 8086 // op: p 8087 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8088 op &= UINT64_C(15); 8089 op <<= 28; 8090 Value |= op; 8091 // op: lane 8092 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8093 op &= UINT64_C(1); 8094 op <<= 21; 8095 Value |= op; 8096 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8097 break; 8098 } 8099 case ARM::VGETLNs16: 8100 case ARM::VGETLNu16: { 8101 // op: V 8102 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8103 Value |= (op & UINT64_C(15)) << 16; 8104 Value |= (op & UINT64_C(16)) << 3; 8105 // op: R 8106 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8107 op &= UINT64_C(15); 8108 op <<= 12; 8109 Value |= op; 8110 // op: p 8111 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8112 op &= UINT64_C(15); 8113 op <<= 28; 8114 Value |= op; 8115 // op: lane 8116 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8117 Value |= (op & UINT64_C(2)) << 20; 8118 Value |= (op & UINT64_C(1)) << 6; 8119 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8120 break; 8121 } 8122 case ARM::VGETLNs8: 8123 case ARM::VGETLNu8: { 8124 // op: V 8125 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8126 Value |= (op & UINT64_C(15)) << 16; 8127 Value |= (op & UINT64_C(16)) << 3; 8128 // op: R 8129 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8130 op &= UINT64_C(15); 8131 op <<= 12; 8132 Value |= op; 8133 // op: p 8134 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8135 op &= UINT64_C(15); 8136 op <<= 28; 8137 Value |= op; 8138 // op: lane 8139 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8140 Value |= (op & UINT64_C(4)) << 19; 8141 Value |= (op & UINT64_C(3)) << 5; 8142 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8143 break; 8144 } 8145 case ARM::VGETLNi32: { 8146 // op: V 8147 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8148 Value |= (op & UINT64_C(15)) << 16; 8149 Value |= (op & UINT64_C(16)) << 3; 8150 // op: R 8151 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8152 op &= UINT64_C(15); 8153 op <<= 12; 8154 Value |= op; 8155 // op: p 8156 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8157 op &= UINT64_C(15); 8158 op <<= 28; 8159 Value |= op; 8160 // op: lane 8161 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8162 op &= UINT64_C(1); 8163 op <<= 21; 8164 Value |= op; 8165 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 8166 break; 8167 } 8168 case ARM::MVE_VST20_16: 8169 case ARM::MVE_VST20_32: 8170 case ARM::MVE_VST20_8: 8171 case ARM::MVE_VST21_16: 8172 case ARM::MVE_VST21_32: 8173 case ARM::MVE_VST21_8: 8174 case ARM::MVE_VST40_16: 8175 case ARM::MVE_VST40_32: 8176 case ARM::MVE_VST40_8: 8177 case ARM::MVE_VST41_16: 8178 case ARM::MVE_VST41_32: 8179 case ARM::MVE_VST41_8: 8180 case ARM::MVE_VST42_16: 8181 case ARM::MVE_VST42_32: 8182 case ARM::MVE_VST42_8: 8183 case ARM::MVE_VST43_16: 8184 case ARM::MVE_VST43_32: 8185 case ARM::MVE_VST43_8: { 8186 // op: VQd 8187 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8188 op &= UINT64_C(7); 8189 op <<= 13; 8190 Value |= op; 8191 // op: Rn 8192 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8193 op &= UINT64_C(15); 8194 op <<= 16; 8195 Value |= op; 8196 break; 8197 } 8198 case ARM::MVE_VLD20_16: 8199 case ARM::MVE_VLD20_32: 8200 case ARM::MVE_VLD20_8: 8201 case ARM::MVE_VLD21_16: 8202 case ARM::MVE_VLD21_32: 8203 case ARM::MVE_VLD21_8: 8204 case ARM::MVE_VLD40_16: 8205 case ARM::MVE_VLD40_32: 8206 case ARM::MVE_VLD40_8: 8207 case ARM::MVE_VLD41_16: 8208 case ARM::MVE_VLD41_32: 8209 case ARM::MVE_VLD41_8: 8210 case ARM::MVE_VLD42_16: 8211 case ARM::MVE_VLD42_32: 8212 case ARM::MVE_VLD42_8: 8213 case ARM::MVE_VLD43_16: 8214 case ARM::MVE_VLD43_32: 8215 case ARM::MVE_VLD43_8: { 8216 // op: VQd 8217 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8218 op &= UINT64_C(7); 8219 op <<= 13; 8220 Value |= op; 8221 // op: Rn 8222 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8223 op &= UINT64_C(15); 8224 op <<= 16; 8225 Value |= op; 8226 break; 8227 } 8228 case ARM::MVE_VLD20_16_wb: 8229 case ARM::MVE_VLD20_32_wb: 8230 case ARM::MVE_VLD20_8_wb: 8231 case ARM::MVE_VLD21_16_wb: 8232 case ARM::MVE_VLD21_32_wb: 8233 case ARM::MVE_VLD21_8_wb: 8234 case ARM::MVE_VLD40_16_wb: 8235 case ARM::MVE_VLD40_32_wb: 8236 case ARM::MVE_VLD40_8_wb: 8237 case ARM::MVE_VLD41_16_wb: 8238 case ARM::MVE_VLD41_32_wb: 8239 case ARM::MVE_VLD41_8_wb: 8240 case ARM::MVE_VLD42_16_wb: 8241 case ARM::MVE_VLD42_32_wb: 8242 case ARM::MVE_VLD42_8_wb: 8243 case ARM::MVE_VLD43_16_wb: 8244 case ARM::MVE_VLD43_32_wb: 8245 case ARM::MVE_VLD43_8_wb: { 8246 // op: VQd 8247 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8248 op &= UINT64_C(7); 8249 op <<= 13; 8250 Value |= op; 8251 // op: Rn 8252 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8253 op &= UINT64_C(15); 8254 op <<= 16; 8255 Value |= op; 8256 break; 8257 } 8258 case ARM::MVE_VST20_16_wb: 8259 case ARM::MVE_VST20_32_wb: 8260 case ARM::MVE_VST20_8_wb: 8261 case ARM::MVE_VST21_16_wb: 8262 case ARM::MVE_VST21_32_wb: 8263 case ARM::MVE_VST21_8_wb: 8264 case ARM::MVE_VST40_16_wb: 8265 case ARM::MVE_VST40_32_wb: 8266 case ARM::MVE_VST40_8_wb: 8267 case ARM::MVE_VST41_16_wb: 8268 case ARM::MVE_VST41_32_wb: 8269 case ARM::MVE_VST41_8_wb: 8270 case ARM::MVE_VST42_16_wb: 8271 case ARM::MVE_VST42_32_wb: 8272 case ARM::MVE_VST42_8_wb: 8273 case ARM::MVE_VST43_16_wb: 8274 case ARM::MVE_VST43_32_wb: 8275 case ARM::MVE_VST43_8_wb: { 8276 // op: VQd 8277 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8278 op &= UINT64_C(7); 8279 op <<= 13; 8280 Value |= op; 8281 // op: Rn 8282 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8283 op &= UINT64_C(15); 8284 op <<= 16; 8285 Value |= op; 8286 break; 8287 } 8288 case ARM::VLD1d16: 8289 case ARM::VLD1d16T: 8290 case ARM::VLD1d32: 8291 case ARM::VLD1d32T: 8292 case ARM::VLD1d64: 8293 case ARM::VLD1d64T: 8294 case ARM::VLD1d8: 8295 case ARM::VLD1d8T: { 8296 // op: Vd 8297 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8298 Value |= (op & UINT64_C(16)) << 18; 8299 Value |= (op & UINT64_C(15)) << 12; 8300 // op: Rn 8301 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8302 Value |= (op & UINT64_C(15)) << 16; 8303 Value |= (op & UINT64_C(16)); 8304 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8305 break; 8306 } 8307 case ARM::VLD1LNd16: { 8308 // op: Vd 8309 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8310 Value |= (op & UINT64_C(16)) << 18; 8311 Value |= (op & UINT64_C(15)) << 12; 8312 // op: Rn 8313 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8314 Value |= (op & UINT64_C(15)) << 16; 8315 Value |= (op & UINT64_C(48)); 8316 // op: lane 8317 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8318 op &= UINT64_C(3); 8319 op <<= 6; 8320 Value |= op; 8321 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8322 break; 8323 } 8324 case ARM::VLD1d16Q: 8325 case ARM::VLD1d32Q: 8326 case ARM::VLD1d64Q: 8327 case ARM::VLD1d8Q: 8328 case ARM::VLD1q16: 8329 case ARM::VLD1q32: 8330 case ARM::VLD1q64: 8331 case ARM::VLD1q8: 8332 case ARM::VLD2b16: 8333 case ARM::VLD2b32: 8334 case ARM::VLD2b8: 8335 case ARM::VLD2d16: 8336 case ARM::VLD2d32: 8337 case ARM::VLD2d8: 8338 case ARM::VLD2q16: 8339 case ARM::VLD2q32: 8340 case ARM::VLD2q8: { 8341 // op: Vd 8342 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8343 Value |= (op & UINT64_C(16)) << 18; 8344 Value |= (op & UINT64_C(15)) << 12; 8345 // op: Rn 8346 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8347 Value |= (op & UINT64_C(15)) << 16; 8348 Value |= (op & UINT64_C(48)); 8349 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8350 break; 8351 } 8352 case ARM::VLD1LNd8: { 8353 // op: Vd 8354 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8355 Value |= (op & UINT64_C(16)) << 18; 8356 Value |= (op & UINT64_C(15)) << 12; 8357 // op: Rn 8358 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 8359 op &= UINT64_C(15); 8360 op <<= 16; 8361 Value |= op; 8362 // op: lane 8363 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8364 op &= UINT64_C(7); 8365 op <<= 5; 8366 Value |= op; 8367 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8368 break; 8369 } 8370 case ARM::VLD1LNd32_UPD: { 8371 // op: Vd 8372 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8373 Value |= (op & UINT64_C(16)) << 18; 8374 Value |= (op & UINT64_C(15)) << 12; 8375 // op: Rn 8376 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8377 Value |= (op & UINT64_C(15)) << 16; 8378 Value |= (op & UINT64_C(16)) << 1; 8379 Value |= (op & UINT64_C(16)); 8380 // op: Rm 8381 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8382 op &= UINT64_C(15); 8383 Value |= op; 8384 // op: lane 8385 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8386 op &= UINT64_C(1); 8387 op <<= 7; 8388 Value |= op; 8389 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8390 break; 8391 } 8392 case ARM::VLD1LNd16_UPD: { 8393 // op: Vd 8394 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8395 Value |= (op & UINT64_C(16)) << 18; 8396 Value |= (op & UINT64_C(15)) << 12; 8397 // op: Rn 8398 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8399 Value |= (op & UINT64_C(15)) << 16; 8400 Value |= (op & UINT64_C(16)); 8401 // op: Rm 8402 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8403 op &= UINT64_C(15); 8404 Value |= op; 8405 // op: lane 8406 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8407 op &= UINT64_C(3); 8408 op <<= 6; 8409 Value |= op; 8410 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8411 break; 8412 } 8413 case ARM::VLD1d16Twb_register: 8414 case ARM::VLD1d16wb_register: 8415 case ARM::VLD1d32Twb_register: 8416 case ARM::VLD1d32wb_register: 8417 case ARM::VLD1d64Twb_register: 8418 case ARM::VLD1d64wb_register: 8419 case ARM::VLD1d8Twb_register: 8420 case ARM::VLD1d8wb_register: { 8421 // op: Vd 8422 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8423 Value |= (op & UINT64_C(16)) << 18; 8424 Value |= (op & UINT64_C(15)) << 12; 8425 // op: Rn 8426 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8427 Value |= (op & UINT64_C(15)) << 16; 8428 Value |= (op & UINT64_C(16)); 8429 // op: Rm 8430 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8431 op &= UINT64_C(15); 8432 Value |= op; 8433 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8434 break; 8435 } 8436 case ARM::VLD2LNd32: 8437 case ARM::VLD2LNq32: { 8438 // op: Vd 8439 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8440 Value |= (op & UINT64_C(16)) << 18; 8441 Value |= (op & UINT64_C(15)) << 12; 8442 // op: Rn 8443 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8444 Value |= (op & UINT64_C(15)) << 16; 8445 Value |= (op & UINT64_C(16)); 8446 // op: lane 8447 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8448 op &= UINT64_C(1); 8449 op <<= 7; 8450 Value |= op; 8451 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8452 break; 8453 } 8454 case ARM::VLD2LNd16: 8455 case ARM::VLD2LNq16: { 8456 // op: Vd 8457 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8458 Value |= (op & UINT64_C(16)) << 18; 8459 Value |= (op & UINT64_C(15)) << 12; 8460 // op: Rn 8461 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8462 Value |= (op & UINT64_C(15)) << 16; 8463 Value |= (op & UINT64_C(16)); 8464 // op: lane 8465 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8466 op &= UINT64_C(3); 8467 op <<= 6; 8468 Value |= op; 8469 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8470 break; 8471 } 8472 case ARM::VLD2LNd8: { 8473 // op: Vd 8474 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8475 Value |= (op & UINT64_C(16)) << 18; 8476 Value |= (op & UINT64_C(15)) << 12; 8477 // op: Rn 8478 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8479 Value |= (op & UINT64_C(15)) << 16; 8480 Value |= (op & UINT64_C(16)); 8481 // op: lane 8482 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8483 op &= UINT64_C(7); 8484 op <<= 5; 8485 Value |= op; 8486 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8487 break; 8488 } 8489 case ARM::VLD1d16Twb_fixed: 8490 case ARM::VLD1d16wb_fixed: 8491 case ARM::VLD1d32Twb_fixed: 8492 case ARM::VLD1d32wb_fixed: 8493 case ARM::VLD1d64Twb_fixed: 8494 case ARM::VLD1d64wb_fixed: 8495 case ARM::VLD1d8Twb_fixed: 8496 case ARM::VLD1d8wb_fixed: { 8497 // op: Vd 8498 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8499 Value |= (op & UINT64_C(16)) << 18; 8500 Value |= (op & UINT64_C(15)) << 12; 8501 // op: Rn 8502 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8503 Value |= (op & UINT64_C(15)) << 16; 8504 Value |= (op & UINT64_C(16)); 8505 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8506 break; 8507 } 8508 case ARM::VLD1d16Qwb_register: 8509 case ARM::VLD1d32Qwb_register: 8510 case ARM::VLD1d64Qwb_register: 8511 case ARM::VLD1d8Qwb_register: 8512 case ARM::VLD1q16wb_register: 8513 case ARM::VLD1q32wb_register: 8514 case ARM::VLD1q64wb_register: 8515 case ARM::VLD1q8wb_register: 8516 case ARM::VLD2b16wb_register: 8517 case ARM::VLD2b32wb_register: 8518 case ARM::VLD2b8wb_register: 8519 case ARM::VLD2d16wb_register: 8520 case ARM::VLD2d32wb_register: 8521 case ARM::VLD2d8wb_register: 8522 case ARM::VLD2q16wb_register: 8523 case ARM::VLD2q32wb_register: 8524 case ARM::VLD2q8wb_register: { 8525 // op: Vd 8526 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8527 Value |= (op & UINT64_C(16)) << 18; 8528 Value |= (op & UINT64_C(15)) << 12; 8529 // op: Rn 8530 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8531 Value |= (op & UINT64_C(15)) << 16; 8532 Value |= (op & UINT64_C(48)); 8533 // op: Rm 8534 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8535 op &= UINT64_C(15); 8536 Value |= op; 8537 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8538 break; 8539 } 8540 case ARM::VLD1d16Qwb_fixed: 8541 case ARM::VLD1d32Qwb_fixed: 8542 case ARM::VLD1d64Qwb_fixed: 8543 case ARM::VLD1d8Qwb_fixed: 8544 case ARM::VLD1q16wb_fixed: 8545 case ARM::VLD1q32wb_fixed: 8546 case ARM::VLD1q64wb_fixed: 8547 case ARM::VLD1q8wb_fixed: 8548 case ARM::VLD2b16wb_fixed: 8549 case ARM::VLD2b32wb_fixed: 8550 case ARM::VLD2b8wb_fixed: 8551 case ARM::VLD2d16wb_fixed: 8552 case ARM::VLD2d32wb_fixed: 8553 case ARM::VLD2d8wb_fixed: 8554 case ARM::VLD2q16wb_fixed: 8555 case ARM::VLD2q32wb_fixed: 8556 case ARM::VLD2q8wb_fixed: { 8557 // op: Vd 8558 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8559 Value |= (op & UINT64_C(16)) << 18; 8560 Value |= (op & UINT64_C(15)) << 12; 8561 // op: Rn 8562 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8563 Value |= (op & UINT64_C(15)) << 16; 8564 Value |= (op & UINT64_C(48)); 8565 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8566 break; 8567 } 8568 case ARM::VLD1LNd8_UPD: { 8569 // op: Vd 8570 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8571 Value |= (op & UINT64_C(16)) << 18; 8572 Value |= (op & UINT64_C(15)) << 12; 8573 // op: Rn 8574 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 8575 op &= UINT64_C(15); 8576 op <<= 16; 8577 Value |= op; 8578 // op: Rm 8579 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 8580 op &= UINT64_C(15); 8581 Value |= op; 8582 // op: lane 8583 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 8584 op &= UINT64_C(7); 8585 op <<= 5; 8586 Value |= op; 8587 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8588 break; 8589 } 8590 case ARM::VLD2LNd32_UPD: 8591 case ARM::VLD2LNq32_UPD: { 8592 // op: Vd 8593 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8594 Value |= (op & UINT64_C(16)) << 18; 8595 Value |= (op & UINT64_C(15)) << 12; 8596 // op: Rn 8597 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8598 Value |= (op & UINT64_C(15)) << 16; 8599 Value |= (op & UINT64_C(16)); 8600 // op: Rm 8601 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8602 op &= UINT64_C(15); 8603 Value |= op; 8604 // op: lane 8605 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8606 op &= UINT64_C(1); 8607 op <<= 7; 8608 Value |= op; 8609 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8610 break; 8611 } 8612 case ARM::VLD2LNd16_UPD: 8613 case ARM::VLD2LNq16_UPD: { 8614 // op: Vd 8615 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8616 Value |= (op & UINT64_C(16)) << 18; 8617 Value |= (op & UINT64_C(15)) << 12; 8618 // op: Rn 8619 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8620 Value |= (op & UINT64_C(15)) << 16; 8621 Value |= (op & UINT64_C(16)); 8622 // op: Rm 8623 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8624 op &= UINT64_C(15); 8625 Value |= op; 8626 // op: lane 8627 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8628 op &= UINT64_C(3); 8629 op <<= 6; 8630 Value |= op; 8631 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8632 break; 8633 } 8634 case ARM::VLD2LNd8_UPD: { 8635 // op: Vd 8636 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8637 Value |= (op & UINT64_C(16)) << 18; 8638 Value |= (op & UINT64_C(15)) << 12; 8639 // op: Rn 8640 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8641 Value |= (op & UINT64_C(15)) << 16; 8642 Value |= (op & UINT64_C(16)); 8643 // op: Rm 8644 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 8645 op &= UINT64_C(15); 8646 Value |= op; 8647 // op: lane 8648 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8649 op &= UINT64_C(7); 8650 op <<= 5; 8651 Value |= op; 8652 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8653 break; 8654 } 8655 case ARM::VLD3d16: 8656 case ARM::VLD3d32: 8657 case ARM::VLD3d8: 8658 case ARM::VLD3q16: 8659 case ARM::VLD3q32: 8660 case ARM::VLD3q8: { 8661 // op: Vd 8662 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8663 Value |= (op & UINT64_C(16)) << 18; 8664 Value |= (op & UINT64_C(15)) << 12; 8665 // op: Rn 8666 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8667 Value |= (op & UINT64_C(15)) << 16; 8668 Value |= (op & UINT64_C(16)); 8669 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8670 break; 8671 } 8672 case ARM::VLD3LNd32: 8673 case ARM::VLD3LNq32: { 8674 // op: Vd 8675 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8676 Value |= (op & UINT64_C(16)) << 18; 8677 Value |= (op & UINT64_C(15)) << 12; 8678 // op: Rn 8679 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8680 op &= UINT64_C(15); 8681 op <<= 16; 8682 Value |= op; 8683 // op: lane 8684 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8685 op &= UINT64_C(1); 8686 op <<= 7; 8687 Value |= op; 8688 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8689 break; 8690 } 8691 case ARM::VLD3LNd16: 8692 case ARM::VLD3LNq16: { 8693 // op: Vd 8694 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8695 Value |= (op & UINT64_C(16)) << 18; 8696 Value |= (op & UINT64_C(15)) << 12; 8697 // op: Rn 8698 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8699 op &= UINT64_C(15); 8700 op <<= 16; 8701 Value |= op; 8702 // op: lane 8703 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8704 op &= UINT64_C(3); 8705 op <<= 6; 8706 Value |= op; 8707 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8708 break; 8709 } 8710 case ARM::VLD3LNd8: { 8711 // op: Vd 8712 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8713 Value |= (op & UINT64_C(16)) << 18; 8714 Value |= (op & UINT64_C(15)) << 12; 8715 // op: Rn 8716 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 8717 op &= UINT64_C(15); 8718 op <<= 16; 8719 Value |= op; 8720 // op: lane 8721 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 8722 op &= UINT64_C(7); 8723 op <<= 5; 8724 Value |= op; 8725 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8726 break; 8727 } 8728 case ARM::VLD3d16_UPD: 8729 case ARM::VLD3d32_UPD: 8730 case ARM::VLD3d8_UPD: 8731 case ARM::VLD3q16_UPD: 8732 case ARM::VLD3q32_UPD: 8733 case ARM::VLD3q8_UPD: { 8734 // op: Vd 8735 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8736 Value |= (op & UINT64_C(16)) << 18; 8737 Value |= (op & UINT64_C(15)) << 12; 8738 // op: Rn 8739 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8740 Value |= (op & UINT64_C(15)) << 16; 8741 Value |= (op & UINT64_C(16)); 8742 // op: Rm 8743 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 8744 op &= UINT64_C(15); 8745 Value |= op; 8746 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8747 break; 8748 } 8749 case ARM::VLD4LNd16: 8750 case ARM::VLD4LNq16: { 8751 // op: Vd 8752 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8753 Value |= (op & UINT64_C(16)) << 18; 8754 Value |= (op & UINT64_C(15)) << 12; 8755 // op: Rn 8756 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8757 Value |= (op & UINT64_C(15)) << 16; 8758 Value |= (op & UINT64_C(16)); 8759 // op: lane 8760 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8761 op &= UINT64_C(3); 8762 op <<= 6; 8763 Value |= op; 8764 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8765 break; 8766 } 8767 case ARM::VLD4LNd8: { 8768 // op: Vd 8769 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8770 Value |= (op & UINT64_C(16)) << 18; 8771 Value |= (op & UINT64_C(15)) << 12; 8772 // op: Rn 8773 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8774 Value |= (op & UINT64_C(15)) << 16; 8775 Value |= (op & UINT64_C(16)); 8776 // op: lane 8777 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8778 op &= UINT64_C(7); 8779 op <<= 5; 8780 Value |= op; 8781 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8782 break; 8783 } 8784 case ARM::VLD4LNd32: 8785 case ARM::VLD4LNq32: { 8786 // op: Vd 8787 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8788 Value |= (op & UINT64_C(16)) << 18; 8789 Value |= (op & UINT64_C(15)) << 12; 8790 // op: Rn 8791 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8792 Value |= (op & UINT64_C(15)) << 16; 8793 Value |= (op & UINT64_C(48)); 8794 // op: lane 8795 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8796 op &= UINT64_C(1); 8797 op <<= 7; 8798 Value |= op; 8799 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8800 break; 8801 } 8802 case ARM::VLD4d16: 8803 case ARM::VLD4d32: 8804 case ARM::VLD4d8: 8805 case ARM::VLD4q16: 8806 case ARM::VLD4q32: 8807 case ARM::VLD4q8: { 8808 // op: Vd 8809 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8810 Value |= (op & UINT64_C(16)) << 18; 8811 Value |= (op & UINT64_C(15)) << 12; 8812 // op: Rn 8813 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8814 Value |= (op & UINT64_C(15)) << 16; 8815 Value |= (op & UINT64_C(48)); 8816 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8817 break; 8818 } 8819 case ARM::VLD3LNd32_UPD: 8820 case ARM::VLD3LNq32_UPD: { 8821 // op: Vd 8822 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8823 Value |= (op & UINT64_C(16)) << 18; 8824 Value |= (op & UINT64_C(15)) << 12; 8825 // op: Rn 8826 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8827 op &= UINT64_C(15); 8828 op <<= 16; 8829 Value |= op; 8830 // op: Rm 8831 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 8832 op &= UINT64_C(15); 8833 Value |= op; 8834 // op: lane 8835 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8836 op &= UINT64_C(1); 8837 op <<= 7; 8838 Value |= op; 8839 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8840 break; 8841 } 8842 case ARM::VLD3LNd16_UPD: 8843 case ARM::VLD3LNq16_UPD: { 8844 // op: Vd 8845 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8846 Value |= (op & UINT64_C(16)) << 18; 8847 Value |= (op & UINT64_C(15)) << 12; 8848 // op: Rn 8849 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8850 op &= UINT64_C(15); 8851 op <<= 16; 8852 Value |= op; 8853 // op: Rm 8854 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 8855 op &= UINT64_C(15); 8856 Value |= op; 8857 // op: lane 8858 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8859 op &= UINT64_C(3); 8860 op <<= 6; 8861 Value |= op; 8862 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8863 break; 8864 } 8865 case ARM::VLD3LNd8_UPD: { 8866 // op: Vd 8867 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8868 Value |= (op & UINT64_C(16)) << 18; 8869 Value |= (op & UINT64_C(15)) << 12; 8870 // op: Rn 8871 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 8872 op &= UINT64_C(15); 8873 op <<= 16; 8874 Value |= op; 8875 // op: Rm 8876 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 8877 op &= UINT64_C(15); 8878 Value |= op; 8879 // op: lane 8880 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 8881 op &= UINT64_C(7); 8882 op <<= 5; 8883 Value |= op; 8884 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8885 break; 8886 } 8887 case ARM::VLD4LNd16_UPD: 8888 case ARM::VLD4LNq16_UPD: { 8889 // op: Vd 8890 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8891 Value |= (op & UINT64_C(16)) << 18; 8892 Value |= (op & UINT64_C(15)) << 12; 8893 // op: Rn 8894 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 8895 Value |= (op & UINT64_C(15)) << 16; 8896 Value |= (op & UINT64_C(16)); 8897 // op: Rm 8898 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 8899 op &= UINT64_C(15); 8900 Value |= op; 8901 // op: lane 8902 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 8903 op &= UINT64_C(3); 8904 op <<= 6; 8905 Value |= op; 8906 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8907 break; 8908 } 8909 case ARM::VLD4LNd8_UPD: { 8910 // op: Vd 8911 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8912 Value |= (op & UINT64_C(16)) << 18; 8913 Value |= (op & UINT64_C(15)) << 12; 8914 // op: Rn 8915 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 8916 Value |= (op & UINT64_C(15)) << 16; 8917 Value |= (op & UINT64_C(16)); 8918 // op: Rm 8919 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 8920 op &= UINT64_C(15); 8921 Value |= op; 8922 // op: lane 8923 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 8924 op &= UINT64_C(7); 8925 op <<= 5; 8926 Value |= op; 8927 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8928 break; 8929 } 8930 case ARM::VLD4LNd32_UPD: 8931 case ARM::VLD4LNq32_UPD: { 8932 // op: Vd 8933 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8934 Value |= (op & UINT64_C(16)) << 18; 8935 Value |= (op & UINT64_C(15)) << 12; 8936 // op: Rn 8937 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 8938 Value |= (op & UINT64_C(15)) << 16; 8939 Value |= (op & UINT64_C(48)); 8940 // op: Rm 8941 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 8942 op &= UINT64_C(15); 8943 Value |= op; 8944 // op: lane 8945 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 8946 op &= UINT64_C(1); 8947 op <<= 7; 8948 Value |= op; 8949 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8950 break; 8951 } 8952 case ARM::VLD4d16_UPD: 8953 case ARM::VLD4d32_UPD: 8954 case ARM::VLD4d8_UPD: 8955 case ARM::VLD4q16_UPD: 8956 case ARM::VLD4q32_UPD: 8957 case ARM::VLD4q8_UPD: { 8958 // op: Vd 8959 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8960 Value |= (op & UINT64_C(16)) << 18; 8961 Value |= (op & UINT64_C(15)) << 12; 8962 // op: Rn 8963 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 8964 Value |= (op & UINT64_C(15)) << 16; 8965 Value |= (op & UINT64_C(48)); 8966 // op: Rm 8967 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 8968 op &= UINT64_C(15); 8969 Value |= op; 8970 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8971 break; 8972 } 8973 case ARM::VLD1DUPd16: 8974 case ARM::VLD1DUPd32: 8975 case ARM::VLD1DUPd8: 8976 case ARM::VLD1DUPq16: 8977 case ARM::VLD1DUPq32: 8978 case ARM::VLD1DUPq8: 8979 case ARM::VLD2DUPd16: 8980 case ARM::VLD2DUPd16x2: 8981 case ARM::VLD2DUPd32: 8982 case ARM::VLD2DUPd32x2: 8983 case ARM::VLD2DUPd8: 8984 case ARM::VLD2DUPd8x2: { 8985 // op: Vd 8986 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8987 Value |= (op & UINT64_C(16)) << 18; 8988 Value |= (op & UINT64_C(15)) << 12; 8989 // op: Rn 8990 op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI); 8991 Value |= (op & UINT64_C(15)) << 16; 8992 Value |= (op & UINT64_C(16)); 8993 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8994 break; 8995 } 8996 case ARM::VLD1DUPd16wb_register: 8997 case ARM::VLD1DUPd32wb_register: 8998 case ARM::VLD1DUPd8wb_register: 8999 case ARM::VLD1DUPq16wb_register: 9000 case ARM::VLD1DUPq32wb_register: 9001 case ARM::VLD1DUPq8wb_register: 9002 case ARM::VLD2DUPd16wb_register: 9003 case ARM::VLD2DUPd16x2wb_register: 9004 case ARM::VLD2DUPd32wb_register: 9005 case ARM::VLD2DUPd32x2wb_register: 9006 case ARM::VLD2DUPd8wb_register: 9007 case ARM::VLD2DUPd8x2wb_register: { 9008 // op: Vd 9009 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9010 Value |= (op & UINT64_C(16)) << 18; 9011 Value |= (op & UINT64_C(15)) << 12; 9012 // op: Rn 9013 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 9014 Value |= (op & UINT64_C(15)) << 16; 9015 Value |= (op & UINT64_C(16)); 9016 // op: Rm 9017 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9018 op &= UINT64_C(15); 9019 Value |= op; 9020 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9021 break; 9022 } 9023 case ARM::VLD1DUPd16wb_fixed: 9024 case ARM::VLD1DUPd32wb_fixed: 9025 case ARM::VLD1DUPd8wb_fixed: 9026 case ARM::VLD1DUPq16wb_fixed: 9027 case ARM::VLD1DUPq32wb_fixed: 9028 case ARM::VLD1DUPq8wb_fixed: 9029 case ARM::VLD2DUPd16wb_fixed: 9030 case ARM::VLD2DUPd16x2wb_fixed: 9031 case ARM::VLD2DUPd32wb_fixed: 9032 case ARM::VLD2DUPd32x2wb_fixed: 9033 case ARM::VLD2DUPd8wb_fixed: 9034 case ARM::VLD2DUPd8x2wb_fixed: { 9035 // op: Vd 9036 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9037 Value |= (op & UINT64_C(16)) << 18; 9038 Value |= (op & UINT64_C(15)) << 12; 9039 // op: Rn 9040 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 9041 Value |= (op & UINT64_C(15)) << 16; 9042 Value |= (op & UINT64_C(16)); 9043 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9044 break; 9045 } 9046 case ARM::VLD3DUPd16: 9047 case ARM::VLD3DUPd32: 9048 case ARM::VLD3DUPd8: 9049 case ARM::VLD3DUPq16: 9050 case ARM::VLD3DUPq32: 9051 case ARM::VLD3DUPq8: { 9052 // op: Vd 9053 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9054 Value |= (op & UINT64_C(16)) << 18; 9055 Value |= (op & UINT64_C(15)) << 12; 9056 // op: Rn 9057 op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI); 9058 op &= UINT64_C(15); 9059 op <<= 16; 9060 Value |= op; 9061 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9062 break; 9063 } 9064 case ARM::VLD4DUPd16: 9065 case ARM::VLD4DUPd8: 9066 case ARM::VLD4DUPq16: 9067 case ARM::VLD4DUPq8: { 9068 // op: Vd 9069 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9070 Value |= (op & UINT64_C(16)) << 18; 9071 Value |= (op & UINT64_C(15)) << 12; 9072 // op: Rn 9073 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9074 Value |= (op & UINT64_C(15)) << 16; 9075 Value |= (op & UINT64_C(16)); 9076 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9077 break; 9078 } 9079 case ARM::VLD4DUPd32: 9080 case ARM::VLD4DUPq32: { 9081 // op: Vd 9082 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9083 Value |= (op & UINT64_C(16)) << 18; 9084 Value |= (op & UINT64_C(15)) << 12; 9085 // op: Rn 9086 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9087 Value |= (op & UINT64_C(15)) << 16; 9088 Value |= (op & UINT64_C(32)) << 1; 9089 Value |= (op & UINT64_C(16)); 9090 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9091 break; 9092 } 9093 case ARM::VLD3DUPd16_UPD: 9094 case ARM::VLD3DUPd32_UPD: 9095 case ARM::VLD3DUPd8_UPD: 9096 case ARM::VLD3DUPq16_UPD: 9097 case ARM::VLD3DUPq32_UPD: 9098 case ARM::VLD3DUPq8_UPD: { 9099 // op: Vd 9100 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9101 Value |= (op & UINT64_C(16)) << 18; 9102 Value |= (op & UINT64_C(15)) << 12; 9103 // op: Rn 9104 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 9105 op &= UINT64_C(15); 9106 op <<= 16; 9107 Value |= op; 9108 // op: Rm 9109 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 9110 op &= UINT64_C(15); 9111 Value |= op; 9112 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9113 break; 9114 } 9115 case ARM::VLD4DUPd16_UPD: 9116 case ARM::VLD4DUPd8_UPD: 9117 case ARM::VLD4DUPq16_UPD: 9118 case ARM::VLD4DUPq8_UPD: { 9119 // op: Vd 9120 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9121 Value |= (op & UINT64_C(16)) << 18; 9122 Value |= (op & UINT64_C(15)) << 12; 9123 // op: Rn 9124 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 9125 Value |= (op & UINT64_C(15)) << 16; 9126 Value |= (op & UINT64_C(16)); 9127 // op: Rm 9128 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9129 op &= UINT64_C(15); 9130 Value |= op; 9131 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9132 break; 9133 } 9134 case ARM::VLD4DUPd32_UPD: 9135 case ARM::VLD4DUPq32_UPD: { 9136 // op: Vd 9137 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9138 Value |= (op & UINT64_C(16)) << 18; 9139 Value |= (op & UINT64_C(15)) << 12; 9140 // op: Rn 9141 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 9142 Value |= (op & UINT64_C(15)) << 16; 9143 Value |= (op & UINT64_C(32)) << 1; 9144 Value |= (op & UINT64_C(16)); 9145 // op: Rm 9146 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 9147 op &= UINT64_C(15); 9148 Value |= op; 9149 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9150 break; 9151 } 9152 case ARM::VLD1LNd32: { 9153 // op: Vd 9154 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9155 Value |= (op & UINT64_C(16)) << 18; 9156 Value |= (op & UINT64_C(15)) << 12; 9157 // op: Rn 9158 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 9159 Value |= (op & UINT64_C(15)) << 16; 9160 Value |= (op & UINT64_C(48)); 9161 // op: lane 9162 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9163 op &= UINT64_C(1); 9164 op <<= 7; 9165 Value |= op; 9166 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 9167 break; 9168 } 9169 case ARM::VMOVv16i8: 9170 case ARM::VMOVv1i64: 9171 case ARM::VMOVv2f32: 9172 case ARM::VMOVv2i64: 9173 case ARM::VMOVv4f32: 9174 case ARM::VMOVv8i8: { 9175 // op: Vd 9176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9177 Value |= (op & UINT64_C(16)) << 18; 9178 Value |= (op & UINT64_C(15)) << 12; 9179 // op: SIMM 9180 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9181 Value |= (op & UINT64_C(128)) << 17; 9182 Value |= (op & UINT64_C(112)) << 12; 9183 Value |= (op & UINT64_C(15)); 9184 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9185 break; 9186 } 9187 case ARM::VBICiv2i32: 9188 case ARM::VBICiv4i32: 9189 case ARM::VORRiv2i32: 9190 case ARM::VORRiv4i32: { 9191 // op: Vd 9192 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9193 Value |= (op & UINT64_C(16)) << 18; 9194 Value |= (op & UINT64_C(15)) << 12; 9195 // op: SIMM 9196 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9197 Value |= (op & UINT64_C(128)) << 17; 9198 Value |= (op & UINT64_C(112)) << 12; 9199 Value |= (op & UINT64_C(1536)); 9200 Value |= (op & UINT64_C(15)); 9201 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9202 break; 9203 } 9204 case ARM::VMOVv2i32: 9205 case ARM::VMOVv4i32: 9206 case ARM::VMVNv2i32: 9207 case ARM::VMVNv4i32: { 9208 // op: Vd 9209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9210 Value |= (op & UINT64_C(16)) << 18; 9211 Value |= (op & UINT64_C(15)) << 12; 9212 // op: SIMM 9213 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9214 Value |= (op & UINT64_C(128)) << 17; 9215 Value |= (op & UINT64_C(112)) << 12; 9216 Value |= (op & UINT64_C(3840)); 9217 Value |= (op & UINT64_C(15)); 9218 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9219 break; 9220 } 9221 case ARM::VBICiv4i16: 9222 case ARM::VBICiv8i16: 9223 case ARM::VMOVv4i16: 9224 case ARM::VMOVv8i16: 9225 case ARM::VMVNv4i16: 9226 case ARM::VMVNv8i16: 9227 case ARM::VORRiv4i16: 9228 case ARM::VORRiv8i16: { 9229 // op: Vd 9230 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9231 Value |= (op & UINT64_C(16)) << 18; 9232 Value |= (op & UINT64_C(15)) << 12; 9233 // op: SIMM 9234 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9235 Value |= (op & UINT64_C(128)) << 17; 9236 Value |= (op & UINT64_C(112)) << 12; 9237 Value |= (op & UINT64_C(512)); 9238 Value |= (op & UINT64_C(15)); 9239 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9240 break; 9241 } 9242 case ARM::VQSHLsiv4i16: 9243 case ARM::VQSHLsiv8i16: 9244 case ARM::VQSHLsuv4i16: 9245 case ARM::VQSHLsuv8i16: 9246 case ARM::VQSHLuiv4i16: 9247 case ARM::VQSHLuiv8i16: 9248 case ARM::VSHLLsv4i32: 9249 case ARM::VSHLLuv4i32: 9250 case ARM::VSHLiv4i16: 9251 case ARM::VSHLiv8i16: { 9252 // op: Vd 9253 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9254 Value |= (op & UINT64_C(16)) << 18; 9255 Value |= (op & UINT64_C(15)) << 12; 9256 // op: Vm 9257 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9258 Value |= (op & UINT64_C(16)) << 1; 9259 Value |= (op & UINT64_C(15)); 9260 // op: SIMM 9261 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9262 op &= UINT64_C(15); 9263 op <<= 16; 9264 Value |= op; 9265 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9266 break; 9267 } 9268 case ARM::VQSHLsiv2i32: 9269 case ARM::VQSHLsiv4i32: 9270 case ARM::VQSHLsuv2i32: 9271 case ARM::VQSHLsuv4i32: 9272 case ARM::VQSHLuiv2i32: 9273 case ARM::VQSHLuiv4i32: 9274 case ARM::VSHLLsv2i64: 9275 case ARM::VSHLLuv2i64: 9276 case ARM::VSHLiv2i32: 9277 case ARM::VSHLiv4i32: { 9278 // op: Vd 9279 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9280 Value |= (op & UINT64_C(16)) << 18; 9281 Value |= (op & UINT64_C(15)) << 12; 9282 // op: Vm 9283 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9284 Value |= (op & UINT64_C(16)) << 1; 9285 Value |= (op & UINT64_C(15)); 9286 // op: SIMM 9287 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9288 op &= UINT64_C(31); 9289 op <<= 16; 9290 Value |= op; 9291 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9292 break; 9293 } 9294 case ARM::VQSHLsiv1i64: 9295 case ARM::VQSHLsiv2i64: 9296 case ARM::VQSHLsuv1i64: 9297 case ARM::VQSHLsuv2i64: 9298 case ARM::VQSHLuiv1i64: 9299 case ARM::VQSHLuiv2i64: 9300 case ARM::VSHLiv1i64: 9301 case ARM::VSHLiv2i64: { 9302 // op: Vd 9303 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9304 Value |= (op & UINT64_C(16)) << 18; 9305 Value |= (op & UINT64_C(15)) << 12; 9306 // op: Vm 9307 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9308 Value |= (op & UINT64_C(16)) << 1; 9309 Value |= (op & UINT64_C(15)); 9310 // op: SIMM 9311 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9312 op &= UINT64_C(63); 9313 op <<= 16; 9314 Value |= op; 9315 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9316 break; 9317 } 9318 case ARM::VQSHLsiv16i8: 9319 case ARM::VQSHLsiv8i8: 9320 case ARM::VQSHLsuv16i8: 9321 case ARM::VQSHLsuv8i8: 9322 case ARM::VQSHLuiv16i8: 9323 case ARM::VQSHLuiv8i8: 9324 case ARM::VSHLLsv8i16: 9325 case ARM::VSHLLuv8i16: 9326 case ARM::VSHLiv16i8: 9327 case ARM::VSHLiv8i8: { 9328 // op: Vd 9329 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9330 Value |= (op & UINT64_C(16)) << 18; 9331 Value |= (op & UINT64_C(15)) << 12; 9332 // op: Vm 9333 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9334 Value |= (op & UINT64_C(16)) << 1; 9335 Value |= (op & UINT64_C(15)); 9336 // op: SIMM 9337 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9338 op &= UINT64_C(7); 9339 op <<= 16; 9340 Value |= op; 9341 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9342 break; 9343 } 9344 case ARM::VCVTf2xsd: 9345 case ARM::VCVTf2xsq: 9346 case ARM::VCVTf2xud: 9347 case ARM::VCVTf2xuq: 9348 case ARM::VCVTh2xsd: 9349 case ARM::VCVTh2xsq: 9350 case ARM::VCVTh2xud: 9351 case ARM::VCVTh2xuq: 9352 case ARM::VCVTxs2fd: 9353 case ARM::VCVTxs2fq: 9354 case ARM::VCVTxs2hd: 9355 case ARM::VCVTxs2hq: 9356 case ARM::VCVTxu2fd: 9357 case ARM::VCVTxu2fq: 9358 case ARM::VCVTxu2hd: 9359 case ARM::VCVTxu2hq: { 9360 // op: Vd 9361 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9362 Value |= (op & UINT64_C(16)) << 18; 9363 Value |= (op & UINT64_C(15)) << 12; 9364 // op: Vm 9365 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9366 Value |= (op & UINT64_C(16)) << 1; 9367 Value |= (op & UINT64_C(15)); 9368 // op: SIMM 9369 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 9370 op &= UINT64_C(63); 9371 op <<= 16; 9372 Value |= op; 9373 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9374 break; 9375 } 9376 case ARM::VQRSHRNsv4i16: 9377 case ARM::VQRSHRNuv4i16: 9378 case ARM::VQRSHRUNv4i16: 9379 case ARM::VQSHRNsv4i16: 9380 case ARM::VQSHRNuv4i16: 9381 case ARM::VQSHRUNv4i16: 9382 case ARM::VRSHRNv4i16: 9383 case ARM::VRSHRsv4i16: 9384 case ARM::VRSHRsv8i16: 9385 case ARM::VRSHRuv4i16: 9386 case ARM::VRSHRuv8i16: 9387 case ARM::VSHRNv4i16: 9388 case ARM::VSHRsv4i16: 9389 case ARM::VSHRsv8i16: 9390 case ARM::VSHRuv4i16: 9391 case ARM::VSHRuv8i16: { 9392 // op: Vd 9393 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9394 Value |= (op & UINT64_C(16)) << 18; 9395 Value |= (op & UINT64_C(15)) << 12; 9396 // op: Vm 9397 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9398 Value |= (op & UINT64_C(16)) << 1; 9399 Value |= (op & UINT64_C(15)); 9400 // op: SIMM 9401 op = getShiftRight16Imm(MI, 2, Fixups, STI); 9402 op &= UINT64_C(15); 9403 op <<= 16; 9404 Value |= op; 9405 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9406 break; 9407 } 9408 case ARM::VQRSHRNsv2i32: 9409 case ARM::VQRSHRNuv2i32: 9410 case ARM::VQRSHRUNv2i32: 9411 case ARM::VQSHRNsv2i32: 9412 case ARM::VQSHRNuv2i32: 9413 case ARM::VQSHRUNv2i32: 9414 case ARM::VRSHRNv2i32: 9415 case ARM::VRSHRsv2i32: 9416 case ARM::VRSHRsv4i32: 9417 case ARM::VRSHRuv2i32: 9418 case ARM::VRSHRuv4i32: 9419 case ARM::VSHRNv2i32: 9420 case ARM::VSHRsv2i32: 9421 case ARM::VSHRsv4i32: 9422 case ARM::VSHRuv2i32: 9423 case ARM::VSHRuv4i32: { 9424 // op: Vd 9425 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9426 Value |= (op & UINT64_C(16)) << 18; 9427 Value |= (op & UINT64_C(15)) << 12; 9428 // op: Vm 9429 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9430 Value |= (op & UINT64_C(16)) << 1; 9431 Value |= (op & UINT64_C(15)); 9432 // op: SIMM 9433 op = getShiftRight32Imm(MI, 2, Fixups, STI); 9434 op &= UINT64_C(31); 9435 op <<= 16; 9436 Value |= op; 9437 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9438 break; 9439 } 9440 case ARM::VRSHRsv1i64: 9441 case ARM::VRSHRsv2i64: 9442 case ARM::VRSHRuv1i64: 9443 case ARM::VRSHRuv2i64: 9444 case ARM::VSHRsv1i64: 9445 case ARM::VSHRsv2i64: 9446 case ARM::VSHRuv1i64: 9447 case ARM::VSHRuv2i64: { 9448 // op: Vd 9449 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9450 Value |= (op & UINT64_C(16)) << 18; 9451 Value |= (op & UINT64_C(15)) << 12; 9452 // op: Vm 9453 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9454 Value |= (op & UINT64_C(16)) << 1; 9455 Value |= (op & UINT64_C(15)); 9456 // op: SIMM 9457 op = getShiftRight64Imm(MI, 2, Fixups, STI); 9458 op &= UINT64_C(63); 9459 op <<= 16; 9460 Value |= op; 9461 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9462 break; 9463 } 9464 case ARM::VQRSHRNsv8i8: 9465 case ARM::VQRSHRNuv8i8: 9466 case ARM::VQRSHRUNv8i8: 9467 case ARM::VQSHRNsv8i8: 9468 case ARM::VQSHRNuv8i8: 9469 case ARM::VQSHRUNv8i8: 9470 case ARM::VRSHRNv8i8: 9471 case ARM::VRSHRsv16i8: 9472 case ARM::VRSHRsv8i8: 9473 case ARM::VRSHRuv16i8: 9474 case ARM::VRSHRuv8i8: 9475 case ARM::VSHRNv8i8: 9476 case ARM::VSHRsv16i8: 9477 case ARM::VSHRsv8i8: 9478 case ARM::VSHRuv16i8: 9479 case ARM::VSHRuv8i8: { 9480 // op: Vd 9481 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9482 Value |= (op & UINT64_C(16)) << 18; 9483 Value |= (op & UINT64_C(15)) << 12; 9484 // op: Vm 9485 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9486 Value |= (op & UINT64_C(16)) << 1; 9487 Value |= (op & UINT64_C(15)); 9488 // op: SIMM 9489 op = getShiftRight8Imm(MI, 2, Fixups, STI); 9490 op &= UINT64_C(7); 9491 op <<= 16; 9492 Value |= op; 9493 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9494 break; 9495 } 9496 case ARM::VDUPLN32d: 9497 case ARM::VDUPLN32q: { 9498 // op: Vd 9499 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9500 Value |= (op & UINT64_C(16)) << 18; 9501 Value |= (op & UINT64_C(15)) << 12; 9502 // op: Vm 9503 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9504 Value |= (op & UINT64_C(16)) << 1; 9505 Value |= (op & UINT64_C(15)); 9506 // op: lane 9507 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9508 op &= UINT64_C(1); 9509 op <<= 19; 9510 Value |= op; 9511 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9512 break; 9513 } 9514 case ARM::VDUPLN16d: 9515 case ARM::VDUPLN16q: { 9516 // op: Vd 9517 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9518 Value |= (op & UINT64_C(16)) << 18; 9519 Value |= (op & UINT64_C(15)) << 12; 9520 // op: Vm 9521 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9522 Value |= (op & UINT64_C(16)) << 1; 9523 Value |= (op & UINT64_C(15)); 9524 // op: lane 9525 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9526 op &= UINT64_C(3); 9527 op <<= 18; 9528 Value |= op; 9529 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9530 break; 9531 } 9532 case ARM::VDUPLN8d: 9533 case ARM::VDUPLN8q: { 9534 // op: Vd 9535 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9536 Value |= (op & UINT64_C(16)) << 18; 9537 Value |= (op & UINT64_C(15)) << 12; 9538 // op: Vm 9539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9540 Value |= (op & UINT64_C(16)) << 1; 9541 Value |= (op & UINT64_C(15)); 9542 // op: lane 9543 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9544 op &= UINT64_C(7); 9545 op <<= 17; 9546 Value |= op; 9547 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9548 break; 9549 } 9550 case ARM::AESIMC: 9551 case ARM::AESMC: 9552 case ARM::SHA1H: 9553 case ARM::VABSfd: 9554 case ARM::VABSfq: 9555 case ARM::VABShd: 9556 case ARM::VABShq: 9557 case ARM::VABSv16i8: 9558 case ARM::VABSv2i32: 9559 case ARM::VABSv4i16: 9560 case ARM::VABSv4i32: 9561 case ARM::VABSv8i16: 9562 case ARM::VABSv8i8: 9563 case ARM::VCEQzv16i8: 9564 case ARM::VCEQzv2f32: 9565 case ARM::VCEQzv2i32: 9566 case ARM::VCEQzv4f16: 9567 case ARM::VCEQzv4f32: 9568 case ARM::VCEQzv4i16: 9569 case ARM::VCEQzv4i32: 9570 case ARM::VCEQzv8f16: 9571 case ARM::VCEQzv8i16: 9572 case ARM::VCEQzv8i8: 9573 case ARM::VCGEzv16i8: 9574 case ARM::VCGEzv2f32: 9575 case ARM::VCGEzv2i32: 9576 case ARM::VCGEzv4f16: 9577 case ARM::VCGEzv4f32: 9578 case ARM::VCGEzv4i16: 9579 case ARM::VCGEzv4i32: 9580 case ARM::VCGEzv8f16: 9581 case ARM::VCGEzv8i16: 9582 case ARM::VCGEzv8i8: 9583 case ARM::VCGTzv16i8: 9584 case ARM::VCGTzv2f32: 9585 case ARM::VCGTzv2i32: 9586 case ARM::VCGTzv4f16: 9587 case ARM::VCGTzv4f32: 9588 case ARM::VCGTzv4i16: 9589 case ARM::VCGTzv4i32: 9590 case ARM::VCGTzv8f16: 9591 case ARM::VCGTzv8i16: 9592 case ARM::VCGTzv8i8: 9593 case ARM::VCLEzv16i8: 9594 case ARM::VCLEzv2f32: 9595 case ARM::VCLEzv2i32: 9596 case ARM::VCLEzv4f16: 9597 case ARM::VCLEzv4f32: 9598 case ARM::VCLEzv4i16: 9599 case ARM::VCLEzv4i32: 9600 case ARM::VCLEzv8f16: 9601 case ARM::VCLEzv8i16: 9602 case ARM::VCLEzv8i8: 9603 case ARM::VCLSv16i8: 9604 case ARM::VCLSv2i32: 9605 case ARM::VCLSv4i16: 9606 case ARM::VCLSv4i32: 9607 case ARM::VCLSv8i16: 9608 case ARM::VCLSv8i8: 9609 case ARM::VCLTzv16i8: 9610 case ARM::VCLTzv2f32: 9611 case ARM::VCLTzv2i32: 9612 case ARM::VCLTzv4f16: 9613 case ARM::VCLTzv4f32: 9614 case ARM::VCLTzv4i16: 9615 case ARM::VCLTzv4i32: 9616 case ARM::VCLTzv8f16: 9617 case ARM::VCLTzv8i16: 9618 case ARM::VCLTzv8i8: 9619 case ARM::VCLZv16i8: 9620 case ARM::VCLZv2i32: 9621 case ARM::VCLZv4i16: 9622 case ARM::VCLZv4i32: 9623 case ARM::VCLZv8i16: 9624 case ARM::VCLZv8i8: 9625 case ARM::VCNTd: 9626 case ARM::VCNTq: 9627 case ARM::VCVTf2h: 9628 case ARM::VCVTf2sd: 9629 case ARM::VCVTf2sq: 9630 case ARM::VCVTf2ud: 9631 case ARM::VCVTf2uq: 9632 case ARM::VCVTh2f: 9633 case ARM::VCVTh2sd: 9634 case ARM::VCVTh2sq: 9635 case ARM::VCVTh2ud: 9636 case ARM::VCVTh2uq: 9637 case ARM::VCVTs2fd: 9638 case ARM::VCVTs2fq: 9639 case ARM::VCVTs2hd: 9640 case ARM::VCVTs2hq: 9641 case ARM::VCVTu2fd: 9642 case ARM::VCVTu2fq: 9643 case ARM::VCVTu2hd: 9644 case ARM::VCVTu2hq: 9645 case ARM::VMOVLsv2i64: 9646 case ARM::VMOVLsv4i32: 9647 case ARM::VMOVLsv8i16: 9648 case ARM::VMOVLuv2i64: 9649 case ARM::VMOVLuv4i32: 9650 case ARM::VMOVLuv8i16: 9651 case ARM::VMOVNv2i32: 9652 case ARM::VMOVNv4i16: 9653 case ARM::VMOVNv8i8: 9654 case ARM::VMVNd: 9655 case ARM::VMVNq: 9656 case ARM::VNEGf32q: 9657 case ARM::VNEGfd: 9658 case ARM::VNEGhd: 9659 case ARM::VNEGhq: 9660 case ARM::VNEGs16d: 9661 case ARM::VNEGs16q: 9662 case ARM::VNEGs32d: 9663 case ARM::VNEGs32q: 9664 case ARM::VNEGs8d: 9665 case ARM::VNEGs8q: 9666 case ARM::VPADDLsv16i8: 9667 case ARM::VPADDLsv2i32: 9668 case ARM::VPADDLsv4i16: 9669 case ARM::VPADDLsv4i32: 9670 case ARM::VPADDLsv8i16: 9671 case ARM::VPADDLsv8i8: 9672 case ARM::VPADDLuv16i8: 9673 case ARM::VPADDLuv2i32: 9674 case ARM::VPADDLuv4i16: 9675 case ARM::VPADDLuv4i32: 9676 case ARM::VPADDLuv8i16: 9677 case ARM::VPADDLuv8i8: 9678 case ARM::VQABSv16i8: 9679 case ARM::VQABSv2i32: 9680 case ARM::VQABSv4i16: 9681 case ARM::VQABSv4i32: 9682 case ARM::VQABSv8i16: 9683 case ARM::VQABSv8i8: 9684 case ARM::VQMOVNsuv2i32: 9685 case ARM::VQMOVNsuv4i16: 9686 case ARM::VQMOVNsuv8i8: 9687 case ARM::VQMOVNsv2i32: 9688 case ARM::VQMOVNsv4i16: 9689 case ARM::VQMOVNsv8i8: 9690 case ARM::VQMOVNuv2i32: 9691 case ARM::VQMOVNuv4i16: 9692 case ARM::VQMOVNuv8i8: 9693 case ARM::VQNEGv16i8: 9694 case ARM::VQNEGv2i32: 9695 case ARM::VQNEGv4i16: 9696 case ARM::VQNEGv4i32: 9697 case ARM::VQNEGv8i16: 9698 case ARM::VQNEGv8i8: 9699 case ARM::VRECPEd: 9700 case ARM::VRECPEfd: 9701 case ARM::VRECPEfq: 9702 case ARM::VRECPEhd: 9703 case ARM::VRECPEhq: 9704 case ARM::VRECPEq: 9705 case ARM::VREV16d8: 9706 case ARM::VREV16q8: 9707 case ARM::VREV32d16: 9708 case ARM::VREV32d8: 9709 case ARM::VREV32q16: 9710 case ARM::VREV32q8: 9711 case ARM::VREV64d16: 9712 case ARM::VREV64d32: 9713 case ARM::VREV64d8: 9714 case ARM::VREV64q16: 9715 case ARM::VREV64q32: 9716 case ARM::VREV64q8: 9717 case ARM::VRSQRTEd: 9718 case ARM::VRSQRTEfd: 9719 case ARM::VRSQRTEfq: 9720 case ARM::VRSQRTEhd: 9721 case ARM::VRSQRTEhq: 9722 case ARM::VRSQRTEq: 9723 case ARM::VSHLLi16: 9724 case ARM::VSHLLi32: 9725 case ARM::VSHLLi8: 9726 case ARM::VSWPd: 9727 case ARM::VSWPq: 9728 case ARM::VTRNd16: 9729 case ARM::VTRNd32: 9730 case ARM::VTRNd8: 9731 case ARM::VTRNq16: 9732 case ARM::VTRNq32: 9733 case ARM::VTRNq8: 9734 case ARM::VUZPd16: 9735 case ARM::VUZPd8: 9736 case ARM::VUZPq16: 9737 case ARM::VUZPq32: 9738 case ARM::VUZPq8: 9739 case ARM::VZIPd16: 9740 case ARM::VZIPd8: 9741 case ARM::VZIPq16: 9742 case ARM::VZIPq32: 9743 case ARM::VZIPq8: { 9744 // op: Vd 9745 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9746 Value |= (op & UINT64_C(16)) << 18; 9747 Value |= (op & UINT64_C(15)) << 12; 9748 // op: Vm 9749 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9750 Value |= (op & UINT64_C(16)) << 1; 9751 Value |= (op & UINT64_C(15)); 9752 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9753 break; 9754 } 9755 case ARM::VCVTANSDf: 9756 case ARM::VCVTANSDh: 9757 case ARM::VCVTANSQf: 9758 case ARM::VCVTANSQh: 9759 case ARM::VCVTANUDf: 9760 case ARM::VCVTANUDh: 9761 case ARM::VCVTANUQf: 9762 case ARM::VCVTANUQh: 9763 case ARM::VCVTMNSDf: 9764 case ARM::VCVTMNSDh: 9765 case ARM::VCVTMNSQf: 9766 case ARM::VCVTMNSQh: 9767 case ARM::VCVTMNUDf: 9768 case ARM::VCVTMNUDh: 9769 case ARM::VCVTMNUQf: 9770 case ARM::VCVTMNUQh: 9771 case ARM::VCVTNNSDf: 9772 case ARM::VCVTNNSDh: 9773 case ARM::VCVTNNSQf: 9774 case ARM::VCVTNNSQh: 9775 case ARM::VCVTNNUDf: 9776 case ARM::VCVTNNUDh: 9777 case ARM::VCVTNNUQf: 9778 case ARM::VCVTNNUQh: 9779 case ARM::VCVTPNSDf: 9780 case ARM::VCVTPNSDh: 9781 case ARM::VCVTPNSQf: 9782 case ARM::VCVTPNSQh: 9783 case ARM::VCVTPNUDf: 9784 case ARM::VCVTPNUDh: 9785 case ARM::VCVTPNUQf: 9786 case ARM::VCVTPNUQh: 9787 case ARM::VRINTANDf: 9788 case ARM::VRINTANDh: 9789 case ARM::VRINTANQf: 9790 case ARM::VRINTANQh: 9791 case ARM::VRINTMNDf: 9792 case ARM::VRINTMNDh: 9793 case ARM::VRINTMNQf: 9794 case ARM::VRINTMNQh: 9795 case ARM::VRINTNNDf: 9796 case ARM::VRINTNNDh: 9797 case ARM::VRINTNNQf: 9798 case ARM::VRINTNNQh: 9799 case ARM::VRINTPNDf: 9800 case ARM::VRINTPNDh: 9801 case ARM::VRINTPNQf: 9802 case ARM::VRINTPNQh: 9803 case ARM::VRINTXNDf: 9804 case ARM::VRINTXNDh: 9805 case ARM::VRINTXNQf: 9806 case ARM::VRINTXNQh: 9807 case ARM::VRINTZNDf: 9808 case ARM::VRINTZNDh: 9809 case ARM::VRINTZNQf: 9810 case ARM::VRINTZNQh: { 9811 // op: Vd 9812 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9813 Value |= (op & UINT64_C(16)) << 18; 9814 Value |= (op & UINT64_C(15)) << 12; 9815 // op: Vm 9816 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9817 Value |= (op & UINT64_C(16)) << 1; 9818 Value |= (op & UINT64_C(15)); 9819 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 9820 break; 9821 } 9822 case ARM::VSLIv4i16: 9823 case ARM::VSLIv8i16: { 9824 // op: Vd 9825 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9826 Value |= (op & UINT64_C(16)) << 18; 9827 Value |= (op & UINT64_C(15)) << 12; 9828 // op: Vm 9829 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9830 Value |= (op & UINT64_C(16)) << 1; 9831 Value |= (op & UINT64_C(15)); 9832 // op: SIMM 9833 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9834 op &= UINT64_C(15); 9835 op <<= 16; 9836 Value |= op; 9837 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9838 break; 9839 } 9840 case ARM::VSLIv2i32: 9841 case ARM::VSLIv4i32: { 9842 // op: Vd 9843 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9844 Value |= (op & UINT64_C(16)) << 18; 9845 Value |= (op & UINT64_C(15)) << 12; 9846 // op: Vm 9847 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9848 Value |= (op & UINT64_C(16)) << 1; 9849 Value |= (op & UINT64_C(15)); 9850 // op: SIMM 9851 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9852 op &= UINT64_C(31); 9853 op <<= 16; 9854 Value |= op; 9855 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9856 break; 9857 } 9858 case ARM::VSLIv1i64: 9859 case ARM::VSLIv2i64: { 9860 // op: Vd 9861 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9862 Value |= (op & UINT64_C(16)) << 18; 9863 Value |= (op & UINT64_C(15)) << 12; 9864 // op: Vm 9865 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9866 Value |= (op & UINT64_C(16)) << 1; 9867 Value |= (op & UINT64_C(15)); 9868 // op: SIMM 9869 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9870 op &= UINT64_C(63); 9871 op <<= 16; 9872 Value |= op; 9873 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9874 break; 9875 } 9876 case ARM::VSLIv16i8: 9877 case ARM::VSLIv8i8: { 9878 // op: Vd 9879 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9880 Value |= (op & UINT64_C(16)) << 18; 9881 Value |= (op & UINT64_C(15)) << 12; 9882 // op: Vm 9883 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9884 Value |= (op & UINT64_C(16)) << 1; 9885 Value |= (op & UINT64_C(15)); 9886 // op: SIMM 9887 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9888 op &= UINT64_C(7); 9889 op <<= 16; 9890 Value |= op; 9891 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9892 break; 9893 } 9894 case ARM::VRSRAsv4i16: 9895 case ARM::VRSRAsv8i16: 9896 case ARM::VRSRAuv4i16: 9897 case ARM::VRSRAuv8i16: 9898 case ARM::VSRAsv4i16: 9899 case ARM::VSRAsv8i16: 9900 case ARM::VSRAuv4i16: 9901 case ARM::VSRAuv8i16: 9902 case ARM::VSRIv4i16: 9903 case ARM::VSRIv8i16: { 9904 // op: Vd 9905 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9906 Value |= (op & UINT64_C(16)) << 18; 9907 Value |= (op & UINT64_C(15)) << 12; 9908 // op: Vm 9909 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9910 Value |= (op & UINT64_C(16)) << 1; 9911 Value |= (op & UINT64_C(15)); 9912 // op: SIMM 9913 op = getShiftRight16Imm(MI, 3, Fixups, STI); 9914 op &= UINT64_C(15); 9915 op <<= 16; 9916 Value |= op; 9917 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9918 break; 9919 } 9920 case ARM::VRSRAsv2i32: 9921 case ARM::VRSRAsv4i32: 9922 case ARM::VRSRAuv2i32: 9923 case ARM::VRSRAuv4i32: 9924 case ARM::VSRAsv2i32: 9925 case ARM::VSRAsv4i32: 9926 case ARM::VSRAuv2i32: 9927 case ARM::VSRAuv4i32: 9928 case ARM::VSRIv2i32: 9929 case ARM::VSRIv4i32: { 9930 // op: Vd 9931 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9932 Value |= (op & UINT64_C(16)) << 18; 9933 Value |= (op & UINT64_C(15)) << 12; 9934 // op: Vm 9935 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9936 Value |= (op & UINT64_C(16)) << 1; 9937 Value |= (op & UINT64_C(15)); 9938 // op: SIMM 9939 op = getShiftRight32Imm(MI, 3, Fixups, STI); 9940 op &= UINT64_C(31); 9941 op <<= 16; 9942 Value |= op; 9943 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9944 break; 9945 } 9946 case ARM::VRSRAsv1i64: 9947 case ARM::VRSRAsv2i64: 9948 case ARM::VRSRAuv1i64: 9949 case ARM::VRSRAuv2i64: 9950 case ARM::VSRAsv1i64: 9951 case ARM::VSRAsv2i64: 9952 case ARM::VSRAuv1i64: 9953 case ARM::VSRAuv2i64: 9954 case ARM::VSRIv1i64: 9955 case ARM::VSRIv2i64: { 9956 // op: Vd 9957 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9958 Value |= (op & UINT64_C(16)) << 18; 9959 Value |= (op & UINT64_C(15)) << 12; 9960 // op: Vm 9961 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9962 Value |= (op & UINT64_C(16)) << 1; 9963 Value |= (op & UINT64_C(15)); 9964 // op: SIMM 9965 op = getShiftRight64Imm(MI, 3, Fixups, STI); 9966 op &= UINT64_C(63); 9967 op <<= 16; 9968 Value |= op; 9969 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9970 break; 9971 } 9972 case ARM::VRSRAsv16i8: 9973 case ARM::VRSRAsv8i8: 9974 case ARM::VRSRAuv16i8: 9975 case ARM::VRSRAuv8i8: 9976 case ARM::VSRAsv16i8: 9977 case ARM::VSRAsv8i8: 9978 case ARM::VSRAuv16i8: 9979 case ARM::VSRAuv8i8: 9980 case ARM::VSRIv16i8: 9981 case ARM::VSRIv8i8: { 9982 // op: Vd 9983 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9984 Value |= (op & UINT64_C(16)) << 18; 9985 Value |= (op & UINT64_C(15)) << 12; 9986 // op: Vm 9987 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9988 Value |= (op & UINT64_C(16)) << 1; 9989 Value |= (op & UINT64_C(15)); 9990 // op: SIMM 9991 op = getShiftRight8Imm(MI, 3, Fixups, STI); 9992 op &= UINT64_C(7); 9993 op <<= 16; 9994 Value |= op; 9995 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 9996 break; 9997 } 9998 case ARM::AESD: 9999 case ARM::AESE: 10000 case ARM::SHA1SU1: 10001 case ARM::SHA256SU0: 10002 case ARM::VPADALsv16i8: 10003 case ARM::VPADALsv2i32: 10004 case ARM::VPADALsv4i16: 10005 case ARM::VPADALsv4i32: 10006 case ARM::VPADALsv8i16: 10007 case ARM::VPADALsv8i8: 10008 case ARM::VPADALuv16i8: 10009 case ARM::VPADALuv2i32: 10010 case ARM::VPADALuv4i16: 10011 case ARM::VPADALuv4i32: 10012 case ARM::VPADALuv8i16: 10013 case ARM::VPADALuv8i8: { 10014 // op: Vd 10015 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10016 Value |= (op & UINT64_C(16)) << 18; 10017 Value |= (op & UINT64_C(15)) << 12; 10018 // op: Vm 10019 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10020 Value |= (op & UINT64_C(16)) << 1; 10021 Value |= (op & UINT64_C(15)); 10022 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10023 break; 10024 } 10025 case ARM::VFMALQ: 10026 case ARM::VFMSLQ: { 10027 // op: Vd 10028 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10029 Value |= (op & UINT64_C(16)) << 18; 10030 Value |= (op & UINT64_C(15)) << 12; 10031 // op: Vn 10032 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10033 Value |= (op & UINT64_C(15)) << 16; 10034 Value |= (op & UINT64_C(16)) << 3; 10035 // op: Vm 10036 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10037 Value |= (op & UINT64_C(16)) << 1; 10038 Value |= (op & UINT64_C(15)); 10039 break; 10040 } 10041 case ARM::VEXTd32: { 10042 // op: Vd 10043 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10044 Value |= (op & UINT64_C(16)) << 18; 10045 Value |= (op & UINT64_C(15)) << 12; 10046 // op: Vn 10047 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10048 Value |= (op & UINT64_C(15)) << 16; 10049 Value |= (op & UINT64_C(16)) << 3; 10050 // op: Vm 10051 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10052 Value |= (op & UINT64_C(16)) << 1; 10053 Value |= (op & UINT64_C(15)); 10054 // op: index 10055 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10056 op &= UINT64_C(1); 10057 op <<= 10; 10058 Value |= op; 10059 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10060 break; 10061 } 10062 case ARM::VEXTq64: { 10063 // op: Vd 10064 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10065 Value |= (op & UINT64_C(16)) << 18; 10066 Value |= (op & UINT64_C(15)) << 12; 10067 // op: Vn 10068 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10069 Value |= (op & UINT64_C(15)) << 16; 10070 Value |= (op & UINT64_C(16)) << 3; 10071 // op: Vm 10072 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10073 Value |= (op & UINT64_C(16)) << 1; 10074 Value |= (op & UINT64_C(15)); 10075 // op: index 10076 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10077 op &= UINT64_C(1); 10078 op <<= 11; 10079 Value |= op; 10080 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10081 break; 10082 } 10083 case ARM::VEXTq8: { 10084 // op: Vd 10085 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10086 Value |= (op & UINT64_C(16)) << 18; 10087 Value |= (op & UINT64_C(15)) << 12; 10088 // op: Vn 10089 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10090 Value |= (op & UINT64_C(15)) << 16; 10091 Value |= (op & UINT64_C(16)) << 3; 10092 // op: Vm 10093 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10094 Value |= (op & UINT64_C(16)) << 1; 10095 Value |= (op & UINT64_C(15)); 10096 // op: index 10097 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10098 op &= UINT64_C(15); 10099 op <<= 8; 10100 Value |= op; 10101 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10102 break; 10103 } 10104 case ARM::VEXTq32: { 10105 // op: Vd 10106 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10107 Value |= (op & UINT64_C(16)) << 18; 10108 Value |= (op & UINT64_C(15)) << 12; 10109 // op: Vn 10110 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10111 Value |= (op & UINT64_C(15)) << 16; 10112 Value |= (op & UINT64_C(16)) << 3; 10113 // op: Vm 10114 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10115 Value |= (op & UINT64_C(16)) << 1; 10116 Value |= (op & UINT64_C(15)); 10117 // op: index 10118 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10119 op &= UINT64_C(3); 10120 op <<= 10; 10121 Value |= op; 10122 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10123 break; 10124 } 10125 case ARM::VEXTd16: { 10126 // op: Vd 10127 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10128 Value |= (op & UINT64_C(16)) << 18; 10129 Value |= (op & UINT64_C(15)) << 12; 10130 // op: Vn 10131 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10132 Value |= (op & UINT64_C(15)) << 16; 10133 Value |= (op & UINT64_C(16)) << 3; 10134 // op: Vm 10135 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10136 Value |= (op & UINT64_C(16)) << 1; 10137 Value |= (op & UINT64_C(15)); 10138 // op: index 10139 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10140 op &= UINT64_C(3); 10141 op <<= 9; 10142 Value |= op; 10143 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10144 break; 10145 } 10146 case ARM::VEXTd8: { 10147 // op: Vd 10148 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10149 Value |= (op & UINT64_C(16)) << 18; 10150 Value |= (op & UINT64_C(15)) << 12; 10151 // op: Vn 10152 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10153 Value |= (op & UINT64_C(15)) << 16; 10154 Value |= (op & UINT64_C(16)) << 3; 10155 // op: Vm 10156 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10157 Value |= (op & UINT64_C(16)) << 1; 10158 Value |= (op & UINT64_C(15)); 10159 // op: index 10160 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10161 op &= UINT64_C(7); 10162 op <<= 8; 10163 Value |= op; 10164 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10165 break; 10166 } 10167 case ARM::VEXTq16: { 10168 // op: Vd 10169 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10170 Value |= (op & UINT64_C(16)) << 18; 10171 Value |= (op & UINT64_C(15)) << 12; 10172 // op: Vn 10173 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10174 Value |= (op & UINT64_C(15)) << 16; 10175 Value |= (op & UINT64_C(16)) << 3; 10176 // op: Vm 10177 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10178 Value |= (op & UINT64_C(16)) << 1; 10179 Value |= (op & UINT64_C(15)); 10180 // op: index 10181 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10182 op &= UINT64_C(7); 10183 op <<= 9; 10184 Value |= op; 10185 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10186 break; 10187 } 10188 case ARM::VCADDv2f32: 10189 case ARM::VCADDv4f16: 10190 case ARM::VCADDv4f32: 10191 case ARM::VCADDv8f16: { 10192 // op: Vd 10193 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10194 Value |= (op & UINT64_C(16)) << 18; 10195 Value |= (op & UINT64_C(15)) << 12; 10196 // op: Vn 10197 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10198 Value |= (op & UINT64_C(15)) << 16; 10199 Value |= (op & UINT64_C(16)) << 3; 10200 // op: Vm 10201 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10202 Value |= (op & UINT64_C(16)) << 1; 10203 Value |= (op & UINT64_C(15)); 10204 // op: rot 10205 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10206 op &= UINT64_C(1); 10207 op <<= 24; 10208 Value |= op; 10209 break; 10210 } 10211 case ARM::VABDLsv2i64: 10212 case ARM::VABDLsv4i32: 10213 case ARM::VABDLsv8i16: 10214 case ARM::VABDLuv2i64: 10215 case ARM::VABDLuv4i32: 10216 case ARM::VABDLuv8i16: 10217 case ARM::VABDfd: 10218 case ARM::VABDfq: 10219 case ARM::VABDhd: 10220 case ARM::VABDhq: 10221 case ARM::VABDsv16i8: 10222 case ARM::VABDsv2i32: 10223 case ARM::VABDsv4i16: 10224 case ARM::VABDsv4i32: 10225 case ARM::VABDsv8i16: 10226 case ARM::VABDsv8i8: 10227 case ARM::VABDuv16i8: 10228 case ARM::VABDuv2i32: 10229 case ARM::VABDuv4i16: 10230 case ARM::VABDuv4i32: 10231 case ARM::VABDuv8i16: 10232 case ARM::VABDuv8i8: 10233 case ARM::VACGEfd: 10234 case ARM::VACGEfq: 10235 case ARM::VACGEhd: 10236 case ARM::VACGEhq: 10237 case ARM::VACGTfd: 10238 case ARM::VACGTfq: 10239 case ARM::VACGThd: 10240 case ARM::VACGThq: 10241 case ARM::VADDHNv2i32: 10242 case ARM::VADDHNv4i16: 10243 case ARM::VADDHNv8i8: 10244 case ARM::VADDLsv2i64: 10245 case ARM::VADDLsv4i32: 10246 case ARM::VADDLsv8i16: 10247 case ARM::VADDLuv2i64: 10248 case ARM::VADDLuv4i32: 10249 case ARM::VADDLuv8i16: 10250 case ARM::VADDWsv2i64: 10251 case ARM::VADDWsv4i32: 10252 case ARM::VADDWsv8i16: 10253 case ARM::VADDWuv2i64: 10254 case ARM::VADDWuv4i32: 10255 case ARM::VADDWuv8i16: 10256 case ARM::VADDfd: 10257 case ARM::VADDfq: 10258 case ARM::VADDhd: 10259 case ARM::VADDhq: 10260 case ARM::VADDv16i8: 10261 case ARM::VADDv1i64: 10262 case ARM::VADDv2i32: 10263 case ARM::VADDv2i64: 10264 case ARM::VADDv4i16: 10265 case ARM::VADDv4i32: 10266 case ARM::VADDv8i16: 10267 case ARM::VADDv8i8: 10268 case ARM::VANDd: 10269 case ARM::VANDq: 10270 case ARM::VBICd: 10271 case ARM::VBICq: 10272 case ARM::VCEQfd: 10273 case ARM::VCEQfq: 10274 case ARM::VCEQhd: 10275 case ARM::VCEQhq: 10276 case ARM::VCEQv16i8: 10277 case ARM::VCEQv2i32: 10278 case ARM::VCEQv4i16: 10279 case ARM::VCEQv4i32: 10280 case ARM::VCEQv8i16: 10281 case ARM::VCEQv8i8: 10282 case ARM::VCGEfd: 10283 case ARM::VCGEfq: 10284 case ARM::VCGEhd: 10285 case ARM::VCGEhq: 10286 case ARM::VCGEsv16i8: 10287 case ARM::VCGEsv2i32: 10288 case ARM::VCGEsv4i16: 10289 case ARM::VCGEsv4i32: 10290 case ARM::VCGEsv8i16: 10291 case ARM::VCGEsv8i8: 10292 case ARM::VCGEuv16i8: 10293 case ARM::VCGEuv2i32: 10294 case ARM::VCGEuv4i16: 10295 case ARM::VCGEuv4i32: 10296 case ARM::VCGEuv8i16: 10297 case ARM::VCGEuv8i8: 10298 case ARM::VCGTfd: 10299 case ARM::VCGTfq: 10300 case ARM::VCGThd: 10301 case ARM::VCGThq: 10302 case ARM::VCGTsv16i8: 10303 case ARM::VCGTsv2i32: 10304 case ARM::VCGTsv4i16: 10305 case ARM::VCGTsv4i32: 10306 case ARM::VCGTsv8i16: 10307 case ARM::VCGTsv8i8: 10308 case ARM::VCGTuv16i8: 10309 case ARM::VCGTuv2i32: 10310 case ARM::VCGTuv4i16: 10311 case ARM::VCGTuv4i32: 10312 case ARM::VCGTuv8i16: 10313 case ARM::VCGTuv8i8: 10314 case ARM::VEORd: 10315 case ARM::VEORq: 10316 case ARM::VHADDsv16i8: 10317 case ARM::VHADDsv2i32: 10318 case ARM::VHADDsv4i16: 10319 case ARM::VHADDsv4i32: 10320 case ARM::VHADDsv8i16: 10321 case ARM::VHADDsv8i8: 10322 case ARM::VHADDuv16i8: 10323 case ARM::VHADDuv2i32: 10324 case ARM::VHADDuv4i16: 10325 case ARM::VHADDuv4i32: 10326 case ARM::VHADDuv8i16: 10327 case ARM::VHADDuv8i8: 10328 case ARM::VHSUBsv16i8: 10329 case ARM::VHSUBsv2i32: 10330 case ARM::VHSUBsv4i16: 10331 case ARM::VHSUBsv4i32: 10332 case ARM::VHSUBsv8i16: 10333 case ARM::VHSUBsv8i8: 10334 case ARM::VHSUBuv16i8: 10335 case ARM::VHSUBuv2i32: 10336 case ARM::VHSUBuv4i16: 10337 case ARM::VHSUBuv4i32: 10338 case ARM::VHSUBuv8i16: 10339 case ARM::VHSUBuv8i8: 10340 case ARM::VMAXfd: 10341 case ARM::VMAXfq: 10342 case ARM::VMAXhd: 10343 case ARM::VMAXhq: 10344 case ARM::VMAXsv16i8: 10345 case ARM::VMAXsv2i32: 10346 case ARM::VMAXsv4i16: 10347 case ARM::VMAXsv4i32: 10348 case ARM::VMAXsv8i16: 10349 case ARM::VMAXsv8i8: 10350 case ARM::VMAXuv16i8: 10351 case ARM::VMAXuv2i32: 10352 case ARM::VMAXuv4i16: 10353 case ARM::VMAXuv4i32: 10354 case ARM::VMAXuv8i16: 10355 case ARM::VMAXuv8i8: 10356 case ARM::VMINfd: 10357 case ARM::VMINfq: 10358 case ARM::VMINhd: 10359 case ARM::VMINhq: 10360 case ARM::VMINsv16i8: 10361 case ARM::VMINsv2i32: 10362 case ARM::VMINsv4i16: 10363 case ARM::VMINsv4i32: 10364 case ARM::VMINsv8i16: 10365 case ARM::VMINsv8i8: 10366 case ARM::VMINuv16i8: 10367 case ARM::VMINuv2i32: 10368 case ARM::VMINuv4i16: 10369 case ARM::VMINuv4i32: 10370 case ARM::VMINuv8i16: 10371 case ARM::VMINuv8i8: 10372 case ARM::VMULLp64: 10373 case ARM::VMULLp8: 10374 case ARM::VMULLsv2i64: 10375 case ARM::VMULLsv4i32: 10376 case ARM::VMULLsv8i16: 10377 case ARM::VMULLuv2i64: 10378 case ARM::VMULLuv4i32: 10379 case ARM::VMULLuv8i16: 10380 case ARM::VMULfd: 10381 case ARM::VMULfq: 10382 case ARM::VMULhd: 10383 case ARM::VMULhq: 10384 case ARM::VMULpd: 10385 case ARM::VMULpq: 10386 case ARM::VMULv16i8: 10387 case ARM::VMULv2i32: 10388 case ARM::VMULv4i16: 10389 case ARM::VMULv4i32: 10390 case ARM::VMULv8i16: 10391 case ARM::VMULv8i8: 10392 case ARM::VORNd: 10393 case ARM::VORNq: 10394 case ARM::VORRd: 10395 case ARM::VORRq: 10396 case ARM::VPADDf: 10397 case ARM::VPADDh: 10398 case ARM::VPADDi16: 10399 case ARM::VPADDi32: 10400 case ARM::VPADDi8: 10401 case ARM::VPMAXf: 10402 case ARM::VPMAXh: 10403 case ARM::VPMAXs16: 10404 case ARM::VPMAXs32: 10405 case ARM::VPMAXs8: 10406 case ARM::VPMAXu16: 10407 case ARM::VPMAXu32: 10408 case ARM::VPMAXu8: 10409 case ARM::VPMINf: 10410 case ARM::VPMINh: 10411 case ARM::VPMINs16: 10412 case ARM::VPMINs32: 10413 case ARM::VPMINs8: 10414 case ARM::VPMINu16: 10415 case ARM::VPMINu32: 10416 case ARM::VPMINu8: 10417 case ARM::VQADDsv16i8: 10418 case ARM::VQADDsv1i64: 10419 case ARM::VQADDsv2i32: 10420 case ARM::VQADDsv2i64: 10421 case ARM::VQADDsv4i16: 10422 case ARM::VQADDsv4i32: 10423 case ARM::VQADDsv8i16: 10424 case ARM::VQADDsv8i8: 10425 case ARM::VQADDuv16i8: 10426 case ARM::VQADDuv1i64: 10427 case ARM::VQADDuv2i32: 10428 case ARM::VQADDuv2i64: 10429 case ARM::VQADDuv4i16: 10430 case ARM::VQADDuv4i32: 10431 case ARM::VQADDuv8i16: 10432 case ARM::VQADDuv8i8: 10433 case ARM::VQDMULHv2i32: 10434 case ARM::VQDMULHv4i16: 10435 case ARM::VQDMULHv4i32: 10436 case ARM::VQDMULHv8i16: 10437 case ARM::VQDMULLv2i64: 10438 case ARM::VQDMULLv4i32: 10439 case ARM::VQRDMULHv2i32: 10440 case ARM::VQRDMULHv4i16: 10441 case ARM::VQRDMULHv4i32: 10442 case ARM::VQRDMULHv8i16: 10443 case ARM::VQSUBsv16i8: 10444 case ARM::VQSUBsv1i64: 10445 case ARM::VQSUBsv2i32: 10446 case ARM::VQSUBsv2i64: 10447 case ARM::VQSUBsv4i16: 10448 case ARM::VQSUBsv4i32: 10449 case ARM::VQSUBsv8i16: 10450 case ARM::VQSUBsv8i8: 10451 case ARM::VQSUBuv16i8: 10452 case ARM::VQSUBuv1i64: 10453 case ARM::VQSUBuv2i32: 10454 case ARM::VQSUBuv2i64: 10455 case ARM::VQSUBuv4i16: 10456 case ARM::VQSUBuv4i32: 10457 case ARM::VQSUBuv8i16: 10458 case ARM::VQSUBuv8i8: 10459 case ARM::VRADDHNv2i32: 10460 case ARM::VRADDHNv4i16: 10461 case ARM::VRADDHNv8i8: 10462 case ARM::VRECPSfd: 10463 case ARM::VRECPSfq: 10464 case ARM::VRECPShd: 10465 case ARM::VRECPShq: 10466 case ARM::VRHADDsv16i8: 10467 case ARM::VRHADDsv2i32: 10468 case ARM::VRHADDsv4i16: 10469 case ARM::VRHADDsv4i32: 10470 case ARM::VRHADDsv8i16: 10471 case ARM::VRHADDsv8i8: 10472 case ARM::VRHADDuv16i8: 10473 case ARM::VRHADDuv2i32: 10474 case ARM::VRHADDuv4i16: 10475 case ARM::VRHADDuv4i32: 10476 case ARM::VRHADDuv8i16: 10477 case ARM::VRHADDuv8i8: 10478 case ARM::VRSQRTSfd: 10479 case ARM::VRSQRTSfq: 10480 case ARM::VRSQRTShd: 10481 case ARM::VRSQRTShq: 10482 case ARM::VRSUBHNv2i32: 10483 case ARM::VRSUBHNv4i16: 10484 case ARM::VRSUBHNv8i8: 10485 case ARM::VSUBHNv2i32: 10486 case ARM::VSUBHNv4i16: 10487 case ARM::VSUBHNv8i8: 10488 case ARM::VSUBLsv2i64: 10489 case ARM::VSUBLsv4i32: 10490 case ARM::VSUBLsv8i16: 10491 case ARM::VSUBLuv2i64: 10492 case ARM::VSUBLuv4i32: 10493 case ARM::VSUBLuv8i16: 10494 case ARM::VSUBWsv2i64: 10495 case ARM::VSUBWsv4i32: 10496 case ARM::VSUBWsv8i16: 10497 case ARM::VSUBWuv2i64: 10498 case ARM::VSUBWuv4i32: 10499 case ARM::VSUBWuv8i16: 10500 case ARM::VSUBfd: 10501 case ARM::VSUBfq: 10502 case ARM::VSUBhd: 10503 case ARM::VSUBhq: 10504 case ARM::VSUBv16i8: 10505 case ARM::VSUBv1i64: 10506 case ARM::VSUBv2i32: 10507 case ARM::VSUBv2i64: 10508 case ARM::VSUBv4i16: 10509 case ARM::VSUBv4i32: 10510 case ARM::VSUBv8i16: 10511 case ARM::VSUBv8i8: 10512 case ARM::VTBL1: 10513 case ARM::VTBL2: 10514 case ARM::VTBL3: 10515 case ARM::VTBL4: 10516 case ARM::VTSTv16i8: 10517 case ARM::VTSTv2i32: 10518 case ARM::VTSTv4i16: 10519 case ARM::VTSTv4i32: 10520 case ARM::VTSTv8i16: 10521 case ARM::VTSTv8i8: { 10522 // op: Vd 10523 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10524 Value |= (op & UINT64_C(16)) << 18; 10525 Value |= (op & UINT64_C(15)) << 12; 10526 // op: Vn 10527 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10528 Value |= (op & UINT64_C(15)) << 16; 10529 Value |= (op & UINT64_C(16)) << 3; 10530 // op: Vm 10531 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10532 Value |= (op & UINT64_C(16)) << 1; 10533 Value |= (op & UINT64_C(15)); 10534 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10535 break; 10536 } 10537 case ARM::NEON_VMAXNMNDf: 10538 case ARM::NEON_VMAXNMNDh: 10539 case ARM::NEON_VMAXNMNQf: 10540 case ARM::NEON_VMAXNMNQh: 10541 case ARM::NEON_VMINNMNDf: 10542 case ARM::NEON_VMINNMNDh: 10543 case ARM::NEON_VMINNMNQf: 10544 case ARM::NEON_VMINNMNQh: { 10545 // op: Vd 10546 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10547 Value |= (op & UINT64_C(16)) << 18; 10548 Value |= (op & UINT64_C(15)) << 12; 10549 // op: Vn 10550 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10551 Value |= (op & UINT64_C(15)) << 16; 10552 Value |= (op & UINT64_C(16)) << 3; 10553 // op: Vm 10554 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10555 Value |= (op & UINT64_C(16)) << 1; 10556 Value |= (op & UINT64_C(15)); 10557 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 10558 break; 10559 } 10560 case ARM::VMULLslsv2i32: 10561 case ARM::VMULLsluv2i32: 10562 case ARM::VMULslfd: 10563 case ARM::VMULslfq: 10564 case ARM::VMULslv2i32: 10565 case ARM::VMULslv4i32: 10566 case ARM::VQDMULHslv2i32: 10567 case ARM::VQDMULHslv4i32: 10568 case ARM::VQDMULLslv2i32: 10569 case ARM::VQRDMULHslv2i32: 10570 case ARM::VQRDMULHslv4i32: { 10571 // op: Vd 10572 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10573 Value |= (op & UINT64_C(16)) << 18; 10574 Value |= (op & UINT64_C(15)) << 12; 10575 // op: Vn 10576 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10577 Value |= (op & UINT64_C(15)) << 16; 10578 Value |= (op & UINT64_C(16)) << 3; 10579 // op: Vm 10580 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10581 op &= UINT64_C(15); 10582 Value |= op; 10583 // op: lane 10584 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10585 op &= UINT64_C(1); 10586 op <<= 5; 10587 Value |= op; 10588 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10589 break; 10590 } 10591 case ARM::VFMALQI: 10592 case ARM::VFMSLQI: { 10593 // op: Vd 10594 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10595 Value |= (op & UINT64_C(16)) << 18; 10596 Value |= (op & UINT64_C(15)) << 12; 10597 // op: Vn 10598 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10599 Value |= (op & UINT64_C(15)) << 16; 10600 Value |= (op & UINT64_C(16)) << 3; 10601 // op: Vm 10602 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10603 op &= UINT64_C(7); 10604 Value |= op; 10605 // op: idx 10606 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10607 Value |= (op & UINT64_C(2)) << 4; 10608 Value |= (op & UINT64_C(1)) << 3; 10609 break; 10610 } 10611 case ARM::VMULLslsv4i16: 10612 case ARM::VMULLsluv4i16: 10613 case ARM::VMULslhd: 10614 case ARM::VMULslhq: 10615 case ARM::VMULslv4i16: 10616 case ARM::VMULslv8i16: 10617 case ARM::VQDMULHslv4i16: 10618 case ARM::VQDMULHslv8i16: 10619 case ARM::VQDMULLslv4i16: 10620 case ARM::VQRDMULHslv4i16: 10621 case ARM::VQRDMULHslv8i16: { 10622 // op: Vd 10623 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10624 Value |= (op & UINT64_C(16)) << 18; 10625 Value |= (op & UINT64_C(15)) << 12; 10626 // op: Vn 10627 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10628 Value |= (op & UINT64_C(15)) << 16; 10629 Value |= (op & UINT64_C(16)) << 3; 10630 // op: Vm 10631 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10632 op &= UINT64_C(7); 10633 Value |= op; 10634 // op: lane 10635 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10636 Value |= (op & UINT64_C(2)) << 4; 10637 Value |= (op & UINT64_C(1)) << 3; 10638 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10639 break; 10640 } 10641 case ARM::VFMALDI: 10642 case ARM::VFMSLDI: { 10643 // op: Vd 10644 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10645 Value |= (op & UINT64_C(16)) << 18; 10646 Value |= (op & UINT64_C(15)) << 12; 10647 // op: Vn 10648 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10649 Value |= (op & UINT64_C(30)) << 15; 10650 Value |= (op & UINT64_C(1)) << 7; 10651 // op: Vm 10652 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10653 Value |= (op & UINT64_C(1)) << 5; 10654 Value |= (op & UINT64_C(14)) >> 1; 10655 // op: idx 10656 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10657 op &= UINT64_C(1); 10658 op <<= 3; 10659 Value |= op; 10660 break; 10661 } 10662 case ARM::VFMALD: 10663 case ARM::VFMSLD: { 10664 // op: Vd 10665 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10666 Value |= (op & UINT64_C(16)) << 18; 10667 Value |= (op & UINT64_C(15)) << 12; 10668 // op: Vn 10669 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10670 Value |= (op & UINT64_C(30)) << 15; 10671 Value |= (op & UINT64_C(1)) << 7; 10672 // op: Vm 10673 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10674 Value |= (op & UINT64_C(1)) << 5; 10675 Value |= (op & UINT64_C(30)) >> 1; 10676 break; 10677 } 10678 case ARM::VQRSHLsv16i8: 10679 case ARM::VQRSHLsv1i64: 10680 case ARM::VQRSHLsv2i32: 10681 case ARM::VQRSHLsv2i64: 10682 case ARM::VQRSHLsv4i16: 10683 case ARM::VQRSHLsv4i32: 10684 case ARM::VQRSHLsv8i16: 10685 case ARM::VQRSHLsv8i8: 10686 case ARM::VQRSHLuv16i8: 10687 case ARM::VQRSHLuv1i64: 10688 case ARM::VQRSHLuv2i32: 10689 case ARM::VQRSHLuv2i64: 10690 case ARM::VQRSHLuv4i16: 10691 case ARM::VQRSHLuv4i32: 10692 case ARM::VQRSHLuv8i16: 10693 case ARM::VQRSHLuv8i8: 10694 case ARM::VQSHLsv16i8: 10695 case ARM::VQSHLsv1i64: 10696 case ARM::VQSHLsv2i32: 10697 case ARM::VQSHLsv2i64: 10698 case ARM::VQSHLsv4i16: 10699 case ARM::VQSHLsv4i32: 10700 case ARM::VQSHLsv8i16: 10701 case ARM::VQSHLsv8i8: 10702 case ARM::VQSHLuv16i8: 10703 case ARM::VQSHLuv1i64: 10704 case ARM::VQSHLuv2i32: 10705 case ARM::VQSHLuv2i64: 10706 case ARM::VQSHLuv4i16: 10707 case ARM::VQSHLuv4i32: 10708 case ARM::VQSHLuv8i16: 10709 case ARM::VQSHLuv8i8: 10710 case ARM::VRSHLsv16i8: 10711 case ARM::VRSHLsv1i64: 10712 case ARM::VRSHLsv2i32: 10713 case ARM::VRSHLsv2i64: 10714 case ARM::VRSHLsv4i16: 10715 case ARM::VRSHLsv4i32: 10716 case ARM::VRSHLsv8i16: 10717 case ARM::VRSHLsv8i8: 10718 case ARM::VRSHLuv16i8: 10719 case ARM::VRSHLuv1i64: 10720 case ARM::VRSHLuv2i32: 10721 case ARM::VRSHLuv2i64: 10722 case ARM::VRSHLuv4i16: 10723 case ARM::VRSHLuv4i32: 10724 case ARM::VRSHLuv8i16: 10725 case ARM::VRSHLuv8i8: 10726 case ARM::VSHLsv16i8: 10727 case ARM::VSHLsv1i64: 10728 case ARM::VSHLsv2i32: 10729 case ARM::VSHLsv2i64: 10730 case ARM::VSHLsv4i16: 10731 case ARM::VSHLsv4i32: 10732 case ARM::VSHLsv8i16: 10733 case ARM::VSHLsv8i8: 10734 case ARM::VSHLuv16i8: 10735 case ARM::VSHLuv1i64: 10736 case ARM::VSHLuv2i32: 10737 case ARM::VSHLuv2i64: 10738 case ARM::VSHLuv4i16: 10739 case ARM::VSHLuv4i32: 10740 case ARM::VSHLuv8i16: 10741 case ARM::VSHLuv8i8: { 10742 // op: Vd 10743 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10744 Value |= (op & UINT64_C(16)) << 18; 10745 Value |= (op & UINT64_C(15)) << 12; 10746 // op: Vn 10747 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10748 Value |= (op & UINT64_C(15)) << 16; 10749 Value |= (op & UINT64_C(16)) << 3; 10750 // op: Vm 10751 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10752 Value |= (op & UINT64_C(16)) << 1; 10753 Value |= (op & UINT64_C(15)); 10754 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10755 break; 10756 } 10757 case ARM::VCMLAv2f32: 10758 case ARM::VCMLAv4f16: 10759 case ARM::VCMLAv4f32: 10760 case ARM::VCMLAv8f16: { 10761 // op: Vd 10762 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10763 Value |= (op & UINT64_C(16)) << 18; 10764 Value |= (op & UINT64_C(15)) << 12; 10765 // op: Vn 10766 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10767 Value |= (op & UINT64_C(15)) << 16; 10768 Value |= (op & UINT64_C(16)) << 3; 10769 // op: Vm 10770 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10771 Value |= (op & UINT64_C(16)) << 1; 10772 Value |= (op & UINT64_C(15)); 10773 // op: rot 10774 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10775 op &= UINT64_C(3); 10776 op <<= 23; 10777 Value |= op; 10778 break; 10779 } 10780 case ARM::VCMLAv2f32_indexed: 10781 case ARM::VCMLAv4f32_indexed: { 10782 // op: Vd 10783 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10784 Value |= (op & UINT64_C(16)) << 18; 10785 Value |= (op & UINT64_C(15)) << 12; 10786 // op: Vn 10787 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10788 Value |= (op & UINT64_C(15)) << 16; 10789 Value |= (op & UINT64_C(16)) << 3; 10790 // op: Vm 10791 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10792 Value |= (op & UINT64_C(16)) << 1; 10793 Value |= (op & UINT64_C(15)); 10794 // op: rot 10795 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10796 op &= UINT64_C(3); 10797 op <<= 20; 10798 Value |= op; 10799 break; 10800 } 10801 case ARM::SHA1C: 10802 case ARM::SHA1M: 10803 case ARM::SHA1P: 10804 case ARM::SHA1SU0: 10805 case ARM::SHA256H: 10806 case ARM::SHA256H2: 10807 case ARM::SHA256SU1: 10808 case ARM::VABALsv2i64: 10809 case ARM::VABALsv4i32: 10810 case ARM::VABALsv8i16: 10811 case ARM::VABALuv2i64: 10812 case ARM::VABALuv4i32: 10813 case ARM::VABALuv8i16: 10814 case ARM::VABAsv16i8: 10815 case ARM::VABAsv2i32: 10816 case ARM::VABAsv4i16: 10817 case ARM::VABAsv4i32: 10818 case ARM::VABAsv8i16: 10819 case ARM::VABAsv8i8: 10820 case ARM::VABAuv16i8: 10821 case ARM::VABAuv2i32: 10822 case ARM::VABAuv4i16: 10823 case ARM::VABAuv4i32: 10824 case ARM::VABAuv8i16: 10825 case ARM::VABAuv8i8: 10826 case ARM::VBIFd: 10827 case ARM::VBIFq: 10828 case ARM::VBITd: 10829 case ARM::VBITq: 10830 case ARM::VBSLd: 10831 case ARM::VBSLq: 10832 case ARM::VFMAfd: 10833 case ARM::VFMAfq: 10834 case ARM::VFMAhd: 10835 case ARM::VFMAhq: 10836 case ARM::VFMSfd: 10837 case ARM::VFMSfq: 10838 case ARM::VFMShd: 10839 case ARM::VFMShq: 10840 case ARM::VMLALsv2i64: 10841 case ARM::VMLALsv4i32: 10842 case ARM::VMLALsv8i16: 10843 case ARM::VMLALuv2i64: 10844 case ARM::VMLALuv4i32: 10845 case ARM::VMLALuv8i16: 10846 case ARM::VMLAfd: 10847 case ARM::VMLAfq: 10848 case ARM::VMLAhd: 10849 case ARM::VMLAhq: 10850 case ARM::VMLAv16i8: 10851 case ARM::VMLAv2i32: 10852 case ARM::VMLAv4i16: 10853 case ARM::VMLAv4i32: 10854 case ARM::VMLAv8i16: 10855 case ARM::VMLAv8i8: 10856 case ARM::VMLSLsv2i64: 10857 case ARM::VMLSLsv4i32: 10858 case ARM::VMLSLsv8i16: 10859 case ARM::VMLSLuv2i64: 10860 case ARM::VMLSLuv4i32: 10861 case ARM::VMLSLuv8i16: 10862 case ARM::VMLSfd: 10863 case ARM::VMLSfq: 10864 case ARM::VMLShd: 10865 case ARM::VMLShq: 10866 case ARM::VMLSv16i8: 10867 case ARM::VMLSv2i32: 10868 case ARM::VMLSv4i16: 10869 case ARM::VMLSv4i32: 10870 case ARM::VMLSv8i16: 10871 case ARM::VMLSv8i8: 10872 case ARM::VQDMLALv2i64: 10873 case ARM::VQDMLALv4i32: 10874 case ARM::VQDMLSLv2i64: 10875 case ARM::VQDMLSLv4i32: 10876 case ARM::VQRDMLAHv2i32: 10877 case ARM::VQRDMLAHv4i16: 10878 case ARM::VQRDMLAHv4i32: 10879 case ARM::VQRDMLAHv8i16: 10880 case ARM::VQRDMLSHv2i32: 10881 case ARM::VQRDMLSHv4i16: 10882 case ARM::VQRDMLSHv4i32: 10883 case ARM::VQRDMLSHv8i16: 10884 case ARM::VTBX1: 10885 case ARM::VTBX2: 10886 case ARM::VTBX3: 10887 case ARM::VTBX4: { 10888 // op: Vd 10889 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10890 Value |= (op & UINT64_C(16)) << 18; 10891 Value |= (op & UINT64_C(15)) << 12; 10892 // op: Vn 10893 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10894 Value |= (op & UINT64_C(15)) << 16; 10895 Value |= (op & UINT64_C(16)) << 3; 10896 // op: Vm 10897 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10898 Value |= (op & UINT64_C(16)) << 1; 10899 Value |= (op & UINT64_C(15)); 10900 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10901 break; 10902 } 10903 case ARM::VMLALslsv2i32: 10904 case ARM::VMLALsluv2i32: 10905 case ARM::VMLAslfd: 10906 case ARM::VMLAslfq: 10907 case ARM::VMLAslv2i32: 10908 case ARM::VMLAslv4i32: 10909 case ARM::VMLSLslsv2i32: 10910 case ARM::VMLSLsluv2i32: 10911 case ARM::VMLSslfd: 10912 case ARM::VMLSslfq: 10913 case ARM::VMLSslv2i32: 10914 case ARM::VMLSslv4i32: 10915 case ARM::VQDMLALslv2i32: 10916 case ARM::VQDMLSLslv2i32: 10917 case ARM::VQRDMLAHslv2i32: 10918 case ARM::VQRDMLAHslv4i32: 10919 case ARM::VQRDMLSHslv2i32: 10920 case ARM::VQRDMLSHslv4i32: { 10921 // op: Vd 10922 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10923 Value |= (op & UINT64_C(16)) << 18; 10924 Value |= (op & UINT64_C(15)) << 12; 10925 // op: Vn 10926 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10927 Value |= (op & UINT64_C(15)) << 16; 10928 Value |= (op & UINT64_C(16)) << 3; 10929 // op: Vm 10930 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10931 op &= UINT64_C(15); 10932 Value |= op; 10933 // op: lane 10934 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10935 op &= UINT64_C(1); 10936 op <<= 5; 10937 Value |= op; 10938 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 10939 break; 10940 } 10941 case ARM::VCMLAv4f16_indexed: 10942 case ARM::VCMLAv8f16_indexed: { 10943 // op: Vd 10944 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10945 Value |= (op & UINT64_C(16)) << 18; 10946 Value |= (op & UINT64_C(15)) << 12; 10947 // op: Vn 10948 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10949 Value |= (op & UINT64_C(15)) << 16; 10950 Value |= (op & UINT64_C(16)) << 3; 10951 // op: Vm 10952 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10953 op &= UINT64_C(15); 10954 Value |= op; 10955 // op: rot 10956 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10957 op &= UINT64_C(3); 10958 op <<= 20; 10959 Value |= op; 10960 // op: lane 10961 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10962 op &= UINT64_C(1); 10963 op <<= 5; 10964 Value |= op; 10965 break; 10966 } 10967 case ARM::VMLALslsv4i16: 10968 case ARM::VMLALsluv4i16: 10969 case ARM::VMLAslhd: 10970 case ARM::VMLAslhq: 10971 case ARM::VMLAslv4i16: 10972 case ARM::VMLAslv8i16: 10973 case ARM::VMLSLslsv4i16: 10974 case ARM::VMLSLsluv4i16: 10975 case ARM::VMLSslhd: 10976 case ARM::VMLSslhq: 10977 case ARM::VMLSslv4i16: 10978 case ARM::VMLSslv8i16: 10979 case ARM::VQDMLALslv4i16: 10980 case ARM::VQDMLSLslv4i16: 10981 case ARM::VQRDMLAHslv4i16: 10982 case ARM::VQRDMLAHslv8i16: 10983 case ARM::VQRDMLSHslv4i16: 10984 case ARM::VQRDMLSHslv8i16: { 10985 // op: Vd 10986 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10987 Value |= (op & UINT64_C(16)) << 18; 10988 Value |= (op & UINT64_C(15)) << 12; 10989 // op: Vn 10990 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10991 Value |= (op & UINT64_C(15)) << 16; 10992 Value |= (op & UINT64_C(16)) << 3; 10993 // op: Vm 10994 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10995 op &= UINT64_C(7); 10996 Value |= op; 10997 // op: lane 10998 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10999 Value |= (op & UINT64_C(2)) << 4; 11000 Value |= (op & UINT64_C(1)) << 3; 11001 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 11002 break; 11003 } 11004 case ARM::VSDOTD: 11005 case ARM::VSDOTQ: 11006 case ARM::VUDOTD: 11007 case ARM::VUDOTQ: { 11008 // op: Vd 11009 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11010 Value |= (op & UINT64_C(16)) << 18; 11011 Value |= (op & UINT64_C(15)) << 12; 11012 // op: Vn 11013 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11014 Value |= (op & UINT64_C(15)) << 16; 11015 Value |= (op & UINT64_C(16)) << 3; 11016 // op: Vm 11017 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11018 Value |= (op & UINT64_C(16)) << 1; 11019 Value |= (op & UINT64_C(15)); 11020 break; 11021 } 11022 case ARM::VSDOTDI: 11023 case ARM::VSDOTQI: 11024 case ARM::VUDOTDI: 11025 case ARM::VUDOTQI: { 11026 // op: Vd 11027 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11028 Value |= (op & UINT64_C(16)) << 18; 11029 Value |= (op & UINT64_C(15)) << 12; 11030 // op: Vn 11031 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11032 Value |= (op & UINT64_C(15)) << 16; 11033 Value |= (op & UINT64_C(16)) << 3; 11034 // op: Vm 11035 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11036 op &= UINT64_C(15); 11037 Value |= op; 11038 // op: lane 11039 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11040 op &= UINT64_C(1); 11041 op <<= 5; 11042 Value |= op; 11043 break; 11044 } 11045 case ARM::VST1LNd16: { 11046 // op: Vd 11047 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11048 Value |= (op & UINT64_C(16)) << 18; 11049 Value |= (op & UINT64_C(15)) << 12; 11050 // op: Rn 11051 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11052 Value |= (op & UINT64_C(15)) << 16; 11053 Value |= (op & UINT64_C(16)); 11054 // op: lane 11055 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11056 op &= UINT64_C(3); 11057 op <<= 6; 11058 Value |= op; 11059 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11060 break; 11061 } 11062 case ARM::VST2LNd32: 11063 case ARM::VST2LNq32: { 11064 // op: Vd 11065 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11066 Value |= (op & UINT64_C(16)) << 18; 11067 Value |= (op & UINT64_C(15)) << 12; 11068 // op: Rn 11069 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11070 Value |= (op & UINT64_C(15)) << 16; 11071 Value |= (op & UINT64_C(16)); 11072 // op: lane 11073 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11074 op &= UINT64_C(1); 11075 op <<= 7; 11076 Value |= op; 11077 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11078 break; 11079 } 11080 case ARM::VST2LNd16: 11081 case ARM::VST2LNq16: { 11082 // op: Vd 11083 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11084 Value |= (op & UINT64_C(16)) << 18; 11085 Value |= (op & UINT64_C(15)) << 12; 11086 // op: Rn 11087 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11088 Value |= (op & UINT64_C(15)) << 16; 11089 Value |= (op & UINT64_C(16)); 11090 // op: lane 11091 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11092 op &= UINT64_C(3); 11093 op <<= 6; 11094 Value |= op; 11095 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11096 break; 11097 } 11098 case ARM::VST2LNd8: { 11099 // op: Vd 11100 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11101 Value |= (op & UINT64_C(16)) << 18; 11102 Value |= (op & UINT64_C(15)) << 12; 11103 // op: Rn 11104 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11105 Value |= (op & UINT64_C(15)) << 16; 11106 Value |= (op & UINT64_C(16)); 11107 // op: lane 11108 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11109 op &= UINT64_C(7); 11110 op <<= 5; 11111 Value |= op; 11112 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11113 break; 11114 } 11115 case ARM::VST4LNd16: 11116 case ARM::VST4LNq16: { 11117 // op: Vd 11118 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11119 Value |= (op & UINT64_C(16)) << 18; 11120 Value |= (op & UINT64_C(15)) << 12; 11121 // op: Rn 11122 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11123 Value |= (op & UINT64_C(15)) << 16; 11124 Value |= (op & UINT64_C(16)); 11125 // op: lane 11126 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11127 op &= UINT64_C(3); 11128 op <<= 6; 11129 Value |= op; 11130 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11131 break; 11132 } 11133 case ARM::VST4LNd8: { 11134 // op: Vd 11135 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11136 Value |= (op & UINT64_C(16)) << 18; 11137 Value |= (op & UINT64_C(15)) << 12; 11138 // op: Rn 11139 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11140 Value |= (op & UINT64_C(15)) << 16; 11141 Value |= (op & UINT64_C(16)); 11142 // op: lane 11143 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11144 op &= UINT64_C(7); 11145 op <<= 5; 11146 Value |= op; 11147 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11148 break; 11149 } 11150 case ARM::VST1d16: 11151 case ARM::VST1d16T: 11152 case ARM::VST1d32: 11153 case ARM::VST1d32T: 11154 case ARM::VST1d64: 11155 case ARM::VST1d64T: 11156 case ARM::VST1d8: 11157 case ARM::VST1d8T: 11158 case ARM::VST3d16: 11159 case ARM::VST3d32: 11160 case ARM::VST3d8: 11161 case ARM::VST3q16: 11162 case ARM::VST3q32: 11163 case ARM::VST3q8: { 11164 // op: Vd 11165 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11166 Value |= (op & UINT64_C(16)) << 18; 11167 Value |= (op & UINT64_C(15)) << 12; 11168 // op: Rn 11169 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11170 Value |= (op & UINT64_C(15)) << 16; 11171 Value |= (op & UINT64_C(16)); 11172 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11173 break; 11174 } 11175 case ARM::VST4LNd32: 11176 case ARM::VST4LNq32: { 11177 // op: Vd 11178 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11179 Value |= (op & UINT64_C(16)) << 18; 11180 Value |= (op & UINT64_C(15)) << 12; 11181 // op: Rn 11182 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11183 Value |= (op & UINT64_C(15)) << 16; 11184 Value |= (op & UINT64_C(48)); 11185 // op: lane 11186 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11187 op &= UINT64_C(1); 11188 op <<= 7; 11189 Value |= op; 11190 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11191 break; 11192 } 11193 case ARM::VST1d16Q: 11194 case ARM::VST1d32Q: 11195 case ARM::VST1d64Q: 11196 case ARM::VST1d8Q: 11197 case ARM::VST1q16: 11198 case ARM::VST1q32: 11199 case ARM::VST1q64: 11200 case ARM::VST1q8: 11201 case ARM::VST2b16: 11202 case ARM::VST2b32: 11203 case ARM::VST2b8: 11204 case ARM::VST2d16: 11205 case ARM::VST2d32: 11206 case ARM::VST2d8: 11207 case ARM::VST2q16: 11208 case ARM::VST2q32: 11209 case ARM::VST2q8: 11210 case ARM::VST4d16: 11211 case ARM::VST4d32: 11212 case ARM::VST4d8: 11213 case ARM::VST4q16: 11214 case ARM::VST4q32: 11215 case ARM::VST4q8: { 11216 // op: Vd 11217 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11218 Value |= (op & UINT64_C(16)) << 18; 11219 Value |= (op & UINT64_C(15)) << 12; 11220 // op: Rn 11221 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11222 Value |= (op & UINT64_C(15)) << 16; 11223 Value |= (op & UINT64_C(48)); 11224 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11225 break; 11226 } 11227 case ARM::VST1LNd8: { 11228 // op: Vd 11229 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11230 Value |= (op & UINT64_C(16)) << 18; 11231 Value |= (op & UINT64_C(15)) << 12; 11232 // op: Rn 11233 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11234 op &= UINT64_C(15); 11235 op <<= 16; 11236 Value |= op; 11237 // op: lane 11238 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11239 op &= UINT64_C(7); 11240 op <<= 5; 11241 Value |= op; 11242 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11243 break; 11244 } 11245 case ARM::VST3LNd32: 11246 case ARM::VST3LNq32: { 11247 // op: Vd 11248 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11249 Value |= (op & UINT64_C(16)) << 18; 11250 Value |= (op & UINT64_C(15)) << 12; 11251 // op: Rn 11252 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11253 op &= UINT64_C(15); 11254 op <<= 16; 11255 Value |= op; 11256 // op: lane 11257 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11258 op &= UINT64_C(1); 11259 op <<= 7; 11260 Value |= op; 11261 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11262 break; 11263 } 11264 case ARM::VST3LNd16: 11265 case ARM::VST3LNq16: { 11266 // op: Vd 11267 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11268 Value |= (op & UINT64_C(16)) << 18; 11269 Value |= (op & UINT64_C(15)) << 12; 11270 // op: Rn 11271 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11272 op &= UINT64_C(15); 11273 op <<= 16; 11274 Value |= op; 11275 // op: lane 11276 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11277 op &= UINT64_C(3); 11278 op <<= 6; 11279 Value |= op; 11280 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11281 break; 11282 } 11283 case ARM::VST3LNd8: { 11284 // op: Vd 11285 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11286 Value |= (op & UINT64_C(16)) << 18; 11287 Value |= (op & UINT64_C(15)) << 12; 11288 // op: Rn 11289 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 11290 op &= UINT64_C(15); 11291 op <<= 16; 11292 Value |= op; 11293 // op: lane 11294 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11295 op &= UINT64_C(7); 11296 op <<= 5; 11297 Value |= op; 11298 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11299 break; 11300 } 11301 case ARM::VST1LNd32: { 11302 // op: Vd 11303 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11304 Value |= (op & UINT64_C(16)) << 18; 11305 Value |= (op & UINT64_C(15)) << 12; 11306 // op: Rn 11307 op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI); 11308 Value |= (op & UINT64_C(15)) << 16; 11309 Value |= (op & UINT64_C(48)); 11310 // op: lane 11311 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11312 op &= UINT64_C(1); 11313 op <<= 7; 11314 Value |= op; 11315 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11316 break; 11317 } 11318 case ARM::VST1d16wb_fixed: 11319 case ARM::VST1d32wb_fixed: 11320 case ARM::VST1d64wb_fixed: 11321 case ARM::VST1d8wb_fixed: { 11322 // op: Vd 11323 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11324 Value |= (op & UINT64_C(16)) << 18; 11325 Value |= (op & UINT64_C(15)) << 12; 11326 // op: Rn 11327 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11328 Value |= (op & UINT64_C(15)) << 16; 11329 Value |= (op & UINT64_C(16)); 11330 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11331 break; 11332 } 11333 case ARM::VST1d16Qwb_fixed: 11334 case ARM::VST1d16Twb_fixed: 11335 case ARM::VST1d32Qwb_fixed: 11336 case ARM::VST1d32Twb_fixed: 11337 case ARM::VST1d64Qwb_fixed: 11338 case ARM::VST1d64Twb_fixed: 11339 case ARM::VST1d8Qwb_fixed: 11340 case ARM::VST1d8Twb_fixed: 11341 case ARM::VST1q16wb_fixed: 11342 case ARM::VST1q32wb_fixed: 11343 case ARM::VST1q64wb_fixed: 11344 case ARM::VST1q8wb_fixed: 11345 case ARM::VST2b16wb_fixed: 11346 case ARM::VST2b32wb_fixed: 11347 case ARM::VST2b8wb_fixed: 11348 case ARM::VST2d16wb_fixed: 11349 case ARM::VST2d32wb_fixed: 11350 case ARM::VST2d8wb_fixed: 11351 case ARM::VST2q16wb_fixed: 11352 case ARM::VST2q32wb_fixed: 11353 case ARM::VST2q8wb_fixed: { 11354 // op: Vd 11355 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11356 Value |= (op & UINT64_C(16)) << 18; 11357 Value |= (op & UINT64_C(15)) << 12; 11358 // op: Rn 11359 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11360 Value |= (op & UINT64_C(15)) << 16; 11361 Value |= (op & UINT64_C(48)); 11362 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11363 break; 11364 } 11365 case ARM::VST1LNd16_UPD: { 11366 // op: Vd 11367 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11368 Value |= (op & UINT64_C(16)) << 18; 11369 Value |= (op & UINT64_C(15)) << 12; 11370 // op: Rn 11371 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11372 Value |= (op & UINT64_C(15)) << 16; 11373 Value |= (op & UINT64_C(16)); 11374 // op: Rm 11375 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11376 op &= UINT64_C(15); 11377 Value |= op; 11378 // op: lane 11379 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11380 op &= UINT64_C(3); 11381 op <<= 6; 11382 Value |= op; 11383 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11384 break; 11385 } 11386 case ARM::VST2LNd32_UPD: 11387 case ARM::VST2LNq32_UPD: { 11388 // op: Vd 11389 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11390 Value |= (op & UINT64_C(16)) << 18; 11391 Value |= (op & UINT64_C(15)) << 12; 11392 // op: Rn 11393 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11394 Value |= (op & UINT64_C(15)) << 16; 11395 Value |= (op & UINT64_C(16)); 11396 // op: Rm 11397 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11398 op &= UINT64_C(15); 11399 Value |= op; 11400 // op: lane 11401 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11402 op &= UINT64_C(1); 11403 op <<= 7; 11404 Value |= op; 11405 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11406 break; 11407 } 11408 case ARM::VST2LNd16_UPD: 11409 case ARM::VST2LNq16_UPD: { 11410 // op: Vd 11411 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11412 Value |= (op & UINT64_C(16)) << 18; 11413 Value |= (op & UINT64_C(15)) << 12; 11414 // op: Rn 11415 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11416 Value |= (op & UINT64_C(15)) << 16; 11417 Value |= (op & UINT64_C(16)); 11418 // op: Rm 11419 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11420 op &= UINT64_C(15); 11421 Value |= op; 11422 // op: lane 11423 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11424 op &= UINT64_C(3); 11425 op <<= 6; 11426 Value |= op; 11427 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11428 break; 11429 } 11430 case ARM::VST2LNd8_UPD: { 11431 // op: Vd 11432 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11433 Value |= (op & UINT64_C(16)) << 18; 11434 Value |= (op & UINT64_C(15)) << 12; 11435 // op: Rn 11436 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11437 Value |= (op & UINT64_C(15)) << 16; 11438 Value |= (op & UINT64_C(16)); 11439 // op: Rm 11440 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11441 op &= UINT64_C(15); 11442 Value |= op; 11443 // op: lane 11444 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 11445 op &= UINT64_C(7); 11446 op <<= 5; 11447 Value |= op; 11448 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11449 break; 11450 } 11451 case ARM::VST4LNd16_UPD: 11452 case ARM::VST4LNq16_UPD: { 11453 // op: Vd 11454 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11455 Value |= (op & UINT64_C(16)) << 18; 11456 Value |= (op & UINT64_C(15)) << 12; 11457 // op: Rn 11458 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11459 Value |= (op & UINT64_C(15)) << 16; 11460 Value |= (op & UINT64_C(16)); 11461 // op: Rm 11462 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11463 op &= UINT64_C(15); 11464 Value |= op; 11465 // op: lane 11466 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11467 op &= UINT64_C(3); 11468 op <<= 6; 11469 Value |= op; 11470 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11471 break; 11472 } 11473 case ARM::VST4LNd8_UPD: { 11474 // op: Vd 11475 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11476 Value |= (op & UINT64_C(16)) << 18; 11477 Value |= (op & UINT64_C(15)) << 12; 11478 // op: Rn 11479 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11480 Value |= (op & UINT64_C(15)) << 16; 11481 Value |= (op & UINT64_C(16)); 11482 // op: Rm 11483 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11484 op &= UINT64_C(15); 11485 Value |= op; 11486 // op: lane 11487 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11488 op &= UINT64_C(7); 11489 op <<= 5; 11490 Value |= op; 11491 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11492 break; 11493 } 11494 case ARM::VST3d16_UPD: 11495 case ARM::VST3d32_UPD: 11496 case ARM::VST3d8_UPD: 11497 case ARM::VST3q16_UPD: 11498 case ARM::VST3q32_UPD: 11499 case ARM::VST3q8_UPD: { 11500 // op: Vd 11501 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11502 Value |= (op & UINT64_C(16)) << 18; 11503 Value |= (op & UINT64_C(15)) << 12; 11504 // op: Rn 11505 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11506 Value |= (op & UINT64_C(15)) << 16; 11507 Value |= (op & UINT64_C(16)); 11508 // op: Rm 11509 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11510 op &= UINT64_C(15); 11511 Value |= op; 11512 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11513 break; 11514 } 11515 case ARM::VST1d16wb_register: 11516 case ARM::VST1d32wb_register: 11517 case ARM::VST1d64wb_register: 11518 case ARM::VST1d8wb_register: { 11519 // op: Vd 11520 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11521 Value |= (op & UINT64_C(16)) << 18; 11522 Value |= (op & UINT64_C(15)) << 12; 11523 // op: Rn 11524 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11525 Value |= (op & UINT64_C(15)) << 16; 11526 Value |= (op & UINT64_C(16)); 11527 // op: Rm 11528 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11529 op &= UINT64_C(15); 11530 Value |= op; 11531 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11532 break; 11533 } 11534 case ARM::VST4LNd32_UPD: 11535 case ARM::VST4LNq32_UPD: { 11536 // op: Vd 11537 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11538 Value |= (op & UINT64_C(16)) << 18; 11539 Value |= (op & UINT64_C(15)) << 12; 11540 // op: Rn 11541 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11542 Value |= (op & UINT64_C(15)) << 16; 11543 Value |= (op & UINT64_C(48)); 11544 // op: Rm 11545 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11546 op &= UINT64_C(15); 11547 Value |= op; 11548 // op: lane 11549 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 11550 op &= UINT64_C(1); 11551 op <<= 7; 11552 Value |= op; 11553 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11554 break; 11555 } 11556 case ARM::VST4d16_UPD: 11557 case ARM::VST4d32_UPD: 11558 case ARM::VST4d8_UPD: 11559 case ARM::VST4q16_UPD: 11560 case ARM::VST4q32_UPD: 11561 case ARM::VST4q8_UPD: { 11562 // op: Vd 11563 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11564 Value |= (op & UINT64_C(16)) << 18; 11565 Value |= (op & UINT64_C(15)) << 12; 11566 // op: Rn 11567 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11568 Value |= (op & UINT64_C(15)) << 16; 11569 Value |= (op & UINT64_C(48)); 11570 // op: Rm 11571 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11572 op &= UINT64_C(15); 11573 Value |= op; 11574 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11575 break; 11576 } 11577 case ARM::VST1d16Qwb_register: 11578 case ARM::VST1d16Twb_register: 11579 case ARM::VST1d32Qwb_register: 11580 case ARM::VST1d32Twb_register: 11581 case ARM::VST1d64Qwb_register: 11582 case ARM::VST1d64Twb_register: 11583 case ARM::VST1d8Qwb_register: 11584 case ARM::VST1d8Twb_register: 11585 case ARM::VST1q16wb_register: 11586 case ARM::VST1q32wb_register: 11587 case ARM::VST1q64wb_register: 11588 case ARM::VST1q8wb_register: 11589 case ARM::VST2b16wb_register: 11590 case ARM::VST2b32wb_register: 11591 case ARM::VST2b8wb_register: 11592 case ARM::VST2d16wb_register: 11593 case ARM::VST2d32wb_register: 11594 case ARM::VST2d8wb_register: 11595 case ARM::VST2q16wb_register: 11596 case ARM::VST2q32wb_register: 11597 case ARM::VST2q8wb_register: { 11598 // op: Vd 11599 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11600 Value |= (op & UINT64_C(16)) << 18; 11601 Value |= (op & UINT64_C(15)) << 12; 11602 // op: Rn 11603 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11604 Value |= (op & UINT64_C(15)) << 16; 11605 Value |= (op & UINT64_C(48)); 11606 // op: Rm 11607 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11608 op &= UINT64_C(15); 11609 Value |= op; 11610 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11611 break; 11612 } 11613 case ARM::VST1LNd8_UPD: { 11614 // op: Vd 11615 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11616 Value |= (op & UINT64_C(16)) << 18; 11617 Value |= (op & UINT64_C(15)) << 12; 11618 // op: Rn 11619 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11620 op &= UINT64_C(15); 11621 op <<= 16; 11622 Value |= op; 11623 // op: Rm 11624 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11625 op &= UINT64_C(15); 11626 Value |= op; 11627 // op: lane 11628 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11629 op &= UINT64_C(7); 11630 op <<= 5; 11631 Value |= op; 11632 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11633 break; 11634 } 11635 case ARM::VST3LNd32_UPD: 11636 case ARM::VST3LNq32_UPD: { 11637 // op: Vd 11638 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11639 Value |= (op & UINT64_C(16)) << 18; 11640 Value |= (op & UINT64_C(15)) << 12; 11641 // op: Rn 11642 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11643 op &= UINT64_C(15); 11644 op <<= 16; 11645 Value |= op; 11646 // op: Rm 11647 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11648 op &= UINT64_C(15); 11649 Value |= op; 11650 // op: lane 11651 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 11652 op &= UINT64_C(1); 11653 op <<= 7; 11654 Value |= op; 11655 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11656 break; 11657 } 11658 case ARM::VST3LNd16_UPD: 11659 case ARM::VST3LNq16_UPD: { 11660 // op: Vd 11661 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11662 Value |= (op & UINT64_C(16)) << 18; 11663 Value |= (op & UINT64_C(15)) << 12; 11664 // op: Rn 11665 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11666 op &= UINT64_C(15); 11667 op <<= 16; 11668 Value |= op; 11669 // op: Rm 11670 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11671 op &= UINT64_C(15); 11672 Value |= op; 11673 // op: lane 11674 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 11675 op &= UINT64_C(3); 11676 op <<= 6; 11677 Value |= op; 11678 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11679 break; 11680 } 11681 case ARM::VST3LNd8_UPD: { 11682 // op: Vd 11683 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11684 Value |= (op & UINT64_C(16)) << 18; 11685 Value |= (op & UINT64_C(15)) << 12; 11686 // op: Rn 11687 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 11688 op &= UINT64_C(15); 11689 op <<= 16; 11690 Value |= op; 11691 // op: Rm 11692 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11693 op &= UINT64_C(15); 11694 Value |= op; 11695 // op: lane 11696 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 11697 op &= UINT64_C(7); 11698 op <<= 5; 11699 Value |= op; 11700 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11701 break; 11702 } 11703 case ARM::VST1LNd32_UPD: { 11704 // op: Vd 11705 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 11706 Value |= (op & UINT64_C(16)) << 18; 11707 Value |= (op & UINT64_C(15)) << 12; 11708 // op: Rn 11709 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 11710 Value |= (op & UINT64_C(15)) << 16; 11711 Value |= (op & UINT64_C(48)); 11712 // op: Rm 11713 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 11714 op &= UINT64_C(15); 11715 Value |= op; 11716 // op: lane 11717 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 11718 op &= UINT64_C(1); 11719 op <<= 7; 11720 Value |= op; 11721 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 11722 break; 11723 } 11724 case ARM::LDC2L_OFFSET: 11725 case ARM::LDC2L_PRE: 11726 case ARM::LDC2_OFFSET: 11727 case ARM::LDC2_PRE: 11728 case ARM::STC2L_OFFSET: 11729 case ARM::STC2L_PRE: 11730 case ARM::STC2_OFFSET: 11731 case ARM::STC2_PRE: 11732 case ARM::t2LDC2L_OFFSET: 11733 case ARM::t2LDC2L_PRE: 11734 case ARM::t2LDC2_OFFSET: 11735 case ARM::t2LDC2_PRE: 11736 case ARM::t2LDCL_OFFSET: 11737 case ARM::t2LDCL_PRE: 11738 case ARM::t2LDC_OFFSET: 11739 case ARM::t2LDC_PRE: 11740 case ARM::t2STC2L_OFFSET: 11741 case ARM::t2STC2L_PRE: 11742 case ARM::t2STC2_OFFSET: 11743 case ARM::t2STC2_PRE: 11744 case ARM::t2STCL_OFFSET: 11745 case ARM::t2STCL_PRE: 11746 case ARM::t2STC_OFFSET: 11747 case ARM::t2STC_PRE: { 11748 // op: addr 11749 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 11750 Value |= (op & UINT64_C(256)) << 15; 11751 Value |= (op & UINT64_C(7680)) << 7; 11752 Value |= (op & UINT64_C(255)); 11753 // op: cop 11754 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11755 op &= UINT64_C(15); 11756 op <<= 8; 11757 Value |= op; 11758 // op: CRd 11759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11760 op &= UINT64_C(15); 11761 op <<= 12; 11762 Value |= op; 11763 break; 11764 } 11765 case ARM::t2PLDWi12: 11766 case ARM::t2PLDi12: 11767 case ARM::t2PLIi12: { 11768 // op: addr 11769 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 11770 Value |= (op & UINT64_C(122880)) << 3; 11771 Value |= (op & UINT64_C(4095)); 11772 break; 11773 } 11774 case ARM::PLDWi12: 11775 case ARM::PLDi12: 11776 case ARM::PLIi12: { 11777 // op: addr 11778 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 11779 Value |= (op & UINT64_C(4096)) << 11; 11780 Value |= (op & UINT64_C(122880)) << 3; 11781 Value |= (op & UINT64_C(4095)); 11782 break; 11783 } 11784 case ARM::t2PLDpci: 11785 case ARM::t2PLIpci: { 11786 // op: addr 11787 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 11788 Value |= (op & UINT64_C(4096)) << 11; 11789 Value |= (op & UINT64_C(4095)); 11790 break; 11791 } 11792 case ARM::t2LDAEXB: 11793 case ARM::t2LDAEXH: 11794 case ARM::t2LDREXB: 11795 case ARM::t2LDREXH: { 11796 // op: addr 11797 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11798 op &= UINT64_C(15); 11799 op <<= 16; 11800 Value |= op; 11801 // op: Rt 11802 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11803 op &= UINT64_C(15); 11804 op <<= 12; 11805 Value |= op; 11806 break; 11807 } 11808 case ARM::t2LDAEXD: 11809 case ARM::t2LDREXD: { 11810 // op: addr 11811 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11812 op &= UINT64_C(15); 11813 op <<= 16; 11814 Value |= op; 11815 // op: Rt 11816 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11817 op &= UINT64_C(15); 11818 op <<= 12; 11819 Value |= op; 11820 // op: Rt2 11821 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11822 op &= UINT64_C(15); 11823 op <<= 8; 11824 Value |= op; 11825 break; 11826 } 11827 case ARM::t2PLDWi8: 11828 case ARM::t2PLDi8: 11829 case ARM::t2PLIi8: { 11830 // op: addr 11831 op = getT2AddrModeImmOpValue<8,0>(MI, 0, Fixups, STI); 11832 Value |= (op & UINT64_C(7680)) << 7; 11833 Value |= (op & UINT64_C(255)); 11834 break; 11835 } 11836 case ARM::t2PLDWs: 11837 case ARM::t2PLDs: 11838 case ARM::t2PLIs: { 11839 // op: addr 11840 op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI); 11841 Value |= (op & UINT64_C(960)) << 10; 11842 Value |= (op & UINT64_C(3)) << 4; 11843 Value |= (op & UINT64_C(60)) >> 2; 11844 break; 11845 } 11846 case ARM::t2BFLr: 11847 case ARM::t2BFr: { 11848 // op: b_label 11849 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 11850 op &= UINT64_C(15); 11851 op <<= 23; 11852 Value |= op; 11853 // op: Rn 11854 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11855 op &= UINT64_C(15); 11856 op <<= 16; 11857 Value |= op; 11858 break; 11859 } 11860 case ARM::t2BFi: { 11861 // op: b_label 11862 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 11863 op &= UINT64_C(15); 11864 op <<= 23; 11865 Value |= op; 11866 // op: label 11867 op = getBFTargetOpValue<false, ARM::fixup_bf_target>(MI, 1, Fixups, STI); 11868 Value |= (op & UINT64_C(63488)) << 5; 11869 Value |= (op & UINT64_C(1)) << 11; 11870 Value |= (op & UINT64_C(2046)); 11871 break; 11872 } 11873 case ARM::t2BFLi: { 11874 // op: b_label 11875 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 11876 op &= UINT64_C(15); 11877 op <<= 23; 11878 Value |= op; 11879 // op: label 11880 op = getBFTargetOpValue<false, ARM::fixup_bfl_target>(MI, 1, Fixups, STI); 11881 Value |= (op & UINT64_C(260096)) << 5; 11882 Value |= (op & UINT64_C(1)) << 11; 11883 Value |= (op & UINT64_C(2046)); 11884 break; 11885 } 11886 case ARM::t2MSRbanked: { 11887 // op: banked 11888 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11889 Value |= (op & UINT64_C(32)) << 15; 11890 Value |= (op & UINT64_C(15)) << 8; 11891 Value |= (op & UINT64_C(16)); 11892 // op: Rn 11893 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11894 op &= UINT64_C(15); 11895 op <<= 16; 11896 Value |= op; 11897 break; 11898 } 11899 case ARM::t2MRSbanked: { 11900 // op: banked 11901 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 11902 Value |= (op & UINT64_C(32)) << 15; 11903 Value |= (op & UINT64_C(15)) << 16; 11904 Value |= (op & UINT64_C(16)); 11905 // op: Rd 11906 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11907 op &= UINT64_C(15); 11908 op <<= 8; 11909 Value |= op; 11910 break; 11911 } 11912 case ARM::t2BFic: { 11913 // op: bcond 11914 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 11915 op &= UINT64_C(15); 11916 op <<= 18; 11917 Value |= op; 11918 // op: label 11919 op = getBFTargetOpValue<false, ARM::fixup_bfc_target>(MI, 1, Fixups, STI); 11920 Value |= (op & UINT64_C(2048)) << 5; 11921 Value |= (op & UINT64_C(1)) << 11; 11922 Value |= (op & UINT64_C(2046)); 11923 // op: ba_label 11924 op = getBFAfterTargetOpValue(MI, 2, Fixups, STI); 11925 op &= UINT64_C(1); 11926 op <<= 17; 11927 Value |= op; 11928 // op: b_label 11929 op = getBFTargetOpValue<false, ARM::fixup_bf_branch>(MI, 0, Fixups, STI); 11930 op &= UINT64_C(15); 11931 op <<= 23; 11932 Value |= op; 11933 break; 11934 } 11935 case ARM::t2IT: { 11936 // op: cc 11937 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11938 op &= UINT64_C(15); 11939 op <<= 4; 11940 Value |= op; 11941 // op: mask 11942 op = getITMaskOpValue(MI, 1, Fixups, STI); 11943 op &= UINT64_C(15); 11944 Value |= op; 11945 break; 11946 } 11947 case ARM::BX: { 11948 // op: dst 11949 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11950 op &= UINT64_C(15); 11951 Value |= op; 11952 break; 11953 } 11954 case ARM::tPICADD: { 11955 // op: dst 11956 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11957 op &= UINT64_C(7); 11958 Value |= op; 11959 break; 11960 } 11961 case ARM::tADDrSPi: { 11962 // op: dst 11963 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11964 op &= UINT64_C(7); 11965 op <<= 8; 11966 Value |= op; 11967 // op: imm 11968 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 11969 op &= UINT64_C(255); 11970 Value |= op; 11971 break; 11972 } 11973 case ARM::tSETEND: { 11974 // op: end 11975 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11976 op &= UINT64_C(1); 11977 op <<= 3; 11978 Value |= op; 11979 break; 11980 } 11981 case ARM::SETEND: { 11982 // op: end 11983 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11984 op &= UINT64_C(1); 11985 op <<= 9; 11986 Value |= op; 11987 break; 11988 } 11989 case ARM::MVE_VPTv16s8r: 11990 case ARM::MVE_VPTv4s32r: 11991 case ARM::MVE_VPTv8s16r: { 11992 // op: fc 11993 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 11994 Value |= (op & UINT64_C(1)) << 7; 11995 Value |= (op & UINT64_C(2)) << 4; 11996 // op: Mk 11997 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 11998 Value |= (op & UINT64_C(8)) << 19; 11999 Value |= (op & UINT64_C(7)) << 13; 12000 // op: Qn 12001 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12002 op &= UINT64_C(7); 12003 op <<= 17; 12004 Value |= op; 12005 // op: Rm 12006 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12007 op &= UINT64_C(15); 12008 Value |= op; 12009 break; 12010 } 12011 case ARM::MVE_VCMPs16r: 12012 case ARM::MVE_VCMPs32r: 12013 case ARM::MVE_VCMPs8r: { 12014 // op: fc 12015 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12016 Value |= (op & UINT64_C(1)) << 7; 12017 Value |= (op & UINT64_C(2)) << 4; 12018 // op: Qn 12019 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12020 op &= UINT64_C(7); 12021 op <<= 17; 12022 Value |= op; 12023 // op: Rm 12024 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12025 op &= UINT64_C(15); 12026 Value |= op; 12027 break; 12028 } 12029 case ARM::MVE_VPTv16s8: 12030 case ARM::MVE_VPTv4s32: 12031 case ARM::MVE_VPTv8s16: { 12032 // op: fc 12033 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12034 Value |= (op & UINT64_C(1)) << 7; 12035 Value |= (op & UINT64_C(2)) >> 1; 12036 // op: Mk 12037 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12038 Value |= (op & UINT64_C(8)) << 19; 12039 Value |= (op & UINT64_C(7)) << 13; 12040 // op: Qn 12041 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12042 op &= UINT64_C(7); 12043 op <<= 17; 12044 Value |= op; 12045 // op: Qm 12046 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12047 Value |= (op & UINT64_C(8)) << 2; 12048 Value |= (op & UINT64_C(7)) << 1; 12049 break; 12050 } 12051 case ARM::MVE_VCMPs16: 12052 case ARM::MVE_VCMPs32: 12053 case ARM::MVE_VCMPs8: { 12054 // op: fc 12055 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12056 Value |= (op & UINT64_C(1)) << 7; 12057 Value |= (op & UINT64_C(2)) >> 1; 12058 // op: Qn 12059 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12060 op &= UINT64_C(7); 12061 op <<= 17; 12062 Value |= op; 12063 // op: Qm 12064 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12065 Value |= (op & UINT64_C(8)) << 2; 12066 Value |= (op & UINT64_C(7)) << 1; 12067 break; 12068 } 12069 case ARM::MVE_VPTv4f32r: 12070 case ARM::MVE_VPTv8f16r: { 12071 // op: fc 12072 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12073 Value |= (op & UINT64_C(4)) << 10; 12074 Value |= (op & UINT64_C(1)) << 7; 12075 Value |= (op & UINT64_C(2)) << 4; 12076 // op: Mk 12077 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12078 Value |= (op & UINT64_C(8)) << 19; 12079 Value |= (op & UINT64_C(7)) << 13; 12080 // op: Qn 12081 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12082 op &= UINT64_C(7); 12083 op <<= 17; 12084 Value |= op; 12085 // op: Rm 12086 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12087 op &= UINT64_C(15); 12088 Value |= op; 12089 break; 12090 } 12091 case ARM::MVE_VCMPf16r: 12092 case ARM::MVE_VCMPf32r: { 12093 // op: fc 12094 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12095 Value |= (op & UINT64_C(4)) << 10; 12096 Value |= (op & UINT64_C(1)) << 7; 12097 Value |= (op & UINT64_C(2)) << 4; 12098 // op: Qn 12099 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12100 op &= UINT64_C(7); 12101 op <<= 17; 12102 Value |= op; 12103 // op: Rm 12104 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12105 op &= UINT64_C(15); 12106 Value |= op; 12107 break; 12108 } 12109 case ARM::MVE_VPTv4f32: 12110 case ARM::MVE_VPTv8f16: { 12111 // op: fc 12112 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12113 Value |= (op & UINT64_C(4)) << 10; 12114 Value |= (op & UINT64_C(1)) << 7; 12115 Value |= (op & UINT64_C(2)) >> 1; 12116 // op: Mk 12117 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12118 Value |= (op & UINT64_C(8)) << 19; 12119 Value |= (op & UINT64_C(7)) << 13; 12120 // op: Qn 12121 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12122 op &= UINT64_C(7); 12123 op <<= 17; 12124 Value |= op; 12125 // op: Qm 12126 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12127 Value |= (op & UINT64_C(8)) << 2; 12128 Value |= (op & UINT64_C(7)) << 1; 12129 break; 12130 } 12131 case ARM::MVE_VCMPf16: 12132 case ARM::MVE_VCMPf32: { 12133 // op: fc 12134 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12135 Value |= (op & UINT64_C(4)) << 10; 12136 Value |= (op & UINT64_C(1)) << 7; 12137 Value |= (op & UINT64_C(2)) >> 1; 12138 // op: Qn 12139 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12140 op &= UINT64_C(7); 12141 op <<= 17; 12142 Value |= op; 12143 // op: Qm 12144 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12145 Value |= (op & UINT64_C(8)) << 2; 12146 Value |= (op & UINT64_C(7)) << 1; 12147 break; 12148 } 12149 case ARM::MVE_VPTv16i8: 12150 case ARM::MVE_VPTv16u8: 12151 case ARM::MVE_VPTv4i32: 12152 case ARM::MVE_VPTv4u32: 12153 case ARM::MVE_VPTv8i16: 12154 case ARM::MVE_VPTv8u16: { 12155 // op: fc 12156 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12157 op &= UINT64_C(1); 12158 op <<= 7; 12159 Value |= op; 12160 // op: Mk 12161 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12162 Value |= (op & UINT64_C(8)) << 19; 12163 Value |= (op & UINT64_C(7)) << 13; 12164 // op: Qn 12165 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12166 op &= UINT64_C(7); 12167 op <<= 17; 12168 Value |= op; 12169 // op: Qm 12170 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12171 Value |= (op & UINT64_C(8)) << 2; 12172 Value |= (op & UINT64_C(7)) << 1; 12173 break; 12174 } 12175 case ARM::MVE_VPTv16i8r: 12176 case ARM::MVE_VPTv16u8r: 12177 case ARM::MVE_VPTv4i32r: 12178 case ARM::MVE_VPTv4u32r: 12179 case ARM::MVE_VPTv8i16r: 12180 case ARM::MVE_VPTv8u16r: { 12181 // op: fc 12182 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12183 op &= UINT64_C(1); 12184 op <<= 7; 12185 Value |= op; 12186 // op: Mk 12187 op = getVPTMaskOpValue(MI, 0, Fixups, STI); 12188 Value |= (op & UINT64_C(8)) << 19; 12189 Value |= (op & UINT64_C(7)) << 13; 12190 // op: Qn 12191 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12192 op &= UINT64_C(7); 12193 op <<= 17; 12194 Value |= op; 12195 // op: Rm 12196 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12197 op &= UINT64_C(15); 12198 Value |= op; 12199 break; 12200 } 12201 case ARM::MVE_VCMPi16: 12202 case ARM::MVE_VCMPi32: 12203 case ARM::MVE_VCMPi8: 12204 case ARM::MVE_VCMPu16: 12205 case ARM::MVE_VCMPu32: 12206 case ARM::MVE_VCMPu8: { 12207 // op: fc 12208 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12209 op &= UINT64_C(1); 12210 op <<= 7; 12211 Value |= op; 12212 // op: Qn 12213 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12214 op &= UINT64_C(7); 12215 op <<= 17; 12216 Value |= op; 12217 // op: Qm 12218 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12219 Value |= (op & UINT64_C(8)) << 2; 12220 Value |= (op & UINT64_C(7)) << 1; 12221 break; 12222 } 12223 case ARM::MVE_VCMPi16r: 12224 case ARM::MVE_VCMPi32r: 12225 case ARM::MVE_VCMPi8r: 12226 case ARM::MVE_VCMPu16r: 12227 case ARM::MVE_VCMPu32r: 12228 case ARM::MVE_VCMPu8r: { 12229 // op: fc 12230 op = getRestrictedCondCodeOpValue(MI, 3, Fixups, STI); 12231 op &= UINT64_C(1); 12232 op <<= 7; 12233 Value |= op; 12234 // op: Qn 12235 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12236 op &= UINT64_C(7); 12237 op <<= 17; 12238 Value |= op; 12239 // op: Rm 12240 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12241 op &= UINT64_C(15); 12242 Value |= op; 12243 break; 12244 } 12245 case ARM::BL: { 12246 // op: func 12247 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 12248 op &= UINT64_C(16777215); 12249 Value |= op; 12250 break; 12251 } 12252 case ARM::BLX: { 12253 // op: func 12254 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12255 op &= UINT64_C(15); 12256 Value |= op; 12257 break; 12258 } 12259 case ARM::t2BXJ: { 12260 // op: func 12261 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12262 op &= UINT64_C(15); 12263 op <<= 16; 12264 Value |= op; 12265 break; 12266 } 12267 case ARM::tBLXNSr: 12268 case ARM::tBLXr: { 12269 // op: func 12270 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12271 op &= UINT64_C(15); 12272 op <<= 3; 12273 Value |= op; 12274 break; 12275 } 12276 case ARM::tBL: { 12277 // op: func 12278 op = getThumbBLTargetOpValue(MI, 2, Fixups, STI); 12279 Value |= (op & UINT64_C(8388608)) << 3; 12280 Value |= (op & UINT64_C(2095104)) << 5; 12281 Value |= (op & UINT64_C(4194304)) >> 9; 12282 Value |= (op & UINT64_C(2097152)) >> 10; 12283 Value |= (op & UINT64_C(2047)); 12284 break; 12285 } 12286 case ARM::tBLXi: { 12287 // op: func 12288 op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI); 12289 Value |= (op & UINT64_C(8388608)) << 3; 12290 Value |= (op & UINT64_C(2095104)) << 5; 12291 Value |= (op & UINT64_C(4194304)) >> 9; 12292 Value |= (op & UINT64_C(2097152)) >> 10; 12293 Value |= (op & UINT64_C(2046)); 12294 break; 12295 } 12296 case ARM::MVE_VBICIZ0v4i32: 12297 case ARM::MVE_VBICIZ0v8i16: 12298 case ARM::MVE_VORRIZ0v4i32: 12299 case ARM::MVE_VORRIZ0v8i16: { 12300 // op: imm 12301 op = getExpandedImmOpValue<0,false>(MI, 2, Fixups, STI); 12302 Value |= (op & UINT64_C(128)) << 21; 12303 Value |= (op & UINT64_C(112)) << 12; 12304 Value |= (op & UINT64_C(15)); 12305 // op: Qd 12306 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12307 Value |= (op & UINT64_C(8)) << 19; 12308 Value |= (op & UINT64_C(7)) << 13; 12309 break; 12310 } 12311 case ARM::MVE_VBICIZ16v4i32: 12312 case ARM::MVE_VORRIZ16v4i32: { 12313 // op: imm 12314 op = getExpandedImmOpValue<16,false>(MI, 2, Fixups, STI); 12315 Value |= (op & UINT64_C(128)) << 21; 12316 Value |= (op & UINT64_C(112)) << 12; 12317 Value |= (op & UINT64_C(15)); 12318 // op: Qd 12319 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12320 Value |= (op & UINT64_C(8)) << 19; 12321 Value |= (op & UINT64_C(7)) << 13; 12322 break; 12323 } 12324 case ARM::MVE_VBICIZ24v4i32: 12325 case ARM::MVE_VORRIZ24v4i32: { 12326 // op: imm 12327 op = getExpandedImmOpValue<24,false>(MI, 2, Fixups, STI); 12328 Value |= (op & UINT64_C(128)) << 21; 12329 Value |= (op & UINT64_C(112)) << 12; 12330 Value |= (op & UINT64_C(15)); 12331 // op: Qd 12332 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12333 Value |= (op & UINT64_C(8)) << 19; 12334 Value |= (op & UINT64_C(7)) << 13; 12335 break; 12336 } 12337 case ARM::MVE_VBICIZ8v4i32: 12338 case ARM::MVE_VBICIZ8v8i16: 12339 case ARM::MVE_VORRIZ8v4i32: 12340 case ARM::MVE_VORRIZ8v8i16: { 12341 // op: imm 12342 op = getExpandedImmOpValue<8,false>(MI, 2, Fixups, STI); 12343 Value |= (op & UINT64_C(128)) << 21; 12344 Value |= (op & UINT64_C(112)) << 12; 12345 Value |= (op & UINT64_C(15)); 12346 // op: Qd 12347 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12348 Value |= (op & UINT64_C(8)) << 19; 12349 Value |= (op & UINT64_C(7)) << 13; 12350 break; 12351 } 12352 case ARM::HVC: { 12353 // op: imm 12354 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12355 Value |= (op & UINT64_C(65520)) << 4; 12356 Value |= (op & UINT64_C(15)); 12357 break; 12358 } 12359 case ARM::t2SETPAN: { 12360 // op: imm 12361 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12362 op &= UINT64_C(1); 12363 op <<= 3; 12364 Value |= op; 12365 break; 12366 } 12367 case ARM::SETPAN: { 12368 // op: imm 12369 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12370 op &= UINT64_C(1); 12371 op <<= 9; 12372 Value |= op; 12373 break; 12374 } 12375 case ARM::tHINT: { 12376 // op: imm 12377 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12378 op &= UINT64_C(15); 12379 op <<= 4; 12380 Value |= op; 12381 break; 12382 } 12383 case ARM::t2HINT: 12384 case ARM::t2SUBS_PC_LR: 12385 case ARM::tSVC: { 12386 // op: imm 12387 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12388 op &= UINT64_C(255); 12389 Value |= op; 12390 break; 12391 } 12392 case ARM::MVE_VMOVimmf32: 12393 case ARM::MVE_VMOVimmi64: 12394 case ARM::MVE_VMOVimmi8: { 12395 // op: imm 12396 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12397 Value |= (op & UINT64_C(128)) << 21; 12398 Value |= (op & UINT64_C(112)) << 12; 12399 Value |= (op & UINT64_C(15)); 12400 // op: Qd 12401 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12402 Value |= (op & UINT64_C(8)) << 19; 12403 Value |= (op & UINT64_C(7)) << 13; 12404 break; 12405 } 12406 case ARM::MVE_VMOVimmi32: 12407 case ARM::MVE_VMVNimmi32: { 12408 // op: imm 12409 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12410 Value |= (op & UINT64_C(128)) << 21; 12411 Value |= (op & UINT64_C(112)) << 12; 12412 Value |= (op & UINT64_C(3840)); 12413 Value |= (op & UINT64_C(15)); 12414 // op: Qd 12415 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12416 Value |= (op & UINT64_C(8)) << 19; 12417 Value |= (op & UINT64_C(7)) << 13; 12418 break; 12419 } 12420 case ARM::MVE_VMOVimmi16: 12421 case ARM::MVE_VMVNimmi16: { 12422 // op: imm 12423 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12424 Value |= (op & UINT64_C(128)) << 21; 12425 Value |= (op & UINT64_C(112)) << 12; 12426 Value |= (op & UINT64_C(512)); 12427 Value |= (op & UINT64_C(15)); 12428 // op: Qd 12429 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12430 Value |= (op & UINT64_C(8)) << 19; 12431 Value |= (op & UINT64_C(7)) << 13; 12432 break; 12433 } 12434 case ARM::t2ADDspImm12: 12435 case ARM::t2SUBspImm12: { 12436 // op: imm 12437 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12438 Value |= (op & UINT64_C(2048)) << 15; 12439 Value |= (op & UINT64_C(1792)) << 4; 12440 Value |= (op & UINT64_C(255)); 12441 break; 12442 } 12443 case ARM::tADDspi: 12444 case ARM::tSUBspi: { 12445 // op: imm 12446 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12447 op &= UINT64_C(127); 12448 Value |= op; 12449 break; 12450 } 12451 case ARM::MVE_VSHLC: { 12452 // op: imm 12453 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12454 op &= UINT64_C(31); 12455 op <<= 16; 12456 Value |= op; 12457 // op: Qd 12458 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12459 Value |= (op & UINT64_C(8)) << 19; 12460 Value |= (op & UINT64_C(7)) << 13; 12461 // op: RdmDest 12462 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12463 op &= UINT64_C(15); 12464 Value |= op; 12465 break; 12466 } 12467 case ARM::t2HVC: 12468 case ARM::t2UDF: { 12469 // op: imm16 12470 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12471 Value |= (op & UINT64_C(61440)) << 4; 12472 Value |= (op & UINT64_C(4095)); 12473 break; 12474 } 12475 case ARM::UDF: { 12476 // op: imm16 12477 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12478 Value |= (op & UINT64_C(65520)) << 4; 12479 Value |= (op & UINT64_C(15)); 12480 break; 12481 } 12482 case ARM::tUDF: { 12483 // op: imm8 12484 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12485 op &= UINT64_C(255); 12486 Value |= op; 12487 break; 12488 } 12489 case ARM::tCPS: { 12490 // op: imod 12491 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12492 op &= UINT64_C(1); 12493 op <<= 4; 12494 Value |= op; 12495 // op: iflags 12496 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12497 op &= UINT64_C(7); 12498 Value |= op; 12499 break; 12500 } 12501 case ARM::CPS2p: { 12502 // op: imod 12503 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12504 op &= UINT64_C(3); 12505 op <<= 18; 12506 Value |= op; 12507 // op: iflags 12508 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12509 op &= UINT64_C(7); 12510 op <<= 6; 12511 Value |= op; 12512 break; 12513 } 12514 case ARM::CPS3p: { 12515 // op: imod 12516 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12517 op &= UINT64_C(3); 12518 op <<= 18; 12519 Value |= op; 12520 // op: iflags 12521 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12522 op &= UINT64_C(7); 12523 op <<= 6; 12524 Value |= op; 12525 // op: mode 12526 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12527 op &= UINT64_C(31); 12528 Value |= op; 12529 break; 12530 } 12531 case ARM::t2CPS2p: { 12532 // op: imod 12533 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12534 op &= UINT64_C(3); 12535 op <<= 9; 12536 Value |= op; 12537 // op: iflags 12538 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12539 op &= UINT64_C(7); 12540 op <<= 5; 12541 Value |= op; 12542 break; 12543 } 12544 case ARM::t2CPS3p: { 12545 // op: imod 12546 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12547 op &= UINT64_C(3); 12548 op <<= 9; 12549 Value |= op; 12550 // op: iflags 12551 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12552 op &= UINT64_C(7); 12553 op <<= 5; 12554 Value |= op; 12555 // op: mode 12556 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12557 op &= UINT64_C(31); 12558 Value |= op; 12559 break; 12560 } 12561 case ARM::t2LE: { 12562 // op: label 12563 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 0, Fixups, STI); 12564 Value |= (op & UINT64_C(1)) << 11; 12565 Value |= (op & UINT64_C(2046)); 12566 break; 12567 } 12568 case ARM::MVE_LETP: 12569 case ARM::t2LEUpdate: { 12570 // op: label 12571 op = getBFTargetOpValue<true, ARM::fixup_le>(MI, 2, Fixups, STI); 12572 Value |= (op & UINT64_C(1)) << 11; 12573 Value |= (op & UINT64_C(2046)); 12574 break; 12575 } 12576 case ARM::t2MSR_AR: { 12577 // op: mask 12578 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12579 Value |= (op & UINT64_C(16)) << 16; 12580 Value |= (op & UINT64_C(15)) << 8; 12581 // op: Rn 12582 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12583 op &= UINT64_C(15); 12584 op <<= 16; 12585 Value |= op; 12586 break; 12587 } 12588 case ARM::CPS1p: 12589 case ARM::SRSDA: 12590 case ARM::SRSDA_UPD: 12591 case ARM::SRSDB: 12592 case ARM::SRSDB_UPD: 12593 case ARM::SRSIA: 12594 case ARM::SRSIA_UPD: 12595 case ARM::SRSIB: 12596 case ARM::SRSIB_UPD: 12597 case ARM::t2CPS1p: 12598 case ARM::t2SRSDB: 12599 case ARM::t2SRSDB_UPD: 12600 case ARM::t2SRSIA: 12601 case ARM::t2SRSIA_UPD: { 12602 // op: mode 12603 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12604 op &= UINT64_C(31); 12605 Value |= op; 12606 break; 12607 } 12608 case ARM::LDC2L_POST: 12609 case ARM::LDC2_POST: 12610 case ARM::STC2L_POST: 12611 case ARM::STC2_POST: 12612 case ARM::t2LDC2L_POST: 12613 case ARM::t2LDC2_POST: 12614 case ARM::t2LDCL_POST: 12615 case ARM::t2LDC_POST: 12616 case ARM::t2STC2L_POST: 12617 case ARM::t2STC2_POST: 12618 case ARM::t2STCL_POST: 12619 case ARM::t2STC_POST: { 12620 // op: offset 12621 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12622 Value |= (op & UINT64_C(256)) << 15; 12623 Value |= (op & UINT64_C(255)); 12624 // op: addr 12625 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12626 op &= UINT64_C(15); 12627 op <<= 16; 12628 Value |= op; 12629 // op: cop 12630 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12631 op &= UINT64_C(15); 12632 op <<= 8; 12633 Value |= op; 12634 // op: CRd 12635 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12636 op &= UINT64_C(15); 12637 op <<= 12; 12638 Value |= op; 12639 break; 12640 } 12641 case ARM::CDP2: 12642 case ARM::t2CDP: 12643 case ARM::t2CDP2: { 12644 // op: opc1 12645 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12646 op &= UINT64_C(15); 12647 op <<= 20; 12648 Value |= op; 12649 // op: CRn 12650 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12651 op &= UINT64_C(15); 12652 op <<= 16; 12653 Value |= op; 12654 // op: CRd 12655 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12656 op &= UINT64_C(15); 12657 op <<= 12; 12658 Value |= op; 12659 // op: cop 12660 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12661 op &= UINT64_C(15); 12662 op <<= 8; 12663 Value |= op; 12664 // op: opc2 12665 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 12666 op &= UINT64_C(7); 12667 op <<= 5; 12668 Value |= op; 12669 // op: CRm 12670 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 12671 op &= UINT64_C(15); 12672 Value |= op; 12673 break; 12674 } 12675 case ARM::DMB: 12676 case ARM::DSB: 12677 case ARM::ISB: 12678 case ARM::t2DBG: 12679 case ARM::t2DMB: 12680 case ARM::t2DSB: 12681 case ARM::t2ISB: { 12682 // op: opt 12683 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12684 op &= UINT64_C(15); 12685 Value |= op; 12686 break; 12687 } 12688 case ARM::t2SMC: { 12689 // op: opt 12690 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12691 op &= UINT64_C(15); 12692 op <<= 16; 12693 Value |= op; 12694 break; 12695 } 12696 case ARM::LDC2L_OPTION: 12697 case ARM::LDC2_OPTION: 12698 case ARM::STC2L_OPTION: 12699 case ARM::STC2_OPTION: 12700 case ARM::t2LDC2L_OPTION: 12701 case ARM::t2LDC2_OPTION: 12702 case ARM::t2LDCL_OPTION: 12703 case ARM::t2LDC_OPTION: 12704 case ARM::t2STC2L_OPTION: 12705 case ARM::t2STC2_OPTION: 12706 case ARM::t2STCL_OPTION: 12707 case ARM::t2STC_OPTION: { 12708 // op: option 12709 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 12710 op &= UINT64_C(255); 12711 Value |= op; 12712 // op: addr 12713 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 12714 op &= UINT64_C(15); 12715 op <<= 16; 12716 Value |= op; 12717 // op: cop 12718 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12719 op &= UINT64_C(15); 12720 op <<= 8; 12721 Value |= op; 12722 // op: CRd 12723 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12724 op &= UINT64_C(15); 12725 op <<= 12; 12726 Value |= op; 12727 break; 12728 } 12729 case ARM::BX_RET: 12730 case ARM::ERET: 12731 case ARM::MOVPCLR: { 12732 // op: p 12733 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12734 op &= UINT64_C(15); 12735 op <<= 28; 12736 Value |= op; 12737 break; 12738 } 12739 case ARM::FMSTAT: { 12740 // op: p 12741 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12742 op &= UINT64_C(15); 12743 op <<= 28; 12744 Value |= op; 12745 Value = VFPThumb2PostEncoder(MI, Value, STI); 12746 break; 12747 } 12748 case ARM::t2Bcc: { 12749 // op: p 12750 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12751 op &= UINT64_C(15); 12752 op <<= 22; 12753 Value |= op; 12754 // op: target 12755 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 12756 Value |= (op & UINT64_C(1048576)) << 6; 12757 Value |= (op & UINT64_C(258048)) << 4; 12758 Value |= (op & UINT64_C(262144)) >> 5; 12759 Value |= (op & UINT64_C(524288)) >> 8; 12760 Value |= (op & UINT64_C(4094)) >> 1; 12761 break; 12762 } 12763 case ARM::VCMPEZD: 12764 case ARM::VCMPZD: { 12765 // op: p 12766 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12767 op &= UINT64_C(15); 12768 op <<= 28; 12769 Value |= op; 12770 // op: Dd 12771 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12772 Value |= (op & UINT64_C(16)) << 18; 12773 Value |= (op & UINT64_C(15)) << 12; 12774 Value = VFPThumb2PostEncoder(MI, Value, STI); 12775 break; 12776 } 12777 case ARM::MRS: 12778 case ARM::MRSsys: { 12779 // op: p 12780 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12781 op &= UINT64_C(15); 12782 op <<= 28; 12783 Value |= op; 12784 // op: Rd 12785 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12786 op &= UINT64_C(15); 12787 op <<= 12; 12788 Value |= op; 12789 break; 12790 } 12791 case ARM::VLDMSIA: 12792 case ARM::VSTMSIA: { 12793 // op: p 12794 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12795 op &= UINT64_C(15); 12796 op <<= 28; 12797 Value |= op; 12798 // op: Rn 12799 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12800 op &= UINT64_C(15); 12801 op <<= 16; 12802 Value |= op; 12803 // op: regs 12804 op = getRegisterListOpValue(MI, 3, Fixups, STI); 12805 Value |= (op & UINT64_C(256)) << 14; 12806 Value |= (op & UINT64_C(7680)) << 3; 12807 Value |= (op & UINT64_C(255)); 12808 Value = VFPThumb2PostEncoder(MI, Value, STI); 12809 break; 12810 } 12811 case ARM::FLDMXIA: 12812 case ARM::FSTMXIA: { 12813 // op: p 12814 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12815 op &= UINT64_C(15); 12816 op <<= 28; 12817 Value |= op; 12818 // op: Rn 12819 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12820 op &= UINT64_C(15); 12821 op <<= 16; 12822 Value |= op; 12823 // op: regs 12824 op = getRegisterListOpValue(MI, 3, Fixups, STI); 12825 Value |= (op & UINT64_C(3840)) << 4; 12826 Value |= (op & UINT64_C(254)); 12827 Value = VFPThumb2PostEncoder(MI, Value, STI); 12828 break; 12829 } 12830 case ARM::VLDMDIA: 12831 case ARM::VSTMDIA: { 12832 // op: p 12833 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12834 op &= UINT64_C(15); 12835 op <<= 28; 12836 Value |= op; 12837 // op: Rn 12838 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12839 op &= UINT64_C(15); 12840 op <<= 16; 12841 Value |= op; 12842 // op: regs 12843 op = getRegisterListOpValue(MI, 3, Fixups, STI); 12844 Value |= (op & UINT64_C(4096)) << 10; 12845 Value |= (op & UINT64_C(3840)) << 4; 12846 Value |= (op & UINT64_C(254)); 12847 Value = VFPThumb2PostEncoder(MI, Value, STI); 12848 break; 12849 } 12850 case ARM::VLLDM: 12851 case ARM::VLSTM: { 12852 // op: p 12853 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12854 op &= UINT64_C(15); 12855 op <<= 28; 12856 Value |= op; 12857 // op: Rn 12858 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12859 op &= UINT64_C(15); 12860 op <<= 16; 12861 Value |= op; 12862 Value = VFPThumb2PostEncoder(MI, Value, STI); 12863 break; 12864 } 12865 case ARM::VMRS: 12866 case ARM::VMRS_FPCXTNS: 12867 case ARM::VMRS_FPCXTS: 12868 case ARM::VMRS_FPEXC: 12869 case ARM::VMRS_FPINST: 12870 case ARM::VMRS_FPINST2: 12871 case ARM::VMRS_FPSID: 12872 case ARM::VMRS_MVFR0: 12873 case ARM::VMRS_MVFR1: 12874 case ARM::VMRS_MVFR2: 12875 case ARM::VMRS_VPR: 12876 case ARM::VMSR: 12877 case ARM::VMSR_FPCXTNS: 12878 case ARM::VMSR_FPCXTS: 12879 case ARM::VMSR_FPEXC: 12880 case ARM::VMSR_FPINST: 12881 case ARM::VMSR_FPINST2: 12882 case ARM::VMSR_FPSID: 12883 case ARM::VMSR_VPR: { 12884 // op: p 12885 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12886 op &= UINT64_C(15); 12887 op <<= 28; 12888 Value |= op; 12889 // op: Rt 12890 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12891 op &= UINT64_C(15); 12892 op <<= 12; 12893 Value |= op; 12894 Value = VFPThumb2PostEncoder(MI, Value, STI); 12895 break; 12896 } 12897 case ARM::VCMPEZH: 12898 case ARM::VCMPEZS: 12899 case ARM::VCMPZH: 12900 case ARM::VCMPZS: { 12901 // op: p 12902 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12903 op &= UINT64_C(15); 12904 op <<= 28; 12905 Value |= op; 12906 // op: Sd 12907 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12908 Value |= (op & UINT64_C(1)) << 22; 12909 Value |= (op & UINT64_C(30)) << 11; 12910 Value = VFPThumb2PostEncoder(MI, Value, STI); 12911 break; 12912 } 12913 case ARM::BX_pred: { 12914 // op: p 12915 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12916 op &= UINT64_C(15); 12917 op <<= 28; 12918 Value |= op; 12919 // op: dst 12920 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12921 op &= UINT64_C(15); 12922 Value |= op; 12923 break; 12924 } 12925 case ARM::BL_pred: { 12926 // op: p 12927 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12928 op &= UINT64_C(15); 12929 op <<= 28; 12930 Value |= op; 12931 // op: func 12932 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 12933 op &= UINT64_C(16777215); 12934 Value |= op; 12935 break; 12936 } 12937 case ARM::BLX_pred: 12938 case ARM::BXJ: { 12939 // op: p 12940 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12941 op &= UINT64_C(15); 12942 op <<= 28; 12943 Value |= op; 12944 // op: func 12945 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12946 op &= UINT64_C(15); 12947 Value |= op; 12948 break; 12949 } 12950 case ARM::HINT: { 12951 // op: p 12952 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12953 op &= UINT64_C(15); 12954 op <<= 28; 12955 Value |= op; 12956 // op: imm 12957 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12958 op &= UINT64_C(255); 12959 Value |= op; 12960 break; 12961 } 12962 case ARM::DBG: 12963 case ARM::SMC: { 12964 // op: p 12965 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12966 op &= UINT64_C(15); 12967 op <<= 28; 12968 Value |= op; 12969 // op: opt 12970 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 12971 op &= UINT64_C(15); 12972 Value |= op; 12973 break; 12974 } 12975 case ARM::LDMDA: 12976 case ARM::LDMDB: 12977 case ARM::LDMIA: 12978 case ARM::LDMIB: 12979 case ARM::STMDA: 12980 case ARM::STMDB: 12981 case ARM::STMIA: 12982 case ARM::STMIB: 12983 case ARM::sysLDMDA: 12984 case ARM::sysLDMDB: 12985 case ARM::sysLDMIA: 12986 case ARM::sysLDMIB: 12987 case ARM::sysSTMDA: 12988 case ARM::sysSTMDB: 12989 case ARM::sysSTMIA: 12990 case ARM::sysSTMIB: { 12991 // op: p 12992 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 12993 op &= UINT64_C(15); 12994 op <<= 28; 12995 Value |= op; 12996 // op: regs 12997 op = getRegisterListOpValue(MI, 3, Fixups, STI); 12998 op &= UINT64_C(65535); 12999 Value |= op; 13000 // op: Rn 13001 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13002 op &= UINT64_C(15); 13003 op <<= 16; 13004 Value |= op; 13005 break; 13006 } 13007 case ARM::SVC: { 13008 // op: p 13009 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13010 op &= UINT64_C(15); 13011 op <<= 28; 13012 Value |= op; 13013 // op: svc 13014 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13015 op &= UINT64_C(16777215); 13016 Value |= op; 13017 break; 13018 } 13019 case ARM::Bcc: { 13020 // op: p 13021 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13022 op &= UINT64_C(15); 13023 op <<= 28; 13024 Value |= op; 13025 // op: target 13026 op = getARMBranchTargetOpValue(MI, 0, Fixups, STI); 13027 op &= UINT64_C(16777215); 13028 Value |= op; 13029 break; 13030 } 13031 case ARM::tBcc: { 13032 // op: p 13033 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13034 op &= UINT64_C(15); 13035 op <<= 8; 13036 Value |= op; 13037 // op: target 13038 op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI); 13039 op &= UINT64_C(255); 13040 Value |= op; 13041 break; 13042 } 13043 case ARM::VABSD: 13044 case ARM::VCMPD: 13045 case ARM::VCMPED: 13046 case ARM::VMOVD: 13047 case ARM::VNEGD: 13048 case ARM::VRINTRD: 13049 case ARM::VRINTXD: 13050 case ARM::VRINTZD: 13051 case ARM::VSQRTD: { 13052 // op: p 13053 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13054 op &= UINT64_C(15); 13055 op <<= 28; 13056 Value |= op; 13057 // op: Dd 13058 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13059 Value |= (op & UINT64_C(16)) << 18; 13060 Value |= (op & UINT64_C(15)) << 12; 13061 // op: Dm 13062 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13063 Value |= (op & UINT64_C(16)) << 1; 13064 Value |= (op & UINT64_C(15)); 13065 Value = VFPThumb2PostEncoder(MI, Value, STI); 13066 break; 13067 } 13068 case ARM::VCVTBHD: 13069 case ARM::VCVTTHD: 13070 case ARM::VSITOD: 13071 case ARM::VUITOD: { 13072 // op: p 13073 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13074 op &= UINT64_C(15); 13075 op <<= 28; 13076 Value |= op; 13077 // op: Dd 13078 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13079 Value |= (op & UINT64_C(16)) << 18; 13080 Value |= (op & UINT64_C(15)) << 12; 13081 // op: Sm 13082 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13083 Value |= (op & UINT64_C(1)) << 5; 13084 Value |= (op & UINT64_C(30)) >> 1; 13085 Value = VFPThumb2PostEncoder(MI, Value, STI); 13086 break; 13087 } 13088 case ARM::FCONSTD: { 13089 // op: p 13090 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13091 op &= UINT64_C(15); 13092 op <<= 28; 13093 Value |= op; 13094 // op: Dd 13095 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13096 Value |= (op & UINT64_C(16)) << 18; 13097 Value |= (op & UINT64_C(15)) << 12; 13098 // op: imm 13099 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13100 Value |= (op & UINT64_C(240)) << 12; 13101 Value |= (op & UINT64_C(15)); 13102 Value = VFPThumb2PostEncoder(MI, Value, STI); 13103 break; 13104 } 13105 case ARM::VCVTBDH: 13106 case ARM::VCVTTDH: { 13107 // op: p 13108 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13109 op &= UINT64_C(15); 13110 op <<= 28; 13111 Value |= op; 13112 // op: Dm 13113 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13114 Value |= (op & UINT64_C(16)) << 1; 13115 Value |= (op & UINT64_C(15)); 13116 // op: Sd 13117 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13118 Value |= (op & UINT64_C(1)) << 22; 13119 Value |= (op & UINT64_C(30)) << 11; 13120 Value = VFPThumb2PostEncoder(MI, Value, STI); 13121 break; 13122 } 13123 case ARM::CLZ: 13124 case ARM::RBIT: 13125 case ARM::REV: 13126 case ARM::REV16: 13127 case ARM::REVSH: { 13128 // op: p 13129 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13130 op &= UINT64_C(15); 13131 op <<= 28; 13132 Value |= op; 13133 // op: Rd 13134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13135 op &= UINT64_C(15); 13136 op <<= 12; 13137 Value |= op; 13138 // op: Rm 13139 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13140 op &= UINT64_C(15); 13141 Value |= op; 13142 break; 13143 } 13144 case ARM::MOVi16: { 13145 // op: p 13146 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13147 op &= UINT64_C(15); 13148 op <<= 28; 13149 Value |= op; 13150 // op: Rd 13151 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13152 op &= UINT64_C(15); 13153 op <<= 12; 13154 Value |= op; 13155 // op: imm 13156 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 13157 Value |= (op & UINT64_C(61440)) << 4; 13158 Value |= (op & UINT64_C(4095)); 13159 break; 13160 } 13161 case ARM::ADR: { 13162 // op: p 13163 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13164 op &= UINT64_C(15); 13165 op <<= 28; 13166 Value |= op; 13167 // op: Rd 13168 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13169 op &= UINT64_C(15); 13170 op <<= 12; 13171 Value |= op; 13172 // op: label 13173 op = getAdrLabelOpValue(MI, 1, Fixups, STI); 13174 Value |= (op & UINT64_C(12288)) << 10; 13175 Value |= (op & UINT64_C(4095)); 13176 break; 13177 } 13178 case ARM::CMNzrr: 13179 case ARM::CMPrr: 13180 case ARM::TEQrr: 13181 case ARM::TSTrr: { 13182 // op: p 13183 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13184 op &= UINT64_C(15); 13185 op <<= 28; 13186 Value |= op; 13187 // op: Rn 13188 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13189 op &= UINT64_C(15); 13190 op <<= 16; 13191 Value |= op; 13192 // op: Rm 13193 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13194 op &= UINT64_C(15); 13195 Value |= op; 13196 break; 13197 } 13198 case ARM::CMNri: 13199 case ARM::CMPri: 13200 case ARM::TEQri: 13201 case ARM::TSTri: { 13202 // op: p 13203 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13204 op &= UINT64_C(15); 13205 op <<= 28; 13206 Value |= op; 13207 // op: Rn 13208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13209 op &= UINT64_C(15); 13210 op <<= 16; 13211 Value |= op; 13212 // op: imm 13213 op = getModImmOpValue(MI, 1, Fixups, STI); 13214 op &= UINT64_C(4095); 13215 Value |= op; 13216 break; 13217 } 13218 case ARM::VLDMSDB_UPD: 13219 case ARM::VLDMSIA_UPD: 13220 case ARM::VSTMSDB_UPD: 13221 case ARM::VSTMSIA_UPD: { 13222 // op: p 13223 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13224 op &= UINT64_C(15); 13225 op <<= 28; 13226 Value |= op; 13227 // op: Rn 13228 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13229 op &= UINT64_C(15); 13230 op <<= 16; 13231 Value |= op; 13232 // op: regs 13233 op = getRegisterListOpValue(MI, 4, Fixups, STI); 13234 Value |= (op & UINT64_C(256)) << 14; 13235 Value |= (op & UINT64_C(7680)) << 3; 13236 Value |= (op & UINT64_C(255)); 13237 Value = VFPThumb2PostEncoder(MI, Value, STI); 13238 break; 13239 } 13240 case ARM::FLDMXDB_UPD: 13241 case ARM::FLDMXIA_UPD: 13242 case ARM::FSTMXDB_UPD: 13243 case ARM::FSTMXIA_UPD: { 13244 // op: p 13245 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13246 op &= UINT64_C(15); 13247 op <<= 28; 13248 Value |= op; 13249 // op: Rn 13250 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13251 op &= UINT64_C(15); 13252 op <<= 16; 13253 Value |= op; 13254 // op: regs 13255 op = getRegisterListOpValue(MI, 4, Fixups, STI); 13256 Value |= (op & UINT64_C(3840)) << 4; 13257 Value |= (op & UINT64_C(254)); 13258 Value = VFPThumb2PostEncoder(MI, Value, STI); 13259 break; 13260 } 13261 case ARM::VLDMDDB_UPD: 13262 case ARM::VLDMDIA_UPD: 13263 case ARM::VSTMDDB_UPD: 13264 case ARM::VSTMDIA_UPD: { 13265 // op: p 13266 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13267 op &= UINT64_C(15); 13268 op <<= 28; 13269 Value |= op; 13270 // op: Rn 13271 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13272 op &= UINT64_C(15); 13273 op <<= 16; 13274 Value |= op; 13275 // op: regs 13276 op = getRegisterListOpValue(MI, 4, Fixups, STI); 13277 Value |= (op & UINT64_C(4096)) << 10; 13278 Value |= (op & UINT64_C(3840)) << 4; 13279 Value |= (op & UINT64_C(254)); 13280 Value = VFPThumb2PostEncoder(MI, Value, STI); 13281 break; 13282 } 13283 case ARM::STL: 13284 case ARM::STLB: 13285 case ARM::STLH: { 13286 // op: p 13287 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13288 op &= UINT64_C(15); 13289 op <<= 28; 13290 Value |= op; 13291 // op: Rt 13292 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13293 op &= UINT64_C(15); 13294 Value |= op; 13295 // op: addr 13296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13297 op &= UINT64_C(15); 13298 op <<= 16; 13299 Value |= op; 13300 break; 13301 } 13302 case ARM::VMOVRH: 13303 case ARM::VMOVRS: { 13304 // op: p 13305 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13306 op &= UINT64_C(15); 13307 op <<= 28; 13308 Value |= op; 13309 // op: Rt 13310 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13311 op &= UINT64_C(15); 13312 op <<= 12; 13313 Value |= op; 13314 // op: Sn 13315 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13316 Value |= (op & UINT64_C(30)) << 15; 13317 Value |= (op & UINT64_C(1)) << 7; 13318 Value = VFPThumb2PostEncoder(MI, Value, STI); 13319 break; 13320 } 13321 case ARM::LDA: 13322 case ARM::LDAB: 13323 case ARM::LDAEX: 13324 case ARM::LDAEXB: 13325 case ARM::LDAEXD: 13326 case ARM::LDAEXH: 13327 case ARM::LDAH: 13328 case ARM::LDREX: 13329 case ARM::LDREXB: 13330 case ARM::LDREXD: 13331 case ARM::LDREXH: { 13332 // op: p 13333 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13334 op &= UINT64_C(15); 13335 op <<= 28; 13336 Value |= op; 13337 // op: Rt 13338 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13339 op &= UINT64_C(15); 13340 op <<= 12; 13341 Value |= op; 13342 // op: addr 13343 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13344 op &= UINT64_C(15); 13345 op <<= 16; 13346 Value |= op; 13347 break; 13348 } 13349 case ARM::VMRS_FPSCR_NZCVQC: 13350 case ARM::VMRS_P0: { 13351 // op: p 13352 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13353 op &= UINT64_C(15); 13354 op <<= 28; 13355 Value |= op; 13356 // op: Rt 13357 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13358 op &= UINT64_C(15); 13359 op <<= 12; 13360 Value |= op; 13361 Value = VFPThumb2PostEncoder(MI, Value, STI); 13362 break; 13363 } 13364 case ARM::VMSR_FPSCR_NZCVQC: 13365 case ARM::VMSR_P0: { 13366 // op: p 13367 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13368 op &= UINT64_C(15); 13369 op <<= 28; 13370 Value |= op; 13371 // op: Rt 13372 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13373 op &= UINT64_C(15); 13374 op <<= 12; 13375 Value |= op; 13376 Value = VFPThumb2PostEncoder(MI, Value, STI); 13377 break; 13378 } 13379 case ARM::VCVTSD: 13380 case ARM::VJCVT: 13381 case ARM::VTOSIRD: 13382 case ARM::VTOSIZD: 13383 case ARM::VTOUIRD: 13384 case ARM::VTOUIZD: { 13385 // op: p 13386 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13387 op &= UINT64_C(15); 13388 op <<= 28; 13389 Value |= op; 13390 // op: Sd 13391 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13392 Value |= (op & UINT64_C(1)) << 22; 13393 Value |= (op & UINT64_C(30)) << 11; 13394 // op: Dm 13395 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13396 Value |= (op & UINT64_C(16)) << 1; 13397 Value |= (op & UINT64_C(15)); 13398 Value = VFPThumb2PostEncoder(MI, Value, STI); 13399 break; 13400 } 13401 case ARM::VABSH: 13402 case ARM::VABSS: 13403 case ARM::VCMPEH: 13404 case ARM::VCMPES: 13405 case ARM::VCMPH: 13406 case ARM::VCMPS: 13407 case ARM::VCVTBHS: 13408 case ARM::VCVTBSH: 13409 case ARM::VCVTTHS: 13410 case ARM::VCVTTSH: 13411 case ARM::VMOVS: 13412 case ARM::VNEGH: 13413 case ARM::VNEGS: 13414 case ARM::VRINTRH: 13415 case ARM::VRINTRS: 13416 case ARM::VRINTXH: 13417 case ARM::VRINTXS: 13418 case ARM::VRINTZH: 13419 case ARM::VRINTZS: 13420 case ARM::VSITOH: 13421 case ARM::VSITOS: 13422 case ARM::VSQRTH: 13423 case ARM::VSQRTS: 13424 case ARM::VTOSIRH: 13425 case ARM::VTOSIRS: 13426 case ARM::VTOSIZH: 13427 case ARM::VTOSIZS: 13428 case ARM::VTOUIRH: 13429 case ARM::VTOUIRS: 13430 case ARM::VTOUIZH: 13431 case ARM::VTOUIZS: 13432 case ARM::VUITOH: 13433 case ARM::VUITOS: { 13434 // op: p 13435 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13436 op &= UINT64_C(15); 13437 op <<= 28; 13438 Value |= op; 13439 // op: Sd 13440 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13441 Value |= (op & UINT64_C(1)) << 22; 13442 Value |= (op & UINT64_C(30)) << 11; 13443 // op: Sm 13444 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13445 Value |= (op & UINT64_C(1)) << 5; 13446 Value |= (op & UINT64_C(30)) >> 1; 13447 Value = VFPThumb2PostEncoder(MI, Value, STI); 13448 break; 13449 } 13450 case ARM::FCONSTH: 13451 case ARM::FCONSTS: { 13452 // op: p 13453 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13454 op &= UINT64_C(15); 13455 op <<= 28; 13456 Value |= op; 13457 // op: Sd 13458 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13459 Value |= (op & UINT64_C(1)) << 22; 13460 Value |= (op & UINT64_C(30)) << 11; 13461 // op: imm 13462 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13463 Value |= (op & UINT64_C(240)) << 12; 13464 Value |= (op & UINT64_C(15)); 13465 Value = VFPThumb2PostEncoder(MI, Value, STI); 13466 break; 13467 } 13468 case ARM::VCVTDS: { 13469 // op: p 13470 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13471 op &= UINT64_C(15); 13472 op <<= 28; 13473 Value |= op; 13474 // op: Sm 13475 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13476 Value |= (op & UINT64_C(1)) << 5; 13477 Value |= (op & UINT64_C(30)) >> 1; 13478 // op: Dd 13479 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13480 Value |= (op & UINT64_C(16)) << 18; 13481 Value |= (op & UINT64_C(15)) << 12; 13482 Value = VFPThumb2PostEncoder(MI, Value, STI); 13483 break; 13484 } 13485 case ARM::VMOVHR: 13486 case ARM::VMOVSR: { 13487 // op: p 13488 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13489 op &= UINT64_C(15); 13490 op <<= 28; 13491 Value |= op; 13492 // op: Sn 13493 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13494 Value |= (op & UINT64_C(30)) << 15; 13495 Value |= (op & UINT64_C(1)) << 7; 13496 // op: Rt 13497 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13498 op &= UINT64_C(15); 13499 op <<= 12; 13500 Value |= op; 13501 Value = VFPThumb2PostEncoder(MI, Value, STI); 13502 break; 13503 } 13504 case ARM::VLDR_FPCXTNS_off: 13505 case ARM::VLDR_FPCXTS_off: 13506 case ARM::VLDR_FPSCR_NZCVQC_off: 13507 case ARM::VLDR_FPSCR_off: 13508 case ARM::VLDR_VPR_off: 13509 case ARM::VSTR_FPCXTNS_off: 13510 case ARM::VSTR_FPCXTS_off: 13511 case ARM::VSTR_FPSCR_NZCVQC_off: 13512 case ARM::VSTR_FPSCR_off: 13513 case ARM::VSTR_VPR_off: { 13514 // op: p 13515 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13516 op &= UINT64_C(15); 13517 op <<= 28; 13518 Value |= op; 13519 // op: addr 13520 op = getT2AddrModeImm7s4OpValue(MI, 0, Fixups, STI); 13521 Value |= (op & UINT64_C(128)) << 16; 13522 Value |= (op & UINT64_C(3840)) << 8; 13523 Value |= (op & UINT64_C(127)); 13524 Value = VFPThumb2PostEncoder(MI, Value, STI); 13525 break; 13526 } 13527 case ARM::MSRbanked: { 13528 // op: p 13529 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13530 op &= UINT64_C(15); 13531 op <<= 28; 13532 Value |= op; 13533 // op: banked 13534 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13535 Value |= (op & UINT64_C(32)) << 17; 13536 Value |= (op & UINT64_C(15)) << 16; 13537 Value |= (op & UINT64_C(16)) << 4; 13538 // op: Rn 13539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13540 op &= UINT64_C(15); 13541 Value |= op; 13542 break; 13543 } 13544 case ARM::MRSbanked: { 13545 // op: p 13546 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13547 op &= UINT64_C(15); 13548 op <<= 28; 13549 Value |= op; 13550 // op: banked 13551 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13552 Value |= (op & UINT64_C(32)) << 17; 13553 Value |= (op & UINT64_C(15)) << 16; 13554 Value |= (op & UINT64_C(16)) << 4; 13555 // op: Rd 13556 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13557 op &= UINT64_C(15); 13558 op <<= 12; 13559 Value |= op; 13560 break; 13561 } 13562 case ARM::MSR: { 13563 // op: p 13564 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13565 op &= UINT64_C(15); 13566 op <<= 28; 13567 Value |= op; 13568 // op: mask 13569 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13570 Value |= (op & UINT64_C(16)) << 18; 13571 Value |= (op & UINT64_C(15)) << 16; 13572 // op: Rn 13573 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13574 op &= UINT64_C(15); 13575 Value |= op; 13576 break; 13577 } 13578 case ARM::MSRi: { 13579 // op: p 13580 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13581 op &= UINT64_C(15); 13582 op <<= 28; 13583 Value |= op; 13584 // op: mask 13585 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13586 Value |= (op & UINT64_C(16)) << 18; 13587 Value |= (op & UINT64_C(15)) << 16; 13588 // op: imm 13589 op = getModImmOpValue(MI, 1, Fixups, STI); 13590 op &= UINT64_C(4095); 13591 Value |= op; 13592 break; 13593 } 13594 case ARM::LDMDA_UPD: 13595 case ARM::LDMDB_UPD: 13596 case ARM::LDMIA_UPD: 13597 case ARM::LDMIB_UPD: 13598 case ARM::STMDA_UPD: 13599 case ARM::STMDB_UPD: 13600 case ARM::STMIA_UPD: 13601 case ARM::STMIB_UPD: 13602 case ARM::sysLDMDA_UPD: 13603 case ARM::sysLDMDB_UPD: 13604 case ARM::sysLDMIA_UPD: 13605 case ARM::sysLDMIB_UPD: 13606 case ARM::sysSTMDA_UPD: 13607 case ARM::sysSTMDB_UPD: 13608 case ARM::sysSTMIA_UPD: 13609 case ARM::sysSTMIB_UPD: { 13610 // op: p 13611 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13612 op &= UINT64_C(15); 13613 op <<= 28; 13614 Value |= op; 13615 // op: regs 13616 op = getRegisterListOpValue(MI, 4, Fixups, STI); 13617 op &= UINT64_C(65535); 13618 Value |= op; 13619 // op: Rn 13620 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13621 op &= UINT64_C(15); 13622 op <<= 16; 13623 Value |= op; 13624 break; 13625 } 13626 case ARM::MOVr: 13627 case ARM::MOVr_TC: 13628 case ARM::MVNr: { 13629 // op: p 13630 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13631 op &= UINT64_C(15); 13632 op <<= 28; 13633 Value |= op; 13634 // op: s 13635 op = getCCOutOpValue(MI, 4, Fixups, STI); 13636 op &= UINT64_C(1); 13637 op <<= 20; 13638 Value |= op; 13639 // op: Rd 13640 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13641 op &= UINT64_C(15); 13642 op <<= 12; 13643 Value |= op; 13644 // op: Rm 13645 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13646 op &= UINT64_C(15); 13647 Value |= op; 13648 break; 13649 } 13650 case ARM::MOVi: 13651 case ARM::MVNi: { 13652 // op: p 13653 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13654 op &= UINT64_C(15); 13655 op <<= 28; 13656 Value |= op; 13657 // op: s 13658 op = getCCOutOpValue(MI, 4, Fixups, STI); 13659 op &= UINT64_C(1); 13660 op <<= 20; 13661 Value |= op; 13662 // op: Rd 13663 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13664 op &= UINT64_C(15); 13665 op <<= 12; 13666 Value |= op; 13667 // op: imm 13668 op = getModImmOpValue(MI, 1, Fixups, STI); 13669 op &= UINT64_C(4095); 13670 Value |= op; 13671 break; 13672 } 13673 case ARM::VADDD: 13674 case ARM::VDIVD: 13675 case ARM::VMULD: 13676 case ARM::VNMULD: 13677 case ARM::VSUBD: { 13678 // op: p 13679 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13680 op &= UINT64_C(15); 13681 op <<= 28; 13682 Value |= op; 13683 // op: Dd 13684 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13685 Value |= (op & UINT64_C(16)) << 18; 13686 Value |= (op & UINT64_C(15)) << 12; 13687 // op: Dn 13688 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13689 Value |= (op & UINT64_C(15)) << 16; 13690 Value |= (op & UINT64_C(16)) << 3; 13691 // op: Dm 13692 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13693 Value |= (op & UINT64_C(16)) << 1; 13694 Value |= (op & UINT64_C(15)); 13695 Value = VFPThumb2PostEncoder(MI, Value, STI); 13696 break; 13697 } 13698 case ARM::VLDRD: 13699 case ARM::VSTRD: { 13700 // op: p 13701 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13702 op &= UINT64_C(15); 13703 op <<= 28; 13704 Value |= op; 13705 // op: Dd 13706 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13707 Value |= (op & UINT64_C(16)) << 18; 13708 Value |= (op & UINT64_C(15)) << 12; 13709 // op: addr 13710 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 13711 Value |= (op & UINT64_C(256)) << 15; 13712 Value |= (op & UINT64_C(7680)) << 7; 13713 Value |= (op & UINT64_C(255)); 13714 Value = VFPThumb2PostEncoder(MI, Value, STI); 13715 break; 13716 } 13717 case ARM::VMOVDRR: { 13718 // op: p 13719 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13720 op &= UINT64_C(15); 13721 op <<= 28; 13722 Value |= op; 13723 // op: Dm 13724 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13725 Value |= (op & UINT64_C(16)) << 1; 13726 Value |= (op & UINT64_C(15)); 13727 // op: Rt 13728 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13729 op &= UINT64_C(15); 13730 op <<= 12; 13731 Value |= op; 13732 // op: Rt2 13733 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13734 op &= UINT64_C(15); 13735 op <<= 16; 13736 Value |= op; 13737 Value = VFPThumb2PostEncoder(MI, Value, STI); 13738 break; 13739 } 13740 case ARM::VMOVRRD: { 13741 // op: p 13742 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13743 op &= UINT64_C(15); 13744 op <<= 28; 13745 Value |= op; 13746 // op: Dm 13747 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13748 Value |= (op & UINT64_C(16)) << 1; 13749 Value |= (op & UINT64_C(15)); 13750 // op: Rt 13751 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13752 op &= UINT64_C(15); 13753 op <<= 12; 13754 Value |= op; 13755 // op: Rt2 13756 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13757 op &= UINT64_C(15); 13758 op <<= 16; 13759 Value |= op; 13760 Value = VFPThumb2PostEncoder(MI, Value, STI); 13761 break; 13762 } 13763 case ARM::SXTB: 13764 case ARM::SXTB16: 13765 case ARM::SXTH: 13766 case ARM::UXTB: 13767 case ARM::UXTB16: 13768 case ARM::UXTH: { 13769 // op: p 13770 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13771 op &= UINT64_C(15); 13772 op <<= 28; 13773 Value |= op; 13774 // op: Rd 13775 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13776 op &= UINT64_C(15); 13777 op <<= 12; 13778 Value |= op; 13779 // op: Rm 13780 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13781 op &= UINT64_C(15); 13782 Value |= op; 13783 // op: rot 13784 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13785 op &= UINT64_C(3); 13786 op <<= 10; 13787 Value |= op; 13788 break; 13789 } 13790 case ARM::SEL: { 13791 // op: p 13792 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13793 op &= UINT64_C(15); 13794 op <<= 28; 13795 Value |= op; 13796 // op: Rd 13797 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13798 op &= UINT64_C(15); 13799 op <<= 12; 13800 Value |= op; 13801 // op: Rn 13802 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13803 op &= UINT64_C(15); 13804 op <<= 16; 13805 Value |= op; 13806 // op: Rm 13807 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13808 op &= UINT64_C(15); 13809 Value |= op; 13810 break; 13811 } 13812 case ARM::BFC: { 13813 // op: p 13814 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13815 op &= UINT64_C(15); 13816 op <<= 28; 13817 Value |= op; 13818 // op: Rd 13819 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13820 op &= UINT64_C(15); 13821 op <<= 12; 13822 Value |= op; 13823 // op: imm 13824 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 13825 Value |= (op & UINT64_C(992)) << 11; 13826 Value |= (op & UINT64_C(31)) << 7; 13827 break; 13828 } 13829 case ARM::MOVTi16: { 13830 // op: p 13831 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13832 op &= UINT64_C(15); 13833 op <<= 28; 13834 Value |= op; 13835 // op: Rd 13836 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13837 op &= UINT64_C(15); 13838 op <<= 12; 13839 Value |= op; 13840 // op: imm 13841 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 13842 Value |= (op & UINT64_C(61440)) << 4; 13843 Value |= (op & UINT64_C(4095)); 13844 break; 13845 } 13846 case ARM::SSAT16: 13847 case ARM::USAT16: { 13848 // op: p 13849 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13850 op &= UINT64_C(15); 13851 op <<= 28; 13852 Value |= op; 13853 // op: Rd 13854 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13855 op &= UINT64_C(15); 13856 op <<= 12; 13857 Value |= op; 13858 // op: sat_imm 13859 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13860 op &= UINT64_C(15); 13861 op <<= 16; 13862 Value |= op; 13863 // op: Rn 13864 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13865 op &= UINT64_C(15); 13866 Value |= op; 13867 break; 13868 } 13869 case ARM::SDIV: 13870 case ARM::SMMUL: 13871 case ARM::SMMULR: 13872 case ARM::UDIV: 13873 case ARM::USAD8: { 13874 // op: p 13875 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13876 op &= UINT64_C(15); 13877 op <<= 28; 13878 Value |= op; 13879 // op: Rd 13880 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13881 op &= UINT64_C(15); 13882 op <<= 16; 13883 Value |= op; 13884 // op: Rn 13885 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13886 op &= UINT64_C(15); 13887 Value |= op; 13888 // op: Rm 13889 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13890 op &= UINT64_C(15); 13891 op <<= 8; 13892 Value |= op; 13893 break; 13894 } 13895 case ARM::CMNzrsi: 13896 case ARM::CMPrsi: 13897 case ARM::TEQrsi: 13898 case ARM::TSTrsi: { 13899 // op: p 13900 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13901 op &= UINT64_C(15); 13902 op <<= 28; 13903 Value |= op; 13904 // op: Rn 13905 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13906 op &= UINT64_C(15); 13907 op <<= 16; 13908 Value |= op; 13909 // op: shift 13910 op = getSORegImmOpValue(MI, 1, Fixups, STI); 13911 Value |= (op & UINT64_C(4064)); 13912 Value |= (op & UINT64_C(15)); 13913 break; 13914 } 13915 case ARM::SMUAD: 13916 case ARM::SMUADX: 13917 case ARM::SMULBB: 13918 case ARM::SMULBT: 13919 case ARM::SMULTB: 13920 case ARM::SMULTT: 13921 case ARM::SMULWB: 13922 case ARM::SMULWT: 13923 case ARM::SMUSD: 13924 case ARM::SMUSDX: { 13925 // op: p 13926 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13927 op &= UINT64_C(15); 13928 op <<= 28; 13929 Value |= op; 13930 // op: Rn 13931 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13932 op &= UINT64_C(15); 13933 Value |= op; 13934 // op: Rm 13935 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13936 op &= UINT64_C(15); 13937 op <<= 8; 13938 Value |= op; 13939 // op: Rd 13940 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13941 op &= UINT64_C(15); 13942 op <<= 16; 13943 Value |= op; 13944 break; 13945 } 13946 case ARM::QADD16: 13947 case ARM::QADD8: 13948 case ARM::QASX: 13949 case ARM::QSAX: 13950 case ARM::QSUB16: 13951 case ARM::QSUB8: 13952 case ARM::SADD16: 13953 case ARM::SADD8: 13954 case ARM::SASX: 13955 case ARM::SHADD16: 13956 case ARM::SHADD8: 13957 case ARM::SHASX: 13958 case ARM::SHSAX: 13959 case ARM::SHSUB16: 13960 case ARM::SHSUB8: 13961 case ARM::SSAX: 13962 case ARM::SSUB16: 13963 case ARM::SSUB8: 13964 case ARM::UADD16: 13965 case ARM::UADD8: 13966 case ARM::UASX: 13967 case ARM::UHADD16: 13968 case ARM::UHADD8: 13969 case ARM::UHASX: 13970 case ARM::UHSAX: 13971 case ARM::UHSUB16: 13972 case ARM::UHSUB8: 13973 case ARM::UQADD16: 13974 case ARM::UQADD8: 13975 case ARM::UQASX: 13976 case ARM::UQSAX: 13977 case ARM::UQSUB16: 13978 case ARM::UQSUB8: 13979 case ARM::USAX: 13980 case ARM::USUB16: 13981 case ARM::USUB8: { 13982 // op: p 13983 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 13984 op &= UINT64_C(15); 13985 op <<= 28; 13986 Value |= op; 13987 // op: Rn 13988 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 13989 op &= UINT64_C(15); 13990 op <<= 16; 13991 Value |= op; 13992 // op: Rd 13993 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 13994 op &= UINT64_C(15); 13995 op <<= 12; 13996 Value |= op; 13997 // op: Rm 13998 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 13999 op &= UINT64_C(15); 14000 Value |= op; 14001 break; 14002 } 14003 case ARM::QADD: 14004 case ARM::QDADD: 14005 case ARM::QDSUB: 14006 case ARM::QSUB: { 14007 // op: p 14008 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14009 op &= UINT64_C(15); 14010 op <<= 28; 14011 Value |= op; 14012 // op: Rn 14013 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14014 op &= UINT64_C(15); 14015 op <<= 16; 14016 Value |= op; 14017 // op: Rd 14018 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14019 op &= UINT64_C(15); 14020 op <<= 12; 14021 Value |= op; 14022 // op: Rm 14023 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14024 op &= UINT64_C(15); 14025 Value |= op; 14026 break; 14027 } 14028 case ARM::SWP: 14029 case ARM::SWPB: { 14030 // op: p 14031 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14032 op &= UINT64_C(15); 14033 op <<= 28; 14034 Value |= op; 14035 // op: Rt 14036 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14037 op &= UINT64_C(15); 14038 op <<= 12; 14039 Value |= op; 14040 // op: Rt2 14041 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14042 op &= UINT64_C(15); 14043 Value |= op; 14044 // op: addr 14045 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14046 op &= UINT64_C(15); 14047 op <<= 16; 14048 Value |= op; 14049 break; 14050 } 14051 case ARM::LDRBi12: 14052 case ARM::LDRi12: 14053 case ARM::STRBi12: 14054 case ARM::STRi12: { 14055 // op: p 14056 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14057 op &= UINT64_C(15); 14058 op <<= 28; 14059 Value |= op; 14060 // op: Rt 14061 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14062 op &= UINT64_C(15); 14063 op <<= 12; 14064 Value |= op; 14065 // op: addr 14066 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 14067 Value |= (op & UINT64_C(4096)) << 11; 14068 Value |= (op & UINT64_C(122880)) << 3; 14069 Value |= (op & UINT64_C(4095)); 14070 break; 14071 } 14072 case ARM::LDRcp: { 14073 // op: p 14074 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14075 op &= UINT64_C(15); 14076 op <<= 28; 14077 Value |= op; 14078 // op: Rt 14079 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14080 op &= UINT64_C(15); 14081 op <<= 12; 14082 Value |= op; 14083 // op: addr 14084 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 14085 Value |= (op & UINT64_C(4096)) << 11; 14086 Value |= (op & UINT64_C(4095)); 14087 break; 14088 } 14089 case ARM::STLEX: 14090 case ARM::STLEXB: 14091 case ARM::STLEXD: 14092 case ARM::STLEXH: 14093 case ARM::STREX: 14094 case ARM::STREXB: 14095 case ARM::STREXD: 14096 case ARM::STREXH: { 14097 // op: p 14098 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14099 op &= UINT64_C(15); 14100 op <<= 28; 14101 Value |= op; 14102 // op: Rt 14103 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14104 op &= UINT64_C(15); 14105 Value |= op; 14106 // op: addr 14107 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14108 op &= UINT64_C(15); 14109 op <<= 16; 14110 Value |= op; 14111 // op: Rd 14112 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14113 op &= UINT64_C(15); 14114 op <<= 12; 14115 Value |= op; 14116 break; 14117 } 14118 case ARM::VADDH: 14119 case ARM::VADDS: 14120 case ARM::VDIVH: 14121 case ARM::VDIVS: 14122 case ARM::VMULH: 14123 case ARM::VMULS: 14124 case ARM::VNMULH: 14125 case ARM::VNMULS: 14126 case ARM::VSUBH: 14127 case ARM::VSUBS: { 14128 // op: p 14129 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14130 op &= UINT64_C(15); 14131 op <<= 28; 14132 Value |= op; 14133 // op: Sd 14134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14135 Value |= (op & UINT64_C(1)) << 22; 14136 Value |= (op & UINT64_C(30)) << 11; 14137 // op: Sn 14138 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14139 Value |= (op & UINT64_C(30)) << 15; 14140 Value |= (op & UINT64_C(1)) << 7; 14141 // op: Sm 14142 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14143 Value |= (op & UINT64_C(1)) << 5; 14144 Value |= (op & UINT64_C(30)) >> 1; 14145 Value = VFPThumb2PostEncoder(MI, Value, STI); 14146 break; 14147 } 14148 case ARM::VLDRH: 14149 case ARM::VSTRH: { 14150 // op: p 14151 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14152 op &= UINT64_C(15); 14153 op <<= 28; 14154 Value |= op; 14155 // op: Sd 14156 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14157 Value |= (op & UINT64_C(1)) << 22; 14158 Value |= (op & UINT64_C(30)) << 11; 14159 // op: addr 14160 op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI); 14161 Value |= (op & UINT64_C(256)) << 15; 14162 Value |= (op & UINT64_C(7680)) << 7; 14163 Value |= (op & UINT64_C(255)); 14164 Value = VFPThumb2PostEncoder(MI, Value, STI); 14165 break; 14166 } 14167 case ARM::VLDRS: 14168 case ARM::VSTRS: { 14169 // op: p 14170 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14171 op &= UINT64_C(15); 14172 op <<= 28; 14173 Value |= op; 14174 // op: Sd 14175 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14176 Value |= (op & UINT64_C(1)) << 22; 14177 Value |= (op & UINT64_C(30)) << 11; 14178 // op: addr 14179 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 14180 Value |= (op & UINT64_C(256)) << 15; 14181 Value |= (op & UINT64_C(7680)) << 7; 14182 Value |= (op & UINT64_C(255)); 14183 Value = VFPThumb2PostEncoder(MI, Value, STI); 14184 break; 14185 } 14186 case ARM::VLDR_FPCXTNS_pre: 14187 case ARM::VLDR_FPCXTS_pre: 14188 case ARM::VLDR_FPSCR_NZCVQC_pre: 14189 case ARM::VLDR_FPSCR_pre: 14190 case ARM::VLDR_P0_off: 14191 case ARM::VLDR_VPR_pre: 14192 case ARM::VSTR_FPCXTNS_pre: 14193 case ARM::VSTR_FPCXTS_pre: 14194 case ARM::VSTR_FPSCR_NZCVQC_pre: 14195 case ARM::VSTR_FPSCR_pre: 14196 case ARM::VSTR_P0_off: 14197 case ARM::VSTR_VPR_pre: { 14198 // op: p 14199 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14200 op &= UINT64_C(15); 14201 op <<= 28; 14202 Value |= op; 14203 // op: addr 14204 op = getT2AddrModeImm7s4OpValue(MI, 1, Fixups, STI); 14205 Value |= (op & UINT64_C(128)) << 16; 14206 Value |= (op & UINT64_C(3840)) << 8; 14207 Value |= (op & UINT64_C(127)); 14208 Value = VFPThumb2PostEncoder(MI, Value, STI); 14209 break; 14210 } 14211 case ARM::VLDR_FPCXTNS_post: 14212 case ARM::VLDR_FPCXTS_post: 14213 case ARM::VLDR_FPSCR_NZCVQC_post: 14214 case ARM::VLDR_FPSCR_post: 14215 case ARM::VLDR_VPR_post: 14216 case ARM::VSTR_FPCXTNS_post: 14217 case ARM::VSTR_FPCXTS_post: 14218 case ARM::VSTR_FPSCR_NZCVQC_post: 14219 case ARM::VSTR_FPSCR_post: 14220 case ARM::VSTR_VPR_post: { 14221 // op: p 14222 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14223 op &= UINT64_C(15); 14224 op <<= 28; 14225 Value |= op; 14226 // op: addr 14227 op = getT2ScaledImmOpValue<7,2>(MI, 2, Fixups, STI); 14228 Value |= (op & UINT64_C(128)) << 16; 14229 Value |= (op & UINT64_C(127)); 14230 // op: Rn 14231 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14232 op &= UINT64_C(15); 14233 op <<= 16; 14234 Value |= op; 14235 Value = VFPThumb2PostEncoder(MI, Value, STI); 14236 break; 14237 } 14238 case ARM::VSHTOH: 14239 case ARM::VSHTOS: 14240 case ARM::VSLTOH: 14241 case ARM::VSLTOS: 14242 case ARM::VTOSHH: 14243 case ARM::VTOSHS: 14244 case ARM::VTOSLH: 14245 case ARM::VTOSLS: 14246 case ARM::VTOUHH: 14247 case ARM::VTOUHS: 14248 case ARM::VTOULH: 14249 case ARM::VTOULS: 14250 case ARM::VUHTOH: 14251 case ARM::VUHTOS: 14252 case ARM::VULTOH: 14253 case ARM::VULTOS: { 14254 // op: p 14255 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14256 op &= UINT64_C(15); 14257 op <<= 28; 14258 Value |= op; 14259 // op: fbits 14260 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14261 Value |= (op & UINT64_C(1)) << 5; 14262 Value |= (op & UINT64_C(30)) >> 1; 14263 // op: dst 14264 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14265 Value |= (op & UINT64_C(1)) << 22; 14266 Value |= (op & UINT64_C(30)) << 11; 14267 Value = VFPThumb2PostEncoder(MI, Value, STI); 14268 break; 14269 } 14270 case ARM::VSHTOD: 14271 case ARM::VSLTOD: 14272 case ARM::VTOSHD: 14273 case ARM::VTOSLD: 14274 case ARM::VTOUHD: 14275 case ARM::VTOULD: 14276 case ARM::VUHTOD: 14277 case ARM::VULTOD: { 14278 // op: p 14279 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14280 op &= UINT64_C(15); 14281 op <<= 28; 14282 Value |= op; 14283 // op: fbits 14284 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14285 Value |= (op & UINT64_C(1)) << 5; 14286 Value |= (op & UINT64_C(30)) >> 1; 14287 // op: dst 14288 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14289 Value |= (op & UINT64_C(16)) << 18; 14290 Value |= (op & UINT64_C(15)) << 12; 14291 Value = VFPThumb2PostEncoder(MI, Value, STI); 14292 break; 14293 } 14294 case ARM::ADCrr: 14295 case ARM::ADDrr: 14296 case ARM::ANDrr: 14297 case ARM::BICrr: 14298 case ARM::EORrr: 14299 case ARM::ORRrr: 14300 case ARM::RSBrr: 14301 case ARM::RSCrr: 14302 case ARM::SBCrr: 14303 case ARM::SUBrr: { 14304 // op: p 14305 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14306 op &= UINT64_C(15); 14307 op <<= 28; 14308 Value |= op; 14309 // op: s 14310 op = getCCOutOpValue(MI, 5, Fixups, STI); 14311 op &= UINT64_C(1); 14312 op <<= 20; 14313 Value |= op; 14314 // op: Rd 14315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14316 op &= UINT64_C(15); 14317 op <<= 12; 14318 Value |= op; 14319 // op: Rn 14320 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14321 op &= UINT64_C(15); 14322 op <<= 16; 14323 Value |= op; 14324 // op: Rm 14325 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14326 op &= UINT64_C(15); 14327 Value |= op; 14328 break; 14329 } 14330 case ARM::ADCri: 14331 case ARM::ADDri: 14332 case ARM::ANDri: 14333 case ARM::BICri: 14334 case ARM::EORri: 14335 case ARM::ORRri: 14336 case ARM::RSBri: 14337 case ARM::RSCri: 14338 case ARM::SBCri: 14339 case ARM::SUBri: { 14340 // op: p 14341 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14342 op &= UINT64_C(15); 14343 op <<= 28; 14344 Value |= op; 14345 // op: s 14346 op = getCCOutOpValue(MI, 5, Fixups, STI); 14347 op &= UINT64_C(1); 14348 op <<= 20; 14349 Value |= op; 14350 // op: Rd 14351 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14352 op &= UINT64_C(15); 14353 op <<= 12; 14354 Value |= op; 14355 // op: Rn 14356 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14357 op &= UINT64_C(15); 14358 op <<= 16; 14359 Value |= op; 14360 // op: imm 14361 op = getModImmOpValue(MI, 2, Fixups, STI); 14362 op &= UINT64_C(4095); 14363 Value |= op; 14364 break; 14365 } 14366 case ARM::MVNsi: { 14367 // op: p 14368 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14369 op &= UINT64_C(15); 14370 op <<= 28; 14371 Value |= op; 14372 // op: s 14373 op = getCCOutOpValue(MI, 5, Fixups, STI); 14374 op &= UINT64_C(1); 14375 op <<= 20; 14376 Value |= op; 14377 // op: Rd 14378 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14379 op &= UINT64_C(15); 14380 op <<= 12; 14381 Value |= op; 14382 // op: shift 14383 op = getSORegImmOpValue(MI, 1, Fixups, STI); 14384 Value |= (op & UINT64_C(4064)); 14385 Value |= (op & UINT64_C(15)); 14386 break; 14387 } 14388 case ARM::MOVsi: { 14389 // op: p 14390 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14391 op &= UINT64_C(15); 14392 op <<= 28; 14393 Value |= op; 14394 // op: s 14395 op = getCCOutOpValue(MI, 5, Fixups, STI); 14396 op &= UINT64_C(1); 14397 op <<= 20; 14398 Value |= op; 14399 // op: Rd 14400 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14401 op &= UINT64_C(15); 14402 op <<= 12; 14403 Value |= op; 14404 // op: src 14405 op = getSORegImmOpValue(MI, 1, Fixups, STI); 14406 Value |= (op & UINT64_C(4064)); 14407 Value |= (op & UINT64_C(15)); 14408 break; 14409 } 14410 case ARM::MUL: { 14411 // op: p 14412 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14413 op &= UINT64_C(15); 14414 op <<= 28; 14415 Value |= op; 14416 // op: s 14417 op = getCCOutOpValue(MI, 5, Fixups, STI); 14418 op &= UINT64_C(1); 14419 op <<= 20; 14420 Value |= op; 14421 // op: Rd 14422 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14423 op &= UINT64_C(15); 14424 op <<= 16; 14425 Value |= op; 14426 // op: Rm 14427 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14428 op &= UINT64_C(15); 14429 op <<= 8; 14430 Value |= op; 14431 // op: Rn 14432 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14433 op &= UINT64_C(15); 14434 Value |= op; 14435 break; 14436 } 14437 case ARM::VFMAD: 14438 case ARM::VFMSD: 14439 case ARM::VFNMAD: 14440 case ARM::VFNMSD: 14441 case ARM::VMLAD: 14442 case ARM::VMLSD: 14443 case ARM::VNMLAD: 14444 case ARM::VNMLSD: { 14445 // op: p 14446 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14447 op &= UINT64_C(15); 14448 op <<= 28; 14449 Value |= op; 14450 // op: Dd 14451 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14452 Value |= (op & UINT64_C(16)) << 18; 14453 Value |= (op & UINT64_C(15)) << 12; 14454 // op: Dn 14455 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14456 Value |= (op & UINT64_C(15)) << 16; 14457 Value |= (op & UINT64_C(16)) << 3; 14458 // op: Dm 14459 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14460 Value |= (op & UINT64_C(16)) << 1; 14461 Value |= (op & UINT64_C(15)); 14462 Value = VFPThumb2PostEncoder(MI, Value, STI); 14463 break; 14464 } 14465 case ARM::SXTAB: 14466 case ARM::SXTAB16: 14467 case ARM::SXTAH: 14468 case ARM::UXTAB: 14469 case ARM::UXTAB16: 14470 case ARM::UXTAH: { 14471 // op: p 14472 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14473 op &= UINT64_C(15); 14474 op <<= 28; 14475 Value |= op; 14476 // op: Rd 14477 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14478 op &= UINT64_C(15); 14479 op <<= 12; 14480 Value |= op; 14481 // op: Rm 14482 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14483 op &= UINT64_C(15); 14484 Value |= op; 14485 // op: Rn 14486 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14487 op &= UINT64_C(15); 14488 op <<= 16; 14489 Value |= op; 14490 // op: rot 14491 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14492 op &= UINT64_C(3); 14493 op <<= 10; 14494 Value |= op; 14495 break; 14496 } 14497 case ARM::SBFX: 14498 case ARM::UBFX: { 14499 // op: p 14500 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14501 op &= UINT64_C(15); 14502 op <<= 28; 14503 Value |= op; 14504 // op: Rd 14505 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14506 op &= UINT64_C(15); 14507 op <<= 12; 14508 Value |= op; 14509 // op: Rn 14510 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14511 op &= UINT64_C(15); 14512 Value |= op; 14513 // op: lsb 14514 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14515 op &= UINT64_C(31); 14516 op <<= 7; 14517 Value |= op; 14518 // op: width 14519 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14520 op &= UINT64_C(31); 14521 op <<= 16; 14522 Value |= op; 14523 break; 14524 } 14525 case ARM::PKHBT: 14526 case ARM::PKHTB: { 14527 // op: p 14528 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14529 op &= UINT64_C(15); 14530 op <<= 28; 14531 Value |= op; 14532 // op: Rd 14533 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14534 op &= UINT64_C(15); 14535 op <<= 12; 14536 Value |= op; 14537 // op: Rn 14538 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14539 op &= UINT64_C(15); 14540 op <<= 16; 14541 Value |= op; 14542 // op: Rm 14543 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14544 op &= UINT64_C(15); 14545 Value |= op; 14546 // op: sh 14547 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14548 op &= UINT64_C(31); 14549 op <<= 7; 14550 Value |= op; 14551 break; 14552 } 14553 case ARM::BFI: { 14554 // op: p 14555 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14556 op &= UINT64_C(15); 14557 op <<= 28; 14558 Value |= op; 14559 // op: Rd 14560 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14561 op &= UINT64_C(15); 14562 op <<= 12; 14563 Value |= op; 14564 // op: Rn 14565 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14566 op &= UINT64_C(15); 14567 Value |= op; 14568 // op: imm 14569 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 14570 Value |= (op & UINT64_C(992)) << 11; 14571 Value |= (op & UINT64_C(31)) << 7; 14572 break; 14573 } 14574 case ARM::SSAT: 14575 case ARM::USAT: { 14576 // op: p 14577 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14578 op &= UINT64_C(15); 14579 op <<= 28; 14580 Value |= op; 14581 // op: Rd 14582 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14583 op &= UINT64_C(15); 14584 op <<= 12; 14585 Value |= op; 14586 // op: sat_imm 14587 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14588 op &= UINT64_C(31); 14589 op <<= 16; 14590 Value |= op; 14591 // op: Rn 14592 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14593 op &= UINT64_C(15); 14594 Value |= op; 14595 // op: sh 14596 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14597 Value |= (op & UINT64_C(31)) << 7; 14598 Value |= (op & UINT64_C(32)) << 1; 14599 break; 14600 } 14601 case ARM::MLS: { 14602 // op: p 14603 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14604 op &= UINT64_C(15); 14605 op <<= 28; 14606 Value |= op; 14607 // op: Rd 14608 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14609 op &= UINT64_C(15); 14610 op <<= 16; 14611 Value |= op; 14612 // op: Rm 14613 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14614 op &= UINT64_C(15); 14615 op <<= 8; 14616 Value |= op; 14617 // op: Rn 14618 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14619 op &= UINT64_C(15); 14620 Value |= op; 14621 // op: Ra 14622 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14623 op &= UINT64_C(15); 14624 op <<= 12; 14625 Value |= op; 14626 break; 14627 } 14628 case ARM::SMMLA: 14629 case ARM::SMMLAR: 14630 case ARM::SMMLS: 14631 case ARM::SMMLSR: 14632 case ARM::USADA8: { 14633 // op: p 14634 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14635 op &= UINT64_C(15); 14636 op <<= 28; 14637 Value |= op; 14638 // op: Rd 14639 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14640 op &= UINT64_C(15); 14641 op <<= 16; 14642 Value |= op; 14643 // op: Rn 14644 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14645 op &= UINT64_C(15); 14646 Value |= op; 14647 // op: Rm 14648 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14649 op &= UINT64_C(15); 14650 op <<= 8; 14651 Value |= op; 14652 // op: Ra 14653 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14654 op &= UINT64_C(15); 14655 op <<= 12; 14656 Value |= op; 14657 break; 14658 } 14659 case ARM::CMNzrsr: 14660 case ARM::CMPrsr: 14661 case ARM::TEQrsr: 14662 case ARM::TSTrsr: { 14663 // op: p 14664 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14665 op &= UINT64_C(15); 14666 op <<= 28; 14667 Value |= op; 14668 // op: Rn 14669 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14670 op &= UINT64_C(15); 14671 op <<= 16; 14672 Value |= op; 14673 // op: shift 14674 op = getSORegRegOpValue(MI, 1, Fixups, STI); 14675 Value |= (op & UINT64_C(3840)); 14676 Value |= (op & UINT64_C(96)); 14677 Value |= (op & UINT64_C(15)); 14678 break; 14679 } 14680 case ARM::SMLAD: 14681 case ARM::SMLADX: 14682 case ARM::SMLSD: 14683 case ARM::SMLSDX: { 14684 // op: p 14685 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14686 op &= UINT64_C(15); 14687 op <<= 28; 14688 Value |= op; 14689 // op: Rn 14690 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14691 op &= UINT64_C(15); 14692 Value |= op; 14693 // op: Rm 14694 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14695 op &= UINT64_C(15); 14696 op <<= 8; 14697 Value |= op; 14698 // op: Ra 14699 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14700 op &= UINT64_C(15); 14701 op <<= 12; 14702 Value |= op; 14703 // op: Rd 14704 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14705 op &= UINT64_C(15); 14706 op <<= 16; 14707 Value |= op; 14708 break; 14709 } 14710 case ARM::SMLABB: 14711 case ARM::SMLABT: 14712 case ARM::SMLATB: 14713 case ARM::SMLATT: 14714 case ARM::SMLAWB: 14715 case ARM::SMLAWT: { 14716 // op: p 14717 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14718 op &= UINT64_C(15); 14719 op <<= 28; 14720 Value |= op; 14721 // op: Rn 14722 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14723 op &= UINT64_C(15); 14724 Value |= op; 14725 // op: Rm 14726 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14727 op &= UINT64_C(15); 14728 op <<= 8; 14729 Value |= op; 14730 // op: Rd 14731 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14732 op &= UINT64_C(15); 14733 op <<= 16; 14734 Value |= op; 14735 // op: Ra 14736 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14737 op &= UINT64_C(15); 14738 op <<= 12; 14739 Value |= op; 14740 break; 14741 } 14742 case ARM::LDRB_PRE_IMM: 14743 case ARM::LDR_PRE_IMM: { 14744 // op: p 14745 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14746 op &= UINT64_C(15); 14747 op <<= 28; 14748 Value |= op; 14749 // op: Rt 14750 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14751 op &= UINT64_C(15); 14752 op <<= 12; 14753 Value |= op; 14754 // op: addr 14755 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 14756 Value |= (op & UINT64_C(4096)) << 11; 14757 Value |= (op & UINT64_C(122880)) << 3; 14758 Value |= (op & UINT64_C(4095)); 14759 break; 14760 } 14761 case ARM::LDRBrs: 14762 case ARM::LDRrs: 14763 case ARM::STRBrs: 14764 case ARM::STRrs: { 14765 // op: p 14766 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14767 op &= UINT64_C(15); 14768 op <<= 28; 14769 Value |= op; 14770 // op: Rt 14771 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14772 op &= UINT64_C(15); 14773 op <<= 12; 14774 Value |= op; 14775 // op: shift 14776 op = getLdStSORegOpValue(MI, 1, Fixups, STI); 14777 Value |= (op & UINT64_C(4096)) << 11; 14778 Value |= (op & UINT64_C(122880)) << 3; 14779 Value |= (op & UINT64_C(4064)); 14780 Value |= (op & UINT64_C(15)); 14781 break; 14782 } 14783 case ARM::STRB_PRE_IMM: 14784 case ARM::STR_PRE_IMM: { 14785 // op: p 14786 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14787 op &= UINT64_C(15); 14788 op <<= 28; 14789 Value |= op; 14790 // op: Rt 14791 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14792 op &= UINT64_C(15); 14793 op <<= 12; 14794 Value |= op; 14795 // op: addr 14796 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 14797 Value |= (op & UINT64_C(4096)) << 11; 14798 Value |= (op & UINT64_C(122880)) << 3; 14799 Value |= (op & UINT64_C(4095)); 14800 break; 14801 } 14802 case ARM::VFMAH: 14803 case ARM::VFMAS: 14804 case ARM::VFMSH: 14805 case ARM::VFMSS: 14806 case ARM::VFNMAH: 14807 case ARM::VFNMAS: 14808 case ARM::VFNMSH: 14809 case ARM::VFNMSS: 14810 case ARM::VMLAH: 14811 case ARM::VMLAS: 14812 case ARM::VMLSH: 14813 case ARM::VMLSS: 14814 case ARM::VNMLAH: 14815 case ARM::VNMLAS: 14816 case ARM::VNMLSH: 14817 case ARM::VNMLSS: { 14818 // op: p 14819 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14820 op &= UINT64_C(15); 14821 op <<= 28; 14822 Value |= op; 14823 // op: Sd 14824 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14825 Value |= (op & UINT64_C(1)) << 22; 14826 Value |= (op & UINT64_C(30)) << 11; 14827 // op: Sn 14828 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14829 Value |= (op & UINT64_C(30)) << 15; 14830 Value |= (op & UINT64_C(1)) << 7; 14831 // op: Sm 14832 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14833 Value |= (op & UINT64_C(1)) << 5; 14834 Value |= (op & UINT64_C(30)) >> 1; 14835 Value = VFPThumb2PostEncoder(MI, Value, STI); 14836 break; 14837 } 14838 case ARM::LDRH: 14839 case ARM::LDRSB: 14840 case ARM::LDRSH: 14841 case ARM::STRH: { 14842 // op: p 14843 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14844 op &= UINT64_C(15); 14845 op <<= 28; 14846 Value |= op; 14847 // op: addr 14848 op = getAddrMode3OpValue(MI, 1, Fixups, STI); 14849 Value |= (op & UINT64_C(256)) << 15; 14850 Value |= (op & UINT64_C(8192)) << 9; 14851 Value |= (op & UINT64_C(7680)) << 7; 14852 Value |= (op & UINT64_C(240)) << 4; 14853 Value |= (op & UINT64_C(15)); 14854 // op: Rt 14855 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14856 op &= UINT64_C(15); 14857 op <<= 12; 14858 Value |= op; 14859 break; 14860 } 14861 case ARM::LDCL_OFFSET: 14862 case ARM::LDCL_PRE: 14863 case ARM::LDC_OFFSET: 14864 case ARM::LDC_PRE: 14865 case ARM::STCL_OFFSET: 14866 case ARM::STCL_PRE: 14867 case ARM::STC_OFFSET: 14868 case ARM::STC_PRE: { 14869 // op: p 14870 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14871 op &= UINT64_C(15); 14872 op <<= 28; 14873 Value |= op; 14874 // op: addr 14875 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 14876 Value |= (op & UINT64_C(256)) << 15; 14877 Value |= (op & UINT64_C(7680)) << 7; 14878 Value |= (op & UINT64_C(255)); 14879 // op: cop 14880 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14881 op &= UINT64_C(15); 14882 op <<= 8; 14883 Value |= op; 14884 // op: CRd 14885 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14886 op &= UINT64_C(15); 14887 op <<= 12; 14888 Value |= op; 14889 break; 14890 } 14891 case ARM::LDRHTi: 14892 case ARM::LDRSBTi: 14893 case ARM::LDRSHTi: { 14894 // op: p 14895 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14896 op &= UINT64_C(15); 14897 op <<= 28; 14898 Value |= op; 14899 // op: addr 14900 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14901 op &= UINT64_C(15); 14902 op <<= 16; 14903 Value |= op; 14904 // op: Rt 14905 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14906 op &= UINT64_C(15); 14907 op <<= 12; 14908 Value |= op; 14909 // op: offset 14910 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14911 Value |= (op & UINT64_C(256)) << 15; 14912 Value |= (op & UINT64_C(240)) << 4; 14913 Value |= (op & UINT64_C(15)); 14914 break; 14915 } 14916 case ARM::STRHTi: { 14917 // op: p 14918 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14919 op &= UINT64_C(15); 14920 op <<= 28; 14921 Value |= op; 14922 // op: addr 14923 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14924 op &= UINT64_C(15); 14925 op <<= 16; 14926 Value |= op; 14927 // op: Rt 14928 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 14929 op &= UINT64_C(15); 14930 op <<= 12; 14931 Value |= op; 14932 // op: offset 14933 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14934 Value |= (op & UINT64_C(256)) << 15; 14935 Value |= (op & UINT64_C(240)) << 4; 14936 Value |= (op & UINT64_C(15)); 14937 break; 14938 } 14939 case ARM::VLDR_P0_pre: 14940 case ARM::VSTR_P0_pre: { 14941 // op: p 14942 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14943 op &= UINT64_C(15); 14944 op <<= 28; 14945 Value |= op; 14946 // op: addr 14947 op = getT2AddrModeImm7s4OpValue(MI, 2, Fixups, STI); 14948 Value |= (op & UINT64_C(128)) << 16; 14949 Value |= (op & UINT64_C(3840)) << 8; 14950 Value |= (op & UINT64_C(127)); 14951 Value = VFPThumb2PostEncoder(MI, Value, STI); 14952 break; 14953 } 14954 case ARM::VLDR_P0_post: 14955 case ARM::VSTR_P0_post: { 14956 // op: p 14957 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14958 op &= UINT64_C(15); 14959 op <<= 28; 14960 Value |= op; 14961 // op: addr 14962 op = getT2ScaledImmOpValue<7,2>(MI, 3, Fixups, STI); 14963 Value |= (op & UINT64_C(128)) << 16; 14964 Value |= (op & UINT64_C(127)); 14965 // op: Rn 14966 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14967 op &= UINT64_C(15); 14968 op <<= 16; 14969 Value |= op; 14970 Value = VFPThumb2PostEncoder(MI, Value, STI); 14971 break; 14972 } 14973 case ARM::VMOVSRR: { 14974 // op: p 14975 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 14976 op &= UINT64_C(15); 14977 op <<= 28; 14978 Value |= op; 14979 // op: dst1 14980 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 14981 Value |= (op & UINT64_C(1)) << 5; 14982 Value |= (op & UINT64_C(30)) >> 1; 14983 // op: src1 14984 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 14985 op &= UINT64_C(15); 14986 op <<= 12; 14987 Value |= op; 14988 // op: src2 14989 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 14990 op &= UINT64_C(15); 14991 op <<= 16; 14992 Value |= op; 14993 Value = VFPThumb2PostEncoder(MI, Value, STI); 14994 break; 14995 } 14996 case ARM::LDCL_POST: 14997 case ARM::LDC_POST: 14998 case ARM::STCL_POST: 14999 case ARM::STC_POST: { 15000 // op: p 15001 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15002 op &= UINT64_C(15); 15003 op <<= 28; 15004 Value |= op; 15005 // op: offset 15006 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15007 Value |= (op & UINT64_C(256)) << 15; 15008 Value |= (op & UINT64_C(255)); 15009 // op: addr 15010 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15011 op &= UINT64_C(15); 15012 op <<= 16; 15013 Value |= op; 15014 // op: cop 15015 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15016 op &= UINT64_C(15); 15017 op <<= 8; 15018 Value |= op; 15019 // op: CRd 15020 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15021 op &= UINT64_C(15); 15022 op <<= 12; 15023 Value |= op; 15024 break; 15025 } 15026 case ARM::LDCL_OPTION: 15027 case ARM::LDC_OPTION: 15028 case ARM::STCL_OPTION: 15029 case ARM::STC_OPTION: { 15030 // op: p 15031 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15032 op &= UINT64_C(15); 15033 op <<= 28; 15034 Value |= op; 15035 // op: option 15036 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15037 op &= UINT64_C(255); 15038 Value |= op; 15039 // op: addr 15040 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15041 op &= UINT64_C(15); 15042 op <<= 16; 15043 Value |= op; 15044 // op: cop 15045 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15046 op &= UINT64_C(15); 15047 op <<= 8; 15048 Value |= op; 15049 // op: CRd 15050 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15051 op &= UINT64_C(15); 15052 op <<= 12; 15053 Value |= op; 15054 break; 15055 } 15056 case ARM::ADCrsi: 15057 case ARM::ADDrsi: 15058 case ARM::ANDrsi: 15059 case ARM::BICrsi: 15060 case ARM::EORrsi: 15061 case ARM::ORRrsi: 15062 case ARM::RSBrsi: 15063 case ARM::RSCrsi: 15064 case ARM::SBCrsi: 15065 case ARM::SUBrsi: { 15066 // op: p 15067 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15068 op &= UINT64_C(15); 15069 op <<= 28; 15070 Value |= op; 15071 // op: s 15072 op = getCCOutOpValue(MI, 6, Fixups, STI); 15073 op &= UINT64_C(1); 15074 op <<= 20; 15075 Value |= op; 15076 // op: Rd 15077 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15078 op &= UINT64_C(15); 15079 op <<= 12; 15080 Value |= op; 15081 // op: Rn 15082 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15083 op &= UINT64_C(15); 15084 op <<= 16; 15085 Value |= op; 15086 // op: shift 15087 op = getSORegImmOpValue(MI, 2, Fixups, STI); 15088 Value |= (op & UINT64_C(4064)); 15089 Value |= (op & UINT64_C(15)); 15090 break; 15091 } 15092 case ARM::MVNsr: { 15093 // op: p 15094 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15095 op &= UINT64_C(15); 15096 op <<= 28; 15097 Value |= op; 15098 // op: s 15099 op = getCCOutOpValue(MI, 6, Fixups, STI); 15100 op &= UINT64_C(1); 15101 op <<= 20; 15102 Value |= op; 15103 // op: Rd 15104 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15105 op &= UINT64_C(15); 15106 op <<= 12; 15107 Value |= op; 15108 // op: shift 15109 op = getSORegRegOpValue(MI, 1, Fixups, STI); 15110 Value |= (op & UINT64_C(3840)); 15111 Value |= (op & UINT64_C(96)); 15112 Value |= (op & UINT64_C(15)); 15113 break; 15114 } 15115 case ARM::MOVsr: { 15116 // op: p 15117 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15118 op &= UINT64_C(15); 15119 op <<= 28; 15120 Value |= op; 15121 // op: s 15122 op = getCCOutOpValue(MI, 6, Fixups, STI); 15123 op &= UINT64_C(1); 15124 op <<= 20; 15125 Value |= op; 15126 // op: Rd 15127 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15128 op &= UINT64_C(15); 15129 op <<= 12; 15130 Value |= op; 15131 // op: src 15132 op = getSORegRegOpValue(MI, 1, Fixups, STI); 15133 Value |= (op & UINT64_C(3840)); 15134 Value |= (op & UINT64_C(96)); 15135 Value |= (op & UINT64_C(15)); 15136 break; 15137 } 15138 case ARM::MLA: { 15139 // op: p 15140 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15141 op &= UINT64_C(15); 15142 op <<= 28; 15143 Value |= op; 15144 // op: s 15145 op = getCCOutOpValue(MI, 6, Fixups, STI); 15146 op &= UINT64_C(1); 15147 op <<= 20; 15148 Value |= op; 15149 // op: Rd 15150 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15151 op &= UINT64_C(15); 15152 op <<= 16; 15153 Value |= op; 15154 // op: Rm 15155 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15156 op &= UINT64_C(15); 15157 op <<= 8; 15158 Value |= op; 15159 // op: Rn 15160 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15161 op &= UINT64_C(15); 15162 Value |= op; 15163 // op: Ra 15164 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15165 op &= UINT64_C(15); 15166 op <<= 12; 15167 Value |= op; 15168 break; 15169 } 15170 case ARM::SMULL: 15171 case ARM::UMULL: { 15172 // op: p 15173 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15174 op &= UINT64_C(15); 15175 op <<= 28; 15176 Value |= op; 15177 // op: s 15178 op = getCCOutOpValue(MI, 6, Fixups, STI); 15179 op &= UINT64_C(1); 15180 op <<= 20; 15181 Value |= op; 15182 // op: RdLo 15183 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15184 op &= UINT64_C(15); 15185 op <<= 12; 15186 Value |= op; 15187 // op: RdHi 15188 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15189 op &= UINT64_C(15); 15190 op <<= 16; 15191 Value |= op; 15192 // op: Rm 15193 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15194 op &= UINT64_C(15); 15195 op <<= 8; 15196 Value |= op; 15197 // op: Rn 15198 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15199 op &= UINT64_C(15); 15200 Value |= op; 15201 break; 15202 } 15203 case ARM::VMOVRRS: { 15204 // op: p 15205 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15206 op &= UINT64_C(15); 15207 op <<= 28; 15208 Value |= op; 15209 // op: src1 15210 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15211 Value |= (op & UINT64_C(1)) << 5; 15212 Value |= (op & UINT64_C(30)) >> 1; 15213 // op: Rt 15214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15215 op &= UINT64_C(15); 15216 op <<= 12; 15217 Value |= op; 15218 // op: Rt2 15219 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15220 op &= UINT64_C(15); 15221 op <<= 16; 15222 Value |= op; 15223 Value = VFPThumb2PostEncoder(MI, Value, STI); 15224 break; 15225 } 15226 case ARM::MRRC: { 15227 // op: p 15228 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15229 op &= UINT64_C(15); 15230 op <<= 28; 15231 Value |= op; 15232 // op: Rt 15233 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15234 op &= UINT64_C(15); 15235 op <<= 12; 15236 Value |= op; 15237 // op: Rt2 15238 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15239 op &= UINT64_C(15); 15240 op <<= 16; 15241 Value |= op; 15242 // op: cop 15243 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15244 op &= UINT64_C(15); 15245 op <<= 8; 15246 Value |= op; 15247 // op: opc1 15248 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15249 op &= UINT64_C(15); 15250 op <<= 4; 15251 Value |= op; 15252 // op: CRm 15253 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15254 op &= UINT64_C(15); 15255 Value |= op; 15256 break; 15257 } 15258 case ARM::LDRH_PRE: 15259 case ARM::LDRSB_PRE: 15260 case ARM::LDRSH_PRE: { 15261 // op: p 15262 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15263 op &= UINT64_C(15); 15264 op <<= 28; 15265 Value |= op; 15266 // op: Rt 15267 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15268 op &= UINT64_C(15); 15269 op <<= 12; 15270 Value |= op; 15271 // op: addr 15272 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 15273 Value |= (op & UINT64_C(256)) << 15; 15274 Value |= (op & UINT64_C(8192)) << 9; 15275 Value |= (op & UINT64_C(7680)) << 7; 15276 Value |= (op & UINT64_C(240)) << 4; 15277 Value |= (op & UINT64_C(15)); 15278 break; 15279 } 15280 case ARM::LDRB_PRE_REG: 15281 case ARM::LDR_PRE_REG: { 15282 // op: p 15283 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15284 op &= UINT64_C(15); 15285 op <<= 28; 15286 Value |= op; 15287 // op: Rt 15288 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15289 op &= UINT64_C(15); 15290 op <<= 12; 15291 Value |= op; 15292 // op: addr 15293 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 15294 Value |= (op & UINT64_C(4096)) << 11; 15295 Value |= (op & UINT64_C(122880)) << 3; 15296 Value |= (op & UINT64_C(4064)); 15297 Value |= (op & UINT64_C(15)); 15298 break; 15299 } 15300 case ARM::LDRBT_POST_REG: 15301 case ARM::LDRB_POST_REG: 15302 case ARM::LDRT_POST_REG: 15303 case ARM::LDR_POST_REG: { 15304 // op: p 15305 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15306 op &= UINT64_C(15); 15307 op <<= 28; 15308 Value |= op; 15309 // op: Rt 15310 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15311 op &= UINT64_C(15); 15312 op <<= 12; 15313 Value |= op; 15314 // op: offset 15315 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 15316 Value |= (op & UINT64_C(4096)) << 11; 15317 Value |= (op & UINT64_C(4064)); 15318 Value |= (op & UINT64_C(15)); 15319 // op: addr 15320 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15321 op &= UINT64_C(15); 15322 op <<= 16; 15323 Value |= op; 15324 break; 15325 } 15326 case ARM::LDRBT_POST_IMM: 15327 case ARM::LDRB_POST_IMM: 15328 case ARM::LDRT_POST_IMM: 15329 case ARM::LDR_POST_IMM: { 15330 // op: p 15331 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15332 op &= UINT64_C(15); 15333 op <<= 28; 15334 Value |= op; 15335 // op: Rt 15336 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15337 op &= UINT64_C(15); 15338 op <<= 12; 15339 Value |= op; 15340 // op: offset 15341 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 15342 Value |= (op & UINT64_C(4096)) << 11; 15343 Value |= (op & UINT64_C(4095)); 15344 // op: addr 15345 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15346 op &= UINT64_C(15); 15347 op <<= 16; 15348 Value |= op; 15349 break; 15350 } 15351 case ARM::LDRH_POST: 15352 case ARM::LDRSB_POST: 15353 case ARM::LDRSH_POST: { 15354 // op: p 15355 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15356 op &= UINT64_C(15); 15357 op <<= 28; 15358 Value |= op; 15359 // op: Rt 15360 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15361 op &= UINT64_C(15); 15362 op <<= 12; 15363 Value |= op; 15364 // op: offset 15365 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 15366 Value |= (op & UINT64_C(256)) << 15; 15367 Value |= (op & UINT64_C(512)) << 13; 15368 Value |= (op & UINT64_C(240)) << 4; 15369 Value |= (op & UINT64_C(15)); 15370 // op: addr 15371 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15372 op &= UINT64_C(15); 15373 op <<= 16; 15374 Value |= op; 15375 break; 15376 } 15377 case ARM::STRH_PRE: { 15378 // op: p 15379 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15380 op &= UINT64_C(15); 15381 op <<= 28; 15382 Value |= op; 15383 // op: Rt 15384 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15385 op &= UINT64_C(15); 15386 op <<= 12; 15387 Value |= op; 15388 // op: addr 15389 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 15390 Value |= (op & UINT64_C(256)) << 15; 15391 Value |= (op & UINT64_C(8192)) << 9; 15392 Value |= (op & UINT64_C(7680)) << 7; 15393 Value |= (op & UINT64_C(240)) << 4; 15394 Value |= (op & UINT64_C(15)); 15395 break; 15396 } 15397 case ARM::STRB_PRE_REG: 15398 case ARM::STR_PRE_REG: { 15399 // op: p 15400 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15401 op &= UINT64_C(15); 15402 op <<= 28; 15403 Value |= op; 15404 // op: Rt 15405 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15406 op &= UINT64_C(15); 15407 op <<= 12; 15408 Value |= op; 15409 // op: addr 15410 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 15411 Value |= (op & UINT64_C(4096)) << 11; 15412 Value |= (op & UINT64_C(122880)) << 3; 15413 Value |= (op & UINT64_C(4064)); 15414 Value |= (op & UINT64_C(15)); 15415 break; 15416 } 15417 case ARM::STRBT_POST_REG: 15418 case ARM::STRB_POST_REG: 15419 case ARM::STRT_POST_REG: 15420 case ARM::STR_POST_REG: { 15421 // op: p 15422 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15423 op &= UINT64_C(15); 15424 op <<= 28; 15425 Value |= op; 15426 // op: Rt 15427 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15428 op &= UINT64_C(15); 15429 op <<= 12; 15430 Value |= op; 15431 // op: offset 15432 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 15433 Value |= (op & UINT64_C(4096)) << 11; 15434 Value |= (op & UINT64_C(4064)); 15435 Value |= (op & UINT64_C(15)); 15436 // op: addr 15437 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15438 op &= UINT64_C(15); 15439 op <<= 16; 15440 Value |= op; 15441 break; 15442 } 15443 case ARM::STRBT_POST_IMM: 15444 case ARM::STRB_POST_IMM: 15445 case ARM::STRT_POST_IMM: 15446 case ARM::STR_POST_IMM: { 15447 // op: p 15448 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15449 op &= UINT64_C(15); 15450 op <<= 28; 15451 Value |= op; 15452 // op: Rt 15453 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15454 op &= UINT64_C(15); 15455 op <<= 12; 15456 Value |= op; 15457 // op: offset 15458 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 15459 Value |= (op & UINT64_C(4096)) << 11; 15460 Value |= (op & UINT64_C(4095)); 15461 // op: addr 15462 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15463 op &= UINT64_C(15); 15464 op <<= 16; 15465 Value |= op; 15466 break; 15467 } 15468 case ARM::STRH_POST: { 15469 // op: p 15470 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15471 op &= UINT64_C(15); 15472 op <<= 28; 15473 Value |= op; 15474 // op: Rt 15475 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15476 op &= UINT64_C(15); 15477 op <<= 12; 15478 Value |= op; 15479 // op: offset 15480 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 15481 Value |= (op & UINT64_C(256)) << 15; 15482 Value |= (op & UINT64_C(512)) << 13; 15483 Value |= (op & UINT64_C(240)) << 4; 15484 Value |= (op & UINT64_C(15)); 15485 // op: addr 15486 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15487 op &= UINT64_C(15); 15488 op <<= 16; 15489 Value |= op; 15490 break; 15491 } 15492 case ARM::MCRR: { 15493 // op: p 15494 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15495 op &= UINT64_C(15); 15496 op <<= 28; 15497 Value |= op; 15498 // op: Rt 15499 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15500 op &= UINT64_C(15); 15501 op <<= 12; 15502 Value |= op; 15503 // op: Rt2 15504 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15505 op &= UINT64_C(15); 15506 op <<= 16; 15507 Value |= op; 15508 // op: cop 15509 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15510 op &= UINT64_C(15); 15511 op <<= 8; 15512 Value |= op; 15513 // op: opc1 15514 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15515 op &= UINT64_C(15); 15516 op <<= 4; 15517 Value |= op; 15518 // op: CRm 15519 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15520 op &= UINT64_C(15); 15521 Value |= op; 15522 break; 15523 } 15524 case ARM::LDRD: 15525 case ARM::STRD: { 15526 // op: p 15527 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15528 op &= UINT64_C(15); 15529 op <<= 28; 15530 Value |= op; 15531 // op: addr 15532 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 15533 Value |= (op & UINT64_C(256)) << 15; 15534 Value |= (op & UINT64_C(8192)) << 9; 15535 Value |= (op & UINT64_C(7680)) << 7; 15536 Value |= (op & UINT64_C(240)) << 4; 15537 Value |= (op & UINT64_C(15)); 15538 // op: Rt 15539 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15540 op &= UINT64_C(15); 15541 op <<= 12; 15542 Value |= op; 15543 break; 15544 } 15545 case ARM::LDRHTr: 15546 case ARM::LDRSBTr: 15547 case ARM::LDRSHTr: { 15548 // op: p 15549 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15550 op &= UINT64_C(15); 15551 op <<= 28; 15552 Value |= op; 15553 // op: addr 15554 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15555 op &= UINT64_C(15); 15556 op <<= 16; 15557 Value |= op; 15558 // op: Rt 15559 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15560 op &= UINT64_C(15); 15561 op <<= 12; 15562 Value |= op; 15563 // op: Rm 15564 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 15565 Value |= (op & UINT64_C(16)) << 19; 15566 Value |= (op & UINT64_C(15)); 15567 break; 15568 } 15569 case ARM::STRHTr: { 15570 // op: p 15571 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15572 op &= UINT64_C(15); 15573 op <<= 28; 15574 Value |= op; 15575 // op: addr 15576 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15577 op &= UINT64_C(15); 15578 op <<= 16; 15579 Value |= op; 15580 // op: Rt 15581 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15582 op &= UINT64_C(15); 15583 op <<= 12; 15584 Value |= op; 15585 // op: Rm 15586 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 15587 Value |= (op & UINT64_C(16)) << 19; 15588 Value |= (op & UINT64_C(15)); 15589 break; 15590 } 15591 case ARM::ADCrsr: 15592 case ARM::ADDrsr: 15593 case ARM::ANDrsr: 15594 case ARM::BICrsr: 15595 case ARM::EORrsr: 15596 case ARM::ORRrsr: 15597 case ARM::RSBrsr: 15598 case ARM::RSCrsr: 15599 case ARM::SBCrsr: 15600 case ARM::SUBrsr: { 15601 // op: p 15602 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15603 op &= UINT64_C(15); 15604 op <<= 28; 15605 Value |= op; 15606 // op: s 15607 op = getCCOutOpValue(MI, 7, Fixups, STI); 15608 op &= UINT64_C(1); 15609 op <<= 20; 15610 Value |= op; 15611 // op: Rd 15612 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15613 op &= UINT64_C(15); 15614 op <<= 12; 15615 Value |= op; 15616 // op: Rn 15617 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15618 op &= UINT64_C(15); 15619 op <<= 16; 15620 Value |= op; 15621 // op: shift 15622 op = getSORegRegOpValue(MI, 2, Fixups, STI); 15623 Value |= (op & UINT64_C(3840)); 15624 Value |= (op & UINT64_C(96)); 15625 Value |= (op & UINT64_C(15)); 15626 break; 15627 } 15628 case ARM::UMAAL: { 15629 // op: p 15630 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15631 op &= UINT64_C(15); 15632 op <<= 28; 15633 Value |= op; 15634 // op: RdLo 15635 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15636 op &= UINT64_C(15); 15637 op <<= 12; 15638 Value |= op; 15639 // op: RdHi 15640 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15641 op &= UINT64_C(15); 15642 op <<= 16; 15643 Value |= op; 15644 // op: Rm 15645 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15646 op &= UINT64_C(15); 15647 op <<= 8; 15648 Value |= op; 15649 // op: Rn 15650 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15651 op &= UINT64_C(15); 15652 Value |= op; 15653 break; 15654 } 15655 case ARM::SMLALBB: 15656 case ARM::SMLALBT: 15657 case ARM::SMLALD: 15658 case ARM::SMLALDX: 15659 case ARM::SMLALTB: 15660 case ARM::SMLALTT: 15661 case ARM::SMLSLD: 15662 case ARM::SMLSLDX: { 15663 // op: p 15664 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15665 op &= UINT64_C(15); 15666 op <<= 28; 15667 Value |= op; 15668 // op: Rn 15669 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15670 op &= UINT64_C(15); 15671 Value |= op; 15672 // op: Rm 15673 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15674 op &= UINT64_C(15); 15675 op <<= 8; 15676 Value |= op; 15677 // op: RdLo 15678 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15679 op &= UINT64_C(15); 15680 op <<= 12; 15681 Value |= op; 15682 // op: RdHi 15683 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15684 op &= UINT64_C(15); 15685 op <<= 16; 15686 Value |= op; 15687 break; 15688 } 15689 case ARM::LDRD_PRE: { 15690 // op: p 15691 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15692 op &= UINT64_C(15); 15693 op <<= 28; 15694 Value |= op; 15695 // op: Rt 15696 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15697 op &= UINT64_C(15); 15698 op <<= 12; 15699 Value |= op; 15700 // op: addr 15701 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 15702 Value |= (op & UINT64_C(256)) << 15; 15703 Value |= (op & UINT64_C(8192)) << 9; 15704 Value |= (op & UINT64_C(7680)) << 7; 15705 Value |= (op & UINT64_C(240)) << 4; 15706 Value |= (op & UINT64_C(15)); 15707 break; 15708 } 15709 case ARM::MRC: { 15710 // op: p 15711 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15712 op &= UINT64_C(15); 15713 op <<= 28; 15714 Value |= op; 15715 // op: Rt 15716 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15717 op &= UINT64_C(15); 15718 op <<= 12; 15719 Value |= op; 15720 // op: cop 15721 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15722 op &= UINT64_C(15); 15723 op <<= 8; 15724 Value |= op; 15725 // op: opc1 15726 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15727 op &= UINT64_C(7); 15728 op <<= 21; 15729 Value |= op; 15730 // op: opc2 15731 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15732 op &= UINT64_C(7); 15733 op <<= 5; 15734 Value |= op; 15735 // op: CRm 15736 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15737 op &= UINT64_C(15); 15738 Value |= op; 15739 // op: CRn 15740 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15741 op &= UINT64_C(15); 15742 op <<= 16; 15743 Value |= op; 15744 break; 15745 } 15746 case ARM::LDRD_POST: { 15747 // op: p 15748 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15749 op &= UINT64_C(15); 15750 op <<= 28; 15751 Value |= op; 15752 // op: Rt 15753 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15754 op &= UINT64_C(15); 15755 op <<= 12; 15756 Value |= op; 15757 // op: offset 15758 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 15759 Value |= (op & UINT64_C(256)) << 15; 15760 Value |= (op & UINT64_C(512)) << 13; 15761 Value |= (op & UINT64_C(240)) << 4; 15762 Value |= (op & UINT64_C(15)); 15763 // op: addr 15764 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15765 op &= UINT64_C(15); 15766 op <<= 16; 15767 Value |= op; 15768 break; 15769 } 15770 case ARM::STRD_PRE: { 15771 // op: p 15772 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15773 op &= UINT64_C(15); 15774 op <<= 28; 15775 Value |= op; 15776 // op: Rt 15777 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15778 op &= UINT64_C(15); 15779 op <<= 12; 15780 Value |= op; 15781 // op: addr 15782 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 15783 Value |= (op & UINT64_C(256)) << 15; 15784 Value |= (op & UINT64_C(8192)) << 9; 15785 Value |= (op & UINT64_C(7680)) << 7; 15786 Value |= (op & UINT64_C(240)) << 4; 15787 Value |= (op & UINT64_C(15)); 15788 break; 15789 } 15790 case ARM::STRD_POST: { 15791 // op: p 15792 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15793 op &= UINT64_C(15); 15794 op <<= 28; 15795 Value |= op; 15796 // op: Rt 15797 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15798 op &= UINT64_C(15); 15799 op <<= 12; 15800 Value |= op; 15801 // op: offset 15802 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 15803 Value |= (op & UINT64_C(256)) << 15; 15804 Value |= (op & UINT64_C(512)) << 13; 15805 Value |= (op & UINT64_C(240)) << 4; 15806 Value |= (op & UINT64_C(15)); 15807 // op: addr 15808 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15809 op &= UINT64_C(15); 15810 op <<= 16; 15811 Value |= op; 15812 break; 15813 } 15814 case ARM::MCR: { 15815 // op: p 15816 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15817 op &= UINT64_C(15); 15818 op <<= 28; 15819 Value |= op; 15820 // op: Rt 15821 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15822 op &= UINT64_C(15); 15823 op <<= 12; 15824 Value |= op; 15825 // op: cop 15826 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15827 op &= UINT64_C(15); 15828 op <<= 8; 15829 Value |= op; 15830 // op: opc1 15831 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15832 op &= UINT64_C(7); 15833 op <<= 21; 15834 Value |= op; 15835 // op: opc2 15836 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15837 op &= UINT64_C(7); 15838 op <<= 5; 15839 Value |= op; 15840 // op: CRm 15841 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15842 op &= UINT64_C(15); 15843 Value |= op; 15844 // op: CRn 15845 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15846 op &= UINT64_C(15); 15847 op <<= 16; 15848 Value |= op; 15849 break; 15850 } 15851 case ARM::CDP: { 15852 // op: p 15853 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15854 op &= UINT64_C(15); 15855 op <<= 28; 15856 Value |= op; 15857 // op: opc1 15858 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15859 op &= UINT64_C(15); 15860 op <<= 20; 15861 Value |= op; 15862 // op: CRn 15863 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15864 op &= UINT64_C(15); 15865 op <<= 16; 15866 Value |= op; 15867 // op: CRd 15868 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15869 op &= UINT64_C(15); 15870 op <<= 12; 15871 Value |= op; 15872 // op: cop 15873 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15874 op &= UINT64_C(15); 15875 op <<= 8; 15876 Value |= op; 15877 // op: opc2 15878 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 15879 op &= UINT64_C(7); 15880 op <<= 5; 15881 Value |= op; 15882 // op: CRm 15883 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 15884 op &= UINT64_C(15); 15885 Value |= op; 15886 break; 15887 } 15888 case ARM::SMLAL: 15889 case ARM::UMLAL: { 15890 // op: p 15891 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 15892 op &= UINT64_C(15); 15893 op <<= 28; 15894 Value |= op; 15895 // op: s 15896 op = getCCOutOpValue(MI, 8, Fixups, STI); 15897 op &= UINT64_C(1); 15898 op <<= 20; 15899 Value |= op; 15900 // op: RdLo 15901 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15902 op &= UINT64_C(15); 15903 op <<= 12; 15904 Value |= op; 15905 // op: RdHi 15906 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15907 op &= UINT64_C(15); 15908 op <<= 16; 15909 Value |= op; 15910 // op: Rm 15911 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 15912 op &= UINT64_C(15); 15913 op <<= 8; 15914 Value |= op; 15915 // op: Rn 15916 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 15917 op &= UINT64_C(15); 15918 Value |= op; 15919 break; 15920 } 15921 case ARM::tPUSH: { 15922 // op: regs 15923 op = getRegisterListOpValue(MI, 2, Fixups, STI); 15924 Value |= (op & UINT64_C(16384)) >> 6; 15925 Value |= (op & UINT64_C(255)); 15926 break; 15927 } 15928 case ARM::VSCCLRMS: { 15929 // op: regs 15930 op = getRegisterListOpValue(MI, 2, Fixups, STI); 15931 Value |= (op & UINT64_C(256)) << 14; 15932 Value |= (op & UINT64_C(7680)) << 3; 15933 Value |= (op & UINT64_C(255)); 15934 Value = VFPThumb2PostEncoder(MI, Value, STI); 15935 break; 15936 } 15937 case ARM::tPOP: { 15938 // op: regs 15939 op = getRegisterListOpValue(MI, 2, Fixups, STI); 15940 Value |= (op & UINT64_C(32768)) >> 7; 15941 Value |= (op & UINT64_C(255)); 15942 break; 15943 } 15944 case ARM::VSCCLRMD: { 15945 // op: regs 15946 op = getRegisterListOpValue(MI, 2, Fixups, STI); 15947 Value |= (op & UINT64_C(4096)) << 10; 15948 Value |= (op & UINT64_C(3840)) << 4; 15949 Value |= (op & UINT64_C(254)); 15950 Value = VFPThumb2PostEncoder(MI, Value, STI); 15951 break; 15952 } 15953 case ARM::t2CLRM: { 15954 // op: regs 15955 op = getRegisterListOpValue(MI, 2, Fixups, STI); 15956 Value |= (op & UINT64_C(49152)); 15957 Value |= (op & UINT64_C(8191)); 15958 break; 15959 } 15960 case ARM::t2MOVr: 15961 case ARM::t2MVNr: 15962 case ARM::t2RRX: { 15963 // op: s 15964 op = getCCOutOpValue(MI, 4, Fixups, STI); 15965 op &= UINT64_C(1); 15966 op <<= 20; 15967 Value |= op; 15968 // op: Rd 15969 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15970 op &= UINT64_C(15); 15971 op <<= 8; 15972 Value |= op; 15973 // op: Rm 15974 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 15975 op &= UINT64_C(15); 15976 Value |= op; 15977 break; 15978 } 15979 case ARM::t2MOVi: 15980 case ARM::t2MVNi: { 15981 // op: s 15982 op = getCCOutOpValue(MI, 4, Fixups, STI); 15983 op &= UINT64_C(1); 15984 op <<= 20; 15985 Value |= op; 15986 // op: Rd 15987 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 15988 op &= UINT64_C(15); 15989 op <<= 8; 15990 Value |= op; 15991 // op: imm 15992 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 15993 Value |= (op & UINT64_C(2048)) << 15; 15994 Value |= (op & UINT64_C(1792)) << 4; 15995 Value |= (op & UINT64_C(255)); 15996 break; 15997 } 15998 case ARM::t2ASRri: 15999 case ARM::t2LSLri: 16000 case ARM::t2LSRri: 16001 case ARM::t2RORri: { 16002 // op: s 16003 op = getCCOutOpValue(MI, 5, Fixups, STI); 16004 op &= UINT64_C(1); 16005 op <<= 20; 16006 Value |= op; 16007 // op: Rd 16008 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16009 op &= UINT64_C(15); 16010 op <<= 8; 16011 Value |= op; 16012 // op: Rm 16013 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16014 op &= UINT64_C(15); 16015 Value |= op; 16016 // op: imm 16017 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16018 Value |= (op & UINT64_C(28)) << 10; 16019 Value |= (op & UINT64_C(3)) << 6; 16020 break; 16021 } 16022 case ARM::t2ADCrr: 16023 case ARM::t2ADDrr: 16024 case ARM::t2ANDrr: 16025 case ARM::t2ASRrr: 16026 case ARM::t2BICrr: 16027 case ARM::t2EORrr: 16028 case ARM::t2LSLrr: 16029 case ARM::t2LSRrr: 16030 case ARM::t2ORNrr: 16031 case ARM::t2ORRrr: 16032 case ARM::t2RORrr: 16033 case ARM::t2RSBrr: 16034 case ARM::t2SBCrr: 16035 case ARM::t2SUBrr: { 16036 // op: s 16037 op = getCCOutOpValue(MI, 5, Fixups, STI); 16038 op &= UINT64_C(1); 16039 op <<= 20; 16040 Value |= op; 16041 // op: Rd 16042 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16043 op &= UINT64_C(15); 16044 op <<= 8; 16045 Value |= op; 16046 // op: Rn 16047 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16048 op &= UINT64_C(15); 16049 op <<= 16; 16050 Value |= op; 16051 // op: Rm 16052 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 16053 op &= UINT64_C(15); 16054 Value |= op; 16055 break; 16056 } 16057 case ARM::t2ADCri: 16058 case ARM::t2ADDri: 16059 case ARM::t2ANDri: 16060 case ARM::t2BICri: 16061 case ARM::t2EORri: 16062 case ARM::t2ORNri: 16063 case ARM::t2ORRri: 16064 case ARM::t2RSBri: 16065 case ARM::t2SBCri: 16066 case ARM::t2SUBri: { 16067 // op: s 16068 op = getCCOutOpValue(MI, 5, Fixups, STI); 16069 op &= UINT64_C(1); 16070 op <<= 20; 16071 Value |= op; 16072 // op: Rd 16073 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16074 op &= UINT64_C(15); 16075 op <<= 8; 16076 Value |= op; 16077 // op: Rn 16078 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16079 op &= UINT64_C(15); 16080 op <<= 16; 16081 Value |= op; 16082 // op: imm 16083 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 16084 Value |= (op & UINT64_C(2048)) << 15; 16085 Value |= (op & UINT64_C(1792)) << 4; 16086 Value |= (op & UINT64_C(255)); 16087 break; 16088 } 16089 case ARM::t2MVNs: { 16090 // op: s 16091 op = getCCOutOpValue(MI, 5, Fixups, STI); 16092 op &= UINT64_C(1); 16093 op <<= 20; 16094 Value |= op; 16095 // op: Rd 16096 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16097 op &= UINT64_C(15); 16098 op <<= 8; 16099 Value |= op; 16100 // op: ShiftedRm 16101 op = getT2SORegOpValue(MI, 1, Fixups, STI); 16102 Value |= (op & UINT64_C(3584)) << 3; 16103 Value |= (op & UINT64_C(480)) >> 1; 16104 Value |= (op & UINT64_C(15)); 16105 break; 16106 } 16107 case ARM::t2ADDspImm: 16108 case ARM::t2SUBspImm: { 16109 // op: s 16110 op = getCCOutOpValue(MI, 5, Fixups, STI); 16111 op &= UINT64_C(1); 16112 op <<= 20; 16113 Value |= op; 16114 // op: imm 16115 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 16116 Value |= (op & UINT64_C(2048)) << 15; 16117 Value |= (op & UINT64_C(1792)) << 4; 16118 Value |= (op & UINT64_C(255)); 16119 break; 16120 } 16121 case ARM::t2ADCrs: 16122 case ARM::t2ADDrs: 16123 case ARM::t2ANDrs: 16124 case ARM::t2BICrs: 16125 case ARM::t2EORrs: 16126 case ARM::t2ORNrs: 16127 case ARM::t2ORRrs: 16128 case ARM::t2RSBrs: 16129 case ARM::t2SBCrs: 16130 case ARM::t2SUBrs: { 16131 // op: s 16132 op = getCCOutOpValue(MI, 6, Fixups, STI); 16133 op &= UINT64_C(1); 16134 op <<= 20; 16135 Value |= op; 16136 // op: Rd 16137 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16138 op &= UINT64_C(15); 16139 op <<= 8; 16140 Value |= op; 16141 // op: Rn 16142 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 16143 op &= UINT64_C(15); 16144 op <<= 16; 16145 Value |= op; 16146 // op: ShiftedRm 16147 op = getT2SORegOpValue(MI, 2, Fixups, STI); 16148 Value |= (op & UINT64_C(3584)) << 3; 16149 Value |= (op & UINT64_C(480)) >> 1; 16150 Value |= (op & UINT64_C(15)); 16151 break; 16152 } 16153 case ARM::PLDWrs: 16154 case ARM::PLDrs: 16155 case ARM::PLIrs: { 16156 // op: shift 16157 op = getLdStSORegOpValue(MI, 0, Fixups, STI); 16158 Value |= (op & UINT64_C(4096)) << 11; 16159 Value |= (op & UINT64_C(122880)) << 3; 16160 Value |= (op & UINT64_C(4064)); 16161 Value |= (op & UINT64_C(15)); 16162 break; 16163 } 16164 case ARM::BLXi: { 16165 // op: target 16166 op = getARMBLXTargetOpValue(MI, 0, Fixups, STI); 16167 Value |= (op & UINT64_C(1)) << 24; 16168 Value |= (op & UINT64_C(33554430)) >> 1; 16169 break; 16170 } 16171 case ARM::tB: { 16172 // op: target 16173 op = getThumbBRTargetOpValue(MI, 0, Fixups, STI); 16174 op &= UINT64_C(2047); 16175 Value |= op; 16176 break; 16177 } 16178 case ARM::t2B: { 16179 // op: target 16180 op = getThumbBranchTargetOpValue(MI, 0, Fixups, STI); 16181 Value |= (op & UINT64_C(8388608)) << 3; 16182 Value |= (op & UINT64_C(2095104)) << 5; 16183 Value |= (op & UINT64_C(4194304)) >> 9; 16184 Value |= (op & UINT64_C(2097152)) >> 10; 16185 Value |= (op & UINT64_C(2047)); 16186 break; 16187 } 16188 case ARM::tCBNZ: 16189 case ARM::tCBZ: { 16190 // op: target 16191 op = getThumbCBTargetOpValue(MI, 1, Fixups, STI); 16192 Value |= (op & UINT64_C(32)) << 4; 16193 Value |= (op & UINT64_C(31)) << 3; 16194 // op: Rn 16195 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16196 op &= UINT64_C(7); 16197 Value |= op; 16198 break; 16199 } 16200 case ARM::BKPT: 16201 case ARM::HLT: { 16202 // op: val 16203 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16204 Value |= (op & UINT64_C(65520)) << 4; 16205 Value |= (op & UINT64_C(15)); 16206 break; 16207 } 16208 case ARM::tBKPT: { 16209 // op: val 16210 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16211 op &= UINT64_C(255); 16212 Value |= op; 16213 break; 16214 } 16215 case ARM::tHLT: { 16216 // op: val 16217 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 16218 op &= UINT64_C(63); 16219 Value |= op; 16220 break; 16221 } 16222 default: 16223 std::string msg; 16224 raw_string_ostream Msg(msg); 16225 Msg << "Not supported instr: " << MI; 16226 report_fatal_error(Msg.str()); 16227 } 16228 return Value; 16229} 16230 16231#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 16232#undef ENABLE_INSTR_PREDICATE_VERIFIER 16233#include <sstream> 16234 16235// Bits for subtarget features that participate in instruction matching. 16236enum SubtargetFeatureBits : uint8_t { 16237 Feature_HasV4TBit = 29, 16238 Feature_HasV5TBit = 30, 16239 Feature_HasV5TEBit = 31, 16240 Feature_HasV6Bit = 32, 16241 Feature_HasV6MBit = 34, 16242 Feature_HasV8MBaselineBit = 39, 16243 Feature_HasV8MMainlineBit = 40, 16244 Feature_HasV8_1MMainlineBit = 41, 16245 Feature_HasMVEIntBit = 23, 16246 Feature_HasMVEFloatBit = 22, 16247 Feature_HasFPRegsBit = 15, 16248 Feature_HasFPRegs16Bit = 16, 16249 Feature_HasFPRegs64Bit = 17, 16250 Feature_HasFPRegsV8_1MBit = 18, 16251 Feature_HasV6T2Bit = 35, 16252 Feature_HasV6KBit = 33, 16253 Feature_HasV7Bit = 36, 16254 Feature_HasV8Bit = 38, 16255 Feature_PreV8Bit = 56, 16256 Feature_HasV8_1aBit = 42, 16257 Feature_HasV8_2aBit = 43, 16258 Feature_HasV8_3aBit = 44, 16259 Feature_HasV8_4aBit = 45, 16260 Feature_HasV8_5aBit = 46, 16261 Feature_HasVFP2Bit = 47, 16262 Feature_HasVFP3Bit = 48, 16263 Feature_HasVFP4Bit = 49, 16264 Feature_HasDPVFPBit = 7, 16265 Feature_HasFPARMv8Bit = 14, 16266 Feature_HasNEONBit = 24, 16267 Feature_HasSHA2Bit = 27, 16268 Feature_HasAESBit = 1, 16269 Feature_HasCryptoBit = 4, 16270 Feature_HasDotProdBit = 11, 16271 Feature_HasCRCBit = 3, 16272 Feature_HasRASBit = 25, 16273 Feature_HasLOBBit = 20, 16274 Feature_HasFP16Bit = 12, 16275 Feature_HasFullFP16Bit = 19, 16276 Feature_HasFP16FMLBit = 13, 16277 Feature_HasDivideInThumbBit = 10, 16278 Feature_HasDivideInARMBit = 9, 16279 Feature_HasDSPBit = 8, 16280 Feature_HasDBBit = 5, 16281 Feature_HasDFBBit = 6, 16282 Feature_HasV7ClrexBit = 37, 16283 Feature_HasAcquireReleaseBit = 2, 16284 Feature_HasMPBit = 21, 16285 Feature_HasVirtualizationBit = 50, 16286 Feature_HasTrustZoneBit = 28, 16287 Feature_Has8MSecExtBit = 0, 16288 Feature_IsThumbBit = 54, 16289 Feature_IsThumb2Bit = 55, 16290 Feature_IsMClassBit = 52, 16291 Feature_IsNotMClassBit = 53, 16292 Feature_IsARMBit = 51, 16293 Feature_UseNaClTrapBit = 57, 16294 Feature_UseNegativeImmediatesBit = 58, 16295 Feature_HasSBBit = 26, 16296}; 16297 16298#ifndef NDEBUG 16299static const char *SubtargetFeatureNames[] = { 16300 "Feature_Has8MSecExt", 16301 "Feature_HasAES", 16302 "Feature_HasAcquireRelease", 16303 "Feature_HasCRC", 16304 "Feature_HasCrypto", 16305 "Feature_HasDB", 16306 "Feature_HasDFB", 16307 "Feature_HasDPVFP", 16308 "Feature_HasDSP", 16309 "Feature_HasDivideInARM", 16310 "Feature_HasDivideInThumb", 16311 "Feature_HasDotProd", 16312 "Feature_HasFP16", 16313 "Feature_HasFP16FML", 16314 "Feature_HasFPARMv8", 16315 "Feature_HasFPRegs", 16316 "Feature_HasFPRegs16", 16317 "Feature_HasFPRegs64", 16318 "Feature_HasFPRegsV8_1M", 16319 "Feature_HasFullFP16", 16320 "Feature_HasLOB", 16321 "Feature_HasMP", 16322 "Feature_HasMVEFloat", 16323 "Feature_HasMVEInt", 16324 "Feature_HasNEON", 16325 "Feature_HasRAS", 16326 "Feature_HasSB", 16327 "Feature_HasSHA2", 16328 "Feature_HasTrustZone", 16329 "Feature_HasV4T", 16330 "Feature_HasV5T", 16331 "Feature_HasV5TE", 16332 "Feature_HasV6", 16333 "Feature_HasV6K", 16334 "Feature_HasV6M", 16335 "Feature_HasV6T2", 16336 "Feature_HasV7", 16337 "Feature_HasV7Clrex", 16338 "Feature_HasV8", 16339 "Feature_HasV8MBaseline", 16340 "Feature_HasV8MMainline", 16341 "Feature_HasV8_1MMainline", 16342 "Feature_HasV8_1a", 16343 "Feature_HasV8_2a", 16344 "Feature_HasV8_3a", 16345 "Feature_HasV8_4a", 16346 "Feature_HasV8_5a", 16347 "Feature_HasVFP2", 16348 "Feature_HasVFP3", 16349 "Feature_HasVFP4", 16350 "Feature_HasVirtualization", 16351 "Feature_IsARM", 16352 "Feature_IsMClass", 16353 "Feature_IsNotMClass", 16354 "Feature_IsThumb", 16355 "Feature_IsThumb2", 16356 "Feature_PreV8", 16357 "Feature_UseNaClTrap", 16358 "Feature_UseNegativeImmediates", 16359 nullptr 16360}; 16361 16362#endif // NDEBUG 16363FeatureBitset ARMMCCodeEmitter:: 16364computeAvailableFeatures(const FeatureBitset& FB) const { 16365 FeatureBitset Features; 16366 if ((FB[ARM::HasV4TOps])) 16367 Features.set(Feature_HasV4TBit); 16368 if ((FB[ARM::HasV5TOps])) 16369 Features.set(Feature_HasV5TBit); 16370 if ((FB[ARM::HasV5TEOps])) 16371 Features.set(Feature_HasV5TEBit); 16372 if ((FB[ARM::HasV6Ops])) 16373 Features.set(Feature_HasV6Bit); 16374 if ((FB[ARM::HasV6MOps])) 16375 Features.set(Feature_HasV6MBit); 16376 if ((FB[ARM::HasV8MBaselineOps])) 16377 Features.set(Feature_HasV8MBaselineBit); 16378 if ((FB[ARM::HasV8MMainlineOps])) 16379 Features.set(Feature_HasV8MMainlineBit); 16380 if ((FB[ARM::HasV8_1MMainlineOps])) 16381 Features.set(Feature_HasV8_1MMainlineBit); 16382 if ((FB[ARM::HasMVEIntegerOps])) 16383 Features.set(Feature_HasMVEIntBit); 16384 if ((FB[ARM::HasMVEFloatOps])) 16385 Features.set(Feature_HasMVEFloatBit); 16386 if ((FB[ARM::FeatureFPRegs])) 16387 Features.set(Feature_HasFPRegsBit); 16388 if ((FB[ARM::FeatureFPRegs16])) 16389 Features.set(Feature_HasFPRegs16Bit); 16390 if ((FB[ARM::FeatureFPRegs64])) 16391 Features.set(Feature_HasFPRegs64Bit); 16392 if ((FB[ARM::FeatureFPRegs]) && (FB[ARM::HasV8_1MMainlineOps])) 16393 Features.set(Feature_HasFPRegsV8_1MBit); 16394 if ((FB[ARM::HasV6T2Ops])) 16395 Features.set(Feature_HasV6T2Bit); 16396 if ((FB[ARM::HasV6KOps])) 16397 Features.set(Feature_HasV6KBit); 16398 if ((FB[ARM::HasV7Ops])) 16399 Features.set(Feature_HasV7Bit); 16400 if ((FB[ARM::HasV8Ops])) 16401 Features.set(Feature_HasV8Bit); 16402 if ((!FB[ARM::HasV8Ops])) 16403 Features.set(Feature_PreV8Bit); 16404 if ((FB[ARM::HasV8_1aOps])) 16405 Features.set(Feature_HasV8_1aBit); 16406 if ((FB[ARM::HasV8_2aOps])) 16407 Features.set(Feature_HasV8_2aBit); 16408 if ((FB[ARM::HasV8_3aOps])) 16409 Features.set(Feature_HasV8_3aBit); 16410 if ((FB[ARM::HasV8_4aOps])) 16411 Features.set(Feature_HasV8_4aBit); 16412 if ((FB[ARM::HasV8_5aOps])) 16413 Features.set(Feature_HasV8_5aBit); 16414 if ((FB[ARM::FeatureVFP2_SP])) 16415 Features.set(Feature_HasVFP2Bit); 16416 if ((FB[ARM::FeatureVFP3_D16_SP])) 16417 Features.set(Feature_HasVFP3Bit); 16418 if ((FB[ARM::FeatureVFP4_D16_SP])) 16419 Features.set(Feature_HasVFP4Bit); 16420 if ((FB[ARM::FeatureFP64])) 16421 Features.set(Feature_HasDPVFPBit); 16422 if ((FB[ARM::FeatureFPARMv8_D16_SP])) 16423 Features.set(Feature_HasFPARMv8Bit); 16424 if ((FB[ARM::FeatureNEON])) 16425 Features.set(Feature_HasNEONBit); 16426 if ((FB[ARM::FeatureSHA2])) 16427 Features.set(Feature_HasSHA2Bit); 16428 if ((FB[ARM::FeatureAES])) 16429 Features.set(Feature_HasAESBit); 16430 if ((FB[ARM::FeatureCrypto])) 16431 Features.set(Feature_HasCryptoBit); 16432 if ((FB[ARM::FeatureDotProd])) 16433 Features.set(Feature_HasDotProdBit); 16434 if ((FB[ARM::FeatureCRC])) 16435 Features.set(Feature_HasCRCBit); 16436 if ((FB[ARM::FeatureRAS])) 16437 Features.set(Feature_HasRASBit); 16438 if ((FB[ARM::FeatureLOB])) 16439 Features.set(Feature_HasLOBBit); 16440 if ((FB[ARM::FeatureFP16])) 16441 Features.set(Feature_HasFP16Bit); 16442 if ((FB[ARM::FeatureFullFP16])) 16443 Features.set(Feature_HasFullFP16Bit); 16444 if ((FB[ARM::FeatureFP16FML])) 16445 Features.set(Feature_HasFP16FMLBit); 16446 if ((FB[ARM::FeatureHWDivThumb])) 16447 Features.set(Feature_HasDivideInThumbBit); 16448 if ((FB[ARM::FeatureHWDivARM])) 16449 Features.set(Feature_HasDivideInARMBit); 16450 if ((FB[ARM::FeatureDSP])) 16451 Features.set(Feature_HasDSPBit); 16452 if ((FB[ARM::FeatureDB])) 16453 Features.set(Feature_HasDBBit); 16454 if ((FB[ARM::FeatureDFB])) 16455 Features.set(Feature_HasDFBBit); 16456 if ((FB[ARM::FeatureV7Clrex])) 16457 Features.set(Feature_HasV7ClrexBit); 16458 if ((FB[ARM::FeatureAcquireRelease])) 16459 Features.set(Feature_HasAcquireReleaseBit); 16460 if ((FB[ARM::FeatureMP])) 16461 Features.set(Feature_HasMPBit); 16462 if ((FB[ARM::FeatureVirtualization])) 16463 Features.set(Feature_HasVirtualizationBit); 16464 if ((FB[ARM::FeatureTrustZone])) 16465 Features.set(Feature_HasTrustZoneBit); 16466 if ((FB[ARM::Feature8MSecExt])) 16467 Features.set(Feature_Has8MSecExtBit); 16468 if ((FB[ARM::ModeThumb])) 16469 Features.set(Feature_IsThumbBit); 16470 if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2])) 16471 Features.set(Feature_IsThumb2Bit); 16472 if ((FB[ARM::FeatureMClass])) 16473 Features.set(Feature_IsMClassBit); 16474 if ((!FB[ARM::FeatureMClass])) 16475 Features.set(Feature_IsNotMClassBit); 16476 if ((!FB[ARM::ModeThumb])) 16477 Features.set(Feature_IsARMBit); 16478 if ((FB[ARM::FeatureNaClTrap])) 16479 Features.set(Feature_UseNaClTrapBit); 16480 if ((!FB[ARM::FeatureNoNegativeImmediates])) 16481 Features.set(Feature_UseNegativeImmediatesBit); 16482 if ((FB[ARM::FeatureSB])) 16483 Features.set(Feature_HasSBBit); 16484 return Features; 16485} 16486 16487#ifndef NDEBUG 16488// Feature bitsets. 16489enum : uint8_t { 16490 CEFBS_None, 16491 CEFBS_Has8MSecExt, 16492 CEFBS_HasDotProd, 16493 CEFBS_HasFP16, 16494 CEFBS_HasFPARMv8, 16495 CEFBS_HasFPRegs, 16496 CEFBS_HasFPRegs16, 16497 CEFBS_HasFPRegs64, 16498 CEFBS_HasFPRegsV8_1M, 16499 CEFBS_HasFullFP16, 16500 CEFBS_HasMVEFloat, 16501 CEFBS_HasMVEInt, 16502 CEFBS_HasNEON, 16503 CEFBS_HasV8_1MMainline, 16504 CEFBS_HasVFP2, 16505 CEFBS_HasVFP3, 16506 CEFBS_HasVFP4, 16507 CEFBS_IsARM, 16508 CEFBS_IsThumb, 16509 CEFBS_IsThumb2, 16510 CEFBS_HasDSP_IsThumb2, 16511 CEFBS_HasFPARMv8_HasDPVFP, 16512 CEFBS_HasFPARMv8_HasV8_3a, 16513 CEFBS_HasFPRegs_HasV8_1MMainline, 16514 CEFBS_HasNEON_HasFP16, 16515 CEFBS_HasNEON_HasFP16FML, 16516 CEFBS_HasNEON_HasFullFP16, 16517 CEFBS_HasNEON_HasV8_1a, 16518 CEFBS_HasNEON_HasV8_3a, 16519 CEFBS_HasNEON_HasVFP4, 16520 CEFBS_HasV8_HasCrypto, 16521 CEFBS_HasV8_HasNEON, 16522 CEFBS_HasV8MMainline_Has8MSecExt, 16523 CEFBS_HasV8_1MMainline_Has8MSecExt, 16524 CEFBS_HasV8_1MMainline_HasFPRegs, 16525 CEFBS_HasV8_1MMainline_HasMVEInt, 16526 CEFBS_HasVFP2_HasDPVFP, 16527 CEFBS_HasVFP3_HasDPVFP, 16528 CEFBS_HasVFP4_HasDPVFP, 16529 CEFBS_IsARM_HasAcquireRelease, 16530 CEFBS_IsARM_HasDB, 16531 CEFBS_IsARM_HasDivideInARM, 16532 CEFBS_IsARM_HasSB, 16533 CEFBS_IsARM_HasTrustZone, 16534 CEFBS_IsARM_HasV4T, 16535 CEFBS_IsARM_HasV5T, 16536 CEFBS_IsARM_HasV5TE, 16537 CEFBS_IsARM_HasV6, 16538 CEFBS_IsARM_HasV6K, 16539 CEFBS_IsARM_HasV6T2, 16540 CEFBS_IsARM_HasV7, 16541 CEFBS_IsARM_HasV8, 16542 CEFBS_IsARM_HasV8_4a, 16543 CEFBS_IsARM_HasVFP2, 16544 CEFBS_IsARM_HasVirtualization, 16545 CEFBS_IsARM_PreV8, 16546 CEFBS_IsARM_UseNaClTrap, 16547 CEFBS_IsThumb_Has8MSecExt, 16548 CEFBS_IsThumb_HasAcquireRelease, 16549 CEFBS_IsThumb_HasDB, 16550 CEFBS_IsThumb_HasV5T, 16551 CEFBS_IsThumb_HasV6, 16552 CEFBS_IsThumb_HasV6M, 16553 CEFBS_IsThumb_HasV7Clrex, 16554 CEFBS_IsThumb_HasV8, 16555 CEFBS_IsThumb_HasV8MBaseline, 16556 CEFBS_IsThumb_HasV8_4a, 16557 CEFBS_IsThumb_HasVirtualization, 16558 CEFBS_IsThumb_IsMClass, 16559 CEFBS_IsThumb_IsNotMClass, 16560 CEFBS_IsThumb2_HasDSP, 16561 CEFBS_IsThumb2_HasSB, 16562 CEFBS_IsThumb2_HasTrustZone, 16563 CEFBS_IsThumb2_HasV7, 16564 CEFBS_IsThumb2_HasV8, 16565 CEFBS_IsThumb2_HasVFP2, 16566 CEFBS_IsThumb2_HasVirtualization, 16567 CEFBS_IsThumb2_IsNotMClass, 16568 CEFBS_IsThumb2_PreV8, 16569 CEFBS_PreV8_IsThumb2, 16570 CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, 16571 CEFBS_HasNEON_HasV8_3a_HasFullFP16, 16572 CEFBS_HasV8_HasNEON_HasFullFP16, 16573 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, 16574 CEFBS_IsARM_HasV7_HasMP, 16575 CEFBS_IsARM_HasV8_HasCRC, 16576 CEFBS_IsARM_HasV8_HasV8_1a, 16577 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, 16578 CEFBS_IsThumb_HasV5T_IsNotMClass, 16579 CEFBS_IsThumb2_HasV7_HasMP, 16580 CEFBS_IsThumb2_HasV8_HasCRC, 16581 CEFBS_IsThumb2_HasV8_HasV8_1a, 16582 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, 16583 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, 16584}; 16585 16586static constexpr FeatureBitset FeatureBitsets[] = { 16587 {}, // CEFBS_None 16588 {Feature_Has8MSecExtBit, }, 16589 {Feature_HasDotProdBit, }, 16590 {Feature_HasFP16Bit, }, 16591 {Feature_HasFPARMv8Bit, }, 16592 {Feature_HasFPRegsBit, }, 16593 {Feature_HasFPRegs16Bit, }, 16594 {Feature_HasFPRegs64Bit, }, 16595 {Feature_HasFPRegsV8_1MBit, }, 16596 {Feature_HasFullFP16Bit, }, 16597 {Feature_HasMVEFloatBit, }, 16598 {Feature_HasMVEIntBit, }, 16599 {Feature_HasNEONBit, }, 16600 {Feature_HasV8_1MMainlineBit, }, 16601 {Feature_HasVFP2Bit, }, 16602 {Feature_HasVFP3Bit, }, 16603 {Feature_HasVFP4Bit, }, 16604 {Feature_IsARMBit, }, 16605 {Feature_IsThumbBit, }, 16606 {Feature_IsThumb2Bit, }, 16607 {Feature_HasDSPBit, Feature_IsThumb2Bit, }, 16608 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, 16609 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, 16610 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, 16611 {Feature_HasNEONBit, Feature_HasFP16Bit, }, 16612 {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, 16613 {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 16614 {Feature_HasNEONBit, Feature_HasV8_1aBit, }, 16615 {Feature_HasNEONBit, Feature_HasV8_3aBit, }, 16616 {Feature_HasNEONBit, Feature_HasVFP4Bit, }, 16617 {Feature_HasV8Bit, Feature_HasCryptoBit, }, 16618 {Feature_HasV8Bit, Feature_HasNEONBit, }, 16619 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, 16620 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, 16621 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, 16622 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, 16623 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, 16624 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, 16625 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, 16626 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, 16627 {Feature_IsARMBit, Feature_HasDBBit, }, 16628 {Feature_IsARMBit, Feature_HasDivideInARMBit, }, 16629 {Feature_IsARMBit, Feature_HasSBBit, }, 16630 {Feature_IsARMBit, Feature_HasTrustZoneBit, }, 16631 {Feature_IsARMBit, Feature_HasV4TBit, }, 16632 {Feature_IsARMBit, Feature_HasV5TBit, }, 16633 {Feature_IsARMBit, Feature_HasV5TEBit, }, 16634 {Feature_IsARMBit, Feature_HasV6Bit, }, 16635 {Feature_IsARMBit, Feature_HasV6KBit, }, 16636 {Feature_IsARMBit, Feature_HasV6T2Bit, }, 16637 {Feature_IsARMBit, Feature_HasV7Bit, }, 16638 {Feature_IsARMBit, Feature_HasV8Bit, }, 16639 {Feature_IsARMBit, Feature_HasV8_4aBit, }, 16640 {Feature_IsARMBit, Feature_HasVFP2Bit, }, 16641 {Feature_IsARMBit, Feature_HasVirtualizationBit, }, 16642 {Feature_IsARMBit, Feature_PreV8Bit, }, 16643 {Feature_IsARMBit, Feature_UseNaClTrapBit, }, 16644 {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, 16645 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, 16646 {Feature_IsThumbBit, Feature_HasDBBit, }, 16647 {Feature_IsThumbBit, Feature_HasV5TBit, }, 16648 {Feature_IsThumbBit, Feature_HasV6Bit, }, 16649 {Feature_IsThumbBit, Feature_HasV6MBit, }, 16650 {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, 16651 {Feature_IsThumbBit, Feature_HasV8Bit, }, 16652 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 16653 {Feature_IsThumbBit, Feature_HasV8_4aBit, }, 16654 {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, 16655 {Feature_IsThumbBit, Feature_IsMClassBit, }, 16656 {Feature_IsThumbBit, Feature_IsNotMClassBit, }, 16657 {Feature_IsThumb2Bit, Feature_HasDSPBit, }, 16658 {Feature_IsThumb2Bit, Feature_HasSBBit, }, 16659 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, 16660 {Feature_IsThumb2Bit, Feature_HasV7Bit, }, 16661 {Feature_IsThumb2Bit, Feature_HasV8Bit, }, 16662 {Feature_IsThumb2Bit, Feature_HasVFP2Bit, }, 16663 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, 16664 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, 16665 {Feature_IsThumb2Bit, Feature_PreV8Bit, }, 16666 {Feature_PreV8Bit, Feature_IsThumb2Bit, }, 16667 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, 16668 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, 16669 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, 16670 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 16671 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, 16672 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCRCBit, }, 16673 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 16674 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, 16675 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, 16676 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, 16677 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCRCBit, }, 16678 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, 16679 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, 16680 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, 16681}; 16682#endif // NDEBUG 16683 16684void ARMMCCodeEmitter::verifyInstructionPredicates( 16685 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { 16686#ifndef NDEBUG 16687 static uint8_t RequiredFeaturesRefs[] = { 16688 CEFBS_None, // PHI = 0 16689 CEFBS_None, // INLINEASM = 1 16690 CEFBS_None, // INLINEASM_BR = 2 16691 CEFBS_None, // CFI_INSTRUCTION = 3 16692 CEFBS_None, // EH_LABEL = 4 16693 CEFBS_None, // GC_LABEL = 5 16694 CEFBS_None, // ANNOTATION_LABEL = 6 16695 CEFBS_None, // KILL = 7 16696 CEFBS_None, // EXTRACT_SUBREG = 8 16697 CEFBS_None, // INSERT_SUBREG = 9 16698 CEFBS_None, // IMPLICIT_DEF = 10 16699 CEFBS_None, // SUBREG_TO_REG = 11 16700 CEFBS_None, // COPY_TO_REGCLASS = 12 16701 CEFBS_None, // DBG_VALUE = 13 16702 CEFBS_None, // DBG_LABEL = 14 16703 CEFBS_None, // REG_SEQUENCE = 15 16704 CEFBS_None, // COPY = 16 16705 CEFBS_None, // BUNDLE = 17 16706 CEFBS_None, // LIFETIME_START = 18 16707 CEFBS_None, // LIFETIME_END = 19 16708 CEFBS_None, // STACKMAP = 20 16709 CEFBS_None, // FENTRY_CALL = 21 16710 CEFBS_None, // PATCHPOINT = 22 16711 CEFBS_None, // LOAD_STACK_GUARD = 23 16712 CEFBS_None, // STATEPOINT = 24 16713 CEFBS_None, // LOCAL_ESCAPE = 25 16714 CEFBS_None, // FAULTING_OP = 26 16715 CEFBS_None, // PATCHABLE_OP = 27 16716 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28 16717 CEFBS_None, // PATCHABLE_RET = 29 16718 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30 16719 CEFBS_None, // PATCHABLE_TAIL_CALL = 31 16720 CEFBS_None, // PATCHABLE_EVENT_CALL = 32 16721 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33 16722 CEFBS_None, // ICALL_BRANCH_FUNNEL = 34 16723 CEFBS_None, // G_ADD = 35 16724 CEFBS_None, // G_SUB = 36 16725 CEFBS_None, // G_MUL = 37 16726 CEFBS_None, // G_SDIV = 38 16727 CEFBS_None, // G_UDIV = 39 16728 CEFBS_None, // G_SREM = 40 16729 CEFBS_None, // G_UREM = 41 16730 CEFBS_None, // G_AND = 42 16731 CEFBS_None, // G_OR = 43 16732 CEFBS_None, // G_XOR = 44 16733 CEFBS_None, // G_IMPLICIT_DEF = 45 16734 CEFBS_None, // G_PHI = 46 16735 CEFBS_None, // G_FRAME_INDEX = 47 16736 CEFBS_None, // G_GLOBAL_VALUE = 48 16737 CEFBS_None, // G_EXTRACT = 49 16738 CEFBS_None, // G_UNMERGE_VALUES = 50 16739 CEFBS_None, // G_INSERT = 51 16740 CEFBS_None, // G_MERGE_VALUES = 52 16741 CEFBS_None, // G_BUILD_VECTOR = 53 16742 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54 16743 CEFBS_None, // G_CONCAT_VECTORS = 55 16744 CEFBS_None, // G_PTRTOINT = 56 16745 CEFBS_None, // G_INTTOPTR = 57 16746 CEFBS_None, // G_BITCAST = 58 16747 CEFBS_None, // G_INTRINSIC_TRUNC = 59 16748 CEFBS_None, // G_INTRINSIC_ROUND = 60 16749 CEFBS_None, // G_READCYCLECOUNTER = 61 16750 CEFBS_None, // G_LOAD = 62 16751 CEFBS_None, // G_SEXTLOAD = 63 16752 CEFBS_None, // G_ZEXTLOAD = 64 16753 CEFBS_None, // G_INDEXED_LOAD = 65 16754 CEFBS_None, // G_INDEXED_SEXTLOAD = 66 16755 CEFBS_None, // G_INDEXED_ZEXTLOAD = 67 16756 CEFBS_None, // G_STORE = 68 16757 CEFBS_None, // G_INDEXED_STORE = 69 16758 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70 16759 CEFBS_None, // G_ATOMIC_CMPXCHG = 71 16760 CEFBS_None, // G_ATOMICRMW_XCHG = 72 16761 CEFBS_None, // G_ATOMICRMW_ADD = 73 16762 CEFBS_None, // G_ATOMICRMW_SUB = 74 16763 CEFBS_None, // G_ATOMICRMW_AND = 75 16764 CEFBS_None, // G_ATOMICRMW_NAND = 76 16765 CEFBS_None, // G_ATOMICRMW_OR = 77 16766 CEFBS_None, // G_ATOMICRMW_XOR = 78 16767 CEFBS_None, // G_ATOMICRMW_MAX = 79 16768 CEFBS_None, // G_ATOMICRMW_MIN = 80 16769 CEFBS_None, // G_ATOMICRMW_UMAX = 81 16770 CEFBS_None, // G_ATOMICRMW_UMIN = 82 16771 CEFBS_None, // G_ATOMICRMW_FADD = 83 16772 CEFBS_None, // G_ATOMICRMW_FSUB = 84 16773 CEFBS_None, // G_FENCE = 85 16774 CEFBS_None, // G_BRCOND = 86 16775 CEFBS_None, // G_BRINDIRECT = 87 16776 CEFBS_None, // G_INTRINSIC = 88 16777 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89 16778 CEFBS_None, // G_ANYEXT = 90 16779 CEFBS_None, // G_TRUNC = 91 16780 CEFBS_None, // G_CONSTANT = 92 16781 CEFBS_None, // G_FCONSTANT = 93 16782 CEFBS_None, // G_VASTART = 94 16783 CEFBS_None, // G_VAARG = 95 16784 CEFBS_None, // G_SEXT = 96 16785 CEFBS_None, // G_SEXT_INREG = 97 16786 CEFBS_None, // G_ZEXT = 98 16787 CEFBS_None, // G_SHL = 99 16788 CEFBS_None, // G_LSHR = 100 16789 CEFBS_None, // G_ASHR = 101 16790 CEFBS_None, // G_ICMP = 102 16791 CEFBS_None, // G_FCMP = 103 16792 CEFBS_None, // G_SELECT = 104 16793 CEFBS_None, // G_UADDO = 105 16794 CEFBS_None, // G_UADDE = 106 16795 CEFBS_None, // G_USUBO = 107 16796 CEFBS_None, // G_USUBE = 108 16797 CEFBS_None, // G_SADDO = 109 16798 CEFBS_None, // G_SADDE = 110 16799 CEFBS_None, // G_SSUBO = 111 16800 CEFBS_None, // G_SSUBE = 112 16801 CEFBS_None, // G_UMULO = 113 16802 CEFBS_None, // G_SMULO = 114 16803 CEFBS_None, // G_UMULH = 115 16804 CEFBS_None, // G_SMULH = 116 16805 CEFBS_None, // G_FADD = 117 16806 CEFBS_None, // G_FSUB = 118 16807 CEFBS_None, // G_FMUL = 119 16808 CEFBS_None, // G_FMA = 120 16809 CEFBS_None, // G_FMAD = 121 16810 CEFBS_None, // G_FDIV = 122 16811 CEFBS_None, // G_FREM = 123 16812 CEFBS_None, // G_FPOW = 124 16813 CEFBS_None, // G_FEXP = 125 16814 CEFBS_None, // G_FEXP2 = 126 16815 CEFBS_None, // G_FLOG = 127 16816 CEFBS_None, // G_FLOG2 = 128 16817 CEFBS_None, // G_FLOG10 = 129 16818 CEFBS_None, // G_FNEG = 130 16819 CEFBS_None, // G_FPEXT = 131 16820 CEFBS_None, // G_FPTRUNC = 132 16821 CEFBS_None, // G_FPTOSI = 133 16822 CEFBS_None, // G_FPTOUI = 134 16823 CEFBS_None, // G_SITOFP = 135 16824 CEFBS_None, // G_UITOFP = 136 16825 CEFBS_None, // G_FABS = 137 16826 CEFBS_None, // G_FCOPYSIGN = 138 16827 CEFBS_None, // G_FCANONICALIZE = 139 16828 CEFBS_None, // G_FMINNUM = 140 16829 CEFBS_None, // G_FMAXNUM = 141 16830 CEFBS_None, // G_FMINNUM_IEEE = 142 16831 CEFBS_None, // G_FMAXNUM_IEEE = 143 16832 CEFBS_None, // G_FMINIMUM = 144 16833 CEFBS_None, // G_FMAXIMUM = 145 16834 CEFBS_None, // G_PTR_ADD = 146 16835 CEFBS_None, // G_PTR_MASK = 147 16836 CEFBS_None, // G_SMIN = 148 16837 CEFBS_None, // G_SMAX = 149 16838 CEFBS_None, // G_UMIN = 150 16839 CEFBS_None, // G_UMAX = 151 16840 CEFBS_None, // G_BR = 152 16841 CEFBS_None, // G_BRJT = 153 16842 CEFBS_None, // G_INSERT_VECTOR_ELT = 154 16843 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155 16844 CEFBS_None, // G_SHUFFLE_VECTOR = 156 16845 CEFBS_None, // G_CTTZ = 157 16846 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158 16847 CEFBS_None, // G_CTLZ = 159 16848 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160 16849 CEFBS_None, // G_CTPOP = 161 16850 CEFBS_None, // G_BSWAP = 162 16851 CEFBS_None, // G_BITREVERSE = 163 16852 CEFBS_None, // G_FCEIL = 164 16853 CEFBS_None, // G_FCOS = 165 16854 CEFBS_None, // G_FSIN = 166 16855 CEFBS_None, // G_FSQRT = 167 16856 CEFBS_None, // G_FFLOOR = 168 16857 CEFBS_None, // G_FRINT = 169 16858 CEFBS_None, // G_FNEARBYINT = 170 16859 CEFBS_None, // G_ADDRSPACE_CAST = 171 16860 CEFBS_None, // G_BLOCK_ADDR = 172 16861 CEFBS_None, // G_JUMP_TABLE = 173 16862 CEFBS_None, // G_DYN_STACKALLOC = 174 16863 CEFBS_None, // G_READ_REGISTER = 175 16864 CEFBS_None, // G_WRITE_REGISTER = 176 16865 CEFBS_IsARM, // ABS = 177 16866 CEFBS_IsARM, // ADDSri = 178 16867 CEFBS_IsARM, // ADDSrr = 179 16868 CEFBS_IsARM, // ADDSrsi = 180 16869 CEFBS_IsARM, // ADDSrsr = 181 16870 CEFBS_None, // ADJCALLSTACKDOWN = 182 16871 CEFBS_None, // ADJCALLSTACKUP = 183 16872 CEFBS_IsARM, // ASRi = 184 16873 CEFBS_IsARM, // ASRr = 185 16874 CEFBS_IsARM, // B = 186 16875 CEFBS_None, // BCCZi64 = 187 16876 CEFBS_None, // BCCi64 = 188 16877 CEFBS_IsARM, // BL_PUSHLR = 189 16878 CEFBS_IsARM, // BMOVPCB_CALL = 190 16879 CEFBS_IsARM, // BMOVPCRX_CALL = 191 16880 CEFBS_IsARM, // BR_JTadd = 192 16881 CEFBS_IsARM, // BR_JTm_i12 = 193 16882 CEFBS_IsARM, // BR_JTm_rs = 194 16883 CEFBS_IsARM, // BR_JTr = 195 16884 CEFBS_IsARM_HasV4T, // BX_CALL = 196 16885 CEFBS_None, // CMP_SWAP_16 = 197 16886 CEFBS_None, // CMP_SWAP_32 = 198 16887 CEFBS_None, // CMP_SWAP_64 = 199 16888 CEFBS_None, // CMP_SWAP_8 = 200 16889 CEFBS_None, // CONSTPOOL_ENTRY = 201 16890 CEFBS_None, // COPY_STRUCT_BYVAL_I32 = 202 16891 CEFBS_None, // CompilerBarrier = 203 16892 CEFBS_IsARM, // ITasm = 204 16893 CEFBS_None, // Int_eh_sjlj_dispatchsetup = 205 16894 CEFBS_IsARM, // Int_eh_sjlj_longjmp = 206 16895 CEFBS_IsARM_HasVFP2, // Int_eh_sjlj_setjmp = 207 16896 CEFBS_IsARM, // Int_eh_sjlj_setjmp_nofp = 208 16897 CEFBS_None, // Int_eh_sjlj_setup_dispatch = 209 16898 CEFBS_None, // JUMPTABLE_ADDRS = 210 16899 CEFBS_None, // JUMPTABLE_INSTS = 211 16900 CEFBS_None, // JUMPTABLE_TBB = 212 16901 CEFBS_None, // JUMPTABLE_TBH = 213 16902 CEFBS_IsARM, // LDMIA_RET = 214 16903 CEFBS_IsARM, // LDRBT_POST = 215 16904 CEFBS_IsARM, // LDRConstPool = 216 16905 CEFBS_IsARM, // LDRLIT_ga_abs = 217 16906 CEFBS_IsARM, // LDRLIT_ga_pcrel = 218 16907 CEFBS_IsARM, // LDRLIT_ga_pcrel_ldr = 219 16908 CEFBS_IsARM, // LDRT_POST = 220 16909 CEFBS_IsARM, // LEApcrel = 221 16910 CEFBS_IsARM, // LEApcrelJT = 222 16911 CEFBS_IsARM, // LSLi = 223 16912 CEFBS_IsARM, // LSLr = 224 16913 CEFBS_IsARM, // LSRi = 225 16914 CEFBS_IsARM, // LSRr = 226 16915 CEFBS_None, // MEMCPY = 227 16916 CEFBS_IsARM, // MLAv5 = 228 16917 CEFBS_IsARM, // MOVCCi = 229 16918 CEFBS_IsARM_HasV6T2, // MOVCCi16 = 230 16919 CEFBS_IsARM_HasV6T2, // MOVCCi32imm = 231 16920 CEFBS_IsARM, // MOVCCr = 232 16921 CEFBS_IsARM, // MOVCCsi = 233 16922 CEFBS_IsARM, // MOVCCsr = 234 16923 CEFBS_IsARM, // MOVPCRX = 235 16924 CEFBS_None, // MOVTi16_ga_pcrel = 236 16925 CEFBS_IsARM, // MOV_ga_pcrel = 237 16926 CEFBS_IsARM, // MOV_ga_pcrel_ldr = 238 16927 CEFBS_None, // MOVi16_ga_pcrel = 239 16928 CEFBS_IsARM, // MOVi32imm = 240 16929 CEFBS_IsARM, // MOVsra_flag = 241 16930 CEFBS_IsARM, // MOVsrl_flag = 242 16931 CEFBS_IsARM, // MULv5 = 243 16932 CEFBS_HasMVEInt, // MVE_VANDIZ0v4i32 = 244 16933 CEFBS_HasMVEInt, // MVE_VANDIZ0v8i16 = 245 16934 CEFBS_HasMVEInt, // MVE_VANDIZ16v4i32 = 246 16935 CEFBS_HasMVEInt, // MVE_VANDIZ24v4i32 = 247 16936 CEFBS_HasMVEInt, // MVE_VANDIZ8v4i32 = 248 16937 CEFBS_HasMVEInt, // MVE_VANDIZ8v8i16 = 249 16938 CEFBS_HasMVEInt, // MVE_VORNIZ0v4i32 = 250 16939 CEFBS_HasMVEInt, // MVE_VORNIZ0v8i16 = 251 16940 CEFBS_HasMVEInt, // MVE_VORNIZ16v4i32 = 252 16941 CEFBS_HasMVEInt, // MVE_VORNIZ24v4i32 = 253 16942 CEFBS_HasMVEInt, // MVE_VORNIZ8v4i32 = 254 16943 CEFBS_HasMVEInt, // MVE_VORNIZ8v8i16 = 255 16944 CEFBS_IsARM, // MVNCCi = 256 16945 CEFBS_IsARM, // PICADD = 257 16946 CEFBS_IsARM, // PICLDR = 258 16947 CEFBS_IsARM, // PICLDRB = 259 16948 CEFBS_IsARM, // PICLDRH = 260 16949 CEFBS_IsARM, // PICLDRSB = 261 16950 CEFBS_IsARM, // PICLDRSH = 262 16951 CEFBS_IsARM, // PICSTR = 263 16952 CEFBS_IsARM, // PICSTRB = 264 16953 CEFBS_IsARM, // PICSTRH = 265 16954 CEFBS_IsARM, // RORi = 266 16955 CEFBS_IsARM, // RORr = 267 16956 CEFBS_IsARM, // RRX = 268 16957 CEFBS_IsARM, // RRXi = 269 16958 CEFBS_IsARM, // RSBSri = 270 16959 CEFBS_IsARM, // RSBSrsi = 271 16960 CEFBS_IsARM, // RSBSrsr = 272 16961 CEFBS_IsARM, // SMLALv5 = 273 16962 CEFBS_IsARM, // SMULLv5 = 274 16963 CEFBS_None, // SPACE = 275 16964 CEFBS_IsARM, // STRBT_POST = 276 16965 CEFBS_IsARM, // STRBi_preidx = 277 16966 CEFBS_IsARM, // STRBr_preidx = 278 16967 CEFBS_IsARM, // STRH_preidx = 279 16968 CEFBS_IsARM, // STRT_POST = 280 16969 CEFBS_IsARM, // STRi_preidx = 281 16970 CEFBS_IsARM, // STRr_preidx = 282 16971 CEFBS_IsARM, // SUBS_PC_LR = 283 16972 CEFBS_IsARM, // SUBSri = 284 16973 CEFBS_IsARM, // SUBSrr = 285 16974 CEFBS_IsARM, // SUBSrsi = 286 16975 CEFBS_IsARM, // SUBSrsr = 287 16976 CEFBS_IsARM, // TAILJMPd = 288 16977 CEFBS_IsARM_HasV4T, // TAILJMPr = 289 16978 CEFBS_IsARM, // TAILJMPr4 = 290 16979 CEFBS_None, // TCRETURNdi = 291 16980 CEFBS_None, // TCRETURNri = 292 16981 CEFBS_IsARM, // TPsoft = 293 16982 CEFBS_IsARM, // UMLALv5 = 294 16983 CEFBS_IsARM, // UMULLv5 = 295 16984 CEFBS_HasNEON, // VLD1LNdAsm_16 = 296 16985 CEFBS_HasNEON, // VLD1LNdAsm_32 = 297 16986 CEFBS_HasNEON, // VLD1LNdAsm_8 = 298 16987 CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_16 = 299 16988 CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_32 = 300 16989 CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_8 = 301 16990 CEFBS_HasNEON, // VLD1LNdWB_register_Asm_16 = 302 16991 CEFBS_HasNEON, // VLD1LNdWB_register_Asm_32 = 303 16992 CEFBS_HasNEON, // VLD1LNdWB_register_Asm_8 = 304 16993 CEFBS_HasNEON, // VLD2LNdAsm_16 = 305 16994 CEFBS_HasNEON, // VLD2LNdAsm_32 = 306 16995 CEFBS_HasNEON, // VLD2LNdAsm_8 = 307 16996 CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_16 = 308 16997 CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_32 = 309 16998 CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_8 = 310 16999 CEFBS_HasNEON, // VLD2LNdWB_register_Asm_16 = 311 17000 CEFBS_HasNEON, // VLD2LNdWB_register_Asm_32 = 312 17001 CEFBS_HasNEON, // VLD2LNdWB_register_Asm_8 = 313 17002 CEFBS_HasNEON, // VLD2LNqAsm_16 = 314 17003 CEFBS_HasNEON, // VLD2LNqAsm_32 = 315 17004 CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_16 = 316 17005 CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_32 = 317 17006 CEFBS_HasNEON, // VLD2LNqWB_register_Asm_16 = 318 17007 CEFBS_HasNEON, // VLD2LNqWB_register_Asm_32 = 319 17008 CEFBS_HasNEON, // VLD3DUPdAsm_16 = 320 17009 CEFBS_HasNEON, // VLD3DUPdAsm_32 = 321 17010 CEFBS_HasNEON, // VLD3DUPdAsm_8 = 322 17011 CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_16 = 323 17012 CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_32 = 324 17013 CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_8 = 325 17014 CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_16 = 326 17015 CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_32 = 327 17016 CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_8 = 328 17017 CEFBS_HasNEON, // VLD3DUPqAsm_16 = 329 17018 CEFBS_HasNEON, // VLD3DUPqAsm_32 = 330 17019 CEFBS_HasNEON, // VLD3DUPqAsm_8 = 331 17020 CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_16 = 332 17021 CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_32 = 333 17022 CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_8 = 334 17023 CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_16 = 335 17024 CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_32 = 336 17025 CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_8 = 337 17026 CEFBS_HasNEON, // VLD3LNdAsm_16 = 338 17027 CEFBS_HasNEON, // VLD3LNdAsm_32 = 339 17028 CEFBS_HasNEON, // VLD3LNdAsm_8 = 340 17029 CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_16 = 341 17030 CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_32 = 342 17031 CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_8 = 343 17032 CEFBS_HasNEON, // VLD3LNdWB_register_Asm_16 = 344 17033 CEFBS_HasNEON, // VLD3LNdWB_register_Asm_32 = 345 17034 CEFBS_HasNEON, // VLD3LNdWB_register_Asm_8 = 346 17035 CEFBS_HasNEON, // VLD3LNqAsm_16 = 347 17036 CEFBS_HasNEON, // VLD3LNqAsm_32 = 348 17037 CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_16 = 349 17038 CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_32 = 350 17039 CEFBS_HasNEON, // VLD3LNqWB_register_Asm_16 = 351 17040 CEFBS_HasNEON, // VLD3LNqWB_register_Asm_32 = 352 17041 CEFBS_HasNEON, // VLD3dAsm_16 = 353 17042 CEFBS_HasNEON, // VLD3dAsm_32 = 354 17043 CEFBS_HasNEON, // VLD3dAsm_8 = 355 17044 CEFBS_HasNEON, // VLD3dWB_fixed_Asm_16 = 356 17045 CEFBS_HasNEON, // VLD3dWB_fixed_Asm_32 = 357 17046 CEFBS_HasNEON, // VLD3dWB_fixed_Asm_8 = 358 17047 CEFBS_HasNEON, // VLD3dWB_register_Asm_16 = 359 17048 CEFBS_HasNEON, // VLD3dWB_register_Asm_32 = 360 17049 CEFBS_HasNEON, // VLD3dWB_register_Asm_8 = 361 17050 CEFBS_HasNEON, // VLD3qAsm_16 = 362 17051 CEFBS_HasNEON, // VLD3qAsm_32 = 363 17052 CEFBS_HasNEON, // VLD3qAsm_8 = 364 17053 CEFBS_HasNEON, // VLD3qWB_fixed_Asm_16 = 365 17054 CEFBS_HasNEON, // VLD3qWB_fixed_Asm_32 = 366 17055 CEFBS_HasNEON, // VLD3qWB_fixed_Asm_8 = 367 17056 CEFBS_HasNEON, // VLD3qWB_register_Asm_16 = 368 17057 CEFBS_HasNEON, // VLD3qWB_register_Asm_32 = 369 17058 CEFBS_HasNEON, // VLD3qWB_register_Asm_8 = 370 17059 CEFBS_HasNEON, // VLD4DUPdAsm_16 = 371 17060 CEFBS_HasNEON, // VLD4DUPdAsm_32 = 372 17061 CEFBS_HasNEON, // VLD4DUPdAsm_8 = 373 17062 CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_16 = 374 17063 CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_32 = 375 17064 CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_8 = 376 17065 CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_16 = 377 17066 CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_32 = 378 17067 CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_8 = 379 17068 CEFBS_HasNEON, // VLD4DUPqAsm_16 = 380 17069 CEFBS_HasNEON, // VLD4DUPqAsm_32 = 381 17070 CEFBS_HasNEON, // VLD4DUPqAsm_8 = 382 17071 CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_16 = 383 17072 CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_32 = 384 17073 CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_8 = 385 17074 CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_16 = 386 17075 CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_32 = 387 17076 CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_8 = 388 17077 CEFBS_HasNEON, // VLD4LNdAsm_16 = 389 17078 CEFBS_HasNEON, // VLD4LNdAsm_32 = 390 17079 CEFBS_HasNEON, // VLD4LNdAsm_8 = 391 17080 CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_16 = 392 17081 CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_32 = 393 17082 CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_8 = 394 17083 CEFBS_HasNEON, // VLD4LNdWB_register_Asm_16 = 395 17084 CEFBS_HasNEON, // VLD4LNdWB_register_Asm_32 = 396 17085 CEFBS_HasNEON, // VLD4LNdWB_register_Asm_8 = 397 17086 CEFBS_HasNEON, // VLD4LNqAsm_16 = 398 17087 CEFBS_HasNEON, // VLD4LNqAsm_32 = 399 17088 CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_16 = 400 17089 CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_32 = 401 17090 CEFBS_HasNEON, // VLD4LNqWB_register_Asm_16 = 402 17091 CEFBS_HasNEON, // VLD4LNqWB_register_Asm_32 = 403 17092 CEFBS_HasNEON, // VLD4dAsm_16 = 404 17093 CEFBS_HasNEON, // VLD4dAsm_32 = 405 17094 CEFBS_HasNEON, // VLD4dAsm_8 = 406 17095 CEFBS_HasNEON, // VLD4dWB_fixed_Asm_16 = 407 17096 CEFBS_HasNEON, // VLD4dWB_fixed_Asm_32 = 408 17097 CEFBS_HasNEON, // VLD4dWB_fixed_Asm_8 = 409 17098 CEFBS_HasNEON, // VLD4dWB_register_Asm_16 = 410 17099 CEFBS_HasNEON, // VLD4dWB_register_Asm_32 = 411 17100 CEFBS_HasNEON, // VLD4dWB_register_Asm_8 = 412 17101 CEFBS_HasNEON, // VLD4qAsm_16 = 413 17102 CEFBS_HasNEON, // VLD4qAsm_32 = 414 17103 CEFBS_HasNEON, // VLD4qAsm_8 = 415 17104 CEFBS_HasNEON, // VLD4qWB_fixed_Asm_16 = 416 17105 CEFBS_HasNEON, // VLD4qWB_fixed_Asm_32 = 417 17106 CEFBS_HasNEON, // VLD4qWB_fixed_Asm_8 = 418 17107 CEFBS_HasNEON, // VLD4qWB_register_Asm_16 = 419 17108 CEFBS_HasNEON, // VLD4qWB_register_Asm_32 = 420 17109 CEFBS_HasNEON, // VLD4qWB_register_Asm_8 = 421 17110 CEFBS_None, // VMOVD0 = 422 17111 CEFBS_HasFPRegs64, // VMOVDcc = 423 17112 CEFBS_HasFPRegs, // VMOVHcc = 424 17113 CEFBS_None, // VMOVQ0 = 425 17114 CEFBS_HasFPRegs, // VMOVScc = 426 17115 CEFBS_HasNEON, // VST1LNdAsm_16 = 427 17116 CEFBS_HasNEON, // VST1LNdAsm_32 = 428 17117 CEFBS_HasNEON, // VST1LNdAsm_8 = 429 17118 CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_16 = 430 17119 CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_32 = 431 17120 CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_8 = 432 17121 CEFBS_HasNEON, // VST1LNdWB_register_Asm_16 = 433 17122 CEFBS_HasNEON, // VST1LNdWB_register_Asm_32 = 434 17123 CEFBS_HasNEON, // VST1LNdWB_register_Asm_8 = 435 17124 CEFBS_HasNEON, // VST2LNdAsm_16 = 436 17125 CEFBS_HasNEON, // VST2LNdAsm_32 = 437 17126 CEFBS_HasNEON, // VST2LNdAsm_8 = 438 17127 CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_16 = 439 17128 CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_32 = 440 17129 CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_8 = 441 17130 CEFBS_HasNEON, // VST2LNdWB_register_Asm_16 = 442 17131 CEFBS_HasNEON, // VST2LNdWB_register_Asm_32 = 443 17132 CEFBS_HasNEON, // VST2LNdWB_register_Asm_8 = 444 17133 CEFBS_HasNEON, // VST2LNqAsm_16 = 445 17134 CEFBS_HasNEON, // VST2LNqAsm_32 = 446 17135 CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_16 = 447 17136 CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_32 = 448 17137 CEFBS_HasNEON, // VST2LNqWB_register_Asm_16 = 449 17138 CEFBS_HasNEON, // VST2LNqWB_register_Asm_32 = 450 17139 CEFBS_HasNEON, // VST3LNdAsm_16 = 451 17140 CEFBS_HasNEON, // VST3LNdAsm_32 = 452 17141 CEFBS_HasNEON, // VST3LNdAsm_8 = 453 17142 CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_16 = 454 17143 CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_32 = 455 17144 CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_8 = 456 17145 CEFBS_HasNEON, // VST3LNdWB_register_Asm_16 = 457 17146 CEFBS_HasNEON, // VST3LNdWB_register_Asm_32 = 458 17147 CEFBS_HasNEON, // VST3LNdWB_register_Asm_8 = 459 17148 CEFBS_HasNEON, // VST3LNqAsm_16 = 460 17149 CEFBS_HasNEON, // VST3LNqAsm_32 = 461 17150 CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_16 = 462 17151 CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_32 = 463 17152 CEFBS_HasNEON, // VST3LNqWB_register_Asm_16 = 464 17153 CEFBS_HasNEON, // VST3LNqWB_register_Asm_32 = 465 17154 CEFBS_HasNEON, // VST3dAsm_16 = 466 17155 CEFBS_HasNEON, // VST3dAsm_32 = 467 17156 CEFBS_HasNEON, // VST3dAsm_8 = 468 17157 CEFBS_HasNEON, // VST3dWB_fixed_Asm_16 = 469 17158 CEFBS_HasNEON, // VST3dWB_fixed_Asm_32 = 470 17159 CEFBS_HasNEON, // VST3dWB_fixed_Asm_8 = 471 17160 CEFBS_HasNEON, // VST3dWB_register_Asm_16 = 472 17161 CEFBS_HasNEON, // VST3dWB_register_Asm_32 = 473 17162 CEFBS_HasNEON, // VST3dWB_register_Asm_8 = 474 17163 CEFBS_HasNEON, // VST3qAsm_16 = 475 17164 CEFBS_HasNEON, // VST3qAsm_32 = 476 17165 CEFBS_HasNEON, // VST3qAsm_8 = 477 17166 CEFBS_HasNEON, // VST3qWB_fixed_Asm_16 = 478 17167 CEFBS_HasNEON, // VST3qWB_fixed_Asm_32 = 479 17168 CEFBS_HasNEON, // VST3qWB_fixed_Asm_8 = 480 17169 CEFBS_HasNEON, // VST3qWB_register_Asm_16 = 481 17170 CEFBS_HasNEON, // VST3qWB_register_Asm_32 = 482 17171 CEFBS_HasNEON, // VST3qWB_register_Asm_8 = 483 17172 CEFBS_HasNEON, // VST4LNdAsm_16 = 484 17173 CEFBS_HasNEON, // VST4LNdAsm_32 = 485 17174 CEFBS_HasNEON, // VST4LNdAsm_8 = 486 17175 CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_16 = 487 17176 CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_32 = 488 17177 CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_8 = 489 17178 CEFBS_HasNEON, // VST4LNdWB_register_Asm_16 = 490 17179 CEFBS_HasNEON, // VST4LNdWB_register_Asm_32 = 491 17180 CEFBS_HasNEON, // VST4LNdWB_register_Asm_8 = 492 17181 CEFBS_HasNEON, // VST4LNqAsm_16 = 493 17182 CEFBS_HasNEON, // VST4LNqAsm_32 = 494 17183 CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_16 = 495 17184 CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_32 = 496 17185 CEFBS_HasNEON, // VST4LNqWB_register_Asm_16 = 497 17186 CEFBS_HasNEON, // VST4LNqWB_register_Asm_32 = 498 17187 CEFBS_HasNEON, // VST4dAsm_16 = 499 17188 CEFBS_HasNEON, // VST4dAsm_32 = 500 17189 CEFBS_HasNEON, // VST4dAsm_8 = 501 17190 CEFBS_HasNEON, // VST4dWB_fixed_Asm_16 = 502 17191 CEFBS_HasNEON, // VST4dWB_fixed_Asm_32 = 503 17192 CEFBS_HasNEON, // VST4dWB_fixed_Asm_8 = 504 17193 CEFBS_HasNEON, // VST4dWB_register_Asm_16 = 505 17194 CEFBS_HasNEON, // VST4dWB_register_Asm_32 = 506 17195 CEFBS_HasNEON, // VST4dWB_register_Asm_8 = 507 17196 CEFBS_HasNEON, // VST4qAsm_16 = 508 17197 CEFBS_HasNEON, // VST4qAsm_32 = 509 17198 CEFBS_HasNEON, // VST4qAsm_8 = 510 17199 CEFBS_HasNEON, // VST4qWB_fixed_Asm_16 = 511 17200 CEFBS_HasNEON, // VST4qWB_fixed_Asm_32 = 512 17201 CEFBS_HasNEON, // VST4qWB_fixed_Asm_8 = 513 17202 CEFBS_HasNEON, // VST4qWB_register_Asm_16 = 514 17203 CEFBS_HasNEON, // VST4qWB_register_Asm_32 = 515 17204 CEFBS_HasNEON, // VST4qWB_register_Asm_8 = 516 17205 CEFBS_None, // WIN__CHKSTK = 517 17206 CEFBS_None, // WIN__DBZCHK = 518 17207 CEFBS_IsThumb2, // t2ABS = 519 17208 CEFBS_IsThumb2, // t2ADDSri = 520 17209 CEFBS_IsThumb2, // t2ADDSrr = 521 17210 CEFBS_IsThumb2, // t2ADDSrs = 522 17211 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BF_LabelPseudo = 523 17212 CEFBS_IsThumb_HasV8MBaseline, // t2BR_JT = 524 17213 CEFBS_IsThumb2, // t2DoLoopStart = 525 17214 CEFBS_IsThumb2, // t2LDMIA_RET = 526 17215 CEFBS_IsThumb2, // t2LDRBpcrel = 527 17216 CEFBS_IsThumb2, // t2LDRConstPool = 528 17217 CEFBS_IsThumb2, // t2LDRHpcrel = 529 17218 CEFBS_IsThumb2, // t2LDRSBpcrel = 530 17219 CEFBS_IsThumb2, // t2LDRSHpcrel = 531 17220 CEFBS_IsThumb2, // t2LDRpci_pic = 532 17221 CEFBS_IsThumb2, // t2LDRpcrel = 533 17222 CEFBS_IsThumb2, // t2LEApcrel = 534 17223 CEFBS_IsThumb2, // t2LEApcrelJT = 535 17224 CEFBS_IsThumb2, // t2LoopDec = 536 17225 CEFBS_IsThumb2, // t2LoopEnd = 537 17226 CEFBS_IsThumb2, // t2MOVCCasr = 538 17227 CEFBS_IsThumb2, // t2MOVCCi = 539 17228 CEFBS_IsThumb2, // t2MOVCCi16 = 540 17229 CEFBS_IsThumb2, // t2MOVCCi32imm = 541 17230 CEFBS_IsThumb2, // t2MOVCClsl = 542 17231 CEFBS_IsThumb2, // t2MOVCClsr = 543 17232 CEFBS_IsThumb2, // t2MOVCCr = 544 17233 CEFBS_IsThumb2, // t2MOVCCror = 545 17234 CEFBS_IsThumb2, // t2MOVSsi = 546 17235 CEFBS_IsThumb2, // t2MOVSsr = 547 17236 CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16_ga_pcrel = 548 17237 CEFBS_IsThumb_HasV8MBaseline, // t2MOV_ga_pcrel = 549 17238 CEFBS_None, // t2MOVi16_ga_pcrel = 550 17239 CEFBS_IsThumb, // t2MOVi32imm = 551 17240 CEFBS_IsThumb2, // t2MOVsi = 552 17241 CEFBS_IsThumb2, // t2MOVsr = 553 17242 CEFBS_IsThumb2, // t2MVNCCi = 554 17243 CEFBS_IsThumb2, // t2RSBSri = 555 17244 CEFBS_IsThumb2, // t2RSBSrs = 556 17245 CEFBS_IsThumb2, // t2STRB_preidx = 557 17246 CEFBS_IsThumb2, // t2STRH_preidx = 558 17247 CEFBS_IsThumb2, // t2STR_preidx = 559 17248 CEFBS_IsThumb2, // t2SUBSri = 560 17249 CEFBS_IsThumb2, // t2SUBSrr = 561 17250 CEFBS_IsThumb2, // t2SUBSrs = 562 17251 CEFBS_IsThumb2, // t2TBB_JT = 563 17252 CEFBS_IsThumb2, // t2TBH_JT = 564 17253 CEFBS_IsThumb2, // t2WhileLoopStart = 565 17254 CEFBS_None, // tADCS = 566 17255 CEFBS_None, // tADDSi3 = 567 17256 CEFBS_None, // tADDSi8 = 568 17257 CEFBS_None, // tADDSrr = 569 17258 CEFBS_IsThumb, // tADDframe = 570 17259 CEFBS_IsThumb, // tADJCALLSTACKDOWN = 571 17260 CEFBS_IsThumb, // tADJCALLSTACKUP = 572 17261 CEFBS_IsThumb, // tBL_PUSHLR = 573 17262 CEFBS_IsThumb, // tBRIND = 574 17263 CEFBS_IsThumb, // tBR_JTr = 575 17264 CEFBS_IsThumb, // tBX_CALL = 576 17265 CEFBS_IsThumb, // tBX_RET = 577 17266 CEFBS_IsThumb, // tBX_RET_vararg = 578 17267 CEFBS_IsThumb, // tBfar = 579 17268 CEFBS_IsThumb, // tLDMIA_UPD = 580 17269 CEFBS_IsThumb, // tLDRConstPool = 581 17270 CEFBS_IsThumb, // tLDRLIT_ga_abs = 582 17271 CEFBS_IsThumb, // tLDRLIT_ga_pcrel = 583 17272 CEFBS_IsThumb, // tLDR_postidx = 584 17273 CEFBS_IsThumb, // tLDRpci_pic = 585 17274 CEFBS_IsThumb, // tLEApcrel = 586 17275 CEFBS_IsThumb, // tLEApcrelJT = 587 17276 CEFBS_None, // tLSLSri = 588 17277 CEFBS_None, // tMOVCCr_pseudo = 589 17278 CEFBS_IsThumb, // tPOP_RET = 590 17279 CEFBS_None, // tRSBS = 591 17280 CEFBS_None, // tSBCS = 592 17281 CEFBS_None, // tSUBSi3 = 593 17282 CEFBS_None, // tSUBSi8 = 594 17283 CEFBS_None, // tSUBSrr = 595 17284 CEFBS_IsThumb2, // tTAILJMPd = 596 17285 CEFBS_IsThumb, // tTAILJMPdND = 597 17286 CEFBS_IsThumb, // tTAILJMPr = 598 17287 CEFBS_IsThumb, // tTBB_JT = 599 17288 CEFBS_IsThumb, // tTBH_JT = 600 17289 CEFBS_IsThumb, // tTPsoft = 601 17290 CEFBS_IsARM, // ADCri = 602 17291 CEFBS_IsARM, // ADCrr = 603 17292 CEFBS_IsARM, // ADCrsi = 604 17293 CEFBS_IsARM, // ADCrsr = 605 17294 CEFBS_IsARM, // ADDri = 606 17295 CEFBS_IsARM, // ADDrr = 607 17296 CEFBS_IsARM, // ADDrsi = 608 17297 CEFBS_IsARM, // ADDrsr = 609 17298 CEFBS_IsARM, // ADR = 610 17299 CEFBS_HasV8_HasCrypto, // AESD = 611 17300 CEFBS_HasV8_HasCrypto, // AESE = 612 17301 CEFBS_HasV8_HasCrypto, // AESIMC = 613 17302 CEFBS_HasV8_HasCrypto, // AESMC = 614 17303 CEFBS_IsARM, // ANDri = 615 17304 CEFBS_IsARM, // ANDrr = 616 17305 CEFBS_IsARM, // ANDrsi = 617 17306 CEFBS_IsARM, // ANDrsr = 618 17307 CEFBS_IsARM_HasV6T2, // BFC = 619 17308 CEFBS_IsARM_HasV6T2, // BFI = 620 17309 CEFBS_IsARM, // BICri = 621 17310 CEFBS_IsARM, // BICrr = 622 17311 CEFBS_IsARM, // BICrsi = 623 17312 CEFBS_IsARM, // BICrsr = 624 17313 CEFBS_IsARM, // BKPT = 625 17314 CEFBS_IsARM, // BL = 626 17315 CEFBS_IsARM_HasV5T, // BLX = 627 17316 CEFBS_IsARM_HasV5T, // BLX_pred = 628 17317 CEFBS_IsARM_HasV5T, // BLXi = 629 17318 CEFBS_IsARM, // BL_pred = 630 17319 CEFBS_IsARM_HasV4T, // BX = 631 17320 CEFBS_IsARM, // BXJ = 632 17321 CEFBS_IsARM_HasV4T, // BX_RET = 633 17322 CEFBS_IsARM_HasV4T, // BX_pred = 634 17323 CEFBS_IsARM, // Bcc = 635 17324 CEFBS_IsARM_PreV8, // CDP = 636 17325 CEFBS_IsARM_PreV8, // CDP2 = 637 17326 CEFBS_IsARM_HasV6K, // CLREX = 638 17327 CEFBS_IsARM_HasV5T, // CLZ = 639 17328 CEFBS_IsARM, // CMNri = 640 17329 CEFBS_IsARM, // CMNzrr = 641 17330 CEFBS_IsARM, // CMNzrsi = 642 17331 CEFBS_IsARM, // CMNzrsr = 643 17332 CEFBS_IsARM, // CMPri = 644 17333 CEFBS_IsARM, // CMPrr = 645 17334 CEFBS_IsARM, // CMPrsi = 646 17335 CEFBS_IsARM, // CMPrsr = 647 17336 CEFBS_IsARM, // CPS1p = 648 17337 CEFBS_IsARM, // CPS2p = 649 17338 CEFBS_IsARM, // CPS3p = 650 17339 CEFBS_IsARM_HasV8_HasCRC, // CRC32B = 651 17340 CEFBS_IsARM_HasV8_HasCRC, // CRC32CB = 652 17341 CEFBS_IsARM_HasV8_HasCRC, // CRC32CH = 653 17342 CEFBS_IsARM_HasV8_HasCRC, // CRC32CW = 654 17343 CEFBS_IsARM_HasV8_HasCRC, // CRC32H = 655 17344 CEFBS_IsARM_HasV8_HasCRC, // CRC32W = 656 17345 CEFBS_IsARM_HasV7, // DBG = 657 17346 CEFBS_IsARM_HasDB, // DMB = 658 17347 CEFBS_IsARM_HasDB, // DSB = 659 17348 CEFBS_IsARM, // EORri = 660 17349 CEFBS_IsARM, // EORrr = 661 17350 CEFBS_IsARM, // EORrsi = 662 17351 CEFBS_IsARM, // EORrsr = 663 17352 CEFBS_IsARM_HasVirtualization, // ERET = 664 17353 CEFBS_HasVFP3_HasDPVFP, // FCONSTD = 665 17354 CEFBS_HasFullFP16, // FCONSTH = 666 17355 CEFBS_HasVFP3, // FCONSTS = 667 17356 CEFBS_HasFPRegs, // FLDMXDB_UPD = 668 17357 CEFBS_HasFPRegs, // FLDMXIA = 669 17358 CEFBS_HasFPRegs, // FLDMXIA_UPD = 670 17359 CEFBS_HasFPRegs, // FMSTAT = 671 17360 CEFBS_HasFPRegs, // FSTMXDB_UPD = 672 17361 CEFBS_HasFPRegs, // FSTMXIA = 673 17362 CEFBS_HasFPRegs, // FSTMXIA_UPD = 674 17363 CEFBS_IsARM_HasV6, // HINT = 675 17364 CEFBS_IsARM_HasV8, // HLT = 676 17365 CEFBS_IsARM_HasVirtualization, // HVC = 677 17366 CEFBS_IsARM_HasDB, // ISB = 678 17367 CEFBS_IsARM_HasAcquireRelease, // LDA = 679 17368 CEFBS_IsARM_HasAcquireRelease, // LDAB = 680 17369 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEX = 681 17370 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXB = 682 17371 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXD = 683 17372 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXH = 684 17373 CEFBS_IsARM_HasAcquireRelease, // LDAH = 685 17374 CEFBS_IsARM_PreV8, // LDC2L_OFFSET = 686 17375 CEFBS_IsARM_PreV8, // LDC2L_OPTION = 687 17376 CEFBS_IsARM_PreV8, // LDC2L_POST = 688 17377 CEFBS_IsARM_PreV8, // LDC2L_PRE = 689 17378 CEFBS_IsARM_PreV8, // LDC2_OFFSET = 690 17379 CEFBS_IsARM_PreV8, // LDC2_OPTION = 691 17380 CEFBS_IsARM_PreV8, // LDC2_POST = 692 17381 CEFBS_IsARM_PreV8, // LDC2_PRE = 693 17382 CEFBS_IsARM, // LDCL_OFFSET = 694 17383 CEFBS_IsARM, // LDCL_OPTION = 695 17384 CEFBS_IsARM, // LDCL_POST = 696 17385 CEFBS_IsARM, // LDCL_PRE = 697 17386 CEFBS_IsARM, // LDC_OFFSET = 698 17387 CEFBS_IsARM, // LDC_OPTION = 699 17388 CEFBS_IsARM, // LDC_POST = 700 17389 CEFBS_IsARM, // LDC_PRE = 701 17390 CEFBS_IsARM, // LDMDA = 702 17391 CEFBS_IsARM, // LDMDA_UPD = 703 17392 CEFBS_IsARM, // LDMDB = 704 17393 CEFBS_IsARM, // LDMDB_UPD = 705 17394 CEFBS_IsARM, // LDMIA = 706 17395 CEFBS_IsARM, // LDMIA_UPD = 707 17396 CEFBS_IsARM, // LDMIB = 708 17397 CEFBS_IsARM, // LDMIB_UPD = 709 17398 CEFBS_IsARM, // LDRBT_POST_IMM = 710 17399 CEFBS_IsARM, // LDRBT_POST_REG = 711 17400 CEFBS_IsARM, // LDRB_POST_IMM = 712 17401 CEFBS_IsARM, // LDRB_POST_REG = 713 17402 CEFBS_IsARM, // LDRB_PRE_IMM = 714 17403 CEFBS_IsARM, // LDRB_PRE_REG = 715 17404 CEFBS_IsARM, // LDRBi12 = 716 17405 CEFBS_IsARM, // LDRBrs = 717 17406 CEFBS_IsARM_HasV5TE, // LDRD = 718 17407 CEFBS_IsARM, // LDRD_POST = 719 17408 CEFBS_IsARM, // LDRD_PRE = 720 17409 CEFBS_IsARM, // LDREX = 721 17410 CEFBS_IsARM, // LDREXB = 722 17411 CEFBS_IsARM, // LDREXD = 723 17412 CEFBS_IsARM, // LDREXH = 724 17413 CEFBS_IsARM, // LDRH = 725 17414 CEFBS_IsARM, // LDRHTi = 726 17415 CEFBS_IsARM, // LDRHTr = 727 17416 CEFBS_IsARM, // LDRH_POST = 728 17417 CEFBS_IsARM, // LDRH_PRE = 729 17418 CEFBS_IsARM, // LDRSB = 730 17419 CEFBS_IsARM, // LDRSBTi = 731 17420 CEFBS_IsARM, // LDRSBTr = 732 17421 CEFBS_IsARM, // LDRSB_POST = 733 17422 CEFBS_IsARM, // LDRSB_PRE = 734 17423 CEFBS_IsARM, // LDRSH = 735 17424 CEFBS_IsARM, // LDRSHTi = 736 17425 CEFBS_IsARM, // LDRSHTr = 737 17426 CEFBS_IsARM, // LDRSH_POST = 738 17427 CEFBS_IsARM, // LDRSH_PRE = 739 17428 CEFBS_IsARM, // LDRT_POST_IMM = 740 17429 CEFBS_IsARM, // LDRT_POST_REG = 741 17430 CEFBS_IsARM, // LDR_POST_IMM = 742 17431 CEFBS_IsARM, // LDR_POST_REG = 743 17432 CEFBS_IsARM, // LDR_PRE_IMM = 744 17433 CEFBS_IsARM, // LDR_PRE_REG = 745 17434 CEFBS_IsARM, // LDRcp = 746 17435 CEFBS_IsARM, // LDRi12 = 747 17436 CEFBS_IsARM, // LDRrs = 748 17437 CEFBS_IsARM, // MCR = 749 17438 CEFBS_IsARM_PreV8, // MCR2 = 750 17439 CEFBS_IsARM, // MCRR = 751 17440 CEFBS_IsARM_PreV8, // MCRR2 = 752 17441 CEFBS_IsARM_HasV6, // MLA = 753 17442 CEFBS_IsARM_HasV6T2, // MLS = 754 17443 CEFBS_IsARM, // MOVPCLR = 755 17444 CEFBS_IsARM_HasV6T2, // MOVTi16 = 756 17445 CEFBS_IsARM, // MOVi = 757 17446 CEFBS_IsARM_HasV6T2, // MOVi16 = 758 17447 CEFBS_IsARM, // MOVr = 759 17448 CEFBS_IsARM, // MOVr_TC = 760 17449 CEFBS_IsARM, // MOVsi = 761 17450 CEFBS_IsARM, // MOVsr = 762 17451 CEFBS_IsARM, // MRC = 763 17452 CEFBS_IsARM_PreV8, // MRC2 = 764 17453 CEFBS_IsARM, // MRRC = 765 17454 CEFBS_IsARM_PreV8, // MRRC2 = 766 17455 CEFBS_IsARM, // MRS = 767 17456 CEFBS_IsARM_HasVirtualization, // MRSbanked = 768 17457 CEFBS_IsARM, // MRSsys = 769 17458 CEFBS_IsARM, // MSR = 770 17459 CEFBS_IsARM_HasVirtualization, // MSRbanked = 771 17460 CEFBS_IsARM, // MSRi = 772 17461 CEFBS_IsARM_HasV6, // MUL = 773 17462 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLi = 774 17463 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLr = 775 17464 CEFBS_HasMVEInt, // MVE_DLSTP_16 = 776 17465 CEFBS_HasMVEInt, // MVE_DLSTP_32 = 777 17466 CEFBS_HasMVEInt, // MVE_DLSTP_64 = 778 17467 CEFBS_HasMVEInt, // MVE_DLSTP_8 = 779 17468 CEFBS_HasMVEInt, // MVE_LCTP = 780 17469 CEFBS_HasMVEInt, // MVE_LETP = 781 17470 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLi = 782 17471 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLr = 783 17472 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSRL = 784 17473 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHR = 785 17474 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHRL = 786 17475 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHL = 787 17476 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHLL = 788 17477 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHR = 789 17478 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHRL = 790 17479 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHL = 791 17480 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHLL = 792 17481 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHL = 793 17482 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHLL = 794 17483 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHR = 795 17484 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHRL = 796 17485 CEFBS_HasMVEInt, // MVE_VABAVs16 = 797 17486 CEFBS_HasMVEInt, // MVE_VABAVs32 = 798 17487 CEFBS_HasMVEInt, // MVE_VABAVs8 = 799 17488 CEFBS_HasMVEInt, // MVE_VABAVu16 = 800 17489 CEFBS_HasMVEInt, // MVE_VABAVu32 = 801 17490 CEFBS_HasMVEInt, // MVE_VABAVu8 = 802 17491 CEFBS_HasMVEFloat, // MVE_VABDf16 = 803 17492 CEFBS_HasMVEFloat, // MVE_VABDf32 = 804 17493 CEFBS_HasMVEInt, // MVE_VABDs16 = 805 17494 CEFBS_HasMVEInt, // MVE_VABDs32 = 806 17495 CEFBS_HasMVEInt, // MVE_VABDs8 = 807 17496 CEFBS_HasMVEInt, // MVE_VABDu16 = 808 17497 CEFBS_HasMVEInt, // MVE_VABDu32 = 809 17498 CEFBS_HasMVEInt, // MVE_VABDu8 = 810 17499 CEFBS_HasMVEFloat, // MVE_VABSf16 = 811 17500 CEFBS_HasMVEFloat, // MVE_VABSf32 = 812 17501 CEFBS_HasMVEInt, // MVE_VABSs16 = 813 17502 CEFBS_HasMVEInt, // MVE_VABSs32 = 814 17503 CEFBS_HasMVEInt, // MVE_VABSs8 = 815 17504 CEFBS_HasMVEInt, // MVE_VADC = 816 17505 CEFBS_HasMVEInt, // MVE_VADCI = 817 17506 CEFBS_HasMVEInt, // MVE_VADDLVs32acc = 818 17507 CEFBS_HasMVEInt, // MVE_VADDLVs32no_acc = 819 17508 CEFBS_HasMVEInt, // MVE_VADDLVu32acc = 820 17509 CEFBS_HasMVEInt, // MVE_VADDLVu32no_acc = 821 17510 CEFBS_HasMVEInt, // MVE_VADDVs16acc = 822 17511 CEFBS_HasMVEInt, // MVE_VADDVs16no_acc = 823 17512 CEFBS_HasMVEInt, // MVE_VADDVs32acc = 824 17513 CEFBS_HasMVEInt, // MVE_VADDVs32no_acc = 825 17514 CEFBS_HasMVEInt, // MVE_VADDVs8acc = 826 17515 CEFBS_HasMVEInt, // MVE_VADDVs8no_acc = 827 17516 CEFBS_HasMVEInt, // MVE_VADDVu16acc = 828 17517 CEFBS_HasMVEInt, // MVE_VADDVu16no_acc = 829 17518 CEFBS_HasMVEInt, // MVE_VADDVu32acc = 830 17519 CEFBS_HasMVEInt, // MVE_VADDVu32no_acc = 831 17520 CEFBS_HasMVEInt, // MVE_VADDVu8acc = 832 17521 CEFBS_HasMVEInt, // MVE_VADDVu8no_acc = 833 17522 CEFBS_HasMVEFloat, // MVE_VADD_qr_f16 = 834 17523 CEFBS_HasMVEFloat, // MVE_VADD_qr_f32 = 835 17524 CEFBS_HasMVEInt, // MVE_VADD_qr_i16 = 836 17525 CEFBS_HasMVEInt, // MVE_VADD_qr_i32 = 837 17526 CEFBS_HasMVEInt, // MVE_VADD_qr_i8 = 838 17527 CEFBS_HasMVEFloat, // MVE_VADDf16 = 839 17528 CEFBS_HasMVEFloat, // MVE_VADDf32 = 840 17529 CEFBS_HasMVEInt, // MVE_VADDi16 = 841 17530 CEFBS_HasMVEInt, // MVE_VADDi32 = 842 17531 CEFBS_HasMVEInt, // MVE_VADDi8 = 843 17532 CEFBS_HasMVEInt, // MVE_VAND = 844 17533 CEFBS_HasMVEInt, // MVE_VBIC = 845 17534 CEFBS_HasMVEInt, // MVE_VBICIZ0v4i32 = 846 17535 CEFBS_HasMVEInt, // MVE_VBICIZ0v8i16 = 847 17536 CEFBS_HasMVEInt, // MVE_VBICIZ16v4i32 = 848 17537 CEFBS_HasMVEInt, // MVE_VBICIZ24v4i32 = 849 17538 CEFBS_HasMVEInt, // MVE_VBICIZ8v4i32 = 850 17539 CEFBS_HasMVEInt, // MVE_VBICIZ8v8i16 = 851 17540 CEFBS_HasMVEInt, // MVE_VBRSR16 = 852 17541 CEFBS_HasMVEInt, // MVE_VBRSR32 = 853 17542 CEFBS_HasMVEInt, // MVE_VBRSR8 = 854 17543 CEFBS_HasMVEFloat, // MVE_VCADDf16 = 855 17544 CEFBS_HasMVEFloat, // MVE_VCADDf32 = 856 17545 CEFBS_HasMVEInt, // MVE_VCADDi16 = 857 17546 CEFBS_HasMVEInt, // MVE_VCADDi32 = 858 17547 CEFBS_HasMVEInt, // MVE_VCADDi8 = 859 17548 CEFBS_HasMVEInt, // MVE_VCLSs16 = 860 17549 CEFBS_HasMVEInt, // MVE_VCLSs32 = 861 17550 CEFBS_HasMVEInt, // MVE_VCLSs8 = 862 17551 CEFBS_HasMVEInt, // MVE_VCLZs16 = 863 17552 CEFBS_HasMVEInt, // MVE_VCLZs32 = 864 17553 CEFBS_HasMVEInt, // MVE_VCLZs8 = 865 17554 CEFBS_HasMVEFloat, // MVE_VCMLAf16 = 866 17555 CEFBS_HasMVEFloat, // MVE_VCMLAf32 = 867 17556 CEFBS_HasMVEFloat, // MVE_VCMPf16 = 868 17557 CEFBS_HasMVEFloat, // MVE_VCMPf16r = 869 17558 CEFBS_HasMVEFloat, // MVE_VCMPf32 = 870 17559 CEFBS_HasMVEFloat, // MVE_VCMPf32r = 871 17560 CEFBS_HasMVEInt, // MVE_VCMPi16 = 872 17561 CEFBS_HasMVEInt, // MVE_VCMPi16r = 873 17562 CEFBS_HasMVEInt, // MVE_VCMPi32 = 874 17563 CEFBS_HasMVEInt, // MVE_VCMPi32r = 875 17564 CEFBS_HasMVEInt, // MVE_VCMPi8 = 876 17565 CEFBS_HasMVEInt, // MVE_VCMPi8r = 877 17566 CEFBS_HasMVEInt, // MVE_VCMPs16 = 878 17567 CEFBS_HasMVEInt, // MVE_VCMPs16r = 879 17568 CEFBS_HasMVEInt, // MVE_VCMPs32 = 880 17569 CEFBS_HasMVEInt, // MVE_VCMPs32r = 881 17570 CEFBS_HasMVEInt, // MVE_VCMPs8 = 882 17571 CEFBS_HasMVEInt, // MVE_VCMPs8r = 883 17572 CEFBS_HasMVEInt, // MVE_VCMPu16 = 884 17573 CEFBS_HasMVEInt, // MVE_VCMPu16r = 885 17574 CEFBS_HasMVEInt, // MVE_VCMPu32 = 886 17575 CEFBS_HasMVEInt, // MVE_VCMPu32r = 887 17576 CEFBS_HasMVEInt, // MVE_VCMPu8 = 888 17577 CEFBS_HasMVEInt, // MVE_VCMPu8r = 889 17578 CEFBS_HasMVEFloat, // MVE_VCMULf16 = 890 17579 CEFBS_HasMVEFloat, // MVE_VCMULf32 = 891 17580 CEFBS_HasMVEInt, // MVE_VCTP16 = 892 17581 CEFBS_HasMVEInt, // MVE_VCTP32 = 893 17582 CEFBS_HasMVEInt, // MVE_VCTP64 = 894 17583 CEFBS_HasMVEInt, // MVE_VCTP8 = 895 17584 CEFBS_HasMVEFloat, // MVE_VCVTf16f32bh = 896 17585 CEFBS_HasMVEFloat, // MVE_VCVTf16f32th = 897 17586 CEFBS_HasMVEFloat, // MVE_VCVTf16s16_fix = 898 17587 CEFBS_HasMVEFloat, // MVE_VCVTf16s16n = 899 17588 CEFBS_HasMVEFloat, // MVE_VCVTf16u16_fix = 900 17589 CEFBS_HasMVEFloat, // MVE_VCVTf16u16n = 901 17590 CEFBS_HasMVEFloat, // MVE_VCVTf32f16bh = 902 17591 CEFBS_HasMVEFloat, // MVE_VCVTf32f16th = 903 17592 CEFBS_HasMVEFloat, // MVE_VCVTf32s32_fix = 904 17593 CEFBS_HasMVEFloat, // MVE_VCVTf32s32n = 905 17594 CEFBS_HasMVEFloat, // MVE_VCVTf32u32_fix = 906 17595 CEFBS_HasMVEFloat, // MVE_VCVTf32u32n = 907 17596 CEFBS_HasMVEFloat, // MVE_VCVTs16f16_fix = 908 17597 CEFBS_HasMVEFloat, // MVE_VCVTs16f16a = 909 17598 CEFBS_HasMVEFloat, // MVE_VCVTs16f16m = 910 17599 CEFBS_HasMVEFloat, // MVE_VCVTs16f16n = 911 17600 CEFBS_HasMVEFloat, // MVE_VCVTs16f16p = 912 17601 CEFBS_HasMVEFloat, // MVE_VCVTs16f16z = 913 17602 CEFBS_HasMVEFloat, // MVE_VCVTs32f32_fix = 914 17603 CEFBS_HasMVEFloat, // MVE_VCVTs32f32a = 915 17604 CEFBS_HasMVEFloat, // MVE_VCVTs32f32m = 916 17605 CEFBS_HasMVEFloat, // MVE_VCVTs32f32n = 917 17606 CEFBS_HasMVEFloat, // MVE_VCVTs32f32p = 918 17607 CEFBS_HasMVEFloat, // MVE_VCVTs32f32z = 919 17608 CEFBS_HasMVEFloat, // MVE_VCVTu16f16_fix = 920 17609 CEFBS_HasMVEFloat, // MVE_VCVTu16f16a = 921 17610 CEFBS_HasMVEFloat, // MVE_VCVTu16f16m = 922 17611 CEFBS_HasMVEFloat, // MVE_VCVTu16f16n = 923 17612 CEFBS_HasMVEFloat, // MVE_VCVTu16f16p = 924 17613 CEFBS_HasMVEFloat, // MVE_VCVTu16f16z = 925 17614 CEFBS_HasMVEFloat, // MVE_VCVTu32f32_fix = 926 17615 CEFBS_HasMVEFloat, // MVE_VCVTu32f32a = 927 17616 CEFBS_HasMVEFloat, // MVE_VCVTu32f32m = 928 17617 CEFBS_HasMVEFloat, // MVE_VCVTu32f32n = 929 17618 CEFBS_HasMVEFloat, // MVE_VCVTu32f32p = 930 17619 CEFBS_HasMVEFloat, // MVE_VCVTu32f32z = 931 17620 CEFBS_HasMVEInt, // MVE_VDDUPu16 = 932 17621 CEFBS_HasMVEInt, // MVE_VDDUPu32 = 933 17622 CEFBS_HasMVEInt, // MVE_VDDUPu8 = 934 17623 CEFBS_HasMVEInt, // MVE_VDUP16 = 935 17624 CEFBS_HasMVEInt, // MVE_VDUP32 = 936 17625 CEFBS_HasMVEInt, // MVE_VDUP8 = 937 17626 CEFBS_HasMVEInt, // MVE_VDWDUPu16 = 938 17627 CEFBS_HasMVEInt, // MVE_VDWDUPu32 = 939 17628 CEFBS_HasMVEInt, // MVE_VDWDUPu8 = 940 17629 CEFBS_HasMVEInt, // MVE_VEOR = 941 17630 CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf16 = 942 17631 CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf32 = 943 17632 CEFBS_HasMVEFloat, // MVE_VFMA_qr_f16 = 944 17633 CEFBS_HasMVEFloat, // MVE_VFMA_qr_f32 = 945 17634 CEFBS_HasMVEFloat, // MVE_VFMAf16 = 946 17635 CEFBS_HasMVEFloat, // MVE_VFMAf32 = 947 17636 CEFBS_HasMVEFloat, // MVE_VFMSf16 = 948 17637 CEFBS_HasMVEFloat, // MVE_VFMSf32 = 949 17638 CEFBS_HasMVEInt, // MVE_VHADD_qr_s16 = 950 17639 CEFBS_HasMVEInt, // MVE_VHADD_qr_s32 = 951 17640 CEFBS_HasMVEInt, // MVE_VHADD_qr_s8 = 952 17641 CEFBS_HasMVEInt, // MVE_VHADD_qr_u16 = 953 17642 CEFBS_HasMVEInt, // MVE_VHADD_qr_u32 = 954 17643 CEFBS_HasMVEInt, // MVE_VHADD_qr_u8 = 955 17644 CEFBS_HasMVEInt, // MVE_VHADDs16 = 956 17645 CEFBS_HasMVEInt, // MVE_VHADDs32 = 957 17646 CEFBS_HasMVEInt, // MVE_VHADDs8 = 958 17647 CEFBS_HasMVEInt, // MVE_VHADDu16 = 959 17648 CEFBS_HasMVEInt, // MVE_VHADDu32 = 960 17649 CEFBS_HasMVEInt, // MVE_VHADDu8 = 961 17650 CEFBS_HasMVEInt, // MVE_VHCADDs16 = 962 17651 CEFBS_HasMVEInt, // MVE_VHCADDs32 = 963 17652 CEFBS_HasMVEInt, // MVE_VHCADDs8 = 964 17653 CEFBS_HasMVEInt, // MVE_VHSUB_qr_s16 = 965 17654 CEFBS_HasMVEInt, // MVE_VHSUB_qr_s32 = 966 17655 CEFBS_HasMVEInt, // MVE_VHSUB_qr_s8 = 967 17656 CEFBS_HasMVEInt, // MVE_VHSUB_qr_u16 = 968 17657 CEFBS_HasMVEInt, // MVE_VHSUB_qr_u32 = 969 17658 CEFBS_HasMVEInt, // MVE_VHSUB_qr_u8 = 970 17659 CEFBS_HasMVEInt, // MVE_VHSUBs16 = 971 17660 CEFBS_HasMVEInt, // MVE_VHSUBs32 = 972 17661 CEFBS_HasMVEInt, // MVE_VHSUBs8 = 973 17662 CEFBS_HasMVEInt, // MVE_VHSUBu16 = 974 17663 CEFBS_HasMVEInt, // MVE_VHSUBu32 = 975 17664 CEFBS_HasMVEInt, // MVE_VHSUBu8 = 976 17665 CEFBS_HasMVEInt, // MVE_VIDUPu16 = 977 17666 CEFBS_HasMVEInt, // MVE_VIDUPu32 = 978 17667 CEFBS_HasMVEInt, // MVE_VIDUPu8 = 979 17668 CEFBS_HasMVEInt, // MVE_VIWDUPu16 = 980 17669 CEFBS_HasMVEInt, // MVE_VIWDUPu32 = 981 17670 CEFBS_HasMVEInt, // MVE_VIWDUPu8 = 982 17671 CEFBS_HasMVEInt, // MVE_VLD20_16 = 983 17672 CEFBS_HasMVEInt, // MVE_VLD20_16_wb = 984 17673 CEFBS_HasMVEInt, // MVE_VLD20_32 = 985 17674 CEFBS_HasMVEInt, // MVE_VLD20_32_wb = 986 17675 CEFBS_HasMVEInt, // MVE_VLD20_8 = 987 17676 CEFBS_HasMVEInt, // MVE_VLD20_8_wb = 988 17677 CEFBS_HasMVEInt, // MVE_VLD21_16 = 989 17678 CEFBS_HasMVEInt, // MVE_VLD21_16_wb = 990 17679 CEFBS_HasMVEInt, // MVE_VLD21_32 = 991 17680 CEFBS_HasMVEInt, // MVE_VLD21_32_wb = 992 17681 CEFBS_HasMVEInt, // MVE_VLD21_8 = 993 17682 CEFBS_HasMVEInt, // MVE_VLD21_8_wb = 994 17683 CEFBS_HasMVEInt, // MVE_VLD40_16 = 995 17684 CEFBS_HasMVEInt, // MVE_VLD40_16_wb = 996 17685 CEFBS_HasMVEInt, // MVE_VLD40_32 = 997 17686 CEFBS_HasMVEInt, // MVE_VLD40_32_wb = 998 17687 CEFBS_HasMVEInt, // MVE_VLD40_8 = 999 17688 CEFBS_HasMVEInt, // MVE_VLD40_8_wb = 1000 17689 CEFBS_HasMVEInt, // MVE_VLD41_16 = 1001 17690 CEFBS_HasMVEInt, // MVE_VLD41_16_wb = 1002 17691 CEFBS_HasMVEInt, // MVE_VLD41_32 = 1003 17692 CEFBS_HasMVEInt, // MVE_VLD41_32_wb = 1004 17693 CEFBS_HasMVEInt, // MVE_VLD41_8 = 1005 17694 CEFBS_HasMVEInt, // MVE_VLD41_8_wb = 1006 17695 CEFBS_HasMVEInt, // MVE_VLD42_16 = 1007 17696 CEFBS_HasMVEInt, // MVE_VLD42_16_wb = 1008 17697 CEFBS_HasMVEInt, // MVE_VLD42_32 = 1009 17698 CEFBS_HasMVEInt, // MVE_VLD42_32_wb = 1010 17699 CEFBS_HasMVEInt, // MVE_VLD42_8 = 1011 17700 CEFBS_HasMVEInt, // MVE_VLD42_8_wb = 1012 17701 CEFBS_HasMVEInt, // MVE_VLD43_16 = 1013 17702 CEFBS_HasMVEInt, // MVE_VLD43_16_wb = 1014 17703 CEFBS_HasMVEInt, // MVE_VLD43_32 = 1015 17704 CEFBS_HasMVEInt, // MVE_VLD43_32_wb = 1016 17705 CEFBS_HasMVEInt, // MVE_VLD43_8 = 1017 17706 CEFBS_HasMVEInt, // MVE_VLD43_8_wb = 1018 17707 CEFBS_HasMVEInt, // MVE_VLDRBS16 = 1019 17708 CEFBS_HasMVEInt, // MVE_VLDRBS16_post = 1020 17709 CEFBS_HasMVEInt, // MVE_VLDRBS16_pre = 1021 17710 CEFBS_HasMVEInt, // MVE_VLDRBS16_rq = 1022 17711 CEFBS_HasMVEInt, // MVE_VLDRBS32 = 1023 17712 CEFBS_HasMVEInt, // MVE_VLDRBS32_post = 1024 17713 CEFBS_HasMVEInt, // MVE_VLDRBS32_pre = 1025 17714 CEFBS_HasMVEInt, // MVE_VLDRBS32_rq = 1026 17715 CEFBS_HasMVEInt, // MVE_VLDRBU16 = 1027 17716 CEFBS_HasMVEInt, // MVE_VLDRBU16_post = 1028 17717 CEFBS_HasMVEInt, // MVE_VLDRBU16_pre = 1029 17718 CEFBS_HasMVEInt, // MVE_VLDRBU16_rq = 1030 17719 CEFBS_HasMVEInt, // MVE_VLDRBU32 = 1031 17720 CEFBS_HasMVEInt, // MVE_VLDRBU32_post = 1032 17721 CEFBS_HasMVEInt, // MVE_VLDRBU32_pre = 1033 17722 CEFBS_HasMVEInt, // MVE_VLDRBU32_rq = 1034 17723 CEFBS_HasMVEInt, // MVE_VLDRBU8 = 1035 17724 CEFBS_HasMVEInt, // MVE_VLDRBU8_post = 1036 17725 CEFBS_HasMVEInt, // MVE_VLDRBU8_pre = 1037 17726 CEFBS_HasMVEInt, // MVE_VLDRBU8_rq = 1038 17727 CEFBS_HasMVEInt, // MVE_VLDRDU64_qi = 1039 17728 CEFBS_HasMVEInt, // MVE_VLDRDU64_qi_pre = 1040 17729 CEFBS_HasMVEInt, // MVE_VLDRDU64_rq = 1041 17730 CEFBS_HasMVEInt, // MVE_VLDRDU64_rq_u = 1042 17731 CEFBS_HasMVEInt, // MVE_VLDRHS32 = 1043 17732 CEFBS_HasMVEInt, // MVE_VLDRHS32_post = 1044 17733 CEFBS_HasMVEInt, // MVE_VLDRHS32_pre = 1045 17734 CEFBS_HasMVEInt, // MVE_VLDRHS32_rq = 1046 17735 CEFBS_HasMVEInt, // MVE_VLDRHS32_rq_u = 1047 17736 CEFBS_HasMVEInt, // MVE_VLDRHU16 = 1048 17737 CEFBS_HasMVEInt, // MVE_VLDRHU16_post = 1049 17738 CEFBS_HasMVEInt, // MVE_VLDRHU16_pre = 1050 17739 CEFBS_HasMVEInt, // MVE_VLDRHU16_rq = 1051 17740 CEFBS_HasMVEInt, // MVE_VLDRHU16_rq_u = 1052 17741 CEFBS_HasMVEInt, // MVE_VLDRHU32 = 1053 17742 CEFBS_HasMVEInt, // MVE_VLDRHU32_post = 1054 17743 CEFBS_HasMVEInt, // MVE_VLDRHU32_pre = 1055 17744 CEFBS_HasMVEInt, // MVE_VLDRHU32_rq = 1056 17745 CEFBS_HasMVEInt, // MVE_VLDRHU32_rq_u = 1057 17746 CEFBS_HasMVEInt, // MVE_VLDRWU32 = 1058 17747 CEFBS_HasMVEInt, // MVE_VLDRWU32_post = 1059 17748 CEFBS_HasMVEInt, // MVE_VLDRWU32_pre = 1060 17749 CEFBS_HasMVEInt, // MVE_VLDRWU32_qi = 1061 17750 CEFBS_HasMVEInt, // MVE_VLDRWU32_qi_pre = 1062 17751 CEFBS_HasMVEInt, // MVE_VLDRWU32_rq = 1063 17752 CEFBS_HasMVEInt, // MVE_VLDRWU32_rq_u = 1064 17753 CEFBS_HasMVEInt, // MVE_VMAXAVs16 = 1065 17754 CEFBS_HasMVEInt, // MVE_VMAXAVs32 = 1066 17755 CEFBS_HasMVEInt, // MVE_VMAXAVs8 = 1067 17756 CEFBS_HasMVEInt, // MVE_VMAXAs16 = 1068 17757 CEFBS_HasMVEInt, // MVE_VMAXAs32 = 1069 17758 CEFBS_HasMVEInt, // MVE_VMAXAs8 = 1070 17759 CEFBS_HasMVEFloat, // MVE_VMAXNMAVf16 = 1071 17760 CEFBS_HasMVEFloat, // MVE_VMAXNMAVf32 = 1072 17761 CEFBS_HasMVEFloat, // MVE_VMAXNMAf16 = 1073 17762 CEFBS_HasMVEFloat, // MVE_VMAXNMAf32 = 1074 17763 CEFBS_HasMVEFloat, // MVE_VMAXNMVf16 = 1075 17764 CEFBS_HasMVEFloat, // MVE_VMAXNMVf32 = 1076 17765 CEFBS_HasMVEFloat, // MVE_VMAXNMf16 = 1077 17766 CEFBS_HasMVEFloat, // MVE_VMAXNMf32 = 1078 17767 CEFBS_HasMVEInt, // MVE_VMAXVs16 = 1079 17768 CEFBS_HasMVEInt, // MVE_VMAXVs32 = 1080 17769 CEFBS_HasMVEInt, // MVE_VMAXVs8 = 1081 17770 CEFBS_HasMVEInt, // MVE_VMAXVu16 = 1082 17771 CEFBS_HasMVEInt, // MVE_VMAXVu32 = 1083 17772 CEFBS_HasMVEInt, // MVE_VMAXVu8 = 1084 17773 CEFBS_HasMVEInt, // MVE_VMAXs16 = 1085 17774 CEFBS_HasMVEInt, // MVE_VMAXs32 = 1086 17775 CEFBS_HasMVEInt, // MVE_VMAXs8 = 1087 17776 CEFBS_HasMVEInt, // MVE_VMAXu16 = 1088 17777 CEFBS_HasMVEInt, // MVE_VMAXu32 = 1089 17778 CEFBS_HasMVEInt, // MVE_VMAXu8 = 1090 17779 CEFBS_HasMVEInt, // MVE_VMINAVs16 = 1091 17780 CEFBS_HasMVEInt, // MVE_VMINAVs32 = 1092 17781 CEFBS_HasMVEInt, // MVE_VMINAVs8 = 1093 17782 CEFBS_HasMVEInt, // MVE_VMINAs16 = 1094 17783 CEFBS_HasMVEInt, // MVE_VMINAs32 = 1095 17784 CEFBS_HasMVEInt, // MVE_VMINAs8 = 1096 17785 CEFBS_HasMVEFloat, // MVE_VMINNMAVf16 = 1097 17786 CEFBS_HasMVEFloat, // MVE_VMINNMAVf32 = 1098 17787 CEFBS_HasMVEFloat, // MVE_VMINNMAf16 = 1099 17788 CEFBS_HasMVEFloat, // MVE_VMINNMAf32 = 1100 17789 CEFBS_HasMVEFloat, // MVE_VMINNMVf16 = 1101 17790 CEFBS_HasMVEFloat, // MVE_VMINNMVf32 = 1102 17791 CEFBS_HasMVEFloat, // MVE_VMINNMf16 = 1103 17792 CEFBS_HasMVEFloat, // MVE_VMINNMf32 = 1104 17793 CEFBS_HasMVEInt, // MVE_VMINVs16 = 1105 17794 CEFBS_HasMVEInt, // MVE_VMINVs32 = 1106 17795 CEFBS_HasMVEInt, // MVE_VMINVs8 = 1107 17796 CEFBS_HasMVEInt, // MVE_VMINVu16 = 1108 17797 CEFBS_HasMVEInt, // MVE_VMINVu32 = 1109 17798 CEFBS_HasMVEInt, // MVE_VMINVu8 = 1110 17799 CEFBS_HasMVEInt, // MVE_VMINs16 = 1111 17800 CEFBS_HasMVEInt, // MVE_VMINs32 = 1112 17801 CEFBS_HasMVEInt, // MVE_VMINs8 = 1113 17802 CEFBS_HasMVEInt, // MVE_VMINu16 = 1114 17803 CEFBS_HasMVEInt, // MVE_VMINu32 = 1115 17804 CEFBS_HasMVEInt, // MVE_VMINu8 = 1116 17805 CEFBS_HasMVEInt, // MVE_VMLADAVas16 = 1117 17806 CEFBS_HasMVEInt, // MVE_VMLADAVas32 = 1118 17807 CEFBS_HasMVEInt, // MVE_VMLADAVas8 = 1119 17808 CEFBS_HasMVEInt, // MVE_VMLADAVau16 = 1120 17809 CEFBS_HasMVEInt, // MVE_VMLADAVau32 = 1121 17810 CEFBS_HasMVEInt, // MVE_VMLADAVau8 = 1122 17811 CEFBS_HasMVEInt, // MVE_VMLADAVaxs16 = 1123 17812 CEFBS_HasMVEInt, // MVE_VMLADAVaxs32 = 1124 17813 CEFBS_HasMVEInt, // MVE_VMLADAVaxs8 = 1125 17814 CEFBS_HasMVEInt, // MVE_VMLADAVs16 = 1126 17815 CEFBS_HasMVEInt, // MVE_VMLADAVs32 = 1127 17816 CEFBS_HasMVEInt, // MVE_VMLADAVs8 = 1128 17817 CEFBS_HasMVEInt, // MVE_VMLADAVu16 = 1129 17818 CEFBS_HasMVEInt, // MVE_VMLADAVu32 = 1130 17819 CEFBS_HasMVEInt, // MVE_VMLADAVu8 = 1131 17820 CEFBS_HasMVEInt, // MVE_VMLADAVxs16 = 1132 17821 CEFBS_HasMVEInt, // MVE_VMLADAVxs32 = 1133 17822 CEFBS_HasMVEInt, // MVE_VMLADAVxs8 = 1134 17823 CEFBS_HasMVEInt, // MVE_VMLALDAVas16 = 1135 17824 CEFBS_HasMVEInt, // MVE_VMLALDAVas32 = 1136 17825 CEFBS_HasMVEInt, // MVE_VMLALDAVau16 = 1137 17826 CEFBS_HasMVEInt, // MVE_VMLALDAVau32 = 1138 17827 CEFBS_HasMVEInt, // MVE_VMLALDAVaxs16 = 1139 17828 CEFBS_HasMVEInt, // MVE_VMLALDAVaxs32 = 1140 17829 CEFBS_HasMVEInt, // MVE_VMLALDAVs16 = 1141 17830 CEFBS_HasMVEInt, // MVE_VMLALDAVs32 = 1142 17831 CEFBS_HasMVEInt, // MVE_VMLALDAVu16 = 1143 17832 CEFBS_HasMVEInt, // MVE_VMLALDAVu32 = 1144 17833 CEFBS_HasMVEInt, // MVE_VMLALDAVxs16 = 1145 17834 CEFBS_HasMVEInt, // MVE_VMLALDAVxs32 = 1146 17835 CEFBS_HasMVEInt, // MVE_VMLAS_qr_s16 = 1147 17836 CEFBS_HasMVEInt, // MVE_VMLAS_qr_s32 = 1148 17837 CEFBS_HasMVEInt, // MVE_VMLAS_qr_s8 = 1149 17838 CEFBS_HasMVEInt, // MVE_VMLAS_qr_u16 = 1150 17839 CEFBS_HasMVEInt, // MVE_VMLAS_qr_u32 = 1151 17840 CEFBS_HasMVEInt, // MVE_VMLAS_qr_u8 = 1152 17841 CEFBS_HasMVEInt, // MVE_VMLA_qr_s16 = 1153 17842 CEFBS_HasMVEInt, // MVE_VMLA_qr_s32 = 1154 17843 CEFBS_HasMVEInt, // MVE_VMLA_qr_s8 = 1155 17844 CEFBS_HasMVEInt, // MVE_VMLA_qr_u16 = 1156 17845 CEFBS_HasMVEInt, // MVE_VMLA_qr_u32 = 1157 17846 CEFBS_HasMVEInt, // MVE_VMLA_qr_u8 = 1158 17847 CEFBS_HasMVEInt, // MVE_VMLSDAVas16 = 1159 17848 CEFBS_HasMVEInt, // MVE_VMLSDAVas32 = 1160 17849 CEFBS_HasMVEInt, // MVE_VMLSDAVas8 = 1161 17850 CEFBS_HasMVEInt, // MVE_VMLSDAVaxs16 = 1162 17851 CEFBS_HasMVEInt, // MVE_VMLSDAVaxs32 = 1163 17852 CEFBS_HasMVEInt, // MVE_VMLSDAVaxs8 = 1164 17853 CEFBS_HasMVEInt, // MVE_VMLSDAVs16 = 1165 17854 CEFBS_HasMVEInt, // MVE_VMLSDAVs32 = 1166 17855 CEFBS_HasMVEInt, // MVE_VMLSDAVs8 = 1167 17856 CEFBS_HasMVEInt, // MVE_VMLSDAVxs16 = 1168 17857 CEFBS_HasMVEInt, // MVE_VMLSDAVxs32 = 1169 17858 CEFBS_HasMVEInt, // MVE_VMLSDAVxs8 = 1170 17859 CEFBS_HasMVEInt, // MVE_VMLSLDAVas16 = 1171 17860 CEFBS_HasMVEInt, // MVE_VMLSLDAVas32 = 1172 17861 CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs16 = 1173 17862 CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs32 = 1174 17863 CEFBS_HasMVEInt, // MVE_VMLSLDAVs16 = 1175 17864 CEFBS_HasMVEInt, // MVE_VMLSLDAVs32 = 1176 17865 CEFBS_HasMVEInt, // MVE_VMLSLDAVxs16 = 1177 17866 CEFBS_HasMVEInt, // MVE_VMLSLDAVxs32 = 1178 17867 CEFBS_HasMVEInt, // MVE_VMOVLs16bh = 1179 17868 CEFBS_HasMVEInt, // MVE_VMOVLs16th = 1180 17869 CEFBS_HasMVEInt, // MVE_VMOVLs8bh = 1181 17870 CEFBS_HasMVEInt, // MVE_VMOVLs8th = 1182 17871 CEFBS_HasMVEInt, // MVE_VMOVLu16bh = 1183 17872 CEFBS_HasMVEInt, // MVE_VMOVLu16th = 1184 17873 CEFBS_HasMVEInt, // MVE_VMOVLu8bh = 1185 17874 CEFBS_HasMVEInt, // MVE_VMOVLu8th = 1186 17875 CEFBS_HasMVEInt, // MVE_VMOVNi16bh = 1187 17876 CEFBS_HasMVEInt, // MVE_VMOVNi16th = 1188 17877 CEFBS_HasMVEInt, // MVE_VMOVNi32bh = 1189 17878 CEFBS_HasMVEInt, // MVE_VMOVNi32th = 1190 17879 CEFBS_HasFPRegsV8_1M, // MVE_VMOV_from_lane_32 = 1191 17880 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s16 = 1192 17881 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s8 = 1193 17882 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u16 = 1194 17883 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u8 = 1195 17884 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_q_rr = 1196 17885 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_rr_q = 1197 17886 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_16 = 1198 17887 CEFBS_HasFPRegsV8_1M, // MVE_VMOV_to_lane_32 = 1199 17888 CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_8 = 1200 17889 CEFBS_HasMVEInt, // MVE_VMOVimmf32 = 1201 17890 CEFBS_HasMVEInt, // MVE_VMOVimmi16 = 1202 17891 CEFBS_HasMVEInt, // MVE_VMOVimmi32 = 1203 17892 CEFBS_HasMVEInt, // MVE_VMOVimmi64 = 1204 17893 CEFBS_HasMVEInt, // MVE_VMOVimmi8 = 1205 17894 CEFBS_HasMVEInt, // MVE_VMULHs16 = 1206 17895 CEFBS_HasMVEInt, // MVE_VMULHs32 = 1207 17896 CEFBS_HasMVEInt, // MVE_VMULHs8 = 1208 17897 CEFBS_HasMVEInt, // MVE_VMULHu16 = 1209 17898 CEFBS_HasMVEInt, // MVE_VMULHu32 = 1210 17899 CEFBS_HasMVEInt, // MVE_VMULHu8 = 1211 17900 CEFBS_HasMVEInt, // MVE_VMULLBp16 = 1212 17901 CEFBS_HasMVEInt, // MVE_VMULLBp8 = 1213 17902 CEFBS_HasMVEInt, // MVE_VMULLBs16 = 1214 17903 CEFBS_HasMVEInt, // MVE_VMULLBs32 = 1215 17904 CEFBS_HasMVEInt, // MVE_VMULLBs8 = 1216 17905 CEFBS_HasMVEInt, // MVE_VMULLBu16 = 1217 17906 CEFBS_HasMVEInt, // MVE_VMULLBu32 = 1218 17907 CEFBS_HasMVEInt, // MVE_VMULLBu8 = 1219 17908 CEFBS_HasMVEInt, // MVE_VMULLTp16 = 1220 17909 CEFBS_HasMVEInt, // MVE_VMULLTp8 = 1221 17910 CEFBS_HasMVEInt, // MVE_VMULLTs16 = 1222 17911 CEFBS_HasMVEInt, // MVE_VMULLTs32 = 1223 17912 CEFBS_HasMVEInt, // MVE_VMULLTs8 = 1224 17913 CEFBS_HasMVEInt, // MVE_VMULLTu16 = 1225 17914 CEFBS_HasMVEInt, // MVE_VMULLTu32 = 1226 17915 CEFBS_HasMVEInt, // MVE_VMULLTu8 = 1227 17916 CEFBS_HasMVEFloat, // MVE_VMUL_qr_f16 = 1228 17917 CEFBS_HasMVEFloat, // MVE_VMUL_qr_f32 = 1229 17918 CEFBS_HasMVEInt, // MVE_VMUL_qr_i16 = 1230 17919 CEFBS_HasMVEInt, // MVE_VMUL_qr_i32 = 1231 17920 CEFBS_HasMVEInt, // MVE_VMUL_qr_i8 = 1232 17921 CEFBS_HasMVEFloat, // MVE_VMULf16 = 1233 17922 CEFBS_HasMVEFloat, // MVE_VMULf32 = 1234 17923 CEFBS_HasMVEInt, // MVE_VMULi16 = 1235 17924 CEFBS_HasMVEInt, // MVE_VMULi32 = 1236 17925 CEFBS_HasMVEInt, // MVE_VMULi8 = 1237 17926 CEFBS_HasMVEInt, // MVE_VMVN = 1238 17927 CEFBS_HasMVEInt, // MVE_VMVNimmi16 = 1239 17928 CEFBS_HasMVEInt, // MVE_VMVNimmi32 = 1240 17929 CEFBS_HasMVEFloat, // MVE_VNEGf16 = 1241 17930 CEFBS_HasMVEFloat, // MVE_VNEGf32 = 1242 17931 CEFBS_HasMVEInt, // MVE_VNEGs16 = 1243 17932 CEFBS_HasMVEInt, // MVE_VNEGs32 = 1244 17933 CEFBS_HasMVEInt, // MVE_VNEGs8 = 1245 17934 CEFBS_HasMVEInt, // MVE_VORN = 1246 17935 CEFBS_HasMVEInt, // MVE_VORR = 1247 17936 CEFBS_HasMVEInt, // MVE_VORRIZ0v4i32 = 1248 17937 CEFBS_HasMVEInt, // MVE_VORRIZ0v8i16 = 1249 17938 CEFBS_HasMVEInt, // MVE_VORRIZ16v4i32 = 1250 17939 CEFBS_HasMVEInt, // MVE_VORRIZ24v4i32 = 1251 17940 CEFBS_HasMVEInt, // MVE_VORRIZ8v4i32 = 1252 17941 CEFBS_HasMVEInt, // MVE_VORRIZ8v8i16 = 1253 17942 CEFBS_HasMVEInt, // MVE_VPNOT = 1254 17943 CEFBS_HasMVEInt, // MVE_VPSEL = 1255 17944 CEFBS_HasMVEInt, // MVE_VPST = 1256 17945 CEFBS_HasMVEInt, // MVE_VPTv16i8 = 1257 17946 CEFBS_HasMVEInt, // MVE_VPTv16i8r = 1258 17947 CEFBS_HasMVEInt, // MVE_VPTv16s8 = 1259 17948 CEFBS_HasMVEInt, // MVE_VPTv16s8r = 1260 17949 CEFBS_HasMVEInt, // MVE_VPTv16u8 = 1261 17950 CEFBS_HasMVEInt, // MVE_VPTv16u8r = 1262 17951 CEFBS_HasMVEFloat, // MVE_VPTv4f32 = 1263 17952 CEFBS_HasMVEFloat, // MVE_VPTv4f32r = 1264 17953 CEFBS_HasMVEInt, // MVE_VPTv4i32 = 1265 17954 CEFBS_HasMVEInt, // MVE_VPTv4i32r = 1266 17955 CEFBS_HasMVEInt, // MVE_VPTv4s32 = 1267 17956 CEFBS_HasMVEInt, // MVE_VPTv4s32r = 1268 17957 CEFBS_HasMVEInt, // MVE_VPTv4u32 = 1269 17958 CEFBS_HasMVEInt, // MVE_VPTv4u32r = 1270 17959 CEFBS_HasMVEFloat, // MVE_VPTv8f16 = 1271 17960 CEFBS_HasMVEFloat, // MVE_VPTv8f16r = 1272 17961 CEFBS_HasMVEInt, // MVE_VPTv8i16 = 1273 17962 CEFBS_HasMVEInt, // MVE_VPTv8i16r = 1274 17963 CEFBS_HasMVEInt, // MVE_VPTv8s16 = 1275 17964 CEFBS_HasMVEInt, // MVE_VPTv8s16r = 1276 17965 CEFBS_HasMVEInt, // MVE_VPTv8u16 = 1277 17966 CEFBS_HasMVEInt, // MVE_VPTv8u16r = 1278 17967 CEFBS_HasMVEInt, // MVE_VQABSs16 = 1279 17968 CEFBS_HasMVEInt, // MVE_VQABSs32 = 1280 17969 CEFBS_HasMVEInt, // MVE_VQABSs8 = 1281 17970 CEFBS_HasMVEInt, // MVE_VQADD_qr_s16 = 1282 17971 CEFBS_HasMVEInt, // MVE_VQADD_qr_s32 = 1283 17972 CEFBS_HasMVEInt, // MVE_VQADD_qr_s8 = 1284 17973 CEFBS_HasMVEInt, // MVE_VQADD_qr_u16 = 1285 17974 CEFBS_HasMVEInt, // MVE_VQADD_qr_u32 = 1286 17975 CEFBS_HasMVEInt, // MVE_VQADD_qr_u8 = 1287 17976 CEFBS_HasMVEInt, // MVE_VQADDs16 = 1288 17977 CEFBS_HasMVEInt, // MVE_VQADDs32 = 1289 17978 CEFBS_HasMVEInt, // MVE_VQADDs8 = 1290 17979 CEFBS_HasMVEInt, // MVE_VQADDu16 = 1291 17980 CEFBS_HasMVEInt, // MVE_VQADDu32 = 1292 17981 CEFBS_HasMVEInt, // MVE_VQADDu8 = 1293 17982 CEFBS_HasMVEInt, // MVE_VQDMLADHXs16 = 1294 17983 CEFBS_HasMVEInt, // MVE_VQDMLADHXs32 = 1295 17984 CEFBS_HasMVEInt, // MVE_VQDMLADHXs8 = 1296 17985 CEFBS_HasMVEInt, // MVE_VQDMLADHs16 = 1297 17986 CEFBS_HasMVEInt, // MVE_VQDMLADHs32 = 1298 17987 CEFBS_HasMVEInt, // MVE_VQDMLADHs8 = 1299 17988 CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs16 = 1300 17989 CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs32 = 1301 17990 CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs8 = 1302 17991 CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs16 = 1303 17992 CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs32 = 1304 17993 CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs8 = 1305 17994 CEFBS_HasMVEInt, // MVE_VQDMLSDHXs16 = 1306 17995 CEFBS_HasMVEInt, // MVE_VQDMLSDHXs32 = 1307 17996 CEFBS_HasMVEInt, // MVE_VQDMLSDHXs8 = 1308 17997 CEFBS_HasMVEInt, // MVE_VQDMLSDHs16 = 1309 17998 CEFBS_HasMVEInt, // MVE_VQDMLSDHs32 = 1310 17999 CEFBS_HasMVEInt, // MVE_VQDMLSDHs8 = 1311 18000 CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s16 = 1312 18001 CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s32 = 1313 18002 CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s8 = 1314 18003 CEFBS_HasMVEInt, // MVE_VQDMULHi16 = 1315 18004 CEFBS_HasMVEInt, // MVE_VQDMULHi32 = 1316 18005 CEFBS_HasMVEInt, // MVE_VQDMULHi8 = 1317 18006 CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16bh = 1318 18007 CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16th = 1319 18008 CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32bh = 1320 18009 CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32th = 1321 18010 CEFBS_HasMVEInt, // MVE_VQDMULLs16bh = 1322 18011 CEFBS_HasMVEInt, // MVE_VQDMULLs16th = 1323 18012 CEFBS_HasMVEInt, // MVE_VQDMULLs32bh = 1324 18013 CEFBS_HasMVEInt, // MVE_VQDMULLs32th = 1325 18014 CEFBS_HasMVEInt, // MVE_VQMOVNs16bh = 1326 18015 CEFBS_HasMVEInt, // MVE_VQMOVNs16th = 1327 18016 CEFBS_HasMVEInt, // MVE_VQMOVNs32bh = 1328 18017 CEFBS_HasMVEInt, // MVE_VQMOVNs32th = 1329 18018 CEFBS_HasMVEInt, // MVE_VQMOVNu16bh = 1330 18019 CEFBS_HasMVEInt, // MVE_VQMOVNu16th = 1331 18020 CEFBS_HasMVEInt, // MVE_VQMOVNu32bh = 1332 18021 CEFBS_HasMVEInt, // MVE_VQMOVNu32th = 1333 18022 CEFBS_HasMVEInt, // MVE_VQMOVUNs16bh = 1334 18023 CEFBS_HasMVEInt, // MVE_VQMOVUNs16th = 1335 18024 CEFBS_HasMVEInt, // MVE_VQMOVUNs32bh = 1336 18025 CEFBS_HasMVEInt, // MVE_VQMOVUNs32th = 1337 18026 CEFBS_HasMVEInt, // MVE_VQNEGs16 = 1338 18027 CEFBS_HasMVEInt, // MVE_VQNEGs32 = 1339 18028 CEFBS_HasMVEInt, // MVE_VQNEGs8 = 1340 18029 CEFBS_HasMVEInt, // MVE_VQRDMLADHXs16 = 1341 18030 CEFBS_HasMVEInt, // MVE_VQRDMLADHXs32 = 1342 18031 CEFBS_HasMVEInt, // MVE_VQRDMLADHXs8 = 1343 18032 CEFBS_HasMVEInt, // MVE_VQRDMLADHs16 = 1344 18033 CEFBS_HasMVEInt, // MVE_VQRDMLADHs32 = 1345 18034 CEFBS_HasMVEInt, // MVE_VQRDMLADHs8 = 1346 18035 CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs16 = 1347 18036 CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs32 = 1348 18037 CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs8 = 1349 18038 CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs16 = 1350 18039 CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs32 = 1351 18040 CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs8 = 1352 18041 CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs16 = 1353 18042 CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs32 = 1354 18043 CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs8 = 1355 18044 CEFBS_HasMVEInt, // MVE_VQRDMLSDHs16 = 1356 18045 CEFBS_HasMVEInt, // MVE_VQRDMLSDHs32 = 1357 18046 CEFBS_HasMVEInt, // MVE_VQRDMLSDHs8 = 1358 18047 CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s16 = 1359 18048 CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s32 = 1360 18049 CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s8 = 1361 18050 CEFBS_HasMVEInt, // MVE_VQRDMULHi16 = 1362 18051 CEFBS_HasMVEInt, // MVE_VQRDMULHi32 = 1363 18052 CEFBS_HasMVEInt, // MVE_VQRDMULHi8 = 1364 18053 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs16 = 1365 18054 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs32 = 1366 18055 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs8 = 1367 18056 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu16 = 1368 18057 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu32 = 1369 18058 CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu8 = 1370 18059 CEFBS_HasMVEInt, // MVE_VQRSHL_qrs16 = 1371 18060 CEFBS_HasMVEInt, // MVE_VQRSHL_qrs32 = 1372 18061 CEFBS_HasMVEInt, // MVE_VQRSHL_qrs8 = 1373 18062 CEFBS_HasMVEInt, // MVE_VQRSHL_qru16 = 1374 18063 CEFBS_HasMVEInt, // MVE_VQRSHL_qru32 = 1375 18064 CEFBS_HasMVEInt, // MVE_VQRSHL_qru8 = 1376 18065 CEFBS_HasMVEInt, // MVE_VQRSHRNbhs16 = 1377 18066 CEFBS_HasMVEInt, // MVE_VQRSHRNbhs32 = 1378 18067 CEFBS_HasMVEInt, // MVE_VQRSHRNbhu16 = 1379 18068 CEFBS_HasMVEInt, // MVE_VQRSHRNbhu32 = 1380 18069 CEFBS_HasMVEInt, // MVE_VQRSHRNths16 = 1381 18070 CEFBS_HasMVEInt, // MVE_VQRSHRNths32 = 1382 18071 CEFBS_HasMVEInt, // MVE_VQRSHRNthu16 = 1383 18072 CEFBS_HasMVEInt, // MVE_VQRSHRNthu32 = 1384 18073 CEFBS_HasMVEInt, // MVE_VQRSHRUNs16bh = 1385 18074 CEFBS_HasMVEInt, // MVE_VQRSHRUNs16th = 1386 18075 CEFBS_HasMVEInt, // MVE_VQRSHRUNs32bh = 1387 18076 CEFBS_HasMVEInt, // MVE_VQRSHRUNs32th = 1388 18077 CEFBS_HasMVEInt, // MVE_VQSHLU_imms16 = 1389 18078 CEFBS_HasMVEInt, // MVE_VQSHLU_imms32 = 1390 18079 CEFBS_HasMVEInt, // MVE_VQSHLU_imms8 = 1391 18080 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs16 = 1392 18081 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs32 = 1393 18082 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs8 = 1394 18083 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu16 = 1395 18084 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu32 = 1396 18085 CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu8 = 1397 18086 CEFBS_HasMVEInt, // MVE_VQSHL_qrs16 = 1398 18087 CEFBS_HasMVEInt, // MVE_VQSHL_qrs32 = 1399 18088 CEFBS_HasMVEInt, // MVE_VQSHL_qrs8 = 1400 18089 CEFBS_HasMVEInt, // MVE_VQSHL_qru16 = 1401 18090 CEFBS_HasMVEInt, // MVE_VQSHL_qru32 = 1402 18091 CEFBS_HasMVEInt, // MVE_VQSHL_qru8 = 1403 18092 CEFBS_HasMVEInt, // MVE_VQSHLimms16 = 1404 18093 CEFBS_HasMVEInt, // MVE_VQSHLimms32 = 1405 18094 CEFBS_HasMVEInt, // MVE_VQSHLimms8 = 1406 18095 CEFBS_HasMVEInt, // MVE_VQSHLimmu16 = 1407 18096 CEFBS_HasMVEInt, // MVE_VQSHLimmu32 = 1408 18097 CEFBS_HasMVEInt, // MVE_VQSHLimmu8 = 1409 18098 CEFBS_HasMVEInt, // MVE_VQSHRNbhs16 = 1410 18099 CEFBS_HasMVEInt, // MVE_VQSHRNbhs32 = 1411 18100 CEFBS_HasMVEInt, // MVE_VQSHRNbhu16 = 1412 18101 CEFBS_HasMVEInt, // MVE_VQSHRNbhu32 = 1413 18102 CEFBS_HasMVEInt, // MVE_VQSHRNths16 = 1414 18103 CEFBS_HasMVEInt, // MVE_VQSHRNths32 = 1415 18104 CEFBS_HasMVEInt, // MVE_VQSHRNthu16 = 1416 18105 CEFBS_HasMVEInt, // MVE_VQSHRNthu32 = 1417 18106 CEFBS_HasMVEInt, // MVE_VQSHRUNs16bh = 1418 18107 CEFBS_HasMVEInt, // MVE_VQSHRUNs16th = 1419 18108 CEFBS_HasMVEInt, // MVE_VQSHRUNs32bh = 1420 18109 CEFBS_HasMVEInt, // MVE_VQSHRUNs32th = 1421 18110 CEFBS_HasMVEInt, // MVE_VQSUB_qr_s16 = 1422 18111 CEFBS_HasMVEInt, // MVE_VQSUB_qr_s32 = 1423 18112 CEFBS_HasMVEInt, // MVE_VQSUB_qr_s8 = 1424 18113 CEFBS_HasMVEInt, // MVE_VQSUB_qr_u16 = 1425 18114 CEFBS_HasMVEInt, // MVE_VQSUB_qr_u32 = 1426 18115 CEFBS_HasMVEInt, // MVE_VQSUB_qr_u8 = 1427 18116 CEFBS_HasMVEInt, // MVE_VQSUBs16 = 1428 18117 CEFBS_HasMVEInt, // MVE_VQSUBs32 = 1429 18118 CEFBS_HasMVEInt, // MVE_VQSUBs8 = 1430 18119 CEFBS_HasMVEInt, // MVE_VQSUBu16 = 1431 18120 CEFBS_HasMVEInt, // MVE_VQSUBu32 = 1432 18121 CEFBS_HasMVEInt, // MVE_VQSUBu8 = 1433 18122 CEFBS_HasMVEInt, // MVE_VREV16_8 = 1434 18123 CEFBS_HasMVEInt, // MVE_VREV32_16 = 1435 18124 CEFBS_HasMVEInt, // MVE_VREV32_8 = 1436 18125 CEFBS_HasMVEInt, // MVE_VREV64_16 = 1437 18126 CEFBS_HasMVEInt, // MVE_VREV64_32 = 1438 18127 CEFBS_HasMVEInt, // MVE_VREV64_8 = 1439 18128 CEFBS_HasMVEInt, // MVE_VRHADDs16 = 1440 18129 CEFBS_HasMVEInt, // MVE_VRHADDs32 = 1441 18130 CEFBS_HasMVEInt, // MVE_VRHADDs8 = 1442 18131 CEFBS_HasMVEInt, // MVE_VRHADDu16 = 1443 18132 CEFBS_HasMVEInt, // MVE_VRHADDu32 = 1444 18133 CEFBS_HasMVEInt, // MVE_VRHADDu8 = 1445 18134 CEFBS_HasMVEFloat, // MVE_VRINTf16A = 1446 18135 CEFBS_HasMVEFloat, // MVE_VRINTf16M = 1447 18136 CEFBS_HasMVEFloat, // MVE_VRINTf16N = 1448 18137 CEFBS_HasMVEFloat, // MVE_VRINTf16P = 1449 18138 CEFBS_HasMVEFloat, // MVE_VRINTf16X = 1450 18139 CEFBS_HasMVEFloat, // MVE_VRINTf16Z = 1451 18140 CEFBS_HasMVEFloat, // MVE_VRINTf32A = 1452 18141 CEFBS_HasMVEFloat, // MVE_VRINTf32M = 1453 18142 CEFBS_HasMVEFloat, // MVE_VRINTf32N = 1454 18143 CEFBS_HasMVEFloat, // MVE_VRINTf32P = 1455 18144 CEFBS_HasMVEFloat, // MVE_VRINTf32X = 1456 18145 CEFBS_HasMVEFloat, // MVE_VRINTf32Z = 1457 18146 CEFBS_HasMVEInt, // MVE_VRMLALDAVHas32 = 1458 18147 CEFBS_HasMVEInt, // MVE_VRMLALDAVHau32 = 1459 18148 CEFBS_HasMVEInt, // MVE_VRMLALDAVHaxs32 = 1460 18149 CEFBS_HasMVEInt, // MVE_VRMLALDAVHs32 = 1461 18150 CEFBS_HasMVEInt, // MVE_VRMLALDAVHu32 = 1462 18151 CEFBS_HasMVEInt, // MVE_VRMLALDAVHxs32 = 1463 18152 CEFBS_HasMVEInt, // MVE_VRMLSLDAVHas32 = 1464 18153 CEFBS_HasMVEInt, // MVE_VRMLSLDAVHaxs32 = 1465 18154 CEFBS_HasMVEInt, // MVE_VRMLSLDAVHs32 = 1466 18155 CEFBS_HasMVEInt, // MVE_VRMLSLDAVHxs32 = 1467 18156 CEFBS_HasMVEInt, // MVE_VRMULHs16 = 1468 18157 CEFBS_HasMVEInt, // MVE_VRMULHs32 = 1469 18158 CEFBS_HasMVEInt, // MVE_VRMULHs8 = 1470 18159 CEFBS_HasMVEInt, // MVE_VRMULHu16 = 1471 18160 CEFBS_HasMVEInt, // MVE_VRMULHu32 = 1472 18161 CEFBS_HasMVEInt, // MVE_VRMULHu8 = 1473 18162 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs16 = 1474 18163 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs32 = 1475 18164 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs8 = 1476 18165 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu16 = 1477 18166 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu32 = 1478 18167 CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu8 = 1479 18168 CEFBS_HasMVEInt, // MVE_VRSHL_qrs16 = 1480 18169 CEFBS_HasMVEInt, // MVE_VRSHL_qrs32 = 1481 18170 CEFBS_HasMVEInt, // MVE_VRSHL_qrs8 = 1482 18171 CEFBS_HasMVEInt, // MVE_VRSHL_qru16 = 1483 18172 CEFBS_HasMVEInt, // MVE_VRSHL_qru32 = 1484 18173 CEFBS_HasMVEInt, // MVE_VRSHL_qru8 = 1485 18174 CEFBS_HasMVEInt, // MVE_VRSHRNi16bh = 1486 18175 CEFBS_HasMVEInt, // MVE_VRSHRNi16th = 1487 18176 CEFBS_HasMVEInt, // MVE_VRSHRNi32bh = 1488 18177 CEFBS_HasMVEInt, // MVE_VRSHRNi32th = 1489 18178 CEFBS_HasMVEInt, // MVE_VRSHR_imms16 = 1490 18179 CEFBS_HasMVEInt, // MVE_VRSHR_imms32 = 1491 18180 CEFBS_HasMVEInt, // MVE_VRSHR_imms8 = 1492 18181 CEFBS_HasMVEInt, // MVE_VRSHR_immu16 = 1493 18182 CEFBS_HasMVEInt, // MVE_VRSHR_immu32 = 1494 18183 CEFBS_HasMVEInt, // MVE_VRSHR_immu8 = 1495 18184 CEFBS_HasMVEInt, // MVE_VSBC = 1496 18185 CEFBS_HasMVEInt, // MVE_VSBCI = 1497 18186 CEFBS_HasMVEInt, // MVE_VSHLC = 1498 18187 CEFBS_HasMVEInt, // MVE_VSHLL_imms16bh = 1499 18188 CEFBS_HasMVEInt, // MVE_VSHLL_imms16th = 1500 18189 CEFBS_HasMVEInt, // MVE_VSHLL_imms8bh = 1501 18190 CEFBS_HasMVEInt, // MVE_VSHLL_imms8th = 1502 18191 CEFBS_HasMVEInt, // MVE_VSHLL_immu16bh = 1503 18192 CEFBS_HasMVEInt, // MVE_VSHLL_immu16th = 1504 18193 CEFBS_HasMVEInt, // MVE_VSHLL_immu8bh = 1505 18194 CEFBS_HasMVEInt, // MVE_VSHLL_immu8th = 1506 18195 CEFBS_HasMVEInt, // MVE_VSHLL_lws16bh = 1507 18196 CEFBS_HasMVEInt, // MVE_VSHLL_lws16th = 1508 18197 CEFBS_HasMVEInt, // MVE_VSHLL_lws8bh = 1509 18198 CEFBS_HasMVEInt, // MVE_VSHLL_lws8th = 1510 18199 CEFBS_HasMVEInt, // MVE_VSHLL_lwu16bh = 1511 18200 CEFBS_HasMVEInt, // MVE_VSHLL_lwu16th = 1512 18201 CEFBS_HasMVEInt, // MVE_VSHLL_lwu8bh = 1513 18202 CEFBS_HasMVEInt, // MVE_VSHLL_lwu8th = 1514 18203 CEFBS_HasMVEInt, // MVE_VSHL_by_vecs16 = 1515 18204 CEFBS_HasMVEInt, // MVE_VSHL_by_vecs32 = 1516 18205 CEFBS_HasMVEInt, // MVE_VSHL_by_vecs8 = 1517 18206 CEFBS_HasMVEInt, // MVE_VSHL_by_vecu16 = 1518 18207 CEFBS_HasMVEInt, // MVE_VSHL_by_vecu32 = 1519 18208 CEFBS_HasMVEInt, // MVE_VSHL_by_vecu8 = 1520 18209 CEFBS_HasMVEInt, // MVE_VSHL_immi16 = 1521 18210 CEFBS_HasMVEInt, // MVE_VSHL_immi32 = 1522 18211 CEFBS_HasMVEInt, // MVE_VSHL_immi8 = 1523 18212 CEFBS_HasMVEInt, // MVE_VSHL_qrs16 = 1524 18213 CEFBS_HasMVEInt, // MVE_VSHL_qrs32 = 1525 18214 CEFBS_HasMVEInt, // MVE_VSHL_qrs8 = 1526 18215 CEFBS_HasMVEInt, // MVE_VSHL_qru16 = 1527 18216 CEFBS_HasMVEInt, // MVE_VSHL_qru32 = 1528 18217 CEFBS_HasMVEInt, // MVE_VSHL_qru8 = 1529 18218 CEFBS_HasMVEInt, // MVE_VSHRNi16bh = 1530 18219 CEFBS_HasMVEInt, // MVE_VSHRNi16th = 1531 18220 CEFBS_HasMVEInt, // MVE_VSHRNi32bh = 1532 18221 CEFBS_HasMVEInt, // MVE_VSHRNi32th = 1533 18222 CEFBS_HasMVEInt, // MVE_VSHR_imms16 = 1534 18223 CEFBS_HasMVEInt, // MVE_VSHR_imms32 = 1535 18224 CEFBS_HasMVEInt, // MVE_VSHR_imms8 = 1536 18225 CEFBS_HasMVEInt, // MVE_VSHR_immu16 = 1537 18226 CEFBS_HasMVEInt, // MVE_VSHR_immu32 = 1538 18227 CEFBS_HasMVEInt, // MVE_VSHR_immu8 = 1539 18228 CEFBS_HasMVEInt, // MVE_VSLIimm16 = 1540 18229 CEFBS_HasMVEInt, // MVE_VSLIimm32 = 1541 18230 CEFBS_HasMVEInt, // MVE_VSLIimm8 = 1542 18231 CEFBS_HasMVEInt, // MVE_VSRIimm16 = 1543 18232 CEFBS_HasMVEInt, // MVE_VSRIimm32 = 1544 18233 CEFBS_HasMVEInt, // MVE_VSRIimm8 = 1545 18234 CEFBS_HasMVEInt, // MVE_VST20_16 = 1546 18235 CEFBS_HasMVEInt, // MVE_VST20_16_wb = 1547 18236 CEFBS_HasMVEInt, // MVE_VST20_32 = 1548 18237 CEFBS_HasMVEInt, // MVE_VST20_32_wb = 1549 18238 CEFBS_HasMVEInt, // MVE_VST20_8 = 1550 18239 CEFBS_HasMVEInt, // MVE_VST20_8_wb = 1551 18240 CEFBS_HasMVEInt, // MVE_VST21_16 = 1552 18241 CEFBS_HasMVEInt, // MVE_VST21_16_wb = 1553 18242 CEFBS_HasMVEInt, // MVE_VST21_32 = 1554 18243 CEFBS_HasMVEInt, // MVE_VST21_32_wb = 1555 18244 CEFBS_HasMVEInt, // MVE_VST21_8 = 1556 18245 CEFBS_HasMVEInt, // MVE_VST21_8_wb = 1557 18246 CEFBS_HasMVEInt, // MVE_VST40_16 = 1558 18247 CEFBS_HasMVEInt, // MVE_VST40_16_wb = 1559 18248 CEFBS_HasMVEInt, // MVE_VST40_32 = 1560 18249 CEFBS_HasMVEInt, // MVE_VST40_32_wb = 1561 18250 CEFBS_HasMVEInt, // MVE_VST40_8 = 1562 18251 CEFBS_HasMVEInt, // MVE_VST40_8_wb = 1563 18252 CEFBS_HasMVEInt, // MVE_VST41_16 = 1564 18253 CEFBS_HasMVEInt, // MVE_VST41_16_wb = 1565 18254 CEFBS_HasMVEInt, // MVE_VST41_32 = 1566 18255 CEFBS_HasMVEInt, // MVE_VST41_32_wb = 1567 18256 CEFBS_HasMVEInt, // MVE_VST41_8 = 1568 18257 CEFBS_HasMVEInt, // MVE_VST41_8_wb = 1569 18258 CEFBS_HasMVEInt, // MVE_VST42_16 = 1570 18259 CEFBS_HasMVEInt, // MVE_VST42_16_wb = 1571 18260 CEFBS_HasMVEInt, // MVE_VST42_32 = 1572 18261 CEFBS_HasMVEInt, // MVE_VST42_32_wb = 1573 18262 CEFBS_HasMVEInt, // MVE_VST42_8 = 1574 18263 CEFBS_HasMVEInt, // MVE_VST42_8_wb = 1575 18264 CEFBS_HasMVEInt, // MVE_VST43_16 = 1576 18265 CEFBS_HasMVEInt, // MVE_VST43_16_wb = 1577 18266 CEFBS_HasMVEInt, // MVE_VST43_32 = 1578 18267 CEFBS_HasMVEInt, // MVE_VST43_32_wb = 1579 18268 CEFBS_HasMVEInt, // MVE_VST43_8 = 1580 18269 CEFBS_HasMVEInt, // MVE_VST43_8_wb = 1581 18270 CEFBS_HasMVEInt, // MVE_VSTRB16 = 1582 18271 CEFBS_HasMVEInt, // MVE_VSTRB16_post = 1583 18272 CEFBS_HasMVEInt, // MVE_VSTRB16_pre = 1584 18273 CEFBS_HasMVEInt, // MVE_VSTRB16_rq = 1585 18274 CEFBS_HasMVEInt, // MVE_VSTRB32 = 1586 18275 CEFBS_HasMVEInt, // MVE_VSTRB32_post = 1587 18276 CEFBS_HasMVEInt, // MVE_VSTRB32_pre = 1588 18277 CEFBS_HasMVEInt, // MVE_VSTRB32_rq = 1589 18278 CEFBS_HasMVEInt, // MVE_VSTRB8_rq = 1590 18279 CEFBS_HasMVEInt, // MVE_VSTRBU8 = 1591 18280 CEFBS_HasMVEInt, // MVE_VSTRBU8_post = 1592 18281 CEFBS_HasMVEInt, // MVE_VSTRBU8_pre = 1593 18282 CEFBS_HasMVEInt, // MVE_VSTRD64_qi = 1594 18283 CEFBS_HasMVEInt, // MVE_VSTRD64_qi_pre = 1595 18284 CEFBS_HasMVEInt, // MVE_VSTRD64_rq = 1596 18285 CEFBS_HasMVEInt, // MVE_VSTRD64_rq_u = 1597 18286 CEFBS_HasMVEInt, // MVE_VSTRH16_rq = 1598 18287 CEFBS_HasMVEInt, // MVE_VSTRH16_rq_u = 1599 18288 CEFBS_HasMVEInt, // MVE_VSTRH32 = 1600 18289 CEFBS_HasMVEInt, // MVE_VSTRH32_post = 1601 18290 CEFBS_HasMVEInt, // MVE_VSTRH32_pre = 1602 18291 CEFBS_HasMVEInt, // MVE_VSTRH32_rq = 1603 18292 CEFBS_HasMVEInt, // MVE_VSTRH32_rq_u = 1604 18293 CEFBS_HasMVEInt, // MVE_VSTRHU16 = 1605 18294 CEFBS_HasMVEInt, // MVE_VSTRHU16_post = 1606 18295 CEFBS_HasMVEInt, // MVE_VSTRHU16_pre = 1607 18296 CEFBS_HasMVEInt, // MVE_VSTRW32_qi = 1608 18297 CEFBS_HasMVEInt, // MVE_VSTRW32_qi_pre = 1609 18298 CEFBS_HasMVEInt, // MVE_VSTRW32_rq = 1610 18299 CEFBS_HasMVEInt, // MVE_VSTRW32_rq_u = 1611 18300 CEFBS_HasMVEInt, // MVE_VSTRWU32 = 1612 18301 CEFBS_HasMVEInt, // MVE_VSTRWU32_post = 1613 18302 CEFBS_HasMVEInt, // MVE_VSTRWU32_pre = 1614 18303 CEFBS_HasMVEFloat, // MVE_VSUB_qr_f16 = 1615 18304 CEFBS_HasMVEFloat, // MVE_VSUB_qr_f32 = 1616 18305 CEFBS_HasMVEInt, // MVE_VSUB_qr_i16 = 1617 18306 CEFBS_HasMVEInt, // MVE_VSUB_qr_i32 = 1618 18307 CEFBS_HasMVEInt, // MVE_VSUB_qr_i8 = 1619 18308 CEFBS_HasMVEFloat, // MVE_VSUBf16 = 1620 18309 CEFBS_HasMVEFloat, // MVE_VSUBf32 = 1621 18310 CEFBS_HasMVEInt, // MVE_VSUBi16 = 1622 18311 CEFBS_HasMVEInt, // MVE_VSUBi32 = 1623 18312 CEFBS_HasMVEInt, // MVE_VSUBi8 = 1624 18313 CEFBS_HasMVEInt, // MVE_WLSTP_16 = 1625 18314 CEFBS_HasMVEInt, // MVE_WLSTP_32 = 1626 18315 CEFBS_HasMVEInt, // MVE_WLSTP_64 = 1627 18316 CEFBS_HasMVEInt, // MVE_WLSTP_8 = 1628 18317 CEFBS_IsARM, // MVNi = 1629 18318 CEFBS_IsARM, // MVNr = 1630 18319 CEFBS_IsARM, // MVNsi = 1631 18320 CEFBS_IsARM, // MVNsr = 1632 18321 CEFBS_HasV8_HasNEON, // NEON_VMAXNMNDf = 1633 18322 CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMAXNMNDh = 1634 18323 CEFBS_HasV8_HasNEON, // NEON_VMAXNMNQf = 1635 18324 CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMAXNMNQh = 1636 18325 CEFBS_HasV8_HasNEON, // NEON_VMINNMNDf = 1637 18326 CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMINNMNDh = 1638 18327 CEFBS_HasV8_HasNEON, // NEON_VMINNMNQf = 1639 18328 CEFBS_HasV8_HasNEON_HasFullFP16, // NEON_VMINNMNQh = 1640 18329 CEFBS_IsARM, // ORRri = 1641 18330 CEFBS_IsARM, // ORRrr = 1642 18331 CEFBS_IsARM, // ORRrsi = 1643 18332 CEFBS_IsARM, // ORRrsr = 1644 18333 CEFBS_IsARM_HasV6, // PKHBT = 1645 18334 CEFBS_IsARM_HasV6, // PKHTB = 1646 18335 CEFBS_IsARM_HasV7_HasMP, // PLDWi12 = 1647 18336 CEFBS_IsARM_HasV7_HasMP, // PLDWrs = 1648 18337 CEFBS_IsARM, // PLDi12 = 1649 18338 CEFBS_IsARM, // PLDrs = 1650 18339 CEFBS_IsARM_HasV7, // PLIi12 = 1651 18340 CEFBS_IsARM_HasV7, // PLIrs = 1652 18341 CEFBS_IsARM, // QADD = 1653 18342 CEFBS_IsARM, // QADD16 = 1654 18343 CEFBS_IsARM, // QADD8 = 1655 18344 CEFBS_IsARM, // QASX = 1656 18345 CEFBS_IsARM, // QDADD = 1657 18346 CEFBS_IsARM, // QDSUB = 1658 18347 CEFBS_IsARM, // QSAX = 1659 18348 CEFBS_IsARM, // QSUB = 1660 18349 CEFBS_IsARM, // QSUB16 = 1661 18350 CEFBS_IsARM, // QSUB8 = 1662 18351 CEFBS_IsARM_HasV6T2, // RBIT = 1663 18352 CEFBS_IsARM_HasV6, // REV = 1664 18353 CEFBS_IsARM_HasV6, // REV16 = 1665 18354 CEFBS_IsARM_HasV6, // REVSH = 1666 18355 CEFBS_IsARM, // RFEDA = 1667 18356 CEFBS_IsARM, // RFEDA_UPD = 1668 18357 CEFBS_IsARM, // RFEDB = 1669 18358 CEFBS_IsARM, // RFEDB_UPD = 1670 18359 CEFBS_IsARM, // RFEIA = 1671 18360 CEFBS_IsARM, // RFEIA_UPD = 1672 18361 CEFBS_IsARM, // RFEIB = 1673 18362 CEFBS_IsARM, // RFEIB_UPD = 1674 18363 CEFBS_IsARM, // RSBri = 1675 18364 CEFBS_IsARM, // RSBrr = 1676 18365 CEFBS_IsARM, // RSBrsi = 1677 18366 CEFBS_IsARM, // RSBrsr = 1678 18367 CEFBS_IsARM, // RSCri = 1679 18368 CEFBS_IsARM, // RSCrr = 1680 18369 CEFBS_IsARM, // RSCrsi = 1681 18370 CEFBS_IsARM, // RSCrsr = 1682 18371 CEFBS_IsARM, // SADD16 = 1683 18372 CEFBS_IsARM, // SADD8 = 1684 18373 CEFBS_IsARM, // SASX = 1685 18374 CEFBS_IsARM_HasSB, // SB = 1686 18375 CEFBS_IsARM, // SBCri = 1687 18376 CEFBS_IsARM, // SBCrr = 1688 18377 CEFBS_IsARM, // SBCrsi = 1689 18378 CEFBS_IsARM, // SBCrsr = 1690 18379 CEFBS_IsARM_HasV6T2, // SBFX = 1691 18380 CEFBS_IsARM_HasDivideInARM, // SDIV = 1692 18381 CEFBS_IsARM_HasV6, // SEL = 1693 18382 CEFBS_IsARM, // SETEND = 1694 18383 CEFBS_IsARM_HasV8_HasV8_1a, // SETPAN = 1695 18384 CEFBS_HasV8_HasCrypto, // SHA1C = 1696 18385 CEFBS_HasV8_HasCrypto, // SHA1H = 1697 18386 CEFBS_HasV8_HasCrypto, // SHA1M = 1698 18387 CEFBS_HasV8_HasCrypto, // SHA1P = 1699 18388 CEFBS_HasV8_HasCrypto, // SHA1SU0 = 1700 18389 CEFBS_HasV8_HasCrypto, // SHA1SU1 = 1701 18390 CEFBS_HasV8_HasCrypto, // SHA256H = 1702 18391 CEFBS_HasV8_HasCrypto, // SHA256H2 = 1703 18392 CEFBS_HasV8_HasCrypto, // SHA256SU0 = 1704 18393 CEFBS_HasV8_HasCrypto, // SHA256SU1 = 1705 18394 CEFBS_IsARM, // SHADD16 = 1706 18395 CEFBS_IsARM, // SHADD8 = 1707 18396 CEFBS_IsARM, // SHASX = 1708 18397 CEFBS_IsARM, // SHSAX = 1709 18398 CEFBS_IsARM, // SHSUB16 = 1710 18399 CEFBS_IsARM, // SHSUB8 = 1711 18400 CEFBS_IsARM_HasTrustZone, // SMC = 1712 18401 CEFBS_IsARM_HasV5TE, // SMLABB = 1713 18402 CEFBS_IsARM_HasV5TE, // SMLABT = 1714 18403 CEFBS_IsARM_HasV6, // SMLAD = 1715 18404 CEFBS_IsARM_HasV6, // SMLADX = 1716 18405 CEFBS_IsARM_HasV6, // SMLAL = 1717 18406 CEFBS_IsARM_HasV5TE, // SMLALBB = 1718 18407 CEFBS_IsARM_HasV5TE, // SMLALBT = 1719 18408 CEFBS_IsARM_HasV6, // SMLALD = 1720 18409 CEFBS_IsARM_HasV6, // SMLALDX = 1721 18410 CEFBS_IsARM_HasV5TE, // SMLALTB = 1722 18411 CEFBS_IsARM_HasV5TE, // SMLALTT = 1723 18412 CEFBS_IsARM_HasV5TE, // SMLATB = 1724 18413 CEFBS_IsARM_HasV5TE, // SMLATT = 1725 18414 CEFBS_IsARM_HasV5TE, // SMLAWB = 1726 18415 CEFBS_IsARM_HasV5TE, // SMLAWT = 1727 18416 CEFBS_IsARM_HasV6, // SMLSD = 1728 18417 CEFBS_IsARM_HasV6, // SMLSDX = 1729 18418 CEFBS_IsARM_HasV6, // SMLSLD = 1730 18419 CEFBS_IsARM_HasV6, // SMLSLDX = 1731 18420 CEFBS_IsARM_HasV6, // SMMLA = 1732 18421 CEFBS_IsARM_HasV6, // SMMLAR = 1733 18422 CEFBS_IsARM_HasV6, // SMMLS = 1734 18423 CEFBS_IsARM_HasV6, // SMMLSR = 1735 18424 CEFBS_IsARM_HasV6, // SMMUL = 1736 18425 CEFBS_IsARM_HasV6, // SMMULR = 1737 18426 CEFBS_IsARM_HasV6, // SMUAD = 1738 18427 CEFBS_IsARM_HasV6, // SMUADX = 1739 18428 CEFBS_IsARM_HasV5TE, // SMULBB = 1740 18429 CEFBS_IsARM_HasV5TE, // SMULBT = 1741 18430 CEFBS_IsARM_HasV6, // SMULL = 1742 18431 CEFBS_IsARM_HasV5TE, // SMULTB = 1743 18432 CEFBS_IsARM_HasV5TE, // SMULTT = 1744 18433 CEFBS_IsARM_HasV5TE, // SMULWB = 1745 18434 CEFBS_IsARM_HasV5TE, // SMULWT = 1746 18435 CEFBS_IsARM_HasV6, // SMUSD = 1747 18436 CEFBS_IsARM_HasV6, // SMUSDX = 1748 18437 CEFBS_IsARM, // SRSDA = 1749 18438 CEFBS_IsARM, // SRSDA_UPD = 1750 18439 CEFBS_IsARM, // SRSDB = 1751 18440 CEFBS_IsARM, // SRSDB_UPD = 1752 18441 CEFBS_IsARM, // SRSIA = 1753 18442 CEFBS_IsARM, // SRSIA_UPD = 1754 18443 CEFBS_IsARM, // SRSIB = 1755 18444 CEFBS_IsARM, // SRSIB_UPD = 1756 18445 CEFBS_IsARM_HasV6, // SSAT = 1757 18446 CEFBS_IsARM_HasV6, // SSAT16 = 1758 18447 CEFBS_IsARM, // SSAX = 1759 18448 CEFBS_IsARM, // SSUB16 = 1760 18449 CEFBS_IsARM, // SSUB8 = 1761 18450 CEFBS_IsARM_PreV8, // STC2L_OFFSET = 1762 18451 CEFBS_IsARM_PreV8, // STC2L_OPTION = 1763 18452 CEFBS_IsARM_PreV8, // STC2L_POST = 1764 18453 CEFBS_IsARM_PreV8, // STC2L_PRE = 1765 18454 CEFBS_IsARM_PreV8, // STC2_OFFSET = 1766 18455 CEFBS_IsARM_PreV8, // STC2_OPTION = 1767 18456 CEFBS_IsARM_PreV8, // STC2_POST = 1768 18457 CEFBS_IsARM_PreV8, // STC2_PRE = 1769 18458 CEFBS_IsARM, // STCL_OFFSET = 1770 18459 CEFBS_IsARM, // STCL_OPTION = 1771 18460 CEFBS_IsARM, // STCL_POST = 1772 18461 CEFBS_IsARM, // STCL_PRE = 1773 18462 CEFBS_IsARM, // STC_OFFSET = 1774 18463 CEFBS_IsARM, // STC_OPTION = 1775 18464 CEFBS_IsARM, // STC_POST = 1776 18465 CEFBS_IsARM, // STC_PRE = 1777 18466 CEFBS_IsARM_HasAcquireRelease, // STL = 1778 18467 CEFBS_IsARM_HasAcquireRelease, // STLB = 1779 18468 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEX = 1780 18469 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXB = 1781 18470 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXD = 1782 18471 CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXH = 1783 18472 CEFBS_IsARM_HasAcquireRelease, // STLH = 1784 18473 CEFBS_IsARM, // STMDA = 1785 18474 CEFBS_IsARM, // STMDA_UPD = 1786 18475 CEFBS_IsARM, // STMDB = 1787 18476 CEFBS_IsARM, // STMDB_UPD = 1788 18477 CEFBS_IsARM, // STMIA = 1789 18478 CEFBS_IsARM, // STMIA_UPD = 1790 18479 CEFBS_IsARM, // STMIB = 1791 18480 CEFBS_IsARM, // STMIB_UPD = 1792 18481 CEFBS_IsARM, // STRBT_POST_IMM = 1793 18482 CEFBS_IsARM, // STRBT_POST_REG = 1794 18483 CEFBS_IsARM, // STRB_POST_IMM = 1795 18484 CEFBS_IsARM, // STRB_POST_REG = 1796 18485 CEFBS_IsARM, // STRB_PRE_IMM = 1797 18486 CEFBS_IsARM, // STRB_PRE_REG = 1798 18487 CEFBS_IsARM, // STRBi12 = 1799 18488 CEFBS_IsARM, // STRBrs = 1800 18489 CEFBS_IsARM_HasV5TE, // STRD = 1801 18490 CEFBS_IsARM, // STRD_POST = 1802 18491 CEFBS_IsARM, // STRD_PRE = 1803 18492 CEFBS_IsARM, // STREX = 1804 18493 CEFBS_IsARM, // STREXB = 1805 18494 CEFBS_IsARM, // STREXD = 1806 18495 CEFBS_IsARM, // STREXH = 1807 18496 CEFBS_IsARM, // STRH = 1808 18497 CEFBS_IsARM, // STRHTi = 1809 18498 CEFBS_IsARM, // STRHTr = 1810 18499 CEFBS_IsARM, // STRH_POST = 1811 18500 CEFBS_IsARM, // STRH_PRE = 1812 18501 CEFBS_IsARM, // STRT_POST_IMM = 1813 18502 CEFBS_IsARM, // STRT_POST_REG = 1814 18503 CEFBS_IsARM, // STR_POST_IMM = 1815 18504 CEFBS_IsARM, // STR_POST_REG = 1816 18505 CEFBS_IsARM, // STR_PRE_IMM = 1817 18506 CEFBS_IsARM, // STR_PRE_REG = 1818 18507 CEFBS_IsARM, // STRi12 = 1819 18508 CEFBS_IsARM, // STRrs = 1820 18509 CEFBS_IsARM, // SUBri = 1821 18510 CEFBS_IsARM, // SUBrr = 1822 18511 CEFBS_IsARM, // SUBrsi = 1823 18512 CEFBS_IsARM, // SUBrsr = 1824 18513 CEFBS_IsARM, // SVC = 1825 18514 CEFBS_IsARM_PreV8, // SWP = 1826 18515 CEFBS_IsARM_PreV8, // SWPB = 1827 18516 CEFBS_IsARM_HasV6, // SXTAB = 1828 18517 CEFBS_IsARM_HasV6, // SXTAB16 = 1829 18518 CEFBS_IsARM_HasV6, // SXTAH = 1830 18519 CEFBS_IsARM_HasV6, // SXTB = 1831 18520 CEFBS_IsARM_HasV6, // SXTB16 = 1832 18521 CEFBS_IsARM_HasV6, // SXTH = 1833 18522 CEFBS_IsARM, // TEQri = 1834 18523 CEFBS_IsARM, // TEQrr = 1835 18524 CEFBS_IsARM, // TEQrsi = 1836 18525 CEFBS_IsARM, // TEQrsr = 1837 18526 CEFBS_IsARM, // TRAP = 1838 18527 CEFBS_IsARM_UseNaClTrap, // TRAPNaCl = 1839 18528 CEFBS_IsARM_HasV8_4a, // TSB = 1840 18529 CEFBS_IsARM, // TSTri = 1841 18530 CEFBS_IsARM, // TSTrr = 1842 18531 CEFBS_IsARM, // TSTrsi = 1843 18532 CEFBS_IsARM, // TSTrsr = 1844 18533 CEFBS_IsARM, // UADD16 = 1845 18534 CEFBS_IsARM, // UADD8 = 1846 18535 CEFBS_IsARM, // UASX = 1847 18536 CEFBS_IsARM_HasV6T2, // UBFX = 1848 18537 CEFBS_IsARM, // UDF = 1849 18538 CEFBS_IsARM_HasDivideInARM, // UDIV = 1850 18539 CEFBS_IsARM, // UHADD16 = 1851 18540 CEFBS_IsARM, // UHADD8 = 1852 18541 CEFBS_IsARM, // UHASX = 1853 18542 CEFBS_IsARM, // UHSAX = 1854 18543 CEFBS_IsARM, // UHSUB16 = 1855 18544 CEFBS_IsARM, // UHSUB8 = 1856 18545 CEFBS_IsARM_HasV6, // UMAAL = 1857 18546 CEFBS_IsARM_HasV6, // UMLAL = 1858 18547 CEFBS_IsARM_HasV6, // UMULL = 1859 18548 CEFBS_IsARM, // UQADD16 = 1860 18549 CEFBS_IsARM, // UQADD8 = 1861 18550 CEFBS_IsARM, // UQASX = 1862 18551 CEFBS_IsARM, // UQSAX = 1863 18552 CEFBS_IsARM, // UQSUB16 = 1864 18553 CEFBS_IsARM, // UQSUB8 = 1865 18554 CEFBS_IsARM_HasV6, // USAD8 = 1866 18555 CEFBS_IsARM_HasV6, // USADA8 = 1867 18556 CEFBS_IsARM_HasV6, // USAT = 1868 18557 CEFBS_IsARM_HasV6, // USAT16 = 1869 18558 CEFBS_IsARM, // USAX = 1870 18559 CEFBS_IsARM, // USUB16 = 1871 18560 CEFBS_IsARM, // USUB8 = 1872 18561 CEFBS_IsARM_HasV6, // UXTAB = 1873 18562 CEFBS_IsARM_HasV6, // UXTAB16 = 1874 18563 CEFBS_IsARM_HasV6, // UXTAH = 1875 18564 CEFBS_IsARM_HasV6, // UXTB = 1876 18565 CEFBS_IsARM_HasV6, // UXTB16 = 1877 18566 CEFBS_IsARM_HasV6, // UXTH = 1878 18567 CEFBS_HasNEON, // VABALsv2i64 = 1879 18568 CEFBS_HasNEON, // VABALsv4i32 = 1880 18569 CEFBS_HasNEON, // VABALsv8i16 = 1881 18570 CEFBS_HasNEON, // VABALuv2i64 = 1882 18571 CEFBS_HasNEON, // VABALuv4i32 = 1883 18572 CEFBS_HasNEON, // VABALuv8i16 = 1884 18573 CEFBS_HasNEON, // VABAsv16i8 = 1885 18574 CEFBS_HasNEON, // VABAsv2i32 = 1886 18575 CEFBS_HasNEON, // VABAsv4i16 = 1887 18576 CEFBS_HasNEON, // VABAsv4i32 = 1888 18577 CEFBS_HasNEON, // VABAsv8i16 = 1889 18578 CEFBS_HasNEON, // VABAsv8i8 = 1890 18579 CEFBS_HasNEON, // VABAuv16i8 = 1891 18580 CEFBS_HasNEON, // VABAuv2i32 = 1892 18581 CEFBS_HasNEON, // VABAuv4i16 = 1893 18582 CEFBS_HasNEON, // VABAuv4i32 = 1894 18583 CEFBS_HasNEON, // VABAuv8i16 = 1895 18584 CEFBS_HasNEON, // VABAuv8i8 = 1896 18585 CEFBS_HasNEON, // VABDLsv2i64 = 1897 18586 CEFBS_HasNEON, // VABDLsv4i32 = 1898 18587 CEFBS_HasNEON, // VABDLsv8i16 = 1899 18588 CEFBS_HasNEON, // VABDLuv2i64 = 1900 18589 CEFBS_HasNEON, // VABDLuv4i32 = 1901 18590 CEFBS_HasNEON, // VABDLuv8i16 = 1902 18591 CEFBS_HasNEON, // VABDfd = 1903 18592 CEFBS_HasNEON, // VABDfq = 1904 18593 CEFBS_HasNEON_HasFullFP16, // VABDhd = 1905 18594 CEFBS_HasNEON_HasFullFP16, // VABDhq = 1906 18595 CEFBS_HasNEON, // VABDsv16i8 = 1907 18596 CEFBS_HasNEON, // VABDsv2i32 = 1908 18597 CEFBS_HasNEON, // VABDsv4i16 = 1909 18598 CEFBS_HasNEON, // VABDsv4i32 = 1910 18599 CEFBS_HasNEON, // VABDsv8i16 = 1911 18600 CEFBS_HasNEON, // VABDsv8i8 = 1912 18601 CEFBS_HasNEON, // VABDuv16i8 = 1913 18602 CEFBS_HasNEON, // VABDuv2i32 = 1914 18603 CEFBS_HasNEON, // VABDuv4i16 = 1915 18604 CEFBS_HasNEON, // VABDuv4i32 = 1916 18605 CEFBS_HasNEON, // VABDuv8i16 = 1917 18606 CEFBS_HasNEON, // VABDuv8i8 = 1918 18607 CEFBS_HasVFP2_HasDPVFP, // VABSD = 1919 18608 CEFBS_HasFullFP16, // VABSH = 1920 18609 CEFBS_HasVFP2, // VABSS = 1921 18610 CEFBS_HasNEON, // VABSfd = 1922 18611 CEFBS_HasNEON, // VABSfq = 1923 18612 CEFBS_HasNEON_HasFullFP16, // VABShd = 1924 18613 CEFBS_HasNEON_HasFullFP16, // VABShq = 1925 18614 CEFBS_HasNEON, // VABSv16i8 = 1926 18615 CEFBS_HasNEON, // VABSv2i32 = 1927 18616 CEFBS_HasNEON, // VABSv4i16 = 1928 18617 CEFBS_HasNEON, // VABSv4i32 = 1929 18618 CEFBS_HasNEON, // VABSv8i16 = 1930 18619 CEFBS_HasNEON, // VABSv8i8 = 1931 18620 CEFBS_HasNEON, // VACGEfd = 1932 18621 CEFBS_HasNEON, // VACGEfq = 1933 18622 CEFBS_HasNEON_HasFullFP16, // VACGEhd = 1934 18623 CEFBS_HasNEON_HasFullFP16, // VACGEhq = 1935 18624 CEFBS_HasNEON, // VACGTfd = 1936 18625 CEFBS_HasNEON, // VACGTfq = 1937 18626 CEFBS_HasNEON_HasFullFP16, // VACGThd = 1938 18627 CEFBS_HasNEON_HasFullFP16, // VACGThq = 1939 18628 CEFBS_HasVFP2_HasDPVFP, // VADDD = 1940 18629 CEFBS_HasFullFP16, // VADDH = 1941 18630 CEFBS_HasNEON, // VADDHNv2i32 = 1942 18631 CEFBS_HasNEON, // VADDHNv4i16 = 1943 18632 CEFBS_HasNEON, // VADDHNv8i8 = 1944 18633 CEFBS_HasNEON, // VADDLsv2i64 = 1945 18634 CEFBS_HasNEON, // VADDLsv4i32 = 1946 18635 CEFBS_HasNEON, // VADDLsv8i16 = 1947 18636 CEFBS_HasNEON, // VADDLuv2i64 = 1948 18637 CEFBS_HasNEON, // VADDLuv4i32 = 1949 18638 CEFBS_HasNEON, // VADDLuv8i16 = 1950 18639 CEFBS_HasVFP2, // VADDS = 1951 18640 CEFBS_HasNEON, // VADDWsv2i64 = 1952 18641 CEFBS_HasNEON, // VADDWsv4i32 = 1953 18642 CEFBS_HasNEON, // VADDWsv8i16 = 1954 18643 CEFBS_HasNEON, // VADDWuv2i64 = 1955 18644 CEFBS_HasNEON, // VADDWuv4i32 = 1956 18645 CEFBS_HasNEON, // VADDWuv8i16 = 1957 18646 CEFBS_HasNEON, // VADDfd = 1958 18647 CEFBS_HasNEON, // VADDfq = 1959 18648 CEFBS_HasNEON_HasFullFP16, // VADDhd = 1960 18649 CEFBS_HasNEON_HasFullFP16, // VADDhq = 1961 18650 CEFBS_HasNEON, // VADDv16i8 = 1962 18651 CEFBS_HasNEON, // VADDv1i64 = 1963 18652 CEFBS_HasNEON, // VADDv2i32 = 1964 18653 CEFBS_HasNEON, // VADDv2i64 = 1965 18654 CEFBS_HasNEON, // VADDv4i16 = 1966 18655 CEFBS_HasNEON, // VADDv4i32 = 1967 18656 CEFBS_HasNEON, // VADDv8i16 = 1968 18657 CEFBS_HasNEON, // VADDv8i8 = 1969 18658 CEFBS_HasNEON, // VANDd = 1970 18659 CEFBS_HasNEON, // VANDq = 1971 18660 CEFBS_HasNEON, // VBICd = 1972 18661 CEFBS_HasNEON, // VBICiv2i32 = 1973 18662 CEFBS_HasNEON, // VBICiv4i16 = 1974 18663 CEFBS_HasNEON, // VBICiv4i32 = 1975 18664 CEFBS_HasNEON, // VBICiv8i16 = 1976 18665 CEFBS_HasNEON, // VBICq = 1977 18666 CEFBS_HasNEON, // VBIFd = 1978 18667 CEFBS_HasNEON, // VBIFq = 1979 18668 CEFBS_HasNEON, // VBITd = 1980 18669 CEFBS_HasNEON, // VBITq = 1981 18670 CEFBS_HasNEON, // VBSLd = 1982 18671 CEFBS_HasNEON, // VBSLq = 1983 18672 CEFBS_HasNEON_HasV8_3a, // VCADDv2f32 = 1984 18673 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv4f16 = 1985 18674 CEFBS_HasNEON_HasV8_3a, // VCADDv4f32 = 1986 18675 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv8f16 = 1987 18676 CEFBS_HasNEON, // VCEQfd = 1988 18677 CEFBS_HasNEON, // VCEQfq = 1989 18678 CEFBS_HasNEON_HasFullFP16, // VCEQhd = 1990 18679 CEFBS_HasNEON_HasFullFP16, // VCEQhq = 1991 18680 CEFBS_HasNEON, // VCEQv16i8 = 1992 18681 CEFBS_HasNEON, // VCEQv2i32 = 1993 18682 CEFBS_HasNEON, // VCEQv4i16 = 1994 18683 CEFBS_HasNEON, // VCEQv4i32 = 1995 18684 CEFBS_HasNEON, // VCEQv8i16 = 1996 18685 CEFBS_HasNEON, // VCEQv8i8 = 1997 18686 CEFBS_HasNEON, // VCEQzv16i8 = 1998 18687 CEFBS_HasNEON, // VCEQzv2f32 = 1999 18688 CEFBS_HasNEON, // VCEQzv2i32 = 2000 18689 CEFBS_HasNEON_HasFullFP16, // VCEQzv4f16 = 2001 18690 CEFBS_HasNEON, // VCEQzv4f32 = 2002 18691 CEFBS_HasNEON, // VCEQzv4i16 = 2003 18692 CEFBS_HasNEON, // VCEQzv4i32 = 2004 18693 CEFBS_HasNEON_HasFullFP16, // VCEQzv8f16 = 2005 18694 CEFBS_HasNEON, // VCEQzv8i16 = 2006 18695 CEFBS_HasNEON, // VCEQzv8i8 = 2007 18696 CEFBS_HasNEON, // VCGEfd = 2008 18697 CEFBS_HasNEON, // VCGEfq = 2009 18698 CEFBS_HasNEON_HasFullFP16, // VCGEhd = 2010 18699 CEFBS_HasNEON_HasFullFP16, // VCGEhq = 2011 18700 CEFBS_HasNEON, // VCGEsv16i8 = 2012 18701 CEFBS_HasNEON, // VCGEsv2i32 = 2013 18702 CEFBS_HasNEON, // VCGEsv4i16 = 2014 18703 CEFBS_HasNEON, // VCGEsv4i32 = 2015 18704 CEFBS_HasNEON, // VCGEsv8i16 = 2016 18705 CEFBS_HasNEON, // VCGEsv8i8 = 2017 18706 CEFBS_HasNEON, // VCGEuv16i8 = 2018 18707 CEFBS_HasNEON, // VCGEuv2i32 = 2019 18708 CEFBS_HasNEON, // VCGEuv4i16 = 2020 18709 CEFBS_HasNEON, // VCGEuv4i32 = 2021 18710 CEFBS_HasNEON, // VCGEuv8i16 = 2022 18711 CEFBS_HasNEON, // VCGEuv8i8 = 2023 18712 CEFBS_HasNEON, // VCGEzv16i8 = 2024 18713 CEFBS_HasNEON, // VCGEzv2f32 = 2025 18714 CEFBS_HasNEON, // VCGEzv2i32 = 2026 18715 CEFBS_HasNEON_HasFullFP16, // VCGEzv4f16 = 2027 18716 CEFBS_HasNEON, // VCGEzv4f32 = 2028 18717 CEFBS_HasNEON, // VCGEzv4i16 = 2029 18718 CEFBS_HasNEON, // VCGEzv4i32 = 2030 18719 CEFBS_HasNEON_HasFullFP16, // VCGEzv8f16 = 2031 18720 CEFBS_HasNEON, // VCGEzv8i16 = 2032 18721 CEFBS_HasNEON, // VCGEzv8i8 = 2033 18722 CEFBS_HasNEON, // VCGTfd = 2034 18723 CEFBS_HasNEON, // VCGTfq = 2035 18724 CEFBS_HasNEON_HasFullFP16, // VCGThd = 2036 18725 CEFBS_HasNEON_HasFullFP16, // VCGThq = 2037 18726 CEFBS_HasNEON, // VCGTsv16i8 = 2038 18727 CEFBS_HasNEON, // VCGTsv2i32 = 2039 18728 CEFBS_HasNEON, // VCGTsv4i16 = 2040 18729 CEFBS_HasNEON, // VCGTsv4i32 = 2041 18730 CEFBS_HasNEON, // VCGTsv8i16 = 2042 18731 CEFBS_HasNEON, // VCGTsv8i8 = 2043 18732 CEFBS_HasNEON, // VCGTuv16i8 = 2044 18733 CEFBS_HasNEON, // VCGTuv2i32 = 2045 18734 CEFBS_HasNEON, // VCGTuv4i16 = 2046 18735 CEFBS_HasNEON, // VCGTuv4i32 = 2047 18736 CEFBS_HasNEON, // VCGTuv8i16 = 2048 18737 CEFBS_HasNEON, // VCGTuv8i8 = 2049 18738 CEFBS_HasNEON, // VCGTzv16i8 = 2050 18739 CEFBS_HasNEON, // VCGTzv2f32 = 2051 18740 CEFBS_HasNEON, // VCGTzv2i32 = 2052 18741 CEFBS_HasNEON_HasFullFP16, // VCGTzv4f16 = 2053 18742 CEFBS_HasNEON, // VCGTzv4f32 = 2054 18743 CEFBS_HasNEON, // VCGTzv4i16 = 2055 18744 CEFBS_HasNEON, // VCGTzv4i32 = 2056 18745 CEFBS_HasNEON_HasFullFP16, // VCGTzv8f16 = 2057 18746 CEFBS_HasNEON, // VCGTzv8i16 = 2058 18747 CEFBS_HasNEON, // VCGTzv8i8 = 2059 18748 CEFBS_HasNEON, // VCLEzv16i8 = 2060 18749 CEFBS_HasNEON, // VCLEzv2f32 = 2061 18750 CEFBS_HasNEON, // VCLEzv2i32 = 2062 18751 CEFBS_HasNEON_HasFullFP16, // VCLEzv4f16 = 2063 18752 CEFBS_HasNEON, // VCLEzv4f32 = 2064 18753 CEFBS_HasNEON, // VCLEzv4i16 = 2065 18754 CEFBS_HasNEON, // VCLEzv4i32 = 2066 18755 CEFBS_HasNEON_HasFullFP16, // VCLEzv8f16 = 2067 18756 CEFBS_HasNEON, // VCLEzv8i16 = 2068 18757 CEFBS_HasNEON, // VCLEzv8i8 = 2069 18758 CEFBS_HasNEON, // VCLSv16i8 = 2070 18759 CEFBS_HasNEON, // VCLSv2i32 = 2071 18760 CEFBS_HasNEON, // VCLSv4i16 = 2072 18761 CEFBS_HasNEON, // VCLSv4i32 = 2073 18762 CEFBS_HasNEON, // VCLSv8i16 = 2074 18763 CEFBS_HasNEON, // VCLSv8i8 = 2075 18764 CEFBS_HasNEON, // VCLTzv16i8 = 2076 18765 CEFBS_HasNEON, // VCLTzv2f32 = 2077 18766 CEFBS_HasNEON, // VCLTzv2i32 = 2078 18767 CEFBS_HasNEON_HasFullFP16, // VCLTzv4f16 = 2079 18768 CEFBS_HasNEON, // VCLTzv4f32 = 2080 18769 CEFBS_HasNEON, // VCLTzv4i16 = 2081 18770 CEFBS_HasNEON, // VCLTzv4i32 = 2082 18771 CEFBS_HasNEON_HasFullFP16, // VCLTzv8f16 = 2083 18772 CEFBS_HasNEON, // VCLTzv8i16 = 2084 18773 CEFBS_HasNEON, // VCLTzv8i8 = 2085 18774 CEFBS_HasNEON, // VCLZv16i8 = 2086 18775 CEFBS_HasNEON, // VCLZv2i32 = 2087 18776 CEFBS_HasNEON, // VCLZv4i16 = 2088 18777 CEFBS_HasNEON, // VCLZv4i32 = 2089 18778 CEFBS_HasNEON, // VCLZv8i16 = 2090 18779 CEFBS_HasNEON, // VCLZv8i8 = 2091 18780 CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32 = 2092 18781 CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32_indexed = 2093 18782 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16 = 2094 18783 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16_indexed = 2095 18784 CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32 = 2096 18785 CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32_indexed = 2097 18786 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16 = 2098 18787 CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16_indexed = 2099 18788 CEFBS_HasVFP2_HasDPVFP, // VCMPD = 2100 18789 CEFBS_HasVFP2_HasDPVFP, // VCMPED = 2101 18790 CEFBS_HasFullFP16, // VCMPEH = 2102 18791 CEFBS_HasVFP2, // VCMPES = 2103 18792 CEFBS_HasVFP2_HasDPVFP, // VCMPEZD = 2104 18793 CEFBS_HasFullFP16, // VCMPEZH = 2105 18794 CEFBS_HasVFP2, // VCMPEZS = 2106 18795 CEFBS_HasFullFP16, // VCMPH = 2107 18796 CEFBS_HasVFP2, // VCMPS = 2108 18797 CEFBS_HasVFP2_HasDPVFP, // VCMPZD = 2109 18798 CEFBS_HasFullFP16, // VCMPZH = 2110 18799 CEFBS_HasVFP2, // VCMPZS = 2111 18800 CEFBS_HasNEON, // VCNTd = 2112 18801 CEFBS_HasNEON, // VCNTq = 2113 18802 CEFBS_HasV8_HasNEON, // VCVTANSDf = 2114 18803 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSDh = 2115 18804 CEFBS_HasV8_HasNEON, // VCVTANSQf = 2116 18805 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSQh = 2117 18806 CEFBS_HasV8_HasNEON, // VCVTANUDf = 2118 18807 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUDh = 2119 18808 CEFBS_HasV8_HasNEON, // VCVTANUQf = 2120 18809 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUQh = 2121 18810 CEFBS_HasFPARMv8_HasDPVFP, // VCVTASD = 2122 18811 CEFBS_HasFullFP16, // VCVTASH = 2123 18812 CEFBS_HasFPARMv8, // VCVTASS = 2124 18813 CEFBS_HasFPARMv8_HasDPVFP, // VCVTAUD = 2125 18814 CEFBS_HasFullFP16, // VCVTAUH = 2126 18815 CEFBS_HasFPARMv8, // VCVTAUS = 2127 18816 CEFBS_HasFPARMv8_HasDPVFP, // VCVTBDH = 2128 18817 CEFBS_HasFPARMv8_HasDPVFP, // VCVTBHD = 2129 18818 CEFBS_HasFP16, // VCVTBHS = 2130 18819 CEFBS_HasFP16, // VCVTBSH = 2131 18820 CEFBS_HasVFP2_HasDPVFP, // VCVTDS = 2132 18821 CEFBS_HasV8_HasNEON, // VCVTMNSDf = 2133 18822 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSDh = 2134 18823 CEFBS_HasV8_HasNEON, // VCVTMNSQf = 2135 18824 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSQh = 2136 18825 CEFBS_HasV8_HasNEON, // VCVTMNUDf = 2137 18826 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUDh = 2138 18827 CEFBS_HasV8_HasNEON, // VCVTMNUQf = 2139 18828 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUQh = 2140 18829 CEFBS_HasFPARMv8_HasDPVFP, // VCVTMSD = 2141 18830 CEFBS_HasFullFP16, // VCVTMSH = 2142 18831 CEFBS_HasFPARMv8, // VCVTMSS = 2143 18832 CEFBS_HasFPARMv8_HasDPVFP, // VCVTMUD = 2144 18833 CEFBS_HasFullFP16, // VCVTMUH = 2145 18834 CEFBS_HasFPARMv8, // VCVTMUS = 2146 18835 CEFBS_HasV8_HasNEON, // VCVTNNSDf = 2147 18836 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSDh = 2148 18837 CEFBS_HasV8_HasNEON, // VCVTNNSQf = 2149 18838 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSQh = 2150 18839 CEFBS_HasV8_HasNEON, // VCVTNNUDf = 2151 18840 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUDh = 2152 18841 CEFBS_HasV8_HasNEON, // VCVTNNUQf = 2153 18842 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUQh = 2154 18843 CEFBS_HasFPARMv8_HasDPVFP, // VCVTNSD = 2155 18844 CEFBS_HasFullFP16, // VCVTNSH = 2156 18845 CEFBS_HasFPARMv8, // VCVTNSS = 2157 18846 CEFBS_HasFPARMv8_HasDPVFP, // VCVTNUD = 2158 18847 CEFBS_HasFullFP16, // VCVTNUH = 2159 18848 CEFBS_HasFPARMv8, // VCVTNUS = 2160 18849 CEFBS_HasV8_HasNEON, // VCVTPNSDf = 2161 18850 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSDh = 2162 18851 CEFBS_HasV8_HasNEON, // VCVTPNSQf = 2163 18852 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSQh = 2164 18853 CEFBS_HasV8_HasNEON, // VCVTPNUDf = 2165 18854 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUDh = 2166 18855 CEFBS_HasV8_HasNEON, // VCVTPNUQf = 2167 18856 CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUQh = 2168 18857 CEFBS_HasFPARMv8_HasDPVFP, // VCVTPSD = 2169 18858 CEFBS_HasFullFP16, // VCVTPSH = 2170 18859 CEFBS_HasFPARMv8, // VCVTPSS = 2171 18860 CEFBS_HasFPARMv8_HasDPVFP, // VCVTPUD = 2172 18861 CEFBS_HasFullFP16, // VCVTPUH = 2173 18862 CEFBS_HasFPARMv8, // VCVTPUS = 2174 18863 CEFBS_HasVFP2_HasDPVFP, // VCVTSD = 2175 18864 CEFBS_HasFPARMv8_HasDPVFP, // VCVTTDH = 2176 18865 CEFBS_HasFPARMv8_HasDPVFP, // VCVTTHD = 2177 18866 CEFBS_HasFP16, // VCVTTHS = 2178 18867 CEFBS_HasFP16, // VCVTTSH = 2179 18868 CEFBS_HasNEON_HasFP16, // VCVTf2h = 2180 18869 CEFBS_HasNEON, // VCVTf2sd = 2181 18870 CEFBS_HasNEON, // VCVTf2sq = 2182 18871 CEFBS_HasNEON, // VCVTf2ud = 2183 18872 CEFBS_HasNEON, // VCVTf2uq = 2184 18873 CEFBS_HasNEON, // VCVTf2xsd = 2185 18874 CEFBS_HasNEON, // VCVTf2xsq = 2186 18875 CEFBS_HasNEON, // VCVTf2xud = 2187 18876 CEFBS_HasNEON, // VCVTf2xuq = 2188 18877 CEFBS_HasNEON_HasFP16, // VCVTh2f = 2189 18878 CEFBS_HasNEON_HasFullFP16, // VCVTh2sd = 2190 18879 CEFBS_HasNEON_HasFullFP16, // VCVTh2sq = 2191 18880 CEFBS_HasNEON_HasFullFP16, // VCVTh2ud = 2192 18881 CEFBS_HasNEON_HasFullFP16, // VCVTh2uq = 2193 18882 CEFBS_HasNEON_HasFullFP16, // VCVTh2xsd = 2194 18883 CEFBS_HasNEON_HasFullFP16, // VCVTh2xsq = 2195 18884 CEFBS_HasNEON_HasFullFP16, // VCVTh2xud = 2196 18885 CEFBS_HasNEON_HasFullFP16, // VCVTh2xuq = 2197 18886 CEFBS_HasNEON, // VCVTs2fd = 2198 18887 CEFBS_HasNEON, // VCVTs2fq = 2199 18888 CEFBS_HasNEON_HasFullFP16, // VCVTs2hd = 2200 18889 CEFBS_HasNEON_HasFullFP16, // VCVTs2hq = 2201 18890 CEFBS_HasNEON, // VCVTu2fd = 2202 18891 CEFBS_HasNEON, // VCVTu2fq = 2203 18892 CEFBS_HasNEON_HasFullFP16, // VCVTu2hd = 2204 18893 CEFBS_HasNEON_HasFullFP16, // VCVTu2hq = 2205 18894 CEFBS_HasNEON, // VCVTxs2fd = 2206 18895 CEFBS_HasNEON, // VCVTxs2fq = 2207 18896 CEFBS_HasNEON_HasFullFP16, // VCVTxs2hd = 2208 18897 CEFBS_HasNEON_HasFullFP16, // VCVTxs2hq = 2209 18898 CEFBS_HasNEON, // VCVTxu2fd = 2210 18899 CEFBS_HasNEON, // VCVTxu2fq = 2211 18900 CEFBS_HasNEON_HasFullFP16, // VCVTxu2hd = 2212 18901 CEFBS_HasNEON_HasFullFP16, // VCVTxu2hq = 2213 18902 CEFBS_HasVFP2_HasDPVFP, // VDIVD = 2214 18903 CEFBS_HasFullFP16, // VDIVH = 2215 18904 CEFBS_HasVFP2, // VDIVS = 2216 18905 CEFBS_HasNEON, // VDUP16d = 2217 18906 CEFBS_HasNEON, // VDUP16q = 2218 18907 CEFBS_HasNEON, // VDUP32d = 2219 18908 CEFBS_HasNEON, // VDUP32q = 2220 18909 CEFBS_HasNEON, // VDUP8d = 2221 18910 CEFBS_HasNEON, // VDUP8q = 2222 18911 CEFBS_HasNEON, // VDUPLN16d = 2223 18912 CEFBS_HasNEON, // VDUPLN16q = 2224 18913 CEFBS_HasNEON, // VDUPLN32d = 2225 18914 CEFBS_HasNEON, // VDUPLN32q = 2226 18915 CEFBS_HasNEON, // VDUPLN8d = 2227 18916 CEFBS_HasNEON, // VDUPLN8q = 2228 18917 CEFBS_HasNEON, // VEORd = 2229 18918 CEFBS_HasNEON, // VEORq = 2230 18919 CEFBS_HasNEON, // VEXTd16 = 2231 18920 CEFBS_HasNEON, // VEXTd32 = 2232 18921 CEFBS_HasNEON, // VEXTd8 = 2233 18922 CEFBS_HasNEON, // VEXTq16 = 2234 18923 CEFBS_HasNEON, // VEXTq32 = 2235 18924 CEFBS_HasNEON, // VEXTq64 = 2236 18925 CEFBS_HasNEON, // VEXTq8 = 2237 18926 CEFBS_HasVFP4_HasDPVFP, // VFMAD = 2238 18927 CEFBS_HasFullFP16, // VFMAH = 2239 18928 CEFBS_HasNEON_HasFP16FML, // VFMALD = 2240 18929 CEFBS_HasNEON_HasFP16FML, // VFMALDI = 2241 18930 CEFBS_HasNEON_HasFP16FML, // VFMALQ = 2242 18931 CEFBS_HasNEON_HasFP16FML, // VFMALQI = 2243 18932 CEFBS_HasVFP4, // VFMAS = 2244 18933 CEFBS_HasNEON_HasVFP4, // VFMAfd = 2245 18934 CEFBS_HasNEON_HasVFP4, // VFMAfq = 2246 18935 CEFBS_HasNEON_HasFullFP16, // VFMAhd = 2247 18936 CEFBS_HasNEON_HasFullFP16, // VFMAhq = 2248 18937 CEFBS_HasVFP4_HasDPVFP, // VFMSD = 2249 18938 CEFBS_HasFullFP16, // VFMSH = 2250 18939 CEFBS_HasNEON_HasFP16FML, // VFMSLD = 2251 18940 CEFBS_HasNEON_HasFP16FML, // VFMSLDI = 2252 18941 CEFBS_HasNEON_HasFP16FML, // VFMSLQ = 2253 18942 CEFBS_HasNEON_HasFP16FML, // VFMSLQI = 2254 18943 CEFBS_HasVFP4, // VFMSS = 2255 18944 CEFBS_HasNEON_HasVFP4, // VFMSfd = 2256 18945 CEFBS_HasNEON_HasVFP4, // VFMSfq = 2257 18946 CEFBS_HasNEON_HasFullFP16, // VFMShd = 2258 18947 CEFBS_HasNEON_HasFullFP16, // VFMShq = 2259 18948 CEFBS_HasVFP4_HasDPVFP, // VFNMAD = 2260 18949 CEFBS_HasFullFP16, // VFNMAH = 2261 18950 CEFBS_HasVFP4, // VFNMAS = 2262 18951 CEFBS_HasVFP4_HasDPVFP, // VFNMSD = 2263 18952 CEFBS_HasFullFP16, // VFNMSH = 2264 18953 CEFBS_HasVFP4, // VFNMSS = 2265 18954 CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMAXNMD = 2266 18955 CEFBS_HasFullFP16, // VFP_VMAXNMH = 2267 18956 CEFBS_HasFPARMv8, // VFP_VMAXNMS = 2268 18957 CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMINNMD = 2269 18958 CEFBS_HasFullFP16, // VFP_VMINNMH = 2270 18959 CEFBS_HasFPARMv8, // VFP_VMINNMS = 2271 18960 CEFBS_HasFPRegs, // VGETLNi32 = 2272 18961 CEFBS_HasNEON, // VGETLNs16 = 2273 18962 CEFBS_HasNEON, // VGETLNs8 = 2274 18963 CEFBS_HasNEON, // VGETLNu16 = 2275 18964 CEFBS_HasNEON, // VGETLNu8 = 2276 18965 CEFBS_HasNEON, // VHADDsv16i8 = 2277 18966 CEFBS_HasNEON, // VHADDsv2i32 = 2278 18967 CEFBS_HasNEON, // VHADDsv4i16 = 2279 18968 CEFBS_HasNEON, // VHADDsv4i32 = 2280 18969 CEFBS_HasNEON, // VHADDsv8i16 = 2281 18970 CEFBS_HasNEON, // VHADDsv8i8 = 2282 18971 CEFBS_HasNEON, // VHADDuv16i8 = 2283 18972 CEFBS_HasNEON, // VHADDuv2i32 = 2284 18973 CEFBS_HasNEON, // VHADDuv4i16 = 2285 18974 CEFBS_HasNEON, // VHADDuv4i32 = 2286 18975 CEFBS_HasNEON, // VHADDuv8i16 = 2287 18976 CEFBS_HasNEON, // VHADDuv8i8 = 2288 18977 CEFBS_HasNEON, // VHSUBsv16i8 = 2289 18978 CEFBS_HasNEON, // VHSUBsv2i32 = 2290 18979 CEFBS_HasNEON, // VHSUBsv4i16 = 2291 18980 CEFBS_HasNEON, // VHSUBsv4i32 = 2292 18981 CEFBS_HasNEON, // VHSUBsv8i16 = 2293 18982 CEFBS_HasNEON, // VHSUBsv8i8 = 2294 18983 CEFBS_HasNEON, // VHSUBuv16i8 = 2295 18984 CEFBS_HasNEON, // VHSUBuv2i32 = 2296 18985 CEFBS_HasNEON, // VHSUBuv4i16 = 2297 18986 CEFBS_HasNEON, // VHSUBuv4i32 = 2298 18987 CEFBS_HasNEON, // VHSUBuv8i16 = 2299 18988 CEFBS_HasNEON, // VHSUBuv8i8 = 2300 18989 CEFBS_HasFullFP16, // VINSH = 2301 18990 CEFBS_HasFPARMv8_HasV8_3a, // VJCVT = 2302 18991 CEFBS_HasNEON, // VLD1DUPd16 = 2303 18992 CEFBS_HasNEON, // VLD1DUPd16wb_fixed = 2304 18993 CEFBS_HasNEON, // VLD1DUPd16wb_register = 2305 18994 CEFBS_HasNEON, // VLD1DUPd32 = 2306 18995 CEFBS_HasNEON, // VLD1DUPd32wb_fixed = 2307 18996 CEFBS_HasNEON, // VLD1DUPd32wb_register = 2308 18997 CEFBS_HasNEON, // VLD1DUPd8 = 2309 18998 CEFBS_HasNEON, // VLD1DUPd8wb_fixed = 2310 18999 CEFBS_HasNEON, // VLD1DUPd8wb_register = 2311 19000 CEFBS_HasNEON, // VLD1DUPq16 = 2312 19001 CEFBS_HasNEON, // VLD1DUPq16wb_fixed = 2313 19002 CEFBS_HasNEON, // VLD1DUPq16wb_register = 2314 19003 CEFBS_HasNEON, // VLD1DUPq32 = 2315 19004 CEFBS_HasNEON, // VLD1DUPq32wb_fixed = 2316 19005 CEFBS_HasNEON, // VLD1DUPq32wb_register = 2317 19006 CEFBS_HasNEON, // VLD1DUPq8 = 2318 19007 CEFBS_HasNEON, // VLD1DUPq8wb_fixed = 2319 19008 CEFBS_HasNEON, // VLD1DUPq8wb_register = 2320 19009 CEFBS_HasNEON, // VLD1LNd16 = 2321 19010 CEFBS_HasNEON, // VLD1LNd16_UPD = 2322 19011 CEFBS_HasNEON, // VLD1LNd32 = 2323 19012 CEFBS_HasNEON, // VLD1LNd32_UPD = 2324 19013 CEFBS_HasNEON, // VLD1LNd8 = 2325 19014 CEFBS_HasNEON, // VLD1LNd8_UPD = 2326 19015 CEFBS_HasNEON, // VLD1LNq16Pseudo = 2327 19016 CEFBS_HasNEON, // VLD1LNq16Pseudo_UPD = 2328 19017 CEFBS_HasNEON, // VLD1LNq32Pseudo = 2329 19018 CEFBS_HasNEON, // VLD1LNq32Pseudo_UPD = 2330 19019 CEFBS_HasNEON, // VLD1LNq8Pseudo = 2331 19020 CEFBS_HasNEON, // VLD1LNq8Pseudo_UPD = 2332 19021 CEFBS_HasNEON, // VLD1d16 = 2333 19022 CEFBS_HasNEON, // VLD1d16Q = 2334 19023 CEFBS_HasNEON, // VLD1d16QPseudo = 2335 19024 CEFBS_HasNEON, // VLD1d16Qwb_fixed = 2336 19025 CEFBS_HasNEON, // VLD1d16Qwb_register = 2337 19026 CEFBS_HasNEON, // VLD1d16T = 2338 19027 CEFBS_HasNEON, // VLD1d16TPseudo = 2339 19028 CEFBS_HasNEON, // VLD1d16Twb_fixed = 2340 19029 CEFBS_HasNEON, // VLD1d16Twb_register = 2341 19030 CEFBS_HasNEON, // VLD1d16wb_fixed = 2342 19031 CEFBS_HasNEON, // VLD1d16wb_register = 2343 19032 CEFBS_HasNEON, // VLD1d32 = 2344 19033 CEFBS_HasNEON, // VLD1d32Q = 2345 19034 CEFBS_HasNEON, // VLD1d32QPseudo = 2346 19035 CEFBS_HasNEON, // VLD1d32Qwb_fixed = 2347 19036 CEFBS_HasNEON, // VLD1d32Qwb_register = 2348 19037 CEFBS_HasNEON, // VLD1d32T = 2349 19038 CEFBS_HasNEON, // VLD1d32TPseudo = 2350 19039 CEFBS_HasNEON, // VLD1d32Twb_fixed = 2351 19040 CEFBS_HasNEON, // VLD1d32Twb_register = 2352 19041 CEFBS_HasNEON, // VLD1d32wb_fixed = 2353 19042 CEFBS_HasNEON, // VLD1d32wb_register = 2354 19043 CEFBS_HasNEON, // VLD1d64 = 2355 19044 CEFBS_HasNEON, // VLD1d64Q = 2356 19045 CEFBS_HasNEON, // VLD1d64QPseudo = 2357 19046 CEFBS_HasNEON, // VLD1d64QPseudoWB_fixed = 2358 19047 CEFBS_HasNEON, // VLD1d64QPseudoWB_register = 2359 19048 CEFBS_HasNEON, // VLD1d64Qwb_fixed = 2360 19049 CEFBS_HasNEON, // VLD1d64Qwb_register = 2361 19050 CEFBS_HasNEON, // VLD1d64T = 2362 19051 CEFBS_HasNEON, // VLD1d64TPseudo = 2363 19052 CEFBS_HasNEON, // VLD1d64TPseudoWB_fixed = 2364 19053 CEFBS_HasNEON, // VLD1d64TPseudoWB_register = 2365 19054 CEFBS_HasNEON, // VLD1d64Twb_fixed = 2366 19055 CEFBS_HasNEON, // VLD1d64Twb_register = 2367 19056 CEFBS_HasNEON, // VLD1d64wb_fixed = 2368 19057 CEFBS_HasNEON, // VLD1d64wb_register = 2369 19058 CEFBS_HasNEON, // VLD1d8 = 2370 19059 CEFBS_HasNEON, // VLD1d8Q = 2371 19060 CEFBS_HasNEON, // VLD1d8QPseudo = 2372 19061 CEFBS_HasNEON, // VLD1d8Qwb_fixed = 2373 19062 CEFBS_HasNEON, // VLD1d8Qwb_register = 2374 19063 CEFBS_HasNEON, // VLD1d8T = 2375 19064 CEFBS_HasNEON, // VLD1d8TPseudo = 2376 19065 CEFBS_HasNEON, // VLD1d8Twb_fixed = 2377 19066 CEFBS_HasNEON, // VLD1d8Twb_register = 2378 19067 CEFBS_HasNEON, // VLD1d8wb_fixed = 2379 19068 CEFBS_HasNEON, // VLD1d8wb_register = 2380 19069 CEFBS_HasNEON, // VLD1q16 = 2381 19070 CEFBS_HasNEON, // VLD1q16HighQPseudo = 2382 19071 CEFBS_HasNEON, // VLD1q16HighTPseudo = 2383 19072 CEFBS_HasNEON, // VLD1q16LowQPseudo_UPD = 2384 19073 CEFBS_HasNEON, // VLD1q16LowTPseudo_UPD = 2385 19074 CEFBS_HasNEON, // VLD1q16wb_fixed = 2386 19075 CEFBS_HasNEON, // VLD1q16wb_register = 2387 19076 CEFBS_HasNEON, // VLD1q32 = 2388 19077 CEFBS_HasNEON, // VLD1q32HighQPseudo = 2389 19078 CEFBS_HasNEON, // VLD1q32HighTPseudo = 2390 19079 CEFBS_HasNEON, // VLD1q32LowQPseudo_UPD = 2391 19080 CEFBS_HasNEON, // VLD1q32LowTPseudo_UPD = 2392 19081 CEFBS_HasNEON, // VLD1q32wb_fixed = 2393 19082 CEFBS_HasNEON, // VLD1q32wb_register = 2394 19083 CEFBS_HasNEON, // VLD1q64 = 2395 19084 CEFBS_HasNEON, // VLD1q64HighQPseudo = 2396 19085 CEFBS_HasNEON, // VLD1q64HighTPseudo = 2397 19086 CEFBS_HasNEON, // VLD1q64LowQPseudo_UPD = 2398 19087 CEFBS_HasNEON, // VLD1q64LowTPseudo_UPD = 2399 19088 CEFBS_HasNEON, // VLD1q64wb_fixed = 2400 19089 CEFBS_HasNEON, // VLD1q64wb_register = 2401 19090 CEFBS_HasNEON, // VLD1q8 = 2402 19091 CEFBS_HasNEON, // VLD1q8HighQPseudo = 2403 19092 CEFBS_HasNEON, // VLD1q8HighTPseudo = 2404 19093 CEFBS_HasNEON, // VLD1q8LowQPseudo_UPD = 2405 19094 CEFBS_HasNEON, // VLD1q8LowTPseudo_UPD = 2406 19095 CEFBS_HasNEON, // VLD1q8wb_fixed = 2407 19096 CEFBS_HasNEON, // VLD1q8wb_register = 2408 19097 CEFBS_HasNEON, // VLD2DUPd16 = 2409 19098 CEFBS_HasNEON, // VLD2DUPd16wb_fixed = 2410 19099 CEFBS_HasNEON, // VLD2DUPd16wb_register = 2411 19100 CEFBS_HasNEON, // VLD2DUPd16x2 = 2412 19101 CEFBS_HasNEON, // VLD2DUPd16x2wb_fixed = 2413 19102 CEFBS_HasNEON, // VLD2DUPd16x2wb_register = 2414 19103 CEFBS_HasNEON, // VLD2DUPd32 = 2415 19104 CEFBS_HasNEON, // VLD2DUPd32wb_fixed = 2416 19105 CEFBS_HasNEON, // VLD2DUPd32wb_register = 2417 19106 CEFBS_HasNEON, // VLD2DUPd32x2 = 2418 19107 CEFBS_HasNEON, // VLD2DUPd32x2wb_fixed = 2419 19108 CEFBS_HasNEON, // VLD2DUPd32x2wb_register = 2420 19109 CEFBS_HasNEON, // VLD2DUPd8 = 2421 19110 CEFBS_HasNEON, // VLD2DUPd8wb_fixed = 2422 19111 CEFBS_HasNEON, // VLD2DUPd8wb_register = 2423 19112 CEFBS_HasNEON, // VLD2DUPd8x2 = 2424 19113 CEFBS_HasNEON, // VLD2DUPd8x2wb_fixed = 2425 19114 CEFBS_HasNEON, // VLD2DUPd8x2wb_register = 2426 19115 CEFBS_HasNEON, // VLD2DUPq16EvenPseudo = 2427 19116 CEFBS_HasNEON, // VLD2DUPq16OddPseudo = 2428 19117 CEFBS_HasNEON, // VLD2DUPq32EvenPseudo = 2429 19118 CEFBS_HasNEON, // VLD2DUPq32OddPseudo = 2430 19119 CEFBS_HasNEON, // VLD2DUPq8EvenPseudo = 2431 19120 CEFBS_HasNEON, // VLD2DUPq8OddPseudo = 2432 19121 CEFBS_HasNEON, // VLD2LNd16 = 2433 19122 CEFBS_HasNEON, // VLD2LNd16Pseudo = 2434 19123 CEFBS_HasNEON, // VLD2LNd16Pseudo_UPD = 2435 19124 CEFBS_HasNEON, // VLD2LNd16_UPD = 2436 19125 CEFBS_HasNEON, // VLD2LNd32 = 2437 19126 CEFBS_HasNEON, // VLD2LNd32Pseudo = 2438 19127 CEFBS_HasNEON, // VLD2LNd32Pseudo_UPD = 2439 19128 CEFBS_HasNEON, // VLD2LNd32_UPD = 2440 19129 CEFBS_HasNEON, // VLD2LNd8 = 2441 19130 CEFBS_HasNEON, // VLD2LNd8Pseudo = 2442 19131 CEFBS_HasNEON, // VLD2LNd8Pseudo_UPD = 2443 19132 CEFBS_HasNEON, // VLD2LNd8_UPD = 2444 19133 CEFBS_HasNEON, // VLD2LNq16 = 2445 19134 CEFBS_HasNEON, // VLD2LNq16Pseudo = 2446 19135 CEFBS_HasNEON, // VLD2LNq16Pseudo_UPD = 2447 19136 CEFBS_HasNEON, // VLD2LNq16_UPD = 2448 19137 CEFBS_HasNEON, // VLD2LNq32 = 2449 19138 CEFBS_HasNEON, // VLD2LNq32Pseudo = 2450 19139 CEFBS_HasNEON, // VLD2LNq32Pseudo_UPD = 2451 19140 CEFBS_HasNEON, // VLD2LNq32_UPD = 2452 19141 CEFBS_HasNEON, // VLD2b16 = 2453 19142 CEFBS_HasNEON, // VLD2b16wb_fixed = 2454 19143 CEFBS_HasNEON, // VLD2b16wb_register = 2455 19144 CEFBS_HasNEON, // VLD2b32 = 2456 19145 CEFBS_HasNEON, // VLD2b32wb_fixed = 2457 19146 CEFBS_HasNEON, // VLD2b32wb_register = 2458 19147 CEFBS_HasNEON, // VLD2b8 = 2459 19148 CEFBS_HasNEON, // VLD2b8wb_fixed = 2460 19149 CEFBS_HasNEON, // VLD2b8wb_register = 2461 19150 CEFBS_HasNEON, // VLD2d16 = 2462 19151 CEFBS_HasNEON, // VLD2d16wb_fixed = 2463 19152 CEFBS_HasNEON, // VLD2d16wb_register = 2464 19153 CEFBS_HasNEON, // VLD2d32 = 2465 19154 CEFBS_HasNEON, // VLD2d32wb_fixed = 2466 19155 CEFBS_HasNEON, // VLD2d32wb_register = 2467 19156 CEFBS_HasNEON, // VLD2d8 = 2468 19157 CEFBS_HasNEON, // VLD2d8wb_fixed = 2469 19158 CEFBS_HasNEON, // VLD2d8wb_register = 2470 19159 CEFBS_HasNEON, // VLD2q16 = 2471 19160 CEFBS_HasNEON, // VLD2q16Pseudo = 2472 19161 CEFBS_HasNEON, // VLD2q16PseudoWB_fixed = 2473 19162 CEFBS_HasNEON, // VLD2q16PseudoWB_register = 2474 19163 CEFBS_HasNEON, // VLD2q16wb_fixed = 2475 19164 CEFBS_HasNEON, // VLD2q16wb_register = 2476 19165 CEFBS_HasNEON, // VLD2q32 = 2477 19166 CEFBS_HasNEON, // VLD2q32Pseudo = 2478 19167 CEFBS_HasNEON, // VLD2q32PseudoWB_fixed = 2479 19168 CEFBS_HasNEON, // VLD2q32PseudoWB_register = 2480 19169 CEFBS_HasNEON, // VLD2q32wb_fixed = 2481 19170 CEFBS_HasNEON, // VLD2q32wb_register = 2482 19171 CEFBS_HasNEON, // VLD2q8 = 2483 19172 CEFBS_HasNEON, // VLD2q8Pseudo = 2484 19173 CEFBS_HasNEON, // VLD2q8PseudoWB_fixed = 2485 19174 CEFBS_HasNEON, // VLD2q8PseudoWB_register = 2486 19175 CEFBS_HasNEON, // VLD2q8wb_fixed = 2487 19176 CEFBS_HasNEON, // VLD2q8wb_register = 2488 19177 CEFBS_HasNEON, // VLD3DUPd16 = 2489 19178 CEFBS_HasNEON, // VLD3DUPd16Pseudo = 2490 19179 CEFBS_HasNEON, // VLD3DUPd16Pseudo_UPD = 2491 19180 CEFBS_HasNEON, // VLD3DUPd16_UPD = 2492 19181 CEFBS_HasNEON, // VLD3DUPd32 = 2493 19182 CEFBS_HasNEON, // VLD3DUPd32Pseudo = 2494 19183 CEFBS_HasNEON, // VLD3DUPd32Pseudo_UPD = 2495 19184 CEFBS_HasNEON, // VLD3DUPd32_UPD = 2496 19185 CEFBS_HasNEON, // VLD3DUPd8 = 2497 19186 CEFBS_HasNEON, // VLD3DUPd8Pseudo = 2498 19187 CEFBS_HasNEON, // VLD3DUPd8Pseudo_UPD = 2499 19188 CEFBS_HasNEON, // VLD3DUPd8_UPD = 2500 19189 CEFBS_HasNEON, // VLD3DUPq16 = 2501 19190 CEFBS_HasNEON, // VLD3DUPq16EvenPseudo = 2502 19191 CEFBS_HasNEON, // VLD3DUPq16OddPseudo = 2503 19192 CEFBS_HasNEON, // VLD3DUPq16_UPD = 2504 19193 CEFBS_HasNEON, // VLD3DUPq32 = 2505 19194 CEFBS_HasNEON, // VLD3DUPq32EvenPseudo = 2506 19195 CEFBS_HasNEON, // VLD3DUPq32OddPseudo = 2507 19196 CEFBS_HasNEON, // VLD3DUPq32_UPD = 2508 19197 CEFBS_HasNEON, // VLD3DUPq8 = 2509 19198 CEFBS_HasNEON, // VLD3DUPq8EvenPseudo = 2510 19199 CEFBS_HasNEON, // VLD3DUPq8OddPseudo = 2511 19200 CEFBS_HasNEON, // VLD3DUPq8_UPD = 2512 19201 CEFBS_HasNEON, // VLD3LNd16 = 2513 19202 CEFBS_HasNEON, // VLD3LNd16Pseudo = 2514 19203 CEFBS_HasNEON, // VLD3LNd16Pseudo_UPD = 2515 19204 CEFBS_HasNEON, // VLD3LNd16_UPD = 2516 19205 CEFBS_HasNEON, // VLD3LNd32 = 2517 19206 CEFBS_HasNEON, // VLD3LNd32Pseudo = 2518 19207 CEFBS_HasNEON, // VLD3LNd32Pseudo_UPD = 2519 19208 CEFBS_HasNEON, // VLD3LNd32_UPD = 2520 19209 CEFBS_HasNEON, // VLD3LNd8 = 2521 19210 CEFBS_HasNEON, // VLD3LNd8Pseudo = 2522 19211 CEFBS_HasNEON, // VLD3LNd8Pseudo_UPD = 2523 19212 CEFBS_HasNEON, // VLD3LNd8_UPD = 2524 19213 CEFBS_HasNEON, // VLD3LNq16 = 2525 19214 CEFBS_HasNEON, // VLD3LNq16Pseudo = 2526 19215 CEFBS_HasNEON, // VLD3LNq16Pseudo_UPD = 2527 19216 CEFBS_HasNEON, // VLD3LNq16_UPD = 2528 19217 CEFBS_HasNEON, // VLD3LNq32 = 2529 19218 CEFBS_HasNEON, // VLD3LNq32Pseudo = 2530 19219 CEFBS_HasNEON, // VLD3LNq32Pseudo_UPD = 2531 19220 CEFBS_HasNEON, // VLD3LNq32_UPD = 2532 19221 CEFBS_HasNEON, // VLD3d16 = 2533 19222 CEFBS_HasNEON, // VLD3d16Pseudo = 2534 19223 CEFBS_HasNEON, // VLD3d16Pseudo_UPD = 2535 19224 CEFBS_HasNEON, // VLD3d16_UPD = 2536 19225 CEFBS_HasNEON, // VLD3d32 = 2537 19226 CEFBS_HasNEON, // VLD3d32Pseudo = 2538 19227 CEFBS_HasNEON, // VLD3d32Pseudo_UPD = 2539 19228 CEFBS_HasNEON, // VLD3d32_UPD = 2540 19229 CEFBS_HasNEON, // VLD3d8 = 2541 19230 CEFBS_HasNEON, // VLD3d8Pseudo = 2542 19231 CEFBS_HasNEON, // VLD3d8Pseudo_UPD = 2543 19232 CEFBS_HasNEON, // VLD3d8_UPD = 2544 19233 CEFBS_HasNEON, // VLD3q16 = 2545 19234 CEFBS_HasNEON, // VLD3q16Pseudo_UPD = 2546 19235 CEFBS_HasNEON, // VLD3q16_UPD = 2547 19236 CEFBS_HasNEON, // VLD3q16oddPseudo = 2548 19237 CEFBS_HasNEON, // VLD3q16oddPseudo_UPD = 2549 19238 CEFBS_HasNEON, // VLD3q32 = 2550 19239 CEFBS_HasNEON, // VLD3q32Pseudo_UPD = 2551 19240 CEFBS_HasNEON, // VLD3q32_UPD = 2552 19241 CEFBS_HasNEON, // VLD3q32oddPseudo = 2553 19242 CEFBS_HasNEON, // VLD3q32oddPseudo_UPD = 2554 19243 CEFBS_HasNEON, // VLD3q8 = 2555 19244 CEFBS_HasNEON, // VLD3q8Pseudo_UPD = 2556 19245 CEFBS_HasNEON, // VLD3q8_UPD = 2557 19246 CEFBS_HasNEON, // VLD3q8oddPseudo = 2558 19247 CEFBS_HasNEON, // VLD3q8oddPseudo_UPD = 2559 19248 CEFBS_HasNEON, // VLD4DUPd16 = 2560 19249 CEFBS_HasNEON, // VLD4DUPd16Pseudo = 2561 19250 CEFBS_HasNEON, // VLD4DUPd16Pseudo_UPD = 2562 19251 CEFBS_HasNEON, // VLD4DUPd16_UPD = 2563 19252 CEFBS_HasNEON, // VLD4DUPd32 = 2564 19253 CEFBS_HasNEON, // VLD4DUPd32Pseudo = 2565 19254 CEFBS_HasNEON, // VLD4DUPd32Pseudo_UPD = 2566 19255 CEFBS_HasNEON, // VLD4DUPd32_UPD = 2567 19256 CEFBS_HasNEON, // VLD4DUPd8 = 2568 19257 CEFBS_HasNEON, // VLD4DUPd8Pseudo = 2569 19258 CEFBS_HasNEON, // VLD4DUPd8Pseudo_UPD = 2570 19259 CEFBS_HasNEON, // VLD4DUPd8_UPD = 2571 19260 CEFBS_HasNEON, // VLD4DUPq16 = 2572 19261 CEFBS_HasNEON, // VLD4DUPq16EvenPseudo = 2573 19262 CEFBS_HasNEON, // VLD4DUPq16OddPseudo = 2574 19263 CEFBS_HasNEON, // VLD4DUPq16_UPD = 2575 19264 CEFBS_HasNEON, // VLD4DUPq32 = 2576 19265 CEFBS_HasNEON, // VLD4DUPq32EvenPseudo = 2577 19266 CEFBS_HasNEON, // VLD4DUPq32OddPseudo = 2578 19267 CEFBS_HasNEON, // VLD4DUPq32_UPD = 2579 19268 CEFBS_HasNEON, // VLD4DUPq8 = 2580 19269 CEFBS_HasNEON, // VLD4DUPq8EvenPseudo = 2581 19270 CEFBS_HasNEON, // VLD4DUPq8OddPseudo = 2582 19271 CEFBS_HasNEON, // VLD4DUPq8_UPD = 2583 19272 CEFBS_HasNEON, // VLD4LNd16 = 2584 19273 CEFBS_HasNEON, // VLD4LNd16Pseudo = 2585 19274 CEFBS_HasNEON, // VLD4LNd16Pseudo_UPD = 2586 19275 CEFBS_HasNEON, // VLD4LNd16_UPD = 2587 19276 CEFBS_HasNEON, // VLD4LNd32 = 2588 19277 CEFBS_HasNEON, // VLD4LNd32Pseudo = 2589 19278 CEFBS_HasNEON, // VLD4LNd32Pseudo_UPD = 2590 19279 CEFBS_HasNEON, // VLD4LNd32_UPD = 2591 19280 CEFBS_HasNEON, // VLD4LNd8 = 2592 19281 CEFBS_HasNEON, // VLD4LNd8Pseudo = 2593 19282 CEFBS_HasNEON, // VLD4LNd8Pseudo_UPD = 2594 19283 CEFBS_HasNEON, // VLD4LNd8_UPD = 2595 19284 CEFBS_HasNEON, // VLD4LNq16 = 2596 19285 CEFBS_HasNEON, // VLD4LNq16Pseudo = 2597 19286 CEFBS_HasNEON, // VLD4LNq16Pseudo_UPD = 2598 19287 CEFBS_HasNEON, // VLD4LNq16_UPD = 2599 19288 CEFBS_HasNEON, // VLD4LNq32 = 2600 19289 CEFBS_HasNEON, // VLD4LNq32Pseudo = 2601 19290 CEFBS_HasNEON, // VLD4LNq32Pseudo_UPD = 2602 19291 CEFBS_HasNEON, // VLD4LNq32_UPD = 2603 19292 CEFBS_HasNEON, // VLD4d16 = 2604 19293 CEFBS_HasNEON, // VLD4d16Pseudo = 2605 19294 CEFBS_HasNEON, // VLD4d16Pseudo_UPD = 2606 19295 CEFBS_HasNEON, // VLD4d16_UPD = 2607 19296 CEFBS_HasNEON, // VLD4d32 = 2608 19297 CEFBS_HasNEON, // VLD4d32Pseudo = 2609 19298 CEFBS_HasNEON, // VLD4d32Pseudo_UPD = 2610 19299 CEFBS_HasNEON, // VLD4d32_UPD = 2611 19300 CEFBS_HasNEON, // VLD4d8 = 2612 19301 CEFBS_HasNEON, // VLD4d8Pseudo = 2613 19302 CEFBS_HasNEON, // VLD4d8Pseudo_UPD = 2614 19303 CEFBS_HasNEON, // VLD4d8_UPD = 2615 19304 CEFBS_HasNEON, // VLD4q16 = 2616 19305 CEFBS_HasNEON, // VLD4q16Pseudo_UPD = 2617 19306 CEFBS_HasNEON, // VLD4q16_UPD = 2618 19307 CEFBS_HasNEON, // VLD4q16oddPseudo = 2619 19308 CEFBS_HasNEON, // VLD4q16oddPseudo_UPD = 2620 19309 CEFBS_HasNEON, // VLD4q32 = 2621 19310 CEFBS_HasNEON, // VLD4q32Pseudo_UPD = 2622 19311 CEFBS_HasNEON, // VLD4q32_UPD = 2623 19312 CEFBS_HasNEON, // VLD4q32oddPseudo = 2624 19313 CEFBS_HasNEON, // VLD4q32oddPseudo_UPD = 2625 19314 CEFBS_HasNEON, // VLD4q8 = 2626 19315 CEFBS_HasNEON, // VLD4q8Pseudo_UPD = 2627 19316 CEFBS_HasNEON, // VLD4q8_UPD = 2628 19317 CEFBS_HasNEON, // VLD4q8oddPseudo = 2629 19318 CEFBS_HasNEON, // VLD4q8oddPseudo_UPD = 2630 19319 CEFBS_HasFPRegs, // VLDMDDB_UPD = 2631 19320 CEFBS_HasFPRegs, // VLDMDIA = 2632 19321 CEFBS_HasFPRegs, // VLDMDIA_UPD = 2633 19322 CEFBS_HasVFP2, // VLDMQIA = 2634 19323 CEFBS_HasFPRegs, // VLDMSDB_UPD = 2635 19324 CEFBS_HasFPRegs, // VLDMSIA = 2636 19325 CEFBS_HasFPRegs, // VLDMSIA_UPD = 2637 19326 CEFBS_HasFPRegs, // VLDRD = 2638 19327 CEFBS_HasFPRegs16, // VLDRH = 2639 19328 CEFBS_HasFPRegs, // VLDRS = 2640 19329 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_off = 2641 19330 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_post = 2642 19331 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_pre = 2643 19332 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_off = 2644 19333 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_post = 2645 19334 CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_pre = 2646 19335 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_off = 2647 19336 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_post = 2648 19337 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_pre = 2649 19338 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_off = 2650 19339 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_post = 2651 19340 CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_pre = 2652 19341 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_off = 2653 19342 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_post = 2654 19343 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_pre = 2655 19344 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_off = 2656 19345 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_post = 2657 19346 CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_pre = 2658 19347 CEFBS_HasV8MMainline_Has8MSecExt, // VLLDM = 2659 19348 CEFBS_HasV8MMainline_Has8MSecExt, // VLSTM = 2660 19349 CEFBS_HasNEON, // VMAXfd = 2661 19350 CEFBS_HasNEON, // VMAXfq = 2662 19351 CEFBS_HasNEON_HasFullFP16, // VMAXhd = 2663 19352 CEFBS_HasNEON_HasFullFP16, // VMAXhq = 2664 19353 CEFBS_HasNEON, // VMAXsv16i8 = 2665 19354 CEFBS_HasNEON, // VMAXsv2i32 = 2666 19355 CEFBS_HasNEON, // VMAXsv4i16 = 2667 19356 CEFBS_HasNEON, // VMAXsv4i32 = 2668 19357 CEFBS_HasNEON, // VMAXsv8i16 = 2669 19358 CEFBS_HasNEON, // VMAXsv8i8 = 2670 19359 CEFBS_HasNEON, // VMAXuv16i8 = 2671 19360 CEFBS_HasNEON, // VMAXuv2i32 = 2672 19361 CEFBS_HasNEON, // VMAXuv4i16 = 2673 19362 CEFBS_HasNEON, // VMAXuv4i32 = 2674 19363 CEFBS_HasNEON, // VMAXuv8i16 = 2675 19364 CEFBS_HasNEON, // VMAXuv8i8 = 2676 19365 CEFBS_HasNEON, // VMINfd = 2677 19366 CEFBS_HasNEON, // VMINfq = 2678 19367 CEFBS_HasNEON_HasFullFP16, // VMINhd = 2679 19368 CEFBS_HasNEON_HasFullFP16, // VMINhq = 2680 19369 CEFBS_HasNEON, // VMINsv16i8 = 2681 19370 CEFBS_HasNEON, // VMINsv2i32 = 2682 19371 CEFBS_HasNEON, // VMINsv4i16 = 2683 19372 CEFBS_HasNEON, // VMINsv4i32 = 2684 19373 CEFBS_HasNEON, // VMINsv8i16 = 2685 19374 CEFBS_HasNEON, // VMINsv8i8 = 2686 19375 CEFBS_HasNEON, // VMINuv16i8 = 2687 19376 CEFBS_HasNEON, // VMINuv2i32 = 2688 19377 CEFBS_HasNEON, // VMINuv4i16 = 2689 19378 CEFBS_HasNEON, // VMINuv4i32 = 2690 19379 CEFBS_HasNEON, // VMINuv8i16 = 2691 19380 CEFBS_HasNEON, // VMINuv8i8 = 2692 19381 CEFBS_HasVFP2_HasDPVFP, // VMLAD = 2693 19382 CEFBS_HasFullFP16, // VMLAH = 2694 19383 CEFBS_HasNEON, // VMLALslsv2i32 = 2695 19384 CEFBS_HasNEON, // VMLALslsv4i16 = 2696 19385 CEFBS_HasNEON, // VMLALsluv2i32 = 2697 19386 CEFBS_HasNEON, // VMLALsluv4i16 = 2698 19387 CEFBS_HasNEON, // VMLALsv2i64 = 2699 19388 CEFBS_HasNEON, // VMLALsv4i32 = 2700 19389 CEFBS_HasNEON, // VMLALsv8i16 = 2701 19390 CEFBS_HasNEON, // VMLALuv2i64 = 2702 19391 CEFBS_HasNEON, // VMLALuv4i32 = 2703 19392 CEFBS_HasNEON, // VMLALuv8i16 = 2704 19393 CEFBS_HasVFP2, // VMLAS = 2705 19394 CEFBS_HasNEON, // VMLAfd = 2706 19395 CEFBS_HasNEON, // VMLAfq = 2707 19396 CEFBS_HasNEON_HasFullFP16, // VMLAhd = 2708 19397 CEFBS_HasNEON_HasFullFP16, // VMLAhq = 2709 19398 CEFBS_HasNEON, // VMLAslfd = 2710 19399 CEFBS_HasNEON, // VMLAslfq = 2711 19400 CEFBS_HasNEON_HasFullFP16, // VMLAslhd = 2712 19401 CEFBS_HasNEON_HasFullFP16, // VMLAslhq = 2713 19402 CEFBS_HasNEON, // VMLAslv2i32 = 2714 19403 CEFBS_HasNEON, // VMLAslv4i16 = 2715 19404 CEFBS_HasNEON, // VMLAslv4i32 = 2716 19405 CEFBS_HasNEON, // VMLAslv8i16 = 2717 19406 CEFBS_HasNEON, // VMLAv16i8 = 2718 19407 CEFBS_HasNEON, // VMLAv2i32 = 2719 19408 CEFBS_HasNEON, // VMLAv4i16 = 2720 19409 CEFBS_HasNEON, // VMLAv4i32 = 2721 19410 CEFBS_HasNEON, // VMLAv8i16 = 2722 19411 CEFBS_HasNEON, // VMLAv8i8 = 2723 19412 CEFBS_HasVFP2_HasDPVFP, // VMLSD = 2724 19413 CEFBS_HasFullFP16, // VMLSH = 2725 19414 CEFBS_HasNEON, // VMLSLslsv2i32 = 2726 19415 CEFBS_HasNEON, // VMLSLslsv4i16 = 2727 19416 CEFBS_HasNEON, // VMLSLsluv2i32 = 2728 19417 CEFBS_HasNEON, // VMLSLsluv4i16 = 2729 19418 CEFBS_HasNEON, // VMLSLsv2i64 = 2730 19419 CEFBS_HasNEON, // VMLSLsv4i32 = 2731 19420 CEFBS_HasNEON, // VMLSLsv8i16 = 2732 19421 CEFBS_HasNEON, // VMLSLuv2i64 = 2733 19422 CEFBS_HasNEON, // VMLSLuv4i32 = 2734 19423 CEFBS_HasNEON, // VMLSLuv8i16 = 2735 19424 CEFBS_HasVFP2, // VMLSS = 2736 19425 CEFBS_HasNEON, // VMLSfd = 2737 19426 CEFBS_HasNEON, // VMLSfq = 2738 19427 CEFBS_HasNEON_HasFullFP16, // VMLShd = 2739 19428 CEFBS_HasNEON_HasFullFP16, // VMLShq = 2740 19429 CEFBS_HasNEON, // VMLSslfd = 2741 19430 CEFBS_HasNEON, // VMLSslfq = 2742 19431 CEFBS_HasNEON_HasFullFP16, // VMLSslhd = 2743 19432 CEFBS_HasNEON_HasFullFP16, // VMLSslhq = 2744 19433 CEFBS_HasNEON, // VMLSslv2i32 = 2745 19434 CEFBS_HasNEON, // VMLSslv4i16 = 2746 19435 CEFBS_HasNEON, // VMLSslv4i32 = 2747 19436 CEFBS_HasNEON, // VMLSslv8i16 = 2748 19437 CEFBS_HasNEON, // VMLSv16i8 = 2749 19438 CEFBS_HasNEON, // VMLSv2i32 = 2750 19439 CEFBS_HasNEON, // VMLSv4i16 = 2751 19440 CEFBS_HasNEON, // VMLSv4i32 = 2752 19441 CEFBS_HasNEON, // VMLSv8i16 = 2753 19442 CEFBS_HasNEON, // VMLSv8i8 = 2754 19443 CEFBS_HasFPRegs64, // VMOVD = 2755 19444 CEFBS_HasFPRegs, // VMOVDRR = 2756 19445 CEFBS_HasFullFP16, // VMOVH = 2757 19446 CEFBS_HasFPRegs16, // VMOVHR = 2758 19447 CEFBS_HasNEON, // VMOVLsv2i64 = 2759 19448 CEFBS_HasNEON, // VMOVLsv4i32 = 2760 19449 CEFBS_HasNEON, // VMOVLsv8i16 = 2761 19450 CEFBS_HasNEON, // VMOVLuv2i64 = 2762 19451 CEFBS_HasNEON, // VMOVLuv4i32 = 2763 19452 CEFBS_HasNEON, // VMOVLuv8i16 = 2764 19453 CEFBS_HasNEON, // VMOVNv2i32 = 2765 19454 CEFBS_HasNEON, // VMOVNv4i16 = 2766 19455 CEFBS_HasNEON, // VMOVNv8i8 = 2767 19456 CEFBS_HasFPRegs16, // VMOVRH = 2768 19457 CEFBS_HasFPRegs, // VMOVRRD = 2769 19458 CEFBS_HasFPRegs, // VMOVRRS = 2770 19459 CEFBS_HasFPRegs, // VMOVRS = 2771 19460 CEFBS_HasFPRegs, // VMOVS = 2772 19461 CEFBS_HasFPRegs, // VMOVSR = 2773 19462 CEFBS_HasFPRegs, // VMOVSRR = 2774 19463 CEFBS_HasNEON, // VMOVv16i8 = 2775 19464 CEFBS_HasNEON, // VMOVv1i64 = 2776 19465 CEFBS_HasNEON, // VMOVv2f32 = 2777 19466 CEFBS_HasNEON, // VMOVv2i32 = 2778 19467 CEFBS_HasNEON, // VMOVv2i64 = 2779 19468 CEFBS_HasNEON, // VMOVv4f32 = 2780 19469 CEFBS_HasNEON, // VMOVv4i16 = 2781 19470 CEFBS_HasNEON, // VMOVv4i32 = 2782 19471 CEFBS_HasNEON, // VMOVv8i16 = 2783 19472 CEFBS_HasNEON, // VMOVv8i8 = 2784 19473 CEFBS_HasFPRegs, // VMRS = 2785 19474 CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTNS = 2786 19475 CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTS = 2787 19476 CEFBS_HasVFP2, // VMRS_FPEXC = 2788 19477 CEFBS_HasVFP2, // VMRS_FPINST = 2789 19478 CEFBS_HasVFP2, // VMRS_FPINST2 = 2790 19479 CEFBS_HasV8_1MMainline_HasFPRegs, // VMRS_FPSCR_NZCVQC = 2791 19480 CEFBS_HasVFP2, // VMRS_FPSID = 2792 19481 CEFBS_HasVFP2, // VMRS_MVFR0 = 2793 19482 CEFBS_HasVFP2, // VMRS_MVFR1 = 2794 19483 CEFBS_HasFPARMv8, // VMRS_MVFR2 = 2795 19484 CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_P0 = 2796 19485 CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_VPR = 2797 19486 CEFBS_HasFPRegs, // VMSR = 2798 19487 CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTNS = 2799 19488 CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTS = 2800 19489 CEFBS_HasVFP2, // VMSR_FPEXC = 2801 19490 CEFBS_HasVFP2, // VMSR_FPINST = 2802 19491 CEFBS_HasVFP2, // VMSR_FPINST2 = 2803 19492 CEFBS_HasV8_1MMainline_HasFPRegs, // VMSR_FPSCR_NZCVQC = 2804 19493 CEFBS_HasVFP2, // VMSR_FPSID = 2805 19494 CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_P0 = 2806 19495 CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_VPR = 2807 19496 CEFBS_HasVFP2_HasDPVFP, // VMULD = 2808 19497 CEFBS_HasFullFP16, // VMULH = 2809 19498 CEFBS_HasV8_HasCrypto, // VMULLp64 = 2810 19499 CEFBS_HasNEON, // VMULLp8 = 2811 19500 CEFBS_HasNEON, // VMULLslsv2i32 = 2812 19501 CEFBS_HasNEON, // VMULLslsv4i16 = 2813 19502 CEFBS_HasNEON, // VMULLsluv2i32 = 2814 19503 CEFBS_HasNEON, // VMULLsluv4i16 = 2815 19504 CEFBS_HasNEON, // VMULLsv2i64 = 2816 19505 CEFBS_HasNEON, // VMULLsv4i32 = 2817 19506 CEFBS_HasNEON, // VMULLsv8i16 = 2818 19507 CEFBS_HasNEON, // VMULLuv2i64 = 2819 19508 CEFBS_HasNEON, // VMULLuv4i32 = 2820 19509 CEFBS_HasNEON, // VMULLuv8i16 = 2821 19510 CEFBS_HasVFP2, // VMULS = 2822 19511 CEFBS_HasNEON, // VMULfd = 2823 19512 CEFBS_HasNEON, // VMULfq = 2824 19513 CEFBS_HasNEON_HasFullFP16, // VMULhd = 2825 19514 CEFBS_HasNEON_HasFullFP16, // VMULhq = 2826 19515 CEFBS_HasNEON, // VMULpd = 2827 19516 CEFBS_HasNEON, // VMULpq = 2828 19517 CEFBS_HasNEON, // VMULslfd = 2829 19518 CEFBS_HasNEON, // VMULslfq = 2830 19519 CEFBS_HasNEON_HasFullFP16, // VMULslhd = 2831 19520 CEFBS_HasNEON_HasFullFP16, // VMULslhq = 2832 19521 CEFBS_HasNEON, // VMULslv2i32 = 2833 19522 CEFBS_HasNEON, // VMULslv4i16 = 2834 19523 CEFBS_HasNEON, // VMULslv4i32 = 2835 19524 CEFBS_HasNEON, // VMULslv8i16 = 2836 19525 CEFBS_HasNEON, // VMULv16i8 = 2837 19526 CEFBS_HasNEON, // VMULv2i32 = 2838 19527 CEFBS_HasNEON, // VMULv4i16 = 2839 19528 CEFBS_HasNEON, // VMULv4i32 = 2840 19529 CEFBS_HasNEON, // VMULv8i16 = 2841 19530 CEFBS_HasNEON, // VMULv8i8 = 2842 19531 CEFBS_HasNEON, // VMVNd = 2843 19532 CEFBS_HasNEON, // VMVNq = 2844 19533 CEFBS_HasNEON, // VMVNv2i32 = 2845 19534 CEFBS_HasNEON, // VMVNv4i16 = 2846 19535 CEFBS_HasNEON, // VMVNv4i32 = 2847 19536 CEFBS_HasNEON, // VMVNv8i16 = 2848 19537 CEFBS_HasVFP2_HasDPVFP, // VNEGD = 2849 19538 CEFBS_HasFullFP16, // VNEGH = 2850 19539 CEFBS_HasVFP2, // VNEGS = 2851 19540 CEFBS_HasNEON, // VNEGf32q = 2852 19541 CEFBS_HasNEON, // VNEGfd = 2853 19542 CEFBS_HasNEON_HasFullFP16, // VNEGhd = 2854 19543 CEFBS_HasNEON_HasFullFP16, // VNEGhq = 2855 19544 CEFBS_HasNEON, // VNEGs16d = 2856 19545 CEFBS_HasNEON, // VNEGs16q = 2857 19546 CEFBS_HasNEON, // VNEGs32d = 2858 19547 CEFBS_HasNEON, // VNEGs32q = 2859 19548 CEFBS_HasNEON, // VNEGs8d = 2860 19549 CEFBS_HasNEON, // VNEGs8q = 2861 19550 CEFBS_HasVFP2_HasDPVFP, // VNMLAD = 2862 19551 CEFBS_HasFullFP16, // VNMLAH = 2863 19552 CEFBS_HasVFP2, // VNMLAS = 2864 19553 CEFBS_HasVFP2_HasDPVFP, // VNMLSD = 2865 19554 CEFBS_HasFullFP16, // VNMLSH = 2866 19555 CEFBS_HasVFP2, // VNMLSS = 2867 19556 CEFBS_HasVFP2_HasDPVFP, // VNMULD = 2868 19557 CEFBS_HasFullFP16, // VNMULH = 2869 19558 CEFBS_HasVFP2, // VNMULS = 2870 19559 CEFBS_HasNEON, // VORNd = 2871 19560 CEFBS_HasNEON, // VORNq = 2872 19561 CEFBS_HasNEON, // VORRd = 2873 19562 CEFBS_HasNEON, // VORRiv2i32 = 2874 19563 CEFBS_HasNEON, // VORRiv4i16 = 2875 19564 CEFBS_HasNEON, // VORRiv4i32 = 2876 19565 CEFBS_HasNEON, // VORRiv8i16 = 2877 19566 CEFBS_HasNEON, // VORRq = 2878 19567 CEFBS_HasNEON, // VPADALsv16i8 = 2879 19568 CEFBS_HasNEON, // VPADALsv2i32 = 2880 19569 CEFBS_HasNEON, // VPADALsv4i16 = 2881 19570 CEFBS_HasNEON, // VPADALsv4i32 = 2882 19571 CEFBS_HasNEON, // VPADALsv8i16 = 2883 19572 CEFBS_HasNEON, // VPADALsv8i8 = 2884 19573 CEFBS_HasNEON, // VPADALuv16i8 = 2885 19574 CEFBS_HasNEON, // VPADALuv2i32 = 2886 19575 CEFBS_HasNEON, // VPADALuv4i16 = 2887 19576 CEFBS_HasNEON, // VPADALuv4i32 = 2888 19577 CEFBS_HasNEON, // VPADALuv8i16 = 2889 19578 CEFBS_HasNEON, // VPADALuv8i8 = 2890 19579 CEFBS_HasNEON, // VPADDLsv16i8 = 2891 19580 CEFBS_HasNEON, // VPADDLsv2i32 = 2892 19581 CEFBS_HasNEON, // VPADDLsv4i16 = 2893 19582 CEFBS_HasNEON, // VPADDLsv4i32 = 2894 19583 CEFBS_HasNEON, // VPADDLsv8i16 = 2895 19584 CEFBS_HasNEON, // VPADDLsv8i8 = 2896 19585 CEFBS_HasNEON, // VPADDLuv16i8 = 2897 19586 CEFBS_HasNEON, // VPADDLuv2i32 = 2898 19587 CEFBS_HasNEON, // VPADDLuv4i16 = 2899 19588 CEFBS_HasNEON, // VPADDLuv4i32 = 2900 19589 CEFBS_HasNEON, // VPADDLuv8i16 = 2901 19590 CEFBS_HasNEON, // VPADDLuv8i8 = 2902 19591 CEFBS_HasNEON, // VPADDf = 2903 19592 CEFBS_HasNEON_HasFullFP16, // VPADDh = 2904 19593 CEFBS_HasNEON, // VPADDi16 = 2905 19594 CEFBS_HasNEON, // VPADDi32 = 2906 19595 CEFBS_HasNEON, // VPADDi8 = 2907 19596 CEFBS_HasNEON, // VPMAXf = 2908 19597 CEFBS_HasNEON_HasFullFP16, // VPMAXh = 2909 19598 CEFBS_HasNEON, // VPMAXs16 = 2910 19599 CEFBS_HasNEON, // VPMAXs32 = 2911 19600 CEFBS_HasNEON, // VPMAXs8 = 2912 19601 CEFBS_HasNEON, // VPMAXu16 = 2913 19602 CEFBS_HasNEON, // VPMAXu32 = 2914 19603 CEFBS_HasNEON, // VPMAXu8 = 2915 19604 CEFBS_HasNEON, // VPMINf = 2916 19605 CEFBS_HasNEON_HasFullFP16, // VPMINh = 2917 19606 CEFBS_HasNEON, // VPMINs16 = 2918 19607 CEFBS_HasNEON, // VPMINs32 = 2919 19608 CEFBS_HasNEON, // VPMINs8 = 2920 19609 CEFBS_HasNEON, // VPMINu16 = 2921 19610 CEFBS_HasNEON, // VPMINu32 = 2922 19611 CEFBS_HasNEON, // VPMINu8 = 2923 19612 CEFBS_HasNEON, // VQABSv16i8 = 2924 19613 CEFBS_HasNEON, // VQABSv2i32 = 2925 19614 CEFBS_HasNEON, // VQABSv4i16 = 2926 19615 CEFBS_HasNEON, // VQABSv4i32 = 2927 19616 CEFBS_HasNEON, // VQABSv8i16 = 2928 19617 CEFBS_HasNEON, // VQABSv8i8 = 2929 19618 CEFBS_HasNEON, // VQADDsv16i8 = 2930 19619 CEFBS_HasNEON, // VQADDsv1i64 = 2931 19620 CEFBS_HasNEON, // VQADDsv2i32 = 2932 19621 CEFBS_HasNEON, // VQADDsv2i64 = 2933 19622 CEFBS_HasNEON, // VQADDsv4i16 = 2934 19623 CEFBS_HasNEON, // VQADDsv4i32 = 2935 19624 CEFBS_HasNEON, // VQADDsv8i16 = 2936 19625 CEFBS_HasNEON, // VQADDsv8i8 = 2937 19626 CEFBS_HasNEON, // VQADDuv16i8 = 2938 19627 CEFBS_HasNEON, // VQADDuv1i64 = 2939 19628 CEFBS_HasNEON, // VQADDuv2i32 = 2940 19629 CEFBS_HasNEON, // VQADDuv2i64 = 2941 19630 CEFBS_HasNEON, // VQADDuv4i16 = 2942 19631 CEFBS_HasNEON, // VQADDuv4i32 = 2943 19632 CEFBS_HasNEON, // VQADDuv8i16 = 2944 19633 CEFBS_HasNEON, // VQADDuv8i8 = 2945 19634 CEFBS_HasNEON, // VQDMLALslv2i32 = 2946 19635 CEFBS_HasNEON, // VQDMLALslv4i16 = 2947 19636 CEFBS_HasNEON, // VQDMLALv2i64 = 2948 19637 CEFBS_HasNEON, // VQDMLALv4i32 = 2949 19638 CEFBS_HasNEON, // VQDMLSLslv2i32 = 2950 19639 CEFBS_HasNEON, // VQDMLSLslv4i16 = 2951 19640 CEFBS_HasNEON, // VQDMLSLv2i64 = 2952 19641 CEFBS_HasNEON, // VQDMLSLv4i32 = 2953 19642 CEFBS_HasNEON, // VQDMULHslv2i32 = 2954 19643 CEFBS_HasNEON, // VQDMULHslv4i16 = 2955 19644 CEFBS_HasNEON, // VQDMULHslv4i32 = 2956 19645 CEFBS_HasNEON, // VQDMULHslv8i16 = 2957 19646 CEFBS_HasNEON, // VQDMULHv2i32 = 2958 19647 CEFBS_HasNEON, // VQDMULHv4i16 = 2959 19648 CEFBS_HasNEON, // VQDMULHv4i32 = 2960 19649 CEFBS_HasNEON, // VQDMULHv8i16 = 2961 19650 CEFBS_HasNEON, // VQDMULLslv2i32 = 2962 19651 CEFBS_HasNEON, // VQDMULLslv4i16 = 2963 19652 CEFBS_HasNEON, // VQDMULLv2i64 = 2964 19653 CEFBS_HasNEON, // VQDMULLv4i32 = 2965 19654 CEFBS_HasNEON, // VQMOVNsuv2i32 = 2966 19655 CEFBS_HasNEON, // VQMOVNsuv4i16 = 2967 19656 CEFBS_HasNEON, // VQMOVNsuv8i8 = 2968 19657 CEFBS_HasNEON, // VQMOVNsv2i32 = 2969 19658 CEFBS_HasNEON, // VQMOVNsv4i16 = 2970 19659 CEFBS_HasNEON, // VQMOVNsv8i8 = 2971 19660 CEFBS_HasNEON, // VQMOVNuv2i32 = 2972 19661 CEFBS_HasNEON, // VQMOVNuv4i16 = 2973 19662 CEFBS_HasNEON, // VQMOVNuv8i8 = 2974 19663 CEFBS_HasNEON, // VQNEGv16i8 = 2975 19664 CEFBS_HasNEON, // VQNEGv2i32 = 2976 19665 CEFBS_HasNEON, // VQNEGv4i16 = 2977 19666 CEFBS_HasNEON, // VQNEGv4i32 = 2978 19667 CEFBS_HasNEON, // VQNEGv8i16 = 2979 19668 CEFBS_HasNEON, // VQNEGv8i8 = 2980 19669 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv2i32 = 2981 19670 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i16 = 2982 19671 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i32 = 2983 19672 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv8i16 = 2984 19673 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv2i32 = 2985 19674 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i16 = 2986 19675 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i32 = 2987 19676 CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv8i16 = 2988 19677 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv2i32 = 2989 19678 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i16 = 2990 19679 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i32 = 2991 19680 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv8i16 = 2992 19681 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv2i32 = 2993 19682 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i16 = 2994 19683 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i32 = 2995 19684 CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv8i16 = 2996 19685 CEFBS_HasNEON, // VQRDMULHslv2i32 = 2997 19686 CEFBS_HasNEON, // VQRDMULHslv4i16 = 2998 19687 CEFBS_HasNEON, // VQRDMULHslv4i32 = 2999 19688 CEFBS_HasNEON, // VQRDMULHslv8i16 = 3000 19689 CEFBS_HasNEON, // VQRDMULHv2i32 = 3001 19690 CEFBS_HasNEON, // VQRDMULHv4i16 = 3002 19691 CEFBS_HasNEON, // VQRDMULHv4i32 = 3003 19692 CEFBS_HasNEON, // VQRDMULHv8i16 = 3004 19693 CEFBS_HasNEON, // VQRSHLsv16i8 = 3005 19694 CEFBS_HasNEON, // VQRSHLsv1i64 = 3006 19695 CEFBS_HasNEON, // VQRSHLsv2i32 = 3007 19696 CEFBS_HasNEON, // VQRSHLsv2i64 = 3008 19697 CEFBS_HasNEON, // VQRSHLsv4i16 = 3009 19698 CEFBS_HasNEON, // VQRSHLsv4i32 = 3010 19699 CEFBS_HasNEON, // VQRSHLsv8i16 = 3011 19700 CEFBS_HasNEON, // VQRSHLsv8i8 = 3012 19701 CEFBS_HasNEON, // VQRSHLuv16i8 = 3013 19702 CEFBS_HasNEON, // VQRSHLuv1i64 = 3014 19703 CEFBS_HasNEON, // VQRSHLuv2i32 = 3015 19704 CEFBS_HasNEON, // VQRSHLuv2i64 = 3016 19705 CEFBS_HasNEON, // VQRSHLuv4i16 = 3017 19706 CEFBS_HasNEON, // VQRSHLuv4i32 = 3018 19707 CEFBS_HasNEON, // VQRSHLuv8i16 = 3019 19708 CEFBS_HasNEON, // VQRSHLuv8i8 = 3020 19709 CEFBS_HasNEON, // VQRSHRNsv2i32 = 3021 19710 CEFBS_HasNEON, // VQRSHRNsv4i16 = 3022 19711 CEFBS_HasNEON, // VQRSHRNsv8i8 = 3023 19712 CEFBS_HasNEON, // VQRSHRNuv2i32 = 3024 19713 CEFBS_HasNEON, // VQRSHRNuv4i16 = 3025 19714 CEFBS_HasNEON, // VQRSHRNuv8i8 = 3026 19715 CEFBS_HasNEON, // VQRSHRUNv2i32 = 3027 19716 CEFBS_HasNEON, // VQRSHRUNv4i16 = 3028 19717 CEFBS_HasNEON, // VQRSHRUNv8i8 = 3029 19718 CEFBS_HasNEON, // VQSHLsiv16i8 = 3030 19719 CEFBS_HasNEON, // VQSHLsiv1i64 = 3031 19720 CEFBS_HasNEON, // VQSHLsiv2i32 = 3032 19721 CEFBS_HasNEON, // VQSHLsiv2i64 = 3033 19722 CEFBS_HasNEON, // VQSHLsiv4i16 = 3034 19723 CEFBS_HasNEON, // VQSHLsiv4i32 = 3035 19724 CEFBS_HasNEON, // VQSHLsiv8i16 = 3036 19725 CEFBS_HasNEON, // VQSHLsiv8i8 = 3037 19726 CEFBS_HasNEON, // VQSHLsuv16i8 = 3038 19727 CEFBS_HasNEON, // VQSHLsuv1i64 = 3039 19728 CEFBS_HasNEON, // VQSHLsuv2i32 = 3040 19729 CEFBS_HasNEON, // VQSHLsuv2i64 = 3041 19730 CEFBS_HasNEON, // VQSHLsuv4i16 = 3042 19731 CEFBS_HasNEON, // VQSHLsuv4i32 = 3043 19732 CEFBS_HasNEON, // VQSHLsuv8i16 = 3044 19733 CEFBS_HasNEON, // VQSHLsuv8i8 = 3045 19734 CEFBS_HasNEON, // VQSHLsv16i8 = 3046 19735 CEFBS_HasNEON, // VQSHLsv1i64 = 3047 19736 CEFBS_HasNEON, // VQSHLsv2i32 = 3048 19737 CEFBS_HasNEON, // VQSHLsv2i64 = 3049 19738 CEFBS_HasNEON, // VQSHLsv4i16 = 3050 19739 CEFBS_HasNEON, // VQSHLsv4i32 = 3051 19740 CEFBS_HasNEON, // VQSHLsv8i16 = 3052 19741 CEFBS_HasNEON, // VQSHLsv8i8 = 3053 19742 CEFBS_HasNEON, // VQSHLuiv16i8 = 3054 19743 CEFBS_HasNEON, // VQSHLuiv1i64 = 3055 19744 CEFBS_HasNEON, // VQSHLuiv2i32 = 3056 19745 CEFBS_HasNEON, // VQSHLuiv2i64 = 3057 19746 CEFBS_HasNEON, // VQSHLuiv4i16 = 3058 19747 CEFBS_HasNEON, // VQSHLuiv4i32 = 3059 19748 CEFBS_HasNEON, // VQSHLuiv8i16 = 3060 19749 CEFBS_HasNEON, // VQSHLuiv8i8 = 3061 19750 CEFBS_HasNEON, // VQSHLuv16i8 = 3062 19751 CEFBS_HasNEON, // VQSHLuv1i64 = 3063 19752 CEFBS_HasNEON, // VQSHLuv2i32 = 3064 19753 CEFBS_HasNEON, // VQSHLuv2i64 = 3065 19754 CEFBS_HasNEON, // VQSHLuv4i16 = 3066 19755 CEFBS_HasNEON, // VQSHLuv4i32 = 3067 19756 CEFBS_HasNEON, // VQSHLuv8i16 = 3068 19757 CEFBS_HasNEON, // VQSHLuv8i8 = 3069 19758 CEFBS_HasNEON, // VQSHRNsv2i32 = 3070 19759 CEFBS_HasNEON, // VQSHRNsv4i16 = 3071 19760 CEFBS_HasNEON, // VQSHRNsv8i8 = 3072 19761 CEFBS_HasNEON, // VQSHRNuv2i32 = 3073 19762 CEFBS_HasNEON, // VQSHRNuv4i16 = 3074 19763 CEFBS_HasNEON, // VQSHRNuv8i8 = 3075 19764 CEFBS_HasNEON, // VQSHRUNv2i32 = 3076 19765 CEFBS_HasNEON, // VQSHRUNv4i16 = 3077 19766 CEFBS_HasNEON, // VQSHRUNv8i8 = 3078 19767 CEFBS_HasNEON, // VQSUBsv16i8 = 3079 19768 CEFBS_HasNEON, // VQSUBsv1i64 = 3080 19769 CEFBS_HasNEON, // VQSUBsv2i32 = 3081 19770 CEFBS_HasNEON, // VQSUBsv2i64 = 3082 19771 CEFBS_HasNEON, // VQSUBsv4i16 = 3083 19772 CEFBS_HasNEON, // VQSUBsv4i32 = 3084 19773 CEFBS_HasNEON, // VQSUBsv8i16 = 3085 19774 CEFBS_HasNEON, // VQSUBsv8i8 = 3086 19775 CEFBS_HasNEON, // VQSUBuv16i8 = 3087 19776 CEFBS_HasNEON, // VQSUBuv1i64 = 3088 19777 CEFBS_HasNEON, // VQSUBuv2i32 = 3089 19778 CEFBS_HasNEON, // VQSUBuv2i64 = 3090 19779 CEFBS_HasNEON, // VQSUBuv4i16 = 3091 19780 CEFBS_HasNEON, // VQSUBuv4i32 = 3092 19781 CEFBS_HasNEON, // VQSUBuv8i16 = 3093 19782 CEFBS_HasNEON, // VQSUBuv8i8 = 3094 19783 CEFBS_HasNEON, // VRADDHNv2i32 = 3095 19784 CEFBS_HasNEON, // VRADDHNv4i16 = 3096 19785 CEFBS_HasNEON, // VRADDHNv8i8 = 3097 19786 CEFBS_HasNEON, // VRECPEd = 3098 19787 CEFBS_HasNEON, // VRECPEfd = 3099 19788 CEFBS_HasNEON, // VRECPEfq = 3100 19789 CEFBS_HasNEON_HasFullFP16, // VRECPEhd = 3101 19790 CEFBS_HasNEON_HasFullFP16, // VRECPEhq = 3102 19791 CEFBS_HasNEON, // VRECPEq = 3103 19792 CEFBS_HasNEON, // VRECPSfd = 3104 19793 CEFBS_HasNEON, // VRECPSfq = 3105 19794 CEFBS_HasNEON_HasFullFP16, // VRECPShd = 3106 19795 CEFBS_HasNEON_HasFullFP16, // VRECPShq = 3107 19796 CEFBS_HasNEON, // VREV16d8 = 3108 19797 CEFBS_HasNEON, // VREV16q8 = 3109 19798 CEFBS_HasNEON, // VREV32d16 = 3110 19799 CEFBS_HasNEON, // VREV32d8 = 3111 19800 CEFBS_HasNEON, // VREV32q16 = 3112 19801 CEFBS_HasNEON, // VREV32q8 = 3113 19802 CEFBS_HasNEON, // VREV64d16 = 3114 19803 CEFBS_HasNEON, // VREV64d32 = 3115 19804 CEFBS_HasNEON, // VREV64d8 = 3116 19805 CEFBS_HasNEON, // VREV64q16 = 3117 19806 CEFBS_HasNEON, // VREV64q32 = 3118 19807 CEFBS_HasNEON, // VREV64q8 = 3119 19808 CEFBS_HasNEON, // VRHADDsv16i8 = 3120 19809 CEFBS_HasNEON, // VRHADDsv2i32 = 3121 19810 CEFBS_HasNEON, // VRHADDsv4i16 = 3122 19811 CEFBS_HasNEON, // VRHADDsv4i32 = 3123 19812 CEFBS_HasNEON, // VRHADDsv8i16 = 3124 19813 CEFBS_HasNEON, // VRHADDsv8i8 = 3125 19814 CEFBS_HasNEON, // VRHADDuv16i8 = 3126 19815 CEFBS_HasNEON, // VRHADDuv2i32 = 3127 19816 CEFBS_HasNEON, // VRHADDuv4i16 = 3128 19817 CEFBS_HasNEON, // VRHADDuv4i32 = 3129 19818 CEFBS_HasNEON, // VRHADDuv8i16 = 3130 19819 CEFBS_HasNEON, // VRHADDuv8i8 = 3131 19820 CEFBS_HasFPARMv8_HasDPVFP, // VRINTAD = 3132 19821 CEFBS_HasFullFP16, // VRINTAH = 3133 19822 CEFBS_HasV8_HasNEON, // VRINTANDf = 3134 19823 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANDh = 3135 19824 CEFBS_HasV8_HasNEON, // VRINTANQf = 3136 19825 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANQh = 3137 19826 CEFBS_HasFPARMv8, // VRINTAS = 3138 19827 CEFBS_HasFPARMv8_HasDPVFP, // VRINTMD = 3139 19828 CEFBS_HasFullFP16, // VRINTMH = 3140 19829 CEFBS_HasV8_HasNEON, // VRINTMNDf = 3141 19830 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNDh = 3142 19831 CEFBS_HasV8_HasNEON, // VRINTMNQf = 3143 19832 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNQh = 3144 19833 CEFBS_HasFPARMv8, // VRINTMS = 3145 19834 CEFBS_HasFPARMv8_HasDPVFP, // VRINTND = 3146 19835 CEFBS_HasFullFP16, // VRINTNH = 3147 19836 CEFBS_HasV8_HasNEON, // VRINTNNDf = 3148 19837 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNDh = 3149 19838 CEFBS_HasV8_HasNEON, // VRINTNNQf = 3150 19839 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNQh = 3151 19840 CEFBS_HasFPARMv8, // VRINTNS = 3152 19841 CEFBS_HasFPARMv8_HasDPVFP, // VRINTPD = 3153 19842 CEFBS_HasFullFP16, // VRINTPH = 3154 19843 CEFBS_HasV8_HasNEON, // VRINTPNDf = 3155 19844 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNDh = 3156 19845 CEFBS_HasV8_HasNEON, // VRINTPNQf = 3157 19846 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNQh = 3158 19847 CEFBS_HasFPARMv8, // VRINTPS = 3159 19848 CEFBS_HasFPARMv8_HasDPVFP, // VRINTRD = 3160 19849 CEFBS_HasFullFP16, // VRINTRH = 3161 19850 CEFBS_HasFPARMv8, // VRINTRS = 3162 19851 CEFBS_HasFPARMv8_HasDPVFP, // VRINTXD = 3163 19852 CEFBS_HasFullFP16, // VRINTXH = 3164 19853 CEFBS_HasV8_HasNEON, // VRINTXNDf = 3165 19854 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNDh = 3166 19855 CEFBS_HasV8_HasNEON, // VRINTXNQf = 3167 19856 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNQh = 3168 19857 CEFBS_HasFPARMv8, // VRINTXS = 3169 19858 CEFBS_HasFPARMv8_HasDPVFP, // VRINTZD = 3170 19859 CEFBS_HasFullFP16, // VRINTZH = 3171 19860 CEFBS_HasV8_HasNEON, // VRINTZNDf = 3172 19861 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNDh = 3173 19862 CEFBS_HasV8_HasNEON, // VRINTZNQf = 3174 19863 CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNQh = 3175 19864 CEFBS_HasFPARMv8, // VRINTZS = 3176 19865 CEFBS_HasNEON, // VRSHLsv16i8 = 3177 19866 CEFBS_HasNEON, // VRSHLsv1i64 = 3178 19867 CEFBS_HasNEON, // VRSHLsv2i32 = 3179 19868 CEFBS_HasNEON, // VRSHLsv2i64 = 3180 19869 CEFBS_HasNEON, // VRSHLsv4i16 = 3181 19870 CEFBS_HasNEON, // VRSHLsv4i32 = 3182 19871 CEFBS_HasNEON, // VRSHLsv8i16 = 3183 19872 CEFBS_HasNEON, // VRSHLsv8i8 = 3184 19873 CEFBS_HasNEON, // VRSHLuv16i8 = 3185 19874 CEFBS_HasNEON, // VRSHLuv1i64 = 3186 19875 CEFBS_HasNEON, // VRSHLuv2i32 = 3187 19876 CEFBS_HasNEON, // VRSHLuv2i64 = 3188 19877 CEFBS_HasNEON, // VRSHLuv4i16 = 3189 19878 CEFBS_HasNEON, // VRSHLuv4i32 = 3190 19879 CEFBS_HasNEON, // VRSHLuv8i16 = 3191 19880 CEFBS_HasNEON, // VRSHLuv8i8 = 3192 19881 CEFBS_HasNEON, // VRSHRNv2i32 = 3193 19882 CEFBS_HasNEON, // VRSHRNv4i16 = 3194 19883 CEFBS_HasNEON, // VRSHRNv8i8 = 3195 19884 CEFBS_HasNEON, // VRSHRsv16i8 = 3196 19885 CEFBS_HasNEON, // VRSHRsv1i64 = 3197 19886 CEFBS_HasNEON, // VRSHRsv2i32 = 3198 19887 CEFBS_HasNEON, // VRSHRsv2i64 = 3199 19888 CEFBS_HasNEON, // VRSHRsv4i16 = 3200 19889 CEFBS_HasNEON, // VRSHRsv4i32 = 3201 19890 CEFBS_HasNEON, // VRSHRsv8i16 = 3202 19891 CEFBS_HasNEON, // VRSHRsv8i8 = 3203 19892 CEFBS_HasNEON, // VRSHRuv16i8 = 3204 19893 CEFBS_HasNEON, // VRSHRuv1i64 = 3205 19894 CEFBS_HasNEON, // VRSHRuv2i32 = 3206 19895 CEFBS_HasNEON, // VRSHRuv2i64 = 3207 19896 CEFBS_HasNEON, // VRSHRuv4i16 = 3208 19897 CEFBS_HasNEON, // VRSHRuv4i32 = 3209 19898 CEFBS_HasNEON, // VRSHRuv8i16 = 3210 19899 CEFBS_HasNEON, // VRSHRuv8i8 = 3211 19900 CEFBS_HasNEON, // VRSQRTEd = 3212 19901 CEFBS_HasNEON, // VRSQRTEfd = 3213 19902 CEFBS_HasNEON, // VRSQRTEfq = 3214 19903 CEFBS_HasNEON_HasFullFP16, // VRSQRTEhd = 3215 19904 CEFBS_HasNEON_HasFullFP16, // VRSQRTEhq = 3216 19905 CEFBS_HasNEON, // VRSQRTEq = 3217 19906 CEFBS_HasNEON, // VRSQRTSfd = 3218 19907 CEFBS_HasNEON, // VRSQRTSfq = 3219 19908 CEFBS_HasNEON_HasFullFP16, // VRSQRTShd = 3220 19909 CEFBS_HasNEON_HasFullFP16, // VRSQRTShq = 3221 19910 CEFBS_HasNEON, // VRSRAsv16i8 = 3222 19911 CEFBS_HasNEON, // VRSRAsv1i64 = 3223 19912 CEFBS_HasNEON, // VRSRAsv2i32 = 3224 19913 CEFBS_HasNEON, // VRSRAsv2i64 = 3225 19914 CEFBS_HasNEON, // VRSRAsv4i16 = 3226 19915 CEFBS_HasNEON, // VRSRAsv4i32 = 3227 19916 CEFBS_HasNEON, // VRSRAsv8i16 = 3228 19917 CEFBS_HasNEON, // VRSRAsv8i8 = 3229 19918 CEFBS_HasNEON, // VRSRAuv16i8 = 3230 19919 CEFBS_HasNEON, // VRSRAuv1i64 = 3231 19920 CEFBS_HasNEON, // VRSRAuv2i32 = 3232 19921 CEFBS_HasNEON, // VRSRAuv2i64 = 3233 19922 CEFBS_HasNEON, // VRSRAuv4i16 = 3234 19923 CEFBS_HasNEON, // VRSRAuv4i32 = 3235 19924 CEFBS_HasNEON, // VRSRAuv8i16 = 3236 19925 CEFBS_HasNEON, // VRSRAuv8i8 = 3237 19926 CEFBS_HasNEON, // VRSUBHNv2i32 = 3238 19927 CEFBS_HasNEON, // VRSUBHNv4i16 = 3239 19928 CEFBS_HasNEON, // VRSUBHNv8i8 = 3240 19929 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMD = 3241 19930 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMS = 3242 19931 CEFBS_HasDotProd, // VSDOTD = 3243 19932 CEFBS_HasDotProd, // VSDOTDI = 3244 19933 CEFBS_HasDotProd, // VSDOTQ = 3245 19934 CEFBS_HasDotProd, // VSDOTQI = 3246 19935 CEFBS_HasFPARMv8_HasDPVFP, // VSELEQD = 3247 19936 CEFBS_HasFullFP16, // VSELEQH = 3248 19937 CEFBS_HasFPARMv8, // VSELEQS = 3249 19938 CEFBS_HasFPARMv8_HasDPVFP, // VSELGED = 3250 19939 CEFBS_HasFullFP16, // VSELGEH = 3251 19940 CEFBS_HasFPARMv8, // VSELGES = 3252 19941 CEFBS_HasFPARMv8_HasDPVFP, // VSELGTD = 3253 19942 CEFBS_HasFullFP16, // VSELGTH = 3254 19943 CEFBS_HasFPARMv8, // VSELGTS = 3255 19944 CEFBS_HasFPARMv8_HasDPVFP, // VSELVSD = 3256 19945 CEFBS_HasFullFP16, // VSELVSH = 3257 19946 CEFBS_HasFPARMv8, // VSELVSS = 3258 19947 CEFBS_HasNEON, // VSETLNi16 = 3259 19948 CEFBS_HasVFP2, // VSETLNi32 = 3260 19949 CEFBS_HasNEON, // VSETLNi8 = 3261 19950 CEFBS_HasNEON, // VSHLLi16 = 3262 19951 CEFBS_HasNEON, // VSHLLi32 = 3263 19952 CEFBS_HasNEON, // VSHLLi8 = 3264 19953 CEFBS_HasNEON, // VSHLLsv2i64 = 3265 19954 CEFBS_HasNEON, // VSHLLsv4i32 = 3266 19955 CEFBS_HasNEON, // VSHLLsv8i16 = 3267 19956 CEFBS_HasNEON, // VSHLLuv2i64 = 3268 19957 CEFBS_HasNEON, // VSHLLuv4i32 = 3269 19958 CEFBS_HasNEON, // VSHLLuv8i16 = 3270 19959 CEFBS_HasNEON, // VSHLiv16i8 = 3271 19960 CEFBS_HasNEON, // VSHLiv1i64 = 3272 19961 CEFBS_HasNEON, // VSHLiv2i32 = 3273 19962 CEFBS_HasNEON, // VSHLiv2i64 = 3274 19963 CEFBS_HasNEON, // VSHLiv4i16 = 3275 19964 CEFBS_HasNEON, // VSHLiv4i32 = 3276 19965 CEFBS_HasNEON, // VSHLiv8i16 = 3277 19966 CEFBS_HasNEON, // VSHLiv8i8 = 3278 19967 CEFBS_HasNEON, // VSHLsv16i8 = 3279 19968 CEFBS_HasNEON, // VSHLsv1i64 = 3280 19969 CEFBS_HasNEON, // VSHLsv2i32 = 3281 19970 CEFBS_HasNEON, // VSHLsv2i64 = 3282 19971 CEFBS_HasNEON, // VSHLsv4i16 = 3283 19972 CEFBS_HasNEON, // VSHLsv4i32 = 3284 19973 CEFBS_HasNEON, // VSHLsv8i16 = 3285 19974 CEFBS_HasNEON, // VSHLsv8i8 = 3286 19975 CEFBS_HasNEON, // VSHLuv16i8 = 3287 19976 CEFBS_HasNEON, // VSHLuv1i64 = 3288 19977 CEFBS_HasNEON, // VSHLuv2i32 = 3289 19978 CEFBS_HasNEON, // VSHLuv2i64 = 3290 19979 CEFBS_HasNEON, // VSHLuv4i16 = 3291 19980 CEFBS_HasNEON, // VSHLuv4i32 = 3292 19981 CEFBS_HasNEON, // VSHLuv8i16 = 3293 19982 CEFBS_HasNEON, // VSHLuv8i8 = 3294 19983 CEFBS_HasNEON, // VSHRNv2i32 = 3295 19984 CEFBS_HasNEON, // VSHRNv4i16 = 3296 19985 CEFBS_HasNEON, // VSHRNv8i8 = 3297 19986 CEFBS_HasNEON, // VSHRsv16i8 = 3298 19987 CEFBS_HasNEON, // VSHRsv1i64 = 3299 19988 CEFBS_HasNEON, // VSHRsv2i32 = 3300 19989 CEFBS_HasNEON, // VSHRsv2i64 = 3301 19990 CEFBS_HasNEON, // VSHRsv4i16 = 3302 19991 CEFBS_HasNEON, // VSHRsv4i32 = 3303 19992 CEFBS_HasNEON, // VSHRsv8i16 = 3304 19993 CEFBS_HasNEON, // VSHRsv8i8 = 3305 19994 CEFBS_HasNEON, // VSHRuv16i8 = 3306 19995 CEFBS_HasNEON, // VSHRuv1i64 = 3307 19996 CEFBS_HasNEON, // VSHRuv2i32 = 3308 19997 CEFBS_HasNEON, // VSHRuv2i64 = 3309 19998 CEFBS_HasNEON, // VSHRuv4i16 = 3310 19999 CEFBS_HasNEON, // VSHRuv4i32 = 3311 20000 CEFBS_HasNEON, // VSHRuv8i16 = 3312 20001 CEFBS_HasNEON, // VSHRuv8i8 = 3313 20002 CEFBS_HasVFP2_HasDPVFP, // VSHTOD = 3314 20003 CEFBS_HasFullFP16, // VSHTOH = 3315 20004 CEFBS_HasVFP2, // VSHTOS = 3316 20005 CEFBS_HasVFP2_HasDPVFP, // VSITOD = 3317 20006 CEFBS_HasFullFP16, // VSITOH = 3318 20007 CEFBS_HasVFP2, // VSITOS = 3319 20008 CEFBS_HasNEON, // VSLIv16i8 = 3320 20009 CEFBS_HasNEON, // VSLIv1i64 = 3321 20010 CEFBS_HasNEON, // VSLIv2i32 = 3322 20011 CEFBS_HasNEON, // VSLIv2i64 = 3323 20012 CEFBS_HasNEON, // VSLIv4i16 = 3324 20013 CEFBS_HasNEON, // VSLIv4i32 = 3325 20014 CEFBS_HasNEON, // VSLIv8i16 = 3326 20015 CEFBS_HasNEON, // VSLIv8i8 = 3327 20016 CEFBS_HasVFP2_HasDPVFP, // VSLTOD = 3328 20017 CEFBS_HasFullFP16, // VSLTOH = 3329 20018 CEFBS_HasVFP2, // VSLTOS = 3330 20019 CEFBS_HasVFP2_HasDPVFP, // VSQRTD = 3331 20020 CEFBS_HasFullFP16, // VSQRTH = 3332 20021 CEFBS_HasVFP2, // VSQRTS = 3333 20022 CEFBS_HasNEON, // VSRAsv16i8 = 3334 20023 CEFBS_HasNEON, // VSRAsv1i64 = 3335 20024 CEFBS_HasNEON, // VSRAsv2i32 = 3336 20025 CEFBS_HasNEON, // VSRAsv2i64 = 3337 20026 CEFBS_HasNEON, // VSRAsv4i16 = 3338 20027 CEFBS_HasNEON, // VSRAsv4i32 = 3339 20028 CEFBS_HasNEON, // VSRAsv8i16 = 3340 20029 CEFBS_HasNEON, // VSRAsv8i8 = 3341 20030 CEFBS_HasNEON, // VSRAuv16i8 = 3342 20031 CEFBS_HasNEON, // VSRAuv1i64 = 3343 20032 CEFBS_HasNEON, // VSRAuv2i32 = 3344 20033 CEFBS_HasNEON, // VSRAuv2i64 = 3345 20034 CEFBS_HasNEON, // VSRAuv4i16 = 3346 20035 CEFBS_HasNEON, // VSRAuv4i32 = 3347 20036 CEFBS_HasNEON, // VSRAuv8i16 = 3348 20037 CEFBS_HasNEON, // VSRAuv8i8 = 3349 20038 CEFBS_HasNEON, // VSRIv16i8 = 3350 20039 CEFBS_HasNEON, // VSRIv1i64 = 3351 20040 CEFBS_HasNEON, // VSRIv2i32 = 3352 20041 CEFBS_HasNEON, // VSRIv2i64 = 3353 20042 CEFBS_HasNEON, // VSRIv4i16 = 3354 20043 CEFBS_HasNEON, // VSRIv4i32 = 3355 20044 CEFBS_HasNEON, // VSRIv8i16 = 3356 20045 CEFBS_HasNEON, // VSRIv8i8 = 3357 20046 CEFBS_HasNEON, // VST1LNd16 = 3358 20047 CEFBS_HasNEON, // VST1LNd16_UPD = 3359 20048 CEFBS_HasNEON, // VST1LNd32 = 3360 20049 CEFBS_HasNEON, // VST1LNd32_UPD = 3361 20050 CEFBS_HasNEON, // VST1LNd8 = 3362 20051 CEFBS_HasNEON, // VST1LNd8_UPD = 3363 20052 CEFBS_HasNEON, // VST1LNq16Pseudo = 3364 20053 CEFBS_HasNEON, // VST1LNq16Pseudo_UPD = 3365 20054 CEFBS_HasNEON, // VST1LNq32Pseudo = 3366 20055 CEFBS_HasNEON, // VST1LNq32Pseudo_UPD = 3367 20056 CEFBS_HasNEON, // VST1LNq8Pseudo = 3368 20057 CEFBS_HasNEON, // VST1LNq8Pseudo_UPD = 3369 20058 CEFBS_HasNEON, // VST1d16 = 3370 20059 CEFBS_HasNEON, // VST1d16Q = 3371 20060 CEFBS_HasNEON, // VST1d16QPseudo = 3372 20061 CEFBS_HasNEON, // VST1d16Qwb_fixed = 3373 20062 CEFBS_HasNEON, // VST1d16Qwb_register = 3374 20063 CEFBS_HasNEON, // VST1d16T = 3375 20064 CEFBS_HasNEON, // VST1d16TPseudo = 3376 20065 CEFBS_HasNEON, // VST1d16Twb_fixed = 3377 20066 CEFBS_HasNEON, // VST1d16Twb_register = 3378 20067 CEFBS_HasNEON, // VST1d16wb_fixed = 3379 20068 CEFBS_HasNEON, // VST1d16wb_register = 3380 20069 CEFBS_HasNEON, // VST1d32 = 3381 20070 CEFBS_HasNEON, // VST1d32Q = 3382 20071 CEFBS_HasNEON, // VST1d32QPseudo = 3383 20072 CEFBS_HasNEON, // VST1d32Qwb_fixed = 3384 20073 CEFBS_HasNEON, // VST1d32Qwb_register = 3385 20074 CEFBS_HasNEON, // VST1d32T = 3386 20075 CEFBS_HasNEON, // VST1d32TPseudo = 3387 20076 CEFBS_HasNEON, // VST1d32Twb_fixed = 3388 20077 CEFBS_HasNEON, // VST1d32Twb_register = 3389 20078 CEFBS_HasNEON, // VST1d32wb_fixed = 3390 20079 CEFBS_HasNEON, // VST1d32wb_register = 3391 20080 CEFBS_HasNEON, // VST1d64 = 3392 20081 CEFBS_HasNEON, // VST1d64Q = 3393 20082 CEFBS_HasNEON, // VST1d64QPseudo = 3394 20083 CEFBS_HasNEON, // VST1d64QPseudoWB_fixed = 3395 20084 CEFBS_HasNEON, // VST1d64QPseudoWB_register = 3396 20085 CEFBS_HasNEON, // VST1d64Qwb_fixed = 3397 20086 CEFBS_HasNEON, // VST1d64Qwb_register = 3398 20087 CEFBS_HasNEON, // VST1d64T = 3399 20088 CEFBS_HasNEON, // VST1d64TPseudo = 3400 20089 CEFBS_HasNEON, // VST1d64TPseudoWB_fixed = 3401 20090 CEFBS_HasNEON, // VST1d64TPseudoWB_register = 3402 20091 CEFBS_HasNEON, // VST1d64Twb_fixed = 3403 20092 CEFBS_HasNEON, // VST1d64Twb_register = 3404 20093 CEFBS_HasNEON, // VST1d64wb_fixed = 3405 20094 CEFBS_HasNEON, // VST1d64wb_register = 3406 20095 CEFBS_HasNEON, // VST1d8 = 3407 20096 CEFBS_HasNEON, // VST1d8Q = 3408 20097 CEFBS_HasNEON, // VST1d8QPseudo = 3409 20098 CEFBS_HasNEON, // VST1d8Qwb_fixed = 3410 20099 CEFBS_HasNEON, // VST1d8Qwb_register = 3411 20100 CEFBS_HasNEON, // VST1d8T = 3412 20101 CEFBS_HasNEON, // VST1d8TPseudo = 3413 20102 CEFBS_HasNEON, // VST1d8Twb_fixed = 3414 20103 CEFBS_HasNEON, // VST1d8Twb_register = 3415 20104 CEFBS_HasNEON, // VST1d8wb_fixed = 3416 20105 CEFBS_HasNEON, // VST1d8wb_register = 3417 20106 CEFBS_HasNEON, // VST1q16 = 3418 20107 CEFBS_HasNEON, // VST1q16HighQPseudo = 3419 20108 CEFBS_HasNEON, // VST1q16HighTPseudo = 3420 20109 CEFBS_HasNEON, // VST1q16LowQPseudo_UPD = 3421 20110 CEFBS_HasNEON, // VST1q16LowTPseudo_UPD = 3422 20111 CEFBS_HasNEON, // VST1q16wb_fixed = 3423 20112 CEFBS_HasNEON, // VST1q16wb_register = 3424 20113 CEFBS_HasNEON, // VST1q32 = 3425 20114 CEFBS_HasNEON, // VST1q32HighQPseudo = 3426 20115 CEFBS_HasNEON, // VST1q32HighTPseudo = 3427 20116 CEFBS_HasNEON, // VST1q32LowQPseudo_UPD = 3428 20117 CEFBS_HasNEON, // VST1q32LowTPseudo_UPD = 3429 20118 CEFBS_HasNEON, // VST1q32wb_fixed = 3430 20119 CEFBS_HasNEON, // VST1q32wb_register = 3431 20120 CEFBS_HasNEON, // VST1q64 = 3432 20121 CEFBS_HasNEON, // VST1q64HighQPseudo = 3433 20122 CEFBS_HasNEON, // VST1q64HighTPseudo = 3434 20123 CEFBS_HasNEON, // VST1q64LowQPseudo_UPD = 3435 20124 CEFBS_HasNEON, // VST1q64LowTPseudo_UPD = 3436 20125 CEFBS_HasNEON, // VST1q64wb_fixed = 3437 20126 CEFBS_HasNEON, // VST1q64wb_register = 3438 20127 CEFBS_HasNEON, // VST1q8 = 3439 20128 CEFBS_HasNEON, // VST1q8HighQPseudo = 3440 20129 CEFBS_HasNEON, // VST1q8HighTPseudo = 3441 20130 CEFBS_HasNEON, // VST1q8LowQPseudo_UPD = 3442 20131 CEFBS_HasNEON, // VST1q8LowTPseudo_UPD = 3443 20132 CEFBS_HasNEON, // VST1q8wb_fixed = 3444 20133 CEFBS_HasNEON, // VST1q8wb_register = 3445 20134 CEFBS_HasNEON, // VST2LNd16 = 3446 20135 CEFBS_HasNEON, // VST2LNd16Pseudo = 3447 20136 CEFBS_HasNEON, // VST2LNd16Pseudo_UPD = 3448 20137 CEFBS_HasNEON, // VST2LNd16_UPD = 3449 20138 CEFBS_HasNEON, // VST2LNd32 = 3450 20139 CEFBS_HasNEON, // VST2LNd32Pseudo = 3451 20140 CEFBS_HasNEON, // VST2LNd32Pseudo_UPD = 3452 20141 CEFBS_HasNEON, // VST2LNd32_UPD = 3453 20142 CEFBS_HasNEON, // VST2LNd8 = 3454 20143 CEFBS_HasNEON, // VST2LNd8Pseudo = 3455 20144 CEFBS_HasNEON, // VST2LNd8Pseudo_UPD = 3456 20145 CEFBS_HasNEON, // VST2LNd8_UPD = 3457 20146 CEFBS_HasNEON, // VST2LNq16 = 3458 20147 CEFBS_HasNEON, // VST2LNq16Pseudo = 3459 20148 CEFBS_HasNEON, // VST2LNq16Pseudo_UPD = 3460 20149 CEFBS_HasNEON, // VST2LNq16_UPD = 3461 20150 CEFBS_HasNEON, // VST2LNq32 = 3462 20151 CEFBS_HasNEON, // VST2LNq32Pseudo = 3463 20152 CEFBS_HasNEON, // VST2LNq32Pseudo_UPD = 3464 20153 CEFBS_HasNEON, // VST2LNq32_UPD = 3465 20154 CEFBS_HasNEON, // VST2b16 = 3466 20155 CEFBS_HasNEON, // VST2b16wb_fixed = 3467 20156 CEFBS_HasNEON, // VST2b16wb_register = 3468 20157 CEFBS_HasNEON, // VST2b32 = 3469 20158 CEFBS_HasNEON, // VST2b32wb_fixed = 3470 20159 CEFBS_HasNEON, // VST2b32wb_register = 3471 20160 CEFBS_HasNEON, // VST2b8 = 3472 20161 CEFBS_HasNEON, // VST2b8wb_fixed = 3473 20162 CEFBS_HasNEON, // VST2b8wb_register = 3474 20163 CEFBS_HasNEON, // VST2d16 = 3475 20164 CEFBS_HasNEON, // VST2d16wb_fixed = 3476 20165 CEFBS_HasNEON, // VST2d16wb_register = 3477 20166 CEFBS_HasNEON, // VST2d32 = 3478 20167 CEFBS_HasNEON, // VST2d32wb_fixed = 3479 20168 CEFBS_HasNEON, // VST2d32wb_register = 3480 20169 CEFBS_HasNEON, // VST2d8 = 3481 20170 CEFBS_HasNEON, // VST2d8wb_fixed = 3482 20171 CEFBS_HasNEON, // VST2d8wb_register = 3483 20172 CEFBS_HasNEON, // VST2q16 = 3484 20173 CEFBS_HasNEON, // VST2q16Pseudo = 3485 20174 CEFBS_HasNEON, // VST2q16PseudoWB_fixed = 3486 20175 CEFBS_HasNEON, // VST2q16PseudoWB_register = 3487 20176 CEFBS_HasNEON, // VST2q16wb_fixed = 3488 20177 CEFBS_HasNEON, // VST2q16wb_register = 3489 20178 CEFBS_HasNEON, // VST2q32 = 3490 20179 CEFBS_HasNEON, // VST2q32Pseudo = 3491 20180 CEFBS_HasNEON, // VST2q32PseudoWB_fixed = 3492 20181 CEFBS_HasNEON, // VST2q32PseudoWB_register = 3493 20182 CEFBS_HasNEON, // VST2q32wb_fixed = 3494 20183 CEFBS_HasNEON, // VST2q32wb_register = 3495 20184 CEFBS_HasNEON, // VST2q8 = 3496 20185 CEFBS_HasNEON, // VST2q8Pseudo = 3497 20186 CEFBS_HasNEON, // VST2q8PseudoWB_fixed = 3498 20187 CEFBS_HasNEON, // VST2q8PseudoWB_register = 3499 20188 CEFBS_HasNEON, // VST2q8wb_fixed = 3500 20189 CEFBS_HasNEON, // VST2q8wb_register = 3501 20190 CEFBS_HasNEON, // VST3LNd16 = 3502 20191 CEFBS_HasNEON, // VST3LNd16Pseudo = 3503 20192 CEFBS_HasNEON, // VST3LNd16Pseudo_UPD = 3504 20193 CEFBS_HasNEON, // VST3LNd16_UPD = 3505 20194 CEFBS_HasNEON, // VST3LNd32 = 3506 20195 CEFBS_HasNEON, // VST3LNd32Pseudo = 3507 20196 CEFBS_HasNEON, // VST3LNd32Pseudo_UPD = 3508 20197 CEFBS_HasNEON, // VST3LNd32_UPD = 3509 20198 CEFBS_HasNEON, // VST3LNd8 = 3510 20199 CEFBS_HasNEON, // VST3LNd8Pseudo = 3511 20200 CEFBS_HasNEON, // VST3LNd8Pseudo_UPD = 3512 20201 CEFBS_HasNEON, // VST3LNd8_UPD = 3513 20202 CEFBS_HasNEON, // VST3LNq16 = 3514 20203 CEFBS_HasNEON, // VST3LNq16Pseudo = 3515 20204 CEFBS_HasNEON, // VST3LNq16Pseudo_UPD = 3516 20205 CEFBS_HasNEON, // VST3LNq16_UPD = 3517 20206 CEFBS_HasNEON, // VST3LNq32 = 3518 20207 CEFBS_HasNEON, // VST3LNq32Pseudo = 3519 20208 CEFBS_HasNEON, // VST3LNq32Pseudo_UPD = 3520 20209 CEFBS_HasNEON, // VST3LNq32_UPD = 3521 20210 CEFBS_HasNEON, // VST3d16 = 3522 20211 CEFBS_HasNEON, // VST3d16Pseudo = 3523 20212 CEFBS_HasNEON, // VST3d16Pseudo_UPD = 3524 20213 CEFBS_HasNEON, // VST3d16_UPD = 3525 20214 CEFBS_HasNEON, // VST3d32 = 3526 20215 CEFBS_HasNEON, // VST3d32Pseudo = 3527 20216 CEFBS_HasNEON, // VST3d32Pseudo_UPD = 3528 20217 CEFBS_HasNEON, // VST3d32_UPD = 3529 20218 CEFBS_HasNEON, // VST3d8 = 3530 20219 CEFBS_HasNEON, // VST3d8Pseudo = 3531 20220 CEFBS_HasNEON, // VST3d8Pseudo_UPD = 3532 20221 CEFBS_HasNEON, // VST3d8_UPD = 3533 20222 CEFBS_HasNEON, // VST3q16 = 3534 20223 CEFBS_HasNEON, // VST3q16Pseudo_UPD = 3535 20224 CEFBS_HasNEON, // VST3q16_UPD = 3536 20225 CEFBS_HasNEON, // VST3q16oddPseudo = 3537 20226 CEFBS_HasNEON, // VST3q16oddPseudo_UPD = 3538 20227 CEFBS_HasNEON, // VST3q32 = 3539 20228 CEFBS_HasNEON, // VST3q32Pseudo_UPD = 3540 20229 CEFBS_HasNEON, // VST3q32_UPD = 3541 20230 CEFBS_HasNEON, // VST3q32oddPseudo = 3542 20231 CEFBS_HasNEON, // VST3q32oddPseudo_UPD = 3543 20232 CEFBS_HasNEON, // VST3q8 = 3544 20233 CEFBS_HasNEON, // VST3q8Pseudo_UPD = 3545 20234 CEFBS_HasNEON, // VST3q8_UPD = 3546 20235 CEFBS_HasNEON, // VST3q8oddPseudo = 3547 20236 CEFBS_HasNEON, // VST3q8oddPseudo_UPD = 3548 20237 CEFBS_HasNEON, // VST4LNd16 = 3549 20238 CEFBS_HasNEON, // VST4LNd16Pseudo = 3550 20239 CEFBS_HasNEON, // VST4LNd16Pseudo_UPD = 3551 20240 CEFBS_HasNEON, // VST4LNd16_UPD = 3552 20241 CEFBS_HasNEON, // VST4LNd32 = 3553 20242 CEFBS_HasNEON, // VST4LNd32Pseudo = 3554 20243 CEFBS_HasNEON, // VST4LNd32Pseudo_UPD = 3555 20244 CEFBS_HasNEON, // VST4LNd32_UPD = 3556 20245 CEFBS_HasNEON, // VST4LNd8 = 3557 20246 CEFBS_HasNEON, // VST4LNd8Pseudo = 3558 20247 CEFBS_HasNEON, // VST4LNd8Pseudo_UPD = 3559 20248 CEFBS_HasNEON, // VST4LNd8_UPD = 3560 20249 CEFBS_HasNEON, // VST4LNq16 = 3561 20250 CEFBS_HasNEON, // VST4LNq16Pseudo = 3562 20251 CEFBS_HasNEON, // VST4LNq16Pseudo_UPD = 3563 20252 CEFBS_HasNEON, // VST4LNq16_UPD = 3564 20253 CEFBS_HasNEON, // VST4LNq32 = 3565 20254 CEFBS_HasNEON, // VST4LNq32Pseudo = 3566 20255 CEFBS_HasNEON, // VST4LNq32Pseudo_UPD = 3567 20256 CEFBS_HasNEON, // VST4LNq32_UPD = 3568 20257 CEFBS_HasNEON, // VST4d16 = 3569 20258 CEFBS_HasNEON, // VST4d16Pseudo = 3570 20259 CEFBS_HasNEON, // VST4d16Pseudo_UPD = 3571 20260 CEFBS_HasNEON, // VST4d16_UPD = 3572 20261 CEFBS_HasNEON, // VST4d32 = 3573 20262 CEFBS_HasNEON, // VST4d32Pseudo = 3574 20263 CEFBS_HasNEON, // VST4d32Pseudo_UPD = 3575 20264 CEFBS_HasNEON, // VST4d32_UPD = 3576 20265 CEFBS_HasNEON, // VST4d8 = 3577 20266 CEFBS_HasNEON, // VST4d8Pseudo = 3578 20267 CEFBS_HasNEON, // VST4d8Pseudo_UPD = 3579 20268 CEFBS_HasNEON, // VST4d8_UPD = 3580 20269 CEFBS_HasNEON, // VST4q16 = 3581 20270 CEFBS_HasNEON, // VST4q16Pseudo_UPD = 3582 20271 CEFBS_HasNEON, // VST4q16_UPD = 3583 20272 CEFBS_HasNEON, // VST4q16oddPseudo = 3584 20273 CEFBS_HasNEON, // VST4q16oddPseudo_UPD = 3585 20274 CEFBS_HasNEON, // VST4q32 = 3586 20275 CEFBS_HasNEON, // VST4q32Pseudo_UPD = 3587 20276 CEFBS_HasNEON, // VST4q32_UPD = 3588 20277 CEFBS_HasNEON, // VST4q32oddPseudo = 3589 20278 CEFBS_HasNEON, // VST4q32oddPseudo_UPD = 3590 20279 CEFBS_HasNEON, // VST4q8 = 3591 20280 CEFBS_HasNEON, // VST4q8Pseudo_UPD = 3592 20281 CEFBS_HasNEON, // VST4q8_UPD = 3593 20282 CEFBS_HasNEON, // VST4q8oddPseudo = 3594 20283 CEFBS_HasNEON, // VST4q8oddPseudo_UPD = 3595 20284 CEFBS_HasFPRegs, // VSTMDDB_UPD = 3596 20285 CEFBS_HasFPRegs, // VSTMDIA = 3597 20286 CEFBS_HasFPRegs, // VSTMDIA_UPD = 3598 20287 CEFBS_HasVFP2, // VSTMQIA = 3599 20288 CEFBS_HasFPRegs, // VSTMSDB_UPD = 3600 20289 CEFBS_HasFPRegs, // VSTMSIA = 3601 20290 CEFBS_HasFPRegs, // VSTMSIA_UPD = 3602 20291 CEFBS_HasFPRegs, // VSTRD = 3603 20292 CEFBS_HasFPRegs16, // VSTRH = 3604 20293 CEFBS_HasFPRegs, // VSTRS = 3605 20294 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_off = 3606 20295 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_post = 3607 20296 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_pre = 3608 20297 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_off = 3609 20298 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_post = 3610 20299 CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_pre = 3611 20300 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_off = 3612 20301 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_post = 3613 20302 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_pre = 3614 20303 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_off = 3615 20304 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_post = 3616 20305 CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_pre = 3617 20306 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_off = 3618 20307 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_post = 3619 20308 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_pre = 3620 20309 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_off = 3621 20310 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_post = 3622 20311 CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_pre = 3623 20312 CEFBS_HasVFP2_HasDPVFP, // VSUBD = 3624 20313 CEFBS_HasFullFP16, // VSUBH = 3625 20314 CEFBS_HasNEON, // VSUBHNv2i32 = 3626 20315 CEFBS_HasNEON, // VSUBHNv4i16 = 3627 20316 CEFBS_HasNEON, // VSUBHNv8i8 = 3628 20317 CEFBS_HasNEON, // VSUBLsv2i64 = 3629 20318 CEFBS_HasNEON, // VSUBLsv4i32 = 3630 20319 CEFBS_HasNEON, // VSUBLsv8i16 = 3631 20320 CEFBS_HasNEON, // VSUBLuv2i64 = 3632 20321 CEFBS_HasNEON, // VSUBLuv4i32 = 3633 20322 CEFBS_HasNEON, // VSUBLuv8i16 = 3634 20323 CEFBS_HasVFP2, // VSUBS = 3635 20324 CEFBS_HasNEON, // VSUBWsv2i64 = 3636 20325 CEFBS_HasNEON, // VSUBWsv4i32 = 3637 20326 CEFBS_HasNEON, // VSUBWsv8i16 = 3638 20327 CEFBS_HasNEON, // VSUBWuv2i64 = 3639 20328 CEFBS_HasNEON, // VSUBWuv4i32 = 3640 20329 CEFBS_HasNEON, // VSUBWuv8i16 = 3641 20330 CEFBS_HasNEON, // VSUBfd = 3642 20331 CEFBS_HasNEON, // VSUBfq = 3643 20332 CEFBS_HasNEON_HasFullFP16, // VSUBhd = 3644 20333 CEFBS_HasNEON_HasFullFP16, // VSUBhq = 3645 20334 CEFBS_HasNEON, // VSUBv16i8 = 3646 20335 CEFBS_HasNEON, // VSUBv1i64 = 3647 20336 CEFBS_HasNEON, // VSUBv2i32 = 3648 20337 CEFBS_HasNEON, // VSUBv2i64 = 3649 20338 CEFBS_HasNEON, // VSUBv4i16 = 3650 20339 CEFBS_HasNEON, // VSUBv4i32 = 3651 20340 CEFBS_HasNEON, // VSUBv8i16 = 3652 20341 CEFBS_HasNEON, // VSUBv8i8 = 3653 20342 CEFBS_HasNEON, // VSWPd = 3654 20343 CEFBS_HasNEON, // VSWPq = 3655 20344 CEFBS_HasNEON, // VTBL1 = 3656 20345 CEFBS_HasNEON, // VTBL2 = 3657 20346 CEFBS_HasNEON, // VTBL3 = 3658 20347 CEFBS_HasNEON, // VTBL3Pseudo = 3659 20348 CEFBS_HasNEON, // VTBL4 = 3660 20349 CEFBS_HasNEON, // VTBL4Pseudo = 3661 20350 CEFBS_HasNEON, // VTBX1 = 3662 20351 CEFBS_HasNEON, // VTBX2 = 3663 20352 CEFBS_HasNEON, // VTBX3 = 3664 20353 CEFBS_HasNEON, // VTBX3Pseudo = 3665 20354 CEFBS_HasNEON, // VTBX4 = 3666 20355 CEFBS_HasNEON, // VTBX4Pseudo = 3667 20356 CEFBS_HasVFP2_HasDPVFP, // VTOSHD = 3668 20357 CEFBS_HasFullFP16, // VTOSHH = 3669 20358 CEFBS_HasVFP2, // VTOSHS = 3670 20359 CEFBS_HasVFP2_HasDPVFP, // VTOSIRD = 3671 20360 CEFBS_HasFullFP16, // VTOSIRH = 3672 20361 CEFBS_HasVFP2, // VTOSIRS = 3673 20362 CEFBS_HasVFP2_HasDPVFP, // VTOSIZD = 3674 20363 CEFBS_HasFullFP16, // VTOSIZH = 3675 20364 CEFBS_HasVFP2, // VTOSIZS = 3676 20365 CEFBS_HasVFP2_HasDPVFP, // VTOSLD = 3677 20366 CEFBS_HasFullFP16, // VTOSLH = 3678 20367 CEFBS_HasVFP2, // VTOSLS = 3679 20368 CEFBS_HasVFP2_HasDPVFP, // VTOUHD = 3680 20369 CEFBS_HasFullFP16, // VTOUHH = 3681 20370 CEFBS_HasVFP2, // VTOUHS = 3682 20371 CEFBS_HasVFP2_HasDPVFP, // VTOUIRD = 3683 20372 CEFBS_HasFullFP16, // VTOUIRH = 3684 20373 CEFBS_HasVFP2, // VTOUIRS = 3685 20374 CEFBS_HasVFP2_HasDPVFP, // VTOUIZD = 3686 20375 CEFBS_HasFullFP16, // VTOUIZH = 3687 20376 CEFBS_HasVFP2, // VTOUIZS = 3688 20377 CEFBS_HasVFP2_HasDPVFP, // VTOULD = 3689 20378 CEFBS_HasFullFP16, // VTOULH = 3690 20379 CEFBS_HasVFP2, // VTOULS = 3691 20380 CEFBS_HasNEON, // VTRNd16 = 3692 20381 CEFBS_HasNEON, // VTRNd32 = 3693 20382 CEFBS_HasNEON, // VTRNd8 = 3694 20383 CEFBS_HasNEON, // VTRNq16 = 3695 20384 CEFBS_HasNEON, // VTRNq32 = 3696 20385 CEFBS_HasNEON, // VTRNq8 = 3697 20386 CEFBS_HasNEON, // VTSTv16i8 = 3698 20387 CEFBS_HasNEON, // VTSTv2i32 = 3699 20388 CEFBS_HasNEON, // VTSTv4i16 = 3700 20389 CEFBS_HasNEON, // VTSTv4i32 = 3701 20390 CEFBS_HasNEON, // VTSTv8i16 = 3702 20391 CEFBS_HasNEON, // VTSTv8i8 = 3703 20392 CEFBS_HasDotProd, // VUDOTD = 3704 20393 CEFBS_HasDotProd, // VUDOTDI = 3705 20394 CEFBS_HasDotProd, // VUDOTQ = 3706 20395 CEFBS_HasDotProd, // VUDOTQI = 3707 20396 CEFBS_HasVFP2_HasDPVFP, // VUHTOD = 3708 20397 CEFBS_HasFullFP16, // VUHTOH = 3709 20398 CEFBS_HasVFP2, // VUHTOS = 3710 20399 CEFBS_HasVFP2_HasDPVFP, // VUITOD = 3711 20400 CEFBS_HasFullFP16, // VUITOH = 3712 20401 CEFBS_HasVFP2, // VUITOS = 3713 20402 CEFBS_HasVFP2_HasDPVFP, // VULTOD = 3714 20403 CEFBS_HasFullFP16, // VULTOH = 3715 20404 CEFBS_HasVFP2, // VULTOS = 3716 20405 CEFBS_HasNEON, // VUZPd16 = 3717 20406 CEFBS_HasNEON, // VUZPd8 = 3718 20407 CEFBS_HasNEON, // VUZPq16 = 3719 20408 CEFBS_HasNEON, // VUZPq32 = 3720 20409 CEFBS_HasNEON, // VUZPq8 = 3721 20410 CEFBS_HasNEON, // VZIPd16 = 3722 20411 CEFBS_HasNEON, // VZIPd8 = 3723 20412 CEFBS_HasNEON, // VZIPq16 = 3724 20413 CEFBS_HasNEON, // VZIPq32 = 3725 20414 CEFBS_HasNEON, // VZIPq8 = 3726 20415 CEFBS_IsARM, // sysLDMDA = 3727 20416 CEFBS_IsARM, // sysLDMDA_UPD = 3728 20417 CEFBS_IsARM, // sysLDMDB = 3729 20418 CEFBS_IsARM, // sysLDMDB_UPD = 3730 20419 CEFBS_IsARM, // sysLDMIA = 3731 20420 CEFBS_IsARM, // sysLDMIA_UPD = 3732 20421 CEFBS_IsARM, // sysLDMIB = 3733 20422 CEFBS_IsARM, // sysLDMIB_UPD = 3734 20423 CEFBS_IsARM, // sysSTMDA = 3735 20424 CEFBS_IsARM, // sysSTMDA_UPD = 3736 20425 CEFBS_IsARM, // sysSTMDB = 3737 20426 CEFBS_IsARM, // sysSTMDB_UPD = 3738 20427 CEFBS_IsARM, // sysSTMIA = 3739 20428 CEFBS_IsARM, // sysSTMIA_UPD = 3740 20429 CEFBS_IsARM, // sysSTMIB = 3741 20430 CEFBS_IsARM, // sysSTMIB_UPD = 3742 20431 CEFBS_IsThumb2, // t2ADCri = 3743 20432 CEFBS_IsThumb2, // t2ADCrr = 3744 20433 CEFBS_IsThumb2, // t2ADCrs = 3745 20434 CEFBS_IsThumb2, // t2ADDri = 3746 20435 CEFBS_IsThumb2, // t2ADDri12 = 3747 20436 CEFBS_IsThumb2, // t2ADDrr = 3748 20437 CEFBS_IsThumb2, // t2ADDrs = 3749 20438 CEFBS_IsThumb2, // t2ADDspImm = 3750 20439 CEFBS_IsThumb2, // t2ADDspImm12 = 3751 20440 CEFBS_IsThumb2, // t2ADR = 3752 20441 CEFBS_IsThumb2, // t2ANDri = 3753 20442 CEFBS_IsThumb2, // t2ANDrr = 3754 20443 CEFBS_IsThumb2, // t2ANDrs = 3755 20444 CEFBS_IsThumb2, // t2ASRri = 3756 20445 CEFBS_IsThumb2, // t2ASRrr = 3757 20446 CEFBS_IsThumb_HasV8MBaseline, // t2B = 3758 20447 CEFBS_IsThumb2, // t2BFC = 3759 20448 CEFBS_IsThumb2, // t2BFI = 3760 20449 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLi = 3761 20450 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLr = 3762 20451 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFi = 3763 20452 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFic = 3764 20453 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFr = 3765 20454 CEFBS_IsThumb2, // t2BICri = 3766 20455 CEFBS_IsThumb2, // t2BICrr = 3767 20456 CEFBS_IsThumb2, // t2BICrs = 3768 20457 CEFBS_IsThumb2_IsNotMClass, // t2BXJ = 3769 20458 CEFBS_IsThumb2, // t2Bcc = 3770 20459 CEFBS_IsThumb2_PreV8, // t2CDP = 3771 20460 CEFBS_IsThumb2_PreV8, // t2CDP2 = 3772 20461 CEFBS_IsThumb_HasV7Clrex, // t2CLREX = 3773 20462 CEFBS_HasV8_1MMainline, // t2CLRM = 3774 20463 CEFBS_IsThumb2, // t2CLZ = 3775 20464 CEFBS_IsThumb2, // t2CMNri = 3776 20465 CEFBS_IsThumb2, // t2CMNzrr = 3777 20466 CEFBS_IsThumb2, // t2CMNzrs = 3778 20467 CEFBS_IsThumb2, // t2CMPri = 3779 20468 CEFBS_IsThumb2, // t2CMPrr = 3780 20469 CEFBS_IsThumb2, // t2CMPrs = 3781 20470 CEFBS_IsThumb2_IsNotMClass, // t2CPS1p = 3782 20471 CEFBS_IsThumb2_IsNotMClass, // t2CPS2p = 3783 20472 CEFBS_IsThumb2_IsNotMClass, // t2CPS3p = 3784 20473 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32B = 3785 20474 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CB = 3786 20475 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CH = 3787 20476 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32CW = 3788 20477 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32H = 3789 20478 CEFBS_IsThumb2_HasV8_HasCRC, // t2CRC32W = 3790 20479 CEFBS_HasV8_1MMainline, // t2CSEL = 3791 20480 CEFBS_HasV8_1MMainline, // t2CSINC = 3792 20481 CEFBS_HasV8_1MMainline, // t2CSINV = 3793 20482 CEFBS_HasV8_1MMainline, // t2CSNEG = 3794 20483 CEFBS_IsThumb2, // t2DBG = 3795 20484 CEFBS_IsThumb2_HasV8, // t2DCPS1 = 3796 20485 CEFBS_IsThumb2_HasV8, // t2DCPS2 = 3797 20486 CEFBS_IsThumb2_HasV8, // t2DCPS3 = 3798 20487 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DLS = 3799 20488 CEFBS_IsThumb_HasDB, // t2DMB = 3800 20489 CEFBS_IsThumb_HasDB, // t2DSB = 3801 20490 CEFBS_IsThumb2, // t2EORri = 3802 20491 CEFBS_IsThumb2, // t2EORrr = 3803 20492 CEFBS_IsThumb2, // t2EORrs = 3804 20493 CEFBS_IsThumb2, // t2HINT = 3805 20494 CEFBS_IsThumb2_HasVirtualization, // t2HVC = 3806 20495 CEFBS_IsThumb_HasDB, // t2ISB = 3807 20496 CEFBS_IsThumb2, // t2IT = 3808 20497 CEFBS_IsThumb2_HasVFP2, // t2Int_eh_sjlj_setjmp = 3809 20498 CEFBS_IsThumb2, // t2Int_eh_sjlj_setjmp_nofp = 3810 20499 CEFBS_IsThumb_HasAcquireRelease, // t2LDA = 3811 20500 CEFBS_IsThumb_HasAcquireRelease, // t2LDAB = 3812 20501 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEX = 3813 20502 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXB = 3814 20503 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2LDAEXD = 3815 20504 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXH = 3816 20505 CEFBS_IsThumb_HasAcquireRelease, // t2LDAH = 3817 20506 CEFBS_PreV8_IsThumb2, // t2LDC2L_OFFSET = 3818 20507 CEFBS_PreV8_IsThumb2, // t2LDC2L_OPTION = 3819 20508 CEFBS_PreV8_IsThumb2, // t2LDC2L_POST = 3820 20509 CEFBS_PreV8_IsThumb2, // t2LDC2L_PRE = 3821 20510 CEFBS_PreV8_IsThumb2, // t2LDC2_OFFSET = 3822 20511 CEFBS_PreV8_IsThumb2, // t2LDC2_OPTION = 3823 20512 CEFBS_PreV8_IsThumb2, // t2LDC2_POST = 3824 20513 CEFBS_PreV8_IsThumb2, // t2LDC2_PRE = 3825 20514 CEFBS_IsThumb2, // t2LDCL_OFFSET = 3826 20515 CEFBS_IsThumb2, // t2LDCL_OPTION = 3827 20516 CEFBS_IsThumb2, // t2LDCL_POST = 3828 20517 CEFBS_IsThumb2, // t2LDCL_PRE = 3829 20518 CEFBS_IsThumb2, // t2LDC_OFFSET = 3830 20519 CEFBS_IsThumb2, // t2LDC_OPTION = 3831 20520 CEFBS_IsThumb2, // t2LDC_POST = 3832 20521 CEFBS_IsThumb2, // t2LDC_PRE = 3833 20522 CEFBS_IsThumb2, // t2LDMDB = 3834 20523 CEFBS_IsThumb2, // t2LDMDB_UPD = 3835 20524 CEFBS_IsThumb2, // t2LDMIA = 3836 20525 CEFBS_IsThumb2, // t2LDMIA_UPD = 3837 20526 CEFBS_IsThumb2, // t2LDRBT = 3838 20527 CEFBS_IsThumb2, // t2LDRB_POST = 3839 20528 CEFBS_IsThumb2, // t2LDRB_PRE = 3840 20529 CEFBS_IsThumb2, // t2LDRBi12 = 3841 20530 CEFBS_IsThumb2, // t2LDRBi8 = 3842 20531 CEFBS_IsThumb2, // t2LDRBpci = 3843 20532 CEFBS_IsThumb2, // t2LDRBs = 3844 20533 CEFBS_IsThumb2, // t2LDRD_POST = 3845 20534 CEFBS_IsThumb2, // t2LDRD_PRE = 3846 20535 CEFBS_IsThumb2, // t2LDRDi8 = 3847 20536 CEFBS_IsThumb_HasV8MBaseline, // t2LDREX = 3848 20537 CEFBS_IsThumb_HasV8MBaseline, // t2LDREXB = 3849 20538 CEFBS_IsThumb2_IsNotMClass, // t2LDREXD = 3850 20539 CEFBS_IsThumb_HasV8MBaseline, // t2LDREXH = 3851 20540 CEFBS_IsThumb2, // t2LDRHT = 3852 20541 CEFBS_IsThumb2, // t2LDRH_POST = 3853 20542 CEFBS_IsThumb2, // t2LDRH_PRE = 3854 20543 CEFBS_IsThumb2, // t2LDRHi12 = 3855 20544 CEFBS_IsThumb2, // t2LDRHi8 = 3856 20545 CEFBS_IsThumb2, // t2LDRHpci = 3857 20546 CEFBS_IsThumb2, // t2LDRHs = 3858 20547 CEFBS_IsThumb2, // t2LDRSBT = 3859 20548 CEFBS_IsThumb2, // t2LDRSB_POST = 3860 20549 CEFBS_IsThumb2, // t2LDRSB_PRE = 3861 20550 CEFBS_IsThumb2, // t2LDRSBi12 = 3862 20551 CEFBS_IsThumb2, // t2LDRSBi8 = 3863 20552 CEFBS_IsThumb2, // t2LDRSBpci = 3864 20553 CEFBS_IsThumb2, // t2LDRSBs = 3865 20554 CEFBS_IsThumb2, // t2LDRSHT = 3866 20555 CEFBS_IsThumb2, // t2LDRSH_POST = 3867 20556 CEFBS_IsThumb2, // t2LDRSH_PRE = 3868 20557 CEFBS_IsThumb2, // t2LDRSHi12 = 3869 20558 CEFBS_IsThumb2, // t2LDRSHi8 = 3870 20559 CEFBS_IsThumb2, // t2LDRSHpci = 3871 20560 CEFBS_IsThumb2, // t2LDRSHs = 3872 20561 CEFBS_IsThumb2, // t2LDRT = 3873 20562 CEFBS_IsThumb2, // t2LDR_POST = 3874 20563 CEFBS_IsThumb2, // t2LDR_PRE = 3875 20564 CEFBS_IsThumb2, // t2LDRi12 = 3876 20565 CEFBS_IsThumb2, // t2LDRi8 = 3877 20566 CEFBS_IsThumb2, // t2LDRpci = 3878 20567 CEFBS_IsThumb2, // t2LDRs = 3879 20568 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LE = 3880 20569 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LEUpdate = 3881 20570 CEFBS_IsThumb2, // t2LSLri = 3882 20571 CEFBS_IsThumb2, // t2LSLrr = 3883 20572 CEFBS_IsThumb2, // t2LSRri = 3884 20573 CEFBS_IsThumb2, // t2LSRrr = 3885 20574 CEFBS_IsThumb2, // t2MCR = 3886 20575 CEFBS_IsThumb2_PreV8, // t2MCR2 = 3887 20576 CEFBS_IsThumb2, // t2MCRR = 3888 20577 CEFBS_IsThumb2_PreV8, // t2MCRR2 = 3889 20578 CEFBS_IsThumb2, // t2MLA = 3890 20579 CEFBS_IsThumb2, // t2MLS = 3891 20580 CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16 = 3892 20581 CEFBS_IsThumb2, // t2MOVi = 3893 20582 CEFBS_IsThumb_HasV8MBaseline, // t2MOVi16 = 3894 20583 CEFBS_IsThumb2, // t2MOVr = 3895 20584 CEFBS_IsThumb2, // t2MOVsra_flag = 3896 20585 CEFBS_IsThumb2, // t2MOVsrl_flag = 3897 20586 CEFBS_IsThumb2, // t2MRC = 3898 20587 CEFBS_IsThumb2_PreV8, // t2MRC2 = 3899 20588 CEFBS_IsThumb2, // t2MRRC = 3900 20589 CEFBS_IsThumb2_PreV8, // t2MRRC2 = 3901 20590 CEFBS_IsThumb2_IsNotMClass, // t2MRS_AR = 3902 20591 CEFBS_IsThumb_IsMClass, // t2MRS_M = 3903 20592 CEFBS_IsThumb_HasVirtualization, // t2MRSbanked = 3904 20593 CEFBS_IsThumb2_IsNotMClass, // t2MRSsys_AR = 3905 20594 CEFBS_IsThumb2_IsNotMClass, // t2MSR_AR = 3906 20595 CEFBS_IsThumb_IsMClass, // t2MSR_M = 3907 20596 CEFBS_IsThumb_HasVirtualization, // t2MSRbanked = 3908 20597 CEFBS_IsThumb2, // t2MUL = 3909 20598 CEFBS_IsThumb2, // t2MVNi = 3910 20599 CEFBS_IsThumb2, // t2MVNr = 3911 20600 CEFBS_IsThumb2, // t2MVNs = 3912 20601 CEFBS_IsThumb2, // t2ORNri = 3913 20602 CEFBS_IsThumb2, // t2ORNrr = 3914 20603 CEFBS_IsThumb2, // t2ORNrs = 3915 20604 CEFBS_IsThumb2, // t2ORRri = 3916 20605 CEFBS_IsThumb2, // t2ORRrr = 3917 20606 CEFBS_IsThumb2, // t2ORRrs = 3918 20607 CEFBS_HasDSP_IsThumb2, // t2PKHBT = 3919 20608 CEFBS_HasDSP_IsThumb2, // t2PKHTB = 3920 20609 CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi12 = 3921 20610 CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi8 = 3922 20611 CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWs = 3923 20612 CEFBS_IsThumb2, // t2PLDi12 = 3924 20613 CEFBS_IsThumb2, // t2PLDi8 = 3925 20614 CEFBS_IsThumb2, // t2PLDpci = 3926 20615 CEFBS_IsThumb2, // t2PLDs = 3927 20616 CEFBS_IsThumb2_HasV7, // t2PLIi12 = 3928 20617 CEFBS_IsThumb2_HasV7, // t2PLIi8 = 3929 20618 CEFBS_IsThumb2_HasV7, // t2PLIpci = 3930 20619 CEFBS_IsThumb2_HasV7, // t2PLIs = 3931 20620 CEFBS_IsThumb2_HasDSP, // t2QADD = 3932 20621 CEFBS_IsThumb2_HasDSP, // t2QADD16 = 3933 20622 CEFBS_IsThumb2_HasDSP, // t2QADD8 = 3934 20623 CEFBS_IsThumb2_HasDSP, // t2QASX = 3935 20624 CEFBS_IsThumb2_HasDSP, // t2QDADD = 3936 20625 CEFBS_IsThumb2_HasDSP, // t2QDSUB = 3937 20626 CEFBS_IsThumb2_HasDSP, // t2QSAX = 3938 20627 CEFBS_IsThumb2_HasDSP, // t2QSUB = 3939 20628 CEFBS_IsThumb2_HasDSP, // t2QSUB16 = 3940 20629 CEFBS_IsThumb2_HasDSP, // t2QSUB8 = 3941 20630 CEFBS_IsThumb2, // t2RBIT = 3942 20631 CEFBS_IsThumb2, // t2REV = 3943 20632 CEFBS_IsThumb2, // t2REV16 = 3944 20633 CEFBS_IsThumb2, // t2REVSH = 3945 20634 CEFBS_IsThumb2_IsNotMClass, // t2RFEDB = 3946 20635 CEFBS_IsThumb2_IsNotMClass, // t2RFEDBW = 3947 20636 CEFBS_IsThumb2_IsNotMClass, // t2RFEIA = 3948 20637 CEFBS_IsThumb2_IsNotMClass, // t2RFEIAW = 3949 20638 CEFBS_IsThumb2, // t2RORri = 3950 20639 CEFBS_IsThumb2, // t2RORrr = 3951 20640 CEFBS_IsThumb2, // t2RRX = 3952 20641 CEFBS_IsThumb2, // t2RSBri = 3953 20642 CEFBS_IsThumb2, // t2RSBrr = 3954 20643 CEFBS_IsThumb2, // t2RSBrs = 3955 20644 CEFBS_IsThumb2_HasDSP, // t2SADD16 = 3956 20645 CEFBS_IsThumb2_HasDSP, // t2SADD8 = 3957 20646 CEFBS_IsThumb2_HasDSP, // t2SASX = 3958 20647 CEFBS_IsThumb2_HasSB, // t2SB = 3959 20648 CEFBS_IsThumb2, // t2SBCri = 3960 20649 CEFBS_IsThumb2, // t2SBCrr = 3961 20650 CEFBS_IsThumb2, // t2SBCrs = 3962 20651 CEFBS_IsThumb2, // t2SBFX = 3963 20652 CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2SDIV = 3964 20653 CEFBS_IsThumb2_HasDSP, // t2SEL = 3965 20654 CEFBS_IsThumb2_HasV8_HasV8_1a, // t2SETPAN = 3966 20655 CEFBS_Has8MSecExt, // t2SG = 3967 20656 CEFBS_IsThumb2_HasDSP, // t2SHADD16 = 3968 20657 CEFBS_IsThumb2_HasDSP, // t2SHADD8 = 3969 20658 CEFBS_IsThumb2_HasDSP, // t2SHASX = 3970 20659 CEFBS_IsThumb2_HasDSP, // t2SHSAX = 3971 20660 CEFBS_IsThumb2_HasDSP, // t2SHSUB16 = 3972 20661 CEFBS_IsThumb2_HasDSP, // t2SHSUB8 = 3973 20662 CEFBS_IsThumb2_HasTrustZone, // t2SMC = 3974 20663 CEFBS_IsThumb2_HasDSP, // t2SMLABB = 3975 20664 CEFBS_IsThumb2_HasDSP, // t2SMLABT = 3976 20665 CEFBS_IsThumb2_HasDSP, // t2SMLAD = 3977 20666 CEFBS_IsThumb2_HasDSP, // t2SMLADX = 3978 20667 CEFBS_IsThumb2, // t2SMLAL = 3979 20668 CEFBS_IsThumb2_HasDSP, // t2SMLALBB = 3980 20669 CEFBS_IsThumb2_HasDSP, // t2SMLALBT = 3981 20670 CEFBS_IsThumb2_HasDSP, // t2SMLALD = 3982 20671 CEFBS_IsThumb2_HasDSP, // t2SMLALDX = 3983 20672 CEFBS_IsThumb2_HasDSP, // t2SMLALTB = 3984 20673 CEFBS_IsThumb2_HasDSP, // t2SMLALTT = 3985 20674 CEFBS_IsThumb2_HasDSP, // t2SMLATB = 3986 20675 CEFBS_IsThumb2_HasDSP, // t2SMLATT = 3987 20676 CEFBS_IsThumb2_HasDSP, // t2SMLAWB = 3988 20677 CEFBS_IsThumb2_HasDSP, // t2SMLAWT = 3989 20678 CEFBS_IsThumb2_HasDSP, // t2SMLSD = 3990 20679 CEFBS_IsThumb2_HasDSP, // t2SMLSDX = 3991 20680 CEFBS_IsThumb2_HasDSP, // t2SMLSLD = 3992 20681 CEFBS_IsThumb2_HasDSP, // t2SMLSLDX = 3993 20682 CEFBS_IsThumb2_HasDSP, // t2SMMLA = 3994 20683 CEFBS_IsThumb2_HasDSP, // t2SMMLAR = 3995 20684 CEFBS_IsThumb2_HasDSP, // t2SMMLS = 3996 20685 CEFBS_IsThumb2_HasDSP, // t2SMMLSR = 3997 20686 CEFBS_IsThumb2_HasDSP, // t2SMMUL = 3998 20687 CEFBS_IsThumb2_HasDSP, // t2SMMULR = 3999 20688 CEFBS_IsThumb2_HasDSP, // t2SMUAD = 4000 20689 CEFBS_IsThumb2_HasDSP, // t2SMUADX = 4001 20690 CEFBS_IsThumb2_HasDSP, // t2SMULBB = 4002 20691 CEFBS_IsThumb2_HasDSP, // t2SMULBT = 4003 20692 CEFBS_IsThumb2, // t2SMULL = 4004 20693 CEFBS_IsThumb2_HasDSP, // t2SMULTB = 4005 20694 CEFBS_IsThumb2_HasDSP, // t2SMULTT = 4006 20695 CEFBS_IsThumb2_HasDSP, // t2SMULWB = 4007 20696 CEFBS_IsThumb2_HasDSP, // t2SMULWT = 4008 20697 CEFBS_IsThumb2_HasDSP, // t2SMUSD = 4009 20698 CEFBS_IsThumb2_HasDSP, // t2SMUSDX = 4010 20699 CEFBS_IsThumb2_IsNotMClass, // t2SRSDB = 4011 20700 CEFBS_IsThumb2_IsNotMClass, // t2SRSDB_UPD = 4012 20701 CEFBS_IsThumb2_IsNotMClass, // t2SRSIA = 4013 20702 CEFBS_IsThumb2_IsNotMClass, // t2SRSIA_UPD = 4014 20703 CEFBS_IsThumb2, // t2SSAT = 4015 20704 CEFBS_IsThumb2_HasDSP, // t2SSAT16 = 4016 20705 CEFBS_IsThumb2_HasDSP, // t2SSAX = 4017 20706 CEFBS_IsThumb2_HasDSP, // t2SSUB16 = 4018 20707 CEFBS_IsThumb2_HasDSP, // t2SSUB8 = 4019 20708 CEFBS_PreV8_IsThumb2, // t2STC2L_OFFSET = 4020 20709 CEFBS_PreV8_IsThumb2, // t2STC2L_OPTION = 4021 20710 CEFBS_PreV8_IsThumb2, // t2STC2L_POST = 4022 20711 CEFBS_PreV8_IsThumb2, // t2STC2L_PRE = 4023 20712 CEFBS_PreV8_IsThumb2, // t2STC2_OFFSET = 4024 20713 CEFBS_PreV8_IsThumb2, // t2STC2_OPTION = 4025 20714 CEFBS_PreV8_IsThumb2, // t2STC2_POST = 4026 20715 CEFBS_PreV8_IsThumb2, // t2STC2_PRE = 4027 20716 CEFBS_IsThumb2, // t2STCL_OFFSET = 4028 20717 CEFBS_IsThumb2, // t2STCL_OPTION = 4029 20718 CEFBS_IsThumb2, // t2STCL_POST = 4030 20719 CEFBS_IsThumb2, // t2STCL_PRE = 4031 20720 CEFBS_IsThumb2, // t2STC_OFFSET = 4032 20721 CEFBS_IsThumb2, // t2STC_OPTION = 4033 20722 CEFBS_IsThumb2, // t2STC_POST = 4034 20723 CEFBS_IsThumb2, // t2STC_PRE = 4035 20724 CEFBS_IsThumb_HasAcquireRelease, // t2STL = 4036 20725 CEFBS_IsThumb_HasAcquireRelease, // t2STLB = 4037 20726 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEX = 4038 20727 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXB = 4039 20728 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2STLEXD = 4040 20729 CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXH = 4041 20730 CEFBS_IsThumb_HasAcquireRelease, // t2STLH = 4042 20731 CEFBS_IsThumb2, // t2STMDB = 4043 20732 CEFBS_IsThumb2, // t2STMDB_UPD = 4044 20733 CEFBS_IsThumb2, // t2STMIA = 4045 20734 CEFBS_IsThumb2, // t2STMIA_UPD = 4046 20735 CEFBS_IsThumb2, // t2STRBT = 4047 20736 CEFBS_IsThumb2, // t2STRB_POST = 4048 20737 CEFBS_IsThumb2, // t2STRB_PRE = 4049 20738 CEFBS_IsThumb2, // t2STRBi12 = 4050 20739 CEFBS_IsThumb2, // t2STRBi8 = 4051 20740 CEFBS_IsThumb2, // t2STRBs = 4052 20741 CEFBS_IsThumb2, // t2STRD_POST = 4053 20742 CEFBS_IsThumb2, // t2STRD_PRE = 4054 20743 CEFBS_IsThumb2, // t2STRDi8 = 4055 20744 CEFBS_IsThumb_HasV8MBaseline, // t2STREX = 4056 20745 CEFBS_IsThumb_HasV8MBaseline, // t2STREXB = 4057 20746 CEFBS_IsThumb2_IsNotMClass, // t2STREXD = 4058 20747 CEFBS_IsThumb_HasV8MBaseline, // t2STREXH = 4059 20748 CEFBS_IsThumb2, // t2STRHT = 4060 20749 CEFBS_IsThumb2, // t2STRH_POST = 4061 20750 CEFBS_IsThumb2, // t2STRH_PRE = 4062 20751 CEFBS_IsThumb2, // t2STRHi12 = 4063 20752 CEFBS_IsThumb2, // t2STRHi8 = 4064 20753 CEFBS_IsThumb2, // t2STRHs = 4065 20754 CEFBS_IsThumb2, // t2STRT = 4066 20755 CEFBS_IsThumb2, // t2STR_POST = 4067 20756 CEFBS_IsThumb2, // t2STR_PRE = 4068 20757 CEFBS_IsThumb2, // t2STRi12 = 4069 20758 CEFBS_IsThumb2, // t2STRi8 = 4070 20759 CEFBS_IsThumb2, // t2STRs = 4071 20760 CEFBS_IsThumb2_IsNotMClass, // t2SUBS_PC_LR = 4072 20761 CEFBS_IsThumb2, // t2SUBri = 4073 20762 CEFBS_IsThumb2, // t2SUBri12 = 4074 20763 CEFBS_IsThumb2, // t2SUBrr = 4075 20764 CEFBS_IsThumb2, // t2SUBrs = 4076 20765 CEFBS_IsThumb2, // t2SUBspImm = 4077 20766 CEFBS_IsThumb2, // t2SUBspImm12 = 4078 20767 CEFBS_HasDSP_IsThumb2, // t2SXTAB = 4079 20768 CEFBS_HasDSP_IsThumb2, // t2SXTAB16 = 4080 20769 CEFBS_HasDSP_IsThumb2, // t2SXTAH = 4081 20770 CEFBS_IsThumb2, // t2SXTB = 4082 20771 CEFBS_HasDSP_IsThumb2, // t2SXTB16 = 4083 20772 CEFBS_IsThumb2, // t2SXTH = 4084 20773 CEFBS_IsThumb2, // t2TBB = 4085 20774 CEFBS_IsThumb2, // t2TBH = 4086 20775 CEFBS_IsThumb2, // t2TEQri = 4087 20776 CEFBS_IsThumb2, // t2TEQrr = 4088 20777 CEFBS_IsThumb2, // t2TEQrs = 4089 20778 CEFBS_IsThumb_HasV8_4a, // t2TSB = 4090 20779 CEFBS_IsThumb2, // t2TSTri = 4091 20780 CEFBS_IsThumb2, // t2TSTrr = 4092 20781 CEFBS_IsThumb2, // t2TSTrs = 4093 20782 CEFBS_IsThumb_Has8MSecExt, // t2TT = 4094 20783 CEFBS_IsThumb_Has8MSecExt, // t2TTA = 4095 20784 CEFBS_IsThumb_Has8MSecExt, // t2TTAT = 4096 20785 CEFBS_IsThumb_Has8MSecExt, // t2TTT = 4097 20786 CEFBS_IsThumb2_HasDSP, // t2UADD16 = 4098 20787 CEFBS_IsThumb2_HasDSP, // t2UADD8 = 4099 20788 CEFBS_IsThumb2_HasDSP, // t2UASX = 4100 20789 CEFBS_IsThumb2, // t2UBFX = 4101 20790 CEFBS_IsThumb2, // t2UDF = 4102 20791 CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2UDIV = 4103 20792 CEFBS_IsThumb2_HasDSP, // t2UHADD16 = 4104 20793 CEFBS_IsThumb2_HasDSP, // t2UHADD8 = 4105 20794 CEFBS_IsThumb2_HasDSP, // t2UHASX = 4106 20795 CEFBS_IsThumb2_HasDSP, // t2UHSAX = 4107 20796 CEFBS_IsThumb2_HasDSP, // t2UHSUB16 = 4108 20797 CEFBS_IsThumb2_HasDSP, // t2UHSUB8 = 4109 20798 CEFBS_IsThumb2_HasDSP, // t2UMAAL = 4110 20799 CEFBS_IsThumb2, // t2UMLAL = 4111 20800 CEFBS_IsThumb2, // t2UMULL = 4112 20801 CEFBS_IsThumb2_HasDSP, // t2UQADD16 = 4113 20802 CEFBS_IsThumb2_HasDSP, // t2UQADD8 = 4114 20803 CEFBS_IsThumb2_HasDSP, // t2UQASX = 4115 20804 CEFBS_IsThumb2_HasDSP, // t2UQSAX = 4116 20805 CEFBS_IsThumb2_HasDSP, // t2UQSUB16 = 4117 20806 CEFBS_IsThumb2_HasDSP, // t2UQSUB8 = 4118 20807 CEFBS_IsThumb2_HasDSP, // t2USAD8 = 4119 20808 CEFBS_IsThumb2_HasDSP, // t2USADA8 = 4120 20809 CEFBS_IsThumb2, // t2USAT = 4121 20810 CEFBS_IsThumb2_HasDSP, // t2USAT16 = 4122 20811 CEFBS_IsThumb2_HasDSP, // t2USAX = 4123 20812 CEFBS_IsThumb2_HasDSP, // t2USUB16 = 4124 20813 CEFBS_IsThumb2_HasDSP, // t2USUB8 = 4125 20814 CEFBS_HasDSP_IsThumb2, // t2UXTAB = 4126 20815 CEFBS_HasDSP_IsThumb2, // t2UXTAB16 = 4127 20816 CEFBS_HasDSP_IsThumb2, // t2UXTAH = 4128 20817 CEFBS_IsThumb2, // t2UXTB = 4129 20818 CEFBS_HasDSP_IsThumb2, // t2UXTB16 = 4130 20819 CEFBS_IsThumb2, // t2UXTH = 4131 20820 CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WLS = 4132 20821 CEFBS_IsThumb, // tADC = 4133 20822 CEFBS_IsThumb, // tADDhirr = 4134 20823 CEFBS_IsThumb, // tADDi3 = 4135 20824 CEFBS_IsThumb, // tADDi8 = 4136 20825 CEFBS_IsThumb, // tADDrSP = 4137 20826 CEFBS_IsThumb, // tADDrSPi = 4138 20827 CEFBS_IsThumb, // tADDrr = 4139 20828 CEFBS_IsThumb, // tADDspi = 4140 20829 CEFBS_IsThumb, // tADDspr = 4141 20830 CEFBS_IsThumb, // tADR = 4142 20831 CEFBS_IsThumb, // tAND = 4143 20832 CEFBS_IsThumb, // tASRri = 4144 20833 CEFBS_IsThumb, // tASRrr = 4145 20834 CEFBS_IsThumb, // tB = 4146 20835 CEFBS_IsThumb, // tBIC = 4147 20836 CEFBS_IsThumb, // tBKPT = 4148 20837 CEFBS_IsThumb, // tBL = 4149 20838 CEFBS_IsThumb_Has8MSecExt, // tBLXNSr = 4150 20839 CEFBS_IsThumb_HasV5T_IsNotMClass, // tBLXi = 4151 20840 CEFBS_IsThumb_HasV5T, // tBLXr = 4152 20841 CEFBS_IsThumb, // tBX = 4153 20842 CEFBS_IsThumb_Has8MSecExt, // tBXNS = 4154 20843 CEFBS_IsThumb, // tBcc = 4155 20844 CEFBS_IsThumb_HasV8MBaseline, // tCBNZ = 4156 20845 CEFBS_IsThumb_HasV8MBaseline, // tCBZ = 4157 20846 CEFBS_IsThumb, // tCMNz = 4158 20847 CEFBS_IsThumb, // tCMPhir = 4159 20848 CEFBS_IsThumb, // tCMPi8 = 4160 20849 CEFBS_IsThumb, // tCMPr = 4161 20850 CEFBS_IsThumb, // tCPS = 4162 20851 CEFBS_IsThumb, // tEOR = 4163 20852 CEFBS_IsThumb_HasV6M, // tHINT = 4164 20853 CEFBS_IsThumb_HasV8, // tHLT = 4165 20854 CEFBS_IsThumb, // tInt_WIN_eh_sjlj_longjmp = 4166 20855 CEFBS_IsThumb, // tInt_eh_sjlj_longjmp = 4167 20856 CEFBS_IsThumb, // tInt_eh_sjlj_setjmp = 4168 20857 CEFBS_IsThumb, // tLDMIA = 4169 20858 CEFBS_IsThumb, // tLDRBi = 4170 20859 CEFBS_IsThumb, // tLDRBr = 4171 20860 CEFBS_IsThumb, // tLDRHi = 4172 20861 CEFBS_IsThumb, // tLDRHr = 4173 20862 CEFBS_IsThumb, // tLDRSB = 4174 20863 CEFBS_IsThumb, // tLDRSH = 4175 20864 CEFBS_IsThumb, // tLDRi = 4176 20865 CEFBS_IsThumb, // tLDRpci = 4177 20866 CEFBS_IsThumb, // tLDRr = 4178 20867 CEFBS_IsThumb, // tLDRspi = 4179 20868 CEFBS_IsThumb, // tLSLri = 4180 20869 CEFBS_IsThumb, // tLSLrr = 4181 20870 CEFBS_IsThumb, // tLSRri = 4182 20871 CEFBS_IsThumb, // tLSRrr = 4183 20872 CEFBS_IsThumb, // tMOVSr = 4184 20873 CEFBS_IsThumb, // tMOVi8 = 4185 20874 CEFBS_IsThumb, // tMOVr = 4186 20875 CEFBS_IsThumb, // tMUL = 4187 20876 CEFBS_IsThumb, // tMVN = 4188 20877 CEFBS_IsThumb, // tORR = 4189 20878 CEFBS_IsThumb, // tPICADD = 4190 20879 CEFBS_IsThumb, // tPOP = 4191 20880 CEFBS_IsThumb, // tPUSH = 4192 20881 CEFBS_IsThumb_HasV6, // tREV = 4193 20882 CEFBS_IsThumb_HasV6, // tREV16 = 4194 20883 CEFBS_IsThumb_HasV6, // tREVSH = 4195 20884 CEFBS_IsThumb, // tROR = 4196 20885 CEFBS_IsThumb, // tRSB = 4197 20886 CEFBS_IsThumb, // tSBC = 4198 20887 CEFBS_IsThumb_IsNotMClass, // tSETEND = 4199 20888 CEFBS_IsThumb, // tSTMIA_UPD = 4200 20889 CEFBS_IsThumb, // tSTRBi = 4201 20890 CEFBS_IsThumb, // tSTRBr = 4202 20891 CEFBS_IsThumb, // tSTRHi = 4203 20892 CEFBS_IsThumb, // tSTRHr = 4204 20893 CEFBS_IsThumb, // tSTRi = 4205 20894 CEFBS_IsThumb, // tSTRr = 4206 20895 CEFBS_IsThumb, // tSTRspi = 4207 20896 CEFBS_IsThumb, // tSUBi3 = 4208 20897 CEFBS_IsThumb, // tSUBi8 = 4209 20898 CEFBS_IsThumb, // tSUBrr = 4210 20899 CEFBS_IsThumb, // tSUBspi = 4211 20900 CEFBS_IsThumb, // tSVC = 4212 20901 CEFBS_IsThumb_HasV6, // tSXTB = 4213 20902 CEFBS_IsThumb_HasV6, // tSXTH = 4214 20903 CEFBS_IsThumb, // tTRAP = 4215 20904 CEFBS_IsThumb, // tTST = 4216 20905 CEFBS_IsThumb, // tUDF = 4217 20906 CEFBS_IsThumb_HasV6, // tUXTB = 4218 20907 CEFBS_IsThumb_HasV6, // tUXTH = 4219 20908 CEFBS_IsThumb, // t__brkdiv0 = 4220 20909 }; 20910 20911 assert(Inst.getOpcode() < 4221); 20912 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; 20913 FeatureBitset MissingFeatures = 20914 (AvailableFeatures & RequiredFeatures) ^ 20915 RequiredFeatures; 20916 if (MissingFeatures.any()) { 20917 std::ostringstream Msg; 20918 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() 20919 << " instruction but the "; 20920 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 20921 if (MissingFeatures.test(i)) 20922 Msg << SubtargetFeatureNames[i] << " "; 20923 Msg << "predicate(s) are not met"; 20924 report_fatal_error(Msg.str()); 20925 } 20926#else 20927// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). 20928(void)MCII; 20929#endif // NDEBUG 20930} 20931#endif 20932