1//===- subzero/src/IceInstMIPS32.def - X-Macros for MIPS insts --*- C++ -*-===// 2// 3// The Subzero Code Generator 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines properties of MIPS32 instructions in the form of x-macros. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef SUBZERO_SRC_ICEINSTMIPS32_DEF 15#define SUBZERO_SRC_ICEINSTMIPS32_DEF 16 17// NOTE: PC and SP are not considered isInt, to avoid register allocating. 18// TODO(reed kotler). This needs to be scrubbed and is a placeholder to get 19// the Mips skeleton in. 20// 21// ALIASESn is a family of macros that we use to define register aliasing in 22// MIPS32. n indicates how many aliases are being provided to the macro. It 23// assumes the parameters are register names declared in a namespace/class 24// named RegMIPS32. 25#ifndef ALIASES1 26#define ALIASES1(r0) \ 27 {RegMIPS32::r0} 28#define ALIASES2(r0, r1) \ 29 {RegMIPS32::r0, RegMIPS32::r1} 30#define ALIASES3(r0, r1, r2) \ 31 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2} 32#define ALIASES4(r0, r1, r2, r3) \ 33 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3} 34#define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \ 35 {RegMIPS32::r0, RegMIPS32::r1, RegMIPS32::r2, RegMIPS32::r3, RegMIPS32::r4,\ 36 RegMIPS32::r5,RegMIPS32::r6} 37#endif 38 39#define REGMIPS32_GPR_TABLE \ 40 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 41 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 42 X(Reg_ZERO, 0, "zero", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 43 ALIASES1(Reg_ZERO)) \ 44 X(Reg_AT, 1, "at", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 45 ALIASES1(Reg_AT)) \ 46 X(Reg_V0, 2, "v0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 47 ALIASES2(Reg_V0, Reg_V0V1)) \ 48 X(Reg_V1, 3, "v1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 49 ALIASES2(Reg_V1, Reg_V0V1)) \ 50 X(Reg_A0, 4, "a0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 51 ALIASES2(Reg_A0, Reg_A0A1)) \ 52 X(Reg_A1, 5, "a1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 53 ALIASES2(Reg_A1, Reg_A0A1)) \ 54 X(Reg_A2, 6, "a2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 55 ALIASES2(Reg_A2, Reg_A2A3)) \ 56 X(Reg_A3, 7, "a3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 57 ALIASES2(Reg_A3, Reg_A2A3)) \ 58 X(Reg_T0, 8, "t0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 59 ALIASES2(Reg_T0, Reg_T0T1)) \ 60 X(Reg_T1, 9, "t1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 61 ALIASES2(Reg_T1, Reg_T0T1)) \ 62 X(Reg_T2, 10, "t2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 63 ALIASES2(Reg_T2, Reg_T2T3)) \ 64 X(Reg_T3, 11, "t3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 65 ALIASES2(Reg_T3, Reg_T2T3)) \ 66 X(Reg_T4, 12, "t4", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 67 ALIASES2(Reg_T4, Reg_T4T5)) \ 68 X(Reg_T5, 13, "t5", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 69 ALIASES2(Reg_T5, Reg_T4T5)) \ 70 X(Reg_T6, 14, "t6", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 71 ALIASES2(Reg_T6, Reg_T6T7)) \ 72 X(Reg_T7, 15, "t7", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 73 ALIASES2(Reg_T7, Reg_T6T7)) \ 74 X(Reg_S0, 16, "s0", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 75 ALIASES2(Reg_S0, Reg_S0S1)) \ 76 X(Reg_S1, 17, "s1", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 77 ALIASES2(Reg_S1, Reg_S0S1)) \ 78 X(Reg_S2, 18, "s2", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 79 ALIASES2(Reg_S2, Reg_S2S3)) \ 80 X(Reg_S3, 19, "s3", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 81 ALIASES2(Reg_S3, Reg_S2S3)) \ 82 X(Reg_S4, 20, "s4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 83 ALIASES2(Reg_S4, Reg_S4S5)) \ 84 X(Reg_S5, 21, "s5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 85 ALIASES2(Reg_S5, Reg_S4S5)) \ 86 X(Reg_S6, 22, "s6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 87 ALIASES2(Reg_S6, Reg_S6S7)) \ 88 X(Reg_S7, 23, "s7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \ 89 ALIASES2(Reg_S7, Reg_S6S7)) \ 90 X(Reg_T8, 24, "t8", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 91 ALIASES2(Reg_T8, Reg_T8T9)) \ 92 X(Reg_T9, 25, "t9", 1, 0, 0, 0, 1, 0, 0, 0, 0, \ 93 ALIASES2(Reg_T9, Reg_T8T9)) \ 94 X(Reg_K0, 26, "k0", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 95 ALIASES1(Reg_K0)) \ 96 X(Reg_K1, 27, "k1", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 97 ALIASES1(Reg_K1)) \ 98 X(Reg_GP, 28, "gp", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 99 ALIASES1(Reg_GP)) \ 100 X(Reg_SP, 29, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 101 ALIASES1(Reg_SP)) \ 102 X(Reg_FP, 30, "fp", 0, 0, 0, 1, 0, 0, 0, 0, 0, \ 103 ALIASES1(Reg_FP)) \ 104 X(Reg_RA, 31, "ra", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 105 ALIASES1(Reg_RA)) \ 106 X(Reg_LO, 0, "lo", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 107 ALIASES2(Reg_LO, Reg_LOHI)) \ 108 X(Reg_HI, 0, "hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 109 ALIASES2(Reg_HI, Reg_LOHI)) 110 111#define REGMIPS32_FPR_TABLE \ 112 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 113 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 114 X(Reg_F0, 0, "f0", 1,0,0,0, 0,0,1,0,0, \ 115 ALIASES2(Reg_F0, Reg_F0F1)) \ 116 X(Reg_F1, 1, "f1", 1,0,0,0, 0,0,1,0,0, \ 117 ALIASES2(Reg_F1, Reg_F0F1)) \ 118 X(Reg_F2, 2, "f2", 1,0,0,0, 0,0,1,0,0, \ 119 ALIASES2(Reg_F2, Reg_F2F3)) \ 120 X(Reg_F3, 3, "f3", 1,0,0,0, 0,0,1,0,0, \ 121 ALIASES2(Reg_F3, Reg_F2F3)) \ 122 X(Reg_F4, 4, "f4", 1,0,0,0, 0,0,1,0,0, \ 123 ALIASES2(Reg_F4, Reg_F4F5)) \ 124 X(Reg_F5, 5, "f5", 1,0,0,0, 0,0,1,0,0, \ 125 ALIASES2(Reg_F5, Reg_F4F5)) \ 126 X(Reg_F6, 6, "f6", 1,0,0,0, 0,0,1,0,0, \ 127 ALIASES2(Reg_F6, Reg_F6F7)) \ 128 X(Reg_F7, 7, "f7", 1,0,0,0, 0,0,1,0,0, \ 129 ALIASES2(Reg_F7, Reg_F6F7)) \ 130 X(Reg_F8, 8, "f8", 1,0,0,0, 0,0,1,0,0, \ 131 ALIASES2(Reg_F8, Reg_F8F9)) \ 132 X(Reg_F9, 9, "f9", 1,0,0,0, 0,0,1,0,0, \ 133 ALIASES2(Reg_F9, Reg_F8F9)) \ 134 X(Reg_F10, 10, "f10", 1,0,0,0, 0,0,1,0,0, \ 135 ALIASES2(Reg_F10, Reg_F10F11)) \ 136 X(Reg_F11, 11, "f11", 1,0,0,0, 0,0,1,0,0, \ 137 ALIASES2(Reg_F11, Reg_F10F11)) \ 138 X(Reg_F12, 12, "f12", 1,0,0,0, 0,0,1,0,0, \ 139 ALIASES2(Reg_F12, Reg_F12F13)) \ 140 X(Reg_F13, 13, "f13", 1,0,0,0, 0,0,1,0,0, \ 141 ALIASES2(Reg_F13, Reg_F12F13)) \ 142 X(Reg_F14, 14, "f14", 1,0,0,0, 0,0,1,0,0, \ 143 ALIASES2(Reg_F14, Reg_F14F15)) \ 144 X(Reg_F15, 15, "f15", 1,0,0,0, 0,0,1,0,0, \ 145 ALIASES2(Reg_F15, Reg_F14F15)) \ 146 X(Reg_F16, 16, "f16", 1,0,0,0, 0,0,1,0,0, \ 147 ALIASES2(Reg_F16, Reg_F16F17)) \ 148 X(Reg_F17, 17, "f17", 1,0,0,0, 0,0,1,0,0, \ 149 ALIASES2(Reg_F17, Reg_F16F17)) \ 150 X(Reg_F18, 18, "f18", 1,0,0,0, 0,0,1,0,0, \ 151 ALIASES2(Reg_F18, Reg_F18F19)) \ 152 X(Reg_F19, 19, "f19", 1,0,0,0, 0,0,1,0,0, \ 153 ALIASES2(Reg_F19, Reg_F18F19)) \ 154 X(Reg_F20, 20, "f20", 0,1,0,0, 0,0,1,0,0, \ 155 ALIASES2(Reg_F20, Reg_F20F21)) \ 156 X(Reg_F21, 21, "f21", 0,1,0,0, 0,0,1,0,0, \ 157 ALIASES2(Reg_F21, Reg_F20F21)) \ 158 X(Reg_F22, 22, "f22", 0,1,0,0, 0,0,1,0,0, \ 159 ALIASES2(Reg_F22, Reg_F22F23)) \ 160 X(Reg_F23, 23, "f23", 0,1,0,0, 0,0,1,0,0, \ 161 ALIASES2(Reg_F23, Reg_F22F23)) \ 162 X(Reg_F24, 24, "f24", 0,1,0,0, 0,0,1,0,0, \ 163 ALIASES2(Reg_F24, Reg_F24F25)) \ 164 X(Reg_F25, 25, "f25", 0,1,0,0, 0,0,1,0,0, \ 165 ALIASES2(Reg_F25, Reg_F24F25)) \ 166 X(Reg_F26, 26, "f26", 0,1,0,0, 0,0,1,0,0, \ 167 ALIASES2(Reg_F26, Reg_F26F27)) \ 168 X(Reg_F27, 27, "f27", 0,1,0,0, 0,0,1,0,0, \ 169 ALIASES2(Reg_F27, Reg_F26F27)) \ 170 X(Reg_F28, 28, "f28", 0,1,0,0, 0,0,1,0,0, \ 171 ALIASES2(Reg_F28, Reg_F28F29)) \ 172 X(Reg_F29, 29, "f29", 0,1,0,0, 0,0,1,0,0, \ 173 ALIASES2(Reg_F29, Reg_F28F29)) \ 174 X(Reg_F30, 30, "f30", 0,1,0,0, 0,0,1,0,0, \ 175 ALIASES2(Reg_F30, Reg_F30F31)) \ 176 X(Reg_F31, 31, "f31", 0,1,0,0, 0,0,1,0,0, \ 177 ALIASES2(Reg_F31, Reg_F30F31)) 178 179//#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 180// isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 181// The following defines a table with the available pairs of consecutive i32 182// GPRs starting at an even GPR that is not r14. Those are used to hold i64 183// variables for atomic memory operations. If one of the registers in the pair 184// is preserved, then we mark the whole pair as preserved to help the register 185// allocator. 186#define REGMIPS32_I64PAIR_TABLE \ 187 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 188 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 189 X(Reg_V0V1, 0, "v0, v1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 190 ALIASES3(Reg_V0, Reg_V1, Reg_V0V1)) \ 191 X(Reg_A0A1, 2, "a0, a1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 192 ALIASES3(Reg_A0, Reg_A1, Reg_A0A1)) \ 193 X(Reg_A2A3, 4, "a2, a3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 194 ALIASES3(Reg_A2, Reg_A3, Reg_A2A3)) \ 195 X(Reg_T0T1, 8, "t0, t1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 196 ALIASES3(Reg_T0, Reg_T1, Reg_T0T1)) \ 197 X(Reg_T2T3, 10, "t2, t3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 198 ALIASES3(Reg_T2, Reg_T3, Reg_T2T3)) \ 199 X(Reg_T4T5, 12,"t4, t5", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 200 ALIASES3(Reg_T4, Reg_T5, Reg_T4T5)) \ 201 X(Reg_T6T7, 14, "t6, t7", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 202 ALIASES3(Reg_T6, Reg_T7, Reg_T6T7)) \ 203 X(Reg_S0S1, 16, "s0, s1", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 204 ALIASES3(Reg_S0, Reg_S1, Reg_S0S1)) \ 205 X(Reg_S2S3, 18, "s2, s3", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 206 ALIASES3(Reg_S2, Reg_S3, Reg_S2S3)) \ 207 X(Reg_S4S5, 20, "s4, s5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 208 ALIASES3(Reg_S4, Reg_S5, Reg_S4S5)) \ 209 X(Reg_S6S7, 22, "s6, s7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \ 210 ALIASES3(Reg_S6, Reg_S7, Reg_S6S7)) \ 211 X(Reg_T8T9, 26, "t8, t9", 1, 0, 0, 0, 0, 1, 0, 0, 0, \ 212 ALIASES3(Reg_T8, Reg_T9, Reg_T8T9)) \ 213 X(Reg_LOHI, 0, "lo, hi", 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 214 ALIASES3(Reg_LO, Reg_HI, Reg_LOHI)) \ 215//#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 216// isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 217 218#define REGMIPS32_F64PAIR_TABLE \ 219 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 220 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ 221 X(Reg_F0F1, 0, "f0", 1,0,0,0, 0,0,0,1,0, \ 222 ALIASES3(Reg_F0, Reg_F1, Reg_F0F1)) \ 223 X(Reg_F2F3, 2, "f2", 1,0,0,0, 0,0,0,1,0, \ 224 ALIASES3(Reg_F2, Reg_F3, Reg_F2F3)) \ 225 X(Reg_F4F5, 4, "f4", 1,0,0,0, 0,0,0,1,0, \ 226 ALIASES3(Reg_F4, Reg_F5, Reg_F4F5)) \ 227 X(Reg_F6F7, 6, "f6", 1,0,0,0, 0,0,0,1,0, \ 228 ALIASES3(Reg_F6, Reg_F7, Reg_F6F7)) \ 229 X(Reg_F8F9, 8, "f8", 1,0,0,0, 0,0,0,1,0, \ 230 ALIASES3(Reg_F8, Reg_F9, Reg_F8F9)) \ 231 X(Reg_F10F11, 10, "f10", 1,0,0,0, 0,0,0,1,0, \ 232 ALIASES3(Reg_F10, Reg_F11, Reg_F10F11)) \ 233 X(Reg_F12F13, 12, "f12", 1,0,0,0, 0,0,0,1,0, \ 234 ALIASES3(Reg_F12, Reg_F13, Reg_F12F13)) \ 235 X(Reg_F14F15, 14, "f14", 1,0,0,0, 0,0,0,1,0, \ 236 ALIASES3(Reg_F14, Reg_F15, Reg_F14F15)) \ 237 X(Reg_F16F17, 16, "f16", 1,0,0,0, 0,0,0,1,0, \ 238 ALIASES3(Reg_F16, Reg_F17, Reg_F16F17)) \ 239 X(Reg_F18F19, 18, "f18", 1,0,0,0, 0,0,0,1,0, \ 240 ALIASES3(Reg_F18, Reg_F19, Reg_F18F19)) \ 241 X(Reg_F20F21, 20, "f20", 0,1,0,0, 0,0,0,1,0, \ 242 ALIASES3(Reg_F20, Reg_F21, Reg_F20F21)) \ 243 X(Reg_F22F23, 22, "f22", 0,1,0,0, 0,0,0,1,0, \ 244 ALIASES3(Reg_F22, Reg_F23, Reg_F22F23)) \ 245 X(Reg_F24F25, 24, "f24", 0,1,0,0, 0,0,0,1,0, \ 246 ALIASES3(Reg_F24, Reg_F25, Reg_F24F25)) \ 247 X(Reg_F26F27, 26, "f26", 0,1,0,0, 0,0,0,1,0, \ 248 ALIASES3(Reg_F26, Reg_F27, Reg_F26F27)) \ 249 X(Reg_F28F29, 28, "f28", 0,1,0,0, 0,0,0,1,0, \ 250 ALIASES3(Reg_F28, Reg_F29, Reg_F28F29)) \ 251 X(Reg_F30F31, 30, "f30", 0,1,0,0, 0,0,0,1,0, \ 252 ALIASES3(Reg_F30, Reg_F31, Reg_F30F31)) 253 254// We also provide a combined table, so that there is a namespace where 255// all of the registers are considered and have distinct numberings. 256// This is in contrast to the above, where the "encode" is based on how 257// the register numbers will be encoded in binaries and values can overlap. 258#define REGMIPS32_TABLE \ 259 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 260 isFP32, isFP64, isVec128, alias_init */ \ 261 REGMIPS32_GPR_TABLE \ 262 REGMIPS32_FPR_TABLE \ 263 REGMIPS32_I64PAIR_TABLE \ 264 REGMIPS32_F64PAIR_TABLE 265 266//#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 267// isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) 268#define REGMIPS32_TABLE_BOUNDS \ 269 /* val, init */ \ 270 X(Reg_GPR_First, = Reg_ZERO) \ 271 X(Reg_GPR_Last, = Reg_HI) \ 272 X(Reg_FPR_First, = Reg_F0) \ 273 X(Reg_FPR_Last, = Reg_F31) \ 274 X(Reg_I64PAIR_First, = Reg_V0V1) \ 275 X(Reg_I64PAIR_Last, = Reg_LOHI) \ 276 X(Reg_F64PAIR_First, = Reg_F0F1) \ 277 X(Reg_F64PAIR_Last, = Reg_F30F31) \ 278//define X(val, init) 279 280#define ICEINSTMIPS32COND_TABLE \ 281 /* enum value, opposite, emit */ \ 282 X(EQ, NE, "eq") /* equal */ \ 283 X(NE, EQ, "ne") /* not equal */ \ 284 X(EQZ, NEZ, "eqz") /* signed equal to zero */ \ 285 X(NEZ, EQZ, "nez") /* signed not equal to zero */ \ 286 X(GEZ, LTZ, "gez") /* signed greater than or equal to zero */ \ 287 X(LTZ, GEZ, "ltz") /* signed less than to zero */ \ 288 X(GTZ, LEZ, "gtz") /* signed greater than to zero */ \ 289 X(LEZ, GTZ, "lez") /* signed less than or equal to zero */ \ 290 X(AL, kNone, "") /* always (unconditional) */ \ 291 X(kNone, kNone, "??") /* special condition / none */ 292//#define X(tag, opp, emit) 293 294#endif // SUBZERO_SRC_ICEINSTMIPS32_DEF 295