1 //===-- DNBArchImpl.cpp -----------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Created by Greg Clayton on 6/25/07.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
14
15 #include "MacOSX/arm/DNBArchImpl.h"
16 #include "ARM_DWARF_Registers.h"
17 #include "ARM_ehframe_Registers.h"
18 #include "DNB.h"
19 #include "DNBBreakpoint.h"
20 #include "DNBLog.h"
21 #include "DNBRegisterInfo.h"
22 #include "MacOSX/MachProcess.h"
23 #include "MacOSX/MachThread.h"
24
25 #include <inttypes.h>
26 #include <sys/sysctl.h>
27
28 // BCR address match type
29 #define BCR_M_IMVA_MATCH ((uint32_t)(0u << 21))
30 #define BCR_M_CONTEXT_ID_MATCH ((uint32_t)(1u << 21))
31 #define BCR_M_IMVA_MISMATCH ((uint32_t)(2u << 21))
32 #define BCR_M_RESERVED ((uint32_t)(3u << 21))
33
34 // Link a BVR/BCR or WVR/WCR pair to another
35 #define E_ENABLE_LINKING ((uint32_t)(1u << 20))
36
37 // Byte Address Select
38 #define BAS_IMVA_PLUS_0 ((uint32_t)(1u << 5))
39 #define BAS_IMVA_PLUS_1 ((uint32_t)(1u << 6))
40 #define BAS_IMVA_PLUS_2 ((uint32_t)(1u << 7))
41 #define BAS_IMVA_PLUS_3 ((uint32_t)(1u << 8))
42 #define BAS_IMVA_0_1 ((uint32_t)(3u << 5))
43 #define BAS_IMVA_2_3 ((uint32_t)(3u << 7))
44 #define BAS_IMVA_ALL ((uint32_t)(0xfu << 5))
45
46 // Break only in privileged or user mode
47 #define S_RSVD ((uint32_t)(0u << 1))
48 #define S_PRIV ((uint32_t)(1u << 1))
49 #define S_USER ((uint32_t)(2u << 1))
50 #define S_PRIV_USER ((S_PRIV) | (S_USER))
51
52 #define BCR_ENABLE ((uint32_t)(1u))
53 #define WCR_ENABLE ((uint32_t)(1u))
54
55 // Watchpoint load/store
56 #define WCR_LOAD ((uint32_t)(1u << 3))
57 #define WCR_STORE ((uint32_t)(1u << 4))
58
59 // Definitions for the Debug Status and Control Register fields:
60 // [5:2] => Method of debug entry
61 //#define WATCHPOINT_OCCURRED ((uint32_t)(2u))
62 // I'm seeing this, instead.
63 #define WATCHPOINT_OCCURRED ((uint32_t)(10u))
64
65 // 0xE120BE70
66 static const uint8_t g_arm_breakpoint_opcode[] = {0x70, 0xBE, 0x20, 0xE1};
67 static const uint8_t g_thumb_breakpoint_opcode[] = {0x70, 0xBE};
68
69 // A watchpoint may need to be implemented using two watchpoint registers.
70 // e.g. watching an 8-byte region when the device can only watch 4-bytes.
71 //
72 // This stores the lo->hi mappings. It's safe to initialize to all 0's
73 // since hi > lo and therefore LoHi[i] cannot be 0.
74 static uint32_t LoHi[16] = {0};
75
76 // ARM constants used during decoding
77 #define REG_RD 0
78 #define LDM_REGLIST 1
79 #define PC_REG 15
80 #define PC_REGLIST_BIT 0x8000
81
82 // ARM conditions
83 #define COND_EQ 0x0
84 #define COND_NE 0x1
85 #define COND_CS 0x2
86 #define COND_HS 0x2
87 #define COND_CC 0x3
88 #define COND_LO 0x3
89 #define COND_MI 0x4
90 #define COND_PL 0x5
91 #define COND_VS 0x6
92 #define COND_VC 0x7
93 #define COND_HI 0x8
94 #define COND_LS 0x9
95 #define COND_GE 0xA
96 #define COND_LT 0xB
97 #define COND_GT 0xC
98 #define COND_LE 0xD
99 #define COND_AL 0xE
100 #define COND_UNCOND 0xF
101
102 #define MASK_CPSR_T (1u << 5)
103 #define MASK_CPSR_J (1u << 24)
104
105 #define MNEMONIC_STRING_SIZE 32
106 #define OPERAND_STRING_SIZE 128
107
108 // Returns true if the first 16 bit opcode of a thumb instruction indicates
109 // the instruction will be a 32 bit thumb opcode
IsThumb32Opcode(uint16_t opcode)110 static bool IsThumb32Opcode(uint16_t opcode) {
111 if (((opcode & 0xE000) == 0xE000) && (opcode & 0x1800))
112 return true;
113 return false;
114 }
115
Initialize()116 void DNBArchMachARM::Initialize() {
117 DNBArchPluginInfo arch_plugin_info = {
118 CPU_TYPE_ARM, DNBArchMachARM::Create, DNBArchMachARM::GetRegisterSetInfo,
119 DNBArchMachARM::SoftwareBreakpointOpcode};
120
121 // Register this arch plug-in with the main protocol class
122 DNBArchProtocol::RegisterArchPlugin(arch_plugin_info);
123 }
124
Create(MachThread * thread)125 DNBArchProtocol *DNBArchMachARM::Create(MachThread *thread) {
126 DNBArchMachARM *obj = new DNBArchMachARM(thread);
127 return obj;
128 }
129
SoftwareBreakpointOpcode(nub_size_t byte_size)130 const uint8_t *DNBArchMachARM::SoftwareBreakpointOpcode(nub_size_t byte_size) {
131 switch (byte_size) {
132 case 2:
133 return g_thumb_breakpoint_opcode;
134 case 4:
135 return g_arm_breakpoint_opcode;
136 }
137 return NULL;
138 }
139
GetCPUType()140 uint32_t DNBArchMachARM::GetCPUType() { return CPU_TYPE_ARM; }
141
GetPC(uint64_t failValue)142 uint64_t DNBArchMachARM::GetPC(uint64_t failValue) {
143 // Get program counter
144 if (GetGPRState(false) == KERN_SUCCESS)
145 return m_state.context.gpr.__pc;
146 return failValue;
147 }
148
SetPC(uint64_t value)149 kern_return_t DNBArchMachARM::SetPC(uint64_t value) {
150 // Get program counter
151 kern_return_t err = GetGPRState(false);
152 if (err == KERN_SUCCESS) {
153 m_state.context.gpr.__pc = (uint32_t)value;
154 err = SetGPRState();
155 }
156 return err == KERN_SUCCESS;
157 }
158
GetSP(uint64_t failValue)159 uint64_t DNBArchMachARM::GetSP(uint64_t failValue) {
160 // Get stack pointer
161 if (GetGPRState(false) == KERN_SUCCESS)
162 return m_state.context.gpr.__sp;
163 return failValue;
164 }
165
GetGPRState(bool force)166 kern_return_t DNBArchMachARM::GetGPRState(bool force) {
167 int set = e_regSetGPR;
168 // Check if we have valid cached registers
169 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
170 return KERN_SUCCESS;
171
172 // Read the registers from our thread
173 mach_msg_type_number_t count = ARM_THREAD_STATE_COUNT;
174 kern_return_t kret =
175 ::thread_get_state(m_thread->MachPortNumber(), ARM_THREAD_STATE,
176 (thread_state_t)&m_state.context.gpr, &count);
177 uint32_t *r = &m_state.context.gpr.__r[0];
178 DNBLogThreadedIf(
179 LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count = "
180 "%u) regs r0=%8.8x r1=%8.8x r2=%8.8x r3=%8.8x r4=%8.8x "
181 "r5=%8.8x r6=%8.8x r7=%8.8x r8=%8.8x r9=%8.8x r10=%8.8x "
182 "r11=%8.8x s12=%8.8x sp=%8.8x lr=%8.8x pc=%8.8x cpsr=%8.8x",
183 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
184 kret, count, r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7], r[8], r[9],
185 r[10], r[11], r[12], r[13], r[14], r[15], r[16]);
186 m_state.SetError(set, Read, kret);
187 return kret;
188 }
189
GetVFPState(bool force)190 kern_return_t DNBArchMachARM::GetVFPState(bool force) {
191 int set = e_regSetVFP;
192 // Check if we have valid cached registers
193 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
194 return KERN_SUCCESS;
195
196 kern_return_t kret;
197
198 #if defined(__arm64__) || defined(__aarch64__)
199 // Read the registers from our thread
200 mach_msg_type_number_t count = ARM_NEON_STATE_COUNT;
201 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
202 (thread_state_t)&m_state.context.vfp, &count);
203 if (DNBLogEnabledForAny(LOG_THREAD)) {
204 DNBLogThreaded(
205 "thread_get_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
206 "\n q0 = 0x%16.16llx%16.16llx"
207 "\n q1 = 0x%16.16llx%16.16llx"
208 "\n q2 = 0x%16.16llx%16.16llx"
209 "\n q3 = 0x%16.16llx%16.16llx"
210 "\n q4 = 0x%16.16llx%16.16llx"
211 "\n q5 = 0x%16.16llx%16.16llx"
212 "\n q6 = 0x%16.16llx%16.16llx"
213 "\n q7 = 0x%16.16llx%16.16llx"
214 "\n q8 = 0x%16.16llx%16.16llx"
215 "\n q9 = 0x%16.16llx%16.16llx"
216 "\n q10 = 0x%16.16llx%16.16llx"
217 "\n q11 = 0x%16.16llx%16.16llx"
218 "\n q12 = 0x%16.16llx%16.16llx"
219 "\n q13 = 0x%16.16llx%16.16llx"
220 "\n q14 = 0x%16.16llx%16.16llx"
221 "\n q15 = 0x%16.16llx%16.16llx"
222 "\n fpsr = 0x%8.8x"
223 "\n fpcr = 0x%8.8x\n\n",
224 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
225 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
226 ((uint64_t *)&m_state.context.vfp.__v[0])[1],
227 ((uint64_t *)&m_state.context.vfp.__v[1])[0],
228 ((uint64_t *)&m_state.context.vfp.__v[1])[1],
229 ((uint64_t *)&m_state.context.vfp.__v[2])[0],
230 ((uint64_t *)&m_state.context.vfp.__v[2])[1],
231 ((uint64_t *)&m_state.context.vfp.__v[3])[0],
232 ((uint64_t *)&m_state.context.vfp.__v[3])[1],
233 ((uint64_t *)&m_state.context.vfp.__v[4])[0],
234 ((uint64_t *)&m_state.context.vfp.__v[4])[1],
235 ((uint64_t *)&m_state.context.vfp.__v[5])[0],
236 ((uint64_t *)&m_state.context.vfp.__v[5])[1],
237 ((uint64_t *)&m_state.context.vfp.__v[6])[0],
238 ((uint64_t *)&m_state.context.vfp.__v[6])[1],
239 ((uint64_t *)&m_state.context.vfp.__v[7])[0],
240 ((uint64_t *)&m_state.context.vfp.__v[7])[1],
241 ((uint64_t *)&m_state.context.vfp.__v[8])[0],
242 ((uint64_t *)&m_state.context.vfp.__v[8])[1],
243 ((uint64_t *)&m_state.context.vfp.__v[9])[0],
244 ((uint64_t *)&m_state.context.vfp.__v[9])[1],
245 ((uint64_t *)&m_state.context.vfp.__v[10])[0],
246 ((uint64_t *)&m_state.context.vfp.__v[10])[1],
247 ((uint64_t *)&m_state.context.vfp.__v[11])[0],
248 ((uint64_t *)&m_state.context.vfp.__v[11])[1],
249 ((uint64_t *)&m_state.context.vfp.__v[12])[0],
250 ((uint64_t *)&m_state.context.vfp.__v[12])[1],
251 ((uint64_t *)&m_state.context.vfp.__v[13])[0],
252 ((uint64_t *)&m_state.context.vfp.__v[13])[1],
253 ((uint64_t *)&m_state.context.vfp.__v[14])[0],
254 ((uint64_t *)&m_state.context.vfp.__v[14])[1],
255 ((uint64_t *)&m_state.context.vfp.__v[15])[0],
256 ((uint64_t *)&m_state.context.vfp.__v[15])[1],
257 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
258 }
259 #else
260 // Read the registers from our thread
261 mach_msg_type_number_t count = ARM_VFP_STATE_COUNT;
262 kret = ::thread_get_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
263 (thread_state_t)&m_state.context.vfp, &count);
264
265 if (DNBLogEnabledForAny(LOG_THREAD)) {
266 uint32_t *r = &m_state.context.vfp.__r[0];
267 DNBLogThreaded(
268 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
269 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
270 kret, count);
271 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
272 "s5=%8.8x s6=%8.8x s7=%8.8x",
273 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
274 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
275 "s13=%8.8x s14=%8.8x s15=%8.8x",
276 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
277 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
278 "s21=%8.8x s22=%8.8x s23=%8.8x",
279 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
280 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
281 "s29=%8.8x s30=%8.8x s31=%8.8x",
282 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
283 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
284 "s37=%8.8x s38=%8.8x s39=%8.8x",
285 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
286 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
287 "s45=%8.8x s46=%8.8x s47=%8.8x",
288 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
289 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
290 "s53=%8.8x s54=%8.8x s55=%8.8x",
291 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
292 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
293 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
294 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
295 r[64]);
296 }
297
298 #endif
299 m_state.SetError(set, Read, kret);
300 return kret;
301 }
302
GetEXCState(bool force)303 kern_return_t DNBArchMachARM::GetEXCState(bool force) {
304 int set = e_regSetEXC;
305 // Check if we have valid cached registers
306 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
307 return KERN_SUCCESS;
308
309 // Read the registers from our thread
310 mach_msg_type_number_t count = ARM_EXCEPTION_STATE_COUNT;
311 kern_return_t kret =
312 ::thread_get_state(m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
313 (thread_state_t)&m_state.context.exc, &count);
314 m_state.SetError(set, Read, kret);
315 return kret;
316 }
317
DumpDBGState(const DNBArchMachARM::DBG & dbg)318 static void DumpDBGState(const DNBArchMachARM::DBG &dbg) {
319 uint32_t i = 0;
320 for (i = 0; i < 16; i++) {
321 DNBLogThreadedIf(LOG_STEP, "BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } "
322 "WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
323 i, i, dbg.__bvr[i], dbg.__bcr[i], i, i, dbg.__wvr[i],
324 dbg.__wcr[i]);
325 }
326 }
327
GetDBGState(bool force)328 kern_return_t DNBArchMachARM::GetDBGState(bool force) {
329 int set = e_regSetDBG;
330
331 // Check if we have valid cached registers
332 if (!force && m_state.GetError(set, Read) == KERN_SUCCESS)
333 return KERN_SUCCESS;
334
335 // Read the registers from our thread
336 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
337 mach_msg_type_number_t count = ARM_DEBUG_STATE32_COUNT;
338 kern_return_t kret =
339 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
340 (thread_state_t)&m_state.dbg, &count);
341 #else
342 mach_msg_type_number_t count = ARM_DEBUG_STATE_COUNT;
343 kern_return_t kret =
344 ::thread_get_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
345 (thread_state_t)&m_state.dbg, &count);
346 #endif
347 m_state.SetError(set, Read, kret);
348
349 return kret;
350 }
351
SetGPRState()352 kern_return_t DNBArchMachARM::SetGPRState() {
353 int set = e_regSetGPR;
354 kern_return_t kret = ::thread_set_state(
355 m_thread->MachPortNumber(), ARM_THREAD_STATE,
356 (thread_state_t)&m_state.context.gpr, ARM_THREAD_STATE_COUNT);
357 m_state.SetError(set, Write,
358 kret); // Set the current write error for this register set
359 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
360 // state in case registers are read
361 // back differently
362 return kret; // Return the error code
363 }
364
SetVFPState()365 kern_return_t DNBArchMachARM::SetVFPState() {
366 int set = e_regSetVFP;
367 kern_return_t kret;
368 mach_msg_type_number_t count;
369
370 #if defined(__arm64__) || defined(__aarch64__)
371 count = ARM_NEON_STATE_COUNT;
372 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_NEON_STATE,
373 (thread_state_t)&m_state.context.vfp, count);
374 #else
375 count = ARM_VFP_STATE_COUNT;
376 kret = ::thread_set_state(m_thread->MachPortNumber(), ARM_VFP_STATE,
377 (thread_state_t)&m_state.context.vfp, count);
378 #endif
379
380 #if defined(__arm64__) || defined(__aarch64__)
381 if (DNBLogEnabledForAny(LOG_THREAD)) {
382 DNBLogThreaded(
383 "thread_set_state(0x%4.4x, %u, &vfp, %u) => 0x%8.8x (count = %u) regs"
384 "\n q0 = 0x%16.16llx%16.16llx"
385 "\n q1 = 0x%16.16llx%16.16llx"
386 "\n q2 = 0x%16.16llx%16.16llx"
387 "\n q3 = 0x%16.16llx%16.16llx"
388 "\n q4 = 0x%16.16llx%16.16llx"
389 "\n q5 = 0x%16.16llx%16.16llx"
390 "\n q6 = 0x%16.16llx%16.16llx"
391 "\n q7 = 0x%16.16llx%16.16llx"
392 "\n q8 = 0x%16.16llx%16.16llx"
393 "\n q9 = 0x%16.16llx%16.16llx"
394 "\n q10 = 0x%16.16llx%16.16llx"
395 "\n q11 = 0x%16.16llx%16.16llx"
396 "\n q12 = 0x%16.16llx%16.16llx"
397 "\n q13 = 0x%16.16llx%16.16llx"
398 "\n q14 = 0x%16.16llx%16.16llx"
399 "\n q15 = 0x%16.16llx%16.16llx"
400 "\n fpsr = 0x%8.8x"
401 "\n fpcr = 0x%8.8x\n\n",
402 m_thread->MachPortNumber(), ARM_NEON_STATE, ARM_NEON_STATE_COUNT, kret,
403 count, ((uint64_t *)&m_state.context.vfp.__v[0])[0],
404 ((uint64_t *)&m_state.context.vfp.__v[0])[1],
405 ((uint64_t *)&m_state.context.vfp.__v[1])[0],
406 ((uint64_t *)&m_state.context.vfp.__v[1])[1],
407 ((uint64_t *)&m_state.context.vfp.__v[2])[0],
408 ((uint64_t *)&m_state.context.vfp.__v[2])[1],
409 ((uint64_t *)&m_state.context.vfp.__v[3])[0],
410 ((uint64_t *)&m_state.context.vfp.__v[3])[1],
411 ((uint64_t *)&m_state.context.vfp.__v[4])[0],
412 ((uint64_t *)&m_state.context.vfp.__v[4])[1],
413 ((uint64_t *)&m_state.context.vfp.__v[5])[0],
414 ((uint64_t *)&m_state.context.vfp.__v[5])[1],
415 ((uint64_t *)&m_state.context.vfp.__v[6])[0],
416 ((uint64_t *)&m_state.context.vfp.__v[6])[1],
417 ((uint64_t *)&m_state.context.vfp.__v[7])[0],
418 ((uint64_t *)&m_state.context.vfp.__v[7])[1],
419 ((uint64_t *)&m_state.context.vfp.__v[8])[0],
420 ((uint64_t *)&m_state.context.vfp.__v[8])[1],
421 ((uint64_t *)&m_state.context.vfp.__v[9])[0],
422 ((uint64_t *)&m_state.context.vfp.__v[9])[1],
423 ((uint64_t *)&m_state.context.vfp.__v[10])[0],
424 ((uint64_t *)&m_state.context.vfp.__v[10])[1],
425 ((uint64_t *)&m_state.context.vfp.__v[11])[0],
426 ((uint64_t *)&m_state.context.vfp.__v[11])[1],
427 ((uint64_t *)&m_state.context.vfp.__v[12])[0],
428 ((uint64_t *)&m_state.context.vfp.__v[12])[1],
429 ((uint64_t *)&m_state.context.vfp.__v[13])[0],
430 ((uint64_t *)&m_state.context.vfp.__v[13])[1],
431 ((uint64_t *)&m_state.context.vfp.__v[14])[0],
432 ((uint64_t *)&m_state.context.vfp.__v[14])[1],
433 ((uint64_t *)&m_state.context.vfp.__v[15])[0],
434 ((uint64_t *)&m_state.context.vfp.__v[15])[1],
435 m_state.context.vfp.__fpsr, m_state.context.vfp.__fpcr);
436 }
437 #else
438 if (DNBLogEnabledForAny(LOG_THREAD)) {
439 uint32_t *r = &m_state.context.vfp.__r[0];
440 DNBLogThreaded(
441 "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x (count => %u)",
442 m_thread->MachPortNumber(), ARM_THREAD_STATE, ARM_THREAD_STATE_COUNT,
443 kret, count);
444 DNBLogThreaded(" s0=%8.8x s1=%8.8x s2=%8.8x s3=%8.8x s4=%8.8x "
445 "s5=%8.8x s6=%8.8x s7=%8.8x",
446 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
447 DNBLogThreaded(" s8=%8.8x s9=%8.8x s10=%8.8x s11=%8.8x s12=%8.8x "
448 "s13=%8.8x s14=%8.8x s15=%8.8x",
449 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
450 DNBLogThreaded(" s16=%8.8x s17=%8.8x s18=%8.8x s19=%8.8x s20=%8.8x "
451 "s21=%8.8x s22=%8.8x s23=%8.8x",
452 r[16], r[17], r[18], r[19], r[20], r[21], r[22], r[23]);
453 DNBLogThreaded(" s24=%8.8x s25=%8.8x s26=%8.8x s27=%8.8x s28=%8.8x "
454 "s29=%8.8x s30=%8.8x s31=%8.8x",
455 r[24], r[25], r[26], r[27], r[28], r[29], r[30], r[31]);
456 DNBLogThreaded(" s32=%8.8x s33=%8.8x s34=%8.8x s35=%8.8x s36=%8.8x "
457 "s37=%8.8x s38=%8.8x s39=%8.8x",
458 r[32], r[33], r[34], r[35], r[36], r[37], r[38], r[39]);
459 DNBLogThreaded(" s40=%8.8x s41=%8.8x s42=%8.8x s43=%8.8x s44=%8.8x "
460 "s45=%8.8x s46=%8.8x s47=%8.8x",
461 r[40], r[41], r[42], r[43], r[44], r[45], r[46], r[47]);
462 DNBLogThreaded(" s48=%8.8x s49=%8.8x s50=%8.8x s51=%8.8x s52=%8.8x "
463 "s53=%8.8x s54=%8.8x s55=%8.8x",
464 r[48], r[49], r[50], r[51], r[52], r[53], r[54], r[55]);
465 DNBLogThreaded(" s56=%8.8x s57=%8.8x s58=%8.8x s59=%8.8x s60=%8.8x "
466 "s61=%8.8x s62=%8.8x s63=%8.8x fpscr=%8.8x",
467 r[56], r[57], r[58], r[59], r[60], r[61], r[62], r[63],
468 r[64]);
469 }
470 #endif
471
472 m_state.SetError(set, Write,
473 kret); // Set the current write error for this register set
474 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
475 // state in case registers are read
476 // back differently
477 return kret; // Return the error code
478 }
479
SetEXCState()480 kern_return_t DNBArchMachARM::SetEXCState() {
481 int set = e_regSetEXC;
482 kern_return_t kret = ::thread_set_state(
483 m_thread->MachPortNumber(), ARM_EXCEPTION_STATE,
484 (thread_state_t)&m_state.context.exc, ARM_EXCEPTION_STATE_COUNT);
485 m_state.SetError(set, Write,
486 kret); // Set the current write error for this register set
487 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
488 // state in case registers are read
489 // back differently
490 return kret; // Return the error code
491 }
492
SetDBGState(bool also_set_on_task)493 kern_return_t DNBArchMachARM::SetDBGState(bool also_set_on_task) {
494 int set = e_regSetDBG;
495 #if defined(ARM_DEBUG_STATE32) && (defined(__arm64__) || defined(__aarch64__))
496 kern_return_t kret =
497 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE32,
498 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
499 if (also_set_on_task) {
500 kern_return_t task_kret = ::task_set_state(
501 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE32,
502 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE32_COUNT);
503 if (task_kret != KERN_SUCCESS)
504 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
505 "set debug control register state: "
506 "0x%8.8x.",
507 kret);
508 }
509 #else
510 kern_return_t kret =
511 ::thread_set_state(m_thread->MachPortNumber(), ARM_DEBUG_STATE,
512 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
513 if (also_set_on_task) {
514 kern_return_t task_kret = ::task_set_state(
515 m_thread->Process()->Task().TaskPort(), ARM_DEBUG_STATE,
516 (thread_state_t)&m_state.dbg, ARM_DEBUG_STATE_COUNT);
517 if (task_kret != KERN_SUCCESS)
518 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::SetDBGState failed to "
519 "set debug control register state: "
520 "0x%8.8x.",
521 kret);
522 }
523 #endif
524
525 m_state.SetError(set, Write,
526 kret); // Set the current write error for this register set
527 m_state.InvalidateRegisterSetState(set); // Invalidate the current register
528 // state in case registers are read
529 // back differently
530 return kret; // Return the error code
531 }
532
ThreadWillResume()533 void DNBArchMachARM::ThreadWillResume() {
534 // Do we need to step this thread? If so, let the mach thread tell us so.
535 if (m_thread->IsStepping()) {
536 // This is the primary thread, let the arch do anything it needs
537 if (NumSupportedHardwareBreakpoints() > 0) {
538 if (EnableHardwareSingleStep(true) != KERN_SUCCESS) {
539 DNBLogThreaded("DNBArchMachARM::ThreadWillResume() failed to enable "
540 "hardware single step");
541 }
542 }
543 }
544
545 // Disable the triggered watchpoint temporarily before we resume.
546 // Plus, we try to enable hardware single step to execute past the instruction
547 // which triggered our watchpoint.
548 if (m_watchpoint_did_occur) {
549 if (m_watchpoint_hw_index >= 0) {
550 kern_return_t kret = GetDBGState(false);
551 if (kret == KERN_SUCCESS &&
552 !IsWatchpointEnabled(m_state.dbg, m_watchpoint_hw_index)) {
553 // The watchpoint might have been disabled by the user. We don't need
554 // to do anything at all
555 // to enable hardware single stepping.
556 m_watchpoint_did_occur = false;
557 m_watchpoint_hw_index = -1;
558 return;
559 }
560
561 DisableHardwareWatchpoint(m_watchpoint_hw_index, false);
562 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
563 "DisableHardwareWatchpoint(%d) called",
564 m_watchpoint_hw_index);
565
566 // Enable hardware single step to move past the watchpoint-triggering
567 // instruction.
568 m_watchpoint_resume_single_step_enabled =
569 (EnableHardwareSingleStep(true) == KERN_SUCCESS);
570
571 // If we are not able to enable single step to move past the
572 // watchpoint-triggering instruction,
573 // at least we should reset the two watchpoint member variables so that
574 // the next time around
575 // this callback function is invoked, the enclosing logical branch is
576 // skipped.
577 if (!m_watchpoint_resume_single_step_enabled) {
578 // Reset the two watchpoint member variables.
579 m_watchpoint_did_occur = false;
580 m_watchpoint_hw_index = -1;
581 DNBLogThreadedIf(
582 LOG_WATCHPOINTS,
583 "DNBArchMachARM::ThreadWillResume() failed to enable single step");
584 } else
585 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::ThreadWillResume() "
586 "succeeded to enable single step");
587 }
588 }
589 }
590
ThreadDidStop()591 bool DNBArchMachARM::ThreadDidStop() {
592 bool success = true;
593
594 m_state.InvalidateRegisterSetState(e_regSetALL);
595
596 if (m_watchpoint_resume_single_step_enabled) {
597 // Great! We now disable the hardware single step as well as re-enable the
598 // hardware watchpoint.
599 // See also ThreadWillResume().
600 if (EnableHardwareSingleStep(false) == KERN_SUCCESS) {
601 if (m_watchpoint_did_occur && m_watchpoint_hw_index >= 0) {
602 ReenableHardwareWatchpoint(m_watchpoint_hw_index);
603 m_watchpoint_resume_single_step_enabled = false;
604 m_watchpoint_did_occur = false;
605 m_watchpoint_hw_index = -1;
606 } else {
607 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
608 "is true but (m_watchpoint_did_occur && "
609 "m_watchpoint_hw_index >= 0) does not hold!");
610 }
611 } else {
612 DNBLogError("internal error detected: m_watchpoint_resume_step_enabled "
613 "is true but unable to disable single step!");
614 }
615 }
616
617 // Are we stepping a single instruction?
618 if (GetGPRState(true) == KERN_SUCCESS) {
619 // We are single stepping, was this the primary thread?
620 if (m_thread->IsStepping()) {
621 success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
622 } else {
623 // The MachThread will automatically restore the suspend count
624 // in ThreadDidStop(), so we don't need to do anything here if
625 // we weren't the primary thread the last time
626 }
627 }
628 return success;
629 }
630
NotifyException(MachException::Data & exc)631 bool DNBArchMachARM::NotifyException(MachException::Data &exc) {
632 switch (exc.exc_type) {
633 default:
634 break;
635 case EXC_BREAKPOINT:
636 if (exc.exc_data.size() == 2 && exc.exc_data[0] == EXC_ARM_DA_DEBUG) {
637 // The data break address is passed as exc_data[1].
638 nub_addr_t addr = exc.exc_data[1];
639 // Find the hardware index with the side effect of possibly massaging the
640 // addr to return the starting address as seen from the debugger side.
641 uint32_t hw_index = GetHardwareWatchpointHit(addr);
642 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
643 "watchpoint %d was hit on address "
644 "0x%llx",
645 hw_index, (uint64_t)addr);
646 const int num_watchpoints = NumSupportedHardwareWatchpoints();
647 for (int i = 0; i < num_watchpoints; i++) {
648 if (LoHi[i] != 0 && LoHi[i] == hw_index && LoHi[i] != i &&
649 GetWatchpointAddressByIndex(i) != INVALID_NUB_ADDRESS) {
650 addr = GetWatchpointAddressByIndex(i);
651 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::NotifyException "
652 "It is a linked watchpoint; "
653 "rewritten to index %d addr 0x%llx",
654 LoHi[i], (uint64_t)addr);
655 }
656 }
657 if (hw_index != INVALID_NUB_HW_INDEX) {
658 m_watchpoint_did_occur = true;
659 m_watchpoint_hw_index = hw_index;
660 exc.exc_data[1] = addr;
661 // Piggyback the hw_index in the exc.data.
662 exc.exc_data.push_back(hw_index);
663 }
664
665 return true;
666 }
667 break;
668 }
669 return false;
670 }
671
StepNotComplete()672 bool DNBArchMachARM::StepNotComplete() {
673 if (m_hw_single_chained_step_addr != INVALID_NUB_ADDRESS) {
674 kern_return_t kret = KERN_INVALID_ARGUMENT;
675 kret = GetGPRState(false);
676 if (kret == KERN_SUCCESS) {
677 if (m_state.context.gpr.__pc == m_hw_single_chained_step_addr) {
678 DNBLogThreadedIf(LOG_STEP, "Need to step some more at 0x%8.8llx",
679 (uint64_t)m_hw_single_chained_step_addr);
680 return true;
681 }
682 }
683 }
684
685 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
686 return false;
687 }
688
689 // Set the single step bit in the processor status register.
EnableHardwareSingleStep(bool enable)690 kern_return_t DNBArchMachARM::EnableHardwareSingleStep(bool enable) {
691 DNBError err;
692 DNBLogThreadedIf(LOG_STEP, "%s( enable = %d )", __FUNCTION__, enable);
693
694 err = GetGPRState(false);
695
696 if (err.Fail()) {
697 err.LogThreaded("%s: failed to read the GPR registers", __FUNCTION__);
698 return err.Status();
699 }
700
701 err = GetDBGState(false);
702
703 if (err.Fail()) {
704 err.LogThreaded("%s: failed to read the DBG registers", __FUNCTION__);
705 return err.Status();
706 }
707
708 // The use of __arm64__ here is not ideal. If debugserver is running on
709 // an armv8 device, regardless of whether it was built for arch arm or arch
710 // arm64,
711 // it needs to use the MDSCR_EL1 SS bit to single instruction step.
712
713 #if defined(__arm64__) || defined(__aarch64__)
714 if (enable) {
715 DNBLogThreadedIf(LOG_STEP,
716 "%s: Setting MDSCR_EL1 Single Step bit at pc 0x%llx",
717 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
718 m_state.dbg.__mdscr_el1 |=
719 1; // Set bit 0 (single step, SS) in the MDSCR_EL1.
720 } else {
721 DNBLogThreadedIf(LOG_STEP,
722 "%s: Clearing MDSCR_EL1 Single Step bit at pc 0x%llx",
723 __FUNCTION__, (uint64_t)m_state.context.gpr.__pc);
724 m_state.dbg.__mdscr_el1 &=
725 ~(1ULL); // Clear bit 0 (single step, SS) in the MDSCR_EL1.
726 }
727 #else
728 const uint32_t i = 0;
729 if (enable) {
730 m_hw_single_chained_step_addr = INVALID_NUB_ADDRESS;
731
732 // Save our previous state
733 m_dbg_save = m_state.dbg;
734 // Set a breakpoint that will stop when the PC doesn't match the current
735 // one!
736 m_state.dbg.__bvr[i] =
737 m_state.context.gpr.__pc &
738 0xFFFFFFFCu; // Set the current PC as the breakpoint address
739 m_state.dbg.__bcr[i] = BCR_M_IMVA_MISMATCH | // Stop on address mismatch
740 S_USER | // Stop only in user mode
741 BCR_ENABLE; // Enable this breakpoint
742 if (m_state.context.gpr.__cpsr & 0x20) {
743 // Thumb breakpoint
744 if (m_state.context.gpr.__pc & 2)
745 m_state.dbg.__bcr[i] |= BAS_IMVA_2_3;
746 else
747 m_state.dbg.__bcr[i] |= BAS_IMVA_0_1;
748
749 uint16_t opcode;
750 if (sizeof(opcode) ==
751 m_thread->Process()->Task().ReadMemory(m_state.context.gpr.__pc,
752 sizeof(opcode), &opcode)) {
753 if (IsThumb32Opcode(opcode)) {
754 // 32 bit thumb opcode...
755 if (m_state.context.gpr.__pc & 2) {
756 // We can't take care of a 32 bit thumb instruction single step
757 // with just IVA mismatching. We will need to chain an extra
758 // hardware single step in order to complete this single step...
759 m_hw_single_chained_step_addr = m_state.context.gpr.__pc + 2;
760 } else {
761 // Extend the number of bits to ignore for the mismatch
762 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL;
763 }
764 }
765 }
766 } else {
767 // ARM breakpoint
768 m_state.dbg.__bcr[i] |= BAS_IMVA_ALL; // Stop when any address bits change
769 }
770
771 DNBLogThreadedIf(LOG_STEP, "%s: BVR%u=0x%8.8x BCR%u=0x%8.8x", __FUNCTION__,
772 i, m_state.dbg.__bvr[i], i, m_state.dbg.__bcr[i]);
773
774 for (uint32_t j = i + 1; j < 16; ++j) {
775 // Disable all others
776 m_state.dbg.__bvr[j] = 0;
777 m_state.dbg.__bcr[j] = 0;
778 }
779 } else {
780 // Just restore the state we had before we did single stepping
781 m_state.dbg = m_dbg_save;
782 }
783 #endif
784
785 return SetDBGState(false);
786 }
787
788 // return 1 if bit "BIT" is set in "value"
bit(uint32_t value,uint32_t bit)789 static inline uint32_t bit(uint32_t value, uint32_t bit) {
790 return (value >> bit) & 1u;
791 }
792
793 // return the bitfield "value[msbit:lsbit]".
bits(uint32_t value,uint32_t msbit,uint32_t lsbit)794 static inline uint32_t bits(uint32_t value, uint32_t msbit, uint32_t lsbit) {
795 assert(msbit >= lsbit);
796 uint32_t shift_left = sizeof(value) * 8 - 1 - msbit;
797 value <<=
798 shift_left; // shift anything above the msbit off of the unsigned edge
799 value >>= (shift_left + lsbit); // shift it back again down to the lsbit
800 // (including undoing any shift from above)
801 return value; // return our result
802 }
803
ConditionPassed(uint8_t condition,uint32_t cpsr)804 bool DNBArchMachARM::ConditionPassed(uint8_t condition, uint32_t cpsr) {
805 uint32_t cpsr_n = bit(cpsr, 31); // Negative condition code flag
806 uint32_t cpsr_z = bit(cpsr, 30); // Zero condition code flag
807 uint32_t cpsr_c = bit(cpsr, 29); // Carry condition code flag
808 uint32_t cpsr_v = bit(cpsr, 28); // Overflow condition code flag
809
810 switch (condition) {
811 case COND_EQ: // (0x0)
812 if (cpsr_z == 1)
813 return true;
814 break;
815 case COND_NE: // (0x1)
816 if (cpsr_z == 0)
817 return true;
818 break;
819 case COND_CS: // (0x2)
820 if (cpsr_c == 1)
821 return true;
822 break;
823 case COND_CC: // (0x3)
824 if (cpsr_c == 0)
825 return true;
826 break;
827 case COND_MI: // (0x4)
828 if (cpsr_n == 1)
829 return true;
830 break;
831 case COND_PL: // (0x5)
832 if (cpsr_n == 0)
833 return true;
834 break;
835 case COND_VS: // (0x6)
836 if (cpsr_v == 1)
837 return true;
838 break;
839 case COND_VC: // (0x7)
840 if (cpsr_v == 0)
841 return true;
842 break;
843 case COND_HI: // (0x8)
844 if ((cpsr_c == 1) && (cpsr_z == 0))
845 return true;
846 break;
847 case COND_LS: // (0x9)
848 if ((cpsr_c == 0) || (cpsr_z == 1))
849 return true;
850 break;
851 case COND_GE: // (0xA)
852 if (cpsr_n == cpsr_v)
853 return true;
854 break;
855 case COND_LT: // (0xB)
856 if (cpsr_n != cpsr_v)
857 return true;
858 break;
859 case COND_GT: // (0xC)
860 if ((cpsr_z == 0) && (cpsr_n == cpsr_v))
861 return true;
862 break;
863 case COND_LE: // (0xD)
864 if ((cpsr_z == 1) || (cpsr_n != cpsr_v))
865 return true;
866 break;
867 default:
868 return true;
869 break;
870 }
871
872 return false;
873 }
874
NumSupportedHardwareBreakpoints()875 uint32_t DNBArchMachARM::NumSupportedHardwareBreakpoints() {
876 // Set the init value to something that will let us know that we need to
877 // autodetect how many breakpoints are supported dynamically...
878 static uint32_t g_num_supported_hw_breakpoints = UINT_MAX;
879 if (g_num_supported_hw_breakpoints == UINT_MAX) {
880 // Set this to zero in case we can't tell if there are any HW breakpoints
881 g_num_supported_hw_breakpoints = 0;
882
883 size_t len;
884 uint32_t n = 0;
885 len = sizeof(n);
886 if (::sysctlbyname("hw.optional.breakpoint", &n, &len, NULL, 0) == 0) {
887 g_num_supported_hw_breakpoints = n;
888 DNBLogThreadedIf(LOG_THREAD, "hw.optional.breakpoint=%u", n);
889 } else {
890 #if !defined(__arm64__) && !defined(__aarch64__)
891 // Read the DBGDIDR to get the number of available hardware breakpoints
892 // However, in some of our current armv7 processors, hardware
893 // breakpoints/watchpoints were not properly connected. So detect those
894 // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
895 // field to distinguish CPU architectures. This is a hack until we can
896 // get <rdar://problem/6372672> fixed, at which point we will switch to
897 // using a different sysctl string that will tell us how many BRPs
898 // are available to us directly without having to read DBGDIDR.
899 uint32_t register_DBGDIDR;
900
901 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
902 uint32_t numBRPs = bits(register_DBGDIDR, 27, 24);
903 // Zero is reserved for the BRP count, so don't increment it if it is zero
904 if (numBRPs > 0)
905 numBRPs++;
906 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number BRP pairs = %u)",
907 register_DBGDIDR, numBRPs);
908
909 if (numBRPs > 0) {
910 uint32_t cpusubtype;
911 len = sizeof(cpusubtype);
912 // TODO: remove this hack and change to using hw.optional.xx when
913 // implmented
914 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
915 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=%d", cpusubtype);
916 if (cpusubtype == CPU_SUBTYPE_ARM_V7)
917 DNBLogThreadedIf(LOG_THREAD, "Hardware breakpoints disabled for "
918 "armv7 (rdar://problem/6372672)");
919 else
920 g_num_supported_hw_breakpoints = numBRPs;
921 }
922 }
923 #endif
924 }
925 }
926 return g_num_supported_hw_breakpoints;
927 }
928
NumSupportedHardwareWatchpoints()929 uint32_t DNBArchMachARM::NumSupportedHardwareWatchpoints() {
930 // Set the init value to something that will let us know that we need to
931 // autodetect how many watchpoints are supported dynamically...
932 static uint32_t g_num_supported_hw_watchpoints = UINT_MAX;
933 if (g_num_supported_hw_watchpoints == UINT_MAX) {
934 // Set this to zero in case we can't tell if there are any HW breakpoints
935 g_num_supported_hw_watchpoints = 0;
936
937 size_t len;
938 uint32_t n = 0;
939 len = sizeof(n);
940 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
941 g_num_supported_hw_watchpoints = n;
942 DNBLogThreadedIf(LOG_THREAD, "hw.optional.watchpoint=%u", n);
943 } else {
944 #if !defined(__arm64__) && !defined(__aarch64__)
945 // Read the DBGDIDR to get the number of available hardware breakpoints
946 // However, in some of our current armv7 processors, hardware
947 // breakpoints/watchpoints were not properly connected. So detect those
948 // cases using a field in a sysctl. For now we are using "hw.cpusubtype"
949 // field to distinguish CPU architectures. This is a hack until we can
950 // get <rdar://problem/6372672> fixed, at which point we will switch to
951 // using a different sysctl string that will tell us how many WRPs
952 // are available to us directly without having to read DBGDIDR.
953
954 uint32_t register_DBGDIDR;
955 asm("mrc p14, 0, %0, c0, c0, 0" : "=r"(register_DBGDIDR));
956 uint32_t numWRPs = bits(register_DBGDIDR, 31, 28) + 1;
957 DNBLogThreadedIf(LOG_THREAD, "DBGDIDR=0x%8.8x (number WRP pairs = %u)",
958 register_DBGDIDR, numWRPs);
959
960 if (numWRPs > 0) {
961 uint32_t cpusubtype;
962 size_t len;
963 len = sizeof(cpusubtype);
964 // TODO: remove this hack and change to using hw.optional.xx when
965 // implmented
966 if (::sysctlbyname("hw.cpusubtype", &cpusubtype, &len, NULL, 0) == 0) {
967 DNBLogThreadedIf(LOG_THREAD, "hw.cpusubtype=0x%d", cpusubtype);
968
969 if (cpusubtype == CPU_SUBTYPE_ARM_V7)
970 DNBLogThreadedIf(LOG_THREAD, "Hardware watchpoints disabled for "
971 "armv7 (rdar://problem/6372672)");
972 else
973 g_num_supported_hw_watchpoints = numWRPs;
974 }
975 }
976 #endif
977 }
978 }
979 return g_num_supported_hw_watchpoints;
980 }
981
EnableHardwareBreakpoint(nub_addr_t addr,nub_size_t size,bool also_set_on_task)982 uint32_t DNBArchMachARM::EnableHardwareBreakpoint(nub_addr_t addr,
983 nub_size_t size,
984 bool also_set_on_task) {
985 // Make sure our address isn't bogus
986 if (addr & 1)
987 return INVALID_NUB_HW_INDEX;
988
989 kern_return_t kret = GetDBGState(false);
990
991 if (kret == KERN_SUCCESS) {
992 const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
993 uint32_t i;
994 for (i = 0; i < num_hw_breakpoints; ++i) {
995 if ((m_state.dbg.__bcr[i] & BCR_ENABLE) == 0)
996 break; // We found an available hw breakpoint slot (in i)
997 }
998
999 // See if we found an available hw breakpoint slot above
1000 if (i < num_hw_breakpoints) {
1001 // Make sure bits 1:0 are clear in our address
1002 m_state.dbg.__bvr[i] = addr & ~((nub_addr_t)3);
1003
1004 if (size == 2 || addr & 2) {
1005 uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
1006
1007 // We have a thumb breakpoint
1008 // We have an ARM breakpoint
1009 m_state.dbg.__bcr[i] =
1010 BCR_M_IMVA_MATCH | // Stop on address mismatch
1011 byte_addr_select | // Set the correct byte address select so we only
1012 // trigger on the correct opcode
1013 S_USER | // Which modes should this breakpoint stop in?
1014 BCR_ENABLE; // Enable this hardware breakpoint
1015 DNBLogThreadedIf(LOG_BREAKPOINTS,
1016 "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
1017 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
1018 "0x%8.8x (Thumb)",
1019 (uint64_t)addr, (uint64_t)size, i, i,
1020 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
1021 } else if (size == 4) {
1022 // We have an ARM breakpoint
1023 m_state.dbg.__bcr[i] =
1024 BCR_M_IMVA_MATCH | // Stop on address mismatch
1025 BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
1026 S_USER | // Which modes should this breakpoint stop in?
1027 BCR_ENABLE; // Enable this hardware breakpoint
1028 DNBLogThreadedIf(LOG_BREAKPOINTS,
1029 "DNBArchMachARM::EnableHardwareBreakpoint( addr = "
1030 "0x%8.8llx, size = %llu ) - BVR%u/BCR%u = 0x%8.8x / "
1031 "0x%8.8x (ARM)",
1032 (uint64_t)addr, (uint64_t)size, i, i,
1033 m_state.dbg.__bvr[i], m_state.dbg.__bcr[i]);
1034 }
1035
1036 kret = SetDBGState(false);
1037 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::"
1038 "EnableHardwareBreakpoint() "
1039 "SetDBGState() => 0x%8.8x.",
1040 kret);
1041
1042 if (kret == KERN_SUCCESS)
1043 return i;
1044 } else {
1045 DNBLogThreadedIf(LOG_BREAKPOINTS,
1046 "DNBArchMachARM::EnableHardwareBreakpoint(addr = "
1047 "0x%8.8llx, size = %llu) => all hardware breakpoint "
1048 "resources are being used.",
1049 (uint64_t)addr, (uint64_t)size);
1050 }
1051 }
1052
1053 return INVALID_NUB_HW_INDEX;
1054 }
1055
DisableHardwareBreakpoint(uint32_t hw_index,bool also_set_on_task)1056 bool DNBArchMachARM::DisableHardwareBreakpoint(uint32_t hw_index,
1057 bool also_set_on_task) {
1058 kern_return_t kret = GetDBGState(false);
1059
1060 const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
1061 if (kret == KERN_SUCCESS) {
1062 if (hw_index < num_hw_points) {
1063 m_state.dbg.__bcr[hw_index] = 0;
1064 DNBLogThreadedIf(LOG_BREAKPOINTS, "DNBArchMachARM::SetHardwareBreakpoint("
1065 " %u ) - BVR%u = 0x%8.8x BCR%u = "
1066 "0x%8.8x",
1067 hw_index, hw_index, m_state.dbg.__bvr[hw_index],
1068 hw_index, m_state.dbg.__bcr[hw_index]);
1069
1070 kret = SetDBGState(false);
1071
1072 if (kret == KERN_SUCCESS)
1073 return true;
1074 }
1075 }
1076 return false;
1077 }
1078
1079 // ARM v7 watchpoints may be either word-size or double-word-size.
1080 // It's implementation defined which they can handle. It looks like on an
1081 // armv8 device, armv7 processes can watch dwords. But on a genuine armv7
1082 // device I tried, only word watchpoints are supported.
1083
1084 #if defined(__arm64__) || defined(__aarch64__)
1085 #define WATCHPOINTS_ARE_DWORD 1
1086 #else
1087 #undef WATCHPOINTS_ARE_DWORD
1088 #endif
1089
EnableHardwareWatchpoint(nub_addr_t addr,nub_size_t size,bool read,bool write,bool also_set_on_task)1090 uint32_t DNBArchMachARM::EnableHardwareWatchpoint(nub_addr_t addr,
1091 nub_size_t size, bool read,
1092 bool write,
1093 bool also_set_on_task) {
1094
1095 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint("
1096 "addr = 0x%8.8llx, size = %zu, read = %u, "
1097 "write = %u)",
1098 (uint64_t)addr, size, read, write);
1099
1100 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
1101
1102 // Can't watch zero bytes
1103 if (size == 0)
1104 return INVALID_NUB_HW_INDEX;
1105
1106 // We must watch for either read or write
1107 if (read == false && write == false)
1108 return INVALID_NUB_HW_INDEX;
1109
1110 // Otherwise, can't watch more than 8 bytes per WVR/WCR pair
1111 if (size > 8)
1112 return INVALID_NUB_HW_INDEX;
1113
1114 // Treat arm watchpoints as having an 8-byte alignment requirement. You can put
1115 // a watchpoint on a 4-byte
1116 // offset address but you can only watch 4 bytes with that watchpoint.
1117
1118 // arm watchpoints on an 8-byte (double word) aligned addr can watch any bytes
1119 // in that
1120 // 8-byte long region of memory. They can watch the 1st byte, the 2nd byte, 3rd
1121 // byte, etc, or any
1122 // combination therein by setting the bits in the BAS [12:5] (Byte Address
1123 // Select) field of
1124 // the DBGWCRn_EL1 reg for the watchpoint.
1125
1126 // If the MASK [28:24] bits in the DBGWCRn_EL1 allow a single watchpoint to
1127 // monitor a larger region
1128 // of memory (16 bytes, 32 bytes, or 2GB) but the Byte Address Select bitfield
1129 // then selects a larger
1130 // range of bytes, instead of individual bytes. See the ARMv8 Debug
1131 // Architecture manual for details.
1132 // This implementation does not currently use the MASK bits; the largest single
1133 // region watched by a single
1134 // watchpoint right now is 8-bytes.
1135
1136 #if defined(WATCHPOINTS_ARE_DWORD)
1137 nub_addr_t aligned_wp_address = addr & ~0x7;
1138 uint32_t addr_dword_offset = addr & 0x7;
1139 const int max_watchpoint_size = 8;
1140 #else
1141 nub_addr_t aligned_wp_address = addr & ~0x3;
1142 uint32_t addr_dword_offset = addr & 0x3;
1143 const int max_watchpoint_size = 4;
1144 #endif
1145
1146 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint "
1147 "aligned_wp_address is 0x%llx and "
1148 "addr_dword_offset is 0x%x",
1149 (uint64_t)aligned_wp_address, addr_dword_offset);
1150
1151 // Do we need to split up this logical watchpoint into two hardware watchpoint
1152 // registers?
1153 // e.g. a watchpoint of length 4 on address 6. We need do this with
1154 // one watchpoint on address 0 with bytes 6 & 7 being monitored
1155 // one watchpoint on address 8 with bytes 0, 1, 2, 3 being monitored
1156
1157 if (addr_dword_offset + size > max_watchpoint_size) {
1158 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1159 "EnableHardwareWatchpoint(addr = "
1160 "0x%8.8llx, size = %zu) needs two "
1161 "hardware watchpoints slots to monitor",
1162 (uint64_t)addr, size);
1163 int low_watchpoint_size = max_watchpoint_size - addr_dword_offset;
1164 int high_watchpoint_size = addr_dword_offset + size - max_watchpoint_size;
1165
1166 uint32_t lo = EnableHardwareWatchpoint(addr, low_watchpoint_size, read,
1167 write, also_set_on_task);
1168 if (lo == INVALID_NUB_HW_INDEX)
1169 return INVALID_NUB_HW_INDEX;
1170 uint32_t hi = EnableHardwareWatchpoint(
1171 aligned_wp_address + max_watchpoint_size, high_watchpoint_size, read,
1172 write, also_set_on_task);
1173 if (hi == INVALID_NUB_HW_INDEX) {
1174 DisableHardwareWatchpoint(lo, also_set_on_task);
1175 return INVALID_NUB_HW_INDEX;
1176 }
1177 // Tag this lo->hi mapping in our database.
1178 LoHi[lo] = hi;
1179 return lo;
1180 }
1181
1182 // At this point
1183 // 1 aligned_wp_address is the requested address rounded down to 8-byte
1184 // alignment
1185 // 2 addr_dword_offset is the offset into that double word (8-byte) region
1186 // that we are watching
1187 // 3 size is the number of bytes within that 8-byte region that we are
1188 // watching
1189
1190 // Set the Byte Address Selects bits DBGWCRn_EL1 bits [12:5] based on the
1191 // above.
1192 // The bit shift and negation operation will give us 0b11 for 2, 0b1111 for 4,
1193 // etc, up to 0b11111111 for 8.
1194 // then we shift those bits left by the offset into this dword that we are
1195 // interested in.
1196 // e.g. if we are watching bytes 4,5,6,7 in a dword we want a BAS of
1197 // 0b11110000.
1198 uint32_t byte_address_select = ((1 << size) - 1) << addr_dword_offset;
1199
1200 // Read the debug state
1201 kern_return_t kret = GetDBGState(true);
1202
1203 if (kret == KERN_SUCCESS) {
1204 // Check to make sure we have the needed hardware support
1205 uint32_t i = 0;
1206
1207 for (i = 0; i < num_hw_watchpoints; ++i) {
1208 if ((m_state.dbg.__wcr[i] & WCR_ENABLE) == 0)
1209 break; // We found an available hw watchpoint slot (in i)
1210 }
1211
1212 // See if we found an available hw watchpoint slot above
1213 if (i < num_hw_watchpoints) {
1214 // DumpDBGState(m_state.dbg);
1215
1216 // Clear any previous LoHi joined-watchpoint that may have been in use
1217 LoHi[i] = 0;
1218
1219 // shift our Byte Address Select bits up to the correct bit range for the
1220 // DBGWCRn_EL1
1221 byte_address_select = byte_address_select << 5;
1222
1223 // Make sure bits 1:0 are clear in our address
1224 m_state.dbg.__wvr[i] = aligned_wp_address; // DVA (Data Virtual Address)
1225 m_state.dbg.__wcr[i] = byte_address_select | // Which bytes that follow
1226 // the DVA that we will watch
1227 S_USER | // Stop only in user mode
1228 (read ? WCR_LOAD : 0) | // Stop on read access?
1229 (write ? WCR_STORE : 0) | // Stop on write access?
1230 WCR_ENABLE; // Enable this watchpoint;
1231
1232 DNBLogThreadedIf(
1233 LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint() adding "
1234 "watchpoint on address 0x%llx with control register "
1235 "value 0x%x",
1236 (uint64_t)m_state.dbg.__wvr[i], (uint32_t)m_state.dbg.__wcr[i]);
1237
1238 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
1239 // automatically, don't need to do it here.
1240
1241 kret = SetDBGState(also_set_on_task);
1242 // DumpDBGState(m_state.dbg);
1243
1244 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1245 "EnableHardwareWatchpoint() "
1246 "SetDBGState() => 0x%8.8x.",
1247 kret);
1248
1249 if (kret == KERN_SUCCESS)
1250 return i;
1251 } else {
1252 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1253 "EnableHardwareWatchpoint(): All "
1254 "hardware resources (%u) are in use.",
1255 num_hw_watchpoints);
1256 }
1257 }
1258 return INVALID_NUB_HW_INDEX;
1259 }
1260
ReenableHardwareWatchpoint(uint32_t hw_index)1261 bool DNBArchMachARM::ReenableHardwareWatchpoint(uint32_t hw_index) {
1262 // If this logical watchpoint # is actually implemented using
1263 // two hardware watchpoint registers, re-enable both of them.
1264
1265 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
1266 return ReenableHardwareWatchpoint_helper(hw_index) &&
1267 ReenableHardwareWatchpoint_helper(LoHi[hw_index]);
1268 } else {
1269 return ReenableHardwareWatchpoint_helper(hw_index);
1270 }
1271 }
1272
ReenableHardwareWatchpoint_helper(uint32_t hw_index)1273 bool DNBArchMachARM::ReenableHardwareWatchpoint_helper(uint32_t hw_index) {
1274 kern_return_t kret = GetDBGState(false);
1275 if (kret != KERN_SUCCESS)
1276 return false;
1277 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1278 if (hw_index >= num_hw_points)
1279 return false;
1280
1281 m_state.dbg.__wvr[hw_index] = m_disabled_watchpoints[hw_index].addr;
1282 m_state.dbg.__wcr[hw_index] = m_disabled_watchpoints[hw_index].control;
1283
1284 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::EnableHardwareWatchpoint( "
1285 "%u ) - WVR%u = 0x%8.8llx WCR%u = "
1286 "0x%8.8llx",
1287 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
1288 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
1289
1290 // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
1291 // automatically, don't need to do it here.
1292
1293 kret = SetDBGState(false);
1294
1295 return (kret == KERN_SUCCESS);
1296 }
1297
DisableHardwareWatchpoint(uint32_t hw_index,bool also_set_on_task)1298 bool DNBArchMachARM::DisableHardwareWatchpoint(uint32_t hw_index,
1299 bool also_set_on_task) {
1300 if (hw_index < NumSupportedHardwareWatchpoints() && LoHi[hw_index]) {
1301 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task) &&
1302 DisableHardwareWatchpoint_helper(LoHi[hw_index], also_set_on_task);
1303 } else {
1304 return DisableHardwareWatchpoint_helper(hw_index, also_set_on_task);
1305 }
1306 }
1307
DisableHardwareWatchpoint_helper(uint32_t hw_index,bool also_set_on_task)1308 bool DNBArchMachARM::DisableHardwareWatchpoint_helper(uint32_t hw_index,
1309 bool also_set_on_task) {
1310 kern_return_t kret = GetDBGState(false);
1311 if (kret != KERN_SUCCESS)
1312 return false;
1313
1314 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1315 if (hw_index >= num_hw_points)
1316 return false;
1317
1318 m_disabled_watchpoints[hw_index].addr = m_state.dbg.__wvr[hw_index];
1319 m_disabled_watchpoints[hw_index].control = m_state.dbg.__wcr[hw_index];
1320
1321 m_state.dbg.__wvr[hw_index] = 0;
1322 m_state.dbg.__wcr[hw_index] = 0;
1323 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::DisableHardwareWatchpoint("
1324 " %u ) - WVR%u = 0x%8.8llx WCR%u = "
1325 "0x%8.8llx",
1326 hw_index, hw_index, (uint64_t)m_state.dbg.__wvr[hw_index],
1327 hw_index, (uint64_t)m_state.dbg.__wcr[hw_index]);
1328
1329 kret = SetDBGState(also_set_on_task);
1330
1331 return (kret == KERN_SUCCESS);
1332 }
1333
1334 // Returns -1 if the trailing bit patterns are not one of:
1335 // { 0b???1, 0b??10, 0b?100, 0b1000 }.
LowestBitSet(uint32_t val)1336 static inline int32_t LowestBitSet(uint32_t val) {
1337 for (unsigned i = 0; i < 4; ++i) {
1338 if (bit(val, i))
1339 return i;
1340 }
1341 return -1;
1342 }
1343
1344 // Iterate through the debug registers; return the index of the first watchpoint
1345 // whose address matches.
1346 // As a side effect, the starting address as understood by the debugger is
1347 // returned which could be
1348 // different from 'addr' passed as an in/out argument.
GetHardwareWatchpointHit(nub_addr_t & addr)1349 uint32_t DNBArchMachARM::GetHardwareWatchpointHit(nub_addr_t &addr) {
1350 // Read the debug state
1351 kern_return_t kret = GetDBGState(true);
1352 // DumpDBGState(m_state.dbg);
1353 DNBLogThreadedIf(
1354 LOG_WATCHPOINTS,
1355 "DNBArchMachARM::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.",
1356 kret);
1357 DNBLogThreadedIf(LOG_WATCHPOINTS,
1358 "DNBArchMachARM::GetHardwareWatchpointHit() addr = 0x%llx",
1359 (uint64_t)addr);
1360
1361 // This is the watchpoint value to match against, i.e., word address.
1362 #if defined(WATCHPOINTS_ARE_DWORD)
1363 nub_addr_t wp_val = addr & ~((nub_addr_t)7);
1364 #else
1365 nub_addr_t wp_val = addr & ~((nub_addr_t)3);
1366 #endif
1367 if (kret == KERN_SUCCESS) {
1368 DBG &debug_state = m_state.dbg;
1369 uint32_t i, num = NumSupportedHardwareWatchpoints();
1370 for (i = 0; i < num; ++i) {
1371 nub_addr_t wp_addr = GetWatchAddress(debug_state, i);
1372 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchMachARM::"
1373 "GetHardwareWatchpointHit() slot: %u "
1374 "(addr = 0x%llx).",
1375 i, (uint64_t)wp_addr);
1376 if (wp_val == wp_addr) {
1377 #if defined(WATCHPOINTS_ARE_DWORD)
1378 uint32_t byte_mask = bits(debug_state.__wcr[i], 12, 5);
1379 #else
1380 uint32_t byte_mask = bits(debug_state.__wcr[i], 8, 5);
1381 #endif
1382
1383 // Sanity check the byte_mask, first.
1384 if (LowestBitSet(byte_mask) < 0)
1385 continue;
1386
1387 // Compute the starting address (from the point of view of the
1388 // debugger).
1389 addr = wp_addr + LowestBitSet(byte_mask);
1390 return i;
1391 }
1392 }
1393 }
1394 return INVALID_NUB_HW_INDEX;
1395 }
1396
GetWatchpointAddressByIndex(uint32_t hw_index)1397 nub_addr_t DNBArchMachARM::GetWatchpointAddressByIndex(uint32_t hw_index) {
1398 kern_return_t kret = GetDBGState(true);
1399 if (kret != KERN_SUCCESS)
1400 return INVALID_NUB_ADDRESS;
1401 const uint32_t num = NumSupportedHardwareWatchpoints();
1402 if (hw_index >= num)
1403 return INVALID_NUB_ADDRESS;
1404 if (IsWatchpointEnabled(m_state.dbg, hw_index))
1405 return GetWatchAddress(m_state.dbg, hw_index);
1406 return INVALID_NUB_ADDRESS;
1407 }
1408
IsWatchpointEnabled(const DBG & debug_state,uint32_t hw_index)1409 bool DNBArchMachARM::IsWatchpointEnabled(const DBG &debug_state,
1410 uint32_t hw_index) {
1411 // Watchpoint Control Registers, bitfield definitions
1412 // ...
1413 // Bits Value Description
1414 // [0] 0 Watchpoint disabled
1415 // 1 Watchpoint enabled.
1416 return (debug_state.__wcr[hw_index] & 1u);
1417 }
1418
GetWatchAddress(const DBG & debug_state,uint32_t hw_index)1419 nub_addr_t DNBArchMachARM::GetWatchAddress(const DBG &debug_state,
1420 uint32_t hw_index) {
1421 // Watchpoint Value Registers, bitfield definitions
1422 // Bits Description
1423 // [31:2] Watchpoint value (word address, i.e., 4-byte aligned)
1424 // [1:0] RAZ/SBZP
1425 return bits(debug_state.__wvr[hw_index], 31, 0);
1426 }
1427
1428 // Register information definitions for 32 bit ARMV7.
1429 enum gpr_regnums {
1430 gpr_r0 = 0,
1431 gpr_r1,
1432 gpr_r2,
1433 gpr_r3,
1434 gpr_r4,
1435 gpr_r5,
1436 gpr_r6,
1437 gpr_r7,
1438 gpr_r8,
1439 gpr_r9,
1440 gpr_r10,
1441 gpr_r11,
1442 gpr_r12,
1443 gpr_sp,
1444 gpr_lr,
1445 gpr_pc,
1446 gpr_cpsr
1447 };
1448
1449 enum {
1450 vfp_s0 = 0,
1451 vfp_s1,
1452 vfp_s2,
1453 vfp_s3,
1454 vfp_s4,
1455 vfp_s5,
1456 vfp_s6,
1457 vfp_s7,
1458 vfp_s8,
1459 vfp_s9,
1460 vfp_s10,
1461 vfp_s11,
1462 vfp_s12,
1463 vfp_s13,
1464 vfp_s14,
1465 vfp_s15,
1466 vfp_s16,
1467 vfp_s17,
1468 vfp_s18,
1469 vfp_s19,
1470 vfp_s20,
1471 vfp_s21,
1472 vfp_s22,
1473 vfp_s23,
1474 vfp_s24,
1475 vfp_s25,
1476 vfp_s26,
1477 vfp_s27,
1478 vfp_s28,
1479 vfp_s29,
1480 vfp_s30,
1481 vfp_s31,
1482 vfp_d0,
1483 vfp_d1,
1484 vfp_d2,
1485 vfp_d3,
1486 vfp_d4,
1487 vfp_d5,
1488 vfp_d6,
1489 vfp_d7,
1490 vfp_d8,
1491 vfp_d9,
1492 vfp_d10,
1493 vfp_d11,
1494 vfp_d12,
1495 vfp_d13,
1496 vfp_d14,
1497 vfp_d15,
1498 vfp_d16,
1499 vfp_d17,
1500 vfp_d18,
1501 vfp_d19,
1502 vfp_d20,
1503 vfp_d21,
1504 vfp_d22,
1505 vfp_d23,
1506 vfp_d24,
1507 vfp_d25,
1508 vfp_d26,
1509 vfp_d27,
1510 vfp_d28,
1511 vfp_d29,
1512 vfp_d30,
1513 vfp_d31,
1514 vfp_q0,
1515 vfp_q1,
1516 vfp_q2,
1517 vfp_q3,
1518 vfp_q4,
1519 vfp_q5,
1520 vfp_q6,
1521 vfp_q7,
1522 vfp_q8,
1523 vfp_q9,
1524 vfp_q10,
1525 vfp_q11,
1526 vfp_q12,
1527 vfp_q13,
1528 vfp_q14,
1529 vfp_q15,
1530 #if defined(__arm64__) || defined(__aarch64__)
1531 vfp_fpsr,
1532 vfp_fpcr,
1533 #else
1534 vfp_fpscr
1535 #endif
1536 };
1537
1538 enum {
1539 exc_exception,
1540 exc_fsr,
1541 exc_far,
1542 };
1543
1544 #define GPR_OFFSET_IDX(idx) (offsetof(DNBArchMachARM::GPR, __r[idx]))
1545 #define GPR_OFFSET_NAME(reg) (offsetof(DNBArchMachARM::GPR, __##reg))
1546
1547 #define EXC_OFFSET(reg) \
1548 (offsetof(DNBArchMachARM::EXC, __##reg) + \
1549 offsetof(DNBArchMachARM::Context, exc))
1550
1551 // These macros will auto define the register name, alt name, register size,
1552 // register offset, encoding, format and native register. This ensures that
1553 // the register state structures are defined correctly and have the correct
1554 // sizes and offsets.
1555 #define DEFINE_GPR_IDX(idx, reg, alt, gen) \
1556 { \
1557 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_IDX(idx), \
1558 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, NULL \
1559 }
1560 #define DEFINE_GPR_NAME(reg, alt, gen, inval) \
1561 { \
1562 e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, 4, GPR_OFFSET_NAME(reg), \
1563 ehframe_##reg, dwarf_##reg, gen, INVALID_NUB_REGNUM, NULL, inval \
1564 }
1565
1566 // In case we are debugging to a debug target that the ability to
1567 // change into the protected modes with folded registers (ABT, IRQ,
1568 // FIQ, SYS, USR, etc..), we should invalidate r8-r14 if the CPSR
1569 // gets modified.
1570
1571 const char *g_invalidate_cpsr[] = {"r8", "r9", "r10", "r11",
1572 "r12", "sp", "lr", NULL};
1573
1574 // General purpose registers
1575 const DNBRegisterInfo DNBArchMachARM::g_gpr_registers[] = {
1576 DEFINE_GPR_IDX(0, r0, "arg1", GENERIC_REGNUM_ARG1),
1577 DEFINE_GPR_IDX(1, r1, "arg2", GENERIC_REGNUM_ARG2),
1578 DEFINE_GPR_IDX(2, r2, "arg3", GENERIC_REGNUM_ARG3),
1579 DEFINE_GPR_IDX(3, r3, "arg4", GENERIC_REGNUM_ARG4),
1580 DEFINE_GPR_IDX(4, r4, NULL, INVALID_NUB_REGNUM),
1581 DEFINE_GPR_IDX(5, r5, NULL, INVALID_NUB_REGNUM),
1582 DEFINE_GPR_IDX(6, r6, NULL, INVALID_NUB_REGNUM),
1583 DEFINE_GPR_IDX(7, r7, "fp", GENERIC_REGNUM_FP),
1584 DEFINE_GPR_IDX(8, r8, NULL, INVALID_NUB_REGNUM),
1585 DEFINE_GPR_IDX(9, r9, NULL, INVALID_NUB_REGNUM),
1586 DEFINE_GPR_IDX(10, r10, NULL, INVALID_NUB_REGNUM),
1587 DEFINE_GPR_IDX(11, r11, NULL, INVALID_NUB_REGNUM),
1588 DEFINE_GPR_IDX(12, r12, NULL, INVALID_NUB_REGNUM),
1589 DEFINE_GPR_NAME(sp, "r13", GENERIC_REGNUM_SP, NULL),
1590 DEFINE_GPR_NAME(lr, "r14", GENERIC_REGNUM_RA, NULL),
1591 DEFINE_GPR_NAME(pc, "r15", GENERIC_REGNUM_PC, NULL),
1592 DEFINE_GPR_NAME(cpsr, "flags", GENERIC_REGNUM_FLAGS, g_invalidate_cpsr)};
1593
1594 const char *g_contained_q0[]{"q0", NULL};
1595 const char *g_contained_q1[]{"q1", NULL};
1596 const char *g_contained_q2[]{"q2", NULL};
1597 const char *g_contained_q3[]{"q3", NULL};
1598 const char *g_contained_q4[]{"q4", NULL};
1599 const char *g_contained_q5[]{"q5", NULL};
1600 const char *g_contained_q6[]{"q6", NULL};
1601 const char *g_contained_q7[]{"q7", NULL};
1602 const char *g_contained_q8[]{"q8", NULL};
1603 const char *g_contained_q9[]{"q9", NULL};
1604 const char *g_contained_q10[]{"q10", NULL};
1605 const char *g_contained_q11[]{"q11", NULL};
1606 const char *g_contained_q12[]{"q12", NULL};
1607 const char *g_contained_q13[]{"q13", NULL};
1608 const char *g_contained_q14[]{"q14", NULL};
1609 const char *g_contained_q15[]{"q15", NULL};
1610
1611 const char *g_invalidate_q0[]{"q0", "d0", "d1", "s0", "s1", "s2", "s3", NULL};
1612 const char *g_invalidate_q1[]{"q1", "d2", "d3", "s4", "s5", "s6", "s7", NULL};
1613 const char *g_invalidate_q2[]{"q2", "d4", "d5", "s8", "s9", "s10", "s11", NULL};
1614 const char *g_invalidate_q3[]{"q3", "d6", "d7", "s12",
1615 "s13", "s14", "s15", NULL};
1616 const char *g_invalidate_q4[]{"q4", "d8", "d9", "s16",
1617 "s17", "s18", "s19", NULL};
1618 const char *g_invalidate_q5[]{"q5", "d10", "d11", "s20",
1619 "s21", "s22", "s23", NULL};
1620 const char *g_invalidate_q6[]{"q6", "d12", "d13", "s24",
1621 "s25", "s26", "s27", NULL};
1622 const char *g_invalidate_q7[]{"q7", "d14", "d15", "s28",
1623 "s29", "s30", "s31", NULL};
1624 const char *g_invalidate_q8[]{"q8", "d16", "d17", NULL};
1625 const char *g_invalidate_q9[]{"q9", "d18", "d19", NULL};
1626 const char *g_invalidate_q10[]{"q10", "d20", "d21", NULL};
1627 const char *g_invalidate_q11[]{"q11", "d22", "d23", NULL};
1628 const char *g_invalidate_q12[]{"q12", "d24", "d25", NULL};
1629 const char *g_invalidate_q13[]{"q13", "d26", "d27", NULL};
1630 const char *g_invalidate_q14[]{"q14", "d28", "d29", NULL};
1631 const char *g_invalidate_q15[]{"q15", "d30", "d31", NULL};
1632
1633 #define VFP_S_OFFSET_IDX(idx) \
1634 (((idx) % 4) * 4) // offset into q reg: 0, 4, 8, 12
1635 #define VFP_D_OFFSET_IDX(idx) (((idx) % 2) * 8) // offset into q reg: 0, 8
1636 #define VFP_Q_OFFSET_IDX(idx) (VFP_S_OFFSET_IDX((idx)*4))
1637
1638 #define VFP_OFFSET_NAME(reg) \
1639 (offsetof(DNBArchMachARM::FPU, __##reg) + \
1640 offsetof(DNBArchMachARM::Context, vfp))
1641
1642 #define FLOAT_FORMAT Float
1643
1644 #define DEFINE_VFP_S_IDX(idx) \
1645 e_regSetVFP, vfp_s##idx, "s" #idx, NULL, IEEE754, FLOAT_FORMAT, 4, \
1646 VFP_S_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_s##idx, \
1647 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1648 #define DEFINE_VFP_D_IDX(idx) \
1649 e_regSetVFP, vfp_d##idx, "d" #idx, NULL, IEEE754, FLOAT_FORMAT, 8, \
1650 VFP_D_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_d##idx, \
1651 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1652 #define DEFINE_VFP_Q_IDX(idx) \
1653 e_regSetVFP, vfp_q##idx, "q" #idx, NULL, Vector, VectorOfUInt8, 16, \
1654 VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, \
1655 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1656
1657 // Floating point registers
1658 const DNBRegisterInfo DNBArchMachARM::g_vfp_registers[] = {
1659 {DEFINE_VFP_S_IDX(0), g_contained_q0, g_invalidate_q0},
1660 {DEFINE_VFP_S_IDX(1), g_contained_q0, g_invalidate_q0},
1661 {DEFINE_VFP_S_IDX(2), g_contained_q0, g_invalidate_q0},
1662 {DEFINE_VFP_S_IDX(3), g_contained_q0, g_invalidate_q0},
1663 {DEFINE_VFP_S_IDX(4), g_contained_q1, g_invalidate_q1},
1664 {DEFINE_VFP_S_IDX(5), g_contained_q1, g_invalidate_q1},
1665 {DEFINE_VFP_S_IDX(6), g_contained_q1, g_invalidate_q1},
1666 {DEFINE_VFP_S_IDX(7), g_contained_q1, g_invalidate_q1},
1667 {DEFINE_VFP_S_IDX(8), g_contained_q2, g_invalidate_q2},
1668 {DEFINE_VFP_S_IDX(9), g_contained_q2, g_invalidate_q2},
1669 {DEFINE_VFP_S_IDX(10), g_contained_q2, g_invalidate_q2},
1670 {DEFINE_VFP_S_IDX(11), g_contained_q2, g_invalidate_q2},
1671 {DEFINE_VFP_S_IDX(12), g_contained_q3, g_invalidate_q3},
1672 {DEFINE_VFP_S_IDX(13), g_contained_q3, g_invalidate_q3},
1673 {DEFINE_VFP_S_IDX(14), g_contained_q3, g_invalidate_q3},
1674 {DEFINE_VFP_S_IDX(15), g_contained_q3, g_invalidate_q3},
1675 {DEFINE_VFP_S_IDX(16), g_contained_q4, g_invalidate_q4},
1676 {DEFINE_VFP_S_IDX(17), g_contained_q4, g_invalidate_q4},
1677 {DEFINE_VFP_S_IDX(18), g_contained_q4, g_invalidate_q4},
1678 {DEFINE_VFP_S_IDX(19), g_contained_q4, g_invalidate_q4},
1679 {DEFINE_VFP_S_IDX(20), g_contained_q5, g_invalidate_q5},
1680 {DEFINE_VFP_S_IDX(21), g_contained_q5, g_invalidate_q5},
1681 {DEFINE_VFP_S_IDX(22), g_contained_q5, g_invalidate_q5},
1682 {DEFINE_VFP_S_IDX(23), g_contained_q5, g_invalidate_q5},
1683 {DEFINE_VFP_S_IDX(24), g_contained_q6, g_invalidate_q6},
1684 {DEFINE_VFP_S_IDX(25), g_contained_q6, g_invalidate_q6},
1685 {DEFINE_VFP_S_IDX(26), g_contained_q6, g_invalidate_q6},
1686 {DEFINE_VFP_S_IDX(27), g_contained_q6, g_invalidate_q6},
1687 {DEFINE_VFP_S_IDX(28), g_contained_q7, g_invalidate_q7},
1688 {DEFINE_VFP_S_IDX(29), g_contained_q7, g_invalidate_q7},
1689 {DEFINE_VFP_S_IDX(30), g_contained_q7, g_invalidate_q7},
1690 {DEFINE_VFP_S_IDX(31), g_contained_q7, g_invalidate_q7},
1691
1692 {DEFINE_VFP_D_IDX(0), g_contained_q0, g_invalidate_q0},
1693 {DEFINE_VFP_D_IDX(1), g_contained_q0, g_invalidate_q0},
1694 {DEFINE_VFP_D_IDX(2), g_contained_q1, g_invalidate_q1},
1695 {DEFINE_VFP_D_IDX(3), g_contained_q1, g_invalidate_q1},
1696 {DEFINE_VFP_D_IDX(4), g_contained_q2, g_invalidate_q2},
1697 {DEFINE_VFP_D_IDX(5), g_contained_q2, g_invalidate_q2},
1698 {DEFINE_VFP_D_IDX(6), g_contained_q3, g_invalidate_q3},
1699 {DEFINE_VFP_D_IDX(7), g_contained_q3, g_invalidate_q3},
1700 {DEFINE_VFP_D_IDX(8), g_contained_q4, g_invalidate_q4},
1701 {DEFINE_VFP_D_IDX(9), g_contained_q4, g_invalidate_q4},
1702 {DEFINE_VFP_D_IDX(10), g_contained_q5, g_invalidate_q5},
1703 {DEFINE_VFP_D_IDX(11), g_contained_q5, g_invalidate_q5},
1704 {DEFINE_VFP_D_IDX(12), g_contained_q6, g_invalidate_q6},
1705 {DEFINE_VFP_D_IDX(13), g_contained_q6, g_invalidate_q6},
1706 {DEFINE_VFP_D_IDX(14), g_contained_q7, g_invalidate_q7},
1707 {DEFINE_VFP_D_IDX(15), g_contained_q7, g_invalidate_q7},
1708 {DEFINE_VFP_D_IDX(16), g_contained_q8, g_invalidate_q8},
1709 {DEFINE_VFP_D_IDX(17), g_contained_q8, g_invalidate_q8},
1710 {DEFINE_VFP_D_IDX(18), g_contained_q9, g_invalidate_q9},
1711 {DEFINE_VFP_D_IDX(19), g_contained_q9, g_invalidate_q9},
1712 {DEFINE_VFP_D_IDX(20), g_contained_q10, g_invalidate_q10},
1713 {DEFINE_VFP_D_IDX(21), g_contained_q10, g_invalidate_q10},
1714 {DEFINE_VFP_D_IDX(22), g_contained_q11, g_invalidate_q11},
1715 {DEFINE_VFP_D_IDX(23), g_contained_q11, g_invalidate_q11},
1716 {DEFINE_VFP_D_IDX(24), g_contained_q12, g_invalidate_q12},
1717 {DEFINE_VFP_D_IDX(25), g_contained_q12, g_invalidate_q12},
1718 {DEFINE_VFP_D_IDX(26), g_contained_q13, g_invalidate_q13},
1719 {DEFINE_VFP_D_IDX(27), g_contained_q13, g_invalidate_q13},
1720 {DEFINE_VFP_D_IDX(28), g_contained_q14, g_invalidate_q14},
1721 {DEFINE_VFP_D_IDX(29), g_contained_q14, g_invalidate_q14},
1722 {DEFINE_VFP_D_IDX(30), g_contained_q15, g_invalidate_q15},
1723 {DEFINE_VFP_D_IDX(31), g_contained_q15, g_invalidate_q15},
1724
1725 {DEFINE_VFP_Q_IDX(0), NULL, g_invalidate_q0},
1726 {DEFINE_VFP_Q_IDX(1), NULL, g_invalidate_q1},
1727 {DEFINE_VFP_Q_IDX(2), NULL, g_invalidate_q2},
1728 {DEFINE_VFP_Q_IDX(3), NULL, g_invalidate_q3},
1729 {DEFINE_VFP_Q_IDX(4), NULL, g_invalidate_q4},
1730 {DEFINE_VFP_Q_IDX(5), NULL, g_invalidate_q5},
1731 {DEFINE_VFP_Q_IDX(6), NULL, g_invalidate_q6},
1732 {DEFINE_VFP_Q_IDX(7), NULL, g_invalidate_q7},
1733 {DEFINE_VFP_Q_IDX(8), NULL, g_invalidate_q8},
1734 {DEFINE_VFP_Q_IDX(9), NULL, g_invalidate_q9},
1735 {DEFINE_VFP_Q_IDX(10), NULL, g_invalidate_q10},
1736 {DEFINE_VFP_Q_IDX(11), NULL, g_invalidate_q11},
1737 {DEFINE_VFP_Q_IDX(12), NULL, g_invalidate_q12},
1738 {DEFINE_VFP_Q_IDX(13), NULL, g_invalidate_q13},
1739 {DEFINE_VFP_Q_IDX(14), NULL, g_invalidate_q14},
1740 {DEFINE_VFP_Q_IDX(15), NULL, g_invalidate_q15},
1741
1742 #if defined(__arm64__) || defined(__aarch64__)
1743 {e_regSetVFP, vfp_fpsr, "fpsr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpsr),
1744 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1745 INVALID_NUB_REGNUM, NULL, NULL},
1746 {e_regSetVFP, vfp_fpcr, "fpcr", NULL, Uint, Hex, 4, VFP_OFFSET_NAME(fpcr),
1747 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1748 INVALID_NUB_REGNUM, NULL, NULL}
1749 #else
1750 {e_regSetVFP, vfp_fpscr, "fpscr", NULL, Uint, Hex, 4,
1751 VFP_OFFSET_NAME(fpscr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1752 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL}
1753 #endif
1754 };
1755
1756 // Exception registers
1757
1758 const DNBRegisterInfo DNBArchMachARM::g_exc_registers[] = {
1759 {e_regSetVFP, exc_exception, "exception", NULL, Uint, Hex, 4,
1760 EXC_OFFSET(exception), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1761 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM},
1762 {e_regSetVFP, exc_fsr, "fsr", NULL, Uint, Hex, 4, EXC_OFFSET(fsr),
1763 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1764 INVALID_NUB_REGNUM},
1765 {e_regSetVFP, exc_far, "far", NULL, Uint, Hex, 4, EXC_OFFSET(far),
1766 INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
1767 INVALID_NUB_REGNUM}};
1768
1769 // Number of registers in each register set
1770 const size_t DNBArchMachARM::k_num_gpr_registers =
1771 sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
1772 const size_t DNBArchMachARM::k_num_vfp_registers =
1773 sizeof(g_vfp_registers) / sizeof(DNBRegisterInfo);
1774 const size_t DNBArchMachARM::k_num_exc_registers =
1775 sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
1776 const size_t DNBArchMachARM::k_num_all_registers =
1777 k_num_gpr_registers + k_num_vfp_registers + k_num_exc_registers;
1778
1779 // Register set definitions. The first definitions at register set index
1780 // of zero is for all registers, followed by other registers sets. The
1781 // register information for the all register set need not be filled in.
1782 const DNBRegisterSetInfo DNBArchMachARM::g_reg_sets[] = {
1783 {"ARM Registers", NULL, k_num_all_registers},
1784 {"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
1785 {"Floating Point Registers", g_vfp_registers, k_num_vfp_registers},
1786 {"Exception State Registers", g_exc_registers, k_num_exc_registers}};
1787 // Total number of register sets for this architecture
1788 const size_t DNBArchMachARM::k_num_register_sets =
1789 sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
1790
1791 const DNBRegisterSetInfo *
GetRegisterSetInfo(nub_size_t * num_reg_sets)1792 DNBArchMachARM::GetRegisterSetInfo(nub_size_t *num_reg_sets) {
1793 *num_reg_sets = k_num_register_sets;
1794 return g_reg_sets;
1795 }
1796
GetRegisterValue(uint32_t set,uint32_t reg,DNBRegisterValue * value)1797 bool DNBArchMachARM::GetRegisterValue(uint32_t set, uint32_t reg,
1798 DNBRegisterValue *value) {
1799 if (set == REGISTER_SET_GENERIC) {
1800 switch (reg) {
1801 case GENERIC_REGNUM_PC: // Program Counter
1802 set = e_regSetGPR;
1803 reg = gpr_pc;
1804 break;
1805
1806 case GENERIC_REGNUM_SP: // Stack Pointer
1807 set = e_regSetGPR;
1808 reg = gpr_sp;
1809 break;
1810
1811 case GENERIC_REGNUM_FP: // Frame Pointer
1812 set = e_regSetGPR;
1813 reg = gpr_r7; // is this the right reg?
1814 break;
1815
1816 case GENERIC_REGNUM_RA: // Return Address
1817 set = e_regSetGPR;
1818 reg = gpr_lr;
1819 break;
1820
1821 case GENERIC_REGNUM_FLAGS: // Processor flags register
1822 set = e_regSetGPR;
1823 reg = gpr_cpsr;
1824 break;
1825
1826 default:
1827 return false;
1828 }
1829 }
1830
1831 if (GetRegisterState(set, false) != KERN_SUCCESS)
1832 return false;
1833
1834 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
1835 if (regInfo) {
1836 value->info = *regInfo;
1837 switch (set) {
1838 case e_regSetGPR:
1839 if (reg < k_num_gpr_registers) {
1840 value->value.uint32 = m_state.context.gpr.__r[reg];
1841 return true;
1842 }
1843 break;
1844
1845 case e_regSetVFP:
1846 // "reg" is an index into the floating point register set at this point.
1847 // We need to translate it up so entry 0 in the fp reg set is the same as
1848 // vfp_s0
1849 // in the enumerated values for case statement below.
1850 if (reg >= vfp_s0 && reg <= vfp_s31) {
1851 #if defined(__arm64__) || defined(__aarch64__)
1852 uint32_t *s_reg =
1853 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
1854 memcpy(&value->value.v_uint8, s_reg, 4);
1855 #else
1856 value->value.uint32 = m_state.context.vfp.__r[reg];
1857 #endif
1858 return true;
1859 } else if (reg >= vfp_d0 && reg <= vfp_d31) {
1860 #if defined(__arm64__) || defined(__aarch64__)
1861 uint64_t *d_reg =
1862 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
1863 memcpy(&value->value.v_uint8, d_reg, 8);
1864 #else
1865 uint32_t d_reg_idx = reg - vfp_d0;
1866 uint32_t s_reg_idx = d_reg_idx * 2;
1867 value->value.v_sint32[0] = m_state.context.vfp.__r[s_reg_idx + 0];
1868 value->value.v_sint32[1] = m_state.context.vfp.__r[s_reg_idx + 1];
1869 #endif
1870 return true;
1871 } else if (reg >= vfp_q0 && reg <= vfp_q15) {
1872 #if defined(__arm64__) || defined(__aarch64__)
1873 memcpy(&value->value.v_uint8,
1874 (uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0], 16);
1875 #else
1876 uint32_t s_reg_idx = (reg - vfp_q0) * 4;
1877 memcpy(&value->value.v_uint8,
1878 (uint8_t *)&m_state.context.vfp.__r[s_reg_idx], 16);
1879 #endif
1880 return true;
1881 }
1882 #if defined(__arm64__) || defined(__aarch64__)
1883 else if (reg == vfp_fpsr) {
1884 value->value.uint32 = m_state.context.vfp.__fpsr;
1885 return true;
1886 } else if (reg == vfp_fpcr) {
1887 value->value.uint32 = m_state.context.vfp.__fpcr;
1888 return true;
1889 }
1890 #else
1891 else if (reg == vfp_fpscr) {
1892 value->value.uint32 = m_state.context.vfp.__fpscr;
1893 return true;
1894 }
1895 #endif
1896 break;
1897
1898 case e_regSetEXC:
1899 if (reg < k_num_exc_registers) {
1900 value->value.uint32 = (&m_state.context.exc.__exception)[reg];
1901 return true;
1902 }
1903 break;
1904 }
1905 }
1906 return false;
1907 }
1908
SetRegisterValue(uint32_t set,uint32_t reg,const DNBRegisterValue * value)1909 bool DNBArchMachARM::SetRegisterValue(uint32_t set, uint32_t reg,
1910 const DNBRegisterValue *value) {
1911 if (set == REGISTER_SET_GENERIC) {
1912 switch (reg) {
1913 case GENERIC_REGNUM_PC: // Program Counter
1914 set = e_regSetGPR;
1915 reg = gpr_pc;
1916 break;
1917
1918 case GENERIC_REGNUM_SP: // Stack Pointer
1919 set = e_regSetGPR;
1920 reg = gpr_sp;
1921 break;
1922
1923 case GENERIC_REGNUM_FP: // Frame Pointer
1924 set = e_regSetGPR;
1925 reg = gpr_r7;
1926 break;
1927
1928 case GENERIC_REGNUM_RA: // Return Address
1929 set = e_regSetGPR;
1930 reg = gpr_lr;
1931 break;
1932
1933 case GENERIC_REGNUM_FLAGS: // Processor flags register
1934 set = e_regSetGPR;
1935 reg = gpr_cpsr;
1936 break;
1937
1938 default:
1939 return false;
1940 }
1941 }
1942
1943 if (GetRegisterState(set, false) != KERN_SUCCESS)
1944 return false;
1945
1946 bool success = false;
1947 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
1948 if (regInfo) {
1949 switch (set) {
1950 case e_regSetGPR:
1951 if (reg < k_num_gpr_registers) {
1952 m_state.context.gpr.__r[reg] = value->value.uint32;
1953 success = true;
1954 }
1955 break;
1956
1957 case e_regSetVFP:
1958 // "reg" is an index into the floating point register set at this point.
1959 // We need to translate it up so entry 0 in the fp reg set is the same as
1960 // vfp_s0
1961 // in the enumerated values for case statement below.
1962 if (reg >= vfp_s0 && reg <= vfp_s31) {
1963 #if defined(__arm64__) || defined(__aarch64__)
1964 uint32_t *s_reg =
1965 ((uint32_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_s0);
1966 memcpy(s_reg, &value->value.v_uint8, 4);
1967 #else
1968 m_state.context.vfp.__r[reg] = value->value.uint32;
1969 #endif
1970 success = true;
1971 } else if (reg >= vfp_d0 && reg <= vfp_d31) {
1972 #if defined(__arm64__) || defined(__aarch64__)
1973 uint64_t *d_reg =
1974 ((uint64_t *)&m_state.context.vfp.__v[0]) + (reg - vfp_d0);
1975 memcpy(d_reg, &value->value.v_uint8, 8);
1976 #else
1977 uint32_t d_reg_idx = reg - vfp_d0;
1978 uint32_t s_reg_idx = d_reg_idx * 2;
1979 m_state.context.vfp.__r[s_reg_idx + 0] = value->value.v_sint32[0];
1980 m_state.context.vfp.__r[s_reg_idx + 1] = value->value.v_sint32[1];
1981 #endif
1982 success = true;
1983 } else if (reg >= vfp_q0 && reg <= vfp_q15) {
1984 #if defined(__arm64__) || defined(__aarch64__)
1985 memcpy((uint8_t *)&m_state.context.vfp.__v[reg - vfp_q0],
1986 &value->value.v_uint8, 16);
1987 #else
1988 uint32_t s_reg_idx = (reg - vfp_q0) * 4;
1989 memcpy((uint8_t *)&m_state.context.vfp.__r[s_reg_idx],
1990 &value->value.v_uint8, 16);
1991 #endif
1992 success = true;
1993 }
1994 #if defined(__arm64__) || defined(__aarch64__)
1995 else if (reg == vfp_fpsr) {
1996 m_state.context.vfp.__fpsr = value->value.uint32;
1997 success = true;
1998 } else if (reg == vfp_fpcr) {
1999 m_state.context.vfp.__fpcr = value->value.uint32;
2000 success = true;
2001 }
2002 #else
2003 else if (reg == vfp_fpscr) {
2004 m_state.context.vfp.__fpscr = value->value.uint32;
2005 success = true;
2006 }
2007 #endif
2008 break;
2009
2010 case e_regSetEXC:
2011 if (reg < k_num_exc_registers) {
2012 (&m_state.context.exc.__exception)[reg] = value->value.uint32;
2013 success = true;
2014 }
2015 break;
2016 }
2017 }
2018 if (success)
2019 return SetRegisterState(set) == KERN_SUCCESS;
2020 return false;
2021 }
2022
GetRegisterState(int set,bool force)2023 kern_return_t DNBArchMachARM::GetRegisterState(int set, bool force) {
2024 switch (set) {
2025 case e_regSetALL:
2026 return GetGPRState(force) | GetVFPState(force) | GetEXCState(force) |
2027 GetDBGState(force);
2028 case e_regSetGPR:
2029 return GetGPRState(force);
2030 case e_regSetVFP:
2031 return GetVFPState(force);
2032 case e_regSetEXC:
2033 return GetEXCState(force);
2034 case e_regSetDBG:
2035 return GetDBGState(force);
2036 default:
2037 break;
2038 }
2039 return KERN_INVALID_ARGUMENT;
2040 }
2041
SetRegisterState(int set)2042 kern_return_t DNBArchMachARM::SetRegisterState(int set) {
2043 // Make sure we have a valid context to set.
2044 kern_return_t err = GetRegisterState(set, false);
2045 if (err != KERN_SUCCESS)
2046 return err;
2047
2048 switch (set) {
2049 case e_regSetALL:
2050 return SetGPRState() | SetVFPState() | SetEXCState() | SetDBGState(false);
2051 case e_regSetGPR:
2052 return SetGPRState();
2053 case e_regSetVFP:
2054 return SetVFPState();
2055 case e_regSetEXC:
2056 return SetEXCState();
2057 case e_regSetDBG:
2058 return SetDBGState(false);
2059 default:
2060 break;
2061 }
2062 return KERN_INVALID_ARGUMENT;
2063 }
2064
RegisterSetStateIsValid(int set) const2065 bool DNBArchMachARM::RegisterSetStateIsValid(int set) const {
2066 return m_state.RegsAreValid(set);
2067 }
2068
GetRegisterContext(void * buf,nub_size_t buf_len)2069 nub_size_t DNBArchMachARM::GetRegisterContext(void *buf, nub_size_t buf_len) {
2070 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
2071 sizeof(m_state.context.exc);
2072
2073 if (buf && buf_len) {
2074 if (size > buf_len)
2075 size = buf_len;
2076
2077 bool force = false;
2078 if (GetGPRState(force) | GetVFPState(force) | GetEXCState(force))
2079 return 0;
2080
2081 // Copy each struct individually to avoid any padding that might be between
2082 // the structs in m_state.context
2083 uint8_t *p = (uint8_t *)buf;
2084 ::memcpy(p, &m_state.context.gpr, sizeof(m_state.context.gpr));
2085 p += sizeof(m_state.context.gpr);
2086 ::memcpy(p, &m_state.context.vfp, sizeof(m_state.context.vfp));
2087 p += sizeof(m_state.context.vfp);
2088 ::memcpy(p, &m_state.context.exc, sizeof(m_state.context.exc));
2089 p += sizeof(m_state.context.exc);
2090
2091 size_t bytes_written = p - (uint8_t *)buf;
2092 UNUSED_IF_ASSERT_DISABLED(bytes_written);
2093 assert(bytes_written == size);
2094 }
2095 DNBLogThreadedIf(
2096 LOG_THREAD,
2097 "DNBArchMachARM::GetRegisterContext (buf = %p, len = %llu) => %llu", buf,
2098 (uint64_t)buf_len, (uint64_t)size);
2099 // Return the size of the register context even if NULL was passed in
2100 return size;
2101 }
2102
SetRegisterContext(const void * buf,nub_size_t buf_len)2103 nub_size_t DNBArchMachARM::SetRegisterContext(const void *buf,
2104 nub_size_t buf_len) {
2105 nub_size_t size = sizeof(m_state.context.gpr) + sizeof(m_state.context.vfp) +
2106 sizeof(m_state.context.exc);
2107
2108 if (buf == NULL || buf_len == 0)
2109 size = 0;
2110
2111 if (size) {
2112 if (size > buf_len)
2113 size = buf_len;
2114
2115 // Copy each struct individually to avoid any padding that might be between
2116 // the structs in m_state.context
2117 uint8_t *p = (uint8_t *)buf;
2118 ::memcpy(&m_state.context.gpr, p, sizeof(m_state.context.gpr));
2119 p += sizeof(m_state.context.gpr);
2120 ::memcpy(&m_state.context.vfp, p, sizeof(m_state.context.vfp));
2121 p += sizeof(m_state.context.vfp);
2122 ::memcpy(&m_state.context.exc, p, sizeof(m_state.context.exc));
2123 p += sizeof(m_state.context.exc);
2124
2125 size_t bytes_written = p - (uint8_t *)buf;
2126 UNUSED_IF_ASSERT_DISABLED(bytes_written);
2127 assert(bytes_written == size);
2128
2129 if (SetGPRState() | SetVFPState() | SetEXCState())
2130 return 0;
2131 }
2132 DNBLogThreadedIf(
2133 LOG_THREAD,
2134 "DNBArchMachARM::SetRegisterContext (buf = %p, len = %llu) => %llu", buf,
2135 (uint64_t)buf_len, (uint64_t)size);
2136 return size;
2137 }
2138
SaveRegisterState()2139 uint32_t DNBArchMachARM::SaveRegisterState() {
2140 kern_return_t kret = ::thread_abort_safely(m_thread->MachPortNumber());
2141 DNBLogThreadedIf(
2142 LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u "
2143 "(SetGPRState() for stop_count = %u)",
2144 m_thread->MachPortNumber(), kret, m_thread->Process()->StopCount());
2145
2146 // Always re-read the registers because above we call thread_abort_safely();
2147 bool force = true;
2148
2149 if ((kret = GetGPRState(force)) != KERN_SUCCESS) {
2150 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
2151 "GPR regs failed to read: %u ",
2152 kret);
2153 } else if ((kret = GetVFPState(force)) != KERN_SUCCESS) {
2154 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::SaveRegisterState () error: "
2155 "%s regs failed to read: %u",
2156 "VFP", kret);
2157 } else {
2158 const uint32_t save_id = GetNextRegisterStateSaveID();
2159 m_saved_register_states[save_id] = m_state.context;
2160 return save_id;
2161 }
2162 return UINT32_MAX;
2163 }
2164
RestoreRegisterState(uint32_t save_id)2165 bool DNBArchMachARM::RestoreRegisterState(uint32_t save_id) {
2166 SaveRegisterStates::iterator pos = m_saved_register_states.find(save_id);
2167 if (pos != m_saved_register_states.end()) {
2168 m_state.context.gpr = pos->second.gpr;
2169 m_state.context.vfp = pos->second.vfp;
2170 kern_return_t kret;
2171 bool success = true;
2172 if ((kret = SetGPRState()) != KERN_SUCCESS) {
2173 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
2174 "(save_id = %u) error: GPR regs failed to "
2175 "write: %u",
2176 save_id, kret);
2177 success = false;
2178 } else if ((kret = SetVFPState()) != KERN_SUCCESS) {
2179 DNBLogThreadedIf(LOG_THREAD, "DNBArchMachARM::RestoreRegisterState "
2180 "(save_id = %u) error: %s regs failed to "
2181 "write: %u",
2182 save_id, "VFP", kret);
2183 success = false;
2184 }
2185 m_saved_register_states.erase(pos);
2186 return success;
2187 }
2188 return false;
2189 }
2190
2191 #endif // #if defined (__arm__)
2192