1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13
14 /* Capstone Disassembly Engine */
15 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17 #ifdef CAPSTONE_HAS_MIPS
18
19 #include <stdio.h>
20 #include <string.h>
21
22 #include "capstone/platform.h"
23
24 #include "MipsDisassembler.h"
25
26 #include "../../utils.h"
27
28 #include "../../MCRegisterInfo.h"
29 #include "../../SStream.h"
30
31 #include "../../MathExtras.h"
32
33 //#include "Mips.h"
34 //#include "MipsRegisterInfo.h"
35 //#include "MipsSubtarget.h"
36 #include "../../MCFixedLenDisassembler.h"
37 #include "../../MCInst.h"
38 //#include "llvm/MC/MCSubtargetInfo.h"
39 #include "../../MCRegisterInfo.h"
40 #include "../../MCDisassembler.h"
41
42 // Forward declare these because the autogenerated code will reference them.
43 // Definitions are further down.
44 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
45 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
46
47 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
48 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
49
50 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
51 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
52
53 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
54 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
55
56 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
57 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
58
59 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
60 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
61
62 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
63 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
64
65 static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
66 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
67
68 static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
69 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
70
71 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
72 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
73
74 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
75 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
76
77 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
78 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
79
80 static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
81 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
82
83 static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
84 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
85
86 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
87 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
88
89 static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
90 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
91
92 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
93 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
94
95 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
96 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
97
98 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
99 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
100
101 static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
102 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
103
104 static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
105 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
106
107 static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
108 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
109
110 static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
111 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
112
113 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
114 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
115
116 static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
117 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
118
119 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
120 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
121
122 static DecodeStatus DecodeJumpTarget(MCInst *Inst,
123 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
124
125 static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
126 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
127
128 static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
129 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
130
131 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
132 // shifted left by 1 bit.
133 static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
134 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
135
136 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
137 // shifted left by 1 bit.
138 static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
139 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
140
141 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
142 // shifted left by 1 bit.
143 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
144 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
145
146 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
147 // shifted left by 1 bit.
148 static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
149 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
150
151 static DecodeStatus DecodeMem(MCInst *Inst,
152 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
153
154 static DecodeStatus DecodeCacheOp(MCInst *Inst,
155 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
156
157 static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
158 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
159
160 static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
161 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
162
163 static DecodeStatus DecodeSyncI(MCInst *Inst,
164 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
165
166 static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
167 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
168
169 static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
170 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
171
172 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
173 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
174
175 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
176 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
177
178 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
179 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
180
181 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
182 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
183
184 static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
185 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
186
187 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
188 uint64_t Address, const MCRegisterInfo *Decoder);
189
190 static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
191 uint64_t Address, MCRegisterInfo *Decoder);
192
193 static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn,
194 uint64_t Address, MCRegisterInfo *Decoder);
195
196 static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn,
197 uint64_t Address, MCRegisterInfo *Decoder);
198
199 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
200 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
201
202 static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
203 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
204
205 static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
206 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
207
208 static DecodeStatus DecodeLiSimm7(MCInst *Inst,
209 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
210
211 static DecodeStatus DecodeSimm4(MCInst *Inst,
212 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
213
214 static DecodeStatus DecodeSimm16(MCInst *Inst,
215 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
216
217 // Decode the immediate field of an LSA instruction which
218 // is off by one.
219 static DecodeStatus DecodeLSAImm(MCInst *Inst,
220 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
221
222 static DecodeStatus DecodeInsSize(MCInst *Inst,
223 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
224
225 static DecodeStatus DecodeExtSize(MCInst *Inst,
226 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
227
228 static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
229 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
230
231 static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
232 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
233
234 static DecodeStatus DecodeSimm9SP(MCInst *Inst,
235 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
236
237 static DecodeStatus DecodeANDI16Imm(MCInst *Inst,
238 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
239
240 static DecodeStatus DecodeUImm5lsl2(MCInst *Inst,
241 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
242
243 static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst,
244 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
245
246 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
247 /// handle.
248 static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
249 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
250
251 static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
252 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
253
254 static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
255 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
256
257 static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
258 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
259
260 static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
261 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
262
263 static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
264 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
265
266 static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
267 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
268
269 static DecodeStatus DecodeRegListOperand(MCInst *Inst,
270 uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
271
272 static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
273 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
274
275 static DecodeStatus DecodeMovePRegPair(MCInst *Inst,
276 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
277
278 #define GET_SUBTARGETINFO_ENUM
279 #include "MipsGenSubtargetInfo.inc"
280
281 // Hacky: enable all features for disassembler
getFeatureBits(int mode)282 static uint64_t getFeatureBits(int mode)
283 {
284 uint64_t Bits = (uint64_t)-1; // include every features at first
285
286 // By default we do not support Mips1
287 Bits &= ~Mips_FeatureMips1;
288
289 // No MicroMips
290 Bits &= ~Mips_FeatureMicroMips;
291
292 // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
293 // some features are mutually execlusive
294 if (mode & CS_MODE_16) {
295 //Bits &= ~Mips_FeatureMips32r2;
296 //Bits &= ~Mips_FeatureMips32;
297 //Bits &= ~Mips_FeatureFPIdx;
298 //Bits &= ~Mips_FeatureBitCount;
299 //Bits &= ~Mips_FeatureSwap;
300 //Bits &= ~Mips_FeatureSEInReg;
301 //Bits &= ~Mips_FeatureMips64r2;
302 //Bits &= ~Mips_FeatureFP64Bit;
303 } else if (mode & CS_MODE_32) {
304 Bits &= ~Mips_FeatureMips16;
305 Bits &= ~Mips_FeatureFP64Bit;
306 Bits &= ~Mips_FeatureMips64r2;
307 Bits &= ~Mips_FeatureMips32r6;
308 Bits &= ~Mips_FeatureMips64r6;
309 } else if (mode & CS_MODE_64) {
310 Bits &= ~Mips_FeatureMips16;
311 Bits &= ~Mips_FeatureMips64r6;
312 Bits &= ~Mips_FeatureMips32r6;
313 } else if (mode & CS_MODE_MIPS32R6) {
314 Bits |= Mips_FeatureMips32r6;
315 Bits &= ~Mips_FeatureMips16;
316 Bits &= ~Mips_FeatureFP64Bit;
317 Bits &= ~Mips_FeatureMips64r6;
318 Bits &= ~Mips_FeatureMips64r2;
319 }
320
321 if (mode & CS_MODE_MICRO) {
322 Bits |= Mips_FeatureMicroMips;
323 Bits &= ~Mips_FeatureMips4_32r2;
324 Bits &= ~Mips_FeatureMips2;
325 }
326
327 return Bits;
328 }
329
330 #include "MipsGenDisassemblerTables.inc"
331
332 #define GET_REGINFO_ENUM
333 #include "MipsGenRegisterInfo.inc"
334
335 #define GET_REGINFO_MC_DESC
336 #include "MipsGenRegisterInfo.inc"
337
338 #define GET_INSTRINFO_ENUM
339 #include "MipsGenInstrInfo.inc"
340
Mips_init(MCRegisterInfo * MRI)341 void Mips_init(MCRegisterInfo *MRI)
342 {
343 // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
344 // MipsMCRegisterClasses, 62,
345 // MipsRegUnitRoots,
346 // 273,
347 // MipsRegDiffLists,
348 // MipsLaneMaskLists,
349 // MipsRegStrings,
350 // MipsRegClassStrings,
351 // MipsSubRegIdxLists,
352 // 12,
353 // MipsSubRegIdxRanges,
354 // MipsRegEncodingTable);
355
356
357 MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
358 0, 0,
359 MipsMCRegisterClasses, 62,
360 0, 0,
361 MipsRegDiffLists,
362 0,
363 MipsSubRegIdxLists, 12,
364 0);
365 }
366
367 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
368 /// according to the given endianess.
readInstruction16(unsigned char * code,uint32_t * insn,bool isBigEndian)369 static void readInstruction16(unsigned char *code, uint32_t *insn,
370 bool isBigEndian)
371 {
372 // We want to read exactly 2 Bytes of data.
373 if (isBigEndian)
374 *insn = (code[0] << 8) | code[1];
375 else
376 *insn = (code[1] << 8) | code[0];
377 }
378
379 /// readInstruction - read four bytes from the MemoryObject
380 /// and return 32 bit word sorted according to the given endianess
readInstruction32(unsigned char * code,uint32_t * insn,bool isBigEndian,bool isMicroMips)381 static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
382 {
383 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
384 // always precede the low 16 bits in the instruction stream (that is, they
385 // are placed at lower addresses in the instruction stream).
386 //
387 // microMIPS byte ordering:
388 // Big-endian: 0 | 1 | 2 | 3
389 // Little-endian: 1 | 0 | 3 | 2
390
391 // We want to read exactly 4 Bytes of data.
392 if (isBigEndian) {
393 // Encoded as a big-endian 32-bit word in the stream.
394 *insn =
395 (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
396 } else {
397 if (isMicroMips) {
398 *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
399 ((uint32_t) code[1] << 24);
400 } else {
401 *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
402 ((uint32_t) code[3] << 24);
403 }
404 }
405 }
406
MipsDisassembler_getInstruction(int mode,MCInst * instr,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address,bool isBigEndian,MCRegisterInfo * MRI)407 static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
408 const uint8_t *code, size_t code_len,
409 uint16_t *Size,
410 uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
411 {
412 uint32_t Insn;
413 DecodeStatus Result;
414
415 if (instr->flat_insn->detail) {
416 memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips));
417 }
418
419 if (mode & CS_MODE_MICRO) {
420 if (code_len < 2)
421 // not enough data
422 return MCDisassembler_Fail;
423
424 readInstruction16((unsigned char*)code, &Insn, isBigEndian);
425
426 // Calling the auto-generated decoder function.
427 Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
428 if (Result != MCDisassembler_Fail) {
429 *Size = 2;
430 return Result;
431 }
432
433 if (code_len < 4)
434 // not enough data
435 return MCDisassembler_Fail;
436
437 readInstruction32((unsigned char*)code, &Insn, isBigEndian, true);
438
439 //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
440 // Calling the auto-generated decoder function.
441 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
442 if (Result != MCDisassembler_Fail) {
443 *Size = 4;
444 return Result;
445 }
446 return MCDisassembler_Fail;
447 }
448
449 if (code_len < 4)
450 // not enough data
451 return MCDisassembler_Fail;
452
453 readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
454
455 if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) {
456 // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
457 Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
458 if (Result != MCDisassembler_Fail) {
459 *Size = 4;
460 return Result;
461 }
462 }
463
464 if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) {
465 // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
466 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
467 Address, MRI, mode);
468 if (Result != MCDisassembler_Fail) {
469 *Size = 4;
470 return Result;
471 }
472 }
473
474 if (mode & CS_MODE_MIPS32R6) {
475 // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
476 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
477 Address, MRI, mode);
478 if (Result != MCDisassembler_Fail) {
479 *Size = 4;
480 return Result;
481 }
482 }
483
484 if (mode & CS_MODE_MIPS64) {
485 // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
486 Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
487 Address, MRI, mode);
488 if (Result != MCDisassembler_Fail) {
489 *Size = 4;
490 return Result;
491 }
492 }
493
494 // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
495 // Calling the auto-generated decoder function.
496 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
497 if (Result != MCDisassembler_Fail) {
498 *Size = 4;
499 return Result;
500 }
501
502 return MCDisassembler_Fail;
503 }
504
Mips_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)505 bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
506 uint16_t *size, uint64_t address, void *info)
507 {
508 cs_struct *handle = (cs_struct *)(uintptr_t)ud;
509
510 DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr,
511 code, code_len,
512 size,
513 address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info);
514
515 return status == MCDisassembler_Success;
516 }
517
getReg(const MCRegisterInfo * MRI,unsigned RC,unsigned RegNo)518 static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
519 {
520 const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
521 return rc->RegsBegin[RegNo];
522 }
523
DecodeINSVE_DF_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)524 static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
525 uint64_t Address, const MCRegisterInfo *Decoder)
526 {
527 typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *);
528 // The size of the n field depends on the element size
529 // The register class also depends on this.
530 uint32_t tmp = fieldFromInstruction(insn, 17, 5);
531 unsigned NSize = 0;
532 DecodeFN RegDecoder = NULL;
533
534 if ((tmp & 0x18) == 0x00) { // INSVE_B
535 NSize = 4;
536 RegDecoder = DecodeMSA128BRegisterClass;
537 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
538 NSize = 3;
539 RegDecoder = DecodeMSA128HRegisterClass;
540 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
541 NSize = 2;
542 RegDecoder = DecodeMSA128WRegisterClass;
543 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
544 NSize = 1;
545 RegDecoder = DecodeMSA128DRegisterClass;
546 } //else llvm_unreachable("Invalid encoding");
547
548 //assert(NSize != 0 && RegDecoder != nullptr);
549 if (NSize == 0 || RegDecoder == NULL)
550 return MCDisassembler_Fail;
551
552 // $wd
553 tmp = fieldFromInstruction(insn, 6, 5);
554 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
555 return MCDisassembler_Fail;
556
557 // $wd_in
558 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
559 return MCDisassembler_Fail;
560
561 // $n
562 tmp = fieldFromInstruction(insn, 16, NSize);
563 MCOperand_CreateImm0(MI, tmp);
564
565 // $ws
566 tmp = fieldFromInstruction(insn, 11, 5);
567 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
568 return MCDisassembler_Fail;
569
570 // $n2
571 MCOperand_CreateImm0(MI, 0);
572
573 return MCDisassembler_Success;
574 }
575
DecodeAddiGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)576 static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
577 uint64_t Address, const MCRegisterInfo *Decoder)
578 {
579 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
580 // (otherwise we would have matched the ADDI instruction from the earlier
581 // ISA's instead).
582 //
583 // We have:
584 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
585 // BOVC if rs >= rt
586 // BEQZALC if rs == 0 && rt != 0
587 // BEQC if rs < rt && rs != 0
588
589 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
590 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
591 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
592 bool HasRs = false;
593
594 if (Rs >= Rt) {
595 MCInst_setOpcode(MI, Mips_BOVC);
596 HasRs = true;
597 } else if (Rs != 0 && Rs < Rt) {
598 MCInst_setOpcode(MI, Mips_BEQC);
599 HasRs = true;
600 } else
601 MCInst_setOpcode(MI, Mips_BEQZALC);
602
603 if (HasRs)
604 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
605
606 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
607 MCOperand_CreateImm0(MI, Imm);
608
609 return MCDisassembler_Success;
610 }
611
DecodeDaddiGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)612 static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
613 uint64_t Address, const MCRegisterInfo *Decoder)
614 {
615 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
616 // (otherwise we would have matched the ADDI instruction from the earlier
617 // ISA's instead).
618 //
619 // We have:
620 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
621 // BNVC if rs >= rt
622 // BNEZALC if rs == 0 && rt != 0
623 // BNEC if rs < rt && rs != 0
624
625 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
626 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
627 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
628 bool HasRs = false;
629
630 if (Rs >= Rt) {
631 MCInst_setOpcode(MI, Mips_BNVC);
632 HasRs = true;
633 } else if (Rs != 0 && Rs < Rt) {
634 MCInst_setOpcode(MI, Mips_BNEC);
635 HasRs = true;
636 } else
637 MCInst_setOpcode(MI, Mips_BNEZALC);
638
639 if (HasRs)
640 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
641
642 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
643 MCOperand_CreateImm0(MI, Imm);
644
645 return MCDisassembler_Success;
646 }
647
DecodeBlezlGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)648 static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
649 uint64_t Address, const MCRegisterInfo *Decoder)
650 {
651 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
652 // (otherwise we would have matched the BLEZL instruction from the earlier
653 // ISA's instead).
654 //
655 // We have:
656 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
657 // Invalid if rs == 0
658 // BLEZC if rs == 0 && rt != 0
659 // BGEZC if rs == rt && rt != 0
660 // BGEC if rs != rt && rs != 0 && rt != 0
661
662 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
663 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
664 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
665 bool HasRs = false;
666
667 if (Rt == 0)
668 return MCDisassembler_Fail;
669 else if (Rs == 0)
670 MCInst_setOpcode(MI, Mips_BLEZC);
671 else if (Rs == Rt)
672 MCInst_setOpcode(MI, Mips_BGEZC);
673 else {
674 HasRs = true;
675 MCInst_setOpcode(MI, Mips_BGEC);
676 }
677
678 if (HasRs)
679 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
680
681 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
682
683 MCOperand_CreateImm0(MI, Imm);
684
685 return MCDisassembler_Success;
686 }
687
DecodeBgtzlGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)688 static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
689 uint64_t Address, const MCRegisterInfo *Decoder)
690 {
691 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
692 // (otherwise we would have matched the BGTZL instruction from the earlier
693 // ISA's instead).
694 //
695 // We have:
696 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
697 // Invalid if rs == 0
698 // BGTZC if rs == 0 && rt != 0
699 // BLTZC if rs == rt && rt != 0
700 // BLTC if rs != rt && rs != 0 && rt != 0
701
702 bool HasRs = false;
703
704 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
705 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
706 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
707
708 if (Rt == 0)
709 return MCDisassembler_Fail;
710 else if (Rs == 0)
711 MCInst_setOpcode(MI, Mips_BGTZC);
712 else if (Rs == Rt)
713 MCInst_setOpcode(MI, Mips_BLTZC);
714 else {
715 MCInst_setOpcode(MI, Mips_BLTC);
716 HasRs = true;
717 }
718
719 if (HasRs)
720 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
721
722 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
723 MCOperand_CreateImm0(MI, Imm);
724
725 return MCDisassembler_Success;
726 }
727
DecodeBgtzGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)728 static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
729 uint64_t Address, const MCRegisterInfo *Decoder)
730 {
731 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
732 // (otherwise we would have matched the BGTZ instruction from the earlier
733 // ISA's instead).
734 //
735 // We have:
736 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
737 // BGTZ if rt == 0
738 // BGTZALC if rs == 0 && rt != 0
739 // BLTZALC if rs != 0 && rs == rt
740 // BLTUC if rs != 0 && rs != rt
741
742 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
743 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
744 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
745 bool HasRs = false;
746 bool HasRt = false;
747
748 if (Rt == 0) {
749 MCInst_setOpcode(MI, Mips_BGTZ);
750 HasRs = true;
751 } else if (Rs == 0) {
752 MCInst_setOpcode(MI, Mips_BGTZALC);
753 HasRt = true;
754 } else if (Rs == Rt) {
755 MCInst_setOpcode(MI, Mips_BLTZALC);
756 HasRs = true;
757 } else {
758 MCInst_setOpcode(MI, Mips_BLTUC);
759 HasRs = true;
760 HasRt = true;
761 }
762
763 if (HasRs)
764 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
765
766 if (HasRt)
767 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
768
769 MCOperand_CreateImm0(MI, Imm);
770
771 return MCDisassembler_Success;
772 }
773
DecodeBlezGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,const MCRegisterInfo * Decoder)774 static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
775 uint64_t Address, const MCRegisterInfo *Decoder)
776 {
777 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
778 // (otherwise we would have matched the BLEZL instruction from the earlier
779 // ISA's instead).
780 //
781 // We have:
782 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
783 // Invalid if rs == 0
784 // BLEZALC if rs == 0 && rt != 0
785 // BGEZALC if rs == rt && rt != 0
786 // BGEUC if rs != rt && rs != 0 && rt != 0
787
788 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
789 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
790 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
791 bool HasRs = false;
792
793 if (Rt == 0)
794 return MCDisassembler_Fail;
795 else if (Rs == 0)
796 MCInst_setOpcode(MI, Mips_BLEZALC);
797 else if (Rs == Rt)
798 MCInst_setOpcode(MI, Mips_BGEZALC);
799 else {
800 HasRs = true;
801 MCInst_setOpcode(MI, Mips_BGEUC);
802 }
803
804 if (HasRs)
805 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
806
807 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
808
809 MCOperand_CreateImm0(MI, Imm);
810
811 return MCDisassembler_Success;
812 }
813
DecodeCPU16RegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)814 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
815 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
816 {
817 return MCDisassembler_Fail;
818 }
819
DecodeGPR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)820 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
821 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
822 {
823 unsigned Reg;
824
825 if (RegNo > 31)
826 return MCDisassembler_Fail;
827
828 Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
829 MCOperand_CreateReg0(Inst, Reg);
830 return MCDisassembler_Success;
831 }
832
DecodeGPRMM16RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)833 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
834 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
835 {
836 unsigned Reg;
837
838 if (RegNo > 7)
839 return MCDisassembler_Fail;
840
841 Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo);
842 MCOperand_CreateReg0(Inst, Reg);
843 return MCDisassembler_Success;
844 }
845
DecodeGPRMM16ZeroRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)846 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
847 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
848 {
849 unsigned Reg;
850
851 if (RegNo > 7)
852 return MCDisassembler_Fail;
853
854 Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo);
855 MCOperand_CreateReg0(Inst, Reg);
856 return MCDisassembler_Success;
857 }
858
DecodeGPRMM16MovePRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)859 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
860 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
861 {
862 unsigned Reg;
863
864 if (RegNo > 7)
865 return MCDisassembler_Fail;
866
867 Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo);
868 MCOperand_CreateReg0(Inst, Reg);
869 return MCDisassembler_Success;
870 }
871
DecodeGPR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)872 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
873 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
874 {
875 unsigned Reg;
876
877 if (RegNo > 31)
878 return MCDisassembler_Fail;
879
880 Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
881 MCOperand_CreateReg0(Inst, Reg);
882 return MCDisassembler_Success;
883 }
884
DecodePtrRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)885 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
886 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
887 {
888 // if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
889 if (Inst->csh->mode & CS_MODE_MIPS64)
890 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
891
892 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
893 }
894
DecodeDSPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)895 static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
896 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
897 {
898 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
899 }
900
DecodeFGR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)901 static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
902 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
903 {
904 unsigned Reg;
905
906 if (RegNo > 31)
907 return MCDisassembler_Fail;
908
909 Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
910 MCOperand_CreateReg0(Inst, Reg);
911 return MCDisassembler_Success;
912 }
913
DecodeFGR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)914 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
915 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
916 {
917 unsigned Reg;
918
919 if (RegNo > 31)
920 return MCDisassembler_Fail;
921
922 Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
923 MCOperand_CreateReg0(Inst, Reg);
924 return MCDisassembler_Success;
925 }
926
DecodeCCRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)927 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
928 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
929 {
930 unsigned Reg;
931
932 if (RegNo > 31)
933 return MCDisassembler_Fail;
934
935 Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
936 MCOperand_CreateReg0(Inst, Reg);
937 return MCDisassembler_Success;
938 }
939
DecodeFCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)940 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
941 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
942 {
943 unsigned Reg;
944
945 if (RegNo > 7)
946 return MCDisassembler_Fail;
947
948 Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
949 MCOperand_CreateReg0(Inst, Reg);
950 return MCDisassembler_Success;
951 }
952
DecodeCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)953 static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
954 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
955 {
956 unsigned Reg;
957
958 if (RegNo > 7)
959 return MCDisassembler_Fail;
960
961 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo);
962 MCOperand_CreateReg0(Inst, Reg);
963 return MCDisassembler_Success;
964 }
965
DecodeFGRCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)966 static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
967 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
968 {
969 unsigned Reg;
970
971 if (RegNo > 31)
972 return MCDisassembler_Fail;
973
974 Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
975 MCOperand_CreateReg0(Inst, Reg);
976 return MCDisassembler_Success;
977 }
978
DecodeMem(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)979 static DecodeStatus DecodeMem(MCInst *Inst,
980 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
981 {
982 int Offset = SignExtend32(Insn & 0xffff, 16);
983 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
984 unsigned Base = fieldFromInstruction(Insn, 21, 5);
985 int opcode = MCInst_getOpcode(Inst);
986
987 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
988 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
989
990 if (opcode == Mips_SC || opcode == Mips_SCD) {
991 MCOperand_CreateReg0(Inst, Reg);
992 }
993
994 MCOperand_CreateReg0(Inst, Reg);
995 MCOperand_CreateReg0(Inst, Base);
996 MCOperand_CreateImm0(Inst, Offset);
997
998 return MCDisassembler_Success;
999 }
1000
DecodeCacheOp(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1001 static DecodeStatus DecodeCacheOp(MCInst *Inst,
1002 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1003 {
1004 int Offset = SignExtend32(Insn & 0xffff, 16);
1005 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1006 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1007
1008 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1009
1010 MCOperand_CreateReg0(Inst, Base);
1011 MCOperand_CreateImm0(Inst, Offset);
1012 MCOperand_CreateImm0(Inst, Hint);
1013
1014 return MCDisassembler_Success;
1015 }
1016
DecodeCacheOpMM(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1017 static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
1018 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1019 {
1020 int Offset = SignExtend32(Insn & 0xfff, 12);
1021 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1022 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1023
1024 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1025
1026 MCOperand_CreateReg0(Inst, Base);
1027 MCOperand_CreateImm0(Inst, Offset);
1028 MCOperand_CreateImm0(Inst, Hint);
1029
1030 return MCDisassembler_Success;
1031 }
1032
DecodeCacheOpR6(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1033 static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
1034 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1035 {
1036 int Offset = fieldFromInstruction(Insn, 7, 9);
1037 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1038 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1039
1040 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1041
1042 MCOperand_CreateReg0(Inst, Base);
1043 MCOperand_CreateImm0(Inst, Offset);
1044 MCOperand_CreateImm0(Inst, Hint);
1045
1046 return MCDisassembler_Success;
1047 }
1048
DecodeSyncI(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1049 static DecodeStatus DecodeSyncI(MCInst *Inst,
1050 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1051 {
1052 int Offset = SignExtend32(Insn & 0xffff, 16);
1053 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1054
1055 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1056
1057 MCOperand_CreateReg0(Inst, Base);
1058 MCOperand_CreateImm0(Inst, Offset);
1059
1060 return MCDisassembler_Success;
1061 }
1062
DecodeMSA128Mem(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1063 static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
1064 uint64_t Address, const MCRegisterInfo *Decoder)
1065 {
1066 int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
1067 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1068 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1069
1070 Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg);
1071 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1072
1073 MCOperand_CreateReg0(Inst, Reg);
1074 MCOperand_CreateReg0(Inst, Base);
1075 // MCOperand_CreateImm0(Inst, Offset);
1076
1077 // The immediate field of an LD/ST instruction is scaled which means it must
1078 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1079 // data format.
1080 // .b - 1 byte
1081 // .h - 2 bytes
1082 // .w - 4 bytes
1083 // .d - 8 bytes
1084 switch(MCInst_getOpcode(Inst)) {
1085 default:
1086 //assert (0 && "Unexpected instruction");
1087 return MCDisassembler_Fail;
1088 break;
1089 case Mips_LD_B:
1090 case Mips_ST_B:
1091 MCOperand_CreateImm0(Inst, Offset);
1092 break;
1093 case Mips_LD_H:
1094 case Mips_ST_H:
1095 MCOperand_CreateImm0(Inst, Offset * 2);
1096 break;
1097 case Mips_LD_W:
1098 case Mips_ST_W:
1099 MCOperand_CreateImm0(Inst, Offset * 4);
1100 break;
1101 case Mips_LD_D:
1102 case Mips_ST_D:
1103 MCOperand_CreateImm0(Inst, Offset * 8);
1104 break;
1105 }
1106
1107 return MCDisassembler_Success;
1108 }
1109
DecodeMemMMImm4(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1110 static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
1111 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1112 {
1113 unsigned Offset = Insn & 0xf;
1114 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1115 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1116
1117 switch (MCInst_getOpcode(Inst)) {
1118 case Mips_LBU16_MM:
1119 case Mips_LHU16_MM:
1120 case Mips_LW16_MM:
1121 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1122 == MCDisassembler_Fail)
1123 return MCDisassembler_Fail;
1124 break;
1125 case Mips_SB16_MM:
1126 case Mips_SH16_MM:
1127 case Mips_SW16_MM:
1128 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1129 == MCDisassembler_Fail)
1130 return MCDisassembler_Fail;
1131 break;
1132 }
1133
1134 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1135 == MCDisassembler_Fail)
1136 return MCDisassembler_Fail;
1137
1138 switch (MCInst_getOpcode(Inst)) {
1139 case Mips_LBU16_MM:
1140 if (Offset == 0xf)
1141 MCOperand_CreateImm0(Inst, -1);
1142 else
1143 MCOperand_CreateImm0(Inst, Offset);
1144 break;
1145 case Mips_SB16_MM:
1146 MCOperand_CreateImm0(Inst, Offset);
1147 break;
1148 case Mips_LHU16_MM:
1149 case Mips_SH16_MM:
1150 MCOperand_CreateImm0(Inst, Offset << 1);
1151 break;
1152 case Mips_LW16_MM:
1153 case Mips_SW16_MM:
1154 MCOperand_CreateImm0(Inst, Offset << 2);
1155 break;
1156 }
1157
1158 return MCDisassembler_Success;
1159 }
1160
DecodeMemMMSPImm5Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1161 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
1162 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1163 {
1164 unsigned Offset = Insn & 0x1F;
1165 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1166
1167 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1168
1169 MCOperand_CreateReg0(Inst, Reg);
1170 MCOperand_CreateReg0(Inst, Mips_SP);
1171 MCOperand_CreateImm0(Inst, Offset << 2);
1172
1173 return MCDisassembler_Success;
1174 }
1175
DecodeMemMMGPImm7Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1176 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
1177 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1178 {
1179 unsigned Offset = Insn & 0x7F;
1180 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1181
1182 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1183
1184 MCOperand_CreateReg0(Inst, Reg);
1185 MCOperand_CreateReg0(Inst, Mips_GP);
1186 MCOperand_CreateImm0(Inst, Offset << 2);
1187
1188 return MCDisassembler_Success;
1189 }
1190
DecodeMemMMReglistImm4Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1191 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
1192 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1193 {
1194 int Offset = SignExtend32(Insn & 0xf, 4);
1195
1196 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail)
1197 return MCDisassembler_Fail;
1198
1199 MCOperand_CreateReg0(Inst, Mips_SP);
1200 MCOperand_CreateImm0(Inst, Offset * 4);
1201
1202 return MCDisassembler_Success;
1203 }
1204
DecodeMemMMImm12(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1205 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
1206 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1207 {
1208 int Offset = SignExtend32(Insn & 0x0fff, 12);
1209 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1210 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1211
1212 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1213 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1214
1215 switch (MCInst_getOpcode(Inst)) {
1216 case Mips_SWM32_MM:
1217 case Mips_LWM32_MM:
1218 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1219 == MCDisassembler_Fail)
1220 return MCDisassembler_Fail;
1221 MCOperand_CreateReg0(Inst, Base);
1222 MCOperand_CreateImm0(Inst, Offset);
1223 break;
1224 case Mips_SC_MM:
1225 MCOperand_CreateReg0(Inst, Reg);
1226 // fallthrough
1227 default:
1228 MCOperand_CreateReg0(Inst, Reg);
1229 if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM)
1230 MCOperand_CreateReg0(Inst, Reg + 1);
1231
1232 MCOperand_CreateReg0(Inst, Base);
1233 MCOperand_CreateImm0(Inst, Offset);
1234 }
1235
1236 return MCDisassembler_Success;
1237 }
1238
DecodeMemMMImm16(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1239 static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
1240 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1241 {
1242 int Offset = SignExtend32(Insn & 0xffff, 16);
1243 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1244 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1245
1246 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1247 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1248
1249 MCOperand_CreateReg0(Inst, Reg);
1250 MCOperand_CreateReg0(Inst, Base);
1251 MCOperand_CreateImm0(Inst, Offset);
1252
1253 return MCDisassembler_Success;
1254 }
1255
DecodeFMem(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1256 static DecodeStatus DecodeFMem(MCInst *Inst,
1257 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1258 {
1259 int Offset = SignExtend32(Insn & 0xffff, 16);
1260 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1261 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1262
1263 Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg);
1264 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1265
1266 MCOperand_CreateReg0(Inst, Reg);
1267 MCOperand_CreateReg0(Inst, Base);
1268 MCOperand_CreateImm0(Inst, Offset);
1269
1270 return MCDisassembler_Success;
1271 }
1272
DecodeFMem2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1273 static DecodeStatus DecodeFMem2(MCInst *Inst,
1274 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1275 {
1276 int Offset = SignExtend32(Insn & 0xffff, 16);
1277 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1278 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1279
1280 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
1281 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1282
1283 MCOperand_CreateReg0(Inst, Reg);
1284 MCOperand_CreateReg0(Inst, Base);
1285 MCOperand_CreateImm0(Inst, Offset);
1286
1287 return MCDisassembler_Success;
1288 }
1289
DecodeFMem3(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1290 static DecodeStatus DecodeFMem3(MCInst *Inst,
1291 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1292 {
1293 int Offset = SignExtend32(Insn & 0xffff, 16);
1294 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1295 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1296
1297 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg);
1298 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1299
1300 MCOperand_CreateReg0(Inst, Reg);
1301 MCOperand_CreateReg0(Inst, Base);
1302 MCOperand_CreateImm0(Inst, Offset);
1303
1304 return MCDisassembler_Success;
1305 }
1306
DecodeFMemCop2R6(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1307 static DecodeStatus DecodeFMemCop2R6(MCInst *Inst,
1308 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1309 {
1310 int Offset = SignExtend32(Insn & 0x07ff, 11);
1311 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1312 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1313
1314 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
1315 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1316
1317 MCOperand_CreateReg0(Inst, Reg);
1318 MCOperand_CreateReg0(Inst, Base);
1319 MCOperand_CreateImm0(Inst, Offset);
1320
1321 return MCDisassembler_Success;
1322 }
1323
DecodeSpecial3LlSc(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1324 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
1325 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1326 {
1327 int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
1328 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1329 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1330
1331 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt);
1332 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1333
1334 if (MCInst_getOpcode(Inst) == Mips_SC_R6 ||
1335 MCInst_getOpcode(Inst) == Mips_SCD_R6) {
1336 MCOperand_CreateReg0(Inst, Rt);
1337 }
1338
1339 MCOperand_CreateReg0(Inst, Rt);
1340 MCOperand_CreateReg0(Inst, Base);
1341 MCOperand_CreateImm0(Inst, Offset);
1342
1343 return MCDisassembler_Success;
1344 }
1345
DecodeHWRegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1346 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
1347 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1348 {
1349 // Currently only hardware register 29 is supported.
1350 if (RegNo != 29)
1351 return MCDisassembler_Fail;
1352
1353 MCOperand_CreateReg0(Inst, Mips_HWR29);
1354
1355 return MCDisassembler_Success;
1356 }
1357
DecodeAFGR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1358 static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
1359 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1360 {
1361 unsigned Reg;
1362
1363 if (RegNo > 30 || RegNo % 2)
1364 return MCDisassembler_Fail;
1365
1366 Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
1367 MCOperand_CreateReg0(Inst, Reg);
1368
1369 return MCDisassembler_Success;
1370 }
1371
DecodeACC64DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1372 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
1373 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1374 {
1375 unsigned Reg;
1376
1377 if (RegNo >= 4)
1378 return MCDisassembler_Fail;
1379
1380 Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
1381 MCOperand_CreateReg0(Inst, Reg);
1382 return MCDisassembler_Success;
1383 }
1384
DecodeHI32DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1385 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
1386 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1387 {
1388 unsigned Reg;
1389
1390 if (RegNo >= 4)
1391 return MCDisassembler_Fail;
1392
1393 Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
1394 MCOperand_CreateReg0(Inst, Reg);
1395
1396 return MCDisassembler_Success;
1397 }
1398
DecodeLO32DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1399 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
1400 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1401 {
1402 unsigned Reg;
1403
1404 if (RegNo >= 4)
1405 return MCDisassembler_Fail;
1406
1407 Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
1408 MCOperand_CreateReg0(Inst, Reg);
1409
1410 return MCDisassembler_Success;
1411 }
1412
DecodeMSA128BRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1413 static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
1414 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1415 {
1416 unsigned Reg;
1417
1418 if (RegNo > 31)
1419 return MCDisassembler_Fail;
1420
1421 Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
1422 MCOperand_CreateReg0(Inst, Reg);
1423
1424 return MCDisassembler_Success;
1425 }
1426
DecodeMSA128HRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1427 static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
1428 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1429 {
1430 unsigned Reg;
1431
1432 if (RegNo > 31)
1433 return MCDisassembler_Fail;
1434
1435 Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
1436 MCOperand_CreateReg0(Inst, Reg);
1437
1438 return MCDisassembler_Success;
1439 }
1440
DecodeMSA128WRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1441 static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
1442 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1443 {
1444 unsigned Reg;
1445
1446 if (RegNo > 31)
1447 return MCDisassembler_Fail;
1448
1449 Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
1450 MCOperand_CreateReg0(Inst, Reg);
1451
1452 return MCDisassembler_Success;
1453 }
1454
DecodeMSA128DRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1455 static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
1456 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1457 {
1458 unsigned Reg;
1459
1460 if (RegNo > 31)
1461 return MCDisassembler_Fail;
1462
1463 Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
1464 MCOperand_CreateReg0(Inst, Reg);
1465
1466 return MCDisassembler_Success;
1467 }
1468
DecodeMSACtrlRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1469 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
1470 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1471 {
1472 unsigned Reg;
1473
1474 if (RegNo > 7)
1475 return MCDisassembler_Fail;
1476
1477 Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
1478 MCOperand_CreateReg0(Inst, Reg);
1479
1480 return MCDisassembler_Success;
1481 }
1482
DecodeCOP2RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const MCRegisterInfo * Decoder)1483 static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
1484 unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1485 {
1486 unsigned Reg;
1487
1488 if (RegNo > 31)
1489 return MCDisassembler_Fail;
1490
1491 Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
1492 MCOperand_CreateReg0(Inst, Reg);
1493
1494 return MCDisassembler_Success;
1495 }
1496
DecodeBranchTarget(MCInst * Inst,unsigned Offset,uint64_t Address,const MCRegisterInfo * Decoder)1497 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
1498 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1499 {
1500 uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
1501 MCOperand_CreateImm0(Inst, TargetAddress);
1502
1503 return MCDisassembler_Success;
1504 }
1505
DecodeJumpTarget(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1506 static DecodeStatus DecodeJumpTarget(MCInst *Inst,
1507 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1508 {
1509 uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
1510 MCOperand_CreateImm0(Inst, TargetAddress);
1511
1512 return MCDisassembler_Success;
1513 }
1514
DecodeBranchTarget21(MCInst * Inst,unsigned Offset,uint64_t Address,const MCRegisterInfo * Decoder)1515 static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
1516 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1517 {
1518 int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
1519
1520 MCOperand_CreateImm0(Inst, BranchOffset);
1521
1522 return MCDisassembler_Success;
1523 }
1524
DecodeBranchTarget26(MCInst * Inst,unsigned Offset,uint64_t Address,const MCRegisterInfo * Decoder)1525 static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
1526 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1527 {
1528 int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
1529
1530 MCOperand_CreateImm0(Inst, BranchOffset);
1531 return MCDisassembler_Success;
1532 }
1533
DecodeBranchTarget7MM(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1534 static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
1535 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1536 {
1537 int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
1538 MCOperand_CreateImm0(Inst, BranchOffset);
1539 return MCDisassembler_Success;
1540 }
1541
DecodeBranchTarget10MM(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1542 static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
1543 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1544 {
1545 int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
1546 MCOperand_CreateImm0(Inst, BranchOffset);
1547 return MCDisassembler_Success;
1548 }
1549
DecodeBranchTargetMM(MCInst * Inst,unsigned Offset,uint64_t Address,const MCRegisterInfo * Decoder)1550 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
1551 unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1552 {
1553 int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
1554 MCOperand_CreateImm0(Inst, BranchOffset);
1555
1556 return MCDisassembler_Success;
1557 }
1558
DecodeJumpTargetMM(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1559 static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
1560 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1561 {
1562 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1563 MCOperand_CreateImm0(Inst, JumpOffset);
1564
1565 return MCDisassembler_Success;
1566 }
1567
DecodeAddiur2Simm7(MCInst * Inst,unsigned Value,uint64_t Address,MCRegisterInfo * Decoder)1568 static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
1569 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1570 {
1571 if (Value == 0)
1572 MCOperand_CreateImm0(Inst, 1);
1573 else if (Value == 0x7)
1574 MCOperand_CreateImm0(Inst, -1);
1575 else
1576 MCOperand_CreateImm0(Inst, Value << 2);
1577
1578 return MCDisassembler_Success;
1579 }
1580
DecodeUImm6Lsl2(MCInst * Inst,unsigned Value,uint64_t Address,MCRegisterInfo * Decoder)1581 static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
1582 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1583 {
1584 MCOperand_CreateImm0(Inst, Value << 2);
1585
1586 return MCDisassembler_Success;
1587 }
1588
DecodeLiSimm7(MCInst * Inst,unsigned Value,uint64_t Address,MCRegisterInfo * Decoder)1589 static DecodeStatus DecodeLiSimm7(MCInst *Inst,
1590 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1591 {
1592 if (Value == 0x7F)
1593 MCOperand_CreateImm0(Inst, -1);
1594 else
1595 MCOperand_CreateImm0(Inst, Value);
1596
1597 return MCDisassembler_Success;
1598 }
1599
DecodeSimm4(MCInst * Inst,unsigned Value,uint64_t Address,MCRegisterInfo * Decoder)1600 static DecodeStatus DecodeSimm4(MCInst *Inst,
1601 unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1602 {
1603 MCOperand_CreateImm0(Inst, SignExtend32(Value, 4));
1604
1605 return MCDisassembler_Success;
1606 }
1607
DecodeSimm16(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1608 static DecodeStatus DecodeSimm16(MCInst *Inst,
1609 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1610 {
1611 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
1612
1613 return MCDisassembler_Success;
1614 }
1615
DecodeLSAImm(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1616 static DecodeStatus DecodeLSAImm(MCInst *Inst,
1617 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1618 {
1619 // We add one to the immediate field as it was encoded as 'imm - 1'.
1620 MCOperand_CreateImm0(Inst, Insn + 1);
1621
1622 return MCDisassembler_Success;
1623 }
1624
DecodeInsSize(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1625 static DecodeStatus DecodeInsSize(MCInst *Inst,
1626 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1627 {
1628 // First we need to grab the pos(lsb) from MCInst.
1629 int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
1630 int Size = (int) Insn - Pos + 1;
1631 MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1632
1633 return MCDisassembler_Success;
1634 }
1635
DecodeExtSize(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1636 static DecodeStatus DecodeExtSize(MCInst *Inst,
1637 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1638 {
1639 int Size = (int)Insn + 1;
1640
1641 MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1642
1643 return MCDisassembler_Success;
1644 }
1645
DecodeSimm19Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1646 static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
1647 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1648 {
1649 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
1650
1651 return MCDisassembler_Success;
1652 }
1653
DecodeSimm18Lsl3(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1654 static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
1655 unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1656 {
1657 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
1658
1659 return MCDisassembler_Success;
1660 }
1661
DecodeSimm9SP(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1662 static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
1663 uint64_t Address, MCRegisterInfo *Decoder)
1664 {
1665 int32_t DecodedValue;
1666
1667 switch (Insn) {
1668 case 0: DecodedValue = 256; break;
1669 case 1: DecodedValue = 257; break;
1670 case 510: DecodedValue = -258; break;
1671 case 511: DecodedValue = -257; break;
1672 default: DecodedValue = SignExtend32(Insn, 9); break;
1673 }
1674 MCOperand_CreateImm0(Inst, DecodedValue * 4);
1675
1676 return MCDisassembler_Success;
1677 }
1678
DecodeANDI16Imm(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1679 static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn,
1680 uint64_t Address, MCRegisterInfo *Decoder)
1681 {
1682 // Insn must be >= 0, since it is unsigned that condition is always true.
1683 // assert(Insn < 16);
1684 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1685 255, 32768, 65535};
1686
1687 if (Insn >= 16)
1688 return MCDisassembler_Fail;
1689
1690 MCOperand_CreateImm0(Inst, DecodedValues[Insn]);
1691
1692 return MCDisassembler_Success;
1693 }
1694
DecodeUImm5lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1695 static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn,
1696 uint64_t Address, MCRegisterInfo *Decoder)
1697 {
1698 MCOperand_CreateImm0(Inst, Insn << 2);
1699
1700 return MCDisassembler_Success;
1701 }
1702
DecodeRegListOperand(MCInst * Inst,unsigned Insn,uint64_t Address,const MCRegisterInfo * Decoder)1703 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
1704 uint64_t Address, const MCRegisterInfo *Decoder)
1705 {
1706 unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
1707 Mips_S6, Mips_FP};
1708 unsigned RegNum;
1709 unsigned int i;
1710
1711 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1712 // Empty register lists are not allowed.
1713 if (RegLst == 0)
1714 return MCDisassembler_Fail;
1715
1716 RegNum = RegLst & 0xf;
1717 for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++)
1718 MCOperand_CreateReg0(Inst, Regs[i]);
1719
1720 if (RegLst & 0x10)
1721 MCOperand_CreateReg0(Inst, Mips_RA);
1722
1723 return MCDisassembler_Success;
1724 }
1725
DecodeRegListOperand16(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1726 static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn,
1727 uint64_t Address, MCRegisterInfo *Decoder)
1728 {
1729 unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3};
1730 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1731 unsigned RegNum = RegLst & 0x3;
1732 unsigned int i;
1733
1734 for (i = 0; i <= RegNum; i++)
1735 MCOperand_CreateReg0(Inst, Regs[i]);
1736
1737 MCOperand_CreateReg0(Inst, Mips_RA);
1738
1739 return MCDisassembler_Success;
1740 }
1741
DecodeMovePRegPair(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1742 static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
1743 uint64_t Address, MCRegisterInfo *Decoder)
1744 {
1745 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1746
1747 switch (RegPair) {
1748 default:
1749 return MCDisassembler_Fail;
1750 case 0:
1751 MCOperand_CreateReg0(Inst, Mips_A1);
1752 MCOperand_CreateReg0(Inst, Mips_A2);
1753 break;
1754 case 1:
1755 MCOperand_CreateReg0(Inst, Mips_A1);
1756 MCOperand_CreateReg0(Inst, Mips_A3);
1757 break;
1758 case 2:
1759 MCOperand_CreateReg0(Inst, Mips_A2);
1760 MCOperand_CreateReg0(Inst, Mips_A3);
1761 break;
1762 case 3:
1763 MCOperand_CreateReg0(Inst, Mips_A0);
1764 MCOperand_CreateReg0(Inst, Mips_S5);
1765 break;
1766 case 4:
1767 MCOperand_CreateReg0(Inst, Mips_A0);
1768 MCOperand_CreateReg0(Inst, Mips_S6);
1769 break;
1770 case 5:
1771 MCOperand_CreateReg0(Inst, Mips_A0);
1772 MCOperand_CreateReg0(Inst, Mips_A1);
1773 break;
1774 case 6:
1775 MCOperand_CreateReg0(Inst, Mips_A0);
1776 MCOperand_CreateReg0(Inst, Mips_A2);
1777 break;
1778 case 7:
1779 MCOperand_CreateReg0(Inst, Mips_A0);
1780 MCOperand_CreateReg0(Inst, Mips_A3);
1781 break;
1782 }
1783
1784 return MCDisassembler_Success;
1785 }
1786
DecodeSimm23Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1787 static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
1788 uint64_t Address, MCRegisterInfo *Decoder)
1789 {
1790 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
1791 return MCDisassembler_Success;
1792 }
1793
1794 #endif
1795