1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the Mips target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_immZExt5(int64_t Imm) { 12return Imm == (Imm & 0x1f); 13} 14static bool Predicate_immZExt6(int64_t Imm) { 15return Imm == (Imm & 0x3f); 16} 17static bool Predicate_immSExt6(int64_t Imm) { 18return isInt<6>(Imm); 19} 20static bool Predicate_immZExt4Ptr(int64_t Imm) { 21return isUInt<4>(Imm); 22} 23static bool Predicate_immZExt3Ptr(int64_t Imm) { 24return isUInt<3>(Imm); 25} 26static bool Predicate_immZExt2Ptr(int64_t Imm) { 27return isUInt<2>(Imm); 28} 29static bool Predicate_immZExt1Ptr(int64_t Imm) { 30return isUInt<1>(Imm); 31} 32static bool Predicate_immZExt4(int64_t Imm) { 33return isUInt<4>(Imm); 34} 35static bool Predicate_immSExtAddiur2(int64_t Imm) { 36return Imm == 1 || Imm == -1 || 37 ((Imm % 4 == 0) && 38 Imm < 28 && Imm > 0); 39} 40static bool Predicate_immSExtAddius5(int64_t Imm) { 41return Imm >= -8 && Imm <= 7; 42} 43static bool Predicate_immZExtAndi16(int64_t Imm) { 44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || 45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || 46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 ); 47} 48static bool Predicate_immZExt2Shift(int64_t Imm) { 49return Imm >= 1 && Imm <= 8; 50} 51 52 53// FastEmit functions for ISD::BITCAST. 54 55unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 56 if (RetVT.SimpleTy != MVT::f32) 57 return 0; 58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 59 return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 60 } 61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 62 return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 63 } 64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 65 return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill); 66 } 67 return 0; 68} 69 70unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 71 if (RetVT.SimpleTy != MVT::f64) 72 return 0; 73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 74 return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill); 75 } 76 return 0; 77} 78 79unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 80 if (RetVT.SimpleTy != MVT::i32) 81 return 0; 82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 83 return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 84 } 85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 86 return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 87 } 88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 89 return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill); 90 } 91 return 0; 92} 93 94unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 95 if (RetVT.SimpleTy != MVT::i64) 96 return 0; 97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 98 return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill); 99 } 100 return 0; 101} 102 103unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 104 switch (VT.SimpleTy) { 105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); 106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill); 107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill); 108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 109 default: return 0; 110 } 111} 112 113// FastEmit functions for ISD::BRIND. 114 115unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 116 if (RetVT.SimpleTy != MVT::isVoid) 117 return 0; 118 if ((Subtarget->inMips16Mode())) { 119 return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill); 120 } 121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 122 return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 123 } 124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 125 return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 126 } 127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 128 return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 129 } 130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 131 return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 132 } 133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 134 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill); 135 } 136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 137 return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill); 138 } 139 return 0; 140} 141 142unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 143 if (RetVT.SimpleTy != MVT::isVoid) 144 return 0; 145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 146 return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 147 } 148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 149 return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 150 } 151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 152 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill); 153 } 154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 155 return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill); 156 } 157 return 0; 158} 159 160unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 161 switch (VT.SimpleTy) { 162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill); 163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill); 164 default: return 0; 165 } 166} 167 168// FastEmit functions for ISD::CTLZ. 169 170unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 171 if (RetVT.SimpleTy != MVT::i32) 172 return 0; 173 if ((Subtarget->inMicroMipsMode())) { 174 return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 175 } 176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) { 177 return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill); 178 } 179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 180 return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill); 181 } 182 return 0; 183} 184 185unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 186 if (RetVT.SimpleTy != MVT::i64) 187 return 0; 188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 189 return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 190 } 191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) { 192 return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill); 193 } 194 return 0; 195} 196 197unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 198 if (RetVT.SimpleTy != MVT::v16i8) 199 return 0; 200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 201 return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill); 202 } 203 return 0; 204} 205 206unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 207 if (RetVT.SimpleTy != MVT::v8i16) 208 return 0; 209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 210 return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill); 211 } 212 return 0; 213} 214 215unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 216 if (RetVT.SimpleTy != MVT::v4i32) 217 return 0; 218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 219 return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 220 } 221 return 0; 222} 223 224unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 225 if (RetVT.SimpleTy != MVT::v2i64) 226 return 0; 227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 228 return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 229 } 230 return 0; 231} 232 233unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 234 switch (VT.SimpleTy) { 235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill); 237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 241 default: return 0; 242 } 243} 244 245// FastEmit functions for ISD::CTPOP. 246 247unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 248 if (RetVT.SimpleTy != MVT::i32) 249 return 0; 250 if ((Subtarget->hasCnMips())) { 251 return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill); 252 } 253 return 0; 254} 255 256unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 257 if (RetVT.SimpleTy != MVT::i64) 258 return 0; 259 if ((Subtarget->hasCnMips())) { 260 return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill); 261 } 262 return 0; 263} 264 265unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 266 if (RetVT.SimpleTy != MVT::v16i8) 267 return 0; 268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 269 return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill); 270 } 271 return 0; 272} 273 274unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 275 if (RetVT.SimpleTy != MVT::v8i16) 276 return 0; 277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 278 return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill); 279 } 280 return 0; 281} 282 283unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 284 if (RetVT.SimpleTy != MVT::v4i32) 285 return 0; 286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 287 return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 288 } 289 return 0; 290} 291 292unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 293 if (RetVT.SimpleTy != MVT::v2i64) 294 return 0; 295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 296 return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 297 } 298 return 0; 299} 300 301unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 302 switch (VT.SimpleTy) { 303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill); 304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill); 305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 309 default: return 0; 310 } 311} 312 313// FastEmit functions for ISD::FABS. 314 315unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 316 if (RetVT.SimpleTy != MVT::f32) 317 return 0; 318 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) { 319 return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 320 } 321 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) { 322 return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 323 } 324 return 0; 325} 326 327unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 328 if (RetVT.SimpleTy != MVT::f64) 329 return 0; 330 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 331 return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 332 } 333 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 334 return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 335 } 336 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) { 337 return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 338 } 339 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) { 340 return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 341 } 342 return 0; 343} 344 345unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 346 if (RetVT.SimpleTy != MVT::v4f32) 347 return 0; 348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 349 return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 350 } 351 return 0; 352} 353 354unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 355 if (RetVT.SimpleTy != MVT::v2f64) 356 return 0; 357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 358 return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 359 } 360 return 0; 361} 362 363unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 364 switch (VT.SimpleTy) { 365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 366 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 367 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 368 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 369 default: return 0; 370 } 371} 372 373// FastEmit functions for ISD::FEXP2. 374 375unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 if (RetVT.SimpleTy != MVT::v4f32) 377 return 0; 378 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 379 return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill); 380 } 381 return 0; 382} 383 384unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 385 if (RetVT.SimpleTy != MVT::v2f64) 386 return 0; 387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 388 return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill); 389 } 390 return 0; 391} 392 393unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 394 switch (VT.SimpleTy) { 395 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 396 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 397 default: return 0; 398 } 399} 400 401// FastEmit functions for ISD::FLOG2. 402 403unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 404 if (RetVT.SimpleTy != MVT::v4f32) 405 return 0; 406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 407 return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 408 } 409 return 0; 410} 411 412unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 413 if (RetVT.SimpleTy != MVT::v2f64) 414 return 0; 415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 416 return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 417 } 418 return 0; 419} 420 421unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 422 switch (VT.SimpleTy) { 423 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 424 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 425 default: return 0; 426 } 427} 428 429// FastEmit functions for ISD::FNEG. 430 431unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 432 if (RetVT.SimpleTy != MVT::f32) 433 return 0; 434 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 435 return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 436 } 437 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 438 return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 439 } 440 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) { 441 return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 442 } 443 return 0; 444} 445 446unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 447 if (RetVT.SimpleTy != MVT::f64) 448 return 0; 449 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 450 return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 451 } 452 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 453 return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 454 } 455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 456 return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 457 } 458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 459 return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 460 } 461 return 0; 462} 463 464unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 465 switch (VT.SimpleTy) { 466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 467 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 468 default: return 0; 469 } 470} 471 472// FastEmit functions for ISD::FP_EXTEND. 473 474unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 475 if ((Subtarget->hasMSA())) { 476 return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill); 477 } 478 return 0; 479} 480 481unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 482 if ((Subtarget->hasMSA())) { 483 return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill); 484 } 485 return 0; 486} 487 488unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 489switch (RetVT.SimpleTy) { 490 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill); 491 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill); 492 default: return 0; 493} 494} 495 496unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 497 if (RetVT.SimpleTy != MVT::f64) 498 return 0; 499 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) { 500 return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 501 } 502 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) { 503 return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 504 } 505 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 506 return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill); 507 } 508 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 509 return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill); 510 } 511 return 0; 512} 513 514unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 515 switch (VT.SimpleTy) { 516 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill); 517 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 518 default: return 0; 519 } 520} 521 522// FastEmit functions for ISD::FP_ROUND. 523 524unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 525 if (RetVT.SimpleTy != MVT::f16) 526 return 0; 527 if ((Subtarget->hasMSA())) { 528 return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill); 529 } 530 return 0; 531} 532 533unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 534 if ((Subtarget->hasMSA())) { 535 return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill); 536 } 537 return 0; 538} 539 540unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 541 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) { 542 return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 543 } 544 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) { 545 return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 546 } 547 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 548 return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill); 549 } 550 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 551 return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill); 552 } 553 return 0; 554} 555 556unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 557switch (RetVT.SimpleTy) { 558 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill); 559 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 560 default: return 0; 561} 562} 563 564unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 565 switch (VT.SimpleTy) { 566 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 567 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 568 default: return 0; 569 } 570} 571 572// FastEmit functions for ISD::FP_TO_SINT. 573 574unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 575 if (RetVT.SimpleTy != MVT::v4i32) 576 return 0; 577 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 578 return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 579 } 580 return 0; 581} 582 583unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 584 if (RetVT.SimpleTy != MVT::v2i64) 585 return 0; 586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 587 return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 588 } 589 return 0; 590} 591 592unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 593 switch (VT.SimpleTy) { 594 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 595 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 596 default: return 0; 597 } 598} 599 600// FastEmit functions for ISD::FP_TO_UINT. 601 602unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 603 if (RetVT.SimpleTy != MVT::v4i32) 604 return 0; 605 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 606 return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 607 } 608 return 0; 609} 610 611unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 612 if (RetVT.SimpleTy != MVT::v2i64) 613 return 0; 614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 615 return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 616 } 617 return 0; 618} 619 620unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 621 switch (VT.SimpleTy) { 622 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 623 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 624 default: return 0; 625 } 626} 627 628// FastEmit functions for ISD::FRINT. 629 630unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 631 if (RetVT.SimpleTy != MVT::v4f32) 632 return 0; 633 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 634 return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 635 } 636 return 0; 637} 638 639unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 640 if (RetVT.SimpleTy != MVT::v2f64) 641 return 0; 642 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 643 return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 644 } 645 return 0; 646} 647 648unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 649 switch (VT.SimpleTy) { 650 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 651 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 652 default: return 0; 653 } 654} 655 656// FastEmit functions for ISD::FSQRT. 657 658unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 659 if (RetVT.SimpleTy != MVT::f32) 660 return 0; 661 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 662 return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 663 } 664 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 665 return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 666 } 667 return 0; 668} 669 670unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 671 if (RetVT.SimpleTy != MVT::f64) 672 return 0; 673 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 674 return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 675 } 676 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 677 return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 678 } 679 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 680 return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 681 } 682 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 683 return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 684 } 685 return 0; 686} 687 688unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 689 if (RetVT.SimpleTy != MVT::v4f32) 690 return 0; 691 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 692 return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 693 } 694 return 0; 695} 696 697unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 698 if (RetVT.SimpleTy != MVT::v2f64) 699 return 0; 700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 701 return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 702 } 703 return 0; 704} 705 706unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 707 switch (VT.SimpleTy) { 708 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 709 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 710 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 711 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 712 default: return 0; 713 } 714} 715 716// FastEmit functions for ISD::SIGN_EXTEND. 717 718unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 719 if (RetVT.SimpleTy != MVT::i64) 720 return 0; 721 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) { 722 return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill); 723 } 724 return 0; 725} 726 727unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 728 switch (VT.SimpleTy) { 729 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill); 730 default: return 0; 731 } 732} 733 734// FastEmit functions for ISD::SINT_TO_FP. 735 736unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 737 return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill); 738} 739 740unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 741 if ((Subtarget->isFP64bit())) { 742 return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill); 743 } 744 if ((!Subtarget->isFP64bit())) { 745 return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill); 746 } 747 return 0; 748} 749 750unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 751switch (RetVT.SimpleTy) { 752 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 753 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 754 default: return 0; 755} 756} 757 758unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 759 if (RetVT.SimpleTy != MVT::f64) 760 return 0; 761 if ((Subtarget->isFP64bit())) { 762 return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill); 763 } 764 return 0; 765} 766 767unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 768 if (RetVT.SimpleTy != MVT::v4f32) 769 return 0; 770 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 771 return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 772 } 773 return 0; 774} 775 776unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 777 if (RetVT.SimpleTy != MVT::v2f64) 778 return 0; 779 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 780 return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 781 } 782 return 0; 783} 784 785unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 786 switch (VT.SimpleTy) { 787 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 788 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 789 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 790 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 791 default: return 0; 792 } 793} 794 795// FastEmit functions for ISD::UINT_TO_FP. 796 797unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 798 if (RetVT.SimpleTy != MVT::v4f32) 799 return 0; 800 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 801 return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 802 } 803 return 0; 804} 805 806unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 807 if (RetVT.SimpleTy != MVT::v2f64) 808 return 0; 809 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 810 return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 811 } 812 return 0; 813} 814 815unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 816 switch (VT.SimpleTy) { 817 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 818 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 819 default: return 0; 820 } 821} 822 823// FastEmit functions for MipsISD::JmpLink. 824 825unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 826 if (RetVT.SimpleTy != MVT::isVoid) 827 return 0; 828 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 829 return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 830 } 831 if ((Subtarget->inMips16Mode())) { 832 return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill); 833 } 834 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 835 return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill); 836 } 837 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) { 838 return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill); 839 } 840 return 0; 841} 842 843unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 844 if (RetVT.SimpleTy != MVT::isVoid) 845 return 0; 846 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 847 return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill); 848 } 849 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) { 850 return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill); 851 } 852 return 0; 853} 854 855unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 856 switch (VT.SimpleTy) { 857 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill); 858 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill); 859 default: return 0; 860 } 861} 862 863// FastEmit functions for MipsISD::MFHI. 864 865unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 866 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 867 return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 868 } 869 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) { 870 return fastEmitInst_r(Mips::PseudoMFHI_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 871 } 872 if ((Subtarget->hasDSP())) { 873 return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill); 874 } 875 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 876 return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill); 877 } 878 return 0; 879} 880 881unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 882 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 883 return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill); 884 } 885 return 0; 886} 887 888unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 889switch (RetVT.SimpleTy) { 890 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill); 891 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill); 892 default: return 0; 893} 894} 895 896unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 897 switch (VT.SimpleTy) { 898 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill); 899 default: return 0; 900 } 901} 902 903// FastEmit functions for MipsISD::MFLO. 904 905unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 906 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 907 return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 908 } 909 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) { 910 return fastEmitInst_r(Mips::PseudoMFLO_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 911 } 912 if ((Subtarget->hasDSP())) { 913 return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill); 914 } 915 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 916 return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill); 917 } 918 return 0; 919} 920 921unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 922 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 923 return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill); 924 } 925 return 0; 926} 927 928unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 929switch (RetVT.SimpleTy) { 930 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill); 931 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill); 932 default: return 0; 933} 934} 935 936unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 937 switch (VT.SimpleTy) { 938 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill); 939 default: return 0; 940 } 941} 942 943// FastEmit functions for MipsISD::MTC1_D64. 944 945unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 946 if (RetVT.SimpleTy != MVT::f64) 947 return 0; 948 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) { 949 return fastEmitInst_r(Mips::MTC1_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 950 } 951 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 952 return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 953 } 954 return 0; 955} 956 957unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 958 switch (VT.SimpleTy) { 959 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill); 960 default: return 0; 961 } 962} 963 964// FastEmit functions for MipsISD::TailCall. 965 966unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 967 if (RetVT.SimpleTy != MVT::isVoid) 968 return 0; 969 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 970 return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 971 } 972 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 973 return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 974 } 975 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 976 return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill); 977 } 978 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 979 return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill); 980 } 981 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 982 return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill); 983 } 984 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 985 return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill); 986 } 987 return 0; 988} 989 990unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 991 if (RetVT.SimpleTy != MVT::isVoid) 992 return 0; 993 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 994 return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill); 995 } 996 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 997 return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill); 998 } 999 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 1000 return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill); 1001 } 1002 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 1003 return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill); 1004 } 1005 return 0; 1006} 1007 1008unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1009 switch (VT.SimpleTy) { 1010 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill); 1011 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill); 1012 default: return 0; 1013 } 1014} 1015 1016// FastEmit functions for MipsISD::TruncIntFP. 1017 1018unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 1019 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1020 return fastEmitInst_r(Mips::TRUNC_W_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 1021 } 1022 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1023 return fastEmitInst_r(Mips::TRUNC_W_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 1024 } 1025 if ((Subtarget->hasStandardEncoding())) { 1026 return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 1027 } 1028 return 0; 1029} 1030 1031unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1032 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1033 return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill); 1034 } 1035 return 0; 1036} 1037 1038unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1039switch (RetVT.SimpleTy) { 1040 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill); 1041 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill); 1042 default: return 0; 1043} 1044} 1045 1046unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 1047 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1048 return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 1049 } 1050 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) { 1051 return fastEmitInst_r(Mips::CVT_W_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 1052 } 1053 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) { 1054 return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 1055 } 1056 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1057 return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill); 1058 } 1059 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1060 return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill); 1061 } 1062 return 0; 1063} 1064 1065unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1066 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1067 return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 1068 } 1069 return 0; 1070} 1071 1072unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1073switch (RetVT.SimpleTy) { 1074 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 1075 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill); 1076 default: return 0; 1077} 1078} 1079 1080unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1081 switch (VT.SimpleTy) { 1082 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill); 1083 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill); 1084 default: return 0; 1085 } 1086} 1087 1088// FastEmit functions for MipsISD::VALL_NONZERO. 1089 1090unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1091 if (RetVT.SimpleTy != MVT::i32) 1092 return 0; 1093 return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1094} 1095 1096unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1097 if (RetVT.SimpleTy != MVT::i32) 1098 return 0; 1099 return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1100} 1101 1102unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1103 if (RetVT.SimpleTy != MVT::i32) 1104 return 0; 1105 return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1106} 1107 1108unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1109 if (RetVT.SimpleTy != MVT::i32) 1110 return 0; 1111 return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1112} 1113 1114unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1115 switch (VT.SimpleTy) { 1116 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1117 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1118 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1119 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1120 default: return 0; 1121 } 1122} 1123 1124// FastEmit functions for MipsISD::VALL_ZERO. 1125 1126unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1127 if (RetVT.SimpleTy != MVT::i32) 1128 return 0; 1129 return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1130} 1131 1132unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1133 if (RetVT.SimpleTy != MVT::i32) 1134 return 0; 1135 return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1136} 1137 1138unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1139 if (RetVT.SimpleTy != MVT::i32) 1140 return 0; 1141 return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1142} 1143 1144unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1145 if (RetVT.SimpleTy != MVT::i32) 1146 return 0; 1147 return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1148} 1149 1150unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1151 switch (VT.SimpleTy) { 1152 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1153 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1154 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1155 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1156 default: return 0; 1157 } 1158} 1159 1160// FastEmit functions for MipsISD::VANY_NONZERO. 1161 1162unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1163 if (RetVT.SimpleTy != MVT::i32) 1164 return 0; 1165 return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1166} 1167 1168unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1169 switch (VT.SimpleTy) { 1170 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1171 default: return 0; 1172 } 1173} 1174 1175// FastEmit functions for MipsISD::VANY_ZERO. 1176 1177unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1178 if (RetVT.SimpleTy != MVT::i32) 1179 return 0; 1180 return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1181} 1182 1183unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1184 switch (VT.SimpleTy) { 1185 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1186 default: return 0; 1187 } 1188} 1189 1190// Top-level FastEmit function. 1191 1192unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 1193 switch (Opcode) { 1194 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 1195 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 1196 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 1197 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 1198 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 1199 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill); 1200 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill); 1201 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 1202 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 1203 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 1204 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 1205 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 1206 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 1207 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 1208 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 1209 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 1210 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 1211 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill); 1212 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill); 1213 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill); 1214 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill); 1215 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill); 1216 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill); 1217 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill); 1218 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill); 1219 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill); 1220 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill); 1221 default: return 0; 1222 } 1223} 1224 1225// FastEmit functions for ISD::ADD. 1226 1227unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1228 if (RetVT.SimpleTy != MVT::i32) 1229 return 0; 1230 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1231 return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1232 } 1233 if ((Subtarget->inMips16Mode())) { 1234 return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1235 } 1236 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1237 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1238 } 1239 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1240 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1241 } 1242 return 0; 1243} 1244 1245unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1246 if (RetVT.SimpleTy != MVT::i64) 1247 return 0; 1248 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1249 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1250 } 1251 return 0; 1252} 1253 1254unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1255 if (RetVT.SimpleTy != MVT::v4i8) 1256 return 0; 1257 if ((Subtarget->hasDSP())) { 1258 return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1259 } 1260 return 0; 1261} 1262 1263unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1264 if (RetVT.SimpleTy != MVT::v16i8) 1265 return 0; 1266 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1267 return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1268 } 1269 return 0; 1270} 1271 1272unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1273 if (RetVT.SimpleTy != MVT::v2i16) 1274 return 0; 1275 if ((Subtarget->hasDSP())) { 1276 return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1277 } 1278 return 0; 1279} 1280 1281unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1282 if (RetVT.SimpleTy != MVT::v8i16) 1283 return 0; 1284 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1285 return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1286 } 1287 return 0; 1288} 1289 1290unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1291 if (RetVT.SimpleTy != MVT::v4i32) 1292 return 0; 1293 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1294 return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1295 } 1296 return 0; 1297} 1298 1299unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1300 if (RetVT.SimpleTy != MVT::v2i64) 1301 return 0; 1302 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1303 return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1304 } 1305 return 0; 1306} 1307 1308unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1309 switch (VT.SimpleTy) { 1310 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1311 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1312 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1313 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1314 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1315 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1316 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1317 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1318 default: return 0; 1319 } 1320} 1321 1322// FastEmit functions for ISD::ADDC. 1323 1324unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1325 if (RetVT.SimpleTy != MVT::i32) 1326 return 0; 1327 if ((Subtarget->hasDSP())) { 1328 return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1329 } 1330 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) { 1331 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1332 } 1333 return 0; 1334} 1335 1336unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1337 if (RetVT.SimpleTy != MVT::i64) 1338 return 0; 1339 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) { 1340 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1341 } 1342 return 0; 1343} 1344 1345unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1346 switch (VT.SimpleTy) { 1347 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1348 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1349 default: return 0; 1350 } 1351} 1352 1353// FastEmit functions for ISD::ADDE. 1354 1355unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1356 if (RetVT.SimpleTy != MVT::i32) 1357 return 0; 1358 if ((Subtarget->hasDSP())) { 1359 return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1360 } 1361 return 0; 1362} 1363 1364unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1365 switch (VT.SimpleTy) { 1366 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1367 default: return 0; 1368 } 1369} 1370 1371// FastEmit functions for ISD::AND. 1372 1373unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1374 if (RetVT.SimpleTy != MVT::i32) 1375 return 0; 1376 if ((Subtarget->inMips16Mode())) { 1377 return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1378 } 1379 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1380 return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1381 } 1382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1383 return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1384 } 1385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1386 return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1387 } 1388 return 0; 1389} 1390 1391unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1392 if (RetVT.SimpleTy != MVT::i64) 1393 return 0; 1394 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 1395 return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1396 } 1397 return 0; 1398} 1399 1400unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1401 if (RetVT.SimpleTy != MVT::v16i8) 1402 return 0; 1403 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1404 return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1405 } 1406 return 0; 1407} 1408 1409unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1410 if (RetVT.SimpleTy != MVT::v8i16) 1411 return 0; 1412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1413 return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1414 } 1415 return 0; 1416} 1417 1418unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1419 if (RetVT.SimpleTy != MVT::v4i32) 1420 return 0; 1421 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1422 return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1423 } 1424 return 0; 1425} 1426 1427unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1428 if (RetVT.SimpleTy != MVT::v2i64) 1429 return 0; 1430 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1431 return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1432 } 1433 return 0; 1434} 1435 1436unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1437 switch (VT.SimpleTy) { 1438 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1439 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1440 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1441 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1442 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1443 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1444 default: return 0; 1445 } 1446} 1447 1448// FastEmit functions for ISD::FADD. 1449 1450unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1451 if (RetVT.SimpleTy != MVT::f32) 1452 return 0; 1453 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1454 return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1455 } 1456 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1457 return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1458 } 1459 return 0; 1460} 1461 1462unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1463 if (RetVT.SimpleTy != MVT::f64) 1464 return 0; 1465 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1466 return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1467 } 1468 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1469 return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1470 } 1471 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1472 return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1473 } 1474 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1475 return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1476 } 1477 return 0; 1478} 1479 1480unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1481 if (RetVT.SimpleTy != MVT::v4f32) 1482 return 0; 1483 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1484 return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1485 } 1486 return 0; 1487} 1488 1489unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1490 if (RetVT.SimpleTy != MVT::v2f64) 1491 return 0; 1492 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1493 return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1494 } 1495 return 0; 1496} 1497 1498unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1499 switch (VT.SimpleTy) { 1500 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1501 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1502 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1503 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1504 default: return 0; 1505 } 1506} 1507 1508// FastEmit functions for ISD::FDIV. 1509 1510unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1511 if (RetVT.SimpleTy != MVT::f32) 1512 return 0; 1513 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1514 return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1515 } 1516 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1517 return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1518 } 1519 return 0; 1520} 1521 1522unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1523 if (RetVT.SimpleTy != MVT::f64) 1524 return 0; 1525 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1526 return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1527 } 1528 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1529 return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1530 } 1531 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1532 return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1533 } 1534 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1535 return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1536 } 1537 return 0; 1538} 1539 1540unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1541 if (RetVT.SimpleTy != MVT::v4f32) 1542 return 0; 1543 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1544 return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1545 } 1546 return 0; 1547} 1548 1549unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1550 if (RetVT.SimpleTy != MVT::v2f64) 1551 return 0; 1552 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1553 return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1554 } 1555 return 0; 1556} 1557 1558unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1559 switch (VT.SimpleTy) { 1560 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1561 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1562 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1563 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1564 default: return 0; 1565 } 1566} 1567 1568// FastEmit functions for ISD::FMUL. 1569 1570unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1571 if (RetVT.SimpleTy != MVT::f32) 1572 return 0; 1573 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1574 return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1575 } 1576 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1577 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1578 } 1579 return 0; 1580} 1581 1582unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1583 if (RetVT.SimpleTy != MVT::f64) 1584 return 0; 1585 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1586 return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1587 } 1588 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1589 return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1590 } 1591 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1592 return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1593 } 1594 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1595 return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1596 } 1597 return 0; 1598} 1599 1600unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1601 if (RetVT.SimpleTy != MVT::v4f32) 1602 return 0; 1603 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1604 return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1605 } 1606 return 0; 1607} 1608 1609unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1610 if (RetVT.SimpleTy != MVT::v2f64) 1611 return 0; 1612 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1613 return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1614 } 1615 return 0; 1616} 1617 1618unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1619 switch (VT.SimpleTy) { 1620 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1621 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1622 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1623 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1624 default: return 0; 1625 } 1626} 1627 1628// FastEmit functions for ISD::FSUB. 1629 1630unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1631 if (RetVT.SimpleTy != MVT::f32) 1632 return 0; 1633 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1634 return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1635 } 1636 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1637 return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1638 } 1639 return 0; 1640} 1641 1642unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1643 if (RetVT.SimpleTy != MVT::f64) 1644 return 0; 1645 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1646 return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1647 } 1648 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1649 return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1650 } 1651 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1652 return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1653 } 1654 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1655 return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1656 } 1657 return 0; 1658} 1659 1660unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1661 if (RetVT.SimpleTy != MVT::v4f32) 1662 return 0; 1663 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1664 return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1665 } 1666 return 0; 1667} 1668 1669unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1670 if (RetVT.SimpleTy != MVT::v2f64) 1671 return 0; 1672 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1673 return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1674 } 1675 return 0; 1676} 1677 1678unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1679 switch (VT.SimpleTy) { 1680 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1681 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1682 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1683 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1684 default: return 0; 1685 } 1686} 1687 1688// FastEmit functions for ISD::MUL. 1689 1690unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1691 if (RetVT.SimpleTy != MVT::i32) 1692 return 0; 1693 if ((Subtarget->inMips16Mode())) { 1694 return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1695 } 1696 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1697 return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1698 } 1699 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1700 return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1701 } 1702 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1703 return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1704 } 1705 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 1706 return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1707 } 1708 return 0; 1709} 1710 1711unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1712 if (RetVT.SimpleTy != MVT::i64) 1713 return 0; 1714 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1715 return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1716 } 1717 if ((Subtarget->hasCnMips())) { 1718 return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1719 } 1720 return 0; 1721} 1722 1723unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1724 if (RetVT.SimpleTy != MVT::v16i8) 1725 return 0; 1726 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1727 return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1728 } 1729 return 0; 1730} 1731 1732unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1733 if (RetVT.SimpleTy != MVT::v2i16) 1734 return 0; 1735 if ((Subtarget->hasDSPR2())) { 1736 return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1737 } 1738 return 0; 1739} 1740 1741unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1742 if (RetVT.SimpleTy != MVT::v8i16) 1743 return 0; 1744 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1745 return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1746 } 1747 return 0; 1748} 1749 1750unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1751 if (RetVT.SimpleTy != MVT::v4i32) 1752 return 0; 1753 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1754 return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1755 } 1756 return 0; 1757} 1758 1759unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1760 if (RetVT.SimpleTy != MVT::v2i64) 1761 return 0; 1762 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1763 return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1764 } 1765 return 0; 1766} 1767 1768unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1769 switch (VT.SimpleTy) { 1770 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1771 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1772 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1773 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1774 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1775 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1776 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1777 default: return 0; 1778 } 1779} 1780 1781// FastEmit functions for ISD::MULHS. 1782 1783unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1784 if (RetVT.SimpleTy != MVT::i32) 1785 return 0; 1786 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1787 return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1788 } 1789 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1790 return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1791 } 1792 return 0; 1793} 1794 1795unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1796 if (RetVT.SimpleTy != MVT::i64) 1797 return 0; 1798 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1799 return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1800 } 1801 return 0; 1802} 1803 1804unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1805 switch (VT.SimpleTy) { 1806 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1807 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1808 default: return 0; 1809 } 1810} 1811 1812// FastEmit functions for ISD::MULHU. 1813 1814unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1815 if (RetVT.SimpleTy != MVT::i32) 1816 return 0; 1817 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1818 return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1819 } 1820 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1821 return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1822 } 1823 return 0; 1824} 1825 1826unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1827 if (RetVT.SimpleTy != MVT::i64) 1828 return 0; 1829 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1830 return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1831 } 1832 return 0; 1833} 1834 1835unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1836 switch (VT.SimpleTy) { 1837 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1838 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1839 default: return 0; 1840 } 1841} 1842 1843// FastEmit functions for ISD::OR. 1844 1845unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1846 if (RetVT.SimpleTy != MVT::i32) 1847 return 0; 1848 if ((Subtarget->inMips16Mode())) { 1849 return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1850 } 1851 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1852 return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1853 } 1854 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1855 return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1856 } 1857 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1858 return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1859 } 1860 return 0; 1861} 1862 1863unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1864 if (RetVT.SimpleTy != MVT::i64) 1865 return 0; 1866 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 1867 return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1868 } 1869 return 0; 1870} 1871 1872unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1873 if (RetVT.SimpleTy != MVT::v16i8) 1874 return 0; 1875 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1876 return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1877 } 1878 return 0; 1879} 1880 1881unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1882 if (RetVT.SimpleTy != MVT::v8i16) 1883 return 0; 1884 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1885 return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1886 } 1887 return 0; 1888} 1889 1890unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1891 if (RetVT.SimpleTy != MVT::v4i32) 1892 return 0; 1893 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1894 return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1895 } 1896 return 0; 1897} 1898 1899unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1900 if (RetVT.SimpleTy != MVT::v2i64) 1901 return 0; 1902 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1903 return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1904 } 1905 return 0; 1906} 1907 1908unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1909 switch (VT.SimpleTy) { 1910 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1911 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1912 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1913 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1914 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1915 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1916 default: return 0; 1917 } 1918} 1919 1920// FastEmit functions for ISD::ROTR. 1921 1922unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1923 if (RetVT.SimpleTy != MVT::i32) 1924 return 0; 1925 if ((Subtarget->inMicroMipsMode())) { 1926 return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1927 } 1928 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1929 return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1930 } 1931 return 0; 1932} 1933 1934unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1935 switch (VT.SimpleTy) { 1936 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1937 default: return 0; 1938 } 1939} 1940 1941// FastEmit functions for ISD::SDIV. 1942 1943unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1944 if (RetVT.SimpleTy != MVT::i32) 1945 return 0; 1946 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1947 return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1948 } 1949 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1950 return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1951 } 1952 return 0; 1953} 1954 1955unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1956 if (RetVT.SimpleTy != MVT::i64) 1957 return 0; 1958 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1959 return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1960 } 1961 return 0; 1962} 1963 1964unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1965 if (RetVT.SimpleTy != MVT::v16i8) 1966 return 0; 1967 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1968 return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1969 } 1970 return 0; 1971} 1972 1973unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1974 if (RetVT.SimpleTy != MVT::v8i16) 1975 return 0; 1976 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1977 return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1978 } 1979 return 0; 1980} 1981 1982unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1983 if (RetVT.SimpleTy != MVT::v4i32) 1984 return 0; 1985 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1986 return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1987 } 1988 return 0; 1989} 1990 1991unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1992 if (RetVT.SimpleTy != MVT::v2i64) 1993 return 0; 1994 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1995 return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1996 } 1997 return 0; 1998} 1999 2000unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2001 switch (VT.SimpleTy) { 2002 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2003 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2004 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2005 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2006 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2007 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2008 default: return 0; 2009 } 2010} 2011 2012// FastEmit functions for ISD::SHL. 2013 2014unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2015 if (RetVT.SimpleTy != MVT::i32) 2016 return 0; 2017 if ((Subtarget->inMicroMipsMode())) { 2018 return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2019 } 2020 if ((Subtarget->inMips16Mode())) { 2021 return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2022 } 2023 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2024 return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2025 } 2026 return 0; 2027} 2028 2029unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2030 if (RetVT.SimpleTy != MVT::v16i8) 2031 return 0; 2032 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2033 return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2034 } 2035 return 0; 2036} 2037 2038unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2039 if (RetVT.SimpleTy != MVT::v8i16) 2040 return 0; 2041 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2042 return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2043 } 2044 return 0; 2045} 2046 2047unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2048 if (RetVT.SimpleTy != MVT::v4i32) 2049 return 0; 2050 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2051 return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2052 } 2053 return 0; 2054} 2055 2056unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2057 if (RetVT.SimpleTy != MVT::v2i64) 2058 return 0; 2059 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2060 return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2061 } 2062 return 0; 2063} 2064 2065unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2066 switch (VT.SimpleTy) { 2067 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2068 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2069 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2070 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2071 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2072 default: return 0; 2073 } 2074} 2075 2076// FastEmit functions for ISD::SMAX. 2077 2078unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2079 if (RetVT.SimpleTy != MVT::v16i8) 2080 return 0; 2081 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2082 return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2083 } 2084 return 0; 2085} 2086 2087unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2088 if (RetVT.SimpleTy != MVT::v8i16) 2089 return 0; 2090 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2091 return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2092 } 2093 return 0; 2094} 2095 2096unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2097 if (RetVT.SimpleTy != MVT::v4i32) 2098 return 0; 2099 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2100 return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2101 } 2102 return 0; 2103} 2104 2105unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2106 if (RetVT.SimpleTy != MVT::v2i64) 2107 return 0; 2108 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2109 return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2110 } 2111 return 0; 2112} 2113 2114unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2115 switch (VT.SimpleTy) { 2116 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2117 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2118 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2119 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2120 default: return 0; 2121 } 2122} 2123 2124// FastEmit functions for ISD::SMIN. 2125 2126unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2127 if (RetVT.SimpleTy != MVT::v16i8) 2128 return 0; 2129 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2130 return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2131 } 2132 return 0; 2133} 2134 2135unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2136 if (RetVT.SimpleTy != MVT::v8i16) 2137 return 0; 2138 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2139 return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2140 } 2141 return 0; 2142} 2143 2144unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2145 if (RetVT.SimpleTy != MVT::v4i32) 2146 return 0; 2147 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2148 return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2149 } 2150 return 0; 2151} 2152 2153unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2154 if (RetVT.SimpleTy != MVT::v2i64) 2155 return 0; 2156 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2157 return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2158 } 2159 return 0; 2160} 2161 2162unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2163 switch (VT.SimpleTy) { 2164 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2165 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2166 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2167 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2168 default: return 0; 2169 } 2170} 2171 2172// FastEmit functions for ISD::SRA. 2173 2174unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2175 if (RetVT.SimpleTy != MVT::i32) 2176 return 0; 2177 if ((Subtarget->inMicroMipsMode())) { 2178 return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2179 } 2180 if ((Subtarget->inMips16Mode())) { 2181 return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2182 } 2183 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2184 return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2185 } 2186 return 0; 2187} 2188 2189unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2190 if (RetVT.SimpleTy != MVT::v16i8) 2191 return 0; 2192 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2193 return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2194 } 2195 return 0; 2196} 2197 2198unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2199 if (RetVT.SimpleTy != MVT::v8i16) 2200 return 0; 2201 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2202 return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2203 } 2204 return 0; 2205} 2206 2207unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2208 if (RetVT.SimpleTy != MVT::v4i32) 2209 return 0; 2210 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2211 return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2212 } 2213 return 0; 2214} 2215 2216unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2217 if (RetVT.SimpleTy != MVT::v2i64) 2218 return 0; 2219 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2220 return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2221 } 2222 return 0; 2223} 2224 2225unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2226 switch (VT.SimpleTy) { 2227 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2228 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2229 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2230 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2231 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2232 default: return 0; 2233 } 2234} 2235 2236// FastEmit functions for ISD::SREM. 2237 2238unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2239 if (RetVT.SimpleTy != MVT::i32) 2240 return 0; 2241 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2242 return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2243 } 2244 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2245 return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2246 } 2247 return 0; 2248} 2249 2250unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2251 if (RetVT.SimpleTy != MVT::i64) 2252 return 0; 2253 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2254 return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2255 } 2256 return 0; 2257} 2258 2259unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2260 if (RetVT.SimpleTy != MVT::v16i8) 2261 return 0; 2262 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2263 return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2264 } 2265 return 0; 2266} 2267 2268unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2269 if (RetVT.SimpleTy != MVT::v8i16) 2270 return 0; 2271 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2272 return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2273 } 2274 return 0; 2275} 2276 2277unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2278 if (RetVT.SimpleTy != MVT::v4i32) 2279 return 0; 2280 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2281 return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2282 } 2283 return 0; 2284} 2285 2286unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2287 if (RetVT.SimpleTy != MVT::v2i64) 2288 return 0; 2289 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2290 return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2291 } 2292 return 0; 2293} 2294 2295unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2296 switch (VT.SimpleTy) { 2297 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2298 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2299 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2300 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2301 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2302 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2303 default: return 0; 2304 } 2305} 2306 2307// FastEmit functions for ISD::SRL. 2308 2309unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2310 if (RetVT.SimpleTy != MVT::i32) 2311 return 0; 2312 if ((Subtarget->inMicroMipsMode())) { 2313 return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2314 } 2315 if ((Subtarget->inMips16Mode())) { 2316 return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2317 } 2318 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2319 return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2320 } 2321 return 0; 2322} 2323 2324unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2325 if (RetVT.SimpleTy != MVT::v16i8) 2326 return 0; 2327 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2328 return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2329 } 2330 return 0; 2331} 2332 2333unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2334 if (RetVT.SimpleTy != MVT::v8i16) 2335 return 0; 2336 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2337 return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2338 } 2339 return 0; 2340} 2341 2342unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2343 if (RetVT.SimpleTy != MVT::v4i32) 2344 return 0; 2345 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2346 return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2347 } 2348 return 0; 2349} 2350 2351unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2352 if (RetVT.SimpleTy != MVT::v2i64) 2353 return 0; 2354 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2355 return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2356 } 2357 return 0; 2358} 2359 2360unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2361 switch (VT.SimpleTy) { 2362 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2363 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2364 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2365 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2366 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2367 default: return 0; 2368 } 2369} 2370 2371// FastEmit functions for ISD::SUB. 2372 2373unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2374 if (RetVT.SimpleTy != MVT::i32) 2375 return 0; 2376 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2377 return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2378 } 2379 if ((Subtarget->inMips16Mode())) { 2380 return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2381 } 2382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 2383 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2384 } 2385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2386 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2387 } 2388 return 0; 2389} 2390 2391unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2392 if (RetVT.SimpleTy != MVT::i64) 2393 return 0; 2394 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2395 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2396 } 2397 return 0; 2398} 2399 2400unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2401 if (RetVT.SimpleTy != MVT::v4i8) 2402 return 0; 2403 if ((Subtarget->hasDSP())) { 2404 return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2405 } 2406 return 0; 2407} 2408 2409unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2410 if (RetVT.SimpleTy != MVT::v16i8) 2411 return 0; 2412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2413 return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2414 } 2415 return 0; 2416} 2417 2418unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2419 if (RetVT.SimpleTy != MVT::v2i16) 2420 return 0; 2421 if ((Subtarget->hasDSP())) { 2422 return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2423 } 2424 return 0; 2425} 2426 2427unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2428 if (RetVT.SimpleTy != MVT::v8i16) 2429 return 0; 2430 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2431 return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2432 } 2433 return 0; 2434} 2435 2436unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2437 if (RetVT.SimpleTy != MVT::v4i32) 2438 return 0; 2439 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2440 return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2441 } 2442 return 0; 2443} 2444 2445unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2446 if (RetVT.SimpleTy != MVT::v2i64) 2447 return 0; 2448 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2449 return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2450 } 2451 return 0; 2452} 2453 2454unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2455 switch (VT.SimpleTy) { 2456 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2457 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2458 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2459 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2460 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2461 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2462 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2463 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2464 default: return 0; 2465 } 2466} 2467 2468// FastEmit functions for ISD::SUBC. 2469 2470unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2471 if (RetVT.SimpleTy != MVT::i32) 2472 return 0; 2473 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2474 return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2475 } 2476 if ((Subtarget->inMicroMipsMode())) { 2477 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2478 } 2479 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2480 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2481 } 2482 return 0; 2483} 2484 2485unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2486 if (RetVT.SimpleTy != MVT::i64) 2487 return 0; 2488 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) { 2489 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2490 } 2491 return 0; 2492} 2493 2494unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2495 switch (VT.SimpleTy) { 2496 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2497 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2498 default: return 0; 2499 } 2500} 2501 2502// FastEmit functions for ISD::UDIV. 2503 2504unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2505 if (RetVT.SimpleTy != MVT::i32) 2506 return 0; 2507 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2508 return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2509 } 2510 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2511 return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2512 } 2513 return 0; 2514} 2515 2516unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2517 if (RetVT.SimpleTy != MVT::i64) 2518 return 0; 2519 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2520 return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2521 } 2522 return 0; 2523} 2524 2525unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2526 if (RetVT.SimpleTy != MVT::v16i8) 2527 return 0; 2528 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2529 return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2530 } 2531 return 0; 2532} 2533 2534unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2535 if (RetVT.SimpleTy != MVT::v8i16) 2536 return 0; 2537 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2538 return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2539 } 2540 return 0; 2541} 2542 2543unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2544 if (RetVT.SimpleTy != MVT::v4i32) 2545 return 0; 2546 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2547 return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2548 } 2549 return 0; 2550} 2551 2552unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2553 if (RetVT.SimpleTy != MVT::v2i64) 2554 return 0; 2555 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2556 return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2557 } 2558 return 0; 2559} 2560 2561unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2562 switch (VT.SimpleTy) { 2563 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2564 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2565 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2566 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2567 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2568 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2569 default: return 0; 2570 } 2571} 2572 2573// FastEmit functions for ISD::UMAX. 2574 2575unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2576 if (RetVT.SimpleTy != MVT::v16i8) 2577 return 0; 2578 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2579 return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2580 } 2581 return 0; 2582} 2583 2584unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2585 if (RetVT.SimpleTy != MVT::v8i16) 2586 return 0; 2587 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2588 return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2589 } 2590 return 0; 2591} 2592 2593unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2594 if (RetVT.SimpleTy != MVT::v4i32) 2595 return 0; 2596 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2597 return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2598 } 2599 return 0; 2600} 2601 2602unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2603 if (RetVT.SimpleTy != MVT::v2i64) 2604 return 0; 2605 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2606 return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2607 } 2608 return 0; 2609} 2610 2611unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2612 switch (VT.SimpleTy) { 2613 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2614 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2615 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2616 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2617 default: return 0; 2618 } 2619} 2620 2621// FastEmit functions for ISD::UMIN. 2622 2623unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2624 if (RetVT.SimpleTy != MVT::v16i8) 2625 return 0; 2626 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2627 return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2628 } 2629 return 0; 2630} 2631 2632unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2633 if (RetVT.SimpleTy != MVT::v8i16) 2634 return 0; 2635 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2636 return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2637 } 2638 return 0; 2639} 2640 2641unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2642 if (RetVT.SimpleTy != MVT::v4i32) 2643 return 0; 2644 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2645 return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2646 } 2647 return 0; 2648} 2649 2650unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2651 if (RetVT.SimpleTy != MVT::v2i64) 2652 return 0; 2653 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2654 return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2655 } 2656 return 0; 2657} 2658 2659unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2660 switch (VT.SimpleTy) { 2661 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2662 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2663 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2664 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2665 default: return 0; 2666 } 2667} 2668 2669// FastEmit functions for ISD::UREM. 2670 2671unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2672 if (RetVT.SimpleTy != MVT::i32) 2673 return 0; 2674 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2675 return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2676 } 2677 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2678 return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2679 } 2680 return 0; 2681} 2682 2683unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2684 if (RetVT.SimpleTy != MVT::i64) 2685 return 0; 2686 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2687 return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2688 } 2689 return 0; 2690} 2691 2692unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2693 if (RetVT.SimpleTy != MVT::v16i8) 2694 return 0; 2695 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2696 return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2697 } 2698 return 0; 2699} 2700 2701unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2702 if (RetVT.SimpleTy != MVT::v8i16) 2703 return 0; 2704 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2705 return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2706 } 2707 return 0; 2708} 2709 2710unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2711 if (RetVT.SimpleTy != MVT::v4i32) 2712 return 0; 2713 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2714 return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2715 } 2716 return 0; 2717} 2718 2719unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2720 if (RetVT.SimpleTy != MVT::v2i64) 2721 return 0; 2722 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2723 return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2724 } 2725 return 0; 2726} 2727 2728unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2729 switch (VT.SimpleTy) { 2730 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2731 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2732 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2733 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2734 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2735 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2736 default: return 0; 2737 } 2738} 2739 2740// FastEmit functions for ISD::XOR. 2741 2742unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2743 if (RetVT.SimpleTy != MVT::i32) 2744 return 0; 2745 if ((Subtarget->inMips16Mode())) { 2746 return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2747 } 2748 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2749 return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2750 } 2751 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 2752 return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2753 } 2754 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2755 return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2756 } 2757 return 0; 2758} 2759 2760unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2761 if (RetVT.SimpleTy != MVT::i64) 2762 return 0; 2763 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 2764 return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2765 } 2766 return 0; 2767} 2768 2769unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2770 if (RetVT.SimpleTy != MVT::v16i8) 2771 return 0; 2772 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2773 return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2774 } 2775 return 0; 2776} 2777 2778unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2779 if (RetVT.SimpleTy != MVT::v8i16) 2780 return 0; 2781 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2782 return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2783 } 2784 return 0; 2785} 2786 2787unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2788 if (RetVT.SimpleTy != MVT::v4i32) 2789 return 0; 2790 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2791 return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2792 } 2793 return 0; 2794} 2795 2796unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2797 if (RetVT.SimpleTy != MVT::v2i64) 2798 return 0; 2799 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2800 return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2801 } 2802 return 0; 2803} 2804 2805unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2806 switch (VT.SimpleTy) { 2807 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2808 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2809 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2810 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2811 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2812 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2813 default: return 0; 2814 } 2815} 2816 2817// FastEmit functions for MipsISD::BuildPairF64. 2818 2819unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2820 if (RetVT.SimpleTy != MVT::f64) 2821 return 0; 2822 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) { 2823 return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2824 } 2825 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) { 2826 return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2827 } 2828 return 0; 2829} 2830 2831unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2832 switch (VT.SimpleTy) { 2833 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2834 default: return 0; 2835 } 2836} 2837 2838// FastEmit functions for MipsISD::DivRem. 2839 2840unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2841 if (RetVT.SimpleTy != MVT::Untyped) 2842 return 0; 2843 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2844 return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2845 } 2846 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2847 return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2848 } 2849 return 0; 2850} 2851 2852unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2853 if (RetVT.SimpleTy != MVT::Untyped) 2854 return 0; 2855 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2856 return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2857 } 2858 return 0; 2859} 2860 2861unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2862 switch (VT.SimpleTy) { 2863 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2864 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2865 default: return 0; 2866 } 2867} 2868 2869// FastEmit functions for MipsISD::DivRem16. 2870 2871unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2872 if (RetVT.SimpleTy != MVT::isVoid) 2873 return 0; 2874 if ((Subtarget->inMips16Mode())) { 2875 return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2876 } 2877 return 0; 2878} 2879 2880unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2881 switch (VT.SimpleTy) { 2882 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2883 default: return 0; 2884 } 2885} 2886 2887// FastEmit functions for MipsISD::DivRemU. 2888 2889unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2890 if (RetVT.SimpleTy != MVT::Untyped) 2891 return 0; 2892 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2893 return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2894 } 2895 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2896 return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2897 } 2898 return 0; 2899} 2900 2901unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2902 if (RetVT.SimpleTy != MVT::Untyped) 2903 return 0; 2904 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2905 return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2906 } 2907 return 0; 2908} 2909 2910unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2911 switch (VT.SimpleTy) { 2912 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2913 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2914 default: return 0; 2915 } 2916} 2917 2918// FastEmit functions for MipsISD::DivRemU16. 2919 2920unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2921 if (RetVT.SimpleTy != MVT::isVoid) 2922 return 0; 2923 if ((Subtarget->inMips16Mode())) { 2924 return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2925 } 2926 return 0; 2927} 2928 2929unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2930 switch (VT.SimpleTy) { 2931 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2932 default: return 0; 2933 } 2934} 2935 2936// FastEmit functions for MipsISD::EH_RETURN. 2937 2938unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2939 if (RetVT.SimpleTy != MVT::isVoid) 2940 return 0; 2941 return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2942} 2943 2944unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2945 if (RetVT.SimpleTy != MVT::isVoid) 2946 return 0; 2947 return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2948} 2949 2950unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2951 switch (VT.SimpleTy) { 2952 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2953 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2954 default: return 0; 2955 } 2956} 2957 2958// FastEmit functions for MipsISD::ILVEV. 2959 2960unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2961 if (RetVT.SimpleTy != MVT::v16i8) 2962 return 0; 2963 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2964 return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2965 } 2966 return 0; 2967} 2968 2969unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2970 if (RetVT.SimpleTy != MVT::v8i16) 2971 return 0; 2972 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2973 return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2974 } 2975 return 0; 2976} 2977 2978unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2979 if (RetVT.SimpleTy != MVT::v4i32) 2980 return 0; 2981 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2982 return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2983 } 2984 return 0; 2985} 2986 2987unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2988 if (RetVT.SimpleTy != MVT::v2i64) 2989 return 0; 2990 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2991 return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2992 } 2993 return 0; 2994} 2995 2996unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2997 switch (VT.SimpleTy) { 2998 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2999 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3000 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3001 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3002 default: return 0; 3003 } 3004} 3005 3006// FastEmit functions for MipsISD::ILVL. 3007 3008unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3009 if (RetVT.SimpleTy != MVT::v16i8) 3010 return 0; 3011 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3012 return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3013 } 3014 return 0; 3015} 3016 3017unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3018 if (RetVT.SimpleTy != MVT::v8i16) 3019 return 0; 3020 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3021 return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3022 } 3023 return 0; 3024} 3025 3026unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3027 if (RetVT.SimpleTy != MVT::v4i32) 3028 return 0; 3029 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3030 return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3031 } 3032 return 0; 3033} 3034 3035unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3036 if (RetVT.SimpleTy != MVT::v2i64) 3037 return 0; 3038 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3039 return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3040 } 3041 return 0; 3042} 3043 3044unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3045 switch (VT.SimpleTy) { 3046 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3047 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3048 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3049 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3050 default: return 0; 3051 } 3052} 3053 3054// FastEmit functions for MipsISD::ILVOD. 3055 3056unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3057 if (RetVT.SimpleTy != MVT::v16i8) 3058 return 0; 3059 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3060 return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3061 } 3062 return 0; 3063} 3064 3065unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3066 if (RetVT.SimpleTy != MVT::v8i16) 3067 return 0; 3068 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3069 return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3070 } 3071 return 0; 3072} 3073 3074unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3075 if (RetVT.SimpleTy != MVT::v4i32) 3076 return 0; 3077 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3078 return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3079 } 3080 return 0; 3081} 3082 3083unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3084 if (RetVT.SimpleTy != MVT::v2i64) 3085 return 0; 3086 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3087 return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3088 } 3089 return 0; 3090} 3091 3092unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3093 switch (VT.SimpleTy) { 3094 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3095 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3096 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3097 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3098 default: return 0; 3099 } 3100} 3101 3102// FastEmit functions for MipsISD::ILVR. 3103 3104unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3105 if (RetVT.SimpleTy != MVT::v16i8) 3106 return 0; 3107 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3108 return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3109 } 3110 return 0; 3111} 3112 3113unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3114 if (RetVT.SimpleTy != MVT::v8i16) 3115 return 0; 3116 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3117 return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3118 } 3119 return 0; 3120} 3121 3122unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3123 if (RetVT.SimpleTy != MVT::v4i32) 3124 return 0; 3125 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3126 return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3127 } 3128 return 0; 3129} 3130 3131unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3132 if (RetVT.SimpleTy != MVT::v2i64) 3133 return 0; 3134 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3135 return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3136 } 3137 return 0; 3138} 3139 3140unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3141 switch (VT.SimpleTy) { 3142 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3143 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3144 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3145 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3146 default: return 0; 3147 } 3148} 3149 3150// FastEmit functions for MipsISD::MTLOHI. 3151 3152unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3153 if (RetVT.SimpleTy != MVT::Untyped) 3154 return 0; 3155 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) { 3156 return fastEmitInst_rr(Mips::PseudoMTLOHI_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3157 } 3158 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) { 3159 return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3160 } 3161 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3162 return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3163 } 3164 return 0; 3165} 3166 3167unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3168 if (RetVT.SimpleTy != MVT::Untyped) 3169 return 0; 3170 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3171 return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3172 } 3173 return 0; 3174} 3175 3176unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3177 switch (VT.SimpleTy) { 3178 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3179 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3180 default: return 0; 3181 } 3182} 3183 3184// FastEmit functions for MipsISD::Mult. 3185 3186unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3187 if (RetVT.SimpleTy != MVT::Untyped) 3188 return 0; 3189 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 3190 return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3191 } 3192 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) { 3193 return fastEmitInst_rr(Mips::PseudoMULT_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3194 } 3195 if ((Subtarget->hasDSP())) { 3196 return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3197 } 3198 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3199 return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3200 } 3201 return 0; 3202} 3203 3204unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3205 if (RetVT.SimpleTy != MVT::Untyped) 3206 return 0; 3207 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3208 return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3209 } 3210 return 0; 3211} 3212 3213unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3214 switch (VT.SimpleTy) { 3215 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3216 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3217 default: return 0; 3218 } 3219} 3220 3221// FastEmit functions for MipsISD::Multu. 3222 3223unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3224 if (RetVT.SimpleTy != MVT::Untyped) 3225 return 0; 3226 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 3227 return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3228 } 3229 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) { 3230 return fastEmitInst_rr(Mips::PseudoMULTu_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3231 } 3232 if ((Subtarget->hasDSP())) { 3233 return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3234 } 3235 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3236 return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3237 } 3238 return 0; 3239} 3240 3241unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3242 if (RetVT.SimpleTy != MVT::Untyped) 3243 return 0; 3244 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3245 return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3246 } 3247 return 0; 3248} 3249 3250unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3251 switch (VT.SimpleTy) { 3252 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3253 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3254 default: return 0; 3255 } 3256} 3257 3258// FastEmit functions for MipsISD::PCKEV. 3259 3260unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3261 if (RetVT.SimpleTy != MVT::v16i8) 3262 return 0; 3263 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3264 return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3265 } 3266 return 0; 3267} 3268 3269unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3270 if (RetVT.SimpleTy != MVT::v8i16) 3271 return 0; 3272 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3273 return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3274 } 3275 return 0; 3276} 3277 3278unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3279 if (RetVT.SimpleTy != MVT::v4i32) 3280 return 0; 3281 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3282 return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3283 } 3284 return 0; 3285} 3286 3287unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3288 if (RetVT.SimpleTy != MVT::v2i64) 3289 return 0; 3290 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3291 return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3292 } 3293 return 0; 3294} 3295 3296unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3297 switch (VT.SimpleTy) { 3298 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3299 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3300 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3301 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3302 default: return 0; 3303 } 3304} 3305 3306// FastEmit functions for MipsISD::PCKOD. 3307 3308unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3309 if (RetVT.SimpleTy != MVT::v16i8) 3310 return 0; 3311 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3312 return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3313 } 3314 return 0; 3315} 3316 3317unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3318 if (RetVT.SimpleTy != MVT::v8i16) 3319 return 0; 3320 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3321 return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3322 } 3323 return 0; 3324} 3325 3326unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3327 if (RetVT.SimpleTy != MVT::v4i32) 3328 return 0; 3329 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3330 return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3331 } 3332 return 0; 3333} 3334 3335unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3336 if (RetVT.SimpleTy != MVT::v2i64) 3337 return 0; 3338 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3339 return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3340 } 3341 return 0; 3342} 3343 3344unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3345 switch (VT.SimpleTy) { 3346 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3347 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3348 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3349 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3350 default: return 0; 3351 } 3352} 3353 3354// FastEmit functions for MipsISD::VNOR. 3355 3356unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3357 if (RetVT.SimpleTy != MVT::v16i8) 3358 return 0; 3359 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3360 return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3361 } 3362 return 0; 3363} 3364 3365unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3366 if (RetVT.SimpleTy != MVT::v8i16) 3367 return 0; 3368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3369 return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3370 } 3371 return 0; 3372} 3373 3374unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3375 if (RetVT.SimpleTy != MVT::v4i32) 3376 return 0; 3377 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3378 return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3379 } 3380 return 0; 3381} 3382 3383unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3384 if (RetVT.SimpleTy != MVT::v2i64) 3385 return 0; 3386 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3387 return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3388 } 3389 return 0; 3390} 3391 3392unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3393 switch (VT.SimpleTy) { 3394 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3395 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3396 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3397 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3398 default: return 0; 3399 } 3400} 3401 3402// Top-level FastEmit function. 3403 3404unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 3405 switch (Opcode) { 3406 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3407 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3408 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3409 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3410 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3411 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3412 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3413 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3414 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3415 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3416 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3417 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3418 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3419 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3420 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3421 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3422 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3423 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3424 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3425 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3426 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3427 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3428 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3429 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3430 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3431 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3432 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3433 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3434 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3435 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3436 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3437 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3438 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3439 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3440 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3441 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3442 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3443 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3444 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3445 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3446 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3447 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3448 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3449 default: return 0; 3450 } 3451} 3452 3453// FastEmit functions for MipsISD::ExtractElementF64. 3454 3455unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3456 if (RetVT.SimpleTy != MVT::i32) 3457 return 0; 3458 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) { 3459 return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3460 } 3461 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) { 3462 return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3463 } 3464 return 0; 3465} 3466 3467unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3468 switch (VT.SimpleTy) { 3469 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1); 3470 default: return 0; 3471 } 3472} 3473 3474// FastEmit functions for MipsISD::SHLL_DSP. 3475 3476unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3477 if (RetVT.SimpleTy != MVT::v4i8) 3478 return 0; 3479 if ((Subtarget->hasDSP())) { 3480 return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3481 } 3482 return 0; 3483} 3484 3485unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3486 if (RetVT.SimpleTy != MVT::v2i16) 3487 return 0; 3488 if ((Subtarget->hasDSP())) { 3489 return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3490 } 3491 return 0; 3492} 3493 3494unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3495 switch (VT.SimpleTy) { 3496 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3497 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3498 default: return 0; 3499 } 3500} 3501 3502// FastEmit functions for MipsISD::SHRA_DSP. 3503 3504unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3505 if (RetVT.SimpleTy != MVT::v4i8) 3506 return 0; 3507 if ((Subtarget->hasDSPR2())) { 3508 return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3509 } 3510 return 0; 3511} 3512 3513unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3514 if (RetVT.SimpleTy != MVT::v2i16) 3515 return 0; 3516 if ((Subtarget->hasDSP())) { 3517 return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3518 } 3519 return 0; 3520} 3521 3522unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3523 switch (VT.SimpleTy) { 3524 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3525 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3526 default: return 0; 3527 } 3528} 3529 3530// FastEmit functions for MipsISD::SHRL_DSP. 3531 3532unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3533 if (RetVT.SimpleTy != MVT::v4i8) 3534 return 0; 3535 if ((Subtarget->hasDSP())) { 3536 return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3537 } 3538 return 0; 3539} 3540 3541unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3542 if (RetVT.SimpleTy != MVT::v2i16) 3543 return 0; 3544 if ((Subtarget->hasDSPR2())) { 3545 return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3546 } 3547 return 0; 3548} 3549 3550unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3551 switch (VT.SimpleTy) { 3552 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3553 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3554 default: return 0; 3555 } 3556} 3557 3558// Top-level FastEmit function. 3559 3560unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override { 3561 if (VT == MVT::i32 && Predicate_immZExt5(imm1)) 3562 if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3563 return Reg; 3564 3565 if (VT == MVT::i32 && Predicate_immZExt6(imm1)) 3566 if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3567 return Reg; 3568 3569 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1)) 3570 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3571 return Reg; 3572 3573 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1)) 3574 if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3575 return Reg; 3576 3577 if (VT == MVT::i32 && Predicate_immZExt4(imm1)) 3578 if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3579 return Reg; 3580 3581 if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1)) 3582 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3583 return Reg; 3584 3585 if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1)) 3586 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3587 return Reg; 3588 3589 if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1)) 3590 if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3591 return Reg; 3592 3593 if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1)) 3594 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3595 return Reg; 3596 3597 switch (Opcode) { 3598 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3599 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3600 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3601 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3602 default: return 0; 3603 } 3604} 3605 3606// FastEmit functions for ISD::ROTR. 3607 3608unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3609 if (RetVT.SimpleTy != MVT::i32) 3610 return 0; 3611 if ((Subtarget->inMicroMipsMode())) { 3612 return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3613 } 3614 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3615 return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3616 } 3617 return 0; 3618} 3619 3620unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3621 switch (VT.SimpleTy) { 3622 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3623 default: return 0; 3624 } 3625} 3626 3627// FastEmit functions for ISD::SHL. 3628 3629unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3630 if (RetVT.SimpleTy != MVT::i32) 3631 return 0; 3632 if ((Subtarget->inMicroMipsMode())) { 3633 return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3634 } 3635 if ((Subtarget->inMips16Mode())) { 3636 return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3637 } 3638 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3639 return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3640 } 3641 return 0; 3642} 3643 3644unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3645 switch (VT.SimpleTy) { 3646 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3647 default: return 0; 3648 } 3649} 3650 3651// FastEmit functions for ISD::SRA. 3652 3653unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3654 if (RetVT.SimpleTy != MVT::i32) 3655 return 0; 3656 if ((Subtarget->inMicroMipsMode())) { 3657 return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3658 } 3659 if ((Subtarget->inMips16Mode())) { 3660 return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3661 } 3662 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3663 return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3664 } 3665 return 0; 3666} 3667 3668unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3669 switch (VT.SimpleTy) { 3670 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3671 default: return 0; 3672 } 3673} 3674 3675// FastEmit functions for ISD::SRL. 3676 3677unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3678 if (RetVT.SimpleTy != MVT::i32) 3679 return 0; 3680 if ((Subtarget->inMicroMipsMode())) { 3681 return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3682 } 3683 if ((Subtarget->inMips16Mode())) { 3684 return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3685 } 3686 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3687 return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3688 } 3689 return 0; 3690} 3691 3692unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3693 switch (VT.SimpleTy) { 3694 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3695 default: return 0; 3696 } 3697} 3698 3699// Top-level FastEmit function. 3700 3701unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3702 switch (Opcode) { 3703 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3704 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3705 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3706 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3707 default: return 0; 3708 } 3709} 3710 3711// FastEmit functions for ISD::ROTR. 3712 3713unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3714 if (RetVT.SimpleTy != MVT::i64) 3715 return 0; 3716 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3717 return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3718 } 3719 return 0; 3720} 3721 3722unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3723 switch (VT.SimpleTy) { 3724 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3725 default: return 0; 3726 } 3727} 3728 3729// FastEmit functions for ISD::SHL. 3730 3731unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3732 if (RetVT.SimpleTy != MVT::i64) 3733 return 0; 3734 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3735 return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3736 } 3737 return 0; 3738} 3739 3740unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3741 switch (VT.SimpleTy) { 3742 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3743 default: return 0; 3744 } 3745} 3746 3747// FastEmit functions for ISD::SRA. 3748 3749unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3750 if (RetVT.SimpleTy != MVT::i64) 3751 return 0; 3752 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3753 return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3754 } 3755 return 0; 3756} 3757 3758unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3759 switch (VT.SimpleTy) { 3760 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3761 default: return 0; 3762 } 3763} 3764 3765// FastEmit functions for ISD::SRL. 3766 3767unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3768 if (RetVT.SimpleTy != MVT::i64) 3769 return 0; 3770 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3771 return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3772 } 3773 return 0; 3774} 3775 3776unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3777 switch (VT.SimpleTy) { 3778 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3779 default: return 0; 3780 } 3781} 3782 3783// Top-level FastEmit function. 3784 3785unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3786 switch (Opcode) { 3787 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3788 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3789 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3790 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3791 default: return 0; 3792 } 3793} 3794 3795// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3796 3797unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3798 if (RetVT.SimpleTy != MVT::f32) 3799 return 0; 3800 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3801 return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1); 3802 } 3803 return 0; 3804} 3805 3806unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3807 switch (VT.SimpleTy) { 3808 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1); 3809 default: return 0; 3810 } 3811} 3812 3813// Top-level FastEmit function. 3814 3815unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3816 switch (Opcode) { 3817 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1); 3818 default: return 0; 3819 } 3820} 3821 3822// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3823 3824unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3825 if (RetVT.SimpleTy != MVT::f64) 3826 return 0; 3827 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3828 return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1); 3829 } 3830 return 0; 3831} 3832 3833unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3834 switch (VT.SimpleTy) { 3835 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1); 3836 default: return 0; 3837 } 3838} 3839 3840// Top-level FastEmit function. 3841 3842unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3843 switch (Opcode) { 3844 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1); 3845 default: return 0; 3846 } 3847} 3848 3849// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3850 3851unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3852 if (RetVT.SimpleTy != MVT::i32) 3853 return 0; 3854 if ((Subtarget->hasMSA())) { 3855 return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3856 } 3857 return 0; 3858} 3859 3860unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3861 switch (VT.SimpleTy) { 3862 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1); 3863 default: return 0; 3864 } 3865} 3866 3867// Top-level FastEmit function. 3868 3869unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3870 switch (Opcode) { 3871 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1); 3872 default: return 0; 3873 } 3874} 3875 3876// FastEmit functions for ISD::ADD. 3877 3878unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3879 if (RetVT.SimpleTy != MVT::i32) 3880 return 0; 3881 if ((Subtarget->inMicroMipsMode())) { 3882 return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3883 } 3884 return 0; 3885} 3886 3887unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3888 switch (VT.SimpleTy) { 3889 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1); 3890 default: return 0; 3891 } 3892} 3893 3894// Top-level FastEmit function. 3895 3896unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3897 switch (Opcode) { 3898 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1); 3899 default: return 0; 3900 } 3901} 3902 3903// FastEmit functions for ISD::ADD. 3904 3905unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3906 if (RetVT.SimpleTy != MVT::i32) 3907 return 0; 3908 if ((Subtarget->inMicroMipsMode())) { 3909 return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3910 } 3911 return 0; 3912} 3913 3914unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3915 switch (VT.SimpleTy) { 3916 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1); 3917 default: return 0; 3918 } 3919} 3920 3921// Top-level FastEmit function. 3922 3923unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3924 switch (Opcode) { 3925 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1); 3926 default: return 0; 3927 } 3928} 3929 3930// FastEmit functions for ISD::AND. 3931 3932unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3933 if (RetVT.SimpleTy != MVT::i32) 3934 return 0; 3935 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 3936 return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3937 } 3938 if ((Subtarget->inMicroMipsMode())) { 3939 return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3940 } 3941 return 0; 3942} 3943 3944unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3945 switch (VT.SimpleTy) { 3946 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1); 3947 default: return 0; 3948 } 3949} 3950 3951// Top-level FastEmit function. 3952 3953unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3954 switch (Opcode) { 3955 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1); 3956 default: return 0; 3957 } 3958} 3959 3960// FastEmit functions for ISD::SHL. 3961 3962unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3963 if (RetVT.SimpleTy != MVT::i32) 3964 return 0; 3965 if ((Subtarget->inMicroMipsMode())) { 3966 return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3967 } 3968 return 0; 3969} 3970 3971unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3972 switch (VT.SimpleTy) { 3973 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1); 3974 default: return 0; 3975 } 3976} 3977 3978// FastEmit functions for ISD::SRL. 3979 3980unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3981 if (RetVT.SimpleTy != MVT::i32) 3982 return 0; 3983 if ((Subtarget->inMicroMipsMode())) { 3984 return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3985 } 3986 return 0; 3987} 3988 3989unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3990 switch (VT.SimpleTy) { 3991 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1); 3992 default: return 0; 3993 } 3994} 3995 3996// Top-level FastEmit function. 3997 3998unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3999 switch (Opcode) { 4000 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1); 4001 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1); 4002 default: return 0; 4003 } 4004} 4005 4006// FastEmit functions for ISD::Constant. 4007 4008unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 4009 if (RetVT.SimpleTy != MVT::i32) 4010 return 0; 4011 if ((Subtarget->inMips16Mode())) { 4012 return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0); 4013 } 4014 return 0; 4015} 4016 4017unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 4018 switch (VT.SimpleTy) { 4019 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 4020 default: return 0; 4021 } 4022} 4023 4024// Top-level FastEmit function. 4025 4026unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 4027 switch (Opcode) { 4028 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 4029 default: return 0; 4030 } 4031} 4032 4033