1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(0), 241 UINT64_C(0), 242 UINT64_C(0), 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(0), 247 UINT64_C(0), 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(0), 251 UINT64_C(0), 252 UINT64_C(0), 253 UINT64_C(0), 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(0), 257 UINT64_C(0), 258 UINT64_C(0), 259 UINT64_C(0), 260 UINT64_C(0), 261 UINT64_C(0), 262 UINT64_C(0), 263 UINT64_C(0), 264 UINT64_C(0), 265 UINT64_C(0), 266 UINT64_C(0), 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(0), 270 UINT64_C(0), 271 UINT64_C(0), 272 UINT64_C(0), 273 UINT64_C(0), 274 UINT64_C(0), 275 UINT64_C(0), 276 UINT64_C(0), 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(0), 287 UINT64_C(0), 288 UINT64_C(0), 289 UINT64_C(0), 290 UINT64_C(0), 291 UINT64_C(0), 292 UINT64_C(0), 293 UINT64_C(0), 294 UINT64_C(0), 295 UINT64_C(0), 296 UINT64_C(0), 297 UINT64_C(0), 298 UINT64_C(0), 299 UINT64_C(0), 300 UINT64_C(0), 301 UINT64_C(0), 302 UINT64_C(0), 303 UINT64_C(0), 304 UINT64_C(0), 305 UINT64_C(0), 306 UINT64_C(0), 307 UINT64_C(0), 308 UINT64_C(0), 309 UINT64_C(0), 310 UINT64_C(0), 311 UINT64_C(0), 312 UINT64_C(0), 313 UINT64_C(0), 314 UINT64_C(0), 315 UINT64_C(0), 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(0), 324 UINT64_C(0), 325 UINT64_C(0), 326 UINT64_C(0), 327 UINT64_C(0), 328 UINT64_C(0), 329 UINT64_C(0), 330 UINT64_C(0), 331 UINT64_C(0), 332 UINT64_C(0), 333 UINT64_C(0), 334 UINT64_C(0), 335 UINT64_C(0), 336 UINT64_C(0), 337 UINT64_C(0), 338 UINT64_C(0), 339 UINT64_C(0), 340 UINT64_C(0), 341 UINT64_C(0), 342 UINT64_C(0), 343 UINT64_C(0), 344 UINT64_C(0), 345 UINT64_C(0), 346 UINT64_C(0), 347 UINT64_C(0), 348 UINT64_C(0), 349 UINT64_C(0), 350 UINT64_C(0), 351 UINT64_C(0), 352 UINT64_C(0), 353 UINT64_C(0), 354 UINT64_C(0), 355 UINT64_C(0), 356 UINT64_C(0), 357 UINT64_C(0), 358 UINT64_C(0), 359 UINT64_C(0), 360 UINT64_C(0), 361 UINT64_C(0), 362 UINT64_C(0), 363 UINT64_C(0), 364 UINT64_C(0), 365 UINT64_C(0), 366 UINT64_C(0), 367 UINT64_C(0), 368 UINT64_C(0), 369 UINT64_C(0), 370 UINT64_C(0), 371 UINT64_C(0), 372 UINT64_C(0), 373 UINT64_C(0), 374 UINT64_C(0), 375 UINT64_C(0), 376 UINT64_C(0), 377 UINT64_C(0), 378 UINT64_C(0), 379 UINT64_C(0), 380 UINT64_C(0), 381 UINT64_C(0), 382 UINT64_C(0), 383 UINT64_C(0), 384 UINT64_C(0), 385 UINT64_C(0), 386 UINT64_C(0), 387 UINT64_C(0), 388 UINT64_C(0), 389 UINT64_C(0), 390 UINT64_C(0), 391 UINT64_C(0), 392 UINT64_C(0), 393 UINT64_C(0), 394 UINT64_C(0), 395 UINT64_C(0), 396 UINT64_C(0), 397 UINT64_C(0), 398 UINT64_C(0), 399 UINT64_C(0), 400 UINT64_C(0), 401 UINT64_C(0), 402 UINT64_C(0), 403 UINT64_C(0), 404 UINT64_C(0), 405 UINT64_C(0), 406 UINT64_C(0), 407 UINT64_C(0), 408 UINT64_C(0), 409 UINT64_C(0), 410 UINT64_C(0), 411 UINT64_C(0), 412 UINT64_C(0), 413 UINT64_C(0), 414 UINT64_C(0), 415 UINT64_C(0), 416 UINT64_C(0), 417 UINT64_C(0), 418 UINT64_C(0), 419 UINT64_C(0), 420 UINT64_C(0), 421 UINT64_C(0), 422 UINT64_C(0), 423 UINT64_C(0), 424 UINT64_C(0), 425 UINT64_C(0), 426 UINT64_C(0), 427 UINT64_C(0), 428 UINT64_C(0), 429 UINT64_C(0), 430 UINT64_C(0), 431 UINT64_C(0), 432 UINT64_C(0), 433 UINT64_C(0), 434 UINT64_C(0), 435 UINT64_C(0), 436 UINT64_C(0), 437 UINT64_C(0), 438 UINT64_C(0), 439 UINT64_C(0), 440 UINT64_C(0), 441 UINT64_C(0), 442 UINT64_C(0), 443 UINT64_C(0), 444 UINT64_C(0), 445 UINT64_C(0), 446 UINT64_C(0), 447 UINT64_C(0), 448 UINT64_C(0), 449 UINT64_C(0), 450 UINT64_C(0), 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(0), 454 UINT64_C(0), 455 UINT64_C(0), 456 UINT64_C(0), 457 UINT64_C(0), 458 UINT64_C(0), 459 UINT64_C(0), 460 UINT64_C(0), 461 UINT64_C(0), 462 UINT64_C(0), 463 UINT64_C(0), 464 UINT64_C(0), 465 UINT64_C(0), 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(0), 469 UINT64_C(0), 470 UINT64_C(0), 471 UINT64_C(0), 472 UINT64_C(0), 473 UINT64_C(0), 474 UINT64_C(0), 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(0), 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(0), 484 UINT64_C(0), 485 UINT64_C(0), 486 UINT64_C(0), 487 UINT64_C(0), 488 UINT64_C(0), 489 UINT64_C(0), 490 UINT64_C(0), 491 UINT64_C(0), 492 UINT64_C(0), 493 UINT64_C(0), 494 UINT64_C(0), 495 UINT64_C(0), 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(0), 501 UINT64_C(0), 502 UINT64_C(0), 503 UINT64_C(0), 504 UINT64_C(0), 505 UINT64_C(0), 506 UINT64_C(0), 507 UINT64_C(0), 508 UINT64_C(0), 509 UINT64_C(0), 510 UINT64_C(0), 511 UINT64_C(0), 512 UINT64_C(0), 513 UINT64_C(0), 514 UINT64_C(0), 515 UINT64_C(0), 516 UINT64_C(0), 517 UINT64_C(0), 518 UINT64_C(0), 519 UINT64_C(0), 520 UINT64_C(0), 521 UINT64_C(0), 522 UINT64_C(0), 523 UINT64_C(0), 524 UINT64_C(0), 525 UINT64_C(0), 526 UINT64_C(0), 527 UINT64_C(0), 528 UINT64_C(0), 529 UINT64_C(0), 530 UINT64_C(0), 531 UINT64_C(0), 532 UINT64_C(0), 533 UINT64_C(0), 534 UINT64_C(0), 535 UINT64_C(0), 536 UINT64_C(0), 537 UINT64_C(0), 538 UINT64_C(0), 539 UINT64_C(0), 540 UINT64_C(0), 541 UINT64_C(0), 542 UINT64_C(0), 543 UINT64_C(0), 544 UINT64_C(0), 545 UINT64_C(0), 546 UINT64_C(0), 547 UINT64_C(0), 548 UINT64_C(0), 549 UINT64_C(0), 550 UINT64_C(0), 551 UINT64_C(0), 552 UINT64_C(0), 553 UINT64_C(0), 554 UINT64_C(0), 555 UINT64_C(0), 556 UINT64_C(0), 557 UINT64_C(0), 558 UINT64_C(0), 559 UINT64_C(0), 560 UINT64_C(0), 561 UINT64_C(0), 562 UINT64_C(0), 563 UINT64_C(0), 564 UINT64_C(0), 565 UINT64_C(0), 566 UINT64_C(0), 567 UINT64_C(0), 568 UINT64_C(0), 569 UINT64_C(0), 570 UINT64_C(0), 571 UINT64_C(0), 572 UINT64_C(0), 573 UINT64_C(0), 574 UINT64_C(0), 575 UINT64_C(0), 576 UINT64_C(0), 577 UINT64_C(0), 578 UINT64_C(0), 579 UINT64_C(0), 580 UINT64_C(0), 581 UINT64_C(0), 582 UINT64_C(0), 583 UINT64_C(0), 584 UINT64_C(0), 585 UINT64_C(0), 586 UINT64_C(0), 587 UINT64_C(0), 588 UINT64_C(0), 589 UINT64_C(0), 590 UINT64_C(0), 591 UINT64_C(0), 592 UINT64_C(0), 593 UINT64_C(0), 594 UINT64_C(0), 595 UINT64_C(0), 596 UINT64_C(0), 597 UINT64_C(0), 598 UINT64_C(0), 599 UINT64_C(0), 600 UINT64_C(0), 601 UINT64_C(0), 602 UINT64_C(0), 603 UINT64_C(0), 604 UINT64_C(0), 605 UINT64_C(0), 606 UINT64_C(0), 607 UINT64_C(0), 608 UINT64_C(0), 609 UINT64_C(0), 610 UINT64_C(0), 611 UINT64_C(0), 612 UINT64_C(0), 613 UINT64_C(0), 614 UINT64_C(0), 615 UINT64_C(0), 616 UINT64_C(0), 617 UINT64_C(0), 618 UINT64_C(0), 619 UINT64_C(0), 620 UINT64_C(0), 621 UINT64_C(0), 622 UINT64_C(0), 623 UINT64_C(0), 624 UINT64_C(0), 625 UINT64_C(0), 626 UINT64_C(0), 627 UINT64_C(0), 628 UINT64_C(0), 629 UINT64_C(0), 630 UINT64_C(0), 631 UINT64_C(0), 632 UINT64_C(0), 633 UINT64_C(0), 634 UINT64_C(0), 635 UINT64_C(0), 636 UINT64_C(2080375378), // ABSQ_S_PH 637 UINT64_C(4412), // ABSQ_S_PH_MM 638 UINT64_C(2080374866), // ABSQ_S_QB 639 UINT64_C(316), // ABSQ_S_QB_MMR2 640 UINT64_C(2080375890), // ABSQ_S_W 641 UINT64_C(8508), // ABSQ_S_W_MM 642 UINT64_C(32), // ADD 643 UINT64_C(3959422976), // ADDIUPC 644 UINT64_C(2013265920), // ADDIUPC_MM 645 UINT64_C(2013265920), // ADDIUPC_MMR6 646 UINT64_C(27649), // ADDIUR1SP_MM 647 UINT64_C(27648), // ADDIUR2_MM 648 UINT64_C(19456), // ADDIUS5_MM 649 UINT64_C(19457), // ADDIUSP_MM 650 UINT64_C(805306368), // ADDIU_MMR6 651 UINT64_C(2080375320), // ADDQH_PH 652 UINT64_C(77), // ADDQH_PH_MMR2 653 UINT64_C(2080375448), // ADDQH_R_PH 654 UINT64_C(1101), // ADDQH_R_PH_MMR2 655 UINT64_C(2080375960), // ADDQH_R_W 656 UINT64_C(1165), // ADDQH_R_W_MMR2 657 UINT64_C(2080375832), // ADDQH_W 658 UINT64_C(141), // ADDQH_W_MMR2 659 UINT64_C(2080375440), // ADDQ_PH 660 UINT64_C(13), // ADDQ_PH_MM 661 UINT64_C(2080375696), // ADDQ_S_PH 662 UINT64_C(1037), // ADDQ_S_PH_MM 663 UINT64_C(2080376208), // ADDQ_S_W 664 UINT64_C(773), // ADDQ_S_W_MM 665 UINT64_C(2080375824), // ADDSC 666 UINT64_C(901), // ADDSC_MM 667 UINT64_C(2021654544), // ADDS_A_B 668 UINT64_C(2027946000), // ADDS_A_D 669 UINT64_C(2023751696), // ADDS_A_H 670 UINT64_C(2025848848), // ADDS_A_W 671 UINT64_C(2030043152), // ADDS_S_B 672 UINT64_C(2036334608), // ADDS_S_D 673 UINT64_C(2032140304), // ADDS_S_H 674 UINT64_C(2034237456), // ADDS_S_W 675 UINT64_C(2038431760), // ADDS_U_B 676 UINT64_C(2044723216), // ADDS_U_D 677 UINT64_C(2040528912), // ADDS_U_H 678 UINT64_C(2042626064), // ADDS_U_W 679 UINT64_C(1024), // ADDU16_MM 680 UINT64_C(1024), // ADDU16_MMR6 681 UINT64_C(2080374808), // ADDUH_QB 682 UINT64_C(333), // ADDUH_QB_MMR2 683 UINT64_C(2080374936), // ADDUH_R_QB 684 UINT64_C(1357), // ADDUH_R_QB_MMR2 685 UINT64_C(336), // ADDU_MMR6 686 UINT64_C(2080375312), // ADDU_PH 687 UINT64_C(269), // ADDU_PH_MMR2 688 UINT64_C(2080374800), // ADDU_QB 689 UINT64_C(205), // ADDU_QB_MM 690 UINT64_C(2080375568), // ADDU_S_PH 691 UINT64_C(1293), // ADDU_S_PH_MMR2 692 UINT64_C(2080375056), // ADDU_S_QB 693 UINT64_C(1229), // ADDU_S_QB_MM 694 UINT64_C(2013265926), // ADDVI_B 695 UINT64_C(2019557382), // ADDVI_D 696 UINT64_C(2015363078), // ADDVI_H 697 UINT64_C(2017460230), // ADDVI_W 698 UINT64_C(2013265934), // ADDV_B 699 UINT64_C(2019557390), // ADDV_D 700 UINT64_C(2015363086), // ADDV_H 701 UINT64_C(2017460238), // ADDV_W 702 UINT64_C(2080375888), // ADDWC 703 UINT64_C(965), // ADDWC_MM 704 UINT64_C(2013265936), // ADD_A_B 705 UINT64_C(2019557392), // ADD_A_D 706 UINT64_C(2015363088), // ADD_A_H 707 UINT64_C(2017460240), // ADD_A_W 708 UINT64_C(272), // ADD_MM 709 UINT64_C(272), // ADD_MMR6 710 UINT64_C(536870912), // ADDi 711 UINT64_C(268435456), // ADDi_MM 712 UINT64_C(603979776), // ADDiu 713 UINT64_C(805306368), // ADDiu_MM 714 UINT64_C(33), // ADDu 715 UINT64_C(336), // ADDu_MM 716 UINT64_C(2080375328), // ALIGN 717 UINT64_C(31), // ALIGN_MMR6 718 UINT64_C(3961454592), // ALUIPC 719 UINT64_C(2015297536), // ALUIPC_MMR6 720 UINT64_C(36), // AND 721 UINT64_C(17536), // AND16_MM 722 UINT64_C(17409), // AND16_MMR6 723 UINT64_C(36), // AND64 724 UINT64_C(11264), // ANDI16_MM 725 UINT64_C(11264), // ANDI16_MMR6 726 UINT64_C(2013265920), // ANDI_B 727 UINT64_C(3489660928), // ANDI_MMR6 728 UINT64_C(592), // AND_MM 729 UINT64_C(592), // AND_MMR6 730 UINT64_C(2013265950), // AND_V 731 UINT64_C(805306368), // ANDi 732 UINT64_C(805306368), // ANDi64 733 UINT64_C(3489660928), // ANDi_MM 734 UINT64_C(2080374833), // APPEND 735 UINT64_C(533), // APPEND_MMR2 736 UINT64_C(2046820369), // ASUB_S_B 737 UINT64_C(2053111825), // ASUB_S_D 738 UINT64_C(2048917521), // ASUB_S_H 739 UINT64_C(2051014673), // ASUB_S_W 740 UINT64_C(2055208977), // ASUB_U_B 741 UINT64_C(2061500433), // ASUB_U_D 742 UINT64_C(2057306129), // ASUB_U_H 743 UINT64_C(2059403281), // ASUB_U_W 744 UINT64_C(1006632960), // AUI 745 UINT64_C(3961389056), // AUIPC 746 UINT64_C(2015232000), // AUIPC_MMR6 747 UINT64_C(268435456), // AUI_MMR6 748 UINT64_C(2063597584), // AVER_S_B 749 UINT64_C(2069889040), // AVER_S_D 750 UINT64_C(2065694736), // AVER_S_H 751 UINT64_C(2067791888), // AVER_S_W 752 UINT64_C(2071986192), // AVER_U_B 753 UINT64_C(2078277648), // AVER_U_D 754 UINT64_C(2074083344), // AVER_U_H 755 UINT64_C(2076180496), // AVER_U_W 756 UINT64_C(2046820368), // AVE_S_B 757 UINT64_C(2053111824), // AVE_S_D 758 UINT64_C(2048917520), // AVE_S_H 759 UINT64_C(2051014672), // AVE_S_W 760 UINT64_C(2055208976), // AVE_U_B 761 UINT64_C(2061500432), // AVE_U_D 762 UINT64_C(2057306128), // AVE_U_H 763 UINT64_C(2059403280), // AVE_U_W 764 UINT64_C(4026550272), // AddiuRxImmX16 765 UINT64_C(4026533888), // AddiuRxPcImmX16 766 UINT64_C(18432), // AddiuRxRxImm16 767 UINT64_C(4026550272), // AddiuRxRxImmX16 768 UINT64_C(4026548224), // AddiuRxRyOffMemX16 769 UINT64_C(25344), // AddiuSpImm16 770 UINT64_C(4026544896), // AddiuSpImmX16 771 UINT64_C(57345), // AdduRxRyRz16 772 UINT64_C(59404), // AndRxRxRy16 773 UINT64_C(52224), // B16_MM 774 UINT64_C(1879048232), // BADDu 775 UINT64_C(68222976), // BAL 776 UINT64_C(3892314112), // BALC 777 UINT64_C(3019898880), // BALC_MMR6 778 UINT64_C(2080375857), // BALIGN 779 UINT64_C(2236), // BALIGN_MMR2 780 UINT64_C(3355443200), // BBIT0 781 UINT64_C(3623878656), // BBIT032 782 UINT64_C(3892314112), // BBIT1 783 UINT64_C(4160749568), // BBIT132 784 UINT64_C(3355443200), // BC 785 UINT64_C(52224), // BC16_MMR6 786 UINT64_C(1159725056), // BC1EQZ 787 UINT64_C(1090519040), // BC1EQZC_MMR6 788 UINT64_C(1157627904), // BC1F 789 UINT64_C(1157758976), // BC1FL 790 UINT64_C(1132462080), // BC1F_MM 791 UINT64_C(1168113664), // BC1NEZ 792 UINT64_C(1092616192), // BC1NEZC_MMR6 793 UINT64_C(1157693440), // BC1T 794 UINT64_C(1157824512), // BC1TL 795 UINT64_C(1134559232), // BC1T_MM 796 UINT64_C(1226833920), // BC2EQZ 797 UINT64_C(1094713344), // BC2EQZC_MMR6 798 UINT64_C(1235222528), // BC2NEZ 799 UINT64_C(1096810496), // BC2NEZC_MMR6 800 UINT64_C(2045771785), // BCLRI_B 801 UINT64_C(2038431753), // BCLRI_D 802 UINT64_C(2044723209), // BCLRI_H 803 UINT64_C(2042626057), // BCLRI_W 804 UINT64_C(2038431757), // BCLR_B 805 UINT64_C(2044723213), // BCLR_D 806 UINT64_C(2040528909), // BCLR_H 807 UINT64_C(2042626061), // BCLR_W 808 UINT64_C(2483027968), // BC_MMR6 809 UINT64_C(268435456), // BEQ 810 UINT64_C(268435456), // BEQ64 811 UINT64_C(536870912), // BEQC 812 UINT64_C(536870912), // BEQC64 813 UINT64_C(1946157056), // BEQC_MMR6 814 UINT64_C(1342177280), // BEQL 815 UINT64_C(35840), // BEQZ16_MM 816 UINT64_C(536870912), // BEQZALC 817 UINT64_C(1946157056), // BEQZALC_MMR6 818 UINT64_C(3623878656), // BEQZC 819 UINT64_C(35840), // BEQZC16_MMR6 820 UINT64_C(3623878656), // BEQZC64 821 UINT64_C(1088421888), // BEQZC_MM 822 UINT64_C(2147483648), // BEQZC_MMR6 823 UINT64_C(2483027968), // BEQ_MM 824 UINT64_C(1476395008), // BGEC 825 UINT64_C(1476395008), // BGEC64 826 UINT64_C(4093640704), // BGEC_MMR6 827 UINT64_C(402653184), // BGEUC 828 UINT64_C(402653184), // BGEUC64 829 UINT64_C(3221225472), // BGEUC_MMR6 830 UINT64_C(67174400), // BGEZ 831 UINT64_C(67174400), // BGEZ64 832 UINT64_C(68222976), // BGEZAL 833 UINT64_C(402653184), // BGEZALC 834 UINT64_C(3221225472), // BGEZALC_MMR6 835 UINT64_C(68354048), // BGEZALL 836 UINT64_C(1113587712), // BGEZALS_MM 837 UINT64_C(1080033280), // BGEZAL_MM 838 UINT64_C(1476395008), // BGEZC 839 UINT64_C(1476395008), // BGEZC64 840 UINT64_C(4093640704), // BGEZC_MMR6 841 UINT64_C(67305472), // BGEZL 842 UINT64_C(1077936128), // BGEZ_MM 843 UINT64_C(469762048), // BGTZ 844 UINT64_C(469762048), // BGTZ64 845 UINT64_C(469762048), // BGTZALC 846 UINT64_C(3758096384), // BGTZALC_MMR6 847 UINT64_C(1543503872), // BGTZC 848 UINT64_C(1543503872), // BGTZC64 849 UINT64_C(3556769792), // BGTZC_MMR6 850 UINT64_C(1543503872), // BGTZL 851 UINT64_C(1086324736), // BGTZ_MM 852 UINT64_C(2070937609), // BINSLI_B 853 UINT64_C(2063597577), // BINSLI_D 854 UINT64_C(2069889033), // BINSLI_H 855 UINT64_C(2067791881), // BINSLI_W 856 UINT64_C(2063597581), // BINSL_B 857 UINT64_C(2069889037), // BINSL_D 858 UINT64_C(2065694733), // BINSL_H 859 UINT64_C(2067791885), // BINSL_W 860 UINT64_C(2079326217), // BINSRI_B 861 UINT64_C(2071986185), // BINSRI_D 862 UINT64_C(2078277641), // BINSRI_H 863 UINT64_C(2076180489), // BINSRI_W 864 UINT64_C(2071986189), // BINSR_B 865 UINT64_C(2078277645), // BINSR_D 866 UINT64_C(2074083341), // BINSR_H 867 UINT64_C(2076180493), // BINSR_W 868 UINT64_C(2080376530), // BITREV 869 UINT64_C(12604), // BITREV_MM 870 UINT64_C(2080374816), // BITSWAP 871 UINT64_C(2876), // BITSWAP_MMR6 872 UINT64_C(402653184), // BLEZ 873 UINT64_C(402653184), // BLEZ64 874 UINT64_C(402653184), // BLEZALC 875 UINT64_C(3221225472), // BLEZALC_MMR6 876 UINT64_C(1476395008), // BLEZC 877 UINT64_C(1476395008), // BLEZC64 878 UINT64_C(4093640704), // BLEZC_MMR6 879 UINT64_C(1476395008), // BLEZL 880 UINT64_C(1082130432), // BLEZ_MM 881 UINT64_C(1543503872), // BLTC 882 UINT64_C(1543503872), // BLTC64 883 UINT64_C(3556769792), // BLTC_MMR6 884 UINT64_C(469762048), // BLTUC 885 UINT64_C(469762048), // BLTUC64 886 UINT64_C(3758096384), // BLTUC_MMR6 887 UINT64_C(67108864), // BLTZ 888 UINT64_C(67108864), // BLTZ64 889 UINT64_C(68157440), // BLTZAL 890 UINT64_C(469762048), // BLTZALC 891 UINT64_C(3758096384), // BLTZALC_MMR6 892 UINT64_C(68288512), // BLTZALL 893 UINT64_C(1109393408), // BLTZALS_MM 894 UINT64_C(1075838976), // BLTZAL_MM 895 UINT64_C(1543503872), // BLTZC 896 UINT64_C(1543503872), // BLTZC64 897 UINT64_C(3556769792), // BLTZC_MMR6 898 UINT64_C(67239936), // BLTZL 899 UINT64_C(1073741824), // BLTZ_MM 900 UINT64_C(2013265921), // BMNZI_B 901 UINT64_C(2021654558), // BMNZ_V 902 UINT64_C(2030043137), // BMZI_B 903 UINT64_C(2023751710), // BMZ_V 904 UINT64_C(335544320), // BNE 905 UINT64_C(335544320), // BNE64 906 UINT64_C(1610612736), // BNEC 907 UINT64_C(1610612736), // BNEC64 908 UINT64_C(2080374784), // BNEC_MMR6 909 UINT64_C(2062549001), // BNEGI_B 910 UINT64_C(2055208969), // BNEGI_D 911 UINT64_C(2061500425), // BNEGI_H 912 UINT64_C(2059403273), // BNEGI_W 913 UINT64_C(2055208973), // BNEG_B 914 UINT64_C(2061500429), // BNEG_D 915 UINT64_C(2057306125), // BNEG_H 916 UINT64_C(2059403277), // BNEG_W 917 UINT64_C(1409286144), // BNEL 918 UINT64_C(44032), // BNEZ16_MM 919 UINT64_C(1610612736), // BNEZALC 920 UINT64_C(2080374784), // BNEZALC_MMR6 921 UINT64_C(4160749568), // BNEZC 922 UINT64_C(44032), // BNEZC16_MMR6 923 UINT64_C(4160749568), // BNEZC64 924 UINT64_C(1084227584), // BNEZC_MM 925 UINT64_C(2684354560), // BNEZC_MMR6 926 UINT64_C(3019898880), // BNE_MM 927 UINT64_C(1610612736), // BNVC 928 UINT64_C(2080374784), // BNVC_MMR6 929 UINT64_C(1199570944), // BNZ_B 930 UINT64_C(1205862400), // BNZ_D 931 UINT64_C(1201668096), // BNZ_H 932 UINT64_C(1172307968), // BNZ_V 933 UINT64_C(1203765248), // BNZ_W 934 UINT64_C(536870912), // BOVC 935 UINT64_C(1946157056), // BOVC_MMR6 936 UINT64_C(68943872), // BPOSGE32 937 UINT64_C(1126170624), // BPOSGE32C_MMR3 938 UINT64_C(1130364928), // BPOSGE32_MM 939 UINT64_C(13), // BREAK 940 UINT64_C(18048), // BREAK16_MM 941 UINT64_C(17435), // BREAK16_MMR6 942 UINT64_C(7), // BREAK_MM 943 UINT64_C(7), // BREAK_MMR6 944 UINT64_C(2046820353), // BSELI_B 945 UINT64_C(2025848862), // BSEL_V 946 UINT64_C(2054160393), // BSETI_B 947 UINT64_C(2046820361), // BSETI_D 948 UINT64_C(2053111817), // BSETI_H 949 UINT64_C(2051014665), // BSETI_W 950 UINT64_C(2046820365), // BSET_B 951 UINT64_C(2053111821), // BSET_D 952 UINT64_C(2048917517), // BSET_H 953 UINT64_C(2051014669), // BSET_W 954 UINT64_C(1191182336), // BZ_B 955 UINT64_C(1197473792), // BZ_D 956 UINT64_C(1193279488), // BZ_H 957 UINT64_C(1163919360), // BZ_V 958 UINT64_C(1195376640), // BZ_W 959 UINT64_C(8192), // BeqzRxImm16 960 UINT64_C(4026540032), // BeqzRxImmX16 961 UINT64_C(4096), // Bimm16 962 UINT64_C(4026535936), // BimmX16 963 UINT64_C(10240), // BnezRxImm16 964 UINT64_C(4026542080), // BnezRxImmX16 965 UINT64_C(59397), // Break16 966 UINT64_C(24576), // Bteqz16 967 UINT64_C(4026544128), // BteqzX16 968 UINT64_C(24832), // Btnez16 969 UINT64_C(4026544384), // BtnezX16 970 UINT64_C(3154116608), // CACHE 971 UINT64_C(2080374811), // CACHEE 972 UINT64_C(1610655232), // CACHEE_MM 973 UINT64_C(536895488), // CACHE_MM 974 UINT64_C(536895488), // CACHE_MMR6 975 UINT64_C(2080374821), // CACHE_R6 976 UINT64_C(1176502282), // CEIL_L_D64 977 UINT64_C(1409307451), // CEIL_L_D_MMR6 978 UINT64_C(1174405130), // CEIL_L_S 979 UINT64_C(1409291067), // CEIL_L_S_MMR6 980 UINT64_C(1176502286), // CEIL_W_D32 981 UINT64_C(1176502286), // CEIL_W_D64 982 UINT64_C(1409309499), // CEIL_W_D_MMR6 983 UINT64_C(1409309499), // CEIL_W_MM 984 UINT64_C(1174405134), // CEIL_W_S 985 UINT64_C(1409293115), // CEIL_W_S_MM 986 UINT64_C(1409293115), // CEIL_W_S_MMR6 987 UINT64_C(2013265927), // CEQI_B 988 UINT64_C(2019557383), // CEQI_D 989 UINT64_C(2015363079), // CEQI_H 990 UINT64_C(2017460231), // CEQI_W 991 UINT64_C(2013265935), // CEQ_B 992 UINT64_C(2019557391), // CEQ_D 993 UINT64_C(2015363087), // CEQ_H 994 UINT64_C(2017460239), // CEQ_W 995 UINT64_C(1145044992), // CFC1 996 UINT64_C(1409290299), // CFC1_MM 997 UINT64_C(52540), // CFC2_MM 998 UINT64_C(2021523481), // CFCMSA 999 UINT64_C(1879048242), // CINS 1000 UINT64_C(1879048243), // CINS32 1001 UINT64_C(1879048242), // CINS64_32 1002 UINT64_C(1879048242), // CINS_i32 1003 UINT64_C(1176502299), // CLASS_D 1004 UINT64_C(1409286752), // CLASS_D_MMR6 1005 UINT64_C(1174405147), // CLASS_S 1006 UINT64_C(1409286240), // CLASS_S_MMR6 1007 UINT64_C(2046820359), // CLEI_S_B 1008 UINT64_C(2053111815), // CLEI_S_D 1009 UINT64_C(2048917511), // CLEI_S_H 1010 UINT64_C(2051014663), // CLEI_S_W 1011 UINT64_C(2055208967), // CLEI_U_B 1012 UINT64_C(2061500423), // CLEI_U_D 1013 UINT64_C(2057306119), // CLEI_U_H 1014 UINT64_C(2059403271), // CLEI_U_W 1015 UINT64_C(2046820367), // CLE_S_B 1016 UINT64_C(2053111823), // CLE_S_D 1017 UINT64_C(2048917519), // CLE_S_H 1018 UINT64_C(2051014671), // CLE_S_W 1019 UINT64_C(2055208975), // CLE_U_B 1020 UINT64_C(2061500431), // CLE_U_D 1021 UINT64_C(2057306127), // CLE_U_H 1022 UINT64_C(2059403279), // CLE_U_W 1023 UINT64_C(1879048225), // CLO 1024 UINT64_C(19260), // CLO_MM 1025 UINT64_C(19260), // CLO_MMR6 1026 UINT64_C(81), // CLO_R6 1027 UINT64_C(2030043143), // CLTI_S_B 1028 UINT64_C(2036334599), // CLTI_S_D 1029 UINT64_C(2032140295), // CLTI_S_H 1030 UINT64_C(2034237447), // CLTI_S_W 1031 UINT64_C(2038431751), // CLTI_U_B 1032 UINT64_C(2044723207), // CLTI_U_D 1033 UINT64_C(2040528903), // CLTI_U_H 1034 UINT64_C(2042626055), // CLTI_U_W 1035 UINT64_C(2030043151), // CLT_S_B 1036 UINT64_C(2036334607), // CLT_S_D 1037 UINT64_C(2032140303), // CLT_S_H 1038 UINT64_C(2034237455), // CLT_S_W 1039 UINT64_C(2038431759), // CLT_U_B 1040 UINT64_C(2044723215), // CLT_U_D 1041 UINT64_C(2040528911), // CLT_U_H 1042 UINT64_C(2042626063), // CLT_U_W 1043 UINT64_C(1879048224), // CLZ 1044 UINT64_C(23356), // CLZ_MM 1045 UINT64_C(80), // CLZ_MMR6 1046 UINT64_C(80), // CLZ_R6 1047 UINT64_C(2080376337), // CMPGDU_EQ_QB 1048 UINT64_C(389), // CMPGDU_EQ_QB_MMR2 1049 UINT64_C(2080376465), // CMPGDU_LE_QB 1050 UINT64_C(517), // CMPGDU_LE_QB_MMR2 1051 UINT64_C(2080376401), // CMPGDU_LT_QB 1052 UINT64_C(453), // CMPGDU_LT_QB_MMR2 1053 UINT64_C(2080375057), // CMPGU_EQ_QB 1054 UINT64_C(1476395205), // CMPGU_EQ_QB_MM 1055 UINT64_C(2080375185), // CMPGU_LE_QB 1056 UINT64_C(1476395333), // CMPGU_LE_QB_MM 1057 UINT64_C(2080375121), // CMPGU_LT_QB 1058 UINT64_C(1476395269), // CMPGU_LT_QB_MM 1059 UINT64_C(2080374801), // CMPU_EQ_QB 1060 UINT64_C(581), // CMPU_EQ_QB_MM 1061 UINT64_C(2080374929), // CMPU_LE_QB 1062 UINT64_C(709), // CMPU_LE_QB_MM 1063 UINT64_C(2080374865), // CMPU_LT_QB 1064 UINT64_C(645), // CMPU_LT_QB_MM 1065 UINT64_C(1409286165), // CMP_AF_D_MMR6 1066 UINT64_C(1409286149), // CMP_AF_S_MMR6 1067 UINT64_C(1184890882), // CMP_EQ_D 1068 UINT64_C(1409286293), // CMP_EQ_D_MMR6 1069 UINT64_C(2080375313), // CMP_EQ_PH 1070 UINT64_C(5), // CMP_EQ_PH_MM 1071 UINT64_C(1182793730), // CMP_EQ_S 1072 UINT64_C(1409286277), // CMP_EQ_S_MMR6 1073 UINT64_C(1184890880), // CMP_F_D 1074 UINT64_C(1182793728), // CMP_F_S 1075 UINT64_C(1184890886), // CMP_LE_D 1076 UINT64_C(1409286549), // CMP_LE_D_MMR6 1077 UINT64_C(2080375441), // CMP_LE_PH 1078 UINT64_C(133), // CMP_LE_PH_MM 1079 UINT64_C(1182793734), // CMP_LE_S 1080 UINT64_C(1409286533), // CMP_LE_S_MMR6 1081 UINT64_C(1184890884), // CMP_LT_D 1082 UINT64_C(1409286421), // CMP_LT_D_MMR6 1083 UINT64_C(2080375377), // CMP_LT_PH 1084 UINT64_C(69), // CMP_LT_PH_MM 1085 UINT64_C(1182793732), // CMP_LT_S 1086 UINT64_C(1409286405), // CMP_LT_S_MMR6 1087 UINT64_C(1184890888), // CMP_SAF_D 1088 UINT64_C(1409286677), // CMP_SAF_D_MMR6 1089 UINT64_C(1182793736), // CMP_SAF_S 1090 UINT64_C(1409286661), // CMP_SAF_S_MMR6 1091 UINT64_C(1184890890), // CMP_SEQ_D 1092 UINT64_C(1409286805), // CMP_SEQ_D_MMR6 1093 UINT64_C(1182793738), // CMP_SEQ_S 1094 UINT64_C(1409286789), // CMP_SEQ_S_MMR6 1095 UINT64_C(1184890894), // CMP_SLE_D 1096 UINT64_C(1409287061), // CMP_SLE_D_MMR6 1097 UINT64_C(1182793742), // CMP_SLE_S 1098 UINT64_C(1409287045), // CMP_SLE_S_MMR6 1099 UINT64_C(1184890892), // CMP_SLT_D 1100 UINT64_C(1409286933), // CMP_SLT_D_MMR6 1101 UINT64_C(1182793740), // CMP_SLT_S 1102 UINT64_C(1409286917), // CMP_SLT_S_MMR6 1103 UINT64_C(1184890891), // CMP_SUEQ_D 1104 UINT64_C(1409286869), // CMP_SUEQ_D_MMR6 1105 UINT64_C(1182793739), // CMP_SUEQ_S 1106 UINT64_C(1409286853), // CMP_SUEQ_S_MMR6 1107 UINT64_C(1184890895), // CMP_SULE_D 1108 UINT64_C(1409287125), // CMP_SULE_D_MMR6 1109 UINT64_C(1182793743), // CMP_SULE_S 1110 UINT64_C(1409287109), // CMP_SULE_S_MMR6 1111 UINT64_C(1184890893), // CMP_SULT_D 1112 UINT64_C(1409286997), // CMP_SULT_D_MMR6 1113 UINT64_C(1182793741), // CMP_SULT_S 1114 UINT64_C(1409286981), // CMP_SULT_S_MMR6 1115 UINT64_C(1184890889), // CMP_SUN_D 1116 UINT64_C(1409286741), // CMP_SUN_D_MMR6 1117 UINT64_C(1182793737), // CMP_SUN_S 1118 UINT64_C(1409286725), // CMP_SUN_S_MMR6 1119 UINT64_C(1184890883), // CMP_UEQ_D 1120 UINT64_C(1409286357), // CMP_UEQ_D_MMR6 1121 UINT64_C(1182793731), // CMP_UEQ_S 1122 UINT64_C(1409286341), // CMP_UEQ_S_MMR6 1123 UINT64_C(1184890887), // CMP_ULE_D 1124 UINT64_C(1409286613), // CMP_ULE_D_MMR6 1125 UINT64_C(1182793735), // CMP_ULE_S 1126 UINT64_C(1409286597), // CMP_ULE_S_MMR6 1127 UINT64_C(1184890885), // CMP_ULT_D 1128 UINT64_C(1409286485), // CMP_ULT_D_MMR6 1129 UINT64_C(1182793733), // CMP_ULT_S 1130 UINT64_C(1409286469), // CMP_ULT_S_MMR6 1131 UINT64_C(1184890881), // CMP_UN_D 1132 UINT64_C(1409286229), // CMP_UN_D_MMR6 1133 UINT64_C(1182793729), // CMP_UN_S 1134 UINT64_C(1409286213), // CMP_UN_S_MMR6 1135 UINT64_C(2021654553), // COPY_S_B 1136 UINT64_C(2025324569), // COPY_S_D 1137 UINT64_C(2023751705), // COPY_S_H 1138 UINT64_C(2024800281), // COPY_S_W 1139 UINT64_C(2025848857), // COPY_U_B 1140 UINT64_C(2027946009), // COPY_U_H 1141 UINT64_C(2028994585), // COPY_U_W 1142 UINT64_C(2080374799), // CRC32B 1143 UINT64_C(2080375055), // CRC32CB 1144 UINT64_C(2080375247), // CRC32CD 1145 UINT64_C(2080375119), // CRC32CH 1146 UINT64_C(2080375183), // CRC32CW 1147 UINT64_C(2080374991), // CRC32D 1148 UINT64_C(2080374863), // CRC32H 1149 UINT64_C(2080374927), // CRC32W 1150 UINT64_C(1153433600), // CTC1 1151 UINT64_C(1409292347), // CTC1_MM 1152 UINT64_C(56636), // CTC2_MM 1153 UINT64_C(2017329177), // CTCMSA 1154 UINT64_C(1174405153), // CVT_D32_S 1155 UINT64_C(1409291131), // CVT_D32_S_MM 1156 UINT64_C(1182793761), // CVT_D32_W 1157 UINT64_C(1409299323), // CVT_D32_W_MM 1158 UINT64_C(1184890913), // CVT_D64_L 1159 UINT64_C(1174405153), // CVT_D64_S 1160 UINT64_C(1409291131), // CVT_D64_S_MM 1161 UINT64_C(1182793761), // CVT_D64_W 1162 UINT64_C(1409299323), // CVT_D64_W_MM 1163 UINT64_C(1409307515), // CVT_D_L_MMR6 1164 UINT64_C(1176502309), // CVT_L_D64 1165 UINT64_C(1409302843), // CVT_L_D64_MM 1166 UINT64_C(1409302843), // CVT_L_D_MMR6 1167 UINT64_C(1174405157), // CVT_L_S 1168 UINT64_C(1409286459), // CVT_L_S_MM 1169 UINT64_C(1409286459), // CVT_L_S_MMR6 1170 UINT64_C(1174405158), // CVT_PS_S64 1171 UINT64_C(1176502304), // CVT_S_D32 1172 UINT64_C(1409293179), // CVT_S_D32_MM 1173 UINT64_C(1176502304), // CVT_S_D64 1174 UINT64_C(1409293179), // CVT_S_D64_MM 1175 UINT64_C(1184890912), // CVT_S_L 1176 UINT64_C(1409309563), // CVT_S_L_MMR6 1177 UINT64_C(1186988072), // CVT_S_PL64 1178 UINT64_C(1186988064), // CVT_S_PU64 1179 UINT64_C(1182793760), // CVT_S_W 1180 UINT64_C(1409301371), // CVT_S_W_MM 1181 UINT64_C(1409301371), // CVT_S_W_MMR6 1182 UINT64_C(1176502308), // CVT_W_D32 1183 UINT64_C(1409304891), // CVT_W_D32_MM 1184 UINT64_C(1176502308), // CVT_W_D64 1185 UINT64_C(1409304891), // CVT_W_D64_MM 1186 UINT64_C(1174405156), // CVT_W_S 1187 UINT64_C(1409288507), // CVT_W_S_MM 1188 UINT64_C(1409288507), // CVT_W_S_MMR6 1189 UINT64_C(1176502322), // C_EQ_D32 1190 UINT64_C(1409287356), // C_EQ_D32_MM 1191 UINT64_C(1176502322), // C_EQ_D64 1192 UINT64_C(1409287356), // C_EQ_D64_MM 1193 UINT64_C(1174405170), // C_EQ_S 1194 UINT64_C(1409286332), // C_EQ_S_MM 1195 UINT64_C(1176502320), // C_F_D32 1196 UINT64_C(1409287228), // C_F_D32_MM 1197 UINT64_C(1176502320), // C_F_D64 1198 UINT64_C(1409287228), // C_F_D64_MM 1199 UINT64_C(1174405168), // C_F_S 1200 UINT64_C(1409286204), // C_F_S_MM 1201 UINT64_C(1176502334), // C_LE_D32 1202 UINT64_C(1409288124), // C_LE_D32_MM 1203 UINT64_C(1176502334), // C_LE_D64 1204 UINT64_C(1409288124), // C_LE_D64_MM 1205 UINT64_C(1174405182), // C_LE_S 1206 UINT64_C(1409287100), // C_LE_S_MM 1207 UINT64_C(1176502332), // C_LT_D32 1208 UINT64_C(1409287996), // C_LT_D32_MM 1209 UINT64_C(1176502332), // C_LT_D64 1210 UINT64_C(1409287996), // C_LT_D64_MM 1211 UINT64_C(1174405180), // C_LT_S 1212 UINT64_C(1409286972), // C_LT_S_MM 1213 UINT64_C(1176502333), // C_NGE_D32 1214 UINT64_C(1409288060), // C_NGE_D32_MM 1215 UINT64_C(1176502333), // C_NGE_D64 1216 UINT64_C(1409288060), // C_NGE_D64_MM 1217 UINT64_C(1174405181), // C_NGE_S 1218 UINT64_C(1409287036), // C_NGE_S_MM 1219 UINT64_C(1176502329), // C_NGLE_D32 1220 UINT64_C(1409287804), // C_NGLE_D32_MM 1221 UINT64_C(1176502329), // C_NGLE_D64 1222 UINT64_C(1409287804), // C_NGLE_D64_MM 1223 UINT64_C(1174405177), // C_NGLE_S 1224 UINT64_C(1409286780), // C_NGLE_S_MM 1225 UINT64_C(1176502331), // C_NGL_D32 1226 UINT64_C(1409287932), // C_NGL_D32_MM 1227 UINT64_C(1176502331), // C_NGL_D64 1228 UINT64_C(1409287932), // C_NGL_D64_MM 1229 UINT64_C(1174405179), // C_NGL_S 1230 UINT64_C(1409286908), // C_NGL_S_MM 1231 UINT64_C(1176502335), // C_NGT_D32 1232 UINT64_C(1409288188), // C_NGT_D32_MM 1233 UINT64_C(1176502335), // C_NGT_D64 1234 UINT64_C(1409288188), // C_NGT_D64_MM 1235 UINT64_C(1174405183), // C_NGT_S 1236 UINT64_C(1409287164), // C_NGT_S_MM 1237 UINT64_C(1176502326), // C_OLE_D32 1238 UINT64_C(1409287612), // C_OLE_D32_MM 1239 UINT64_C(1176502326), // C_OLE_D64 1240 UINT64_C(1409287612), // C_OLE_D64_MM 1241 UINT64_C(1174405174), // C_OLE_S 1242 UINT64_C(1409286588), // C_OLE_S_MM 1243 UINT64_C(1176502324), // C_OLT_D32 1244 UINT64_C(1409287484), // C_OLT_D32_MM 1245 UINT64_C(1176502324), // C_OLT_D64 1246 UINT64_C(1409287484), // C_OLT_D64_MM 1247 UINT64_C(1174405172), // C_OLT_S 1248 UINT64_C(1409286460), // C_OLT_S_MM 1249 UINT64_C(1176502330), // C_SEQ_D32 1250 UINT64_C(1409287868), // C_SEQ_D32_MM 1251 UINT64_C(1176502330), // C_SEQ_D64 1252 UINT64_C(1409287868), // C_SEQ_D64_MM 1253 UINT64_C(1174405178), // C_SEQ_S 1254 UINT64_C(1409286844), // C_SEQ_S_MM 1255 UINT64_C(1176502328), // C_SF_D32 1256 UINT64_C(1409287740), // C_SF_D32_MM 1257 UINT64_C(1176502328), // C_SF_D64 1258 UINT64_C(1409287740), // C_SF_D64_MM 1259 UINT64_C(1174405176), // C_SF_S 1260 UINT64_C(1409286716), // C_SF_S_MM 1261 UINT64_C(1176502323), // C_UEQ_D32 1262 UINT64_C(1409287420), // C_UEQ_D32_MM 1263 UINT64_C(1176502323), // C_UEQ_D64 1264 UINT64_C(1409287420), // C_UEQ_D64_MM 1265 UINT64_C(1174405171), // C_UEQ_S 1266 UINT64_C(1409286396), // C_UEQ_S_MM 1267 UINT64_C(1176502327), // C_ULE_D32 1268 UINT64_C(1409287676), // C_ULE_D32_MM 1269 UINT64_C(1176502327), // C_ULE_D64 1270 UINT64_C(1409287676), // C_ULE_D64_MM 1271 UINT64_C(1174405175), // C_ULE_S 1272 UINT64_C(1409286652), // C_ULE_S_MM 1273 UINT64_C(1176502325), // C_ULT_D32 1274 UINT64_C(1409287548), // C_ULT_D32_MM 1275 UINT64_C(1176502325), // C_ULT_D64 1276 UINT64_C(1409287548), // C_ULT_D64_MM 1277 UINT64_C(1174405173), // C_ULT_S 1278 UINT64_C(1409286524), // C_ULT_S_MM 1279 UINT64_C(1176502321), // C_UN_D32 1280 UINT64_C(1409287292), // C_UN_D32_MM 1281 UINT64_C(1176502321), // C_UN_D64 1282 UINT64_C(1409287292), // C_UN_D64_MM 1283 UINT64_C(1174405169), // C_UN_S 1284 UINT64_C(1409286268), // C_UN_S_MM 1285 UINT64_C(59402), // CmpRxRy16 1286 UINT64_C(28672), // CmpiRxImm16 1287 UINT64_C(4026560512), // CmpiRxImmX16 1288 UINT64_C(44), // DADD 1289 UINT64_C(1610612736), // DADDi 1290 UINT64_C(1677721600), // DADDiu 1291 UINT64_C(45), // DADDu 1292 UINT64_C(67502080), // DAHI 1293 UINT64_C(2080375332), // DALIGN 1294 UINT64_C(69074944), // DATI 1295 UINT64_C(1946157056), // DAUI 1296 UINT64_C(2080374820), // DBITSWAP 1297 UINT64_C(1879048229), // DCLO 1298 UINT64_C(83), // DCLO_R6 1299 UINT64_C(1879048228), // DCLZ 1300 UINT64_C(82), // DCLZ_R6 1301 UINT64_C(158), // DDIV 1302 UINT64_C(159), // DDIVU 1303 UINT64_C(1107296287), // DERET 1304 UINT64_C(58236), // DERET_MM 1305 UINT64_C(58236), // DERET_MMR6 1306 UINT64_C(2080374787), // DEXT 1307 UINT64_C(2080374787), // DEXT64_32 1308 UINT64_C(2080374785), // DEXTM 1309 UINT64_C(2080374786), // DEXTU 1310 UINT64_C(1096835072), // DI 1311 UINT64_C(2080374791), // DINS 1312 UINT64_C(2080374789), // DINSM 1313 UINT64_C(2080374790), // DINSU 1314 UINT64_C(154), // DIV 1315 UINT64_C(155), // DIVU 1316 UINT64_C(408), // DIVU_MMR6 1317 UINT64_C(280), // DIV_MMR6 1318 UINT64_C(2046820370), // DIV_S_B 1319 UINT64_C(2053111826), // DIV_S_D 1320 UINT64_C(2048917522), // DIV_S_H 1321 UINT64_C(2051014674), // DIV_S_W 1322 UINT64_C(2055208978), // DIV_U_B 1323 UINT64_C(2061500434), // DIV_U_D 1324 UINT64_C(2057306130), // DIV_U_H 1325 UINT64_C(2059403282), // DIV_U_W 1326 UINT64_C(18300), // DI_MM 1327 UINT64_C(18300), // DI_MMR6 1328 UINT64_C(21), // DLSA 1329 UINT64_C(21), // DLSA_R6 1330 UINT64_C(1075838976), // DMFC0 1331 UINT64_C(1142947840), // DMFC1 1332 UINT64_C(1210056704), // DMFC2 1333 UINT64_C(1210056704), // DMFC2_OCTEON 1334 UINT64_C(1080033536), // DMFGC0 1335 UINT64_C(222), // DMOD 1336 UINT64_C(223), // DMODU 1337 UINT64_C(1096813505), // DMT 1338 UINT64_C(1084227584), // DMTC0 1339 UINT64_C(1151336448), // DMTC1 1340 UINT64_C(1218445312), // DMTC2 1341 UINT64_C(1218445312), // DMTC2_OCTEON 1342 UINT64_C(1080034048), // DMTGC0 1343 UINT64_C(220), // DMUH 1344 UINT64_C(221), // DMUHU 1345 UINT64_C(1879048195), // DMUL 1346 UINT64_C(28), // DMULT 1347 UINT64_C(29), // DMULTu 1348 UINT64_C(157), // DMULU 1349 UINT64_C(156), // DMUL_R6 1350 UINT64_C(2019557395), // DOTP_S_D 1351 UINT64_C(2015363091), // DOTP_S_H 1352 UINT64_C(2017460243), // DOTP_S_W 1353 UINT64_C(2027946003), // DOTP_U_D 1354 UINT64_C(2023751699), // DOTP_U_H 1355 UINT64_C(2025848851), // DOTP_U_W 1356 UINT64_C(2036334611), // DPADD_S_D 1357 UINT64_C(2032140307), // DPADD_S_H 1358 UINT64_C(2034237459), // DPADD_S_W 1359 UINT64_C(2044723219), // DPADD_U_D 1360 UINT64_C(2040528915), // DPADD_U_H 1361 UINT64_C(2042626067), // DPADD_U_W 1362 UINT64_C(2080376496), // DPAQX_SA_W_PH 1363 UINT64_C(12988), // DPAQX_SA_W_PH_MMR2 1364 UINT64_C(2080376368), // DPAQX_S_W_PH 1365 UINT64_C(8892), // DPAQX_S_W_PH_MMR2 1366 UINT64_C(2080375600), // DPAQ_SA_L_W 1367 UINT64_C(4796), // DPAQ_SA_L_W_MM 1368 UINT64_C(2080375088), // DPAQ_S_W_PH 1369 UINT64_C(700), // DPAQ_S_W_PH_MM 1370 UINT64_C(2080375024), // DPAU_H_QBL 1371 UINT64_C(8380), // DPAU_H_QBL_MM 1372 UINT64_C(2080375280), // DPAU_H_QBR 1373 UINT64_C(12476), // DPAU_H_QBR_MM 1374 UINT64_C(2080375344), // DPAX_W_PH 1375 UINT64_C(4284), // DPAX_W_PH_MMR2 1376 UINT64_C(2080374832), // DPA_W_PH 1377 UINT64_C(188), // DPA_W_PH_MMR2 1378 UINT64_C(1879048237), // DPOP 1379 UINT64_C(2080376560), // DPSQX_SA_W_PH 1380 UINT64_C(14012), // DPSQX_SA_W_PH_MMR2 1381 UINT64_C(2080376432), // DPSQX_S_W_PH 1382 UINT64_C(9916), // DPSQX_S_W_PH_MMR2 1383 UINT64_C(2080375664), // DPSQ_SA_L_W 1384 UINT64_C(5820), // DPSQ_SA_L_W_MM 1385 UINT64_C(2080375152), // DPSQ_S_W_PH 1386 UINT64_C(1724), // DPSQ_S_W_PH_MM 1387 UINT64_C(2053111827), // DPSUB_S_D 1388 UINT64_C(2048917523), // DPSUB_S_H 1389 UINT64_C(2051014675), // DPSUB_S_W 1390 UINT64_C(2061500435), // DPSUB_U_D 1391 UINT64_C(2057306131), // DPSUB_U_H 1392 UINT64_C(2059403283), // DPSUB_U_W 1393 UINT64_C(2080375536), // DPSU_H_QBL 1394 UINT64_C(9404), // DPSU_H_QBL_MM 1395 UINT64_C(2080375792), // DPSU_H_QBR 1396 UINT64_C(13500), // DPSU_H_QBR_MM 1397 UINT64_C(2080375408), // DPSX_W_PH 1398 UINT64_C(5308), // DPSX_W_PH_MMR2 1399 UINT64_C(2080374896), // DPS_W_PH 1400 UINT64_C(1212), // DPS_W_PH_MMR2 1401 UINT64_C(2097210), // DROTR 1402 UINT64_C(2097214), // DROTR32 1403 UINT64_C(86), // DROTRV 1404 UINT64_C(2080374948), // DSBH 1405 UINT64_C(30), // DSDIV 1406 UINT64_C(2080375140), // DSHD 1407 UINT64_C(56), // DSLL 1408 UINT64_C(60), // DSLL32 1409 UINT64_C(60), // DSLL64_32 1410 UINT64_C(20), // DSLLV 1411 UINT64_C(59), // DSRA 1412 UINT64_C(63), // DSRA32 1413 UINT64_C(23), // DSRAV 1414 UINT64_C(58), // DSRL 1415 UINT64_C(62), // DSRL32 1416 UINT64_C(22), // DSRLV 1417 UINT64_C(46), // DSUB 1418 UINT64_C(47), // DSUBu 1419 UINT64_C(31), // DUDIV 1420 UINT64_C(1096810532), // DVP 1421 UINT64_C(1096810497), // DVPE 1422 UINT64_C(6524), // DVP_MMR6 1423 UINT64_C(59418), // DivRxRy16 1424 UINT64_C(59419), // DivuRxRy16 1425 UINT64_C(192), // EHB 1426 UINT64_C(6144), // EHB_MM 1427 UINT64_C(6144), // EHB_MMR6 1428 UINT64_C(1096835104), // EI 1429 UINT64_C(22396), // EI_MM 1430 UINT64_C(22396), // EI_MMR6 1431 UINT64_C(1096813537), // EMT 1432 UINT64_C(1107296280), // ERET 1433 UINT64_C(1107296344), // ERETNC 1434 UINT64_C(127868), // ERETNC_MMR6 1435 UINT64_C(62332), // ERET_MM 1436 UINT64_C(62332), // ERET_MMR6 1437 UINT64_C(1096810500), // EVP 1438 UINT64_C(1096810529), // EVPE 1439 UINT64_C(14716), // EVP_MMR6 1440 UINT64_C(2080374784), // EXT 1441 UINT64_C(2080374968), // EXTP 1442 UINT64_C(2080375480), // EXTPDP 1443 UINT64_C(2080375544), // EXTPDPV 1444 UINT64_C(14524), // EXTPDPV_MM 1445 UINT64_C(13948), // EXTPDP_MM 1446 UINT64_C(2080375032), // EXTPV 1447 UINT64_C(10428), // EXTPV_MM 1448 UINT64_C(9852), // EXTP_MM 1449 UINT64_C(2080375288), // EXTRV_RS_W 1450 UINT64_C(11964), // EXTRV_RS_W_MM 1451 UINT64_C(2080375160), // EXTRV_R_W 1452 UINT64_C(7868), // EXTRV_R_W_MM 1453 UINT64_C(2080375800), // EXTRV_S_H 1454 UINT64_C(16060), // EXTRV_S_H_MM 1455 UINT64_C(2080374904), // EXTRV_W 1456 UINT64_C(3772), // EXTRV_W_MM 1457 UINT64_C(2080375224), // EXTR_RS_W 1458 UINT64_C(11900), // EXTR_RS_W_MM 1459 UINT64_C(2080375096), // EXTR_R_W 1460 UINT64_C(7804), // EXTR_R_W_MM 1461 UINT64_C(2080375736), // EXTR_S_H 1462 UINT64_C(15996), // EXTR_S_H_MM 1463 UINT64_C(2080374840), // EXTR_W 1464 UINT64_C(3708), // EXTR_W_MM 1465 UINT64_C(1879048250), // EXTS 1466 UINT64_C(1879048251), // EXTS32 1467 UINT64_C(44), // EXT_MM 1468 UINT64_C(44), // EXT_MMR6 1469 UINT64_C(1176502277), // FABS_D32 1470 UINT64_C(1409295227), // FABS_D32_MM 1471 UINT64_C(1176502277), // FABS_D64 1472 UINT64_C(1409295227), // FABS_D64_MM 1473 UINT64_C(1174405125), // FABS_S 1474 UINT64_C(1409287035), // FABS_S_MM 1475 UINT64_C(2015363099), // FADD_D 1476 UINT64_C(1176502272), // FADD_D32 1477 UINT64_C(1409286448), // FADD_D32_MM 1478 UINT64_C(1176502272), // FADD_D64 1479 UINT64_C(1409286448), // FADD_D64_MM 1480 UINT64_C(1174405120), // FADD_S 1481 UINT64_C(1409286192), // FADD_S_MM 1482 UINT64_C(1409286192), // FADD_S_MMR6 1483 UINT64_C(2013265947), // FADD_W 1484 UINT64_C(2015363098), // FCAF_D 1485 UINT64_C(2013265946), // FCAF_W 1486 UINT64_C(2023751706), // FCEQ_D 1487 UINT64_C(2021654554), // FCEQ_W 1488 UINT64_C(2065760286), // FCLASS_D 1489 UINT64_C(2065694750), // FCLASS_W 1490 UINT64_C(2040528922), // FCLE_D 1491 UINT64_C(2038431770), // FCLE_W 1492 UINT64_C(2032140314), // FCLT_D 1493 UINT64_C(2030043162), // FCLT_W 1494 UINT64_C(1176502320), // FCMP_D32 1495 UINT64_C(1409287228), // FCMP_D32_MM 1496 UINT64_C(1176502320), // FCMP_D64 1497 UINT64_C(1174405168), // FCMP_S32 1498 UINT64_C(1409286204), // FCMP_S32_MM 1499 UINT64_C(2027946012), // FCNE_D 1500 UINT64_C(2025848860), // FCNE_W 1501 UINT64_C(2019557404), // FCOR_D 1502 UINT64_C(2017460252), // FCOR_W 1503 UINT64_C(2027946010), // FCUEQ_D 1504 UINT64_C(2025848858), // FCUEQ_W 1505 UINT64_C(2044723226), // FCULE_D 1506 UINT64_C(2042626074), // FCULE_W 1507 UINT64_C(2036334618), // FCULT_D 1508 UINT64_C(2034237466), // FCULT_W 1509 UINT64_C(2023751708), // FCUNE_D 1510 UINT64_C(2021654556), // FCUNE_W 1511 UINT64_C(2019557402), // FCUN_D 1512 UINT64_C(2017460250), // FCUN_W 1513 UINT64_C(2027946011), // FDIV_D 1514 UINT64_C(1176502275), // FDIV_D32 1515 UINT64_C(1409286640), // FDIV_D32_MM 1516 UINT64_C(1176502275), // FDIV_D64 1517 UINT64_C(1409286640), // FDIV_D64_MM 1518 UINT64_C(1174405123), // FDIV_S 1519 UINT64_C(1409286384), // FDIV_S_MM 1520 UINT64_C(1409286384), // FDIV_S_MMR6 1521 UINT64_C(2025848859), // FDIV_W 1522 UINT64_C(2046820379), // FEXDO_H 1523 UINT64_C(2048917531), // FEXDO_W 1524 UINT64_C(2044723227), // FEXP2_D 1525 UINT64_C(2042626075), // FEXP2_W 1526 UINT64_C(2066808862), // FEXUPL_D 1527 UINT64_C(2066743326), // FEXUPL_W 1528 UINT64_C(2066939934), // FEXUPR_D 1529 UINT64_C(2066874398), // FEXUPR_W 1530 UINT64_C(2067595294), // FFINT_S_D 1531 UINT64_C(2067529758), // FFINT_S_W 1532 UINT64_C(2067726366), // FFINT_U_D 1533 UINT64_C(2067660830), // FFINT_U_W 1534 UINT64_C(2067071006), // FFQL_D 1535 UINT64_C(2067005470), // FFQL_W 1536 UINT64_C(2067202078), // FFQR_D 1537 UINT64_C(2067136542), // FFQR_W 1538 UINT64_C(2063597598), // FILL_B 1539 UINT64_C(2063794206), // FILL_D 1540 UINT64_C(2063663134), // FILL_H 1541 UINT64_C(2063728670), // FILL_W 1542 UINT64_C(2066677790), // FLOG2_D 1543 UINT64_C(2066612254), // FLOG2_W 1544 UINT64_C(1176502283), // FLOOR_L_D64 1545 UINT64_C(1409303355), // FLOOR_L_D_MMR6 1546 UINT64_C(1174405131), // FLOOR_L_S 1547 UINT64_C(1409286971), // FLOOR_L_S_MMR6 1548 UINT64_C(1176502287), // FLOOR_W_D32 1549 UINT64_C(1176502287), // FLOOR_W_D64 1550 UINT64_C(1409305403), // FLOOR_W_D_MMR6 1551 UINT64_C(1409305403), // FLOOR_W_MM 1552 UINT64_C(1174405135), // FLOOR_W_S 1553 UINT64_C(1409289019), // FLOOR_W_S_MM 1554 UINT64_C(1409289019), // FLOOR_W_S_MMR6 1555 UINT64_C(2032140315), // FMADD_D 1556 UINT64_C(2030043163), // FMADD_W 1557 UINT64_C(2078277659), // FMAX_A_D 1558 UINT64_C(2076180507), // FMAX_A_W 1559 UINT64_C(2074083355), // FMAX_D 1560 UINT64_C(2071986203), // FMAX_W 1561 UINT64_C(2069889051), // FMIN_A_D 1562 UINT64_C(2067791899), // FMIN_A_W 1563 UINT64_C(2065694747), // FMIN_D 1564 UINT64_C(2063597595), // FMIN_W 1565 UINT64_C(1176502278), // FMOV_D32 1566 UINT64_C(1409294459), // FMOV_D32_MM 1567 UINT64_C(1176502278), // FMOV_D64 1568 UINT64_C(1409294459), // FMOV_D64_MM 1569 UINT64_C(1409294459), // FMOV_D_MMR6 1570 UINT64_C(1174405126), // FMOV_S 1571 UINT64_C(1409286267), // FMOV_S_MM 1572 UINT64_C(1409286267), // FMOV_S_MMR6 1573 UINT64_C(2036334619), // FMSUB_D 1574 UINT64_C(2034237467), // FMSUB_W 1575 UINT64_C(2023751707), // FMUL_D 1576 UINT64_C(1176502274), // FMUL_D32 1577 UINT64_C(1409286576), // FMUL_D32_MM 1578 UINT64_C(1176502274), // FMUL_D64 1579 UINT64_C(1409286576), // FMUL_D64_MM 1580 UINT64_C(1174405122), // FMUL_S 1581 UINT64_C(1409286320), // FMUL_S_MM 1582 UINT64_C(1409286320), // FMUL_S_MMR6 1583 UINT64_C(2021654555), // FMUL_W 1584 UINT64_C(1176502279), // FNEG_D32 1585 UINT64_C(1409297275), // FNEG_D32_MM 1586 UINT64_C(1176502279), // FNEG_D64 1587 UINT64_C(1409297275), // FNEG_D64_MM 1588 UINT64_C(1174405127), // FNEG_S 1589 UINT64_C(1409289083), // FNEG_S_MM 1590 UINT64_C(1409289083), // FNEG_S_MMR6 1591 UINT64_C(2080374792), // FORK 1592 UINT64_C(2066415646), // FRCP_D 1593 UINT64_C(2066350110), // FRCP_W 1594 UINT64_C(2066546718), // FRINT_D 1595 UINT64_C(2066481182), // FRINT_W 1596 UINT64_C(2066284574), // FRSQRT_D 1597 UINT64_C(2066219038), // FRSQRT_W 1598 UINT64_C(2048917530), // FSAF_D 1599 UINT64_C(2046820378), // FSAF_W 1600 UINT64_C(2057306138), // FSEQ_D 1601 UINT64_C(2055208986), // FSEQ_W 1602 UINT64_C(2074083354), // FSLE_D 1603 UINT64_C(2071986202), // FSLE_W 1604 UINT64_C(2065694746), // FSLT_D 1605 UINT64_C(2063597594), // FSLT_W 1606 UINT64_C(2061500444), // FSNE_D 1607 UINT64_C(2059403292), // FSNE_W 1608 UINT64_C(2053111836), // FSOR_D 1609 UINT64_C(2051014684), // FSOR_W 1610 UINT64_C(2066153502), // FSQRT_D 1611 UINT64_C(1176502276), // FSQRT_D32 1612 UINT64_C(1409305147), // FSQRT_D32_MM 1613 UINT64_C(1176502276), // FSQRT_D64 1614 UINT64_C(1409305147), // FSQRT_D64_MM 1615 UINT64_C(1174405124), // FSQRT_S 1616 UINT64_C(1409288763), // FSQRT_S_MM 1617 UINT64_C(2066087966), // FSQRT_W 1618 UINT64_C(2019557403), // FSUB_D 1619 UINT64_C(1176502273), // FSUB_D32 1620 UINT64_C(1409286512), // FSUB_D32_MM 1621 UINT64_C(1176502273), // FSUB_D64 1622 UINT64_C(1409286512), // FSUB_D64_MM 1623 UINT64_C(1174405121), // FSUB_S 1624 UINT64_C(1409286256), // FSUB_S_MM 1625 UINT64_C(1409286256), // FSUB_S_MMR6 1626 UINT64_C(2017460251), // FSUB_W 1627 UINT64_C(2061500442), // FSUEQ_D 1628 UINT64_C(2059403290), // FSUEQ_W 1629 UINT64_C(2078277658), // FSULE_D 1630 UINT64_C(2076180506), // FSULE_W 1631 UINT64_C(2069889050), // FSULT_D 1632 UINT64_C(2067791898), // FSULT_W 1633 UINT64_C(2057306140), // FSUNE_D 1634 UINT64_C(2055208988), // FSUNE_W 1635 UINT64_C(2053111834), // FSUN_D 1636 UINT64_C(2051014682), // FSUN_W 1637 UINT64_C(2067333150), // FTINT_S_D 1638 UINT64_C(2067267614), // FTINT_S_W 1639 UINT64_C(2067464222), // FTINT_U_D 1640 UINT64_C(2067398686), // FTINT_U_W 1641 UINT64_C(2055208987), // FTQ_H 1642 UINT64_C(2057306139), // FTQ_W 1643 UINT64_C(2065891358), // FTRUNC_S_D 1644 UINT64_C(2065825822), // FTRUNC_S_W 1645 UINT64_C(2066022430), // FTRUNC_U_D 1646 UINT64_C(2065956894), // FTRUNC_U_W 1647 UINT64_C(2080374845), // GINVI 1648 UINT64_C(24956), // GINVI_MMR6 1649 UINT64_C(2080374973), // GINVT 1650 UINT64_C(29052), // GINVT_MMR6 1651 UINT64_C(2053111829), // HADD_S_D 1652 UINT64_C(2048917525), // HADD_S_H 1653 UINT64_C(2051014677), // HADD_S_W 1654 UINT64_C(2061500437), // HADD_U_D 1655 UINT64_C(2057306133), // HADD_U_H 1656 UINT64_C(2059403285), // HADD_U_W 1657 UINT64_C(2069889045), // HSUB_S_D 1658 UINT64_C(2065694741), // HSUB_S_H 1659 UINT64_C(2067791893), // HSUB_S_W 1660 UINT64_C(2078277653), // HSUB_U_D 1661 UINT64_C(2074083349), // HSUB_U_H 1662 UINT64_C(2076180501), // HSUB_U_W 1663 UINT64_C(1107296296), // HYPCALL 1664 UINT64_C(50044), // HYPCALL_MM 1665 UINT64_C(2063597588), // ILVEV_B 1666 UINT64_C(2069889044), // ILVEV_D 1667 UINT64_C(2065694740), // ILVEV_H 1668 UINT64_C(2067791892), // ILVEV_W 1669 UINT64_C(2046820372), // ILVL_B 1670 UINT64_C(2053111828), // ILVL_D 1671 UINT64_C(2048917524), // ILVL_H 1672 UINT64_C(2051014676), // ILVL_W 1673 UINT64_C(2071986196), // ILVOD_B 1674 UINT64_C(2078277652), // ILVOD_D 1675 UINT64_C(2074083348), // ILVOD_H 1676 UINT64_C(2076180500), // ILVOD_W 1677 UINT64_C(2055208980), // ILVR_B 1678 UINT64_C(2061500436), // ILVR_D 1679 UINT64_C(2057306132), // ILVR_H 1680 UINT64_C(2059403284), // ILVR_W 1681 UINT64_C(2080374788), // INS 1682 UINT64_C(2030043161), // INSERT_B 1683 UINT64_C(2033713177), // INSERT_D 1684 UINT64_C(2032140313), // INSERT_H 1685 UINT64_C(2033188889), // INSERT_W 1686 UINT64_C(2080374796), // INSV 1687 UINT64_C(2034237465), // INSVE_B 1688 UINT64_C(2037907481), // INSVE_D 1689 UINT64_C(2036334617), // INSVE_H 1690 UINT64_C(2037383193), // INSVE_W 1691 UINT64_C(16700), // INSV_MM 1692 UINT64_C(12), // INS_MM 1693 UINT64_C(12), // INS_MMR6 1694 UINT64_C(134217728), // J 1695 UINT64_C(201326592), // JAL 1696 UINT64_C(9), // JALR 1697 UINT64_C(17856), // JALR16_MM 1698 UINT64_C(9), // JALR64 1699 UINT64_C(17419), // JALRC16_MMR6 1700 UINT64_C(7996), // JALRC_HB_MMR6 1701 UINT64_C(3900), // JALRC_MMR6 1702 UINT64_C(17888), // JALRS16_MM 1703 UINT64_C(20284), // JALRS_MM 1704 UINT64_C(1033), // JALR_HB 1705 UINT64_C(1033), // JALR_HB64 1706 UINT64_C(3900), // JALR_MM 1707 UINT64_C(1946157056), // JALS_MM 1708 UINT64_C(1946157056), // JALX 1709 UINT64_C(4026531840), // JALX_MM 1710 UINT64_C(4093640704), // JAL_MM 1711 UINT64_C(4160749568), // JIALC 1712 UINT64_C(4160749568), // JIALC64 1713 UINT64_C(2147483648), // JIALC_MMR6 1714 UINT64_C(3623878656), // JIC 1715 UINT64_C(3623878656), // JIC64 1716 UINT64_C(2684354560), // JIC_MMR6 1717 UINT64_C(8), // JR 1718 UINT64_C(17792), // JR16_MM 1719 UINT64_C(8), // JR64 1720 UINT64_C(18176), // JRADDIUSP 1721 UINT64_C(17824), // JRC16_MM 1722 UINT64_C(17411), // JRC16_MMR6 1723 UINT64_C(17427), // JRCADDIUSP_MMR6 1724 UINT64_C(1032), // JR_HB 1725 UINT64_C(1032), // JR_HB64 1726 UINT64_C(1033), // JR_HB64_R6 1727 UINT64_C(1033), // JR_HB_R6 1728 UINT64_C(3900), // JR_MM 1729 UINT64_C(3556769792), // J_MM 1730 UINT64_C(402653184), // Jal16 1731 UINT64_C(402653184), // JalB16 1732 UINT64_C(59424), // JrRa16 1733 UINT64_C(59616), // JrcRa16 1734 UINT64_C(59584), // JrcRx16 1735 UINT64_C(59392), // JumpLinkReg16 1736 UINT64_C(2147483648), // LB 1737 UINT64_C(2147483648), // LB64 1738 UINT64_C(2080374828), // LBE 1739 UINT64_C(1610639360), // LBE_MM 1740 UINT64_C(2048), // LBU16_MM 1741 UINT64_C(2080375178), // LBUX 1742 UINT64_C(549), // LBUX_MM 1743 UINT64_C(335544320), // LBU_MMR6 1744 UINT64_C(469762048), // LB_MM 1745 UINT64_C(469762048), // LB_MMR6 1746 UINT64_C(2415919104), // LBu 1747 UINT64_C(2415919104), // LBu64 1748 UINT64_C(2080374824), // LBuE 1749 UINT64_C(1610637312), // LBuE_MM 1750 UINT64_C(335544320), // LBu_MM 1751 UINT64_C(3690987520), // LD 1752 UINT64_C(3556769792), // LDC1 1753 UINT64_C(3556769792), // LDC164 1754 UINT64_C(3154116608), // LDC1_D64_MMR6 1755 UINT64_C(3154116608), // LDC1_MM 1756 UINT64_C(3623878656), // LDC2 1757 UINT64_C(536879104), // LDC2_MMR6 1758 UINT64_C(1237319680), // LDC2_R6 1759 UINT64_C(3690987520), // LDC3 1760 UINT64_C(2063597575), // LDI_B 1761 UINT64_C(2069889031), // LDI_D 1762 UINT64_C(2065694727), // LDI_H 1763 UINT64_C(2067791879), // LDI_W 1764 UINT64_C(1744830464), // LDL 1765 UINT64_C(3960995840), // LDPC 1766 UINT64_C(1811939328), // LDR 1767 UINT64_C(1275068417), // LDXC1 1768 UINT64_C(1275068417), // LDXC164 1769 UINT64_C(2013265952), // LD_B 1770 UINT64_C(2013265955), // LD_D 1771 UINT64_C(2013265953), // LD_H 1772 UINT64_C(2013265954), // LD_W 1773 UINT64_C(603979776), // LEA_ADDiu 1774 UINT64_C(1677721600), // LEA_ADDiu64 1775 UINT64_C(805306368), // LEA_ADDiu_MM 1776 UINT64_C(2214592512), // LH 1777 UINT64_C(2214592512), // LH64 1778 UINT64_C(2080374829), // LHE 1779 UINT64_C(1610639872), // LHE_MM 1780 UINT64_C(10240), // LHU16_MM 1781 UINT64_C(2080375050), // LHX 1782 UINT64_C(357), // LHX_MM 1783 UINT64_C(1006632960), // LH_MM 1784 UINT64_C(2483027968), // LHu 1785 UINT64_C(2483027968), // LHu64 1786 UINT64_C(2080374825), // LHuE 1787 UINT64_C(1610637824), // LHuE_MM 1788 UINT64_C(872415232), // LHu_MM 1789 UINT64_C(60416), // LI16_MM 1790 UINT64_C(60416), // LI16_MMR6 1791 UINT64_C(3221225472), // LL 1792 UINT64_C(3221225472), // LL64 1793 UINT64_C(2080374838), // LL64_R6 1794 UINT64_C(3489660928), // LLD 1795 UINT64_C(2080374839), // LLD_R6 1796 UINT64_C(2080374830), // LLE 1797 UINT64_C(1610640384), // LLE_MM 1798 UINT64_C(1610625024), // LL_MM 1799 UINT64_C(1610625024), // LL_MMR6 1800 UINT64_C(2080374838), // LL_R6 1801 UINT64_C(5), // LSA 1802 UINT64_C(15), // LSA_MMR6 1803 UINT64_C(5), // LSA_R6 1804 UINT64_C(268435456), // LUI_MMR6 1805 UINT64_C(1275068421), // LUXC1 1806 UINT64_C(1275068421), // LUXC164 1807 UINT64_C(1409286472), // LUXC1_MM 1808 UINT64_C(1006632960), // LUi 1809 UINT64_C(1006632960), // LUi64 1810 UINT64_C(1101004800), // LUi_MM 1811 UINT64_C(2348810240), // LW 1812 UINT64_C(26624), // LW16_MM 1813 UINT64_C(2348810240), // LW64 1814 UINT64_C(3288334336), // LWC1 1815 UINT64_C(2617245696), // LWC1_MM 1816 UINT64_C(3355443200), // LWC2 1817 UINT64_C(536870912), // LWC2_MMR6 1818 UINT64_C(1228931072), // LWC2_R6 1819 UINT64_C(3422552064), // LWC3 1820 UINT64_C(2348810240), // LWDSP 1821 UINT64_C(4227858432), // LWDSP_MM 1822 UINT64_C(2080374831), // LWE 1823 UINT64_C(1610640896), // LWE_MM 1824 UINT64_C(25600), // LWGP_MM 1825 UINT64_C(2281701376), // LWL 1826 UINT64_C(2281701376), // LWL64 1827 UINT64_C(2080374809), // LWLE 1828 UINT64_C(1610638336), // LWLE_MM 1829 UINT64_C(1610612736), // LWL_MM 1830 UINT64_C(17664), // LWM16_MM 1831 UINT64_C(17410), // LWM16_MMR6 1832 UINT64_C(536891392), // LWM32_MM 1833 UINT64_C(3959947264), // LWPC 1834 UINT64_C(2013790208), // LWPC_MMR6 1835 UINT64_C(536875008), // LWP_MM 1836 UINT64_C(2550136832), // LWR 1837 UINT64_C(2550136832), // LWR64 1838 UINT64_C(2080374810), // LWRE 1839 UINT64_C(1610638848), // LWRE_MM 1840 UINT64_C(1610616832), // LWR_MM 1841 UINT64_C(18432), // LWSP_MM 1842 UINT64_C(3960471552), // LWUPC 1843 UINT64_C(1610670080), // LWU_MM 1844 UINT64_C(2080374794), // LWX 1845 UINT64_C(1275068416), // LWXC1 1846 UINT64_C(1409286216), // LWXC1_MM 1847 UINT64_C(280), // LWXS_MM 1848 UINT64_C(421), // LWX_MM 1849 UINT64_C(4227858432), // LW_MM 1850 UINT64_C(4227858432), // LW_MMR6 1851 UINT64_C(2617245696), // LWu 1852 UINT64_C(4026570752), // LbRxRyOffMemX16 1853 UINT64_C(4026572800), // LbuRxRyOffMemX16 1854 UINT64_C(4026572800), // LhRxRyOffMemX16 1855 UINT64_C(4026572800), // LhuRxRyOffMemX16 1856 UINT64_C(26624), // LiRxImm16 1857 UINT64_C(4026558464), // LiRxImmAlignX16 1858 UINT64_C(4026558464), // LiRxImmX16 1859 UINT64_C(45056), // LwRxPcTcp16 1860 UINT64_C(4026576896), // LwRxPcTcpX16 1861 UINT64_C(4026570752), // LwRxRyOffMemX16 1862 UINT64_C(4026568704), // LwRxSpImmX16 1863 UINT64_C(1879048192), // MADD 1864 UINT64_C(1176502296), // MADDF_D 1865 UINT64_C(1409287096), // MADDF_D_MMR6 1866 UINT64_C(1174405144), // MADDF_S 1867 UINT64_C(1409286584), // MADDF_S_MMR6 1868 UINT64_C(2067791900), // MADDR_Q_H 1869 UINT64_C(2069889052), // MADDR_Q_W 1870 UINT64_C(1879048193), // MADDU 1871 UINT64_C(1879048193), // MADDU_DSP 1872 UINT64_C(6844), // MADDU_DSP_MM 1873 UINT64_C(56124), // MADDU_MM 1874 UINT64_C(2021654546), // MADDV_B 1875 UINT64_C(2027946002), // MADDV_D 1876 UINT64_C(2023751698), // MADDV_H 1877 UINT64_C(2025848850), // MADDV_W 1878 UINT64_C(1275068449), // MADD_D32 1879 UINT64_C(1409286153), // MADD_D32_MM 1880 UINT64_C(1275068449), // MADD_D64 1881 UINT64_C(1879048192), // MADD_DSP 1882 UINT64_C(2748), // MADD_DSP_MM 1883 UINT64_C(52028), // MADD_MM 1884 UINT64_C(2034237468), // MADD_Q_H 1885 UINT64_C(2036334620), // MADD_Q_W 1886 UINT64_C(1275068448), // MADD_S 1887 UINT64_C(1409286145), // MADD_S_MM 1888 UINT64_C(2080375856), // MAQ_SA_W_PHL 1889 UINT64_C(14972), // MAQ_SA_W_PHL_MM 1890 UINT64_C(2080375984), // MAQ_SA_W_PHR 1891 UINT64_C(10876), // MAQ_SA_W_PHR_MM 1892 UINT64_C(2080376112), // MAQ_S_W_PHL 1893 UINT64_C(6780), // MAQ_S_W_PHL_MM 1894 UINT64_C(2080376240), // MAQ_S_W_PHR 1895 UINT64_C(2684), // MAQ_S_W_PHR_MM 1896 UINT64_C(1176502303), // MAXA_D 1897 UINT64_C(1409286699), // MAXA_D_MMR6 1898 UINT64_C(1174405151), // MAXA_S 1899 UINT64_C(1409286187), // MAXA_S_MMR6 1900 UINT64_C(2030043142), // MAXI_S_B 1901 UINT64_C(2036334598), // MAXI_S_D 1902 UINT64_C(2032140294), // MAXI_S_H 1903 UINT64_C(2034237446), // MAXI_S_W 1904 UINT64_C(2038431750), // MAXI_U_B 1905 UINT64_C(2044723206), // MAXI_U_D 1906 UINT64_C(2040528902), // MAXI_U_H 1907 UINT64_C(2042626054), // MAXI_U_W 1908 UINT64_C(2063597582), // MAX_A_B 1909 UINT64_C(2069889038), // MAX_A_D 1910 UINT64_C(2065694734), // MAX_A_H 1911 UINT64_C(2067791886), // MAX_A_W 1912 UINT64_C(1176502301), // MAX_D 1913 UINT64_C(1409286667), // MAX_D_MMR6 1914 UINT64_C(1174405149), // MAX_S 1915 UINT64_C(2030043150), // MAX_S_B 1916 UINT64_C(2036334606), // MAX_S_D 1917 UINT64_C(2032140302), // MAX_S_H 1918 UINT64_C(1409286155), // MAX_S_MMR6 1919 UINT64_C(2034237454), // MAX_S_W 1920 UINT64_C(2038431758), // MAX_U_B 1921 UINT64_C(2044723214), // MAX_U_D 1922 UINT64_C(2040528910), // MAX_U_H 1923 UINT64_C(2042626062), // MAX_U_W 1924 UINT64_C(1073741824), // MFC0 1925 UINT64_C(252), // MFC0_MMR6 1926 UINT64_C(1140850688), // MFC1 1927 UINT64_C(1140850688), // MFC1_D64 1928 UINT64_C(1409294395), // MFC1_MM 1929 UINT64_C(1409294395), // MFC1_MMR6 1930 UINT64_C(1207959552), // MFC2 1931 UINT64_C(19772), // MFC2_MMR6 1932 UINT64_C(1080033280), // MFGC0 1933 UINT64_C(1276), // MFGC0_MM 1934 UINT64_C(244), // MFHC0_MMR6 1935 UINT64_C(1147142144), // MFHC1_D32 1936 UINT64_C(1409298491), // MFHC1_D32_MM 1937 UINT64_C(1147142144), // MFHC1_D64 1938 UINT64_C(1409298491), // MFHC1_D64_MM 1939 UINT64_C(36156), // MFHC2_MMR6 1940 UINT64_C(1080034304), // MFHGC0 1941 UINT64_C(1268), // MFHGC0_MM 1942 UINT64_C(16), // MFHI 1943 UINT64_C(17920), // MFHI16_MM 1944 UINT64_C(16), // MFHI64 1945 UINT64_C(16), // MFHI_DSP 1946 UINT64_C(124), // MFHI_DSP_MM 1947 UINT64_C(3452), // MFHI_MM 1948 UINT64_C(18), // MFLO 1949 UINT64_C(17984), // MFLO16_MM 1950 UINT64_C(18), // MFLO64 1951 UINT64_C(18), // MFLO_DSP 1952 UINT64_C(4220), // MFLO_DSP_MM 1953 UINT64_C(7548), // MFLO_MM 1954 UINT64_C(1090519040), // MFTR 1955 UINT64_C(1176502302), // MINA_D 1956 UINT64_C(1409286691), // MINA_D_MMR6 1957 UINT64_C(1174405150), // MINA_S 1958 UINT64_C(1409286179), // MINA_S_MMR6 1959 UINT64_C(2046820358), // MINI_S_B 1960 UINT64_C(2053111814), // MINI_S_D 1961 UINT64_C(2048917510), // MINI_S_H 1962 UINT64_C(2051014662), // MINI_S_W 1963 UINT64_C(2055208966), // MINI_U_B 1964 UINT64_C(2061500422), // MINI_U_D 1965 UINT64_C(2057306118), // MINI_U_H 1966 UINT64_C(2059403270), // MINI_U_W 1967 UINT64_C(2071986190), // MIN_A_B 1968 UINT64_C(2078277646), // MIN_A_D 1969 UINT64_C(2074083342), // MIN_A_H 1970 UINT64_C(2076180494), // MIN_A_W 1971 UINT64_C(1176502300), // MIN_D 1972 UINT64_C(1409286659), // MIN_D_MMR6 1973 UINT64_C(1174405148), // MIN_S 1974 UINT64_C(2046820366), // MIN_S_B 1975 UINT64_C(2053111822), // MIN_S_D 1976 UINT64_C(2048917518), // MIN_S_H 1977 UINT64_C(1409286147), // MIN_S_MMR6 1978 UINT64_C(2051014670), // MIN_S_W 1979 UINT64_C(2055208974), // MIN_U_B 1980 UINT64_C(2061500430), // MIN_U_D 1981 UINT64_C(2057306126), // MIN_U_H 1982 UINT64_C(2059403278), // MIN_U_W 1983 UINT64_C(218), // MOD 1984 UINT64_C(2080375952), // MODSUB 1985 UINT64_C(661), // MODSUB_MM 1986 UINT64_C(219), // MODU 1987 UINT64_C(472), // MODU_MMR6 1988 UINT64_C(344), // MOD_MMR6 1989 UINT64_C(2063597586), // MOD_S_B 1990 UINT64_C(2069889042), // MOD_S_D 1991 UINT64_C(2065694738), // MOD_S_H 1992 UINT64_C(2067791890), // MOD_S_W 1993 UINT64_C(2071986194), // MOD_U_B 1994 UINT64_C(2078277650), // MOD_U_D 1995 UINT64_C(2074083346), // MOD_U_H 1996 UINT64_C(2076180498), // MOD_U_W 1997 UINT64_C(3072), // MOVE16_MM 1998 UINT64_C(3072), // MOVE16_MMR6 1999 UINT64_C(33792), // MOVEP_MM 2000 UINT64_C(17412), // MOVEP_MMR6 2001 UINT64_C(2025717785), // MOVE_V 2002 UINT64_C(1176502289), // MOVF_D32 2003 UINT64_C(1409286688), // MOVF_D32_MM 2004 UINT64_C(1176502289), // MOVF_D64 2005 UINT64_C(1), // MOVF_I 2006 UINT64_C(1), // MOVF_I64 2007 UINT64_C(1409286523), // MOVF_I_MM 2008 UINT64_C(1174405137), // MOVF_S 2009 UINT64_C(1409286176), // MOVF_S_MM 2010 UINT64_C(1176502291), // MOVN_I64_D64 2011 UINT64_C(11), // MOVN_I64_I 2012 UINT64_C(11), // MOVN_I64_I64 2013 UINT64_C(1174405139), // MOVN_I64_S 2014 UINT64_C(1176502291), // MOVN_I_D32 2015 UINT64_C(1409286456), // MOVN_I_D32_MM 2016 UINT64_C(1176502291), // MOVN_I_D64 2017 UINT64_C(11), // MOVN_I_I 2018 UINT64_C(11), // MOVN_I_I64 2019 UINT64_C(24), // MOVN_I_MM 2020 UINT64_C(1174405139), // MOVN_I_S 2021 UINT64_C(1409286200), // MOVN_I_S_MM 2022 UINT64_C(1176567825), // MOVT_D32 2023 UINT64_C(1409286752), // MOVT_D32_MM 2024 UINT64_C(1176567825), // MOVT_D64 2025 UINT64_C(65537), // MOVT_I 2026 UINT64_C(65537), // MOVT_I64 2027 UINT64_C(1409288571), // MOVT_I_MM 2028 UINT64_C(1174470673), // MOVT_S 2029 UINT64_C(1409286240), // MOVT_S_MM 2030 UINT64_C(1176502290), // MOVZ_I64_D64 2031 UINT64_C(10), // MOVZ_I64_I 2032 UINT64_C(10), // MOVZ_I64_I64 2033 UINT64_C(1174405138), // MOVZ_I64_S 2034 UINT64_C(1176502290), // MOVZ_I_D32 2035 UINT64_C(1409286520), // MOVZ_I_D32_MM 2036 UINT64_C(1176502290), // MOVZ_I_D64 2037 UINT64_C(10), // MOVZ_I_I 2038 UINT64_C(10), // MOVZ_I_I64 2039 UINT64_C(88), // MOVZ_I_MM 2040 UINT64_C(1174405138), // MOVZ_I_S 2041 UINT64_C(1409286264), // MOVZ_I_S_MM 2042 UINT64_C(1879048196), // MSUB 2043 UINT64_C(1176502297), // MSUBF_D 2044 UINT64_C(1409287160), // MSUBF_D_MMR6 2045 UINT64_C(1174405145), // MSUBF_S 2046 UINT64_C(1409286648), // MSUBF_S_MMR6 2047 UINT64_C(2071986204), // MSUBR_Q_H 2048 UINT64_C(2074083356), // MSUBR_Q_W 2049 UINT64_C(1879048197), // MSUBU 2050 UINT64_C(1879048197), // MSUBU_DSP 2051 UINT64_C(15036), // MSUBU_DSP_MM 2052 UINT64_C(64316), // MSUBU_MM 2053 UINT64_C(2030043154), // MSUBV_B 2054 UINT64_C(2036334610), // MSUBV_D 2055 UINT64_C(2032140306), // MSUBV_H 2056 UINT64_C(2034237458), // MSUBV_W 2057 UINT64_C(1275068457), // MSUB_D32 2058 UINT64_C(1409286185), // MSUB_D32_MM 2059 UINT64_C(1275068457), // MSUB_D64 2060 UINT64_C(1879048196), // MSUB_DSP 2061 UINT64_C(10940), // MSUB_DSP_MM 2062 UINT64_C(60220), // MSUB_MM 2063 UINT64_C(2038431772), // MSUB_Q_H 2064 UINT64_C(2040528924), // MSUB_Q_W 2065 UINT64_C(1275068456), // MSUB_S 2066 UINT64_C(1409286177), // MSUB_S_MM 2067 UINT64_C(1082130432), // MTC0 2068 UINT64_C(764), // MTC0_MMR6 2069 UINT64_C(1149239296), // MTC1 2070 UINT64_C(1149239296), // MTC1_D64 2071 UINT64_C(1409296443), // MTC1_D64_MM 2072 UINT64_C(1409296443), // MTC1_MM 2073 UINT64_C(1409296443), // MTC1_MMR6 2074 UINT64_C(1216348160), // MTC2 2075 UINT64_C(23868), // MTC2_MMR6 2076 UINT64_C(1080033792), // MTGC0 2077 UINT64_C(1788), // MTGC0_MM 2078 UINT64_C(756), // MTHC0_MMR6 2079 UINT64_C(1155530752), // MTHC1_D32 2080 UINT64_C(1409300539), // MTHC1_D32_MM 2081 UINT64_C(1155530752), // MTHC1_D64 2082 UINT64_C(1409300539), // MTHC1_D64_MM 2083 UINT64_C(40252), // MTHC2_MMR6 2084 UINT64_C(1080034816), // MTHGC0 2085 UINT64_C(1780), // MTHGC0_MM 2086 UINT64_C(17), // MTHI 2087 UINT64_C(17), // MTHI64 2088 UINT64_C(17), // MTHI_DSP 2089 UINT64_C(8316), // MTHI_DSP_MM 2090 UINT64_C(11644), // MTHI_MM 2091 UINT64_C(2080376824), // MTHLIP 2092 UINT64_C(636), // MTHLIP_MM 2093 UINT64_C(19), // MTLO 2094 UINT64_C(19), // MTLO64 2095 UINT64_C(19), // MTLO_DSP 2096 UINT64_C(12412), // MTLO_DSP_MM 2097 UINT64_C(15740), // MTLO_MM 2098 UINT64_C(1879048200), // MTM0 2099 UINT64_C(1879048204), // MTM1 2100 UINT64_C(1879048205), // MTM2 2101 UINT64_C(1879048201), // MTP0 2102 UINT64_C(1879048202), // MTP1 2103 UINT64_C(1879048203), // MTP2 2104 UINT64_C(1098907648), // MTTR 2105 UINT64_C(216), // MUH 2106 UINT64_C(217), // MUHU 2107 UINT64_C(216), // MUHU_MMR6 2108 UINT64_C(88), // MUH_MMR6 2109 UINT64_C(1879048194), // MUL 2110 UINT64_C(2080376592), // MULEQ_S_W_PHL 2111 UINT64_C(37), // MULEQ_S_W_PHL_MM 2112 UINT64_C(2080376656), // MULEQ_S_W_PHR 2113 UINT64_C(101), // MULEQ_S_W_PHR_MM 2114 UINT64_C(2080375184), // MULEU_S_PH_QBL 2115 UINT64_C(149), // MULEU_S_PH_QBL_MM 2116 UINT64_C(2080375248), // MULEU_S_PH_QBR 2117 UINT64_C(213), // MULEU_S_PH_QBR_MM 2118 UINT64_C(2080376784), // MULQ_RS_PH 2119 UINT64_C(277), // MULQ_RS_PH_MM 2120 UINT64_C(2080376280), // MULQ_RS_W 2121 UINT64_C(405), // MULQ_RS_W_MMR2 2122 UINT64_C(2080376720), // MULQ_S_PH 2123 UINT64_C(341), // MULQ_S_PH_MMR2 2124 UINT64_C(2080376216), // MULQ_S_W 2125 UINT64_C(469), // MULQ_S_W_MMR2 2126 UINT64_C(2063597596), // MULR_Q_H 2127 UINT64_C(2065694748), // MULR_Q_W 2128 UINT64_C(2080375216), // MULSAQ_S_W_PH 2129 UINT64_C(15548), // MULSAQ_S_W_PH_MM 2130 UINT64_C(2080374960), // MULSA_W_PH 2131 UINT64_C(11452), // MULSA_W_PH_MMR2 2132 UINT64_C(24), // MULT 2133 UINT64_C(25), // MULTU_DSP 2134 UINT64_C(7356), // MULTU_DSP_MM 2135 UINT64_C(24), // MULT_DSP 2136 UINT64_C(3260), // MULT_DSP_MM 2137 UINT64_C(35644), // MULT_MM 2138 UINT64_C(25), // MULTu 2139 UINT64_C(39740), // MULTu_MM 2140 UINT64_C(153), // MULU 2141 UINT64_C(152), // MULU_MMR6 2142 UINT64_C(2013265938), // MULV_B 2143 UINT64_C(2019557394), // MULV_D 2144 UINT64_C(2015363090), // MULV_H 2145 UINT64_C(2017460242), // MULV_W 2146 UINT64_C(528), // MUL_MM 2147 UINT64_C(24), // MUL_MMR6 2148 UINT64_C(2080375576), // MUL_PH 2149 UINT64_C(45), // MUL_PH_MMR2 2150 UINT64_C(2030043164), // MUL_Q_H 2151 UINT64_C(2032140316), // MUL_Q_W 2152 UINT64_C(152), // MUL_R6 2153 UINT64_C(2080375704), // MUL_S_PH 2154 UINT64_C(1069), // MUL_S_PH_MMR2 2155 UINT64_C(59408), // Mfhi16 2156 UINT64_C(59410), // Mflo16 2157 UINT64_C(25856), // Move32R16 2158 UINT64_C(26368), // MoveR3216 2159 UINT64_C(2064121886), // NLOC_B 2160 UINT64_C(2064318494), // NLOC_D 2161 UINT64_C(2064187422), // NLOC_H 2162 UINT64_C(2064252958), // NLOC_W 2163 UINT64_C(2064384030), // NLZC_B 2164 UINT64_C(2064580638), // NLZC_D 2165 UINT64_C(2064449566), // NLZC_H 2166 UINT64_C(2064515102), // NLZC_W 2167 UINT64_C(1275068465), // NMADD_D32 2168 UINT64_C(1409286154), // NMADD_D32_MM 2169 UINT64_C(1275068465), // NMADD_D64 2170 UINT64_C(1275068464), // NMADD_S 2171 UINT64_C(1409286146), // NMADD_S_MM 2172 UINT64_C(1275068473), // NMSUB_D32 2173 UINT64_C(1409286186), // NMSUB_D32_MM 2174 UINT64_C(1275068473), // NMSUB_D64 2175 UINT64_C(1275068472), // NMSUB_S 2176 UINT64_C(1409286178), // NMSUB_S_MM 2177 UINT64_C(39), // NOR 2178 UINT64_C(39), // NOR64 2179 UINT64_C(2046820352), // NORI_B 2180 UINT64_C(720), // NOR_MM 2181 UINT64_C(720), // NOR_MMR6 2182 UINT64_C(2017460254), // NOR_V 2183 UINT64_C(17408), // NOT16_MM 2184 UINT64_C(17408), // NOT16_MMR6 2185 UINT64_C(59421), // NegRxRy16 2186 UINT64_C(59407), // NotRxRy16 2187 UINT64_C(37), // OR 2188 UINT64_C(17600), // OR16_MM 2189 UINT64_C(17417), // OR16_MMR6 2190 UINT64_C(37), // OR64 2191 UINT64_C(2030043136), // ORI_B 2192 UINT64_C(1342177280), // ORI_MMR6 2193 UINT64_C(656), // OR_MM 2194 UINT64_C(656), // OR_MMR6 2195 UINT64_C(2015363102), // OR_V 2196 UINT64_C(872415232), // ORi 2197 UINT64_C(872415232), // ORi64 2198 UINT64_C(1342177280), // ORi_MM 2199 UINT64_C(59405), // OrRxRxRy16 2200 UINT64_C(2080375697), // PACKRL_PH 2201 UINT64_C(429), // PACKRL_PH_MM 2202 UINT64_C(320), // PAUSE 2203 UINT64_C(10240), // PAUSE_MM 2204 UINT64_C(10240), // PAUSE_MMR6 2205 UINT64_C(2030043156), // PCKEV_B 2206 UINT64_C(2036334612), // PCKEV_D 2207 UINT64_C(2032140308), // PCKEV_H 2208 UINT64_C(2034237460), // PCKEV_W 2209 UINT64_C(2038431764), // PCKOD_B 2210 UINT64_C(2044723220), // PCKOD_D 2211 UINT64_C(2040528916), // PCKOD_H 2212 UINT64_C(2042626068), // PCKOD_W 2213 UINT64_C(2063859742), // PCNT_B 2214 UINT64_C(2064056350), // PCNT_D 2215 UINT64_C(2063925278), // PCNT_H 2216 UINT64_C(2063990814), // PCNT_W 2217 UINT64_C(2080375505), // PICK_PH 2218 UINT64_C(557), // PICK_PH_MM 2219 UINT64_C(2080374993), // PICK_QB 2220 UINT64_C(493), // PICK_QB_MM 2221 UINT64_C(1186988076), // PLL_PS64 2222 UINT64_C(1186988077), // PLU_PS64 2223 UINT64_C(1879048236), // POP 2224 UINT64_C(2080375058), // PRECEQU_PH_QBL 2225 UINT64_C(2080375186), // PRECEQU_PH_QBLA 2226 UINT64_C(29500), // PRECEQU_PH_QBLA_MM 2227 UINT64_C(28988), // PRECEQU_PH_QBL_MM 2228 UINT64_C(2080375122), // PRECEQU_PH_QBR 2229 UINT64_C(2080375250), // PRECEQU_PH_QBRA 2230 UINT64_C(37692), // PRECEQU_PH_QBRA_MM 2231 UINT64_C(37180), // PRECEQU_PH_QBR_MM 2232 UINT64_C(2080375570), // PRECEQ_W_PHL 2233 UINT64_C(20796), // PRECEQ_W_PHL_MM 2234 UINT64_C(2080375634), // PRECEQ_W_PHR 2235 UINT64_C(24892), // PRECEQ_W_PHR_MM 2236 UINT64_C(2080376594), // PRECEU_PH_QBL 2237 UINT64_C(2080376722), // PRECEU_PH_QBLA 2238 UINT64_C(45884), // PRECEU_PH_QBLA_MM 2239 UINT64_C(45372), // PRECEU_PH_QBL_MM 2240 UINT64_C(2080376658), // PRECEU_PH_QBR 2241 UINT64_C(2080376786), // PRECEU_PH_QBRA 2242 UINT64_C(54076), // PRECEU_PH_QBRA_MM 2243 UINT64_C(53564), // PRECEU_PH_QBR_MM 2244 UINT64_C(2080375761), // PRECRQU_S_QB_PH 2245 UINT64_C(365), // PRECRQU_S_QB_PH_MM 2246 UINT64_C(2080376081), // PRECRQ_PH_W 2247 UINT64_C(237), // PRECRQ_PH_W_MM 2248 UINT64_C(2080375569), // PRECRQ_QB_PH 2249 UINT64_C(173), // PRECRQ_QB_PH_MM 2250 UINT64_C(2080376145), // PRECRQ_RS_PH_W 2251 UINT64_C(301), // PRECRQ_RS_PH_W_MM 2252 UINT64_C(2080375633), // PRECR_QB_PH 2253 UINT64_C(109), // PRECR_QB_PH_MMR2 2254 UINT64_C(2080376721), // PRECR_SRA_PH_W 2255 UINT64_C(973), // PRECR_SRA_PH_W_MMR2 2256 UINT64_C(2080376785), // PRECR_SRA_R_PH_W 2257 UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2 2258 UINT64_C(3422552064), // PREF 2259 UINT64_C(2080374819), // PREFE 2260 UINT64_C(1610654720), // PREFE_MM 2261 UINT64_C(1409286560), // PREFX_MM 2262 UINT64_C(1610620928), // PREF_MM 2263 UINT64_C(1610620928), // PREF_MMR6 2264 UINT64_C(2080374837), // PREF_R6 2265 UINT64_C(2080374897), // PREPEND 2266 UINT64_C(597), // PREPEND_MMR2 2267 UINT64_C(2080376080), // RADDU_W_QB 2268 UINT64_C(61756), // RADDU_W_QB_MM 2269 UINT64_C(2080375992), // RDDSP 2270 UINT64_C(1660), // RDDSP_MM 2271 UINT64_C(2080374843), // RDHWR 2272 UINT64_C(2080374843), // RDHWR64 2273 UINT64_C(27452), // RDHWR_MM 2274 UINT64_C(448), // RDHWR_MMR6 2275 UINT64_C(57724), // RDPGPR_MMR6 2276 UINT64_C(1176502293), // RECIP_D32 2277 UINT64_C(1409307195), // RECIP_D32_MM 2278 UINT64_C(1176502293), // RECIP_D64 2279 UINT64_C(1409307195), // RECIP_D64_MM 2280 UINT64_C(1174405141), // RECIP_S 2281 UINT64_C(1409290811), // RECIP_S_MM 2282 UINT64_C(2080375506), // REPLV_PH 2283 UINT64_C(828), // REPLV_PH_MM 2284 UINT64_C(2080374994), // REPLV_QB 2285 UINT64_C(4924), // REPLV_QB_MM 2286 UINT64_C(2080375442), // REPL_PH 2287 UINT64_C(61), // REPL_PH_MM 2288 UINT64_C(2080374930), // REPL_QB 2289 UINT64_C(1532), // REPL_QB_MM 2290 UINT64_C(1176502298), // RINT_D 2291 UINT64_C(1409286688), // RINT_D_MMR6 2292 UINT64_C(1174405146), // RINT_S 2293 UINT64_C(1409286176), // RINT_S_MMR6 2294 UINT64_C(2097154), // ROTR 2295 UINT64_C(70), // ROTRV 2296 UINT64_C(208), // ROTRV_MM 2297 UINT64_C(192), // ROTR_MM 2298 UINT64_C(1176502280), // ROUND_L_D64 2299 UINT64_C(1409315643), // ROUND_L_D_MMR6 2300 UINT64_C(1174405128), // ROUND_L_S 2301 UINT64_C(1409299259), // ROUND_L_S_MMR6 2302 UINT64_C(1176502284), // ROUND_W_D32 2303 UINT64_C(1176502284), // ROUND_W_D64 2304 UINT64_C(1409317691), // ROUND_W_D_MMR6 2305 UINT64_C(1409317691), // ROUND_W_MM 2306 UINT64_C(1174405132), // ROUND_W_S 2307 UINT64_C(1409301307), // ROUND_W_S_MM 2308 UINT64_C(1409301307), // ROUND_W_S_MMR6 2309 UINT64_C(1176502294), // RSQRT_D32 2310 UINT64_C(1409303099), // RSQRT_D32_MM 2311 UINT64_C(1176502294), // RSQRT_D64 2312 UINT64_C(1409303099), // RSQRT_D64_MM 2313 UINT64_C(1174405142), // RSQRT_S 2314 UINT64_C(1409286715), // RSQRT_S_MM 2315 UINT64_C(25728), // Restore16 2316 UINT64_C(25728), // RestoreX16 2317 UINT64_C(1879048216), // SAA 2318 UINT64_C(1879048217), // SAAD 2319 UINT64_C(2020605962), // SAT_S_B 2320 UINT64_C(2013265930), // SAT_S_D 2321 UINT64_C(2019557386), // SAT_S_H 2322 UINT64_C(2017460234), // SAT_S_W 2323 UINT64_C(2028994570), // SAT_U_B 2324 UINT64_C(2021654538), // SAT_U_D 2325 UINT64_C(2027945994), // SAT_U_H 2326 UINT64_C(2025848842), // SAT_U_W 2327 UINT64_C(2684354560), // SB 2328 UINT64_C(34816), // SB16_MM 2329 UINT64_C(34816), // SB16_MMR6 2330 UINT64_C(2684354560), // SB64 2331 UINT64_C(2080374812), // SBE 2332 UINT64_C(1610655744), // SBE_MM 2333 UINT64_C(402653184), // SB_MM 2334 UINT64_C(402653184), // SB_MMR6 2335 UINT64_C(3758096384), // SC 2336 UINT64_C(3758096384), // SC64 2337 UINT64_C(2080374822), // SC64_R6 2338 UINT64_C(4026531840), // SCD 2339 UINT64_C(2080374823), // SCD_R6 2340 UINT64_C(2080374814), // SCE 2341 UINT64_C(1610656768), // SCE_MM 2342 UINT64_C(1610657792), // SC_MM 2343 UINT64_C(1610657792), // SC_MMR6 2344 UINT64_C(2080374822), // SC_R6 2345 UINT64_C(4227858432), // SD 2346 UINT64_C(1879048255), // SDBBP 2347 UINT64_C(18112), // SDBBP16_MM 2348 UINT64_C(17467), // SDBBP16_MMR6 2349 UINT64_C(56188), // SDBBP_MM 2350 UINT64_C(56188), // SDBBP_MMR6 2351 UINT64_C(14), // SDBBP_R6 2352 UINT64_C(4093640704), // SDC1 2353 UINT64_C(4093640704), // SDC164 2354 UINT64_C(3087007744), // SDC1_D64_MMR6 2355 UINT64_C(3087007744), // SDC1_MM 2356 UINT64_C(4160749568), // SDC2 2357 UINT64_C(536911872), // SDC2_MMR6 2358 UINT64_C(1239416832), // SDC2_R6 2359 UINT64_C(4227858432), // SDC3 2360 UINT64_C(26), // SDIV 2361 UINT64_C(43836), // SDIV_MM 2362 UINT64_C(2952790016), // SDL 2363 UINT64_C(3019898880), // SDR 2364 UINT64_C(1275068425), // SDXC1 2365 UINT64_C(1275068425), // SDXC164 2366 UINT64_C(2080375840), // SEB 2367 UINT64_C(2080375840), // SEB64 2368 UINT64_C(11068), // SEB_MM 2369 UINT64_C(2080376352), // SEH 2370 UINT64_C(2080376352), // SEH64 2371 UINT64_C(15164), // SEH_MM 2372 UINT64_C(53), // SELEQZ 2373 UINT64_C(53), // SELEQZ64 2374 UINT64_C(1176502292), // SELEQZ_D 2375 UINT64_C(1409286712), // SELEQZ_D_MMR6 2376 UINT64_C(320), // SELEQZ_MMR6 2377 UINT64_C(1174405140), // SELEQZ_S 2378 UINT64_C(1409286200), // SELEQZ_S_MMR6 2379 UINT64_C(55), // SELNEZ 2380 UINT64_C(55), // SELNEZ64 2381 UINT64_C(1176502295), // SELNEZ_D 2382 UINT64_C(1409286776), // SELNEZ_D_MMR6 2383 UINT64_C(384), // SELNEZ_MMR6 2384 UINT64_C(1174405143), // SELNEZ_S 2385 UINT64_C(1409286264), // SELNEZ_S_MMR6 2386 UINT64_C(1176502288), // SEL_D 2387 UINT64_C(1409286840), // SEL_D_MMR6 2388 UINT64_C(1174405136), // SEL_S 2389 UINT64_C(1409286328), // SEL_S_MMR6 2390 UINT64_C(1879048234), // SEQ 2391 UINT64_C(1879048238), // SEQi 2392 UINT64_C(2751463424), // SH 2393 UINT64_C(43008), // SH16_MM 2394 UINT64_C(43008), // SH16_MMR6 2395 UINT64_C(2751463424), // SH64 2396 UINT64_C(2080374813), // SHE 2397 UINT64_C(1610656256), // SHE_MM 2398 UINT64_C(2013265922), // SHF_B 2399 UINT64_C(2030043138), // SHF_H 2400 UINT64_C(2046820354), // SHF_W 2401 UINT64_C(2080376504), // SHILO 2402 UINT64_C(2080376568), // SHILOV 2403 UINT64_C(4732), // SHILOV_MM 2404 UINT64_C(29), // SHILO_MM 2405 UINT64_C(2080375443), // SHLLV_PH 2406 UINT64_C(14), // SHLLV_PH_MM 2407 UINT64_C(2080374931), // SHLLV_QB 2408 UINT64_C(917), // SHLLV_QB_MM 2409 UINT64_C(2080375699), // SHLLV_S_PH 2410 UINT64_C(1038), // SHLLV_S_PH_MM 2411 UINT64_C(2080376211), // SHLLV_S_W 2412 UINT64_C(981), // SHLLV_S_W_MM 2413 UINT64_C(2080375315), // SHLL_PH 2414 UINT64_C(949), // SHLL_PH_MM 2415 UINT64_C(2080374803), // SHLL_QB 2416 UINT64_C(2172), // SHLL_QB_MM 2417 UINT64_C(2080375571), // SHLL_S_PH 2418 UINT64_C(2997), // SHLL_S_PH_MM 2419 UINT64_C(2080376083), // SHLL_S_W 2420 UINT64_C(1013), // SHLL_S_W_MM 2421 UINT64_C(2080375507), // SHRAV_PH 2422 UINT64_C(397), // SHRAV_PH_MM 2423 UINT64_C(2080375187), // SHRAV_QB 2424 UINT64_C(461), // SHRAV_QB_MMR2 2425 UINT64_C(2080375763), // SHRAV_R_PH 2426 UINT64_C(1421), // SHRAV_R_PH_MM 2427 UINT64_C(2080375251), // SHRAV_R_QB 2428 UINT64_C(1485), // SHRAV_R_QB_MMR2 2429 UINT64_C(2080376275), // SHRAV_R_W 2430 UINT64_C(725), // SHRAV_R_W_MM 2431 UINT64_C(2080375379), // SHRA_PH 2432 UINT64_C(821), // SHRA_PH_MM 2433 UINT64_C(2080375059), // SHRA_QB 2434 UINT64_C(508), // SHRA_QB_MMR2 2435 UINT64_C(2080375635), // SHRA_R_PH 2436 UINT64_C(1845), // SHRA_R_PH_MM 2437 UINT64_C(2080375123), // SHRA_R_QB 2438 UINT64_C(4604), // SHRA_R_QB_MMR2 2439 UINT64_C(2080376147), // SHRA_R_W 2440 UINT64_C(757), // SHRA_R_W_MM 2441 UINT64_C(2080376531), // SHRLV_PH 2442 UINT64_C(789), // SHRLV_PH_MMR2 2443 UINT64_C(2080374995), // SHRLV_QB 2444 UINT64_C(853), // SHRLV_QB_MM 2445 UINT64_C(2080376403), // SHRL_PH 2446 UINT64_C(1020), // SHRL_PH_MMR2 2447 UINT64_C(2080374867), // SHRL_QB 2448 UINT64_C(6268), // SHRL_QB_MM 2449 UINT64_C(939524096), // SH_MM 2450 UINT64_C(939524096), // SH_MMR6 2451 UINT64_C(68616192), // SIGRIE 2452 UINT64_C(63), // SIGRIE_MMR6 2453 UINT64_C(2013265945), // SLDI_B 2454 UINT64_C(2016935961), // SLDI_D 2455 UINT64_C(2015363097), // SLDI_H 2456 UINT64_C(2016411673), // SLDI_W 2457 UINT64_C(2013265940), // SLD_B 2458 UINT64_C(2019557396), // SLD_D 2459 UINT64_C(2015363092), // SLD_H 2460 UINT64_C(2017460244), // SLD_W 2461 UINT64_C(0), // SLL 2462 UINT64_C(9216), // SLL16_MM 2463 UINT64_C(9216), // SLL16_MMR6 2464 UINT64_C(0), // SLL64_32 2465 UINT64_C(0), // SLL64_64 2466 UINT64_C(2020605961), // SLLI_B 2467 UINT64_C(2013265929), // SLLI_D 2468 UINT64_C(2019557385), // SLLI_H 2469 UINT64_C(2017460233), // SLLI_W 2470 UINT64_C(4), // SLLV 2471 UINT64_C(16), // SLLV_MM 2472 UINT64_C(2013265933), // SLL_B 2473 UINT64_C(2019557389), // SLL_D 2474 UINT64_C(2015363085), // SLL_H 2475 UINT64_C(0), // SLL_MM 2476 UINT64_C(0), // SLL_MMR6 2477 UINT64_C(2017460237), // SLL_W 2478 UINT64_C(42), // SLT 2479 UINT64_C(42), // SLT64 2480 UINT64_C(848), // SLT_MM 2481 UINT64_C(671088640), // SLTi 2482 UINT64_C(671088640), // SLTi64 2483 UINT64_C(2415919104), // SLTi_MM 2484 UINT64_C(738197504), // SLTiu 2485 UINT64_C(738197504), // SLTiu64 2486 UINT64_C(2952790016), // SLTiu_MM 2487 UINT64_C(43), // SLTu 2488 UINT64_C(43), // SLTu64 2489 UINT64_C(912), // SLTu_MM 2490 UINT64_C(1879048235), // SNE 2491 UINT64_C(1879048239), // SNEi 2492 UINT64_C(2017460249), // SPLATI_B 2493 UINT64_C(2021130265), // SPLATI_D 2494 UINT64_C(2019557401), // SPLATI_H 2495 UINT64_C(2020605977), // SPLATI_W 2496 UINT64_C(2021654548), // SPLAT_B 2497 UINT64_C(2027946004), // SPLAT_D 2498 UINT64_C(2023751700), // SPLAT_H 2499 UINT64_C(2025848852), // SPLAT_W 2500 UINT64_C(3), // SRA 2501 UINT64_C(2028994569), // SRAI_B 2502 UINT64_C(2021654537), // SRAI_D 2503 UINT64_C(2027945993), // SRAI_H 2504 UINT64_C(2025848841), // SRAI_W 2505 UINT64_C(2037383178), // SRARI_B 2506 UINT64_C(2030043146), // SRARI_D 2507 UINT64_C(2036334602), // SRARI_H 2508 UINT64_C(2034237450), // SRARI_W 2509 UINT64_C(2021654549), // SRAR_B 2510 UINT64_C(2027946005), // SRAR_D 2511 UINT64_C(2023751701), // SRAR_H 2512 UINT64_C(2025848853), // SRAR_W 2513 UINT64_C(7), // SRAV 2514 UINT64_C(144), // SRAV_MM 2515 UINT64_C(2021654541), // SRA_B 2516 UINT64_C(2027945997), // SRA_D 2517 UINT64_C(2023751693), // SRA_H 2518 UINT64_C(128), // SRA_MM 2519 UINT64_C(2025848845), // SRA_W 2520 UINT64_C(2), // SRL 2521 UINT64_C(9217), // SRL16_MM 2522 UINT64_C(9217), // SRL16_MMR6 2523 UINT64_C(2037383177), // SRLI_B 2524 UINT64_C(2030043145), // SRLI_D 2525 UINT64_C(2036334601), // SRLI_H 2526 UINT64_C(2034237449), // SRLI_W 2527 UINT64_C(2045771786), // SRLRI_B 2528 UINT64_C(2038431754), // SRLRI_D 2529 UINT64_C(2044723210), // SRLRI_H 2530 UINT64_C(2042626058), // SRLRI_W 2531 UINT64_C(2030043157), // SRLR_B 2532 UINT64_C(2036334613), // SRLR_D 2533 UINT64_C(2032140309), // SRLR_H 2534 UINT64_C(2034237461), // SRLR_W 2535 UINT64_C(6), // SRLV 2536 UINT64_C(80), // SRLV_MM 2537 UINT64_C(2030043149), // SRL_B 2538 UINT64_C(2036334605), // SRL_D 2539 UINT64_C(2032140301), // SRL_H 2540 UINT64_C(64), // SRL_MM 2541 UINT64_C(2034237453), // SRL_W 2542 UINT64_C(64), // SSNOP 2543 UINT64_C(2048), // SSNOP_MM 2544 UINT64_C(2048), // SSNOP_MMR6 2545 UINT64_C(2013265956), // ST_B 2546 UINT64_C(2013265959), // ST_D 2547 UINT64_C(2013265957), // ST_H 2548 UINT64_C(2013265958), // ST_W 2549 UINT64_C(34), // SUB 2550 UINT64_C(2080375384), // SUBQH_PH 2551 UINT64_C(589), // SUBQH_PH_MMR2 2552 UINT64_C(2080375512), // SUBQH_R_PH 2553 UINT64_C(1613), // SUBQH_R_PH_MMR2 2554 UINT64_C(2080376024), // SUBQH_R_W 2555 UINT64_C(1677), // SUBQH_R_W_MMR2 2556 UINT64_C(2080375896), // SUBQH_W 2557 UINT64_C(653), // SUBQH_W_MMR2 2558 UINT64_C(2080375504), // SUBQ_PH 2559 UINT64_C(525), // SUBQ_PH_MM 2560 UINT64_C(2080375760), // SUBQ_S_PH 2561 UINT64_C(1549), // SUBQ_S_PH_MM 2562 UINT64_C(2080376272), // SUBQ_S_W 2563 UINT64_C(837), // SUBQ_S_W_MM 2564 UINT64_C(2030043153), // SUBSUS_U_B 2565 UINT64_C(2036334609), // SUBSUS_U_D 2566 UINT64_C(2032140305), // SUBSUS_U_H 2567 UINT64_C(2034237457), // SUBSUS_U_W 2568 UINT64_C(2038431761), // SUBSUU_S_B 2569 UINT64_C(2044723217), // SUBSUU_S_D 2570 UINT64_C(2040528913), // SUBSUU_S_H 2571 UINT64_C(2042626065), // SUBSUU_S_W 2572 UINT64_C(2013265937), // SUBS_S_B 2573 UINT64_C(2019557393), // SUBS_S_D 2574 UINT64_C(2015363089), // SUBS_S_H 2575 UINT64_C(2017460241), // SUBS_S_W 2576 UINT64_C(2021654545), // SUBS_U_B 2577 UINT64_C(2027946001), // SUBS_U_D 2578 UINT64_C(2023751697), // SUBS_U_H 2579 UINT64_C(2025848849), // SUBS_U_W 2580 UINT64_C(1025), // SUBU16_MM 2581 UINT64_C(1025), // SUBU16_MMR6 2582 UINT64_C(2080374872), // SUBUH_QB 2583 UINT64_C(845), // SUBUH_QB_MMR2 2584 UINT64_C(2080375000), // SUBUH_R_QB 2585 UINT64_C(1869), // SUBUH_R_QB_MMR2 2586 UINT64_C(464), // SUBU_MMR6 2587 UINT64_C(2080375376), // SUBU_PH 2588 UINT64_C(781), // SUBU_PH_MMR2 2589 UINT64_C(2080374864), // SUBU_QB 2590 UINT64_C(717), // SUBU_QB_MM 2591 UINT64_C(2080375632), // SUBU_S_PH 2592 UINT64_C(1805), // SUBU_S_PH_MMR2 2593 UINT64_C(2080375120), // SUBU_S_QB 2594 UINT64_C(1741), // SUBU_S_QB_MM 2595 UINT64_C(2021654534), // SUBVI_B 2596 UINT64_C(2027945990), // SUBVI_D 2597 UINT64_C(2023751686), // SUBVI_H 2598 UINT64_C(2025848838), // SUBVI_W 2599 UINT64_C(2021654542), // SUBV_B 2600 UINT64_C(2027945998), // SUBV_D 2601 UINT64_C(2023751694), // SUBV_H 2602 UINT64_C(2025848846), // SUBV_W 2603 UINT64_C(400), // SUB_MM 2604 UINT64_C(400), // SUB_MMR6 2605 UINT64_C(35), // SUBu 2606 UINT64_C(464), // SUBu_MM 2607 UINT64_C(1275068429), // SUXC1 2608 UINT64_C(1275068429), // SUXC164 2609 UINT64_C(1409286536), // SUXC1_MM 2610 UINT64_C(2885681152), // SW 2611 UINT64_C(59392), // SW16_MM 2612 UINT64_C(59392), // SW16_MMR6 2613 UINT64_C(2885681152), // SW64 2614 UINT64_C(3825205248), // SWC1 2615 UINT64_C(2550136832), // SWC1_MM 2616 UINT64_C(3892314112), // SWC2 2617 UINT64_C(536903680), // SWC2_MMR6 2618 UINT64_C(1231028224), // SWC2_R6 2619 UINT64_C(3959422976), // SWC3 2620 UINT64_C(2885681152), // SWDSP 2621 UINT64_C(4160749568), // SWDSP_MM 2622 UINT64_C(2080374815), // SWE 2623 UINT64_C(1610657280), // SWE_MM 2624 UINT64_C(2818572288), // SWL 2625 UINT64_C(2818572288), // SWL64 2626 UINT64_C(2080374817), // SWLE 2627 UINT64_C(1610653696), // SWLE_MM 2628 UINT64_C(1610645504), // SWL_MM 2629 UINT64_C(17728), // SWM16_MM 2630 UINT64_C(17418), // SWM16_MMR6 2631 UINT64_C(536924160), // SWM32_MM 2632 UINT64_C(536907776), // SWP_MM 2633 UINT64_C(3087007744), // SWR 2634 UINT64_C(3087007744), // SWR64 2635 UINT64_C(2080374818), // SWRE 2636 UINT64_C(1610654208), // SWRE_MM 2637 UINT64_C(1610649600), // SWR_MM 2638 UINT64_C(51200), // SWSP_MM 2639 UINT64_C(51200), // SWSP_MMR6 2640 UINT64_C(1275068424), // SWXC1 2641 UINT64_C(1409286280), // SWXC1_MM 2642 UINT64_C(4160749568), // SW_MM 2643 UINT64_C(4160749568), // SW_MMR6 2644 UINT64_C(15), // SYNC 2645 UINT64_C(69140480), // SYNCI 2646 UINT64_C(1107296256), // SYNCI_MM 2647 UINT64_C(1098907648), // SYNCI_MMR6 2648 UINT64_C(27516), // SYNC_MM 2649 UINT64_C(27516), // SYNC_MMR6 2650 UINT64_C(12), // SYSCALL 2651 UINT64_C(35708), // SYSCALL_MM 2652 UINT64_C(25728), // Save16 2653 UINT64_C(25728), // SaveX16 2654 UINT64_C(4026580992), // SbRxRyOffMemX16 2655 UINT64_C(59537), // SebRx16 2656 UINT64_C(59569), // SehRx16 2657 UINT64_C(4026583040), // ShRxRyOffMemX16 2658 UINT64_C(4026544128), // SllX16 2659 UINT64_C(59396), // SllvRxRy16 2660 UINT64_C(59394), // SltRxRy16 2661 UINT64_C(20480), // SltiRxImm16 2662 UINT64_C(4026552320), // SltiRxImmX16 2663 UINT64_C(22528), // SltiuRxImm16 2664 UINT64_C(4026554368), // SltiuRxImmX16 2665 UINT64_C(59395), // SltuRxRy16 2666 UINT64_C(4026544131), // SraX16 2667 UINT64_C(59399), // SravRxRy16 2668 UINT64_C(4026544130), // SrlX16 2669 UINT64_C(59398), // SrlvRxRy16 2670 UINT64_C(57347), // SubuRxRyRz16 2671 UINT64_C(4026587136), // SwRxRyOffMemX16 2672 UINT64_C(4026585088), // SwRxSpImmX16 2673 UINT64_C(52), // TEQ 2674 UINT64_C(67895296), // TEQI 2675 UINT64_C(1103101952), // TEQI_MM 2676 UINT64_C(60), // TEQ_MM 2677 UINT64_C(48), // TGE 2678 UINT64_C(67633152), // TGEI 2679 UINT64_C(67698688), // TGEIU 2680 UINT64_C(1096810496), // TGEIU_MM 2681 UINT64_C(1092616192), // TGEI_MM 2682 UINT64_C(49), // TGEU 2683 UINT64_C(1084), // TGEU_MM 2684 UINT64_C(572), // TGE_MM 2685 UINT64_C(1107296267), // TLBGINV 2686 UINT64_C(1107296268), // TLBGINVF 2687 UINT64_C(20860), // TLBGINVF_MM 2688 UINT64_C(16764), // TLBGINV_MM 2689 UINT64_C(1107296272), // TLBGP 2690 UINT64_C(380), // TLBGP_MM 2691 UINT64_C(1107296265), // TLBGR 2692 UINT64_C(4476), // TLBGR_MM 2693 UINT64_C(1107296266), // TLBGWI 2694 UINT64_C(8572), // TLBGWI_MM 2695 UINT64_C(1107296270), // TLBGWR 2696 UINT64_C(12668), // TLBGWR_MM 2697 UINT64_C(1107296259), // TLBINV 2698 UINT64_C(1107296260), // TLBINVF 2699 UINT64_C(21372), // TLBINVF_MMR6 2700 UINT64_C(17276), // TLBINV_MMR6 2701 UINT64_C(1107296264), // TLBP 2702 UINT64_C(892), // TLBP_MM 2703 UINT64_C(1107296257), // TLBR 2704 UINT64_C(4988), // TLBR_MM 2705 UINT64_C(1107296258), // TLBWI 2706 UINT64_C(9084), // TLBWI_MM 2707 UINT64_C(1107296262), // TLBWR 2708 UINT64_C(13180), // TLBWR_MM 2709 UINT64_C(50), // TLT 2710 UINT64_C(67764224), // TLTI 2711 UINT64_C(1094713344), // TLTIU_MM 2712 UINT64_C(1090519040), // TLTI_MM 2713 UINT64_C(51), // TLTU 2714 UINT64_C(2620), // TLTU_MM 2715 UINT64_C(2108), // TLT_MM 2716 UINT64_C(54), // TNE 2717 UINT64_C(68026368), // TNEI 2718 UINT64_C(1098907648), // TNEI_MM 2719 UINT64_C(3132), // TNE_MM 2720 UINT64_C(1176502281), // TRUNC_L_D64 2721 UINT64_C(1409311547), // TRUNC_L_D_MMR6 2722 UINT64_C(1174405129), // TRUNC_L_S 2723 UINT64_C(1409295163), // TRUNC_L_S_MMR6 2724 UINT64_C(1176502285), // TRUNC_W_D32 2725 UINT64_C(1176502285), // TRUNC_W_D64 2726 UINT64_C(1409313595), // TRUNC_W_D_MMR6 2727 UINT64_C(1409313595), // TRUNC_W_MM 2728 UINT64_C(1174405133), // TRUNC_W_S 2729 UINT64_C(1409297211), // TRUNC_W_S_MM 2730 UINT64_C(1409297211), // TRUNC_W_S_MMR6 2731 UINT64_C(67829760), // TTLTIU 2732 UINT64_C(27), // UDIV 2733 UINT64_C(47932), // UDIV_MM 2734 UINT64_C(1879048209), // V3MULU 2735 UINT64_C(1879048208), // VMM0 2736 UINT64_C(1879048207), // VMULU 2737 UINT64_C(2013265941), // VSHF_B 2738 UINT64_C(2019557397), // VSHF_D 2739 UINT64_C(2015363093), // VSHF_H 2740 UINT64_C(2017460245), // VSHF_W 2741 UINT64_C(1107296288), // WAIT 2742 UINT64_C(37756), // WAIT_MM 2743 UINT64_C(37756), // WAIT_MMR6 2744 UINT64_C(2080376056), // WRDSP 2745 UINT64_C(5756), // WRDSP_MM 2746 UINT64_C(61820), // WRPGPR_MMR6 2747 UINT64_C(2080374944), // WSBH 2748 UINT64_C(31548), // WSBH_MM 2749 UINT64_C(31548), // WSBH_MMR6 2750 UINT64_C(38), // XOR 2751 UINT64_C(17472), // XOR16_MM 2752 UINT64_C(17416), // XOR16_MMR6 2753 UINT64_C(38), // XOR64 2754 UINT64_C(2063597568), // XORI_B 2755 UINT64_C(1879048192), // XORI_MMR6 2756 UINT64_C(784), // XOR_MM 2757 UINT64_C(784), // XOR_MMR6 2758 UINT64_C(2019557406), // XOR_V 2759 UINT64_C(939524096), // XORi 2760 UINT64_C(939524096), // XORi64 2761 UINT64_C(1879048192), // XORi_MM 2762 UINT64_C(59406), // XorRxRxRy16 2763 UINT64_C(2080374793), // YIELD 2764 UINT64_C(0) 2765 }; 2766 const unsigned opcode = MI.getOpcode(); 2767 uint64_t Value = InstBits[opcode]; 2768 uint64_t op = 0; 2769 (void)op; // suppress warning 2770 switch (opcode) { 2771 case Mips::Break16: 2772 case Mips::DERET: 2773 case Mips::DERET_MM: 2774 case Mips::DERET_MMR6: 2775 case Mips::EHB: 2776 case Mips::EHB_MM: 2777 case Mips::EHB_MMR6: 2778 case Mips::ERET: 2779 case Mips::ERETNC: 2780 case Mips::ERETNC_MMR6: 2781 case Mips::ERET_MM: 2782 case Mips::ERET_MMR6: 2783 case Mips::JrRa16: 2784 case Mips::JrcRa16: 2785 case Mips::PAUSE: 2786 case Mips::PAUSE_MM: 2787 case Mips::PAUSE_MMR6: 2788 case Mips::Restore16: 2789 case Mips::RestoreX16: 2790 case Mips::SSNOP: 2791 case Mips::SSNOP_MM: 2792 case Mips::SSNOP_MMR6: 2793 case Mips::Save16: 2794 case Mips::SaveX16: 2795 case Mips::TLBGINV: 2796 case Mips::TLBGINVF: 2797 case Mips::TLBGINVF_MM: 2798 case Mips::TLBGINV_MM: 2799 case Mips::TLBGP: 2800 case Mips::TLBGP_MM: 2801 case Mips::TLBGR: 2802 case Mips::TLBGR_MM: 2803 case Mips::TLBGWI: 2804 case Mips::TLBGWI_MM: 2805 case Mips::TLBGWR: 2806 case Mips::TLBGWR_MM: 2807 case Mips::TLBINV: 2808 case Mips::TLBINVF: 2809 case Mips::TLBINVF_MMR6: 2810 case Mips::TLBINV_MMR6: 2811 case Mips::TLBP: 2812 case Mips::TLBP_MM: 2813 case Mips::TLBR: 2814 case Mips::TLBR_MM: 2815 case Mips::TLBWI: 2816 case Mips::TLBWI_MM: 2817 case Mips::TLBWR: 2818 case Mips::TLBWR_MM: 2819 case Mips::WAIT: { 2820 break; 2821 } 2822 case Mips::MTHLIP: 2823 case Mips::SHILOV: { 2824 // op: ac 2825 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2826 op &= UINT64_C(3); 2827 op <<= 11; 2828 Value |= op; 2829 // op: rs 2830 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2831 op &= UINT64_C(31); 2832 op <<= 21; 2833 Value |= op; 2834 break; 2835 } 2836 case Mips::DPAQX_SA_W_PH: 2837 case Mips::DPAQX_S_W_PH: 2838 case Mips::DPAQ_SA_L_W: 2839 case Mips::DPAQ_S_W_PH: 2840 case Mips::DPAU_H_QBL: 2841 case Mips::DPAU_H_QBR: 2842 case Mips::DPAX_W_PH: 2843 case Mips::DPA_W_PH: 2844 case Mips::DPSQX_SA_W_PH: 2845 case Mips::DPSQX_S_W_PH: 2846 case Mips::DPSQ_SA_L_W: 2847 case Mips::DPSQ_S_W_PH: 2848 case Mips::DPSU_H_QBL: 2849 case Mips::DPSU_H_QBR: 2850 case Mips::DPSX_W_PH: 2851 case Mips::DPS_W_PH: 2852 case Mips::MADDU_DSP: 2853 case Mips::MADD_DSP: 2854 case Mips::MAQ_SA_W_PHL: 2855 case Mips::MAQ_SA_W_PHR: 2856 case Mips::MAQ_S_W_PHL: 2857 case Mips::MAQ_S_W_PHR: 2858 case Mips::MSUBU_DSP: 2859 case Mips::MSUB_DSP: 2860 case Mips::MULSAQ_S_W_PH: 2861 case Mips::MULSA_W_PH: 2862 case Mips::MULTU_DSP: 2863 case Mips::MULT_DSP: { 2864 // op: ac 2865 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2866 op &= UINT64_C(3); 2867 op <<= 11; 2868 Value |= op; 2869 // op: rs 2870 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2871 op &= UINT64_C(31); 2872 op <<= 21; 2873 Value |= op; 2874 // op: rt 2875 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 2876 op &= UINT64_C(31); 2877 op <<= 16; 2878 Value |= op; 2879 break; 2880 } 2881 case Mips::SHILO: { 2882 // op: ac 2883 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2884 op &= UINT64_C(3); 2885 op <<= 11; 2886 Value |= op; 2887 // op: shift 2888 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 2889 op &= UINT64_C(63); 2890 op <<= 20; 2891 Value |= op; 2892 break; 2893 } 2894 case Mips::CACHEE: 2895 case Mips::CACHE_R6: 2896 case Mips::PREFE: 2897 case Mips::PREF_R6: { 2898 // op: addr 2899 op = getMemEncoding(MI, 0, Fixups, STI); 2900 Value |= (op & UINT64_C(2031616)) << 5; 2901 Value |= (op & UINT64_C(511)) << 7; 2902 // op: hint 2903 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 2904 op &= UINT64_C(31); 2905 op <<= 16; 2906 Value |= op; 2907 break; 2908 } 2909 case Mips::SYNCI: { 2910 // op: addr 2911 op = getMemEncoding(MI, 0, Fixups, STI); 2912 Value |= (op & UINT64_C(2031616)) << 5; 2913 Value |= (op & UINT64_C(65535)); 2914 break; 2915 } 2916 case Mips::CACHE: 2917 case Mips::PREF: { 2918 // op: addr 2919 op = getMemEncoding(MI, 0, Fixups, STI); 2920 Value |= (op & UINT64_C(2031616)) << 5; 2921 Value |= (op & UINT64_C(65535)); 2922 // op: hint 2923 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 2924 op &= UINT64_C(31); 2925 op <<= 16; 2926 Value |= op; 2927 break; 2928 } 2929 case Mips::LD_B: 2930 case Mips::ST_B: { 2931 // op: addr 2932 op = getMemEncoding(MI, 1, Fixups, STI); 2933 Value |= (op & UINT64_C(1023)) << 16; 2934 Value |= (op & UINT64_C(2031616)) >> 5; 2935 // op: wd 2936 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2937 op &= UINT64_C(31); 2938 op <<= 6; 2939 Value |= op; 2940 break; 2941 } 2942 case Mips::LBE: 2943 case Mips::LBuE: 2944 case Mips::LHE: 2945 case Mips::LHuE: 2946 case Mips::LLE: 2947 case Mips::LWE: 2948 case Mips::LWLE: 2949 case Mips::LWRE: 2950 case Mips::SBE: 2951 case Mips::SHE: 2952 case Mips::SWE: 2953 case Mips::SWLE: 2954 case Mips::SWRE: { 2955 // op: addr 2956 op = getMemEncoding(MI, 1, Fixups, STI); 2957 Value |= (op & UINT64_C(2031616)) << 5; 2958 Value |= (op & UINT64_C(511)) << 7; 2959 // op: hint 2960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2961 op &= UINT64_C(31); 2962 op <<= 16; 2963 Value |= op; 2964 break; 2965 } 2966 case Mips::SCE: { 2967 // op: addr 2968 op = getMemEncoding(MI, 2, Fixups, STI); 2969 Value |= (op & UINT64_C(2031616)) << 5; 2970 Value |= (op & UINT64_C(511)) << 7; 2971 // op: hint 2972 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2973 op &= UINT64_C(31); 2974 op <<= 16; 2975 Value |= op; 2976 break; 2977 } 2978 case Mips::LD_H: 2979 case Mips::ST_H: { 2980 // op: addr 2981 op = getMemEncoding<1>(MI, 1, Fixups, STI); 2982 Value |= (op & UINT64_C(1023)) << 16; 2983 Value |= (op & UINT64_C(2031616)) >> 5; 2984 // op: wd 2985 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2986 op &= UINT64_C(31); 2987 op <<= 6; 2988 Value |= op; 2989 break; 2990 } 2991 case Mips::LD_W: 2992 case Mips::ST_W: { 2993 // op: addr 2994 op = getMemEncoding<2>(MI, 1, Fixups, STI); 2995 Value |= (op & UINT64_C(1023)) << 16; 2996 Value |= (op & UINT64_C(2031616)) >> 5; 2997 // op: wd 2998 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 2999 op &= UINT64_C(31); 3000 op <<= 6; 3001 Value |= op; 3002 break; 3003 } 3004 case Mips::LD_D: 3005 case Mips::ST_D: { 3006 // op: addr 3007 op = getMemEncoding<3>(MI, 1, Fixups, STI); 3008 Value |= (op & UINT64_C(1023)) << 16; 3009 Value |= (op & UINT64_C(2031616)) >> 5; 3010 // op: wd 3011 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3012 op &= UINT64_C(31); 3013 op <<= 6; 3014 Value |= op; 3015 break; 3016 } 3017 case Mips::CACHE_MM: 3018 case Mips::CACHE_MMR6: 3019 case Mips::PREF_MM: 3020 case Mips::PREF_MMR6: { 3021 // op: addr 3022 op = getMemEncodingMMImm12(MI, 0, Fixups, STI); 3023 Value |= (op & UINT64_C(2031616)); 3024 Value |= (op & UINT64_C(4095)); 3025 // op: hint 3026 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3027 op &= UINT64_C(31); 3028 op <<= 21; 3029 Value |= op; 3030 break; 3031 } 3032 case Mips::SYNCI_MM: 3033 case Mips::SYNCI_MMR6: { 3034 // op: addr 3035 op = getMemEncodingMMImm16(MI, 0, Fixups, STI); 3036 op &= UINT64_C(2097151); 3037 Value |= op; 3038 break; 3039 } 3040 case Mips::LBU_MMR6: 3041 case Mips::LB_MMR6: { 3042 // op: addr 3043 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 3044 op &= UINT64_C(2097151); 3045 Value |= op; 3046 // op: rt 3047 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3048 op &= UINT64_C(31); 3049 op <<= 21; 3050 Value |= op; 3051 break; 3052 } 3053 case Mips::CACHEE_MM: 3054 case Mips::PREFE_MM: { 3055 // op: addr 3056 op = getMemEncodingMMImm9(MI, 0, Fixups, STI); 3057 Value |= (op & UINT64_C(2031616)); 3058 Value |= (op & UINT64_C(511)); 3059 // op: hint 3060 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3061 op &= UINT64_C(31); 3062 op <<= 21; 3063 Value |= op; 3064 break; 3065 } 3066 case Mips::HYPCALL: { 3067 // op: code_ 3068 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3069 op &= UINT64_C(1023); 3070 op <<= 11; 3071 Value |= op; 3072 break; 3073 } 3074 case Mips::HYPCALL_MM: 3075 case Mips::SDBBP_MM: 3076 case Mips::SDBBP_MMR6: 3077 case Mips::SYSCALL_MM: 3078 case Mips::WAIT_MM: 3079 case Mips::WAIT_MMR6: { 3080 // op: code_ 3081 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3082 op &= UINT64_C(1023); 3083 op <<= 16; 3084 Value |= op; 3085 break; 3086 } 3087 case Mips::SDBBP: 3088 case Mips::SDBBP_R6: 3089 case Mips::SYSCALL: { 3090 // op: code_ 3091 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3092 op &= UINT64_C(1048575); 3093 op <<= 6; 3094 Value |= op; 3095 break; 3096 } 3097 case Mips::BREAK16_MM: 3098 case Mips::SDBBP16_MM: { 3099 // op: code_ 3100 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3101 op &= UINT64_C(15); 3102 Value |= op; 3103 break; 3104 } 3105 case Mips::BREAK16_MMR6: 3106 case Mips::SDBBP16_MMR6: { 3107 // op: code_ 3108 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3109 op &= UINT64_C(15); 3110 op <<= 6; 3111 Value |= op; 3112 break; 3113 } 3114 case Mips::SIGRIE: { 3115 // op: code_ 3116 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3117 op &= UINT64_C(65535); 3118 Value |= op; 3119 break; 3120 } 3121 case Mips::SIGRIE_MMR6: { 3122 // op: code_ 3123 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3124 op &= UINT64_C(65535); 3125 op <<= 6; 3126 Value |= op; 3127 break; 3128 } 3129 case Mips::BREAK: 3130 case Mips::BREAK_MM: 3131 case Mips::BREAK_MMR6: { 3132 // op: code_1 3133 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3134 op &= UINT64_C(1023); 3135 op <<= 16; 3136 Value |= op; 3137 // op: code_2 3138 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3139 op &= UINT64_C(1023); 3140 op <<= 6; 3141 Value |= op; 3142 break; 3143 } 3144 case Mips::BC2EQZ: 3145 case Mips::BC2NEZ: { 3146 // op: ct 3147 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3148 op &= UINT64_C(31); 3149 op <<= 16; 3150 Value |= op; 3151 // op: offset 3152 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3153 op &= UINT64_C(65535); 3154 Value |= op; 3155 break; 3156 } 3157 case Mips::MOVEP_MMR6: { 3158 // op: dst_regs 3159 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3160 op &= UINT64_C(7); 3161 op <<= 7; 3162 Value |= op; 3163 // op: rt 3164 op = getMovePRegSingleOpValue(MI, 3, Fixups, STI); 3165 op &= UINT64_C(7); 3166 op <<= 4; 3167 Value |= op; 3168 // op: rs 3169 op = getMovePRegSingleOpValue(MI, 2, Fixups, STI); 3170 Value |= (op & UINT64_C(4)) << 1; 3171 Value |= (op & UINT64_C(3)); 3172 break; 3173 } 3174 case Mips::MOVEP_MM: { 3175 // op: dst_regs 3176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3177 op &= UINT64_C(7); 3178 op <<= 7; 3179 Value |= op; 3180 // op: rt 3181 op = getMovePRegSingleOpValue(MI, 3, Fixups, STI); 3182 op &= UINT64_C(7); 3183 op <<= 4; 3184 Value |= op; 3185 // op: rs 3186 op = getMovePRegSingleOpValue(MI, 2, Fixups, STI); 3187 op &= UINT64_C(7); 3188 op <<= 1; 3189 Value |= op; 3190 break; 3191 } 3192 case Mips::BC1F: 3193 case Mips::BC1FL: 3194 case Mips::BC1T: 3195 case Mips::BC1TL: { 3196 // op: fcc 3197 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3198 op &= UINT64_C(7); 3199 op <<= 18; 3200 Value |= op; 3201 // op: offset 3202 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3203 op &= UINT64_C(65535); 3204 Value |= op; 3205 break; 3206 } 3207 case Mips::BC1F_MM: 3208 case Mips::BC1T_MM: { 3209 // op: fcc 3210 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3211 op &= UINT64_C(7); 3212 op <<= 18; 3213 Value |= op; 3214 // op: offset 3215 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 3216 op &= UINT64_C(65535); 3217 Value |= op; 3218 break; 3219 } 3220 case Mips::LUXC1_MM: 3221 case Mips::LWXC1_MM: { 3222 // op: fd 3223 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3224 op &= UINT64_C(31); 3225 op <<= 11; 3226 Value |= op; 3227 // op: base 3228 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3229 op &= UINT64_C(31); 3230 op <<= 16; 3231 Value |= op; 3232 // op: index 3233 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3234 op &= UINT64_C(31); 3235 op <<= 21; 3236 Value |= op; 3237 break; 3238 } 3239 case Mips::MOVN_I_D32_MM: 3240 case Mips::MOVN_I_S_MM: 3241 case Mips::MOVZ_I_D32_MM: 3242 case Mips::MOVZ_I_S_MM: { 3243 // op: fd 3244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3245 op &= UINT64_C(31); 3246 op <<= 11; 3247 Value |= op; 3248 // op: fs 3249 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3250 op &= UINT64_C(31); 3251 op <<= 16; 3252 Value |= op; 3253 // op: rt 3254 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3255 op &= UINT64_C(31); 3256 op <<= 21; 3257 Value |= op; 3258 break; 3259 } 3260 case Mips::CEIL_W_MM: 3261 case Mips::CEIL_W_S_MM: 3262 case Mips::CVT_D32_S_MM: 3263 case Mips::CVT_D32_W_MM: 3264 case Mips::CVT_D64_S_MM: 3265 case Mips::CVT_D64_W_MM: 3266 case Mips::CVT_L_D64_MM: 3267 case Mips::CVT_L_S_MM: 3268 case Mips::CVT_S_D32_MM: 3269 case Mips::CVT_S_D64_MM: 3270 case Mips::CVT_S_W_MM: 3271 case Mips::CVT_W_D32_MM: 3272 case Mips::CVT_W_D64_MM: 3273 case Mips::CVT_W_S_MM: 3274 case Mips::FABS_D32_MM: 3275 case Mips::FABS_D64_MM: 3276 case Mips::FABS_S_MM: 3277 case Mips::FLOOR_W_MM: 3278 case Mips::FLOOR_W_S_MM: 3279 case Mips::FMOV_D32_MM: 3280 case Mips::FMOV_D64_MM: 3281 case Mips::FMOV_S_MM: 3282 case Mips::FNEG_D32_MM: 3283 case Mips::FNEG_D64_MM: 3284 case Mips::FNEG_S_MM: 3285 case Mips::FSQRT_D32_MM: 3286 case Mips::FSQRT_D64_MM: 3287 case Mips::FSQRT_S_MM: 3288 case Mips::RECIP_D32_MM: 3289 case Mips::RECIP_D64_MM: 3290 case Mips::RECIP_S_MM: 3291 case Mips::ROUND_W_MM: 3292 case Mips::ROUND_W_S_MM: 3293 case Mips::RSQRT_D32_MM: 3294 case Mips::RSQRT_D64_MM: 3295 case Mips::RSQRT_S_MM: 3296 case Mips::TRUNC_W_MM: 3297 case Mips::TRUNC_W_S_MM: { 3298 // op: fd 3299 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3300 op &= UINT64_C(31); 3301 op <<= 21; 3302 Value |= op; 3303 // op: fs 3304 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3305 op &= UINT64_C(31); 3306 op <<= 16; 3307 Value |= op; 3308 break; 3309 } 3310 case Mips::MOVF_D32_MM: 3311 case Mips::MOVF_S_MM: 3312 case Mips::MOVT_D32_MM: 3313 case Mips::MOVT_S_MM: { 3314 // op: fd 3315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3316 op &= UINT64_C(31); 3317 op <<= 21; 3318 Value |= op; 3319 // op: fs 3320 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3321 op &= UINT64_C(31); 3322 op <<= 16; 3323 Value |= op; 3324 // op: fcc 3325 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3326 op &= UINT64_C(7); 3327 op <<= 13; 3328 Value |= op; 3329 break; 3330 } 3331 case Mips::LDXC1: 3332 case Mips::LDXC164: 3333 case Mips::LUXC1: 3334 case Mips::LUXC164: 3335 case Mips::LWXC1: { 3336 // op: fd 3337 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3338 op &= UINT64_C(31); 3339 op <<= 6; 3340 Value |= op; 3341 // op: base 3342 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3343 op &= UINT64_C(31); 3344 op <<= 21; 3345 Value |= op; 3346 // op: index 3347 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3348 op &= UINT64_C(31); 3349 op <<= 16; 3350 Value |= op; 3351 break; 3352 } 3353 case Mips::MADD_D32: 3354 case Mips::MADD_D64: 3355 case Mips::MADD_S: 3356 case Mips::MSUB_D32: 3357 case Mips::MSUB_D64: 3358 case Mips::MSUB_S: 3359 case Mips::NMADD_D32: 3360 case Mips::NMADD_D64: 3361 case Mips::NMADD_S: 3362 case Mips::NMSUB_D32: 3363 case Mips::NMSUB_D64: 3364 case Mips::NMSUB_S: { 3365 // op: fd 3366 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3367 op &= UINT64_C(31); 3368 op <<= 6; 3369 Value |= op; 3370 // op: fr 3371 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3372 op &= UINT64_C(31); 3373 op <<= 21; 3374 Value |= op; 3375 // op: fs 3376 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3377 op &= UINT64_C(31); 3378 op <<= 11; 3379 Value |= op; 3380 // op: ft 3381 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3382 op &= UINT64_C(31); 3383 op <<= 16; 3384 Value |= op; 3385 break; 3386 } 3387 case Mips::CEIL_L_D64: 3388 case Mips::CEIL_L_S: 3389 case Mips::CEIL_W_D32: 3390 case Mips::CEIL_W_D64: 3391 case Mips::CEIL_W_S: 3392 case Mips::CVT_D32_S: 3393 case Mips::CVT_D32_W: 3394 case Mips::CVT_D64_L: 3395 case Mips::CVT_D64_S: 3396 case Mips::CVT_D64_W: 3397 case Mips::CVT_L_D64: 3398 case Mips::CVT_L_S: 3399 case Mips::CVT_S_D32: 3400 case Mips::CVT_S_D64: 3401 case Mips::CVT_S_L: 3402 case Mips::CVT_S_PL64: 3403 case Mips::CVT_S_PU64: 3404 case Mips::CVT_S_W: 3405 case Mips::CVT_W_D32: 3406 case Mips::CVT_W_D64: 3407 case Mips::CVT_W_S: 3408 case Mips::FABS_D32: 3409 case Mips::FABS_D64: 3410 case Mips::FABS_S: 3411 case Mips::FLOOR_L_D64: 3412 case Mips::FLOOR_L_S: 3413 case Mips::FLOOR_W_D32: 3414 case Mips::FLOOR_W_D64: 3415 case Mips::FLOOR_W_S: 3416 case Mips::FMOV_D32: 3417 case Mips::FMOV_D64: 3418 case Mips::FMOV_S: 3419 case Mips::FNEG_D32: 3420 case Mips::FNEG_D64: 3421 case Mips::FNEG_S: 3422 case Mips::FSQRT_D32: 3423 case Mips::FSQRT_D64: 3424 case Mips::FSQRT_S: 3425 case Mips::RECIP_D32: 3426 case Mips::RECIP_D64: 3427 case Mips::RECIP_S: 3428 case Mips::ROUND_L_D64: 3429 case Mips::ROUND_L_S: 3430 case Mips::ROUND_W_D32: 3431 case Mips::ROUND_W_D64: 3432 case Mips::ROUND_W_S: 3433 case Mips::RSQRT_D32: 3434 case Mips::RSQRT_D64: 3435 case Mips::RSQRT_S: 3436 case Mips::TRUNC_L_D64: 3437 case Mips::TRUNC_L_S: 3438 case Mips::TRUNC_W_D32: 3439 case Mips::TRUNC_W_D64: 3440 case Mips::TRUNC_W_S: { 3441 // op: fd 3442 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3443 op &= UINT64_C(31); 3444 op <<= 6; 3445 Value |= op; 3446 // op: fs 3447 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3448 op &= UINT64_C(31); 3449 op <<= 11; 3450 Value |= op; 3451 break; 3452 } 3453 case Mips::MOVF_D32: 3454 case Mips::MOVF_D64: 3455 case Mips::MOVF_S: 3456 case Mips::MOVT_D32: 3457 case Mips::MOVT_D64: 3458 case Mips::MOVT_S: { 3459 // op: fd 3460 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3461 op &= UINT64_C(31); 3462 op <<= 6; 3463 Value |= op; 3464 // op: fs 3465 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3466 op &= UINT64_C(31); 3467 op <<= 11; 3468 Value |= op; 3469 // op: fcc 3470 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3471 op &= UINT64_C(7); 3472 op <<= 18; 3473 Value |= op; 3474 break; 3475 } 3476 case Mips::CMP_EQ_D: 3477 case Mips::CMP_EQ_S: 3478 case Mips::CMP_F_D: 3479 case Mips::CMP_F_S: 3480 case Mips::CMP_LE_D: 3481 case Mips::CMP_LE_S: 3482 case Mips::CMP_LT_D: 3483 case Mips::CMP_LT_S: 3484 case Mips::CMP_SAF_D: 3485 case Mips::CMP_SAF_S: 3486 case Mips::CMP_SEQ_D: 3487 case Mips::CMP_SEQ_S: 3488 case Mips::CMP_SLE_D: 3489 case Mips::CMP_SLE_S: 3490 case Mips::CMP_SLT_D: 3491 case Mips::CMP_SLT_S: 3492 case Mips::CMP_SUEQ_D: 3493 case Mips::CMP_SUEQ_S: 3494 case Mips::CMP_SULE_D: 3495 case Mips::CMP_SULE_S: 3496 case Mips::CMP_SULT_D: 3497 case Mips::CMP_SULT_S: 3498 case Mips::CMP_SUN_D: 3499 case Mips::CMP_SUN_S: 3500 case Mips::CMP_UEQ_D: 3501 case Mips::CMP_UEQ_S: 3502 case Mips::CMP_ULE_D: 3503 case Mips::CMP_ULE_S: 3504 case Mips::CMP_ULT_D: 3505 case Mips::CMP_ULT_S: 3506 case Mips::CMP_UN_D: 3507 case Mips::CMP_UN_S: 3508 case Mips::CVT_PS_S64: 3509 case Mips::FADD_D32: 3510 case Mips::FADD_D64: 3511 case Mips::FADD_S: 3512 case Mips::FDIV_D32: 3513 case Mips::FDIV_D64: 3514 case Mips::FDIV_S: 3515 case Mips::FMUL_D32: 3516 case Mips::FMUL_D64: 3517 case Mips::FMUL_S: 3518 case Mips::FSUB_D32: 3519 case Mips::FSUB_D64: 3520 case Mips::FSUB_S: 3521 case Mips::PLL_PS64: 3522 case Mips::PLU_PS64: { 3523 // op: fd 3524 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3525 op &= UINT64_C(31); 3526 op <<= 6; 3527 Value |= op; 3528 // op: fs 3529 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3530 op &= UINT64_C(31); 3531 op <<= 11; 3532 Value |= op; 3533 // op: ft 3534 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3535 op &= UINT64_C(31); 3536 op <<= 16; 3537 Value |= op; 3538 break; 3539 } 3540 case Mips::MOVN_I64_D64: 3541 case Mips::MOVN_I64_S: 3542 case Mips::MOVN_I_D32: 3543 case Mips::MOVN_I_D64: 3544 case Mips::MOVN_I_S: 3545 case Mips::MOVZ_I64_D64: 3546 case Mips::MOVZ_I64_S: 3547 case Mips::MOVZ_I_D32: 3548 case Mips::MOVZ_I_D64: 3549 case Mips::MOVZ_I_S: { 3550 // op: fd 3551 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3552 op &= UINT64_C(31); 3553 op <<= 6; 3554 Value |= op; 3555 // op: fs 3556 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3557 op &= UINT64_C(31); 3558 op <<= 11; 3559 Value |= op; 3560 // op: rt 3561 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3562 op &= UINT64_C(31); 3563 op <<= 16; 3564 Value |= op; 3565 break; 3566 } 3567 case Mips::SUXC1_MM: 3568 case Mips::SWXC1_MM: { 3569 // op: fs 3570 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3571 op &= UINT64_C(31); 3572 op <<= 11; 3573 Value |= op; 3574 // op: base 3575 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3576 op &= UINT64_C(31); 3577 op <<= 16; 3578 Value |= op; 3579 // op: index 3580 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3581 op &= UINT64_C(31); 3582 op <<= 21; 3583 Value |= op; 3584 break; 3585 } 3586 case Mips::SDXC1: 3587 case Mips::SDXC164: 3588 case Mips::SUXC1: 3589 case Mips::SUXC164: 3590 case Mips::SWXC1: { 3591 // op: fs 3592 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3593 op &= UINT64_C(31); 3594 op <<= 11; 3595 Value |= op; 3596 // op: base 3597 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3598 op &= UINT64_C(31); 3599 op <<= 21; 3600 Value |= op; 3601 // op: index 3602 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3603 op &= UINT64_C(31); 3604 op <<= 16; 3605 Value |= op; 3606 break; 3607 } 3608 case Mips::FCMP_D32: 3609 case Mips::FCMP_D64: 3610 case Mips::FCMP_S32: { 3611 // op: fs 3612 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3613 op &= UINT64_C(31); 3614 op <<= 11; 3615 Value |= op; 3616 // op: ft 3617 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3618 op &= UINT64_C(31); 3619 op <<= 16; 3620 Value |= op; 3621 // op: cond 3622 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3623 op &= UINT64_C(15); 3624 Value |= op; 3625 break; 3626 } 3627 case Mips::FCMP_D32_MM: 3628 case Mips::FCMP_S32_MM: { 3629 // op: fs 3630 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3631 op &= UINT64_C(31); 3632 op <<= 16; 3633 Value |= op; 3634 // op: ft 3635 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3636 op &= UINT64_C(31); 3637 op <<= 21; 3638 Value |= op; 3639 // op: cond 3640 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3641 op &= UINT64_C(15); 3642 op <<= 6; 3643 Value |= op; 3644 break; 3645 } 3646 case Mips::CLASS_D: 3647 case Mips::CLASS_S: 3648 case Mips::RINT_D: 3649 case Mips::RINT_S: { 3650 // op: fs 3651 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3652 op &= UINT64_C(31); 3653 op <<= 11; 3654 Value |= op; 3655 // op: fd 3656 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3657 op &= UINT64_C(31); 3658 op <<= 6; 3659 Value |= op; 3660 break; 3661 } 3662 case Mips::C_EQ_D32: 3663 case Mips::C_EQ_D64: 3664 case Mips::C_EQ_S: 3665 case Mips::C_F_D32: 3666 case Mips::C_F_D64: 3667 case Mips::C_F_S: 3668 case Mips::C_LE_D32: 3669 case Mips::C_LE_D64: 3670 case Mips::C_LE_S: 3671 case Mips::C_LT_D32: 3672 case Mips::C_LT_D64: 3673 case Mips::C_LT_S: 3674 case Mips::C_NGE_D32: 3675 case Mips::C_NGE_D64: 3676 case Mips::C_NGE_S: 3677 case Mips::C_NGLE_D32: 3678 case Mips::C_NGLE_D64: 3679 case Mips::C_NGLE_S: 3680 case Mips::C_NGL_D32: 3681 case Mips::C_NGL_D64: 3682 case Mips::C_NGL_S: 3683 case Mips::C_NGT_D32: 3684 case Mips::C_NGT_D64: 3685 case Mips::C_NGT_S: 3686 case Mips::C_OLE_D32: 3687 case Mips::C_OLE_D64: 3688 case Mips::C_OLE_S: 3689 case Mips::C_OLT_D32: 3690 case Mips::C_OLT_D64: 3691 case Mips::C_OLT_S: 3692 case Mips::C_SEQ_D32: 3693 case Mips::C_SEQ_D64: 3694 case Mips::C_SEQ_S: 3695 case Mips::C_SF_D32: 3696 case Mips::C_SF_D64: 3697 case Mips::C_SF_S: 3698 case Mips::C_UEQ_D32: 3699 case Mips::C_UEQ_D64: 3700 case Mips::C_UEQ_S: 3701 case Mips::C_ULE_D32: 3702 case Mips::C_ULE_D64: 3703 case Mips::C_ULE_S: 3704 case Mips::C_ULT_D32: 3705 case Mips::C_ULT_D64: 3706 case Mips::C_ULT_S: 3707 case Mips::C_UN_D32: 3708 case Mips::C_UN_D64: 3709 case Mips::C_UN_S: { 3710 // op: fs 3711 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3712 op &= UINT64_C(31); 3713 op <<= 11; 3714 Value |= op; 3715 // op: ft 3716 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3717 op &= UINT64_C(31); 3718 op <<= 16; 3719 Value |= op; 3720 // op: fcc 3721 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3722 op &= UINT64_C(7); 3723 op <<= 8; 3724 Value |= op; 3725 break; 3726 } 3727 case Mips::C_EQ_D32_MM: 3728 case Mips::C_EQ_D64_MM: 3729 case Mips::C_EQ_S_MM: 3730 case Mips::C_F_D32_MM: 3731 case Mips::C_F_D64_MM: 3732 case Mips::C_F_S_MM: 3733 case Mips::C_LE_D32_MM: 3734 case Mips::C_LE_D64_MM: 3735 case Mips::C_LE_S_MM: 3736 case Mips::C_LT_D32_MM: 3737 case Mips::C_LT_D64_MM: 3738 case Mips::C_LT_S_MM: 3739 case Mips::C_NGE_D32_MM: 3740 case Mips::C_NGE_D64_MM: 3741 case Mips::C_NGE_S_MM: 3742 case Mips::C_NGLE_D32_MM: 3743 case Mips::C_NGLE_D64_MM: 3744 case Mips::C_NGLE_S_MM: 3745 case Mips::C_NGL_D32_MM: 3746 case Mips::C_NGL_D64_MM: 3747 case Mips::C_NGL_S_MM: 3748 case Mips::C_NGT_D32_MM: 3749 case Mips::C_NGT_D64_MM: 3750 case Mips::C_NGT_S_MM: 3751 case Mips::C_OLE_D32_MM: 3752 case Mips::C_OLE_D64_MM: 3753 case Mips::C_OLE_S_MM: 3754 case Mips::C_OLT_D32_MM: 3755 case Mips::C_OLT_D64_MM: 3756 case Mips::C_OLT_S_MM: 3757 case Mips::C_SEQ_D32_MM: 3758 case Mips::C_SEQ_D64_MM: 3759 case Mips::C_SEQ_S_MM: 3760 case Mips::C_SF_D32_MM: 3761 case Mips::C_SF_D64_MM: 3762 case Mips::C_SF_S_MM: 3763 case Mips::C_UEQ_D32_MM: 3764 case Mips::C_UEQ_D64_MM: 3765 case Mips::C_UEQ_S_MM: 3766 case Mips::C_ULE_D32_MM: 3767 case Mips::C_ULE_D64_MM: 3768 case Mips::C_ULE_S_MM: 3769 case Mips::C_ULT_D32_MM: 3770 case Mips::C_ULT_D64_MM: 3771 case Mips::C_ULT_S_MM: 3772 case Mips::C_UN_D32_MM: 3773 case Mips::C_UN_D64_MM: 3774 case Mips::C_UN_S_MM: { 3775 // op: fs 3776 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3777 op &= UINT64_C(31); 3778 op <<= 16; 3779 Value |= op; 3780 // op: ft 3781 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3782 op &= UINT64_C(31); 3783 op <<= 21; 3784 Value |= op; 3785 // op: fcc 3786 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3787 op &= UINT64_C(7); 3788 op <<= 13; 3789 Value |= op; 3790 break; 3791 } 3792 case Mips::CLASS_D_MMR6: 3793 case Mips::CLASS_S_MMR6: 3794 case Mips::RINT_D_MMR6: 3795 case Mips::RINT_S_MMR6: { 3796 // op: fs 3797 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3798 op &= UINT64_C(31); 3799 op <<= 21; 3800 Value |= op; 3801 // op: fd 3802 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3803 op &= UINT64_C(31); 3804 op <<= 16; 3805 Value |= op; 3806 break; 3807 } 3808 case Mips::BC1EQZ: 3809 case Mips::BC1NEZ: { 3810 // op: ft 3811 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3812 op &= UINT64_C(31); 3813 op <<= 16; 3814 Value |= op; 3815 // op: offset 3816 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 3817 op &= UINT64_C(65535); 3818 Value |= op; 3819 break; 3820 } 3821 case Mips::LDC1_D64_MMR6: 3822 case Mips::SDC1_D64_MMR6: { 3823 // op: ft 3824 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3825 op &= UINT64_C(31); 3826 op <<= 21; 3827 Value |= op; 3828 // op: addr 3829 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 3830 op &= UINT64_C(2097151); 3831 Value |= op; 3832 break; 3833 } 3834 case Mips::CEIL_L_D_MMR6: 3835 case Mips::CEIL_L_S_MMR6: 3836 case Mips::CEIL_W_D_MMR6: 3837 case Mips::CEIL_W_S_MMR6: 3838 case Mips::CVT_D_L_MMR6: 3839 case Mips::CVT_L_D_MMR6: 3840 case Mips::CVT_L_S_MMR6: 3841 case Mips::CVT_S_L_MMR6: 3842 case Mips::CVT_S_W_MMR6: 3843 case Mips::CVT_W_S_MMR6: 3844 case Mips::FLOOR_L_D_MMR6: 3845 case Mips::FLOOR_L_S_MMR6: 3846 case Mips::FLOOR_W_D_MMR6: 3847 case Mips::FLOOR_W_S_MMR6: 3848 case Mips::FMOV_D_MMR6: 3849 case Mips::FMOV_S_MMR6: 3850 case Mips::FNEG_S_MMR6: 3851 case Mips::ROUND_L_D_MMR6: 3852 case Mips::ROUND_L_S_MMR6: 3853 case Mips::ROUND_W_D_MMR6: 3854 case Mips::ROUND_W_S_MMR6: 3855 case Mips::TRUNC_L_D_MMR6: 3856 case Mips::TRUNC_L_S_MMR6: 3857 case Mips::TRUNC_W_D_MMR6: 3858 case Mips::TRUNC_W_S_MMR6: { 3859 // op: ft 3860 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3861 op &= UINT64_C(31); 3862 op <<= 21; 3863 Value |= op; 3864 // op: fs 3865 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3866 op &= UINT64_C(31); 3867 op <<= 16; 3868 Value |= op; 3869 break; 3870 } 3871 case Mips::FADD_S_MMR6: 3872 case Mips::FDIV_S_MMR6: 3873 case Mips::FMUL_S_MMR6: 3874 case Mips::FSUB_S_MMR6: { 3875 // op: ft 3876 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3877 op &= UINT64_C(31); 3878 op <<= 21; 3879 Value |= op; 3880 // op: fs 3881 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3882 op &= UINT64_C(31); 3883 op <<= 16; 3884 Value |= op; 3885 // op: fd 3886 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3887 op &= UINT64_C(31); 3888 op <<= 11; 3889 Value |= op; 3890 break; 3891 } 3892 case Mips::MAXA_D: 3893 case Mips::MAXA_S: 3894 case Mips::MAX_D: 3895 case Mips::MAX_S: 3896 case Mips::MINA_D: 3897 case Mips::MINA_S: 3898 case Mips::MIN_D: 3899 case Mips::MIN_S: 3900 case Mips::SELEQZ_D: 3901 case Mips::SELEQZ_S: 3902 case Mips::SELNEZ_D: 3903 case Mips::SELNEZ_S: { 3904 // op: ft 3905 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3906 op &= UINT64_C(31); 3907 op <<= 16; 3908 Value |= op; 3909 // op: fs 3910 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3911 op &= UINT64_C(31); 3912 op <<= 11; 3913 Value |= op; 3914 // op: fd 3915 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3916 op &= UINT64_C(31); 3917 op <<= 6; 3918 Value |= op; 3919 break; 3920 } 3921 case Mips::CMP_AF_D_MMR6: 3922 case Mips::CMP_AF_S_MMR6: 3923 case Mips::CMP_EQ_D_MMR6: 3924 case Mips::CMP_EQ_S_MMR6: 3925 case Mips::CMP_LE_D_MMR6: 3926 case Mips::CMP_LE_S_MMR6: 3927 case Mips::CMP_LT_D_MMR6: 3928 case Mips::CMP_LT_S_MMR6: 3929 case Mips::CMP_SAF_D_MMR6: 3930 case Mips::CMP_SAF_S_MMR6: 3931 case Mips::CMP_SEQ_D_MMR6: 3932 case Mips::CMP_SEQ_S_MMR6: 3933 case Mips::CMP_SLE_D_MMR6: 3934 case Mips::CMP_SLE_S_MMR6: 3935 case Mips::CMP_SLT_D_MMR6: 3936 case Mips::CMP_SLT_S_MMR6: 3937 case Mips::CMP_SUEQ_D_MMR6: 3938 case Mips::CMP_SUEQ_S_MMR6: 3939 case Mips::CMP_SULE_D_MMR6: 3940 case Mips::CMP_SULE_S_MMR6: 3941 case Mips::CMP_SULT_D_MMR6: 3942 case Mips::CMP_SULT_S_MMR6: 3943 case Mips::CMP_SUN_D_MMR6: 3944 case Mips::CMP_SUN_S_MMR6: 3945 case Mips::CMP_UEQ_D_MMR6: 3946 case Mips::CMP_UEQ_S_MMR6: 3947 case Mips::CMP_ULE_D_MMR6: 3948 case Mips::CMP_ULE_S_MMR6: 3949 case Mips::CMP_ULT_D_MMR6: 3950 case Mips::CMP_ULT_S_MMR6: 3951 case Mips::CMP_UN_D_MMR6: 3952 case Mips::CMP_UN_S_MMR6: 3953 case Mips::FADD_D32_MM: 3954 case Mips::FADD_D64_MM: 3955 case Mips::FADD_S_MM: 3956 case Mips::FDIV_D32_MM: 3957 case Mips::FDIV_D64_MM: 3958 case Mips::FDIV_S_MM: 3959 case Mips::FMUL_D32_MM: 3960 case Mips::FMUL_D64_MM: 3961 case Mips::FMUL_S_MM: 3962 case Mips::FSUB_D32_MM: 3963 case Mips::FSUB_D64_MM: 3964 case Mips::FSUB_S_MM: 3965 case Mips::MAXA_D_MMR6: 3966 case Mips::MAXA_S_MMR6: 3967 case Mips::MAX_D_MMR6: 3968 case Mips::MAX_S_MMR6: 3969 case Mips::MINA_D_MMR6: 3970 case Mips::MINA_S_MMR6: 3971 case Mips::MIN_D_MMR6: 3972 case Mips::MIN_S_MMR6: 3973 case Mips::SELEQZ_D_MMR6: 3974 case Mips::SELEQZ_S_MMR6: 3975 case Mips::SELNEZ_D_MMR6: 3976 case Mips::SELNEZ_S_MMR6: { 3977 // op: ft 3978 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3979 op &= UINT64_C(31); 3980 op <<= 21; 3981 Value |= op; 3982 // op: fs 3983 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3984 op &= UINT64_C(31); 3985 op <<= 16; 3986 Value |= op; 3987 // op: fd 3988 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3989 op &= UINT64_C(31); 3990 op <<= 11; 3991 Value |= op; 3992 break; 3993 } 3994 case Mips::MADDF_D: 3995 case Mips::MADDF_S: 3996 case Mips::MSUBF_D: 3997 case Mips::MSUBF_S: 3998 case Mips::SEL_D: 3999 case Mips::SEL_S: { 4000 // op: ft 4001 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4002 op &= UINT64_C(31); 4003 op <<= 16; 4004 Value |= op; 4005 // op: fs 4006 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4007 op &= UINT64_C(31); 4008 op <<= 11; 4009 Value |= op; 4010 // op: fd 4011 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4012 op &= UINT64_C(31); 4013 op <<= 6; 4014 Value |= op; 4015 break; 4016 } 4017 case Mips::MADDF_D_MMR6: 4018 case Mips::MADDF_S_MMR6: 4019 case Mips::MSUBF_D_MMR6: 4020 case Mips::MSUBF_S_MMR6: 4021 case Mips::SEL_D_MMR6: 4022 case Mips::SEL_S_MMR6: { 4023 // op: ft 4024 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4025 op &= UINT64_C(31); 4026 op <<= 21; 4027 Value |= op; 4028 // op: fs 4029 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4030 op &= UINT64_C(31); 4031 op <<= 16; 4032 Value |= op; 4033 // op: fd 4034 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4035 op &= UINT64_C(31); 4036 op <<= 11; 4037 Value |= op; 4038 break; 4039 } 4040 case Mips::MADD_D32_MM: 4041 case Mips::MADD_S_MM: 4042 case Mips::MSUB_D32_MM: 4043 case Mips::MSUB_S_MM: 4044 case Mips::NMADD_D32_MM: 4045 case Mips::NMADD_S_MM: 4046 case Mips::NMSUB_D32_MM: 4047 case Mips::NMSUB_S_MM: { 4048 // op: ft 4049 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4050 op &= UINT64_C(31); 4051 op <<= 21; 4052 Value |= op; 4053 // op: fs 4054 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4055 op &= UINT64_C(31); 4056 op <<= 16; 4057 Value |= op; 4058 // op: fd 4059 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4060 op &= UINT64_C(31); 4061 op <<= 11; 4062 Value |= op; 4063 // op: fr 4064 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4065 op &= UINT64_C(31); 4066 op <<= 6; 4067 Value |= op; 4068 break; 4069 } 4070 case Mips::ADDVI_B: 4071 case Mips::ADDVI_D: 4072 case Mips::ADDVI_H: 4073 case Mips::ADDVI_W: 4074 case Mips::CEQI_B: 4075 case Mips::CEQI_D: 4076 case Mips::CEQI_H: 4077 case Mips::CEQI_W: 4078 case Mips::CLEI_S_B: 4079 case Mips::CLEI_S_D: 4080 case Mips::CLEI_S_H: 4081 case Mips::CLEI_S_W: 4082 case Mips::CLEI_U_B: 4083 case Mips::CLEI_U_D: 4084 case Mips::CLEI_U_H: 4085 case Mips::CLEI_U_W: 4086 case Mips::CLTI_S_B: 4087 case Mips::CLTI_S_D: 4088 case Mips::CLTI_S_H: 4089 case Mips::CLTI_S_W: 4090 case Mips::CLTI_U_B: 4091 case Mips::CLTI_U_D: 4092 case Mips::CLTI_U_H: 4093 case Mips::CLTI_U_W: 4094 case Mips::MAXI_S_B: 4095 case Mips::MAXI_S_D: 4096 case Mips::MAXI_S_H: 4097 case Mips::MAXI_S_W: 4098 case Mips::MAXI_U_B: 4099 case Mips::MAXI_U_D: 4100 case Mips::MAXI_U_H: 4101 case Mips::MAXI_U_W: 4102 case Mips::MINI_S_B: 4103 case Mips::MINI_S_D: 4104 case Mips::MINI_S_H: 4105 case Mips::MINI_S_W: 4106 case Mips::MINI_U_B: 4107 case Mips::MINI_U_D: 4108 case Mips::MINI_U_H: 4109 case Mips::MINI_U_W: 4110 case Mips::SUBVI_B: 4111 case Mips::SUBVI_D: 4112 case Mips::SUBVI_H: 4113 case Mips::SUBVI_W: { 4114 // op: imm 4115 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4116 op &= UINT64_C(31); 4117 op <<= 16; 4118 Value |= op; 4119 // op: ws 4120 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4121 op &= UINT64_C(31); 4122 op <<= 11; 4123 Value |= op; 4124 // op: wd 4125 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4126 op &= UINT64_C(31); 4127 op <<= 6; 4128 Value |= op; 4129 break; 4130 } 4131 case Mips::ADDIUSP_MM: { 4132 // op: imm 4133 op = getSImm9AddiuspValue(MI, 0, Fixups, STI); 4134 op &= UINT64_C(511); 4135 op <<= 1; 4136 Value |= op; 4137 break; 4138 } 4139 case Mips::JRADDIUSP: { 4140 // op: imm 4141 op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI); 4142 op &= UINT64_C(31); 4143 Value |= op; 4144 break; 4145 } 4146 case Mips::JRCADDIUSP_MMR6: { 4147 // op: imm 4148 op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI); 4149 op &= UINT64_C(31); 4150 op <<= 5; 4151 Value |= op; 4152 break; 4153 } 4154 case Mips::Bimm16: { 4155 // op: imm11 4156 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4157 op &= UINT64_C(2047); 4158 Value |= op; 4159 break; 4160 } 4161 case Mips::AddiuRxRyOffMemX16: { 4162 // op: imm15 4163 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4164 Value |= (op & UINT64_C(2032)) << 16; 4165 Value |= (op & UINT64_C(30720)) << 5; 4166 Value |= (op & UINT64_C(15)); 4167 // op: rx 4168 op = getMemEncoding(MI, 1, Fixups, STI); 4169 op &= UINT64_C(7); 4170 op <<= 8; 4171 Value |= op; 4172 // op: ry 4173 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4174 op &= UINT64_C(7); 4175 op <<= 5; 4176 Value |= op; 4177 break; 4178 } 4179 case Mips::BimmX16: { 4180 // op: imm16 4181 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4182 Value |= (op & UINT64_C(2016)) << 16; 4183 Value |= (op & UINT64_C(63488)) << 5; 4184 Value |= (op & UINT64_C(31)); 4185 break; 4186 } 4187 case Mips::AddiuSpImmX16: 4188 case Mips::BteqzX16: 4189 case Mips::BtnezX16: { 4190 // op: imm16 4191 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4192 Value |= (op & UINT64_C(2016)) << 16; 4193 Value |= (op & UINT64_C(63488)) << 5; 4194 Value |= (op & UINT64_C(31)); 4195 break; 4196 } 4197 case Mips::AddiuRxImmX16: 4198 case Mips::AddiuRxPcImmX16: 4199 case Mips::AddiuRxRxImmX16: 4200 case Mips::BeqzRxImmX16: 4201 case Mips::BnezRxImmX16: 4202 case Mips::CmpiRxImmX16: 4203 case Mips::LiRxImmAlignX16: 4204 case Mips::LiRxImmX16: 4205 case Mips::LwRxPcTcpX16: 4206 case Mips::SltiRxImmX16: 4207 case Mips::SltiuRxImmX16: { 4208 // op: imm16 4209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4210 Value |= (op & UINT64_C(2016)) << 16; 4211 Value |= (op & UINT64_C(63488)) << 5; 4212 Value |= (op & UINT64_C(31)); 4213 // op: rx 4214 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4215 op &= UINT64_C(7); 4216 op <<= 8; 4217 Value |= op; 4218 break; 4219 } 4220 case Mips::LbRxRyOffMemX16: 4221 case Mips::LbuRxRyOffMemX16: 4222 case Mips::LhRxRyOffMemX16: 4223 case Mips::LhuRxRyOffMemX16: 4224 case Mips::LwRxRyOffMemX16: 4225 case Mips::LwRxSpImmX16: 4226 case Mips::SbRxRyOffMemX16: 4227 case Mips::ShRxRyOffMemX16: 4228 case Mips::SwRxRyOffMemX16: 4229 case Mips::SwRxSpImmX16: { 4230 // op: imm16 4231 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4232 Value |= (op & UINT64_C(2016)) << 16; 4233 Value |= (op & UINT64_C(63488)) << 5; 4234 Value |= (op & UINT64_C(31)); 4235 // op: rx 4236 op = getMemEncoding(MI, 1, Fixups, STI); 4237 op &= UINT64_C(7); 4238 op <<= 8; 4239 Value |= op; 4240 // op: ry 4241 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4242 op &= UINT64_C(7); 4243 op <<= 5; 4244 Value |= op; 4245 break; 4246 } 4247 case Mips::Jal16: 4248 case Mips::JalB16: { 4249 // op: imm26 4250 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4251 Value |= (op & UINT64_C(2031616)) << 5; 4252 Value |= (op & UINT64_C(65011712)) >> 5; 4253 Value |= (op & UINT64_C(65535)); 4254 break; 4255 } 4256 case Mips::AddiuSpImm16: 4257 case Mips::Bteqz16: 4258 case Mips::Btnez16: { 4259 // op: imm8 4260 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4261 op &= UINT64_C(255); 4262 Value |= op; 4263 break; 4264 } 4265 case Mips::PREFX_MM: { 4266 // op: index 4267 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4268 op &= UINT64_C(31); 4269 op <<= 21; 4270 Value |= op; 4271 // op: base 4272 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4273 op &= UINT64_C(31); 4274 op <<= 16; 4275 Value |= op; 4276 // op: hint 4277 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4278 op &= UINT64_C(31); 4279 op <<= 11; 4280 Value |= op; 4281 break; 4282 } 4283 case Mips::LBUX_MM: 4284 case Mips::LHX_MM: 4285 case Mips::LWX_MM: { 4286 // op: index 4287 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4288 op &= UINT64_C(31); 4289 op <<= 21; 4290 Value |= op; 4291 // op: base 4292 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4293 op &= UINT64_C(31); 4294 op <<= 16; 4295 Value |= op; 4296 // op: rd 4297 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4298 op &= UINT64_C(31); 4299 op <<= 11; 4300 Value |= op; 4301 break; 4302 } 4303 case Mips::COPY_S_D: { 4304 // op: n 4305 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4306 op &= UINT64_C(1); 4307 op <<= 16; 4308 Value |= op; 4309 // op: ws 4310 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4311 op &= UINT64_C(31); 4312 op <<= 11; 4313 Value |= op; 4314 // op: rd 4315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4316 op &= UINT64_C(31); 4317 op <<= 6; 4318 Value |= op; 4319 break; 4320 } 4321 case Mips::SPLATI_D: { 4322 // op: n 4323 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4324 op &= UINT64_C(1); 4325 op <<= 16; 4326 Value |= op; 4327 // op: ws 4328 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4329 op &= UINT64_C(31); 4330 op <<= 11; 4331 Value |= op; 4332 // op: wd 4333 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4334 op &= UINT64_C(31); 4335 op <<= 6; 4336 Value |= op; 4337 break; 4338 } 4339 case Mips::INSVE_D: { 4340 // op: n 4341 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4342 op &= UINT64_C(1); 4343 op <<= 16; 4344 Value |= op; 4345 // op: ws 4346 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4347 op &= UINT64_C(31); 4348 op <<= 11; 4349 Value |= op; 4350 // op: wd 4351 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4352 op &= UINT64_C(31); 4353 op <<= 6; 4354 Value |= op; 4355 break; 4356 } 4357 case Mips::COPY_S_B: 4358 case Mips::COPY_U_B: { 4359 // op: n 4360 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4361 op &= UINT64_C(15); 4362 op <<= 16; 4363 Value |= op; 4364 // op: ws 4365 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4366 op &= UINT64_C(31); 4367 op <<= 11; 4368 Value |= op; 4369 // op: rd 4370 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4371 op &= UINT64_C(31); 4372 op <<= 6; 4373 Value |= op; 4374 break; 4375 } 4376 case Mips::SPLATI_B: { 4377 // op: n 4378 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4379 op &= UINT64_C(15); 4380 op <<= 16; 4381 Value |= op; 4382 // op: ws 4383 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4384 op &= UINT64_C(31); 4385 op <<= 11; 4386 Value |= op; 4387 // op: wd 4388 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4389 op &= UINT64_C(31); 4390 op <<= 6; 4391 Value |= op; 4392 break; 4393 } 4394 case Mips::INSVE_B: { 4395 // op: n 4396 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4397 op &= UINT64_C(15); 4398 op <<= 16; 4399 Value |= op; 4400 // op: ws 4401 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4402 op &= UINT64_C(31); 4403 op <<= 11; 4404 Value |= op; 4405 // op: wd 4406 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4407 op &= UINT64_C(31); 4408 op <<= 6; 4409 Value |= op; 4410 break; 4411 } 4412 case Mips::COPY_S_W: 4413 case Mips::COPY_U_W: { 4414 // op: n 4415 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4416 op &= UINT64_C(3); 4417 op <<= 16; 4418 Value |= op; 4419 // op: ws 4420 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4421 op &= UINT64_C(31); 4422 op <<= 11; 4423 Value |= op; 4424 // op: rd 4425 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4426 op &= UINT64_C(31); 4427 op <<= 6; 4428 Value |= op; 4429 break; 4430 } 4431 case Mips::SPLATI_W: { 4432 // op: n 4433 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4434 op &= UINT64_C(3); 4435 op <<= 16; 4436 Value |= op; 4437 // op: ws 4438 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4439 op &= UINT64_C(31); 4440 op <<= 11; 4441 Value |= op; 4442 // op: wd 4443 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4444 op &= UINT64_C(31); 4445 op <<= 6; 4446 Value |= op; 4447 break; 4448 } 4449 case Mips::INSVE_W: { 4450 // op: n 4451 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4452 op &= UINT64_C(3); 4453 op <<= 16; 4454 Value |= op; 4455 // op: ws 4456 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4457 op &= UINT64_C(31); 4458 op <<= 11; 4459 Value |= op; 4460 // op: wd 4461 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4462 op &= UINT64_C(31); 4463 op <<= 6; 4464 Value |= op; 4465 break; 4466 } 4467 case Mips::COPY_S_H: 4468 case Mips::COPY_U_H: { 4469 // op: n 4470 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4471 op &= UINT64_C(7); 4472 op <<= 16; 4473 Value |= op; 4474 // op: ws 4475 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4476 op &= UINT64_C(31); 4477 op <<= 11; 4478 Value |= op; 4479 // op: rd 4480 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4481 op &= UINT64_C(31); 4482 op <<= 6; 4483 Value |= op; 4484 break; 4485 } 4486 case Mips::SPLATI_H: { 4487 // op: n 4488 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4489 op &= UINT64_C(7); 4490 op <<= 16; 4491 Value |= op; 4492 // op: ws 4493 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4494 op &= UINT64_C(31); 4495 op <<= 11; 4496 Value |= op; 4497 // op: wd 4498 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4499 op &= UINT64_C(31); 4500 op <<= 6; 4501 Value |= op; 4502 break; 4503 } 4504 case Mips::INSVE_H: { 4505 // op: n 4506 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4507 op &= UINT64_C(7); 4508 op <<= 16; 4509 Value |= op; 4510 // op: ws 4511 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4512 op &= UINT64_C(31); 4513 op <<= 11; 4514 Value |= op; 4515 // op: wd 4516 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4517 op &= UINT64_C(31); 4518 op <<= 6; 4519 Value |= op; 4520 break; 4521 } 4522 case Mips::INSERT_D: { 4523 // op: n 4524 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4525 op &= UINT64_C(1); 4526 op <<= 16; 4527 Value |= op; 4528 // op: rs 4529 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4530 op &= UINT64_C(31); 4531 op <<= 11; 4532 Value |= op; 4533 // op: wd 4534 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4535 op &= UINT64_C(31); 4536 op <<= 6; 4537 Value |= op; 4538 break; 4539 } 4540 case Mips::SLDI_D: { 4541 // op: n 4542 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4543 op &= UINT64_C(1); 4544 op <<= 16; 4545 Value |= op; 4546 // op: ws 4547 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4548 op &= UINT64_C(31); 4549 op <<= 11; 4550 Value |= op; 4551 // op: wd 4552 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4553 op &= UINT64_C(31); 4554 op <<= 6; 4555 Value |= op; 4556 break; 4557 } 4558 case Mips::INSERT_B: { 4559 // op: n 4560 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4561 op &= UINT64_C(15); 4562 op <<= 16; 4563 Value |= op; 4564 // op: rs 4565 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4566 op &= UINT64_C(31); 4567 op <<= 11; 4568 Value |= op; 4569 // op: wd 4570 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4571 op &= UINT64_C(31); 4572 op <<= 6; 4573 Value |= op; 4574 break; 4575 } 4576 case Mips::SLDI_B: { 4577 // op: n 4578 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4579 op &= UINT64_C(15); 4580 op <<= 16; 4581 Value |= op; 4582 // op: ws 4583 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4584 op &= UINT64_C(31); 4585 op <<= 11; 4586 Value |= op; 4587 // op: wd 4588 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4589 op &= UINT64_C(31); 4590 op <<= 6; 4591 Value |= op; 4592 break; 4593 } 4594 case Mips::INSERT_W: { 4595 // op: n 4596 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4597 op &= UINT64_C(3); 4598 op <<= 16; 4599 Value |= op; 4600 // op: rs 4601 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4602 op &= UINT64_C(31); 4603 op <<= 11; 4604 Value |= op; 4605 // op: wd 4606 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4607 op &= UINT64_C(31); 4608 op <<= 6; 4609 Value |= op; 4610 break; 4611 } 4612 case Mips::SLDI_W: { 4613 // op: n 4614 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4615 op &= UINT64_C(3); 4616 op <<= 16; 4617 Value |= op; 4618 // op: ws 4619 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4620 op &= UINT64_C(31); 4621 op <<= 11; 4622 Value |= op; 4623 // op: wd 4624 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4625 op &= UINT64_C(31); 4626 op <<= 6; 4627 Value |= op; 4628 break; 4629 } 4630 case Mips::INSERT_H: { 4631 // op: n 4632 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4633 op &= UINT64_C(7); 4634 op <<= 16; 4635 Value |= op; 4636 // op: rs 4637 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4638 op &= UINT64_C(31); 4639 op <<= 11; 4640 Value |= op; 4641 // op: wd 4642 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4643 op &= UINT64_C(31); 4644 op <<= 6; 4645 Value |= op; 4646 break; 4647 } 4648 case Mips::SLDI_H: { 4649 // op: n 4650 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4651 op &= UINT64_C(7); 4652 op <<= 16; 4653 Value |= op; 4654 // op: ws 4655 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4656 op &= UINT64_C(31); 4657 op <<= 11; 4658 Value |= op; 4659 // op: wd 4660 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4661 op &= UINT64_C(31); 4662 op <<= 6; 4663 Value |= op; 4664 break; 4665 } 4666 case Mips::BALC: 4667 case Mips::BC: { 4668 // op: offset 4669 op = getBranchTarget26OpValue(MI, 0, Fixups, STI); 4670 op &= UINT64_C(67108863); 4671 Value |= op; 4672 break; 4673 } 4674 case Mips::BALC_MMR6: 4675 case Mips::BC_MMR6: { 4676 // op: offset 4677 op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI); 4678 op &= UINT64_C(67108863); 4679 Value |= op; 4680 break; 4681 } 4682 case Mips::BAL: 4683 case Mips::BPOSGE32: { 4684 // op: offset 4685 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 4686 op &= UINT64_C(65535); 4687 Value |= op; 4688 break; 4689 } 4690 case Mips::BNZ_B: 4691 case Mips::BNZ_D: 4692 case Mips::BNZ_H: 4693 case Mips::BNZ_V: 4694 case Mips::BNZ_W: 4695 case Mips::BZ_B: 4696 case Mips::BZ_D: 4697 case Mips::BZ_H: 4698 case Mips::BZ_V: 4699 case Mips::BZ_W: { 4700 // op: offset 4701 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 4702 op &= UINT64_C(65535); 4703 Value |= op; 4704 // op: wt 4705 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4706 op &= UINT64_C(31); 4707 op <<= 16; 4708 Value |= op; 4709 break; 4710 } 4711 case Mips::BPOSGE32C_MMR3: { 4712 // op: offset 4713 op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI); 4714 op &= UINT64_C(65535); 4715 Value |= op; 4716 break; 4717 } 4718 case Mips::BPOSGE32_MM: { 4719 // op: offset 4720 op = getBranchTargetOpValueMM(MI, 0, Fixups, STI); 4721 op &= UINT64_C(65535); 4722 Value |= op; 4723 break; 4724 } 4725 case Mips::B16_MM: 4726 case Mips::BC16_MMR6: { 4727 // op: offset 4728 op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI); 4729 op &= UINT64_C(1023); 4730 Value |= op; 4731 break; 4732 } 4733 case Mips::Move32R16: { 4734 // op: r32 4735 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4736 Value |= (op & UINT64_C(7)) << 5; 4737 Value |= (op & UINT64_C(24)); 4738 // op: rz 4739 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4740 op &= UINT64_C(7); 4741 Value |= op; 4742 break; 4743 } 4744 case Mips::CLO: 4745 case Mips::CLZ: 4746 case Mips::DCLO: 4747 case Mips::DCLZ: { 4748 // op: rd 4749 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4750 Value |= (op & UINT64_C(31)) << 16; 4751 Value |= (op & UINT64_C(31)) << 11; 4752 // op: rs 4753 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4754 op &= UINT64_C(31); 4755 op <<= 21; 4756 Value |= op; 4757 break; 4758 } 4759 case Mips::MFHI16_MM: 4760 case Mips::MFLO16_MM: { 4761 // op: rd 4762 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4763 op &= UINT64_C(31); 4764 Value |= op; 4765 break; 4766 } 4767 case Mips::MFHI: 4768 case Mips::MFHI64: 4769 case Mips::MFLO: 4770 case Mips::MFLO64: { 4771 // op: rd 4772 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4773 op &= UINT64_C(31); 4774 op <<= 11; 4775 Value |= op; 4776 break; 4777 } 4778 case Mips::MFHI_DSP: 4779 case Mips::MFLO_DSP: { 4780 // op: rd 4781 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4782 op &= UINT64_C(31); 4783 op <<= 11; 4784 Value |= op; 4785 // op: ac 4786 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4787 op &= UINT64_C(3); 4788 op <<= 21; 4789 Value |= op; 4790 break; 4791 } 4792 case Mips::LWXS_MM: { 4793 // op: rd 4794 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4795 op &= UINT64_C(31); 4796 op <<= 11; 4797 Value |= op; 4798 // op: base 4799 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4800 op &= UINT64_C(31); 4801 op <<= 16; 4802 Value |= op; 4803 // op: index 4804 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4805 op &= UINT64_C(31); 4806 op <<= 21; 4807 Value |= op; 4808 break; 4809 } 4810 case Mips::LBUX: 4811 case Mips::LHX: 4812 case Mips::LWX: { 4813 // op: rd 4814 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4815 op &= UINT64_C(31); 4816 op <<= 11; 4817 Value |= op; 4818 // op: base 4819 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4820 op &= UINT64_C(31); 4821 op <<= 21; 4822 Value |= op; 4823 // op: index 4824 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4825 op &= UINT64_C(31); 4826 op <<= 16; 4827 Value |= op; 4828 break; 4829 } 4830 case Mips::REPL_PH: 4831 case Mips::REPL_PH_MM: 4832 case Mips::REPL_QB: { 4833 // op: rd 4834 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4835 op &= UINT64_C(31); 4836 op <<= 11; 4837 Value |= op; 4838 // op: imm 4839 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4840 op &= UINT64_C(1023); 4841 op <<= 16; 4842 Value |= op; 4843 break; 4844 } 4845 case Mips::RDDSP: { 4846 // op: rd 4847 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4848 op &= UINT64_C(31); 4849 op <<= 11; 4850 Value |= op; 4851 // op: mask 4852 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4853 op &= UINT64_C(1023); 4854 op <<= 16; 4855 Value |= op; 4856 break; 4857 } 4858 case Mips::ADDQH_PH_MMR2: 4859 case Mips::ADDQH_R_PH_MMR2: 4860 case Mips::ADDQH_R_W_MMR2: 4861 case Mips::ADDQH_W_MMR2: 4862 case Mips::ADDQ_PH_MM: 4863 case Mips::ADDQ_S_PH_MM: 4864 case Mips::ADDQ_S_W_MM: 4865 case Mips::ADDSC_MM: 4866 case Mips::ADDUH_QB_MMR2: 4867 case Mips::ADDUH_R_QB_MMR2: 4868 case Mips::ADDU_PH_MMR2: 4869 case Mips::ADDU_QB_MM: 4870 case Mips::ADDU_S_PH_MMR2: 4871 case Mips::ADDU_S_QB_MM: 4872 case Mips::ADDWC_MM: 4873 case Mips::CMPGDU_EQ_QB_MMR2: 4874 case Mips::CMPGDU_LE_QB_MMR2: 4875 case Mips::CMPGDU_LT_QB_MMR2: 4876 case Mips::MODSUB_MM: 4877 case Mips::MULEQ_S_W_PHL_MM: 4878 case Mips::MULEQ_S_W_PHR_MM: 4879 case Mips::MULEU_S_PH_QBL_MM: 4880 case Mips::MULEU_S_PH_QBR_MM: 4881 case Mips::MULQ_RS_PH_MM: 4882 case Mips::MULQ_RS_W_MMR2: 4883 case Mips::MULQ_S_PH_MMR2: 4884 case Mips::MULQ_S_W_MMR2: 4885 case Mips::MUL_PH_MMR2: 4886 case Mips::MUL_S_PH_MMR2: 4887 case Mips::PACKRL_PH_MM: 4888 case Mips::PICK_PH_MM: 4889 case Mips::PICK_QB_MM: 4890 case Mips::PRECRQU_S_QB_PH_MM: 4891 case Mips::PRECRQ_PH_W_MM: 4892 case Mips::PRECRQ_QB_PH_MM: 4893 case Mips::PRECRQ_RS_PH_W_MM: 4894 case Mips::PRECR_QB_PH_MMR2: 4895 case Mips::SELEQZ_MMR6: 4896 case Mips::SELNEZ_MMR6: 4897 case Mips::SUBQH_PH_MMR2: 4898 case Mips::SUBQH_R_PH_MMR2: 4899 case Mips::SUBQH_R_W_MMR2: 4900 case Mips::SUBQH_W_MMR2: 4901 case Mips::SUBQ_PH_MM: 4902 case Mips::SUBQ_S_PH_MM: 4903 case Mips::SUBQ_S_W_MM: 4904 case Mips::SUBUH_QB_MMR2: 4905 case Mips::SUBUH_R_QB_MMR2: 4906 case Mips::SUBU_PH_MMR2: 4907 case Mips::SUBU_QB_MM: 4908 case Mips::SUBU_S_PH_MMR2: 4909 case Mips::SUBU_S_QB_MM: { 4910 // op: rd 4911 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4912 op &= UINT64_C(31); 4913 op <<= 11; 4914 Value |= op; 4915 // op: rs 4916 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4917 op &= UINT64_C(31); 4918 op <<= 16; 4919 Value |= op; 4920 // op: rt 4921 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4922 op &= UINT64_C(31); 4923 op <<= 21; 4924 Value |= op; 4925 break; 4926 } 4927 case Mips::LSA_MMR6: { 4928 // op: rd 4929 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4930 op &= UINT64_C(31); 4931 op <<= 11; 4932 Value |= op; 4933 // op: rs 4934 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4935 op &= UINT64_C(31); 4936 op <<= 16; 4937 Value |= op; 4938 // op: rt 4939 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4940 op &= UINT64_C(31); 4941 op <<= 21; 4942 Value |= op; 4943 // op: imm2 4944 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 4945 op &= UINT64_C(3); 4946 op <<= 9; 4947 Value |= op; 4948 break; 4949 } 4950 case Mips::CLO_R6: 4951 case Mips::CLZ_R6: 4952 case Mips::DCLO_R6: 4953 case Mips::DCLZ_R6: 4954 case Mips::DPOP: 4955 case Mips::JALR: 4956 case Mips::JALR64: 4957 case Mips::JALR_HB: 4958 case Mips::JALR_HB64: 4959 case Mips::POP: 4960 case Mips::RADDU_W_QB: { 4961 // op: rd 4962 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4963 op &= UINT64_C(31); 4964 op <<= 11; 4965 Value |= op; 4966 // op: rs 4967 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4968 op &= UINT64_C(31); 4969 op <<= 21; 4970 Value |= op; 4971 break; 4972 } 4973 case Mips::MOVF_I: 4974 case Mips::MOVF_I64: 4975 case Mips::MOVT_I: 4976 case Mips::MOVT_I64: { 4977 // op: rd 4978 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4979 op &= UINT64_C(31); 4980 op <<= 11; 4981 Value |= op; 4982 // op: rs 4983 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4984 op &= UINT64_C(31); 4985 op <<= 21; 4986 Value |= op; 4987 // op: fcc 4988 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4989 op &= UINT64_C(7); 4990 op <<= 18; 4991 Value |= op; 4992 break; 4993 } 4994 case Mips::ADD: 4995 case Mips::ADDQH_PH: 4996 case Mips::ADDQH_R_PH: 4997 case Mips::ADDQH_R_W: 4998 case Mips::ADDQH_W: 4999 case Mips::ADDQ_PH: 5000 case Mips::ADDQ_S_PH: 5001 case Mips::ADDQ_S_W: 5002 case Mips::ADDSC: 5003 case Mips::ADDUH_QB: 5004 case Mips::ADDUH_R_QB: 5005 case Mips::ADDU_PH: 5006 case Mips::ADDU_QB: 5007 case Mips::ADDU_S_PH: 5008 case Mips::ADDU_S_QB: 5009 case Mips::ADDWC: 5010 case Mips::ADDu: 5011 case Mips::AND: 5012 case Mips::AND64: 5013 case Mips::BADDu: 5014 case Mips::DADD: 5015 case Mips::DADDu: 5016 case Mips::DDIV: 5017 case Mips::DDIVU: 5018 case Mips::DIV: 5019 case Mips::DIVU: 5020 case Mips::DMOD: 5021 case Mips::DMODU: 5022 case Mips::DMUH: 5023 case Mips::DMUHU: 5024 case Mips::DMUL: 5025 case Mips::DMULU: 5026 case Mips::DMUL_R6: 5027 case Mips::DSUB: 5028 case Mips::DSUBu: 5029 case Mips::MOD: 5030 case Mips::MODSUB: 5031 case Mips::MODU: 5032 case Mips::MOVN_I64_I: 5033 case Mips::MOVN_I64_I64: 5034 case Mips::MOVN_I_I: 5035 case Mips::MOVN_I_I64: 5036 case Mips::MOVZ_I64_I: 5037 case Mips::MOVZ_I64_I64: 5038 case Mips::MOVZ_I_I: 5039 case Mips::MOVZ_I_I64: 5040 case Mips::MUH: 5041 case Mips::MUHU: 5042 case Mips::MUL: 5043 case Mips::MULEQ_S_W_PHL: 5044 case Mips::MULEQ_S_W_PHR: 5045 case Mips::MULEU_S_PH_QBL: 5046 case Mips::MULEU_S_PH_QBR: 5047 case Mips::MULQ_RS_PH: 5048 case Mips::MULQ_RS_W: 5049 case Mips::MULQ_S_PH: 5050 case Mips::MULQ_S_W: 5051 case Mips::MULU: 5052 case Mips::MUL_PH: 5053 case Mips::MUL_R6: 5054 case Mips::MUL_S_PH: 5055 case Mips::NOR: 5056 case Mips::NOR64: 5057 case Mips::OR: 5058 case Mips::OR64: 5059 case Mips::SELEQZ: 5060 case Mips::SELEQZ64: 5061 case Mips::SELNEZ: 5062 case Mips::SELNEZ64: 5063 case Mips::SEQ: 5064 case Mips::SLT: 5065 case Mips::SLT64: 5066 case Mips::SLTu: 5067 case Mips::SLTu64: 5068 case Mips::SNE: 5069 case Mips::SUB: 5070 case Mips::SUBQH_PH: 5071 case Mips::SUBQH_R_PH: 5072 case Mips::SUBQH_R_W: 5073 case Mips::SUBQH_W: 5074 case Mips::SUBQ_PH: 5075 case Mips::SUBQ_S_PH: 5076 case Mips::SUBQ_S_W: 5077 case Mips::SUBUH_QB: 5078 case Mips::SUBUH_R_QB: 5079 case Mips::SUBU_PH: 5080 case Mips::SUBU_QB: 5081 case Mips::SUBU_S_PH: 5082 case Mips::SUBU_S_QB: 5083 case Mips::SUBu: 5084 case Mips::V3MULU: 5085 case Mips::VMM0: 5086 case Mips::VMULU: 5087 case Mips::XOR: 5088 case Mips::XOR64: { 5089 // op: rd 5090 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5091 op &= UINT64_C(31); 5092 op <<= 11; 5093 Value |= op; 5094 // op: rs 5095 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5096 op &= UINT64_C(31); 5097 op <<= 21; 5098 Value |= op; 5099 // op: rt 5100 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5101 op &= UINT64_C(31); 5102 op <<= 16; 5103 Value |= op; 5104 break; 5105 } 5106 case Mips::ALIGN: { 5107 // op: rd 5108 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5109 op &= UINT64_C(31); 5110 op <<= 11; 5111 Value |= op; 5112 // op: rs 5113 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5114 op &= UINT64_C(31); 5115 op <<= 21; 5116 Value |= op; 5117 // op: rt 5118 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5119 op &= UINT64_C(31); 5120 op <<= 16; 5121 Value |= op; 5122 // op: bp 5123 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5124 op &= UINT64_C(3); 5125 op <<= 6; 5126 Value |= op; 5127 break; 5128 } 5129 case Mips::ALIGN_MMR6: { 5130 // op: rd 5131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5132 op &= UINT64_C(31); 5133 op <<= 11; 5134 Value |= op; 5135 // op: rs 5136 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5137 op &= UINT64_C(31); 5138 op <<= 21; 5139 Value |= op; 5140 // op: rt 5141 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5142 op &= UINT64_C(31); 5143 op <<= 16; 5144 Value |= op; 5145 // op: bp 5146 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5147 op &= UINT64_C(3); 5148 op <<= 9; 5149 Value |= op; 5150 break; 5151 } 5152 case Mips::DALIGN: { 5153 // op: rd 5154 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5155 op &= UINT64_C(31); 5156 op <<= 11; 5157 Value |= op; 5158 // op: rs 5159 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5160 op &= UINT64_C(31); 5161 op <<= 21; 5162 Value |= op; 5163 // op: rt 5164 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5165 op &= UINT64_C(31); 5166 op <<= 16; 5167 Value |= op; 5168 // op: bp 5169 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 5170 op &= UINT64_C(7); 5171 op <<= 6; 5172 Value |= op; 5173 break; 5174 } 5175 case Mips::DLSA_R6: 5176 case Mips::LSA_R6: { 5177 // op: rd 5178 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5179 op &= UINT64_C(31); 5180 op <<= 11; 5181 Value |= op; 5182 // op: rs 5183 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5184 op &= UINT64_C(31); 5185 op <<= 21; 5186 Value |= op; 5187 // op: rt 5188 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5189 op &= UINT64_C(31); 5190 op <<= 16; 5191 Value |= op; 5192 // op: imm2 5193 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 5194 op &= UINT64_C(3); 5195 op <<= 6; 5196 Value |= op; 5197 break; 5198 } 5199 case Mips::SHLLV_PH_MM: 5200 case Mips::SHLLV_QB_MM: 5201 case Mips::SHLLV_S_PH_MM: 5202 case Mips::SHLLV_S_W_MM: 5203 case Mips::SHRAV_PH_MM: 5204 case Mips::SHRAV_QB_MMR2: 5205 case Mips::SHRAV_R_PH_MM: 5206 case Mips::SHRAV_R_QB_MMR2: 5207 case Mips::SHRAV_R_W_MM: 5208 case Mips::SHRLV_PH_MMR2: 5209 case Mips::SHRLV_QB_MM: { 5210 // op: rd 5211 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5212 op &= UINT64_C(31); 5213 op <<= 11; 5214 Value |= op; 5215 // op: rs 5216 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5217 op &= UINT64_C(31); 5218 op <<= 16; 5219 Value |= op; 5220 // op: rt 5221 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5222 op &= UINT64_C(31); 5223 op <<= 21; 5224 Value |= op; 5225 break; 5226 } 5227 case Mips::ABSQ_S_PH: 5228 case Mips::ABSQ_S_QB: 5229 case Mips::ABSQ_S_W: 5230 case Mips::BITREV: 5231 case Mips::BITSWAP: 5232 case Mips::DBITSWAP: 5233 case Mips::DSBH: 5234 case Mips::DSHD: 5235 case Mips::DSLL64_32: 5236 case Mips::PRECEQU_PH_QBL: 5237 case Mips::PRECEQU_PH_QBLA: 5238 case Mips::PRECEQU_PH_QBR: 5239 case Mips::PRECEQU_PH_QBRA: 5240 case Mips::PRECEQ_W_PHL: 5241 case Mips::PRECEQ_W_PHR: 5242 case Mips::PRECEU_PH_QBL: 5243 case Mips::PRECEU_PH_QBLA: 5244 case Mips::PRECEU_PH_QBR: 5245 case Mips::PRECEU_PH_QBRA: 5246 case Mips::REPLV_PH: 5247 case Mips::REPLV_QB: 5248 case Mips::SEB: 5249 case Mips::SEB64: 5250 case Mips::SEH: 5251 case Mips::SEH64: 5252 case Mips::SLL64_32: 5253 case Mips::SLL64_64: 5254 case Mips::WSBH: { 5255 // op: rd 5256 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5257 op &= UINT64_C(31); 5258 op <<= 11; 5259 Value |= op; 5260 // op: rt 5261 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5262 op &= UINT64_C(31); 5263 op <<= 16; 5264 Value |= op; 5265 break; 5266 } 5267 case Mips::DROTRV: 5268 case Mips::DSLLV: 5269 case Mips::DSRAV: 5270 case Mips::DSRLV: 5271 case Mips::ROTRV: 5272 case Mips::SLLV: 5273 case Mips::SRAV: 5274 case Mips::SRLV: { 5275 // op: rd 5276 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5277 op &= UINT64_C(31); 5278 op <<= 11; 5279 Value |= op; 5280 // op: rt 5281 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5282 op &= UINT64_C(31); 5283 op <<= 16; 5284 Value |= op; 5285 // op: rs 5286 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5287 op &= UINT64_C(31); 5288 op <<= 21; 5289 Value |= op; 5290 break; 5291 } 5292 case Mips::SHLLV_PH: 5293 case Mips::SHLLV_QB: 5294 case Mips::SHLLV_S_PH: 5295 case Mips::SHLLV_S_W: 5296 case Mips::SHLL_PH: 5297 case Mips::SHLL_QB: 5298 case Mips::SHLL_S_PH: 5299 case Mips::SHLL_S_W: 5300 case Mips::SHRAV_PH: 5301 case Mips::SHRAV_QB: 5302 case Mips::SHRAV_R_PH: 5303 case Mips::SHRAV_R_QB: 5304 case Mips::SHRAV_R_W: 5305 case Mips::SHRA_PH: 5306 case Mips::SHRA_QB: 5307 case Mips::SHRA_R_PH: 5308 case Mips::SHRA_R_QB: 5309 case Mips::SHRA_R_W: 5310 case Mips::SHRLV_PH: 5311 case Mips::SHRLV_QB: 5312 case Mips::SHRL_PH: 5313 case Mips::SHRL_QB: { 5314 // op: rd 5315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5316 op &= UINT64_C(31); 5317 op <<= 11; 5318 Value |= op; 5319 // op: rt 5320 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5321 op &= UINT64_C(31); 5322 op <<= 16; 5323 Value |= op; 5324 // op: rs_sa 5325 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5326 op &= UINT64_C(31); 5327 op <<= 21; 5328 Value |= op; 5329 break; 5330 } 5331 case Mips::DROTR: 5332 case Mips::DROTR32: 5333 case Mips::DSLL: 5334 case Mips::DSLL32: 5335 case Mips::DSRA: 5336 case Mips::DSRA32: 5337 case Mips::DSRL: 5338 case Mips::DSRL32: 5339 case Mips::ROTR: 5340 case Mips::SLL: 5341 case Mips::SRA: 5342 case Mips::SRL: { 5343 // op: rd 5344 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5345 op &= UINT64_C(31); 5346 op <<= 11; 5347 Value |= op; 5348 // op: rt 5349 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5350 op &= UINT64_C(31); 5351 op <<= 16; 5352 Value |= op; 5353 // op: shamt 5354 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5355 op &= UINT64_C(31); 5356 op <<= 6; 5357 Value |= op; 5358 break; 5359 } 5360 case Mips::ROTRV_MM: 5361 case Mips::SLLV_MM: 5362 case Mips::SRAV_MM: 5363 case Mips::SRLV_MM: { 5364 // op: rd 5365 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5366 op &= UINT64_C(31); 5367 op <<= 11; 5368 Value |= op; 5369 // op: rt 5370 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5371 op &= UINT64_C(31); 5372 op <<= 21; 5373 Value |= op; 5374 // op: rs 5375 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5376 op &= UINT64_C(31); 5377 op <<= 16; 5378 Value |= op; 5379 break; 5380 } 5381 case Mips::ADDU_MMR6: 5382 case Mips::ADD_MMR6: 5383 case Mips::AND_MMR6: 5384 case Mips::DIVU_MMR6: 5385 case Mips::DIV_MMR6: 5386 case Mips::MODU_MMR6: 5387 case Mips::MOD_MMR6: 5388 case Mips::MUHU_MMR6: 5389 case Mips::MUH_MMR6: 5390 case Mips::MULU_MMR6: 5391 case Mips::MUL_MMR6: 5392 case Mips::NOR_MMR6: 5393 case Mips::OR_MMR6: 5394 case Mips::SUBU_MMR6: 5395 case Mips::SUB_MMR6: 5396 case Mips::XOR_MMR6: { 5397 // op: rd 5398 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5399 op &= UINT64_C(31); 5400 op <<= 11; 5401 Value |= op; 5402 // op: rt 5403 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5404 op &= UINT64_C(31); 5405 op <<= 21; 5406 Value |= op; 5407 // op: rs 5408 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5409 op &= UINT64_C(31); 5410 op <<= 16; 5411 Value |= op; 5412 break; 5413 } 5414 case Mips::MFHI_MM: 5415 case Mips::MFLO_MM: { 5416 // op: rd 5417 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5418 op &= UINT64_C(31); 5419 op <<= 16; 5420 Value |= op; 5421 break; 5422 } 5423 case Mips::BITSWAP_MMR6: { 5424 // op: rd 5425 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5426 op &= UINT64_C(31); 5427 op <<= 16; 5428 Value |= op; 5429 // op: rt 5430 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5431 op &= UINT64_C(31); 5432 op <<= 21; 5433 Value |= op; 5434 break; 5435 } 5436 case Mips::CLO_MM: 5437 case Mips::CLZ_MM: { 5438 // op: rd 5439 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5440 op &= UINT64_C(31); 5441 op <<= 21; 5442 Value |= op; 5443 // op: rs 5444 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5445 op &= UINT64_C(31); 5446 op <<= 16; 5447 Value |= op; 5448 break; 5449 } 5450 case Mips::MOVF_I_MM: 5451 case Mips::MOVT_I_MM: { 5452 // op: rd 5453 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5454 op &= UINT64_C(31); 5455 op <<= 21; 5456 Value |= op; 5457 // op: rs 5458 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5459 op &= UINT64_C(31); 5460 op <<= 16; 5461 Value |= op; 5462 // op: fcc 5463 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5464 op &= UINT64_C(7); 5465 op <<= 13; 5466 Value |= op; 5467 break; 5468 } 5469 case Mips::SEB_MM: 5470 case Mips::SEH_MM: 5471 case Mips::WSBH_MM: { 5472 // op: rd 5473 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5474 op &= UINT64_C(31); 5475 op <<= 21; 5476 Value |= op; 5477 // op: rt 5478 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5479 op &= UINT64_C(31); 5480 op <<= 16; 5481 Value |= op; 5482 break; 5483 } 5484 case Mips::ROTR_MM: 5485 case Mips::SLL_MM: 5486 case Mips::SLL_MMR6: 5487 case Mips::SRA_MM: 5488 case Mips::SRL_MM: { 5489 // op: rd 5490 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5491 op &= UINT64_C(31); 5492 op <<= 21; 5493 Value |= op; 5494 // op: rt 5495 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5496 op &= UINT64_C(31); 5497 op <<= 16; 5498 Value |= op; 5499 // op: shamt 5500 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5501 op &= UINT64_C(31); 5502 op <<= 11; 5503 Value |= op; 5504 break; 5505 } 5506 case Mips::CFCMSA: { 5507 // op: rd 5508 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5509 op &= UINT64_C(31); 5510 op <<= 6; 5511 Value |= op; 5512 // op: cs 5513 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5514 op &= UINT64_C(31); 5515 op <<= 11; 5516 Value |= op; 5517 break; 5518 } 5519 case Mips::LI16_MM: 5520 case Mips::LI16_MMR6: { 5521 // op: rd 5522 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5523 op &= UINT64_C(7); 5524 op <<= 7; 5525 Value |= op; 5526 // op: imm 5527 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5528 op &= UINT64_C(127); 5529 Value |= op; 5530 break; 5531 } 5532 case Mips::ADDIUR1SP_MM: { 5533 // op: rd 5534 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5535 op &= UINT64_C(7); 5536 op <<= 7; 5537 Value |= op; 5538 // op: imm 5539 op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI); 5540 op &= UINT64_C(63); 5541 op <<= 1; 5542 Value |= op; 5543 break; 5544 } 5545 case Mips::ADDIUR2_MM: { 5546 // op: rd 5547 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5548 op &= UINT64_C(7); 5549 op <<= 7; 5550 Value |= op; 5551 // op: rs 5552 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5553 op &= UINT64_C(7); 5554 op <<= 4; 5555 Value |= op; 5556 // op: imm 5557 op = getSImm3Lsa2Value(MI, 2, Fixups, STI); 5558 op &= UINT64_C(7); 5559 op <<= 1; 5560 Value |= op; 5561 break; 5562 } 5563 case Mips::ANDI16_MM: 5564 case Mips::ANDI16_MMR6: { 5565 // op: rd 5566 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5567 op &= UINT64_C(7); 5568 op <<= 7; 5569 Value |= op; 5570 // op: rs 5571 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5572 op &= UINT64_C(7); 5573 op <<= 4; 5574 Value |= op; 5575 // op: imm 5576 op = getUImm4AndValue(MI, 2, Fixups, STI); 5577 op &= UINT64_C(15); 5578 Value |= op; 5579 break; 5580 } 5581 case Mips::SLL16_MM: 5582 case Mips::SLL16_MMR6: 5583 case Mips::SRL16_MM: 5584 case Mips::SRL16_MMR6: { 5585 // op: rd 5586 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5587 op &= UINT64_C(7); 5588 op <<= 7; 5589 Value |= op; 5590 // op: rt 5591 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5592 op &= UINT64_C(7); 5593 op <<= 4; 5594 Value |= op; 5595 // op: shamt 5596 op = getUImm3Mod8Encoding(MI, 2, Fixups, STI); 5597 op &= UINT64_C(7); 5598 op <<= 1; 5599 Value |= op; 5600 break; 5601 } 5602 case Mips::ADDU16_MM: 5603 case Mips::SUBU16_MM: { 5604 // op: rd 5605 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5606 op &= UINT64_C(7); 5607 op <<= 7; 5608 Value |= op; 5609 // op: rt 5610 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5611 op &= UINT64_C(7); 5612 op <<= 4; 5613 Value |= op; 5614 // op: rs 5615 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5616 op &= UINT64_C(7); 5617 op <<= 1; 5618 Value |= op; 5619 break; 5620 } 5621 case Mips::ADDIUS5_MM: { 5622 // op: rd 5623 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5624 op &= UINT64_C(31); 5625 op <<= 5; 5626 Value |= op; 5627 // op: imm 5628 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5629 op &= UINT64_C(15); 5630 op <<= 1; 5631 Value |= op; 5632 break; 5633 } 5634 case Mips::JALR16_MM: 5635 case Mips::JALRS16_MM: 5636 case Mips::JR16_MM: 5637 case Mips::JRC16_MM: { 5638 // op: rs 5639 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5640 op &= UINT64_C(31); 5641 Value |= op; 5642 break; 5643 } 5644 case Mips::DVP_MMR6: 5645 case Mips::EVP_MMR6: 5646 case Mips::JR_MM: 5647 case Mips::MTHI_MM: 5648 case Mips::MTLO_MM: { 5649 // op: rs 5650 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5651 op &= UINT64_C(31); 5652 op <<= 16; 5653 Value |= op; 5654 break; 5655 } 5656 case Mips::MFHI_DSP_MM: 5657 case Mips::MFLO_DSP_MM: { 5658 // op: rs 5659 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5660 op &= UINT64_C(31); 5661 op <<= 16; 5662 Value |= op; 5663 // op: ac 5664 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5665 op &= UINT64_C(3); 5666 op <<= 14; 5667 Value |= op; 5668 break; 5669 } 5670 case Mips::TEQI_MM: 5671 case Mips::TGEIU_MM: 5672 case Mips::TGEI_MM: 5673 case Mips::TLTIU_MM: 5674 case Mips::TLTI_MM: 5675 case Mips::TNEI_MM: { 5676 // op: rs 5677 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5678 op &= UINT64_C(31); 5679 op <<= 16; 5680 Value |= op; 5681 // op: imm16 5682 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5683 op &= UINT64_C(65535); 5684 Value |= op; 5685 break; 5686 } 5687 case Mips::BEQZC_MM: 5688 case Mips::BGEZALS_MM: 5689 case Mips::BGEZAL_MM: 5690 case Mips::BGEZ_MM: 5691 case Mips::BGTZ_MM: 5692 case Mips::BLEZ_MM: 5693 case Mips::BLTZALS_MM: 5694 case Mips::BLTZAL_MM: 5695 case Mips::BLTZ_MM: 5696 case Mips::BNEZC_MM: { 5697 // op: rs 5698 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5699 op &= UINT64_C(31); 5700 op <<= 16; 5701 Value |= op; 5702 // op: offset 5703 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 5704 op &= UINT64_C(65535); 5705 Value |= op; 5706 break; 5707 } 5708 case Mips::MADDU_MM: 5709 case Mips::MADD_MM: 5710 case Mips::MSUBU_MM: 5711 case Mips::MSUB_MM: 5712 case Mips::MULT_MM: 5713 case Mips::MULTu_MM: 5714 case Mips::SDIV_MM: 5715 case Mips::UDIV_MM: { 5716 // op: rs 5717 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5718 op &= UINT64_C(31); 5719 op <<= 16; 5720 Value |= op; 5721 // op: rt 5722 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5723 op &= UINT64_C(31); 5724 op <<= 21; 5725 Value |= op; 5726 break; 5727 } 5728 case Mips::TEQ_MM: 5729 case Mips::TGEU_MM: 5730 case Mips::TGE_MM: 5731 case Mips::TLTU_MM: 5732 case Mips::TLT_MM: 5733 case Mips::TNE_MM: { 5734 // op: rs 5735 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5736 op &= UINT64_C(31); 5737 op <<= 16; 5738 Value |= op; 5739 // op: rt 5740 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5741 op &= UINT64_C(31); 5742 op <<= 21; 5743 Value |= op; 5744 // op: code_ 5745 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5746 op &= UINT64_C(15); 5747 op <<= 12; 5748 Value |= op; 5749 break; 5750 } 5751 case Mips::BEQ_MM: 5752 case Mips::BNE_MM: { 5753 // op: rs 5754 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5755 op &= UINT64_C(31); 5756 op <<= 16; 5757 Value |= op; 5758 // op: rt 5759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5760 op &= UINT64_C(31); 5761 op <<= 21; 5762 Value |= op; 5763 // op: offset 5764 op = getBranchTargetOpValueMM(MI, 2, Fixups, STI); 5765 op &= UINT64_C(65535); 5766 Value |= op; 5767 break; 5768 } 5769 case Mips::GINVI_MMR6: { 5770 // op: rs 5771 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5772 op &= UINT64_C(31); 5773 op <<= 16; 5774 Value |= op; 5775 // op: type 5776 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5777 op &= UINT64_C(3); 5778 op <<= 9; 5779 Value |= op; 5780 break; 5781 } 5782 case Mips::GINVT_MMR6: { 5783 // op: rs 5784 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5785 op &= UINT64_C(31); 5786 op <<= 16; 5787 Value |= op; 5788 // op: type 5789 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5790 op &= UINT64_C(3); 5791 op <<= 9; 5792 Value |= op; 5793 break; 5794 } 5795 case Mips::JR: 5796 case Mips::JR64: 5797 case Mips::JR_HB: 5798 case Mips::JR_HB64: 5799 case Mips::JR_HB64_R6: 5800 case Mips::JR_HB_R6: 5801 case Mips::MTHI: 5802 case Mips::MTHI64: 5803 case Mips::MTLO: 5804 case Mips::MTLO64: 5805 case Mips::MTM0: 5806 case Mips::MTM1: 5807 case Mips::MTM2: 5808 case Mips::MTP0: 5809 case Mips::MTP1: 5810 case Mips::MTP2: { 5811 // op: rs 5812 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5813 op &= UINT64_C(31); 5814 op <<= 21; 5815 Value |= op; 5816 break; 5817 } 5818 case Mips::ALUIPC: 5819 case Mips::AUIPC: { 5820 // op: rs 5821 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5822 op &= UINT64_C(31); 5823 op <<= 21; 5824 Value |= op; 5825 // op: imm 5826 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5827 op &= UINT64_C(65535); 5828 Value |= op; 5829 break; 5830 } 5831 case Mips::DAHI: 5832 case Mips::DATI: { 5833 // op: rs 5834 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5835 op &= UINT64_C(31); 5836 op <<= 21; 5837 Value |= op; 5838 // op: imm 5839 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5840 op &= UINT64_C(65535); 5841 Value |= op; 5842 break; 5843 } 5844 case Mips::LDPC: { 5845 // op: rs 5846 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5847 op &= UINT64_C(31); 5848 op <<= 21; 5849 Value |= op; 5850 // op: imm 5851 op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI); 5852 op &= UINT64_C(262143); 5853 Value |= op; 5854 break; 5855 } 5856 case Mips::ADDIUPC: 5857 case Mips::LWPC: 5858 case Mips::LWUPC: { 5859 // op: rs 5860 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5861 op &= UINT64_C(31); 5862 op <<= 21; 5863 Value |= op; 5864 // op: imm 5865 op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI); 5866 op &= UINT64_C(524287); 5867 Value |= op; 5868 break; 5869 } 5870 case Mips::TEQI: 5871 case Mips::TGEI: 5872 case Mips::TGEIU: 5873 case Mips::TLTI: 5874 case Mips::TNEI: 5875 case Mips::TTLTIU: { 5876 // op: rs 5877 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5878 op &= UINT64_C(31); 5879 op <<= 21; 5880 Value |= op; 5881 // op: imm16 5882 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5883 op &= UINT64_C(65535); 5884 Value |= op; 5885 break; 5886 } 5887 case Mips::WRDSP: { 5888 // op: rs 5889 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5890 op &= UINT64_C(31); 5891 op <<= 21; 5892 Value |= op; 5893 // op: mask 5894 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5895 op &= UINT64_C(1023); 5896 op <<= 11; 5897 Value |= op; 5898 break; 5899 } 5900 case Mips::BEQZC: 5901 case Mips::BEQZC64: 5902 case Mips::BNEZC: 5903 case Mips::BNEZC64: { 5904 // op: rs 5905 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5906 op &= UINT64_C(31); 5907 op <<= 21; 5908 Value |= op; 5909 // op: offset 5910 op = getBranchTarget21OpValue(MI, 1, Fixups, STI); 5911 op &= UINT64_C(2097151); 5912 Value |= op; 5913 break; 5914 } 5915 case Mips::BEQZC_MMR6: 5916 case Mips::BNEZC_MMR6: { 5917 // op: rs 5918 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5919 op &= UINT64_C(31); 5920 op <<= 21; 5921 Value |= op; 5922 // op: offset 5923 op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI); 5924 op &= UINT64_C(2097151); 5925 Value |= op; 5926 break; 5927 } 5928 case Mips::BGEZ: 5929 case Mips::BGEZ64: 5930 case Mips::BGEZAL: 5931 case Mips::BGEZALL: 5932 case Mips::BGEZL: 5933 case Mips::BGTZ: 5934 case Mips::BGTZ64: 5935 case Mips::BGTZL: 5936 case Mips::BLEZ: 5937 case Mips::BLEZ64: 5938 case Mips::BLEZL: 5939 case Mips::BLTZ: 5940 case Mips::BLTZ64: 5941 case Mips::BLTZAL: 5942 case Mips::BLTZALL: 5943 case Mips::BLTZL: { 5944 // op: rs 5945 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5946 op &= UINT64_C(31); 5947 op <<= 21; 5948 Value |= op; 5949 // op: offset 5950 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 5951 op &= UINT64_C(65535); 5952 Value |= op; 5953 break; 5954 } 5955 case Mips::BBIT0: 5956 case Mips::BBIT032: 5957 case Mips::BBIT1: 5958 case Mips::BBIT132: { 5959 // op: rs 5960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5961 op &= UINT64_C(31); 5962 op <<= 21; 5963 Value |= op; 5964 // op: p 5965 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5966 op &= UINT64_C(31); 5967 op <<= 16; 5968 Value |= op; 5969 // op: offset 5970 op = getBranchTargetOpValue(MI, 2, Fixups, STI); 5971 op &= UINT64_C(65535); 5972 Value |= op; 5973 break; 5974 } 5975 case Mips::CMPU_EQ_QB: 5976 case Mips::CMPU_LE_QB: 5977 case Mips::CMPU_LT_QB: 5978 case Mips::CMP_EQ_PH: 5979 case Mips::CMP_LE_PH: 5980 case Mips::CMP_LT_PH: 5981 case Mips::DMULT: 5982 case Mips::DMULTu: 5983 case Mips::DSDIV: 5984 case Mips::DUDIV: 5985 case Mips::MADD: 5986 case Mips::MADDU: 5987 case Mips::MSUB: 5988 case Mips::MSUBU: 5989 case Mips::MULT: 5990 case Mips::MULTu: 5991 case Mips::SDIV: 5992 case Mips::UDIV: { 5993 // op: rs 5994 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5995 op &= UINT64_C(31); 5996 op <<= 21; 5997 Value |= op; 5998 // op: rt 5999 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6000 op &= UINT64_C(31); 6001 op <<= 16; 6002 Value |= op; 6003 break; 6004 } 6005 case Mips::TEQ: 6006 case Mips::TGE: 6007 case Mips::TGEU: 6008 case Mips::TLT: 6009 case Mips::TLTU: 6010 case Mips::TNE: { 6011 // op: rs 6012 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6013 op &= UINT64_C(31); 6014 op <<= 21; 6015 Value |= op; 6016 // op: rt 6017 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6018 op &= UINT64_C(31); 6019 op <<= 16; 6020 Value |= op; 6021 // op: code_ 6022 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6023 op &= UINT64_C(1023); 6024 op <<= 6; 6025 Value |= op; 6026 break; 6027 } 6028 case Mips::BEQ: 6029 case Mips::BEQ64: 6030 case Mips::BEQC: 6031 case Mips::BEQC64: 6032 case Mips::BEQL: 6033 case Mips::BGEC: 6034 case Mips::BGEC64: 6035 case Mips::BGEUC: 6036 case Mips::BGEUC64: 6037 case Mips::BLTC: 6038 case Mips::BLTC64: 6039 case Mips::BLTUC: 6040 case Mips::BLTUC64: 6041 case Mips::BNE: 6042 case Mips::BNE64: 6043 case Mips::BNEC: 6044 case Mips::BNEC64: 6045 case Mips::BNEL: 6046 case Mips::BNVC: 6047 case Mips::BOVC: { 6048 // op: rs 6049 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6050 op &= UINT64_C(31); 6051 op <<= 21; 6052 Value |= op; 6053 // op: rt 6054 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6055 op &= UINT64_C(31); 6056 op <<= 16; 6057 Value |= op; 6058 // op: offset 6059 op = getBranchTargetOpValue(MI, 2, Fixups, STI); 6060 op &= UINT64_C(65535); 6061 Value |= op; 6062 break; 6063 } 6064 case Mips::FORK: { 6065 // op: rs 6066 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6067 op &= UINT64_C(31); 6068 op <<= 21; 6069 Value |= op; 6070 // op: rt 6071 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6072 op &= UINT64_C(31); 6073 op <<= 16; 6074 Value |= op; 6075 // op: rd 6076 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6077 op &= UINT64_C(31); 6078 op <<= 11; 6079 Value |= op; 6080 break; 6081 } 6082 case Mips::GINVI: { 6083 // op: rs 6084 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6085 op &= UINT64_C(31); 6086 op <<= 21; 6087 Value |= op; 6088 // op: type_ 6089 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6090 op &= UINT64_C(3); 6091 op <<= 8; 6092 Value |= op; 6093 break; 6094 } 6095 case Mips::GINVT: { 6096 // op: rs 6097 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6098 op &= UINT64_C(31); 6099 op <<= 21; 6100 Value |= op; 6101 // op: type_ 6102 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6103 op &= UINT64_C(3); 6104 op <<= 8; 6105 Value |= op; 6106 break; 6107 } 6108 case Mips::JALRC16_MMR6: 6109 case Mips::JRC16_MMR6: { 6110 // op: rs 6111 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6112 op &= UINT64_C(31); 6113 op <<= 5; 6114 Value |= op; 6115 break; 6116 } 6117 case Mips::ADDIUPC_MM: { 6118 // op: rs 6119 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6120 op &= UINT64_C(7); 6121 op <<= 23; 6122 Value |= op; 6123 // op: imm 6124 op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI); 6125 op &= UINT64_C(8388607); 6126 Value |= op; 6127 break; 6128 } 6129 case Mips::BEQZ16_MM: 6130 case Mips::BEQZC16_MMR6: 6131 case Mips::BNEZ16_MM: 6132 case Mips::BNEZC16_MMR6: { 6133 // op: rs 6134 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6135 op &= UINT64_C(7); 6136 op <<= 7; 6137 Value |= op; 6138 // op: offset 6139 op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI); 6140 op &= UINT64_C(127); 6141 Value |= op; 6142 break; 6143 } 6144 case Mips::MOVE16_MM: 6145 case Mips::MOVE16_MMR6: { 6146 // op: rs 6147 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6148 op &= UINT64_C(31); 6149 Value |= op; 6150 // op: rd 6151 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6152 op &= UINT64_C(31); 6153 op <<= 5; 6154 Value |= op; 6155 break; 6156 } 6157 case Mips::CTCMSA: { 6158 // op: rs 6159 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6160 op &= UINT64_C(31); 6161 op <<= 11; 6162 Value |= op; 6163 // op: cd 6164 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6165 op &= UINT64_C(31); 6166 op <<= 6; 6167 Value |= op; 6168 break; 6169 } 6170 case Mips::FILL_B: 6171 case Mips::FILL_D: 6172 case Mips::FILL_H: 6173 case Mips::FILL_W: { 6174 // op: rs 6175 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6176 op &= UINT64_C(31); 6177 op <<= 11; 6178 Value |= op; 6179 // op: wd 6180 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6181 op &= UINT64_C(31); 6182 op <<= 6; 6183 Value |= op; 6184 break; 6185 } 6186 case Mips::MTHI_DSP_MM: 6187 case Mips::MTHLIP_MM: 6188 case Mips::MTLO_DSP_MM: 6189 case Mips::SHILOV_MM: { 6190 // op: rs 6191 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6192 op &= UINT64_C(31); 6193 op <<= 16; 6194 Value |= op; 6195 // op: ac 6196 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6197 op &= UINT64_C(3); 6198 op <<= 14; 6199 Value |= op; 6200 break; 6201 } 6202 case Mips::JALRS_MM: 6203 case Mips::JALR_MM: { 6204 // op: rs 6205 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6206 op &= UINT64_C(31); 6207 op <<= 16; 6208 Value |= op; 6209 // op: rd 6210 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6211 op &= UINT64_C(31); 6212 op <<= 21; 6213 Value |= op; 6214 break; 6215 } 6216 case Mips::CLO_MMR6: { 6217 // op: rs 6218 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6219 op &= UINT64_C(31); 6220 op <<= 16; 6221 Value |= op; 6222 // op: rt 6223 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6224 op &= UINT64_C(31); 6225 op <<= 21; 6226 Value |= op; 6227 break; 6228 } 6229 case Mips::AUI_MMR6: { 6230 // op: rs 6231 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6232 op &= UINT64_C(31); 6233 op <<= 16; 6234 Value |= op; 6235 // op: rt 6236 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6237 op &= UINT64_C(31); 6238 op <<= 21; 6239 Value |= op; 6240 // op: imm 6241 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6242 op &= UINT64_C(65535); 6243 Value |= op; 6244 break; 6245 } 6246 case Mips::ADDi_MM: 6247 case Mips::ADDiu_MM: 6248 case Mips::ANDi_MM: 6249 case Mips::ORi_MM: 6250 case Mips::XORi_MM: { 6251 // op: rs 6252 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6253 op &= UINT64_C(31); 6254 op <<= 16; 6255 Value |= op; 6256 // op: rt 6257 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6258 op &= UINT64_C(31); 6259 op <<= 21; 6260 Value |= op; 6261 // op: imm16 6262 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6263 op &= UINT64_C(65535); 6264 Value |= op; 6265 break; 6266 } 6267 case Mips::MTHI_DSP: 6268 case Mips::MTLO_DSP: { 6269 // op: rs 6270 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6271 op &= UINT64_C(31); 6272 op <<= 21; 6273 Value |= op; 6274 // op: ac 6275 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6276 op &= UINT64_C(3); 6277 op <<= 11; 6278 Value |= op; 6279 break; 6280 } 6281 case Mips::YIELD: { 6282 // op: rs 6283 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6284 op &= UINT64_C(31); 6285 op <<= 21; 6286 Value |= op; 6287 // op: rd 6288 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6289 op &= UINT64_C(31); 6290 op <<= 11; 6291 Value |= op; 6292 break; 6293 } 6294 case Mips::CLZ_MMR6: { 6295 // op: rs 6296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6297 op &= UINT64_C(31); 6298 op <<= 21; 6299 Value |= op; 6300 // op: rt 6301 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6302 op &= UINT64_C(31); 6303 op <<= 11; 6304 Value |= op; 6305 break; 6306 } 6307 case Mips::AUI: 6308 case Mips::DAUI: { 6309 // op: rs 6310 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6311 op &= UINT64_C(31); 6312 op <<= 21; 6313 Value |= op; 6314 // op: rt 6315 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6316 op &= UINT64_C(31); 6317 op <<= 16; 6318 Value |= op; 6319 // op: imm 6320 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6321 op &= UINT64_C(65535); 6322 Value |= op; 6323 break; 6324 } 6325 case Mips::SEQi: 6326 case Mips::SNEi: { 6327 // op: rs 6328 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6329 op &= UINT64_C(31); 6330 op <<= 21; 6331 Value |= op; 6332 // op: rt 6333 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6334 op &= UINT64_C(31); 6335 op <<= 16; 6336 Value |= op; 6337 // op: imm10 6338 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6339 op &= UINT64_C(1023); 6340 op <<= 6; 6341 Value |= op; 6342 break; 6343 } 6344 case Mips::ADDi: 6345 case Mips::ADDiu: 6346 case Mips::ANDi: 6347 case Mips::ANDi64: 6348 case Mips::DADDi: 6349 case Mips::DADDiu: 6350 case Mips::ORi: 6351 case Mips::ORi64: 6352 case Mips::XORi: 6353 case Mips::XORi64: { 6354 // op: rs 6355 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6356 op &= UINT64_C(31); 6357 op <<= 21; 6358 Value |= op; 6359 // op: rt 6360 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6361 op &= UINT64_C(31); 6362 op <<= 16; 6363 Value |= op; 6364 // op: imm16 6365 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6366 op &= UINT64_C(65535); 6367 Value |= op; 6368 break; 6369 } 6370 case Mips::PRECR_SRA_PH_W: 6371 case Mips::PRECR_SRA_R_PH_W: { 6372 // op: rs 6373 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6374 op &= UINT64_C(31); 6375 op <<= 21; 6376 Value |= op; 6377 // op: rt 6378 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6379 op &= UINT64_C(31); 6380 op <<= 16; 6381 Value |= op; 6382 // op: sa 6383 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6384 op &= UINT64_C(31); 6385 op <<= 11; 6386 Value |= op; 6387 break; 6388 } 6389 case Mips::CRC32B: 6390 case Mips::CRC32CB: 6391 case Mips::CRC32CD: 6392 case Mips::CRC32CH: 6393 case Mips::CRC32CW: 6394 case Mips::CRC32D: 6395 case Mips::CRC32H: 6396 case Mips::CRC32W: { 6397 // op: rs 6398 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6399 op &= UINT64_C(31); 6400 op <<= 21; 6401 Value |= op; 6402 // op: rt 6403 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6404 op &= UINT64_C(31); 6405 op <<= 16; 6406 Value |= op; 6407 break; 6408 } 6409 case Mips::CMPGDU_EQ_QB: 6410 case Mips::CMPGDU_LE_QB: 6411 case Mips::CMPGDU_LT_QB: 6412 case Mips::CMPGU_EQ_QB: 6413 case Mips::CMPGU_LE_QB: 6414 case Mips::CMPGU_LT_QB: 6415 case Mips::PACKRL_PH: 6416 case Mips::PICK_PH: 6417 case Mips::PICK_QB: 6418 case Mips::PRECRQU_S_QB_PH: 6419 case Mips::PRECRQ_PH_W: 6420 case Mips::PRECRQ_QB_PH: 6421 case Mips::PRECRQ_RS_PH_W: 6422 case Mips::PRECR_QB_PH: { 6423 // op: rs 6424 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6425 op &= UINT64_C(31); 6426 op <<= 21; 6427 Value |= op; 6428 // op: rt 6429 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6430 op &= UINT64_C(31); 6431 op <<= 16; 6432 Value |= op; 6433 // op: rd 6434 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6435 op &= UINT64_C(31); 6436 op <<= 11; 6437 Value |= op; 6438 break; 6439 } 6440 case Mips::DLSA: 6441 case Mips::LSA: { 6442 // op: rs 6443 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6444 op &= UINT64_C(31); 6445 op <<= 21; 6446 Value |= op; 6447 // op: rt 6448 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6449 op &= UINT64_C(31); 6450 op <<= 16; 6451 Value |= op; 6452 // op: rd 6453 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6454 op &= UINT64_C(31); 6455 op <<= 11; 6456 Value |= op; 6457 // op: sa 6458 op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI); 6459 op &= UINT64_C(3); 6460 op <<= 6; 6461 Value |= op; 6462 break; 6463 } 6464 case Mips::ADDU16_MMR6: 6465 case Mips::SUBU16_MMR6: { 6466 // op: rs 6467 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6468 op &= UINT64_C(7); 6469 op <<= 7; 6470 Value |= op; 6471 // op: rt 6472 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6473 op &= UINT64_C(7); 6474 op <<= 4; 6475 Value |= op; 6476 // op: rd 6477 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6478 op &= UINT64_C(7); 6479 op <<= 1; 6480 Value |= op; 6481 break; 6482 } 6483 case Mips::BGEZALC: 6484 case Mips::BGEZC: 6485 case Mips::BGEZC64: 6486 case Mips::BLTZALC: 6487 case Mips::BLTZC: 6488 case Mips::BLTZC64: { 6489 // op: rt 6490 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6491 Value |= (op & UINT64_C(31)) << 21; 6492 Value |= (op & UINT64_C(31)) << 16; 6493 // op: offset 6494 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 6495 op &= UINT64_C(65535); 6496 Value |= op; 6497 break; 6498 } 6499 case Mips::BGEZC_MMR6: 6500 case Mips::BLTZC_MMR6: { 6501 // op: rt 6502 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6503 Value |= (op & UINT64_C(31)) << 21; 6504 Value |= (op & UINT64_C(31)) << 16; 6505 // op: offset 6506 op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI); 6507 op &= UINT64_C(65535); 6508 Value |= op; 6509 break; 6510 } 6511 case Mips::BGEZALC_MMR6: 6512 case Mips::BLTZALC_MMR6: { 6513 // op: rt 6514 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6515 Value |= (op & UINT64_C(31)) << 21; 6516 Value |= (op & UINT64_C(31)) << 16; 6517 // op: offset 6518 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 6519 op &= UINT64_C(65535); 6520 Value |= op; 6521 break; 6522 } 6523 case Mips::DI: 6524 case Mips::DI_MM: 6525 case Mips::DI_MMR6: 6526 case Mips::DMT: 6527 case Mips::DVP: 6528 case Mips::DVPE: 6529 case Mips::EI: 6530 case Mips::EI_MM: 6531 case Mips::EI_MMR6: 6532 case Mips::EMT: 6533 case Mips::EVP: 6534 case Mips::EVPE: { 6535 // op: rt 6536 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6537 op &= UINT64_C(31); 6538 op <<= 16; 6539 Value |= op; 6540 break; 6541 } 6542 case Mips::EXTP: 6543 case Mips::EXTPDP: 6544 case Mips::EXTPDPV: 6545 case Mips::EXTPV: 6546 case Mips::EXTRV_RS_W: 6547 case Mips::EXTRV_R_W: 6548 case Mips::EXTRV_S_H: 6549 case Mips::EXTRV_W: 6550 case Mips::EXTR_RS_W: 6551 case Mips::EXTR_R_W: 6552 case Mips::EXTR_S_H: 6553 case Mips::EXTR_W: { 6554 // op: rt 6555 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6556 op &= UINT64_C(31); 6557 op <<= 16; 6558 Value |= op; 6559 // op: ac 6560 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6561 op &= UINT64_C(3); 6562 op <<= 11; 6563 Value |= op; 6564 // op: shift_rs 6565 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6566 op &= UINT64_C(31); 6567 op <<= 21; 6568 Value |= op; 6569 break; 6570 } 6571 case Mips::LL64_R6: 6572 case Mips::LLD_R6: 6573 case Mips::LL_R6: { 6574 // op: rt 6575 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6576 op &= UINT64_C(31); 6577 op <<= 16; 6578 Value |= op; 6579 // op: addr 6580 op = getMemEncoding(MI, 1, Fixups, STI); 6581 Value |= (op & UINT64_C(2031616)) << 5; 6582 Value |= (op & UINT64_C(511)) << 7; 6583 break; 6584 } 6585 case Mips::LB: 6586 case Mips::LB64: 6587 case Mips::LBu: 6588 case Mips::LBu64: 6589 case Mips::LD: 6590 case Mips::LDC1: 6591 case Mips::LDC164: 6592 case Mips::LDC2: 6593 case Mips::LDC3: 6594 case Mips::LDL: 6595 case Mips::LDR: 6596 case Mips::LEA_ADDiu: 6597 case Mips::LEA_ADDiu64: 6598 case Mips::LH: 6599 case Mips::LH64: 6600 case Mips::LHu: 6601 case Mips::LHu64: 6602 case Mips::LL: 6603 case Mips::LL64: 6604 case Mips::LLD: 6605 case Mips::LW: 6606 case Mips::LW64: 6607 case Mips::LWC1: 6608 case Mips::LWC2: 6609 case Mips::LWC3: 6610 case Mips::LWDSP: 6611 case Mips::LWL: 6612 case Mips::LWL64: 6613 case Mips::LWR: 6614 case Mips::LWR64: 6615 case Mips::LWu: 6616 case Mips::SB: 6617 case Mips::SB64: 6618 case Mips::SD: 6619 case Mips::SDC1: 6620 case Mips::SDC164: 6621 case Mips::SDC2: 6622 case Mips::SDC3: 6623 case Mips::SDL: 6624 case Mips::SDR: 6625 case Mips::SH: 6626 case Mips::SH64: 6627 case Mips::SW: 6628 case Mips::SW64: 6629 case Mips::SWC1: 6630 case Mips::SWC2: 6631 case Mips::SWC3: 6632 case Mips::SWDSP: 6633 case Mips::SWL: 6634 case Mips::SWL64: 6635 case Mips::SWR: 6636 case Mips::SWR64: { 6637 // op: rt 6638 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6639 op &= UINT64_C(31); 6640 op <<= 16; 6641 Value |= op; 6642 // op: addr 6643 op = getMemEncoding(MI, 1, Fixups, STI); 6644 Value |= (op & UINT64_C(2031616)) << 5; 6645 Value |= (op & UINT64_C(65535)); 6646 break; 6647 } 6648 case Mips::LDC2_R6: 6649 case Mips::LWC2_R6: 6650 case Mips::SDC2_R6: 6651 case Mips::SWC2_R6: { 6652 // op: rt 6653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6654 op &= UINT64_C(31); 6655 op <<= 16; 6656 Value |= op; 6657 // op: addr 6658 op = getMemEncoding(MI, 1, Fixups, STI); 6659 Value |= (op & UINT64_C(2031616)) >> 5; 6660 Value |= (op & UINT64_C(2047)); 6661 break; 6662 } 6663 case Mips::CFC1: 6664 case Mips::DMFC1: 6665 case Mips::MFC1: 6666 case Mips::MFC1_D64: 6667 case Mips::MFHC1_D32: 6668 case Mips::MFHC1_D64: { 6669 // op: rt 6670 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6671 op &= UINT64_C(31); 6672 op <<= 16; 6673 Value |= op; 6674 // op: fs 6675 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6676 op &= UINT64_C(31); 6677 op <<= 11; 6678 Value |= op; 6679 break; 6680 } 6681 case Mips::DMFC2_OCTEON: 6682 case Mips::DMTC2_OCTEON: 6683 case Mips::LUi: 6684 case Mips::LUi64: 6685 case Mips::LUi_MM: { 6686 // op: rt 6687 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6688 op &= UINT64_C(31); 6689 op <<= 16; 6690 Value |= op; 6691 // op: imm16 6692 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6693 op &= UINT64_C(65535); 6694 Value |= op; 6695 break; 6696 } 6697 case Mips::BEQZALC: 6698 case Mips::BGTZALC: 6699 case Mips::BGTZC: 6700 case Mips::BGTZC64: 6701 case Mips::BLEZALC: 6702 case Mips::BLEZC: 6703 case Mips::BLEZC64: 6704 case Mips::BNEZALC: { 6705 // op: rt 6706 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6707 op &= UINT64_C(31); 6708 op <<= 16; 6709 Value |= op; 6710 // op: offset 6711 op = getBranchTargetOpValue(MI, 1, Fixups, STI); 6712 op &= UINT64_C(65535); 6713 Value |= op; 6714 break; 6715 } 6716 case Mips::BC1EQZC_MMR6: 6717 case Mips::BC1NEZC_MMR6: 6718 case Mips::BC2EQZC_MMR6: 6719 case Mips::BC2NEZC_MMR6: { 6720 // op: rt 6721 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6722 op &= UINT64_C(31); 6723 op <<= 16; 6724 Value |= op; 6725 // op: offset 6726 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 6727 op &= UINT64_C(65535); 6728 Value |= op; 6729 break; 6730 } 6731 case Mips::JIALC: 6732 case Mips::JIALC64: 6733 case Mips::JIALC_MMR6: 6734 case Mips::JIC: 6735 case Mips::JIC64: 6736 case Mips::JIC_MMR6: { 6737 // op: rt 6738 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6739 op &= UINT64_C(31); 6740 op <<= 16; 6741 Value |= op; 6742 // op: offset 6743 op = getJumpOffset16OpValue(MI, 1, Fixups, STI); 6744 op &= UINT64_C(65535); 6745 Value |= op; 6746 break; 6747 } 6748 case Mips::DMFC0: 6749 case Mips::DMFC2: 6750 case Mips::DMFGC0: 6751 case Mips::MFC0: 6752 case Mips::MFC2: 6753 case Mips::MFGC0: 6754 case Mips::MFHGC0: { 6755 // op: rt 6756 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6757 op &= UINT64_C(31); 6758 op <<= 16; 6759 Value |= op; 6760 // op: rd 6761 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6762 op &= UINT64_C(31); 6763 op <<= 11; 6764 Value |= op; 6765 // op: sel 6766 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6767 op &= UINT64_C(7); 6768 Value |= op; 6769 break; 6770 } 6771 case Mips::RDHWR: 6772 case Mips::RDHWR64: { 6773 // op: rt 6774 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6775 op &= UINT64_C(31); 6776 op <<= 16; 6777 Value |= op; 6778 // op: rd 6779 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6780 op &= UINT64_C(31); 6781 op <<= 11; 6782 Value |= op; 6783 // op: sel 6784 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6785 op &= UINT64_C(7); 6786 op <<= 6; 6787 Value |= op; 6788 break; 6789 } 6790 case Mips::SAA: 6791 case Mips::SAAD: { 6792 // op: rt 6793 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6794 op &= UINT64_C(31); 6795 op <<= 16; 6796 Value |= op; 6797 // op: rs 6798 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6799 op &= UINT64_C(31); 6800 op <<= 21; 6801 Value |= op; 6802 break; 6803 } 6804 case Mips::SLTi: 6805 case Mips::SLTi64: 6806 case Mips::SLTiu: 6807 case Mips::SLTiu64: { 6808 // op: rt 6809 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6810 op &= UINT64_C(31); 6811 op <<= 16; 6812 Value |= op; 6813 // op: rs 6814 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6815 op &= UINT64_C(31); 6816 op <<= 21; 6817 Value |= op; 6818 // op: imm16 6819 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6820 op &= UINT64_C(65535); 6821 Value |= op; 6822 break; 6823 } 6824 case Mips::CINS: 6825 case Mips::CINS32: 6826 case Mips::CINS64_32: 6827 case Mips::CINS_i32: 6828 case Mips::EXTS: 6829 case Mips::EXTS32: { 6830 // op: rt 6831 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6832 op &= UINT64_C(31); 6833 op <<= 16; 6834 Value |= op; 6835 // op: rs 6836 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6837 op &= UINT64_C(31); 6838 op <<= 21; 6839 Value |= op; 6840 // op: pos 6841 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6842 op &= UINT64_C(31); 6843 op <<= 6; 6844 Value |= op; 6845 // op: lenm1 6846 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6847 op &= UINT64_C(31); 6848 op <<= 11; 6849 Value |= op; 6850 break; 6851 } 6852 case Mips::DINS: 6853 case Mips::DINSM: 6854 case Mips::DINSU: 6855 case Mips::INS: { 6856 // op: rt 6857 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6858 op &= UINT64_C(31); 6859 op <<= 16; 6860 Value |= op; 6861 // op: rs 6862 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6863 op &= UINT64_C(31); 6864 op <<= 21; 6865 Value |= op; 6866 // op: pos 6867 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6868 op &= UINT64_C(31); 6869 op <<= 6; 6870 Value |= op; 6871 // op: size 6872 op = getSizeInsEncoding(MI, 3, Fixups, STI); 6873 op &= UINT64_C(31); 6874 op <<= 11; 6875 Value |= op; 6876 break; 6877 } 6878 case Mips::DEXT: 6879 case Mips::DEXT64_32: 6880 case Mips::DEXTM: 6881 case Mips::DEXTU: 6882 case Mips::EXT: { 6883 // op: rt 6884 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6885 op &= UINT64_C(31); 6886 op <<= 16; 6887 Value |= op; 6888 // op: rs 6889 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6890 op &= UINT64_C(31); 6891 op <<= 21; 6892 Value |= op; 6893 // op: pos 6894 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6895 op &= UINT64_C(31); 6896 op <<= 6; 6897 Value |= op; 6898 // op: size 6899 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 6900 op &= UINT64_C(31); 6901 op <<= 11; 6902 Value |= op; 6903 break; 6904 } 6905 case Mips::APPEND: 6906 case Mips::BALIGN: 6907 case Mips::PREPEND: { 6908 // op: rt 6909 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6910 op &= UINT64_C(31); 6911 op <<= 16; 6912 Value |= op; 6913 // op: rs 6914 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6915 op &= UINT64_C(31); 6916 op <<= 21; 6917 Value |= op; 6918 // op: sa 6919 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6920 op &= UINT64_C(31); 6921 op <<= 11; 6922 Value |= op; 6923 break; 6924 } 6925 case Mips::INSV: { 6926 // op: rt 6927 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6928 op &= UINT64_C(31); 6929 op <<= 16; 6930 Value |= op; 6931 // op: rs 6932 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6933 op &= UINT64_C(31); 6934 op <<= 21; 6935 Value |= op; 6936 break; 6937 } 6938 case Mips::LWU_MM: { 6939 // op: rt 6940 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6941 op &= UINT64_C(31); 6942 op <<= 21; 6943 Value |= op; 6944 // op: addr 6945 op = getMemEncoding(MI, 1, Fixups, STI); 6946 Value |= (op & UINT64_C(2031616)); 6947 Value |= (op & UINT64_C(4095)); 6948 break; 6949 } 6950 case Mips::LBE_MM: 6951 case Mips::LBuE_MM: 6952 case Mips::LHE_MM: 6953 case Mips::LHuE_MM: 6954 case Mips::LLE_MM: 6955 case Mips::LWE_MM: 6956 case Mips::SBE_MM: 6957 case Mips::SHE_MM: 6958 case Mips::SWE_MM: { 6959 // op: rt 6960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6961 op &= UINT64_C(31); 6962 op <<= 21; 6963 Value |= op; 6964 // op: addr 6965 op = getMemEncoding(MI, 1, Fixups, STI); 6966 Value |= (op & UINT64_C(2031616)); 6967 Value |= (op & UINT64_C(511)); 6968 break; 6969 } 6970 case Mips::LEA_ADDiu_MM: 6971 case Mips::LH_MM: 6972 case Mips::LHu_MM: 6973 case Mips::LWDSP_MM: 6974 case Mips::LW_MM: 6975 case Mips::LW_MMR6: 6976 case Mips::SB_MM: 6977 case Mips::SB_MMR6: 6978 case Mips::SH_MM: 6979 case Mips::SH_MMR6: 6980 case Mips::SWDSP_MM: 6981 case Mips::SW_MM: 6982 case Mips::SW_MMR6: { 6983 // op: rt 6984 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6985 op &= UINT64_C(31); 6986 op <<= 21; 6987 Value |= op; 6988 // op: addr 6989 op = getMemEncoding(MI, 1, Fixups, STI); 6990 op &= UINT64_C(2097151); 6991 Value |= op; 6992 break; 6993 } 6994 case Mips::LWP_MM: 6995 case Mips::SWP_MM: { 6996 // op: rt 6997 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6998 op &= UINT64_C(31); 6999 op <<= 21; 7000 Value |= op; 7001 // op: addr 7002 op = getMemEncoding(MI, 2, Fixups, STI); 7003 Value |= (op & UINT64_C(2031616)); 7004 Value |= (op & UINT64_C(4095)); 7005 break; 7006 } 7007 case Mips::LDC2_MMR6: 7008 case Mips::LWC2_MMR6: 7009 case Mips::SDC2_MMR6: 7010 case Mips::SWC2_MMR6: { 7011 // op: rt 7012 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7013 op &= UINT64_C(31); 7014 op <<= 21; 7015 Value |= op; 7016 // op: addr 7017 op = getMemEncodingMMImm11(MI, 1, Fixups, STI); 7018 Value |= (op & UINT64_C(2031616)); 7019 Value |= (op & UINT64_C(2047)); 7020 break; 7021 } 7022 case Mips::LL_MM: 7023 case Mips::LWL_MM: 7024 case Mips::LWR_MM: 7025 case Mips::SWL_MM: 7026 case Mips::SWR_MM: { 7027 // op: rt 7028 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7029 op &= UINT64_C(31); 7030 op <<= 21; 7031 Value |= op; 7032 // op: addr 7033 op = getMemEncodingMMImm12(MI, 1, Fixups, STI); 7034 Value |= (op & UINT64_C(2031616)); 7035 Value |= (op & UINT64_C(4095)); 7036 break; 7037 } 7038 case Mips::LB_MM: 7039 case Mips::LBu_MM: 7040 case Mips::LDC1_MM: 7041 case Mips::LWC1_MM: 7042 case Mips::SDC1_MM: 7043 case Mips::SWC1_MM: { 7044 // op: rt 7045 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7046 op &= UINT64_C(31); 7047 op <<= 21; 7048 Value |= op; 7049 // op: addr 7050 op = getMemEncodingMMImm16(MI, 1, Fixups, STI); 7051 op &= UINT64_C(2097151); 7052 Value |= op; 7053 break; 7054 } 7055 case Mips::LL_MMR6: 7056 case Mips::LWLE_MM: 7057 case Mips::LWRE_MM: 7058 case Mips::SWLE_MM: 7059 case Mips::SWRE_MM: { 7060 // op: rt 7061 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7062 op &= UINT64_C(31); 7063 op <<= 21; 7064 Value |= op; 7065 // op: addr 7066 op = getMemEncodingMMImm9(MI, 1, Fixups, STI); 7067 Value |= (op & UINT64_C(2031616)); 7068 Value |= (op & UINT64_C(511)); 7069 break; 7070 } 7071 case Mips::CFC1_MM: 7072 case Mips::MFC1_MM: 7073 case Mips::MFC1_MMR6: 7074 case Mips::MFHC1_D32_MM: 7075 case Mips::MFHC1_D64_MM: { 7076 // op: rt 7077 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7078 op &= UINT64_C(31); 7079 op <<= 21; 7080 Value |= op; 7081 // op: fs 7082 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7083 op &= UINT64_C(31); 7084 op <<= 16; 7085 Value |= op; 7086 break; 7087 } 7088 case Mips::REPL_QB_MM: { 7089 // op: rt 7090 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7091 op &= UINT64_C(31); 7092 op <<= 21; 7093 Value |= op; 7094 // op: imm 7095 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7096 op &= UINT64_C(255); 7097 op <<= 13; 7098 Value |= op; 7099 break; 7100 } 7101 case Mips::ALUIPC_MMR6: 7102 case Mips::AUIPC_MMR6: { 7103 // op: rt 7104 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7105 op &= UINT64_C(31); 7106 op <<= 21; 7107 Value |= op; 7108 // op: imm 7109 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7110 op &= UINT64_C(65535); 7111 Value |= op; 7112 break; 7113 } 7114 case Mips::EXTPDP_MM: 7115 case Mips::EXTP_MM: 7116 case Mips::EXTR_RS_W_MM: 7117 case Mips::EXTR_R_W_MM: 7118 case Mips::EXTR_S_H_MM: 7119 case Mips::EXTR_W_MM: { 7120 // op: rt 7121 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7122 op &= UINT64_C(31); 7123 op <<= 21; 7124 Value |= op; 7125 // op: imm 7126 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7127 op &= UINT64_C(31); 7128 op <<= 16; 7129 Value |= op; 7130 // op: ac 7131 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7132 op &= UINT64_C(3); 7133 op <<= 14; 7134 Value |= op; 7135 break; 7136 } 7137 case Mips::ADDIUPC_MMR6: 7138 case Mips::LWPC_MMR6: { 7139 // op: rt 7140 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7141 op &= UINT64_C(31); 7142 op <<= 21; 7143 Value |= op; 7144 // op: imm 7145 op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI); 7146 op &= UINT64_C(524287); 7147 Value |= op; 7148 break; 7149 } 7150 case Mips::LUI_MMR6: { 7151 // op: rt 7152 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7153 op &= UINT64_C(31); 7154 op <<= 21; 7155 Value |= op; 7156 // op: imm16 7157 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7158 op &= UINT64_C(65535); 7159 Value |= op; 7160 break; 7161 } 7162 case Mips::CFC2_MM: 7163 case Mips::MFC2_MMR6: 7164 case Mips::MFHC2_MMR6: { 7165 // op: rt 7166 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7167 op &= UINT64_C(31); 7168 op <<= 21; 7169 Value |= op; 7170 // op: impl 7171 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7172 op &= UINT64_C(31); 7173 op <<= 16; 7174 Value |= op; 7175 break; 7176 } 7177 case Mips::RDDSP_MM: 7178 case Mips::WRDSP_MM: { 7179 // op: rt 7180 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7181 op &= UINT64_C(31); 7182 op <<= 21; 7183 Value |= op; 7184 // op: mask 7185 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7186 op &= UINT64_C(127); 7187 op <<= 14; 7188 Value |= op; 7189 break; 7190 } 7191 case Mips::BGTZC_MMR6: 7192 case Mips::BLEZC_MMR6: { 7193 // op: rt 7194 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7195 op &= UINT64_C(31); 7196 op <<= 21; 7197 Value |= op; 7198 // op: offset 7199 op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI); 7200 op &= UINT64_C(65535); 7201 Value |= op; 7202 break; 7203 } 7204 case Mips::BEQZALC_MMR6: 7205 case Mips::BGTZALC_MMR6: 7206 case Mips::BLEZALC_MMR6: 7207 case Mips::BNEZALC_MMR6: { 7208 // op: rt 7209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7210 op &= UINT64_C(31); 7211 op <<= 21; 7212 Value |= op; 7213 // op: offset 7214 op = getBranchTargetOpValueMM(MI, 1, Fixups, STI); 7215 op &= UINT64_C(65535); 7216 Value |= op; 7217 break; 7218 } 7219 case Mips::RDHWR_MM: 7220 case Mips::RDPGPR_MMR6: { 7221 // op: rt 7222 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7223 op &= UINT64_C(31); 7224 op <<= 21; 7225 Value |= op; 7226 // op: rd 7227 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7228 op &= UINT64_C(31); 7229 op <<= 16; 7230 Value |= op; 7231 break; 7232 } 7233 case Mips::ABSQ_S_PH_MM: 7234 case Mips::ABSQ_S_QB_MMR2: 7235 case Mips::ABSQ_S_W_MM: 7236 case Mips::BITREV_MM: 7237 case Mips::JALRC_HB_MMR6: 7238 case Mips::JALRC_MMR6: 7239 case Mips::PRECEQU_PH_QBLA_MM: 7240 case Mips::PRECEQU_PH_QBL_MM: 7241 case Mips::PRECEQU_PH_QBRA_MM: 7242 case Mips::PRECEQU_PH_QBR_MM: 7243 case Mips::PRECEQ_W_PHL_MM: 7244 case Mips::PRECEQ_W_PHR_MM: 7245 case Mips::PRECEU_PH_QBLA_MM: 7246 case Mips::PRECEU_PH_QBL_MM: 7247 case Mips::PRECEU_PH_QBRA_MM: 7248 case Mips::PRECEU_PH_QBR_MM: 7249 case Mips::RADDU_W_QB_MM: 7250 case Mips::REPLV_PH_MM: 7251 case Mips::REPLV_QB_MM: 7252 case Mips::WRPGPR_MMR6: 7253 case Mips::WSBH_MMR6: { 7254 // op: rt 7255 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7256 op &= UINT64_C(31); 7257 op <<= 21; 7258 Value |= op; 7259 // op: rs 7260 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7261 op &= UINT64_C(31); 7262 op <<= 16; 7263 Value |= op; 7264 break; 7265 } 7266 case Mips::BALIGN_MMR2: { 7267 // op: rt 7268 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7269 op &= UINT64_C(31); 7270 op <<= 21; 7271 Value |= op; 7272 // op: rs 7273 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7274 op &= UINT64_C(31); 7275 op <<= 16; 7276 Value |= op; 7277 // op: bp 7278 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7279 op &= UINT64_C(3); 7280 op <<= 14; 7281 Value |= op; 7282 break; 7283 } 7284 case Mips::ADDIU_MMR6: 7285 case Mips::ANDI_MMR6: 7286 case Mips::ORI_MMR6: 7287 case Mips::SLTi_MM: 7288 case Mips::SLTiu_MM: 7289 case Mips::XORI_MMR6: { 7290 // op: rt 7291 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7292 op &= UINT64_C(31); 7293 op <<= 21; 7294 Value |= op; 7295 // op: rs 7296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7297 op &= UINT64_C(31); 7298 op <<= 16; 7299 Value |= op; 7300 // op: imm16 7301 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7302 op &= UINT64_C(65535); 7303 Value |= op; 7304 break; 7305 } 7306 case Mips::BNVC_MMR6: 7307 case Mips::BOVC_MMR6: { 7308 // op: rt 7309 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7310 op &= UINT64_C(31); 7311 op <<= 21; 7312 Value |= op; 7313 // op: rs 7314 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7315 op &= UINT64_C(31); 7316 op <<= 16; 7317 Value |= op; 7318 // op: offset 7319 op = getBranchTargetOpValueMMR6(MI, 2, Fixups, STI); 7320 op &= UINT64_C(65535); 7321 Value |= op; 7322 break; 7323 } 7324 case Mips::INS_MM: { 7325 // op: rt 7326 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7327 op &= UINT64_C(31); 7328 op <<= 21; 7329 Value |= op; 7330 // op: rs 7331 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7332 op &= UINT64_C(31); 7333 op <<= 16; 7334 Value |= op; 7335 // op: pos 7336 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7337 op &= UINT64_C(31); 7338 op <<= 6; 7339 Value |= op; 7340 // op: size 7341 op = getSizeInsEncoding(MI, 3, Fixups, STI); 7342 op &= UINT64_C(31); 7343 op <<= 11; 7344 Value |= op; 7345 break; 7346 } 7347 case Mips::EXT_MM: { 7348 // op: rt 7349 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7350 op &= UINT64_C(31); 7351 op <<= 21; 7352 Value |= op; 7353 // op: rs 7354 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7355 op &= UINT64_C(31); 7356 op <<= 16; 7357 Value |= op; 7358 // op: pos 7359 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7360 op &= UINT64_C(31); 7361 op <<= 6; 7362 Value |= op; 7363 // op: size 7364 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 7365 op &= UINT64_C(31); 7366 op <<= 11; 7367 Value |= op; 7368 break; 7369 } 7370 case Mips::SHLL_PH_MM: 7371 case Mips::SHLL_S_PH_MM: 7372 case Mips::SHRA_PH_MM: 7373 case Mips::SHRA_R_PH_MM: 7374 case Mips::SHRL_PH_MMR2: { 7375 // op: rt 7376 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7377 op &= UINT64_C(31); 7378 op <<= 21; 7379 Value |= op; 7380 // op: rs 7381 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7382 op &= UINT64_C(31); 7383 op <<= 16; 7384 Value |= op; 7385 // op: sa 7386 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7387 op &= UINT64_C(15); 7388 op <<= 12; 7389 Value |= op; 7390 break; 7391 } 7392 case Mips::APPEND_MMR2: 7393 case Mips::PRECR_SRA_PH_W_MMR2: 7394 case Mips::PRECR_SRA_R_PH_W_MMR2: 7395 case Mips::PREPEND_MMR2: 7396 case Mips::SHLL_S_W_MM: 7397 case Mips::SHRA_R_W_MM: { 7398 // op: rt 7399 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7400 op &= UINT64_C(31); 7401 op <<= 21; 7402 Value |= op; 7403 // op: rs 7404 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7405 op &= UINT64_C(31); 7406 op <<= 16; 7407 Value |= op; 7408 // op: sa 7409 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7410 op &= UINT64_C(31); 7411 op <<= 11; 7412 Value |= op; 7413 break; 7414 } 7415 case Mips::SHLL_QB_MM: 7416 case Mips::SHRA_QB_MMR2: 7417 case Mips::SHRA_R_QB_MMR2: 7418 case Mips::SHRL_QB_MM: { 7419 // op: rt 7420 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7421 op &= UINT64_C(31); 7422 op <<= 21; 7423 Value |= op; 7424 // op: rs 7425 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7426 op &= UINT64_C(31); 7427 op <<= 16; 7428 Value |= op; 7429 // op: sa 7430 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7431 op &= UINT64_C(7); 7432 op <<= 13; 7433 Value |= op; 7434 break; 7435 } 7436 case Mips::MFC0_MMR6: 7437 case Mips::MFGC0_MM: 7438 case Mips::MFHC0_MMR6: 7439 case Mips::MFHGC0_MM: 7440 case Mips::RDHWR_MMR6: { 7441 // op: rt 7442 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7443 op &= UINT64_C(31); 7444 op <<= 21; 7445 Value |= op; 7446 // op: rs 7447 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7448 op &= UINT64_C(31); 7449 op <<= 16; 7450 Value |= op; 7451 // op: sel 7452 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7453 op &= UINT64_C(7); 7454 op <<= 11; 7455 Value |= op; 7456 break; 7457 } 7458 case Mips::INS_MMR6: { 7459 // op: rt 7460 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7461 op &= UINT64_C(31); 7462 op <<= 21; 7463 Value |= op; 7464 // op: rs 7465 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7466 op &= UINT64_C(31); 7467 op <<= 16; 7468 Value |= op; 7469 // op: size 7470 op = getSizeInsEncoding(MI, 3, Fixups, STI); 7471 op &= UINT64_C(31); 7472 op <<= 11; 7473 Value |= op; 7474 // op: pos 7475 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7476 op &= UINT64_C(31); 7477 op <<= 6; 7478 Value |= op; 7479 break; 7480 } 7481 case Mips::EXT_MMR6: { 7482 // op: rt 7483 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7484 op &= UINT64_C(31); 7485 op <<= 21; 7486 Value |= op; 7487 // op: rs 7488 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7489 op &= UINT64_C(31); 7490 op <<= 16; 7491 Value |= op; 7492 // op: size 7493 op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI); 7494 op &= UINT64_C(31); 7495 op <<= 11; 7496 Value |= op; 7497 // op: pos 7498 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7499 op &= UINT64_C(31); 7500 op <<= 6; 7501 Value |= op; 7502 break; 7503 } 7504 case Mips::INSV_MM: { 7505 // op: rt 7506 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7507 op &= UINT64_C(31); 7508 op <<= 21; 7509 Value |= op; 7510 // op: rs 7511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7512 op &= UINT64_C(31); 7513 op <<= 16; 7514 Value |= op; 7515 break; 7516 } 7517 case Mips::EXTPDPV_MM: 7518 case Mips::EXTPV_MM: 7519 case Mips::EXTRV_RS_W_MM: 7520 case Mips::EXTRV_R_W_MM: 7521 case Mips::EXTRV_S_H_MM: 7522 case Mips::EXTRV_W_MM: { 7523 // op: rt 7524 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7525 op &= UINT64_C(31); 7526 op <<= 21; 7527 Value |= op; 7528 // op: rs 7529 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7530 op &= UINT64_C(31); 7531 op <<= 16; 7532 Value |= op; 7533 // op: ac 7534 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7535 op &= UINT64_C(3); 7536 op <<= 14; 7537 Value |= op; 7538 break; 7539 } 7540 case Mips::LWSP_MM: 7541 case Mips::SWSP_MM: 7542 case Mips::SWSP_MMR6: { 7543 // op: rt 7544 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7545 op &= UINT64_C(31); 7546 op <<= 5; 7547 Value |= op; 7548 // op: offset 7549 op = getMemEncodingMMSPImm5Lsl2(MI, 1, Fixups, STI); 7550 op &= UINT64_C(31); 7551 Value |= op; 7552 break; 7553 } 7554 case Mips::NOT16_MM: { 7555 // op: rt 7556 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7557 op &= UINT64_C(7); 7558 op <<= 3; 7559 Value |= op; 7560 // op: rs 7561 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7562 op &= UINT64_C(7); 7563 Value |= op; 7564 break; 7565 } 7566 case Mips::LBU16_MM: 7567 case Mips::SB16_MM: 7568 case Mips::SB16_MMR6: { 7569 // op: rt 7570 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7571 op &= UINT64_C(7); 7572 op <<= 7; 7573 Value |= op; 7574 // op: addr 7575 op = getMemEncodingMMImm4(MI, 1, Fixups, STI); 7576 op &= UINT64_C(127); 7577 Value |= op; 7578 break; 7579 } 7580 case Mips::LHU16_MM: 7581 case Mips::SH16_MM: 7582 case Mips::SH16_MMR6: { 7583 // op: rt 7584 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7585 op &= UINT64_C(7); 7586 op <<= 7; 7587 Value |= op; 7588 // op: addr 7589 op = getMemEncodingMMImm4Lsl1(MI, 1, Fixups, STI); 7590 op &= UINT64_C(127); 7591 Value |= op; 7592 break; 7593 } 7594 case Mips::LW16_MM: 7595 case Mips::SW16_MM: 7596 case Mips::SW16_MMR6: { 7597 // op: rt 7598 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7599 op &= UINT64_C(7); 7600 op <<= 7; 7601 Value |= op; 7602 // op: addr 7603 op = getMemEncodingMMImm4Lsl2(MI, 1, Fixups, STI); 7604 op &= UINT64_C(127); 7605 Value |= op; 7606 break; 7607 } 7608 case Mips::LWGP_MM: { 7609 // op: rt 7610 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7611 op &= UINT64_C(7); 7612 op <<= 7; 7613 Value |= op; 7614 // op: offset 7615 op = getMemEncodingMMGPImm7Lsl2(MI, 1, Fixups, STI); 7616 op &= UINT64_C(127); 7617 Value |= op; 7618 break; 7619 } 7620 case Mips::NOT16_MMR6: { 7621 // op: rt 7622 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7623 op &= UINT64_C(7); 7624 op <<= 7; 7625 Value |= op; 7626 // op: rs 7627 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7628 op &= UINT64_C(7); 7629 op <<= 4; 7630 Value |= op; 7631 break; 7632 } 7633 case Mips::SC64_R6: 7634 case Mips::SCD_R6: 7635 case Mips::SC_R6: { 7636 // op: rt 7637 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7638 op &= UINT64_C(31); 7639 op <<= 16; 7640 Value |= op; 7641 // op: addr 7642 op = getMemEncoding(MI, 2, Fixups, STI); 7643 Value |= (op & UINT64_C(2031616)) << 5; 7644 Value |= (op & UINT64_C(511)) << 7; 7645 break; 7646 } 7647 case Mips::SC: 7648 case Mips::SC64: 7649 case Mips::SCD: { 7650 // op: rt 7651 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7652 op &= UINT64_C(31); 7653 op <<= 16; 7654 Value |= op; 7655 // op: addr 7656 op = getMemEncoding(MI, 2, Fixups, STI); 7657 Value |= (op & UINT64_C(2031616)) << 5; 7658 Value |= (op & UINT64_C(65535)); 7659 break; 7660 } 7661 case Mips::CTC1: 7662 case Mips::DMTC1: 7663 case Mips::MTC1: 7664 case Mips::MTC1_D64: { 7665 // op: rt 7666 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7667 op &= UINT64_C(31); 7668 op <<= 16; 7669 Value |= op; 7670 // op: fs 7671 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7672 op &= UINT64_C(31); 7673 op <<= 11; 7674 Value |= op; 7675 break; 7676 } 7677 case Mips::DMTC0: 7678 case Mips::DMTC2: 7679 case Mips::DMTGC0: 7680 case Mips::MTC0: 7681 case Mips::MTC2: 7682 case Mips::MTGC0: 7683 case Mips::MTHGC0: { 7684 // op: rt 7685 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7686 op &= UINT64_C(31); 7687 op <<= 16; 7688 Value |= op; 7689 // op: rd 7690 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7691 op &= UINT64_C(31); 7692 op <<= 11; 7693 Value |= op; 7694 // op: sel 7695 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7696 op &= UINT64_C(7); 7697 Value |= op; 7698 break; 7699 } 7700 case Mips::MFTR: 7701 case Mips::MTTR: { 7702 // op: rt 7703 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7704 op &= UINT64_C(31); 7705 op <<= 16; 7706 Value |= op; 7707 // op: rd 7708 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7709 op &= UINT64_C(31); 7710 op <<= 11; 7711 Value |= op; 7712 // op: u 7713 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7714 op &= UINT64_C(1); 7715 op <<= 5; 7716 Value |= op; 7717 // op: h 7718 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7719 op &= UINT64_C(1); 7720 op <<= 4; 7721 Value |= op; 7722 // op: sel 7723 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7724 op &= UINT64_C(7); 7725 Value |= op; 7726 break; 7727 } 7728 case Mips::SCE_MM: { 7729 // op: rt 7730 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7731 op &= UINT64_C(31); 7732 op <<= 21; 7733 Value |= op; 7734 // op: addr 7735 op = getMemEncoding(MI, 2, Fixups, STI); 7736 Value |= (op & UINT64_C(2031616)); 7737 Value |= (op & UINT64_C(511)); 7738 break; 7739 } 7740 case Mips::SC_MM: { 7741 // op: rt 7742 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7743 op &= UINT64_C(31); 7744 op <<= 21; 7745 Value |= op; 7746 // op: addr 7747 op = getMemEncodingMMImm12(MI, 2, Fixups, STI); 7748 Value |= (op & UINT64_C(2031616)); 7749 Value |= (op & UINT64_C(4095)); 7750 break; 7751 } 7752 case Mips::SC_MMR6: { 7753 // op: rt 7754 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7755 op &= UINT64_C(31); 7756 op <<= 21; 7757 Value |= op; 7758 // op: addr 7759 op = getMemEncodingMMImm9(MI, 2, Fixups, STI); 7760 Value |= (op & UINT64_C(2031616)); 7761 Value |= (op & UINT64_C(511)); 7762 break; 7763 } 7764 case Mips::CTC1_MM: 7765 case Mips::MTC1_D64_MM: 7766 case Mips::MTC1_MM: 7767 case Mips::MTC1_MMR6: { 7768 // op: rt 7769 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7770 op &= UINT64_C(31); 7771 op <<= 21; 7772 Value |= op; 7773 // op: fs 7774 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7775 op &= UINT64_C(31); 7776 op <<= 16; 7777 Value |= op; 7778 break; 7779 } 7780 case Mips::CTC2_MM: 7781 case Mips::MTC2_MMR6: 7782 case Mips::MTHC2_MMR6: { 7783 // op: rt 7784 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7785 op &= UINT64_C(31); 7786 op <<= 21; 7787 Value |= op; 7788 // op: impl 7789 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7790 op &= UINT64_C(31); 7791 op <<= 16; 7792 Value |= op; 7793 break; 7794 } 7795 case Mips::CMPU_EQ_QB_MM: 7796 case Mips::CMPU_LE_QB_MM: 7797 case Mips::CMPU_LT_QB_MM: 7798 case Mips::CMP_EQ_PH_MM: 7799 case Mips::CMP_LE_PH_MM: 7800 case Mips::CMP_LT_PH_MM: { 7801 // op: rt 7802 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7803 op &= UINT64_C(31); 7804 op <<= 21; 7805 Value |= op; 7806 // op: rs 7807 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7808 op &= UINT64_C(31); 7809 op <<= 16; 7810 Value |= op; 7811 break; 7812 } 7813 case Mips::BEQC_MMR6: 7814 case Mips::BGEC_MMR6: 7815 case Mips::BGEUC_MMR6: 7816 case Mips::BLTC_MMR6: 7817 case Mips::BLTUC_MMR6: 7818 case Mips::BNEC_MMR6: { 7819 // op: rt 7820 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7821 op &= UINT64_C(31); 7822 op <<= 21; 7823 Value |= op; 7824 // op: rs 7825 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7826 op &= UINT64_C(31); 7827 op <<= 16; 7828 Value |= op; 7829 // op: offset 7830 op = getBranchTargetOpValueLsl2MMR6(MI, 2, Fixups, STI); 7831 op &= UINT64_C(65535); 7832 Value |= op; 7833 break; 7834 } 7835 case Mips::MTC0_MMR6: 7836 case Mips::MTGC0_MM: 7837 case Mips::MTHC0_MMR6: 7838 case Mips::MTHGC0_MM: { 7839 // op: rt 7840 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7841 op &= UINT64_C(31); 7842 op <<= 21; 7843 Value |= op; 7844 // op: rs 7845 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7846 op &= UINT64_C(31); 7847 op <<= 16; 7848 Value |= op; 7849 // op: sel 7850 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7851 op &= UINT64_C(7); 7852 op <<= 11; 7853 Value |= op; 7854 break; 7855 } 7856 case Mips::MTHC1_D32: 7857 case Mips::MTHC1_D64: { 7858 // op: rt 7859 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7860 op &= UINT64_C(31); 7861 op <<= 16; 7862 Value |= op; 7863 // op: fs 7864 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7865 op &= UINT64_C(31); 7866 op <<= 11; 7867 Value |= op; 7868 break; 7869 } 7870 case Mips::SPLAT_B: 7871 case Mips::SPLAT_D: 7872 case Mips::SPLAT_H: 7873 case Mips::SPLAT_W: { 7874 // op: rt 7875 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7876 op &= UINT64_C(31); 7877 op <<= 16; 7878 Value |= op; 7879 // op: ws 7880 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7881 op &= UINT64_C(31); 7882 op <<= 11; 7883 Value |= op; 7884 // op: wd 7885 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7886 op &= UINT64_C(31); 7887 op <<= 6; 7888 Value |= op; 7889 break; 7890 } 7891 case Mips::MTHC1_D32_MM: 7892 case Mips::MTHC1_D64_MM: { 7893 // op: rt 7894 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7895 op &= UINT64_C(31); 7896 op <<= 21; 7897 Value |= op; 7898 // op: fs 7899 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7900 op &= UINT64_C(31); 7901 op <<= 16; 7902 Value |= op; 7903 break; 7904 } 7905 case Mips::DPAQX_SA_W_PH_MMR2: 7906 case Mips::DPAQX_S_W_PH_MMR2: 7907 case Mips::DPAQ_SA_L_W_MM: 7908 case Mips::DPAQ_S_W_PH_MM: 7909 case Mips::DPAU_H_QBL_MM: 7910 case Mips::DPAU_H_QBR_MM: 7911 case Mips::DPAX_W_PH_MMR2: 7912 case Mips::DPA_W_PH_MMR2: 7913 case Mips::DPSQX_SA_W_PH_MMR2: 7914 case Mips::DPSQX_S_W_PH_MMR2: 7915 case Mips::DPSQ_SA_L_W_MM: 7916 case Mips::DPSQ_S_W_PH_MM: 7917 case Mips::DPSU_H_QBL_MM: 7918 case Mips::DPSU_H_QBR_MM: 7919 case Mips::DPSX_W_PH_MMR2: 7920 case Mips::DPS_W_PH_MMR2: 7921 case Mips::MADDU_DSP_MM: 7922 case Mips::MADD_DSP_MM: 7923 case Mips::MAQ_SA_W_PHL_MM: 7924 case Mips::MAQ_SA_W_PHR_MM: 7925 case Mips::MAQ_S_W_PHL_MM: 7926 case Mips::MAQ_S_W_PHR_MM: 7927 case Mips::MSUBU_DSP_MM: 7928 case Mips::MSUB_DSP_MM: 7929 case Mips::MULSAQ_S_W_PH_MM: 7930 case Mips::MULSA_W_PH_MMR2: 7931 case Mips::MULTU_DSP_MM: 7932 case Mips::MULT_DSP_MM: { 7933 // op: rt 7934 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7935 op &= UINT64_C(31); 7936 op <<= 21; 7937 Value |= op; 7938 // op: rs 7939 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7940 op &= UINT64_C(31); 7941 op <<= 16; 7942 Value |= op; 7943 // op: ac 7944 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7945 op &= UINT64_C(3); 7946 op <<= 14; 7947 Value |= op; 7948 break; 7949 } 7950 case Mips::ADD_MM: 7951 case Mips::ADDu_MM: 7952 case Mips::AND_MM: 7953 case Mips::CMPGU_EQ_QB_MM: 7954 case Mips::CMPGU_LE_QB_MM: 7955 case Mips::CMPGU_LT_QB_MM: 7956 case Mips::MOVN_I_MM: 7957 case Mips::MOVZ_I_MM: 7958 case Mips::MUL_MM: 7959 case Mips::NOR_MM: 7960 case Mips::OR_MM: 7961 case Mips::SLT_MM: 7962 case Mips::SLTu_MM: 7963 case Mips::SUB_MM: 7964 case Mips::SUBu_MM: 7965 case Mips::XOR_MM: { 7966 // op: rt 7967 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7968 op &= UINT64_C(31); 7969 op <<= 21; 7970 Value |= op; 7971 // op: rs 7972 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7973 op &= UINT64_C(31); 7974 op <<= 16; 7975 Value |= op; 7976 // op: rd 7977 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7978 op &= UINT64_C(31); 7979 op <<= 11; 7980 Value |= op; 7981 break; 7982 } 7983 case Mips::AND16_MM: 7984 case Mips::OR16_MM: 7985 case Mips::XOR16_MM: { 7986 // op: rt 7987 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7988 op &= UINT64_C(7); 7989 op <<= 3; 7990 Value |= op; 7991 // op: rs 7992 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7993 op &= UINT64_C(7); 7994 Value |= op; 7995 break; 7996 } 7997 case Mips::AND16_MMR6: 7998 case Mips::OR16_MMR6: 7999 case Mips::XOR16_MMR6: { 8000 // op: rt 8001 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8002 op &= UINT64_C(7); 8003 op <<= 7; 8004 Value |= op; 8005 // op: rs 8006 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8007 op &= UINT64_C(7); 8008 op <<= 4; 8009 Value |= op; 8010 break; 8011 } 8012 case Mips::SLD_B: 8013 case Mips::SLD_D: 8014 case Mips::SLD_H: 8015 case Mips::SLD_W: { 8016 // op: rt 8017 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8018 op &= UINT64_C(31); 8019 op <<= 16; 8020 Value |= op; 8021 // op: ws 8022 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8023 op &= UINT64_C(31); 8024 op <<= 11; 8025 Value |= op; 8026 // op: wd 8027 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8028 op &= UINT64_C(31); 8029 op <<= 6; 8030 Value |= op; 8031 break; 8032 } 8033 case Mips::LWM32_MM: 8034 case Mips::SWM32_MM: { 8035 // op: rt 8036 op = getRegisterListOpValue(MI, 0, Fixups, STI); 8037 op &= UINT64_C(31); 8038 op <<= 21; 8039 Value |= op; 8040 // op: addr 8041 op = getMemEncodingMMImm12(MI, 1, Fixups, STI); 8042 Value |= (op & UINT64_C(2031616)); 8043 Value |= (op & UINT64_C(4095)); 8044 break; 8045 } 8046 case Mips::LWM16_MM: 8047 case Mips::SWM16_MM: { 8048 // op: rt 8049 op = getRegisterListOpValue16(MI, 0, Fixups, STI); 8050 op &= UINT64_C(3); 8051 op <<= 4; 8052 Value |= op; 8053 // op: addr 8054 op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI); 8055 op &= UINT64_C(15); 8056 Value |= op; 8057 break; 8058 } 8059 case Mips::LWM16_MMR6: 8060 case Mips::SWM16_MMR6: { 8061 // op: rt 8062 op = getRegisterListOpValue16(MI, 0, Fixups, STI); 8063 op &= UINT64_C(3); 8064 op <<= 8; 8065 Value |= op; 8066 // op: addr 8067 op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI); 8068 op &= UINT64_C(15); 8069 op <<= 4; 8070 Value |= op; 8071 break; 8072 } 8073 case Mips::JrcRx16: 8074 case Mips::JumpLinkReg16: 8075 case Mips::SebRx16: 8076 case Mips::SehRx16: { 8077 // op: rx 8078 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8079 op &= UINT64_C(7); 8080 op <<= 8; 8081 Value |= op; 8082 break; 8083 } 8084 case Mips::AddiuRxRxImm16: 8085 case Mips::BeqzRxImm16: 8086 case Mips::BnezRxImm16: 8087 case Mips::CmpiRxImm16: 8088 case Mips::LiRxImm16: 8089 case Mips::LwRxPcTcp16: 8090 case Mips::SltiRxImm16: 8091 case Mips::SltiuRxImm16: { 8092 // op: rx 8093 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8094 op &= UINT64_C(7); 8095 op <<= 8; 8096 Value |= op; 8097 // op: imm8 8098 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8099 op &= UINT64_C(255); 8100 Value |= op; 8101 break; 8102 } 8103 case Mips::Mfhi16: 8104 case Mips::Mflo16: { 8105 // op: rx 8106 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8107 op &= UINT64_C(7); 8108 op <<= 8; 8109 Value |= op; 8110 // op: ry 8111 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8112 op &= UINT64_C(7); 8113 op <<= 5; 8114 Value |= op; 8115 break; 8116 } 8117 case Mips::CmpRxRy16: 8118 case Mips::DivRxRy16: 8119 case Mips::DivuRxRy16: 8120 case Mips::NegRxRy16: 8121 case Mips::NotRxRy16: 8122 case Mips::SltRxRy16: 8123 case Mips::SltuRxRy16: { 8124 // op: rx 8125 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8126 op &= UINT64_C(7); 8127 op <<= 8; 8128 Value |= op; 8129 // op: ry 8130 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8131 op &= UINT64_C(7); 8132 op <<= 5; 8133 Value |= op; 8134 break; 8135 } 8136 case Mips::AndRxRxRy16: 8137 case Mips::OrRxRxRy16: 8138 case Mips::SllvRxRy16: 8139 case Mips::SravRxRy16: 8140 case Mips::SrlvRxRy16: 8141 case Mips::XorRxRxRy16: { 8142 // op: rx 8143 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8144 op &= UINT64_C(7); 8145 op <<= 8; 8146 Value |= op; 8147 // op: ry 8148 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8149 op &= UINT64_C(7); 8150 op <<= 5; 8151 Value |= op; 8152 break; 8153 } 8154 case Mips::AdduRxRyRz16: 8155 case Mips::SubuRxRyRz16: { 8156 // op: rx 8157 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8158 op &= UINT64_C(7); 8159 op <<= 8; 8160 Value |= op; 8161 // op: ry 8162 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8163 op &= UINT64_C(7); 8164 op <<= 5; 8165 Value |= op; 8166 // op: rz 8167 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8168 op &= UINT64_C(7); 8169 op <<= 2; 8170 Value |= op; 8171 break; 8172 } 8173 case Mips::MoveR3216: { 8174 // op: ry 8175 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8176 op &= UINT64_C(15); 8177 op <<= 4; 8178 Value |= op; 8179 // op: r32 8180 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8181 op &= UINT64_C(15); 8182 Value |= op; 8183 break; 8184 } 8185 case Mips::LDI_B: 8186 case Mips::LDI_D: 8187 case Mips::LDI_H: 8188 case Mips::LDI_W: { 8189 // op: s10 8190 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8191 op &= UINT64_C(1023); 8192 op <<= 11; 8193 Value |= op; 8194 // op: wd 8195 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8196 op &= UINT64_C(31); 8197 op <<= 6; 8198 Value |= op; 8199 break; 8200 } 8201 case Mips::SllX16: 8202 case Mips::SraX16: 8203 case Mips::SrlX16: { 8204 // op: sa6 8205 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8206 Value |= (op & UINT64_C(31)) << 22; 8207 Value |= (op & UINT64_C(32)) << 16; 8208 // op: rx 8209 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8210 op &= UINT64_C(7); 8211 op <<= 8; 8212 Value |= op; 8213 // op: ry 8214 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8215 op &= UINT64_C(7); 8216 op <<= 5; 8217 Value |= op; 8218 break; 8219 } 8220 case Mips::SHILO_MM: { 8221 // op: shift 8222 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8223 op &= UINT64_C(63); 8224 op <<= 16; 8225 Value |= op; 8226 // op: ac 8227 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8228 op &= UINT64_C(3); 8229 op <<= 14; 8230 Value |= op; 8231 break; 8232 } 8233 case Mips::SYNC_MM: 8234 case Mips::SYNC_MMR6: { 8235 // op: stype 8236 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8237 op &= UINT64_C(31); 8238 op <<= 16; 8239 Value |= op; 8240 break; 8241 } 8242 case Mips::SYNC: { 8243 // op: stype 8244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8245 op &= UINT64_C(31); 8246 op <<= 6; 8247 Value |= op; 8248 break; 8249 } 8250 case Mips::J: 8251 case Mips::JAL: 8252 case Mips::JALX: 8253 case Mips::JALX_MM: { 8254 // op: target 8255 op = getJumpTargetOpValue(MI, 0, Fixups, STI); 8256 op &= UINT64_C(67108863); 8257 Value |= op; 8258 break; 8259 } 8260 case Mips::JALS_MM: 8261 case Mips::JAL_MM: 8262 case Mips::J_MM: { 8263 // op: target 8264 op = getJumpTargetOpValueMM(MI, 0, Fixups, STI); 8265 op &= UINT64_C(67108863); 8266 Value |= op; 8267 break; 8268 } 8269 case Mips::ANDI_B: 8270 case Mips::NORI_B: 8271 case Mips::ORI_B: 8272 case Mips::SHF_B: 8273 case Mips::SHF_H: 8274 case Mips::SHF_W: 8275 case Mips::XORI_B: { 8276 // op: u8 8277 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8278 op &= UINT64_C(255); 8279 op <<= 16; 8280 Value |= op; 8281 // op: ws 8282 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8283 op &= UINT64_C(31); 8284 op <<= 11; 8285 Value |= op; 8286 // op: wd 8287 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8288 op &= UINT64_C(31); 8289 op <<= 6; 8290 Value |= op; 8291 break; 8292 } 8293 case Mips::BMNZI_B: 8294 case Mips::BMZI_B: 8295 case Mips::BSELI_B: { 8296 // op: u8 8297 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8298 op &= UINT64_C(255); 8299 op <<= 16; 8300 Value |= op; 8301 // op: ws 8302 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8303 op &= UINT64_C(31); 8304 op <<= 11; 8305 Value |= op; 8306 // op: wd 8307 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8308 op &= UINT64_C(31); 8309 op <<= 6; 8310 Value |= op; 8311 break; 8312 } 8313 case Mips::FCLASS_D: 8314 case Mips::FCLASS_W: 8315 case Mips::FEXUPL_D: 8316 case Mips::FEXUPL_W: 8317 case Mips::FEXUPR_D: 8318 case Mips::FEXUPR_W: 8319 case Mips::FFINT_S_D: 8320 case Mips::FFINT_S_W: 8321 case Mips::FFINT_U_D: 8322 case Mips::FFINT_U_W: 8323 case Mips::FFQL_D: 8324 case Mips::FFQL_W: 8325 case Mips::FFQR_D: 8326 case Mips::FFQR_W: 8327 case Mips::FLOG2_D: 8328 case Mips::FLOG2_W: 8329 case Mips::FRCP_D: 8330 case Mips::FRCP_W: 8331 case Mips::FRINT_D: 8332 case Mips::FRINT_W: 8333 case Mips::FRSQRT_D: 8334 case Mips::FRSQRT_W: 8335 case Mips::FSQRT_D: 8336 case Mips::FSQRT_W: 8337 case Mips::FTINT_S_D: 8338 case Mips::FTINT_S_W: 8339 case Mips::FTINT_U_D: 8340 case Mips::FTINT_U_W: 8341 case Mips::FTRUNC_S_D: 8342 case Mips::FTRUNC_S_W: 8343 case Mips::FTRUNC_U_D: 8344 case Mips::FTRUNC_U_W: 8345 case Mips::MOVE_V: 8346 case Mips::NLOC_B: 8347 case Mips::NLOC_D: 8348 case Mips::NLOC_H: 8349 case Mips::NLOC_W: 8350 case Mips::NLZC_B: 8351 case Mips::NLZC_D: 8352 case Mips::NLZC_H: 8353 case Mips::NLZC_W: 8354 case Mips::PCNT_B: 8355 case Mips::PCNT_D: 8356 case Mips::PCNT_H: 8357 case Mips::PCNT_W: { 8358 // op: ws 8359 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8360 op &= UINT64_C(31); 8361 op <<= 11; 8362 Value |= op; 8363 // op: wd 8364 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8365 op &= UINT64_C(31); 8366 op <<= 6; 8367 Value |= op; 8368 break; 8369 } 8370 case Mips::BCLRI_H: 8371 case Mips::BNEGI_H: 8372 case Mips::BSETI_H: 8373 case Mips::SAT_S_H: 8374 case Mips::SAT_U_H: 8375 case Mips::SLLI_H: 8376 case Mips::SRAI_H: 8377 case Mips::SRARI_H: 8378 case Mips::SRLI_H: 8379 case Mips::SRLRI_H: { 8380 // op: ws 8381 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8382 op &= UINT64_C(31); 8383 op <<= 11; 8384 Value |= op; 8385 // op: wd 8386 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8387 op &= UINT64_C(31); 8388 op <<= 6; 8389 Value |= op; 8390 // op: m 8391 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8392 op &= UINT64_C(15); 8393 op <<= 16; 8394 Value |= op; 8395 break; 8396 } 8397 case Mips::BCLRI_W: 8398 case Mips::BNEGI_W: 8399 case Mips::BSETI_W: 8400 case Mips::SAT_S_W: 8401 case Mips::SAT_U_W: 8402 case Mips::SLLI_W: 8403 case Mips::SRAI_W: 8404 case Mips::SRARI_W: 8405 case Mips::SRLI_W: 8406 case Mips::SRLRI_W: { 8407 // op: ws 8408 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8409 op &= UINT64_C(31); 8410 op <<= 11; 8411 Value |= op; 8412 // op: wd 8413 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8414 op &= UINT64_C(31); 8415 op <<= 6; 8416 Value |= op; 8417 // op: m 8418 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8419 op &= UINT64_C(31); 8420 op <<= 16; 8421 Value |= op; 8422 break; 8423 } 8424 case Mips::BCLRI_D: 8425 case Mips::BNEGI_D: 8426 case Mips::BSETI_D: 8427 case Mips::SAT_S_D: 8428 case Mips::SAT_U_D: 8429 case Mips::SLLI_D: 8430 case Mips::SRAI_D: 8431 case Mips::SRARI_D: 8432 case Mips::SRLI_D: 8433 case Mips::SRLRI_D: { 8434 // op: ws 8435 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8436 op &= UINT64_C(31); 8437 op <<= 11; 8438 Value |= op; 8439 // op: wd 8440 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8441 op &= UINT64_C(31); 8442 op <<= 6; 8443 Value |= op; 8444 // op: m 8445 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8446 op &= UINT64_C(63); 8447 op <<= 16; 8448 Value |= op; 8449 break; 8450 } 8451 case Mips::BCLRI_B: 8452 case Mips::BNEGI_B: 8453 case Mips::BSETI_B: 8454 case Mips::SAT_S_B: 8455 case Mips::SAT_U_B: 8456 case Mips::SLLI_B: 8457 case Mips::SRAI_B: 8458 case Mips::SRARI_B: 8459 case Mips::SRLI_B: 8460 case Mips::SRLRI_B: { 8461 // op: ws 8462 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8463 op &= UINT64_C(31); 8464 op <<= 11; 8465 Value |= op; 8466 // op: wd 8467 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8468 op &= UINT64_C(31); 8469 op <<= 6; 8470 Value |= op; 8471 // op: m 8472 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8473 op &= UINT64_C(7); 8474 op <<= 16; 8475 Value |= op; 8476 break; 8477 } 8478 case Mips::BINSLI_H: 8479 case Mips::BINSRI_H: { 8480 // op: ws 8481 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8482 op &= UINT64_C(31); 8483 op <<= 11; 8484 Value |= op; 8485 // op: wd 8486 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8487 op &= UINT64_C(31); 8488 op <<= 6; 8489 Value |= op; 8490 // op: m 8491 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8492 op &= UINT64_C(15); 8493 op <<= 16; 8494 Value |= op; 8495 break; 8496 } 8497 case Mips::BINSLI_W: 8498 case Mips::BINSRI_W: { 8499 // op: ws 8500 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8501 op &= UINT64_C(31); 8502 op <<= 11; 8503 Value |= op; 8504 // op: wd 8505 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8506 op &= UINT64_C(31); 8507 op <<= 6; 8508 Value |= op; 8509 // op: m 8510 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8511 op &= UINT64_C(31); 8512 op <<= 16; 8513 Value |= op; 8514 break; 8515 } 8516 case Mips::BINSLI_D: 8517 case Mips::BINSRI_D: { 8518 // op: ws 8519 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8520 op &= UINT64_C(31); 8521 op <<= 11; 8522 Value |= op; 8523 // op: wd 8524 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8525 op &= UINT64_C(31); 8526 op <<= 6; 8527 Value |= op; 8528 // op: m 8529 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8530 op &= UINT64_C(63); 8531 op <<= 16; 8532 Value |= op; 8533 break; 8534 } 8535 case Mips::BINSLI_B: 8536 case Mips::BINSRI_B: { 8537 // op: ws 8538 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8539 op &= UINT64_C(31); 8540 op <<= 11; 8541 Value |= op; 8542 // op: wd 8543 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8544 op &= UINT64_C(31); 8545 op <<= 6; 8546 Value |= op; 8547 // op: m 8548 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8549 op &= UINT64_C(7); 8550 op <<= 16; 8551 Value |= op; 8552 break; 8553 } 8554 case Mips::ADDS_A_B: 8555 case Mips::ADDS_A_D: 8556 case Mips::ADDS_A_H: 8557 case Mips::ADDS_A_W: 8558 case Mips::ADDS_S_B: 8559 case Mips::ADDS_S_D: 8560 case Mips::ADDS_S_H: 8561 case Mips::ADDS_S_W: 8562 case Mips::ADDS_U_B: 8563 case Mips::ADDS_U_D: 8564 case Mips::ADDS_U_H: 8565 case Mips::ADDS_U_W: 8566 case Mips::ADDV_B: 8567 case Mips::ADDV_D: 8568 case Mips::ADDV_H: 8569 case Mips::ADDV_W: 8570 case Mips::ADD_A_B: 8571 case Mips::ADD_A_D: 8572 case Mips::ADD_A_H: 8573 case Mips::ADD_A_W: 8574 case Mips::AND_V: 8575 case Mips::ASUB_S_B: 8576 case Mips::ASUB_S_D: 8577 case Mips::ASUB_S_H: 8578 case Mips::ASUB_S_W: 8579 case Mips::ASUB_U_B: 8580 case Mips::ASUB_U_D: 8581 case Mips::ASUB_U_H: 8582 case Mips::ASUB_U_W: 8583 case Mips::AVER_S_B: 8584 case Mips::AVER_S_D: 8585 case Mips::AVER_S_H: 8586 case Mips::AVER_S_W: 8587 case Mips::AVER_U_B: 8588 case Mips::AVER_U_D: 8589 case Mips::AVER_U_H: 8590 case Mips::AVER_U_W: 8591 case Mips::AVE_S_B: 8592 case Mips::AVE_S_D: 8593 case Mips::AVE_S_H: 8594 case Mips::AVE_S_W: 8595 case Mips::AVE_U_B: 8596 case Mips::AVE_U_D: 8597 case Mips::AVE_U_H: 8598 case Mips::AVE_U_W: 8599 case Mips::BCLR_B: 8600 case Mips::BCLR_D: 8601 case Mips::BCLR_H: 8602 case Mips::BCLR_W: 8603 case Mips::BNEG_B: 8604 case Mips::BNEG_D: 8605 case Mips::BNEG_H: 8606 case Mips::BNEG_W: 8607 case Mips::BSET_B: 8608 case Mips::BSET_D: 8609 case Mips::BSET_H: 8610 case Mips::BSET_W: 8611 case Mips::CEQ_B: 8612 case Mips::CEQ_D: 8613 case Mips::CEQ_H: 8614 case Mips::CEQ_W: 8615 case Mips::CLE_S_B: 8616 case Mips::CLE_S_D: 8617 case Mips::CLE_S_H: 8618 case Mips::CLE_S_W: 8619 case Mips::CLE_U_B: 8620 case Mips::CLE_U_D: 8621 case Mips::CLE_U_H: 8622 case Mips::CLE_U_W: 8623 case Mips::CLT_S_B: 8624 case Mips::CLT_S_D: 8625 case Mips::CLT_S_H: 8626 case Mips::CLT_S_W: 8627 case Mips::CLT_U_B: 8628 case Mips::CLT_U_D: 8629 case Mips::CLT_U_H: 8630 case Mips::CLT_U_W: 8631 case Mips::DIV_S_B: 8632 case Mips::DIV_S_D: 8633 case Mips::DIV_S_H: 8634 case Mips::DIV_S_W: 8635 case Mips::DIV_U_B: 8636 case Mips::DIV_U_D: 8637 case Mips::DIV_U_H: 8638 case Mips::DIV_U_W: 8639 case Mips::DOTP_S_D: 8640 case Mips::DOTP_S_H: 8641 case Mips::DOTP_S_W: 8642 case Mips::DOTP_U_D: 8643 case Mips::DOTP_U_H: 8644 case Mips::DOTP_U_W: 8645 case Mips::FADD_D: 8646 case Mips::FADD_W: 8647 case Mips::FCAF_D: 8648 case Mips::FCAF_W: 8649 case Mips::FCEQ_D: 8650 case Mips::FCEQ_W: 8651 case Mips::FCLE_D: 8652 case Mips::FCLE_W: 8653 case Mips::FCLT_D: 8654 case Mips::FCLT_W: 8655 case Mips::FCNE_D: 8656 case Mips::FCNE_W: 8657 case Mips::FCOR_D: 8658 case Mips::FCOR_W: 8659 case Mips::FCUEQ_D: 8660 case Mips::FCUEQ_W: 8661 case Mips::FCULE_D: 8662 case Mips::FCULE_W: 8663 case Mips::FCULT_D: 8664 case Mips::FCULT_W: 8665 case Mips::FCUNE_D: 8666 case Mips::FCUNE_W: 8667 case Mips::FCUN_D: 8668 case Mips::FCUN_W: 8669 case Mips::FDIV_D: 8670 case Mips::FDIV_W: 8671 case Mips::FEXDO_H: 8672 case Mips::FEXDO_W: 8673 case Mips::FEXP2_D: 8674 case Mips::FEXP2_W: 8675 case Mips::FMAX_A_D: 8676 case Mips::FMAX_A_W: 8677 case Mips::FMAX_D: 8678 case Mips::FMAX_W: 8679 case Mips::FMIN_A_D: 8680 case Mips::FMIN_A_W: 8681 case Mips::FMIN_D: 8682 case Mips::FMIN_W: 8683 case Mips::FMUL_D: 8684 case Mips::FMUL_W: 8685 case Mips::FSAF_D: 8686 case Mips::FSAF_W: 8687 case Mips::FSEQ_D: 8688 case Mips::FSEQ_W: 8689 case Mips::FSLE_D: 8690 case Mips::FSLE_W: 8691 case Mips::FSLT_D: 8692 case Mips::FSLT_W: 8693 case Mips::FSNE_D: 8694 case Mips::FSNE_W: 8695 case Mips::FSOR_D: 8696 case Mips::FSOR_W: 8697 case Mips::FSUB_D: 8698 case Mips::FSUB_W: 8699 case Mips::FSUEQ_D: 8700 case Mips::FSUEQ_W: 8701 case Mips::FSULE_D: 8702 case Mips::FSULE_W: 8703 case Mips::FSULT_D: 8704 case Mips::FSULT_W: 8705 case Mips::FSUNE_D: 8706 case Mips::FSUNE_W: 8707 case Mips::FSUN_D: 8708 case Mips::FSUN_W: 8709 case Mips::FTQ_H: 8710 case Mips::FTQ_W: 8711 case Mips::HADD_S_D: 8712 case Mips::HADD_S_H: 8713 case Mips::HADD_S_W: 8714 case Mips::HADD_U_D: 8715 case Mips::HADD_U_H: 8716 case Mips::HADD_U_W: 8717 case Mips::HSUB_S_D: 8718 case Mips::HSUB_S_H: 8719 case Mips::HSUB_S_W: 8720 case Mips::HSUB_U_D: 8721 case Mips::HSUB_U_H: 8722 case Mips::HSUB_U_W: 8723 case Mips::ILVEV_B: 8724 case Mips::ILVEV_D: 8725 case Mips::ILVEV_H: 8726 case Mips::ILVEV_W: 8727 case Mips::ILVL_B: 8728 case Mips::ILVL_D: 8729 case Mips::ILVL_H: 8730 case Mips::ILVL_W: 8731 case Mips::ILVOD_B: 8732 case Mips::ILVOD_D: 8733 case Mips::ILVOD_H: 8734 case Mips::ILVOD_W: 8735 case Mips::ILVR_B: 8736 case Mips::ILVR_D: 8737 case Mips::ILVR_H: 8738 case Mips::ILVR_W: 8739 case Mips::MAX_A_B: 8740 case Mips::MAX_A_D: 8741 case Mips::MAX_A_H: 8742 case Mips::MAX_A_W: 8743 case Mips::MAX_S_B: 8744 case Mips::MAX_S_D: 8745 case Mips::MAX_S_H: 8746 case Mips::MAX_S_W: 8747 case Mips::MAX_U_B: 8748 case Mips::MAX_U_D: 8749 case Mips::MAX_U_H: 8750 case Mips::MAX_U_W: 8751 case Mips::MIN_A_B: 8752 case Mips::MIN_A_D: 8753 case Mips::MIN_A_H: 8754 case Mips::MIN_A_W: 8755 case Mips::MIN_S_B: 8756 case Mips::MIN_S_D: 8757 case Mips::MIN_S_H: 8758 case Mips::MIN_S_W: 8759 case Mips::MIN_U_B: 8760 case Mips::MIN_U_D: 8761 case Mips::MIN_U_H: 8762 case Mips::MIN_U_W: 8763 case Mips::MOD_S_B: 8764 case Mips::MOD_S_D: 8765 case Mips::MOD_S_H: 8766 case Mips::MOD_S_W: 8767 case Mips::MOD_U_B: 8768 case Mips::MOD_U_D: 8769 case Mips::MOD_U_H: 8770 case Mips::MOD_U_W: 8771 case Mips::MULR_Q_H: 8772 case Mips::MULR_Q_W: 8773 case Mips::MULV_B: 8774 case Mips::MULV_D: 8775 case Mips::MULV_H: 8776 case Mips::MULV_W: 8777 case Mips::MUL_Q_H: 8778 case Mips::MUL_Q_W: 8779 case Mips::NOR_V: 8780 case Mips::OR_V: 8781 case Mips::PCKEV_B: 8782 case Mips::PCKEV_D: 8783 case Mips::PCKEV_H: 8784 case Mips::PCKEV_W: 8785 case Mips::PCKOD_B: 8786 case Mips::PCKOD_D: 8787 case Mips::PCKOD_H: 8788 case Mips::PCKOD_W: 8789 case Mips::SLL_B: 8790 case Mips::SLL_D: 8791 case Mips::SLL_H: 8792 case Mips::SLL_W: 8793 case Mips::SRAR_B: 8794 case Mips::SRAR_D: 8795 case Mips::SRAR_H: 8796 case Mips::SRAR_W: 8797 case Mips::SRA_B: 8798 case Mips::SRA_D: 8799 case Mips::SRA_H: 8800 case Mips::SRA_W: 8801 case Mips::SRLR_B: 8802 case Mips::SRLR_D: 8803 case Mips::SRLR_H: 8804 case Mips::SRLR_W: 8805 case Mips::SRL_B: 8806 case Mips::SRL_D: 8807 case Mips::SRL_H: 8808 case Mips::SRL_W: 8809 case Mips::SUBSUS_U_B: 8810 case Mips::SUBSUS_U_D: 8811 case Mips::SUBSUS_U_H: 8812 case Mips::SUBSUS_U_W: 8813 case Mips::SUBSUU_S_B: 8814 case Mips::SUBSUU_S_D: 8815 case Mips::SUBSUU_S_H: 8816 case Mips::SUBSUU_S_W: 8817 case Mips::SUBS_S_B: 8818 case Mips::SUBS_S_D: 8819 case Mips::SUBS_S_H: 8820 case Mips::SUBS_S_W: 8821 case Mips::SUBS_U_B: 8822 case Mips::SUBS_U_D: 8823 case Mips::SUBS_U_H: 8824 case Mips::SUBS_U_W: 8825 case Mips::SUBV_B: 8826 case Mips::SUBV_D: 8827 case Mips::SUBV_H: 8828 case Mips::SUBV_W: 8829 case Mips::XOR_V: { 8830 // op: wt 8831 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8832 op &= UINT64_C(31); 8833 op <<= 16; 8834 Value |= op; 8835 // op: ws 8836 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8837 op &= UINT64_C(31); 8838 op <<= 11; 8839 Value |= op; 8840 // op: wd 8841 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8842 op &= UINT64_C(31); 8843 op <<= 6; 8844 Value |= op; 8845 break; 8846 } 8847 case Mips::BINSL_B: 8848 case Mips::BINSL_D: 8849 case Mips::BINSL_H: 8850 case Mips::BINSL_W: 8851 case Mips::BINSR_B: 8852 case Mips::BINSR_D: 8853 case Mips::BINSR_H: 8854 case Mips::BINSR_W: 8855 case Mips::BMNZ_V: 8856 case Mips::BMZ_V: 8857 case Mips::BSEL_V: 8858 case Mips::DPADD_S_D: 8859 case Mips::DPADD_S_H: 8860 case Mips::DPADD_S_W: 8861 case Mips::DPADD_U_D: 8862 case Mips::DPADD_U_H: 8863 case Mips::DPADD_U_W: 8864 case Mips::DPSUB_S_D: 8865 case Mips::DPSUB_S_H: 8866 case Mips::DPSUB_S_W: 8867 case Mips::DPSUB_U_D: 8868 case Mips::DPSUB_U_H: 8869 case Mips::DPSUB_U_W: 8870 case Mips::FMADD_D: 8871 case Mips::FMADD_W: 8872 case Mips::FMSUB_D: 8873 case Mips::FMSUB_W: 8874 case Mips::MADDR_Q_H: 8875 case Mips::MADDR_Q_W: 8876 case Mips::MADDV_B: 8877 case Mips::MADDV_D: 8878 case Mips::MADDV_H: 8879 case Mips::MADDV_W: 8880 case Mips::MADD_Q_H: 8881 case Mips::MADD_Q_W: 8882 case Mips::MSUBR_Q_H: 8883 case Mips::MSUBR_Q_W: 8884 case Mips::MSUBV_B: 8885 case Mips::MSUBV_D: 8886 case Mips::MSUBV_H: 8887 case Mips::MSUBV_W: 8888 case Mips::MSUB_Q_H: 8889 case Mips::MSUB_Q_W: 8890 case Mips::VSHF_B: 8891 case Mips::VSHF_D: 8892 case Mips::VSHF_H: 8893 case Mips::VSHF_W: { 8894 // op: wt 8895 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8896 op &= UINT64_C(31); 8897 op <<= 16; 8898 Value |= op; 8899 // op: ws 8900 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8901 op &= UINT64_C(31); 8902 op <<= 11; 8903 Value |= op; 8904 // op: wd 8905 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8906 op &= UINT64_C(31); 8907 op <<= 6; 8908 Value |= op; 8909 break; 8910 } 8911 default: 8912 std::string msg; 8913 raw_string_ostream Msg(msg); 8914 Msg << "Not supported instr: " << MI; 8915 report_fatal_error(Msg.str()); 8916 } 8917 return Value; 8918} 8919 8920#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 8921#undef ENABLE_INSTR_PREDICATE_VERIFIER 8922#include <sstream> 8923 8924// Bits for subtarget features that participate in instruction matching. 8925enum SubtargetFeatureBits : uint8_t { 8926 Feature_HasMips2Bit = 11, 8927 Feature_HasMips3_32Bit = 17, 8928 Feature_HasMips3_32r2Bit = 18, 8929 Feature_HasMips3Bit = 12, 8930 Feature_NotMips3Bit = 46, 8931 Feature_HasMips4_32Bit = 19, 8932 Feature_NotMips4_32Bit = 48, 8933 Feature_HasMips4_32r2Bit = 20, 8934 Feature_HasMips5_32r2Bit = 21, 8935 Feature_HasMips32Bit = 13, 8936 Feature_HasMips32r2Bit = 14, 8937 Feature_HasMips32r5Bit = 15, 8938 Feature_HasMips32r6Bit = 16, 8939 Feature_NotMips32r6Bit = 47, 8940 Feature_IsGP64bitBit = 32, 8941 Feature_IsGP32bitBit = 31, 8942 Feature_IsPTR64bitBit = 36, 8943 Feature_IsPTR32bitBit = 35, 8944 Feature_HasMips64Bit = 22, 8945 Feature_NotMips64Bit = 49, 8946 Feature_HasMips64r2Bit = 23, 8947 Feature_HasMips64r5Bit = 24, 8948 Feature_HasMips64r6Bit = 25, 8949 Feature_NotMips64r6Bit = 50, 8950 Feature_InMips16ModeBit = 29, 8951 Feature_NotInMips16ModeBit = 45, 8952 Feature_HasCnMipsBit = 1, 8953 Feature_NotCnMipsBit = 41, 8954 Feature_HasCnMipsPBit = 2, 8955 Feature_NotCnMipsPBit = 42, 8956 Feature_IsSym32Bit = 38, 8957 Feature_IsSym64Bit = 39, 8958 Feature_HasStdEncBit = 26, 8959 Feature_InMicroMipsBit = 28, 8960 Feature_NotInMicroMipsBit = 44, 8961 Feature_HasEVABit = 6, 8962 Feature_HasMSABit = 8, 8963 Feature_HasMadd4Bit = 10, 8964 Feature_HasMTBit = 9, 8965 Feature_UseIndirectJumpsHazardBit = 51, 8966 Feature_NoIndirectJumpGuardsBit = 40, 8967 Feature_HasCRCBit = 0, 8968 Feature_HasVirtBit = 27, 8969 Feature_HasGINVBit = 7, 8970 Feature_IsFP64bitBit = 30, 8971 Feature_NotFP64bitBit = 43, 8972 Feature_IsSingleFloatBit = 37, 8973 Feature_IsNotSingleFloatBit = 33, 8974 Feature_IsNotSoftFloatBit = 34, 8975 Feature_HasDSPBit = 3, 8976 Feature_HasDSPR2Bit = 4, 8977 Feature_HasDSPR3Bit = 5, 8978}; 8979 8980#ifndef NDEBUG 8981static const char *SubtargetFeatureNames[] = { 8982 "Feature_HasCRC", 8983 "Feature_HasCnMips", 8984 "Feature_HasCnMipsP", 8985 "Feature_HasDSP", 8986 "Feature_HasDSPR2", 8987 "Feature_HasDSPR3", 8988 "Feature_HasEVA", 8989 "Feature_HasGINV", 8990 "Feature_HasMSA", 8991 "Feature_HasMT", 8992 "Feature_HasMadd4", 8993 "Feature_HasMips2", 8994 "Feature_HasMips3", 8995 "Feature_HasMips32", 8996 "Feature_HasMips32r2", 8997 "Feature_HasMips32r5", 8998 "Feature_HasMips32r6", 8999 "Feature_HasMips3_32", 9000 "Feature_HasMips3_32r2", 9001 "Feature_HasMips4_32", 9002 "Feature_HasMips4_32r2", 9003 "Feature_HasMips5_32r2", 9004 "Feature_HasMips64", 9005 "Feature_HasMips64r2", 9006 "Feature_HasMips64r5", 9007 "Feature_HasMips64r6", 9008 "Feature_HasStdEnc", 9009 "Feature_HasVirt", 9010 "Feature_InMicroMips", 9011 "Feature_InMips16Mode", 9012 "Feature_IsFP64bit", 9013 "Feature_IsGP32bit", 9014 "Feature_IsGP64bit", 9015 "Feature_IsNotSingleFloat", 9016 "Feature_IsNotSoftFloat", 9017 "Feature_IsPTR32bit", 9018 "Feature_IsPTR64bit", 9019 "Feature_IsSingleFloat", 9020 "Feature_IsSym32", 9021 "Feature_IsSym64", 9022 "Feature_NoIndirectJumpGuards", 9023 "Feature_NotCnMips", 9024 "Feature_NotCnMipsP", 9025 "Feature_NotFP64bit", 9026 "Feature_NotInMicroMips", 9027 "Feature_NotInMips16Mode", 9028 "Feature_NotMips3", 9029 "Feature_NotMips32r6", 9030 "Feature_NotMips4_32", 9031 "Feature_NotMips64", 9032 "Feature_NotMips64r6", 9033 "Feature_UseIndirectJumpsHazard", 9034 nullptr 9035}; 9036 9037#endif // NDEBUG 9038FeatureBitset MipsMCCodeEmitter:: 9039computeAvailableFeatures(const FeatureBitset& FB) const { 9040 FeatureBitset Features; 9041 if ((FB[Mips::FeatureMips2])) 9042 Features.set(Feature_HasMips2Bit); 9043 if ((FB[Mips::FeatureMips3_32])) 9044 Features.set(Feature_HasMips3_32Bit); 9045 if ((FB[Mips::FeatureMips3_32r2])) 9046 Features.set(Feature_HasMips3_32r2Bit); 9047 if ((FB[Mips::FeatureMips3])) 9048 Features.set(Feature_HasMips3Bit); 9049 if ((!FB[Mips::FeatureMips3])) 9050 Features.set(Feature_NotMips3Bit); 9051 if ((FB[Mips::FeatureMips4_32])) 9052 Features.set(Feature_HasMips4_32Bit); 9053 if ((!FB[Mips::FeatureMips4_32])) 9054 Features.set(Feature_NotMips4_32Bit); 9055 if ((FB[Mips::FeatureMips4_32r2])) 9056 Features.set(Feature_HasMips4_32r2Bit); 9057 if ((FB[Mips::FeatureMips5_32r2])) 9058 Features.set(Feature_HasMips5_32r2Bit); 9059 if ((FB[Mips::FeatureMips32])) 9060 Features.set(Feature_HasMips32Bit); 9061 if ((FB[Mips::FeatureMips32r2])) 9062 Features.set(Feature_HasMips32r2Bit); 9063 if ((FB[Mips::FeatureMips32r5])) 9064 Features.set(Feature_HasMips32r5Bit); 9065 if ((FB[Mips::FeatureMips32r6])) 9066 Features.set(Feature_HasMips32r6Bit); 9067 if ((!FB[Mips::FeatureMips32r6])) 9068 Features.set(Feature_NotMips32r6Bit); 9069 if ((FB[Mips::FeatureGP64Bit])) 9070 Features.set(Feature_IsGP64bitBit); 9071 if ((!FB[Mips::FeatureGP64Bit])) 9072 Features.set(Feature_IsGP32bitBit); 9073 if ((FB[Mips::FeaturePTR64Bit])) 9074 Features.set(Feature_IsPTR64bitBit); 9075 if ((!FB[Mips::FeaturePTR64Bit])) 9076 Features.set(Feature_IsPTR32bitBit); 9077 if ((FB[Mips::FeatureMips64])) 9078 Features.set(Feature_HasMips64Bit); 9079 if ((!FB[Mips::FeatureMips64])) 9080 Features.set(Feature_NotMips64Bit); 9081 if ((FB[Mips::FeatureMips64r2])) 9082 Features.set(Feature_HasMips64r2Bit); 9083 if ((FB[Mips::FeatureMips64r5])) 9084 Features.set(Feature_HasMips64r5Bit); 9085 if ((FB[Mips::FeatureMips64r6])) 9086 Features.set(Feature_HasMips64r6Bit); 9087 if ((!FB[Mips::FeatureMips64r6])) 9088 Features.set(Feature_NotMips64r6Bit); 9089 if ((FB[Mips::FeatureMips16])) 9090 Features.set(Feature_InMips16ModeBit); 9091 if ((!FB[Mips::FeatureMips16])) 9092 Features.set(Feature_NotInMips16ModeBit); 9093 if ((FB[Mips::FeatureCnMips])) 9094 Features.set(Feature_HasCnMipsBit); 9095 if ((!FB[Mips::FeatureCnMips])) 9096 Features.set(Feature_NotCnMipsBit); 9097 if ((FB[Mips::FeatureCnMipsP])) 9098 Features.set(Feature_HasCnMipsPBit); 9099 if ((!FB[Mips::FeatureCnMipsP])) 9100 Features.set(Feature_NotCnMipsPBit); 9101 if ((FB[Mips::FeatureSym32])) 9102 Features.set(Feature_IsSym32Bit); 9103 if ((!FB[Mips::FeatureSym32])) 9104 Features.set(Feature_IsSym64Bit); 9105 if ((!FB[Mips::FeatureMips16])) 9106 Features.set(Feature_HasStdEncBit); 9107 if ((FB[Mips::FeatureMicroMips])) 9108 Features.set(Feature_InMicroMipsBit); 9109 if ((!FB[Mips::FeatureMicroMips])) 9110 Features.set(Feature_NotInMicroMipsBit); 9111 if ((FB[Mips::FeatureEVA])) 9112 Features.set(Feature_HasEVABit); 9113 if ((FB[Mips::FeatureMSA])) 9114 Features.set(Feature_HasMSABit); 9115 if ((!FB[Mips::FeatureMadd4])) 9116 Features.set(Feature_HasMadd4Bit); 9117 if ((FB[Mips::FeatureMT])) 9118 Features.set(Feature_HasMTBit); 9119 if ((FB[Mips::FeatureUseIndirectJumpsHazard])) 9120 Features.set(Feature_UseIndirectJumpsHazardBit); 9121 if ((!FB[Mips::FeatureUseIndirectJumpsHazard])) 9122 Features.set(Feature_NoIndirectJumpGuardsBit); 9123 if ((FB[Mips::FeatureCRC])) 9124 Features.set(Feature_HasCRCBit); 9125 if ((FB[Mips::FeatureVirt])) 9126 Features.set(Feature_HasVirtBit); 9127 if ((FB[Mips::FeatureGINV])) 9128 Features.set(Feature_HasGINVBit); 9129 if ((FB[Mips::FeatureFP64Bit])) 9130 Features.set(Feature_IsFP64bitBit); 9131 if ((!FB[Mips::FeatureFP64Bit])) 9132 Features.set(Feature_NotFP64bitBit); 9133 if ((FB[Mips::FeatureSingleFloat])) 9134 Features.set(Feature_IsSingleFloatBit); 9135 if ((!FB[Mips::FeatureSingleFloat])) 9136 Features.set(Feature_IsNotSingleFloatBit); 9137 if ((!FB[Mips::FeatureSoftFloat])) 9138 Features.set(Feature_IsNotSoftFloatBit); 9139 if ((FB[Mips::FeatureDSP])) 9140 Features.set(Feature_HasDSPBit); 9141 if ((FB[Mips::FeatureDSPR2])) 9142 Features.set(Feature_HasDSPR2Bit); 9143 if ((FB[Mips::FeatureDSPR3])) 9144 Features.set(Feature_HasDSPR3Bit); 9145 return Features; 9146} 9147 9148#ifndef NDEBUG 9149// Feature bitsets. 9150enum : uint8_t { 9151 CEFBS_None, 9152 CEFBS_HasCnMips, 9153 CEFBS_HasCnMipsP, 9154 CEFBS_HasDSP, 9155 CEFBS_HasDSPR2, 9156 CEFBS_HasMSA, 9157 CEFBS_HasMT, 9158 CEFBS_InMicroMips, 9159 CEFBS_InMips16Mode, 9160 CEFBS_IsGP32bit, 9161 CEFBS_IsGP64bit, 9162 CEFBS_IsNotSoftFloat, 9163 CEFBS_NotCnMips, 9164 CEFBS_NotInMips16Mode, 9165 CEFBS_HasDSP_NotInMicroMips, 9166 CEFBS_HasStdEnc_HasMSA, 9167 CEFBS_HasStdEnc_HasMips32, 9168 CEFBS_HasStdEnc_HasMips32r6, 9169 CEFBS_HasStdEnc_HasMips64, 9170 CEFBS_HasStdEnc_HasMips64r6, 9171 CEFBS_HasStdEnc_IsNotSoftFloat, 9172 CEFBS_HasStdEnc_NotInMicroMips, 9173 CEFBS_HasStdEnc_NotMips3, 9174 CEFBS_HasStdEnc_NotMips4_32, 9175 CEFBS_InMicroMips_HasDSP, 9176 CEFBS_InMicroMips_HasDSPR2, 9177 CEFBS_InMicroMips_HasDSPR3, 9178 CEFBS_InMicroMips_HasEVA, 9179 CEFBS_InMicroMips_HasMips32r6, 9180 CEFBS_InMicroMips_IsNotSoftFloat, 9181 CEFBS_InMicroMips_NotMips32r6, 9182 CEFBS_IsFP64bit_IsNotSoftFloat, 9183 CEFBS_IsGP32bit_NotInMicroMips, 9184 CEFBS_NotFP64bit_IsNotSoftFloat, 9185 CEFBS_NotInMips16Mode_HasDSP, 9186 CEFBS_NotInMips16Mode_IsGP64bit, 9187 CEFBS_NotInMips16Mode_IsNotSoftFloat, 9188 CEFBS_NotInMips16Mode_IsPTR64bit, 9189 CEFBS_HasMips3_NotMips64r6_NotCnMips, 9190 CEFBS_HasMips64_HasCnMips_NotInMicroMips, 9191 CEFBS_HasStdEnc_HasMSA_HasMips64, 9192 CEFBS_HasStdEnc_HasMT_NotInMicroMips, 9193 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, 9194 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, 9195 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, 9196 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, 9197 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, 9198 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, 9199 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, 9200 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, 9201 CEFBS_HasStdEnc_HasMips64r5_HasVirt, 9202 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, 9203 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, 9204 CEFBS_HasStdEnc_IsGP64bit_HasMips3, 9205 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, 9206 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, 9207 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, 9208 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, 9209 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, 9210 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, 9211 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, 9212 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, 9213 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, 9214 CEFBS_InMicroMips_HasMips32r5_HasVirt, 9215 CEFBS_InMicroMips_HasMips32r6_HasGINV, 9216 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, 9217 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, 9218 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, 9219 CEFBS_InMicroMips_NotMips32r6_HasDSP, 9220 CEFBS_InMicroMips_NotMips32r6_HasEVA, 9221 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, 9222 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, 9223 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, 9224 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, 9225 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, 9226 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, 9227 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, 9228 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, 9229 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9230 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, 9231 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, 9232 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, 9233 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, 9234 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, 9235 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, 9236 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, 9237 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, 9238 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, 9239 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, 9240 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, 9241 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, 9242 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 9243 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 9244 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, 9245 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, 9246 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, 9247 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, 9248 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, 9249 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, 9250 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, 9251 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, 9252 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, 9253 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, 9254 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, 9255 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, 9256 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 9257 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, 9258 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, 9259 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 9260 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9261 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, 9262 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, 9263 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 9264 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 9265 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9266 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 9267 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 9268 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, 9269 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, 9270 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 9271 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, 9272 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, 9273 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, 9274 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, 9275 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, 9276 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9277 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, 9278 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, 9279 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9280 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, 9281 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9282 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, 9283 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9284 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, 9285 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 9286 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, 9287 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9288 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 9289 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 9290 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9291 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9292 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 9293 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 9294 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9295 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9296 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9297 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9298 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9299 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9300 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9301 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 9302 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 9303 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, 9304 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, 9305 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, 9306 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, 9307 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, 9308}; 9309 9310static constexpr FeatureBitset FeatureBitsets[] = { 9311 {}, // CEFBS_None 9312 {Feature_HasCnMipsBit, }, 9313 {Feature_HasCnMipsPBit, }, 9314 {Feature_HasDSPBit, }, 9315 {Feature_HasDSPR2Bit, }, 9316 {Feature_HasMSABit, }, 9317 {Feature_HasMTBit, }, 9318 {Feature_InMicroMipsBit, }, 9319 {Feature_InMips16ModeBit, }, 9320 {Feature_IsGP32bitBit, }, 9321 {Feature_IsGP64bitBit, }, 9322 {Feature_IsNotSoftFloatBit, }, 9323 {Feature_NotCnMipsBit, }, 9324 {Feature_NotInMips16ModeBit, }, 9325 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, 9326 {Feature_HasStdEncBit, Feature_HasMSABit, }, 9327 {Feature_HasStdEncBit, Feature_HasMips32Bit, }, 9328 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, 9329 {Feature_HasStdEncBit, Feature_HasMips64Bit, }, 9330 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, 9331 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, 9332 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, 9333 {Feature_HasStdEncBit, Feature_NotMips3Bit, }, 9334 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, 9335 {Feature_InMicroMipsBit, Feature_HasDSPBit, }, 9336 {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, 9337 {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, 9338 {Feature_InMicroMipsBit, Feature_HasEVABit, }, 9339 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, 9340 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, 9341 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, 9342 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 9343 {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, 9344 {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 9345 {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, 9346 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, 9347 {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, 9348 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, 9349 {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, 9350 {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, 9351 {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, 9352 {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, 9353 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, 9354 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, 9355 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, 9356 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, 9357 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, 9358 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 9359 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, 9360 {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, 9361 {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, 9362 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 9363 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, 9364 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, 9365 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, 9366 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, 9367 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, 9368 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9369 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 9370 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, 9371 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9372 {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, 9373 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9374 {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, 9375 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, 9376 {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 9377 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 9378 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 9379 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, 9380 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, 9381 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 9382 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9383 {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, 9384 {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, 9385 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, 9386 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, 9387 {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, 9388 {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, 9389 {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9390 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9391 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 9392 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9393 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9394 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9395 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9396 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 9397 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, 9398 {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, 9399 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 9400 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, 9401 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9402 {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9403 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9404 {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9405 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, 9406 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9407 {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 9408 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, 9409 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, 9410 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9411 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9412 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, 9413 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 9414 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, 9415 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 9416 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9417 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9418 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9419 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9420 {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9421 {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9422 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9423 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 9424 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9425 {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9426 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9427 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9428 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9429 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9430 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9431 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 9432 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9433 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9434 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9435 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9436 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9437 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, 9438 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, 9439 {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9440 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, 9441 {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9442 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, 9443 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9444 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9445 {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9446 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, 9447 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9448 {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9449 {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9450 {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9451 {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9452 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 9453 {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 9454 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9455 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9456 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9457 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9458 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9459 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9460 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9461 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 9462 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 9463 {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, 9464 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, 9465 {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, 9466 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, 9467 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, 9468}; 9469#endif // NDEBUG 9470 9471void MipsMCCodeEmitter::verifyInstructionPredicates( 9472 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { 9473#ifndef NDEBUG 9474 static uint8_t RequiredFeaturesRefs[] = { 9475 CEFBS_None, // PHI = 0 9476 CEFBS_None, // INLINEASM = 1 9477 CEFBS_None, // INLINEASM_BR = 2 9478 CEFBS_None, // CFI_INSTRUCTION = 3 9479 CEFBS_None, // EH_LABEL = 4 9480 CEFBS_None, // GC_LABEL = 5 9481 CEFBS_None, // ANNOTATION_LABEL = 6 9482 CEFBS_None, // KILL = 7 9483 CEFBS_None, // EXTRACT_SUBREG = 8 9484 CEFBS_None, // INSERT_SUBREG = 9 9485 CEFBS_None, // IMPLICIT_DEF = 10 9486 CEFBS_None, // SUBREG_TO_REG = 11 9487 CEFBS_None, // COPY_TO_REGCLASS = 12 9488 CEFBS_None, // DBG_VALUE = 13 9489 CEFBS_None, // DBG_LABEL = 14 9490 CEFBS_None, // REG_SEQUENCE = 15 9491 CEFBS_None, // COPY = 16 9492 CEFBS_None, // BUNDLE = 17 9493 CEFBS_None, // LIFETIME_START = 18 9494 CEFBS_None, // LIFETIME_END = 19 9495 CEFBS_None, // STACKMAP = 20 9496 CEFBS_None, // FENTRY_CALL = 21 9497 CEFBS_None, // PATCHPOINT = 22 9498 CEFBS_None, // LOAD_STACK_GUARD = 23 9499 CEFBS_None, // STATEPOINT = 24 9500 CEFBS_None, // LOCAL_ESCAPE = 25 9501 CEFBS_None, // FAULTING_OP = 26 9502 CEFBS_None, // PATCHABLE_OP = 27 9503 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28 9504 CEFBS_None, // PATCHABLE_RET = 29 9505 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30 9506 CEFBS_None, // PATCHABLE_TAIL_CALL = 31 9507 CEFBS_None, // PATCHABLE_EVENT_CALL = 32 9508 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33 9509 CEFBS_None, // ICALL_BRANCH_FUNNEL = 34 9510 CEFBS_None, // G_ADD = 35 9511 CEFBS_None, // G_SUB = 36 9512 CEFBS_None, // G_MUL = 37 9513 CEFBS_None, // G_SDIV = 38 9514 CEFBS_None, // G_UDIV = 39 9515 CEFBS_None, // G_SREM = 40 9516 CEFBS_None, // G_UREM = 41 9517 CEFBS_None, // G_AND = 42 9518 CEFBS_None, // G_OR = 43 9519 CEFBS_None, // G_XOR = 44 9520 CEFBS_None, // G_IMPLICIT_DEF = 45 9521 CEFBS_None, // G_PHI = 46 9522 CEFBS_None, // G_FRAME_INDEX = 47 9523 CEFBS_None, // G_GLOBAL_VALUE = 48 9524 CEFBS_None, // G_EXTRACT = 49 9525 CEFBS_None, // G_UNMERGE_VALUES = 50 9526 CEFBS_None, // G_INSERT = 51 9527 CEFBS_None, // G_MERGE_VALUES = 52 9528 CEFBS_None, // G_BUILD_VECTOR = 53 9529 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54 9530 CEFBS_None, // G_CONCAT_VECTORS = 55 9531 CEFBS_None, // G_PTRTOINT = 56 9532 CEFBS_None, // G_INTTOPTR = 57 9533 CEFBS_None, // G_BITCAST = 58 9534 CEFBS_None, // G_INTRINSIC_TRUNC = 59 9535 CEFBS_None, // G_INTRINSIC_ROUND = 60 9536 CEFBS_None, // G_READCYCLECOUNTER = 61 9537 CEFBS_None, // G_LOAD = 62 9538 CEFBS_None, // G_SEXTLOAD = 63 9539 CEFBS_None, // G_ZEXTLOAD = 64 9540 CEFBS_None, // G_INDEXED_LOAD = 65 9541 CEFBS_None, // G_INDEXED_SEXTLOAD = 66 9542 CEFBS_None, // G_INDEXED_ZEXTLOAD = 67 9543 CEFBS_None, // G_STORE = 68 9544 CEFBS_None, // G_INDEXED_STORE = 69 9545 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70 9546 CEFBS_None, // G_ATOMIC_CMPXCHG = 71 9547 CEFBS_None, // G_ATOMICRMW_XCHG = 72 9548 CEFBS_None, // G_ATOMICRMW_ADD = 73 9549 CEFBS_None, // G_ATOMICRMW_SUB = 74 9550 CEFBS_None, // G_ATOMICRMW_AND = 75 9551 CEFBS_None, // G_ATOMICRMW_NAND = 76 9552 CEFBS_None, // G_ATOMICRMW_OR = 77 9553 CEFBS_None, // G_ATOMICRMW_XOR = 78 9554 CEFBS_None, // G_ATOMICRMW_MAX = 79 9555 CEFBS_None, // G_ATOMICRMW_MIN = 80 9556 CEFBS_None, // G_ATOMICRMW_UMAX = 81 9557 CEFBS_None, // G_ATOMICRMW_UMIN = 82 9558 CEFBS_None, // G_ATOMICRMW_FADD = 83 9559 CEFBS_None, // G_ATOMICRMW_FSUB = 84 9560 CEFBS_None, // G_FENCE = 85 9561 CEFBS_None, // G_BRCOND = 86 9562 CEFBS_None, // G_BRINDIRECT = 87 9563 CEFBS_None, // G_INTRINSIC = 88 9564 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89 9565 CEFBS_None, // G_ANYEXT = 90 9566 CEFBS_None, // G_TRUNC = 91 9567 CEFBS_None, // G_CONSTANT = 92 9568 CEFBS_None, // G_FCONSTANT = 93 9569 CEFBS_None, // G_VASTART = 94 9570 CEFBS_None, // G_VAARG = 95 9571 CEFBS_None, // G_SEXT = 96 9572 CEFBS_None, // G_SEXT_INREG = 97 9573 CEFBS_None, // G_ZEXT = 98 9574 CEFBS_None, // G_SHL = 99 9575 CEFBS_None, // G_LSHR = 100 9576 CEFBS_None, // G_ASHR = 101 9577 CEFBS_None, // G_ICMP = 102 9578 CEFBS_None, // G_FCMP = 103 9579 CEFBS_None, // G_SELECT = 104 9580 CEFBS_None, // G_UADDO = 105 9581 CEFBS_None, // G_UADDE = 106 9582 CEFBS_None, // G_USUBO = 107 9583 CEFBS_None, // G_USUBE = 108 9584 CEFBS_None, // G_SADDO = 109 9585 CEFBS_None, // G_SADDE = 110 9586 CEFBS_None, // G_SSUBO = 111 9587 CEFBS_None, // G_SSUBE = 112 9588 CEFBS_None, // G_UMULO = 113 9589 CEFBS_None, // G_SMULO = 114 9590 CEFBS_None, // G_UMULH = 115 9591 CEFBS_None, // G_SMULH = 116 9592 CEFBS_None, // G_FADD = 117 9593 CEFBS_None, // G_FSUB = 118 9594 CEFBS_None, // G_FMUL = 119 9595 CEFBS_None, // G_FMA = 120 9596 CEFBS_None, // G_FMAD = 121 9597 CEFBS_None, // G_FDIV = 122 9598 CEFBS_None, // G_FREM = 123 9599 CEFBS_None, // G_FPOW = 124 9600 CEFBS_None, // G_FEXP = 125 9601 CEFBS_None, // G_FEXP2 = 126 9602 CEFBS_None, // G_FLOG = 127 9603 CEFBS_None, // G_FLOG2 = 128 9604 CEFBS_None, // G_FLOG10 = 129 9605 CEFBS_None, // G_FNEG = 130 9606 CEFBS_None, // G_FPEXT = 131 9607 CEFBS_None, // G_FPTRUNC = 132 9608 CEFBS_None, // G_FPTOSI = 133 9609 CEFBS_None, // G_FPTOUI = 134 9610 CEFBS_None, // G_SITOFP = 135 9611 CEFBS_None, // G_UITOFP = 136 9612 CEFBS_None, // G_FABS = 137 9613 CEFBS_None, // G_FCOPYSIGN = 138 9614 CEFBS_None, // G_FCANONICALIZE = 139 9615 CEFBS_None, // G_FMINNUM = 140 9616 CEFBS_None, // G_FMAXNUM = 141 9617 CEFBS_None, // G_FMINNUM_IEEE = 142 9618 CEFBS_None, // G_FMAXNUM_IEEE = 143 9619 CEFBS_None, // G_FMINIMUM = 144 9620 CEFBS_None, // G_FMAXIMUM = 145 9621 CEFBS_None, // G_PTR_ADD = 146 9622 CEFBS_None, // G_PTR_MASK = 147 9623 CEFBS_None, // G_SMIN = 148 9624 CEFBS_None, // G_SMAX = 149 9625 CEFBS_None, // G_UMIN = 150 9626 CEFBS_None, // G_UMAX = 151 9627 CEFBS_None, // G_BR = 152 9628 CEFBS_None, // G_BRJT = 153 9629 CEFBS_None, // G_INSERT_VECTOR_ELT = 154 9630 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155 9631 CEFBS_None, // G_SHUFFLE_VECTOR = 156 9632 CEFBS_None, // G_CTTZ = 157 9633 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158 9634 CEFBS_None, // G_CTLZ = 159 9635 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160 9636 CEFBS_None, // G_CTPOP = 161 9637 CEFBS_None, // G_BSWAP = 162 9638 CEFBS_None, // G_BITREVERSE = 163 9639 CEFBS_None, // G_FCEIL = 164 9640 CEFBS_None, // G_FCOS = 165 9641 CEFBS_None, // G_FSIN = 166 9642 CEFBS_None, // G_FSQRT = 167 9643 CEFBS_None, // G_FFLOOR = 168 9644 CEFBS_None, // G_FRINT = 169 9645 CEFBS_None, // G_FNEARBYINT = 170 9646 CEFBS_None, // G_ADDRSPACE_CAST = 171 9647 CEFBS_None, // G_BLOCK_ADDR = 172 9648 CEFBS_None, // G_JUMP_TABLE = 173 9649 CEFBS_None, // G_DYN_STACKALLOC = 174 9650 CEFBS_None, // G_READ_REGISTER = 175 9651 CEFBS_None, // G_WRITE_REGISTER = 176 9652 CEFBS_None, // ABSMacro = 177 9653 CEFBS_None, // ADJCALLSTACKDOWN = 178 9654 CEFBS_None, // ADJCALLSTACKUP = 179 9655 CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 180 9656 CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 181 9657 CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 182 9658 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 183 9659 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 184 9660 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 185 9661 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 186 9662 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 187 9663 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 188 9664 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 189 9665 CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 190 9666 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 191 9667 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 192 9668 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 193 9669 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 194 9670 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 195 9671 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 196 9672 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 197 9673 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 198 9674 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 199 9675 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 200 9676 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 201 9677 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 202 9678 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 203 9679 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 204 9680 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 205 9681 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 206 9682 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 207 9683 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 208 9684 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 209 9685 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 210 9686 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 211 9687 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 212 9688 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 213 9689 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 214 9690 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 215 9691 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 216 9692 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 217 9693 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 218 9694 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 219 9695 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 220 9696 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 221 9697 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 222 9698 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 223 9699 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 224 9700 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 225 9701 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 226 9702 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 227 9703 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 228 9704 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 229 9705 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 230 9706 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 231 9707 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 232 9708 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 233 9709 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 234 9710 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 235 9711 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 236 9712 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 237 9713 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 238 9714 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 239 9715 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 240 9716 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 241 9717 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 242 9718 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 243 9719 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 244 9720 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 245 9721 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 246 9722 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 247 9723 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 248 9724 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 249 9725 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 250 9726 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 251 9727 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 252 9728 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 253 9729 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 254 9730 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 255 9731 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 256 9732 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 257 9733 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 258 9734 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 259 9735 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 260 9736 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 261 9737 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 262 9738 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 263 9739 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 264 9740 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 265 9741 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 266 9742 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 267 9743 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 268 9744 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 269 9745 CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 270 9746 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 271 9747 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 272 9748 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 273 9749 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 274 9750 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 275 9751 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 276 9752 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 277 9753 CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 278 9754 CEFBS_HasStdEnc_NotInMicroMips, // B = 279 9755 CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 280 9756 CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 281 9757 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 282 9758 CEFBS_None, // BGE = 283 9759 CEFBS_None, // BGEImmMacro = 284 9760 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 285 9761 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 286 9762 CEFBS_None, // BGEU = 287 9763 CEFBS_None, // BGEUImmMacro = 288 9764 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 289 9765 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 290 9766 CEFBS_None, // BGT = 291 9767 CEFBS_None, // BGTImmMacro = 292 9768 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 293 9769 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 294 9770 CEFBS_None, // BGTU = 295 9771 CEFBS_None, // BGTUImmMacro = 296 9772 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 297 9773 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 298 9774 CEFBS_None, // BLE = 299 9775 CEFBS_None, // BLEImmMacro = 300 9776 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 301 9777 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 302 9778 CEFBS_None, // BLEU = 303 9779 CEFBS_None, // BLEUImmMacro = 304 9780 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 305 9781 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 306 9782 CEFBS_None, // BLT = 307 9783 CEFBS_None, // BLTImmMacro = 308 9784 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 309 9785 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 310 9786 CEFBS_None, // BLTU = 311 9787 CEFBS_None, // BLTUImmMacro = 312 9788 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 313 9789 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 314 9790 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 315 9791 CEFBS_None, // BPOSGE32_PSEUDO = 316 9792 CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 317 9793 CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 318 9794 CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 319 9795 CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 320 9796 CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 321 9797 CEFBS_InMicroMips_NotMips32r6, // B_MM = 322 9798 CEFBS_None, // B_MMR6_Pseudo = 323 9799 CEFBS_InMicroMips, // B_MM_Pseudo = 324 9800 CEFBS_None, // BeqImm = 325 9801 CEFBS_None, // BneImm = 326 9802 CEFBS_InMips16Mode, // BteqzT8CmpX16 = 327 9803 CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 328 9804 CEFBS_InMips16Mode, // BteqzT8SltX16 = 329 9805 CEFBS_InMips16Mode, // BteqzT8SltiX16 = 330 9806 CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 331 9807 CEFBS_InMips16Mode, // BteqzT8SltuX16 = 332 9808 CEFBS_InMips16Mode, // BtnezT8CmpX16 = 333 9809 CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 334 9810 CEFBS_InMips16Mode, // BtnezT8SltX16 = 335 9811 CEFBS_InMips16Mode, // BtnezT8SltiX16 = 336 9812 CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 337 9813 CEFBS_InMips16Mode, // BtnezT8SltuX16 = 338 9814 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 339 9815 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 340 9816 CEFBS_HasMT, // CFTC1 = 341 9817 CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 342 9818 CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 343 9819 CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 344 9820 CEFBS_HasMT, // CTTC1 = 345 9821 CEFBS_InMips16Mode, // Constant32 = 346 9822 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 347 9823 CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 348 9824 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 349 9825 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 350 9826 CEFBS_HasStdEnc_HasMips64, // DROL = 351 9827 CEFBS_HasStdEnc_HasMips64, // DROLImm = 352 9828 CEFBS_HasStdEnc_HasMips64, // DROR = 353 9829 CEFBS_HasStdEnc_HasMips64, // DRORImm = 354 9830 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 355 9831 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 356 9832 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 357 9833 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 358 9834 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 359 9835 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 360 9836 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 361 9837 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 362 9838 CEFBS_NotInMips16Mode, // ERet = 363 9839 CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 364 9840 CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 365 9841 CEFBS_HasStdEnc_HasMSA, // FABS_D = 366 9842 CEFBS_HasStdEnc_HasMSA, // FABS_W = 367 9843 CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 368 9844 CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 369 9845 CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 370 9846 CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 371 9847 CEFBS_InMips16Mode, // GotPrologue16 = 372 9848 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 373 9849 CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 374 9850 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 375 9851 CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 376 9852 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 377 9853 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 378 9854 CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 379 9855 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 380 9856 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 381 9857 CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 382 9858 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 383 9859 CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 384 9860 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 385 9861 CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 386 9862 CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 387 9863 CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 388 9864 CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 389 9865 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 390 9866 CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 391 9867 CEFBS_None, // JalOneReg = 392 9868 CEFBS_None, // JalTwoReg = 393 9869 CEFBS_HasStdEnc_NotMips3, // LDMacro = 394 9870 CEFBS_HasMSA, // LD_F16 = 395 9871 CEFBS_NotInMips16Mode, // LOAD_ACC128 = 396 9872 CEFBS_NotInMips16Mode, // LOAD_ACC64 = 397 9873 CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 398 9874 CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 399 9875 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 400 9876 CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 401 9877 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 402 9878 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 403 9879 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 404 9880 CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 405 9881 CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 406 9882 CEFBS_InMicroMips, // LWM_MM = 407 9883 CEFBS_None, // LoadAddrImm32 = 408 9884 CEFBS_None, // LoadAddrImm64 = 409 9885 CEFBS_None, // LoadAddrReg32 = 410 9886 CEFBS_None, // LoadAddrReg64 = 411 9887 CEFBS_None, // LoadImm32 = 412 9888 CEFBS_None, // LoadImm64 = 413 9889 CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 414 9890 CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 415 9891 CEFBS_None, // LoadImmDoubleGPR = 416 9892 CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 417 9893 CEFBS_None, // LoadImmSingleGPR = 418 9894 CEFBS_InMips16Mode, // LwConstant32 = 419 9895 CEFBS_HasMT, // MFTACX = 420 9896 CEFBS_HasMT, // MFTC0 = 421 9897 CEFBS_HasMT, // MFTC1 = 422 9898 CEFBS_HasMT, // MFTDSP = 423 9899 CEFBS_HasMT, // MFTGPR = 424 9900 CEFBS_HasMT, // MFTHC1 = 425 9901 CEFBS_HasMT, // MFTHI = 426 9902 CEFBS_HasMT, // MFTLO = 427 9903 CEFBS_None, // MIPSeh_return32 = 428 9904 CEFBS_None, // MIPSeh_return64 = 429 9905 CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 430 9906 CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 431 9907 CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 432 9908 CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 433 9909 CEFBS_HasMT, // MTTACX = 434 9910 CEFBS_HasMT, // MTTC0 = 435 9911 CEFBS_HasMT, // MTTC1 = 436 9912 CEFBS_HasMT, // MTTDSP = 437 9913 CEFBS_HasMT, // MTTGPR = 438 9914 CEFBS_HasMT, // MTTHC1 = 439 9915 CEFBS_HasMT, // MTTHI = 440 9916 CEFBS_HasMT, // MTTLO = 441 9917 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 442 9918 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 443 9919 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 444 9920 CEFBS_InMips16Mode, // MultRxRy16 = 445 9921 CEFBS_InMips16Mode, // MultRxRyRz16 = 446 9922 CEFBS_InMips16Mode, // MultuRxRy16 = 447 9923 CEFBS_InMips16Mode, // MultuRxRyRz16 = 448 9924 CEFBS_HasStdEnc_NotInMicroMips, // NOP = 449 9925 CEFBS_IsGP32bit, // NORImm = 450 9926 CEFBS_IsGP64bit, // NORImm64 = 451 9927 CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 452 9928 CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 453 9929 CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 454 9930 CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 455 9931 CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 456 9932 CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 457 9933 CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 458 9934 CEFBS_HasDSP, // PseudoCMPU_LE_QB = 459 9935 CEFBS_HasDSP, // PseudoCMPU_LT_QB = 460 9936 CEFBS_HasDSP, // PseudoCMP_EQ_PH = 461 9937 CEFBS_HasDSP, // PseudoCMP_LE_PH = 462 9938 CEFBS_HasDSP, // PseudoCMP_LT_PH = 463 9939 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 464 9940 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 465 9941 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 466 9942 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 467 9943 CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 468 9944 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 469 9945 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 470 9946 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 471 9947 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 472 9948 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 473 9949 CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 474 9950 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 475 9951 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 476 9952 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 477 9953 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 478 9954 CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 479 9955 CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 480 9956 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 481 9957 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 482 9958 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 483 9959 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 484 9960 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 485 9961 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 486 9962 CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 487 9963 CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 488 9964 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 489 9965 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 490 9966 CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 491 9967 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 492 9968 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 493 9969 CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 494 9970 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 495 9971 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 496 9972 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 497 9973 CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 498 9974 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 499 9975 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 500 9976 CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 501 9977 CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 502 9978 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 503 9979 CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 504 9980 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 505 9981 CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 506 9982 CEFBS_HasDSP, // PseudoPICK_PH = 507 9983 CEFBS_HasDSP, // PseudoPICK_QB = 508 9984 CEFBS_None, // PseudoReturn = 509 9985 CEFBS_IsGP64bit, // PseudoReturn64 = 510 9986 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 511 9987 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 512 9988 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 513 9989 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 514 9990 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 515 9991 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 516 9992 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 517 9993 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 518 9994 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 519 9995 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 520 9996 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 521 9997 CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 522 9998 CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 523 9999 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 524 10000 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 525 10001 CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 526 10002 CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 527 10003 CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 528 10004 CEFBS_None, // PseudoTRUNC_W_S = 529 10005 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 530 10006 CEFBS_None, // ROL = 531 10007 CEFBS_None, // ROLImm = 532 10008 CEFBS_None, // ROR = 533 10009 CEFBS_None, // RORImm = 534 10010 CEFBS_NotInMips16Mode, // RetRA = 535 10011 CEFBS_InMips16Mode, // RetRA16 = 536 10012 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 537 10013 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 538 10014 CEFBS_HasStdEnc_NotMips3, // SDMacro = 539 10015 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 540 10016 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 541 10017 CEFBS_NotCnMips, // SEQIMacro = 542 10018 CEFBS_NotCnMips, // SEQMacro = 543 10019 CEFBS_HasStdEnc_NotInMicroMips, // SGE = 544 10020 CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 545 10021 CEFBS_IsGP64bit, // SGEImm64 = 546 10022 CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 547 10023 CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 548 10024 CEFBS_IsGP64bit, // SGEUImm64 = 549 10025 CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 550 10026 CEFBS_IsGP64bit, // SGTImm64 = 551 10027 CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 552 10028 CEFBS_IsGP64bit, // SGTUImm64 = 553 10029 CEFBS_IsGP64bit, // SLTImm64 = 554 10030 CEFBS_IsGP64bit, // SLTUImm64 = 555 10031 CEFBS_None, // SNZ_B_PSEUDO = 556 10032 CEFBS_None, // SNZ_D_PSEUDO = 557 10033 CEFBS_None, // SNZ_H_PSEUDO = 558 10034 CEFBS_None, // SNZ_V_PSEUDO = 559 10035 CEFBS_None, // SNZ_W_PSEUDO = 560 10036 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 561 10037 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 562 10038 CEFBS_NotInMips16Mode, // STORE_ACC128 = 563 10039 CEFBS_NotInMips16Mode, // STORE_ACC64 = 564 10040 CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 565 10041 CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 566 10042 CEFBS_HasMSA, // ST_F16 = 567 10043 CEFBS_InMicroMips, // SWM_MM = 568 10044 CEFBS_None, // SZ_B_PSEUDO = 569 10045 CEFBS_None, // SZ_D_PSEUDO = 570 10046 CEFBS_None, // SZ_H_PSEUDO = 571 10047 CEFBS_None, // SZ_V_PSEUDO = 572 10048 CEFBS_None, // SZ_W_PSEUDO = 573 10049 CEFBS_HasCnMipsP, // SaaAddr = 574 10050 CEFBS_HasCnMipsP, // SaadAddr = 575 10051 CEFBS_InMips16Mode, // SelBeqZ = 576 10052 CEFBS_InMips16Mode, // SelBneZ = 577 10053 CEFBS_InMips16Mode, // SelTBteqZCmp = 578 10054 CEFBS_InMips16Mode, // SelTBteqZCmpi = 579 10055 CEFBS_InMips16Mode, // SelTBteqZSlt = 580 10056 CEFBS_InMips16Mode, // SelTBteqZSlti = 581 10057 CEFBS_InMips16Mode, // SelTBteqZSltiu = 582 10058 CEFBS_InMips16Mode, // SelTBteqZSltu = 583 10059 CEFBS_InMips16Mode, // SelTBtneZCmp = 584 10060 CEFBS_InMips16Mode, // SelTBtneZCmpi = 585 10061 CEFBS_InMips16Mode, // SelTBtneZSlt = 586 10062 CEFBS_InMips16Mode, // SelTBtneZSlti = 587 10063 CEFBS_InMips16Mode, // SelTBtneZSltiu = 588 10064 CEFBS_InMips16Mode, // SelTBtneZSltu = 589 10065 CEFBS_InMips16Mode, // SltCCRxRy16 = 590 10066 CEFBS_InMips16Mode, // SltiCCRxImmX16 = 591 10067 CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 592 10068 CEFBS_InMips16Mode, // SltuCCRxRy16 = 593 10069 CEFBS_InMips16Mode, // SltuRxRyRz16 = 594 10070 CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 595 10071 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 596 10072 CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 597 10073 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 598 10074 CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 599 10075 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 600 10076 CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 601 10077 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 602 10078 CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 603 10079 CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 604 10080 CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 605 10081 CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 606 10082 CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 607 10083 CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 608 10084 CEFBS_InMicroMips, // TRAP_MM = 609 10085 CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 610 10086 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 611 10087 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 612 10088 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 613 10089 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 614 10090 CEFBS_None, // Ulh = 615 10091 CEFBS_None, // Ulhu = 616 10092 CEFBS_None, // Ulw = 617 10093 CEFBS_None, // Ush = 618 10094 CEFBS_None, // Usw = 619 10095 CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 620 10096 CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 621 10097 CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 622 10098 CEFBS_HasDSP, // ABSQ_S_PH = 623 10099 CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 624 10100 CEFBS_HasDSPR2, // ABSQ_S_QB = 625 10101 CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 626 10102 CEFBS_HasDSP, // ABSQ_S_W = 627 10103 CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 628 10104 CEFBS_HasStdEnc_NotInMicroMips, // ADD = 629 10105 CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 630 10106 CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 631 10107 CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 632 10108 CEFBS_InMicroMips, // ADDIUR1SP_MM = 633 10109 CEFBS_InMicroMips, // ADDIUR2_MM = 634 10110 CEFBS_InMicroMips, // ADDIUS5_MM = 635 10111 CEFBS_InMicroMips, // ADDIUSP_MM = 636 10112 CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 637 10113 CEFBS_HasDSPR2, // ADDQH_PH = 638 10114 CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 639 10115 CEFBS_HasDSPR2, // ADDQH_R_PH = 640 10116 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 641 10117 CEFBS_HasDSPR2, // ADDQH_R_W = 642 10118 CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 643 10119 CEFBS_HasDSPR2, // ADDQH_W = 644 10120 CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 645 10121 CEFBS_HasDSP, // ADDQ_PH = 646 10122 CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 647 10123 CEFBS_HasDSP, // ADDQ_S_PH = 648 10124 CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 649 10125 CEFBS_HasDSP, // ADDQ_S_W = 650 10126 CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 651 10127 CEFBS_HasDSP, // ADDSC = 652 10128 CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 653 10129 CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 654 10130 CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 655 10131 CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 656 10132 CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 657 10133 CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 658 10134 CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 659 10135 CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 660 10136 CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 661 10137 CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 662 10138 CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 663 10139 CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 664 10140 CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 665 10141 CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 666 10142 CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 667 10143 CEFBS_HasDSPR2, // ADDUH_QB = 668 10144 CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 669 10145 CEFBS_HasDSPR2, // ADDUH_R_QB = 670 10146 CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 671 10147 CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 672 10148 CEFBS_HasDSPR2, // ADDU_PH = 673 10149 CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 674 10150 CEFBS_HasDSP, // ADDU_QB = 675 10151 CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 676 10152 CEFBS_HasDSPR2, // ADDU_S_PH = 677 10153 CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 678 10154 CEFBS_HasDSP, // ADDU_S_QB = 679 10155 CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 680 10156 CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 681 10157 CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 682 10158 CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 683 10159 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 684 10160 CEFBS_HasStdEnc_HasMSA, // ADDV_B = 685 10161 CEFBS_HasStdEnc_HasMSA, // ADDV_D = 686 10162 CEFBS_HasStdEnc_HasMSA, // ADDV_H = 687 10163 CEFBS_HasStdEnc_HasMSA, // ADDV_W = 688 10164 CEFBS_HasDSP, // ADDWC = 689 10165 CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 690 10166 CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 691 10167 CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 692 10168 CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 693 10169 CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 694 10170 CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 695 10171 CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 696 10172 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 697 10173 CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 698 10174 CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 699 10175 CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 700 10176 CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 701 10177 CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 702 10178 CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 703 10179 CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 704 10180 CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 705 10181 CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 706 10182 CEFBS_HasStdEnc_NotInMicroMips, // AND = 707 10183 CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 708 10184 CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 709 10185 CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 710 10186 CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 711 10187 CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 712 10188 CEFBS_HasStdEnc_HasMSA, // ANDI_B = 713 10189 CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 714 10190 CEFBS_InMicroMips_NotMips32r6, // AND_MM = 715 10191 CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 716 10192 CEFBS_HasStdEnc_HasMSA, // AND_V = 717 10193 CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 718 10194 CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 719 10195 CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 720 10196 CEFBS_HasDSPR2, // APPEND = 721 10197 CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 722 10198 CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 723 10199 CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 724 10200 CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 725 10201 CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 726 10202 CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 727 10203 CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 728 10204 CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 729 10205 CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 730 10206 CEFBS_HasStdEnc_HasMips32r6, // AUI = 731 10207 CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 732 10208 CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 733 10209 CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 734 10210 CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 735 10211 CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 736 10212 CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 737 10213 CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 738 10214 CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 739 10215 CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 740 10216 CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 741 10217 CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 742 10218 CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 743 10219 CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 744 10220 CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 745 10221 CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 746 10222 CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 747 10223 CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 748 10224 CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 749 10225 CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 750 10226 CEFBS_InMips16Mode, // AddiuRxImmX16 = 751 10227 CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 752 10228 CEFBS_InMips16Mode, // AddiuRxRxImm16 = 753 10229 CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 754 10230 CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 755 10231 CEFBS_InMips16Mode, // AddiuSpImm16 = 756 10232 CEFBS_InMips16Mode, // AddiuSpImmX16 = 757 10233 CEFBS_InMips16Mode, // AdduRxRyRz16 = 758 10234 CEFBS_InMips16Mode, // AndRxRxRy16 = 759 10235 CEFBS_InMicroMips, // B16_MM = 760 10236 CEFBS_HasCnMips, // BADDu = 761 10237 CEFBS_HasStdEnc_HasMips32r6, // BAL = 762 10238 CEFBS_HasStdEnc_HasMips32r6, // BALC = 763 10239 CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 764 10240 CEFBS_HasDSPR2, // BALIGN = 765 10241 CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 766 10242 CEFBS_HasCnMips, // BBIT0 = 767 10243 CEFBS_HasCnMips, // BBIT032 = 768 10244 CEFBS_HasCnMips, // BBIT1 = 769 10245 CEFBS_HasCnMips, // BBIT132 = 770 10246 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 771 10247 CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 772 10248 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 773 10249 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 774 10250 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 775 10251 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 776 10252 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 777 10253 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 778 10254 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 779 10255 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 780 10256 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 781 10257 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 782 10258 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 783 10259 CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 784 10260 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 785 10261 CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 786 10262 CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 787 10263 CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 788 10264 CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 789 10265 CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 790 10266 CEFBS_HasStdEnc_HasMSA, // BCLR_B = 791 10267 CEFBS_HasStdEnc_HasMSA, // BCLR_D = 792 10268 CEFBS_HasStdEnc_HasMSA, // BCLR_H = 793 10269 CEFBS_HasStdEnc_HasMSA, // BCLR_W = 794 10270 CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 795 10271 CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 796 10272 CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 797 10273 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 798 10274 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 799 10275 CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 800 10276 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 801 10277 CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 802 10278 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 803 10279 CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 804 10280 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 805 10281 CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 806 10282 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 807 10283 CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 808 10284 CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 809 10285 CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 810 10286 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 811 10287 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 812 10288 CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 813 10289 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 814 10290 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 815 10291 CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 816 10292 CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 817 10293 CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 818 10294 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 819 10295 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 820 10296 CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 821 10297 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 822 10298 CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 823 10299 CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 824 10300 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 825 10301 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 826 10302 CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 827 10303 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 828 10304 CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 829 10305 CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 830 10306 CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 831 10307 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 832 10308 CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 833 10309 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 834 10310 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 835 10311 CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 836 10312 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 837 10313 CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 838 10314 CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 839 10315 CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 840 10316 CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 841 10317 CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 842 10318 CEFBS_HasStdEnc_HasMSA, // BINSL_B = 843 10319 CEFBS_HasStdEnc_HasMSA, // BINSL_D = 844 10320 CEFBS_HasStdEnc_HasMSA, // BINSL_H = 845 10321 CEFBS_HasStdEnc_HasMSA, // BINSL_W = 846 10322 CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 847 10323 CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 848 10324 CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 849 10325 CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 850 10326 CEFBS_HasStdEnc_HasMSA, // BINSR_B = 851 10327 CEFBS_HasStdEnc_HasMSA, // BINSR_D = 852 10328 CEFBS_HasStdEnc_HasMSA, // BINSR_H = 853 10329 CEFBS_HasStdEnc_HasMSA, // BINSR_W = 854 10330 CEFBS_HasDSP, // BITREV = 855 10331 CEFBS_InMicroMips_HasDSP, // BITREV_MM = 856 10332 CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 857 10333 CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 858 10334 CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 859 10335 CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 860 10336 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 861 10337 CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 862 10338 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 863 10339 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 864 10340 CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 865 10341 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 866 10342 CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 867 10343 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 868 10344 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 869 10345 CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 870 10346 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 871 10347 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 872 10348 CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 873 10349 CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 874 10350 CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 875 10351 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 876 10352 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 877 10353 CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 878 10354 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 879 10355 CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 880 10356 CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 881 10357 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 882 10358 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 883 10359 CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 884 10360 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 885 10361 CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 886 10362 CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 887 10363 CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 888 10364 CEFBS_HasStdEnc_HasMSA, // BMZI_B = 889 10365 CEFBS_HasStdEnc_HasMSA, // BMZ_V = 890 10366 CEFBS_HasStdEnc_NotInMicroMips, // BNE = 891 10367 CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 892 10368 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 893 10369 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 894 10370 CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 895 10371 CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 896 10372 CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 897 10373 CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 898 10374 CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 899 10375 CEFBS_HasStdEnc_HasMSA, // BNEG_B = 900 10376 CEFBS_HasStdEnc_HasMSA, // BNEG_D = 901 10377 CEFBS_HasStdEnc_HasMSA, // BNEG_H = 902 10378 CEFBS_HasStdEnc_HasMSA, // BNEG_W = 903 10379 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 904 10380 CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 905 10381 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 906 10382 CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 907 10383 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 908 10384 CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 909 10385 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 910 10386 CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 911 10387 CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 912 10388 CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 913 10389 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 914 10390 CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 915 10391 CEFBS_HasStdEnc_HasMSA, // BNZ_B = 916 10392 CEFBS_HasStdEnc_HasMSA, // BNZ_D = 917 10393 CEFBS_HasStdEnc_HasMSA, // BNZ_H = 918 10394 CEFBS_HasStdEnc_HasMSA, // BNZ_V = 919 10395 CEFBS_HasStdEnc_HasMSA, // BNZ_W = 920 10396 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 921 10397 CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 922 10398 CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 923 10399 CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 924 10400 CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 925 10401 CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 926 10402 CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 927 10403 CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 928 10404 CEFBS_InMicroMips, // BREAK_MM = 929 10405 CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 930 10406 CEFBS_HasStdEnc_HasMSA, // BSELI_B = 931 10407 CEFBS_HasStdEnc_HasMSA, // BSEL_V = 932 10408 CEFBS_HasStdEnc_HasMSA, // BSETI_B = 933 10409 CEFBS_HasStdEnc_HasMSA, // BSETI_D = 934 10410 CEFBS_HasStdEnc_HasMSA, // BSETI_H = 935 10411 CEFBS_HasStdEnc_HasMSA, // BSETI_W = 936 10412 CEFBS_HasStdEnc_HasMSA, // BSET_B = 937 10413 CEFBS_HasStdEnc_HasMSA, // BSET_D = 938 10414 CEFBS_HasStdEnc_HasMSA, // BSET_H = 939 10415 CEFBS_HasStdEnc_HasMSA, // BSET_W = 940 10416 CEFBS_HasStdEnc_HasMSA, // BZ_B = 941 10417 CEFBS_HasStdEnc_HasMSA, // BZ_D = 942 10418 CEFBS_HasStdEnc_HasMSA, // BZ_H = 943 10419 CEFBS_HasStdEnc_HasMSA, // BZ_V = 944 10420 CEFBS_HasStdEnc_HasMSA, // BZ_W = 945 10421 CEFBS_InMips16Mode, // BeqzRxImm16 = 946 10422 CEFBS_InMips16Mode, // BeqzRxImmX16 = 947 10423 CEFBS_InMips16Mode, // Bimm16 = 948 10424 CEFBS_InMips16Mode, // BimmX16 = 949 10425 CEFBS_InMips16Mode, // BnezRxImm16 = 950 10426 CEFBS_InMips16Mode, // BnezRxImmX16 = 951 10427 CEFBS_InMips16Mode, // Break16 = 952 10428 CEFBS_InMips16Mode, // Bteqz16 = 953 10429 CEFBS_InMips16Mode, // BteqzX16 = 954 10430 CEFBS_InMips16Mode, // Btnez16 = 955 10431 CEFBS_InMips16Mode, // BtnezX16 = 956 10432 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 957 10433 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 958 10434 CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 959 10435 CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 960 10436 CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 961 10437 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 962 10438 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 963 10439 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 964 10440 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 965 10441 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 966 10442 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 967 10443 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 968 10444 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 969 10445 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 970 10446 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 971 10447 CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 972 10448 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 973 10449 CEFBS_HasStdEnc_HasMSA, // CEQI_B = 974 10450 CEFBS_HasStdEnc_HasMSA, // CEQI_D = 975 10451 CEFBS_HasStdEnc_HasMSA, // CEQI_H = 976 10452 CEFBS_HasStdEnc_HasMSA, // CEQI_W = 977 10453 CEFBS_HasStdEnc_HasMSA, // CEQ_B = 978 10454 CEFBS_HasStdEnc_HasMSA, // CEQ_D = 979 10455 CEFBS_HasStdEnc_HasMSA, // CEQ_H = 980 10456 CEFBS_HasStdEnc_HasMSA, // CEQ_W = 981 10457 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 982 10458 CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 983 10459 CEFBS_InMicroMips, // CFC2_MM = 984 10460 CEFBS_HasStdEnc_HasMSA, // CFCMSA = 985 10461 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 986 10462 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 987 10463 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 988 10464 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 989 10465 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 990 10466 CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 991 10467 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 992 10468 CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 993 10469 CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 994 10470 CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 995 10471 CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 996 10472 CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 997 10473 CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 998 10474 CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 999 10475 CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1000 10476 CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1001 10477 CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1002 10478 CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1003 10479 CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1004 10480 CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1005 10481 CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1006 10482 CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1007 10483 CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1008 10484 CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1009 10485 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1010 10486 CEFBS_InMicroMips, // CLO_MM = 1011 10487 CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1012 10488 CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1013 10489 CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1014 10490 CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1015 10491 CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1016 10492 CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1017 10493 CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1018 10494 CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1019 10495 CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1020 10496 CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1021 10497 CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1022 10498 CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1023 10499 CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1024 10500 CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1025 10501 CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1026 10502 CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1027 10503 CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1028 10504 CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1029 10505 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1030 10506 CEFBS_InMicroMips, // CLZ_MM = 1031 10507 CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1032 10508 CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1033 10509 CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1034 10510 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1035 10511 CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1036 10512 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1037 10513 CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1038 10514 CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1039 10515 CEFBS_HasDSP, // CMPGU_EQ_QB = 1040 10516 CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1041 10517 CEFBS_HasDSP, // CMPGU_LE_QB = 1042 10518 CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1043 10519 CEFBS_HasDSP, // CMPGU_LT_QB = 1044 10520 CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1045 10521 CEFBS_HasDSP, // CMPU_EQ_QB = 1046 10522 CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1047 10523 CEFBS_HasDSP, // CMPU_LE_QB = 1048 10524 CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1049 10525 CEFBS_HasDSP, // CMPU_LT_QB = 1050 10526 CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1051 10527 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1052 10528 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1053 10529 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1054 10530 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1055 10531 CEFBS_HasDSP, // CMP_EQ_PH = 1056 10532 CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1057 10533 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1058 10534 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1059 10535 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1060 10536 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1061 10537 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1062 10538 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1063 10539 CEFBS_HasDSP, // CMP_LE_PH = 1064 10540 CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1065 10541 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1066 10542 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1067 10543 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1068 10544 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1069 10545 CEFBS_HasDSP, // CMP_LT_PH = 1070 10546 CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1071 10547 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1072 10548 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1073 10549 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1074 10550 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1075 10551 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1076 10552 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1077 10553 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1078 10554 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1079 10555 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1080 10556 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1081 10557 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1082 10558 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1083 10559 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1084 10560 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1085 10561 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1086 10562 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1087 10563 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1088 10564 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1089 10565 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1090 10566 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1091 10567 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1092 10568 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1093 10569 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1094 10570 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1095 10571 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1096 10572 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1097 10573 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1098 10574 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1099 10575 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1100 10576 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1101 10577 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1102 10578 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1103 10579 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1104 10580 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1105 10581 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1106 10582 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1107 10583 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1108 10584 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1109 10585 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1110 10586 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1111 10587 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1112 10588 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1113 10589 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1114 10590 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1115 10591 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1116 10592 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1117 10593 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1118 10594 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1119 10595 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1120 10596 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1121 10597 CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1122 10598 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1123 10599 CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1124 10600 CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1125 10601 CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1126 10602 CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1127 10603 CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1128 10604 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1129 10605 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1130 10606 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1131 10607 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1132 10608 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1133 10609 CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1134 10610 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1135 10611 CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1136 10612 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1137 10613 CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1138 10614 CEFBS_InMicroMips, // CTC2_MM = 1139 10615 CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1140 10616 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1141 10617 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1142 10618 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1143 10619 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1144 10620 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1145 10621 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1146 10622 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1147 10623 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1148 10624 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1149 10625 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1150 10626 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1151 10627 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1152 10628 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1153 10629 CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1154 10630 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1155 10631 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1156 10632 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1157 10633 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1158 10634 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1159 10635 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1160 10636 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1161 10637 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1162 10638 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1163 10639 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1164 10640 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1165 10641 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1166 10642 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1167 10643 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1168 10644 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1169 10645 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1170 10646 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1171 10647 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1172 10648 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1173 10649 CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1174 10650 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1175 10651 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1176 10652 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1177 10653 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1178 10654 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1179 10655 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1180 10656 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1181 10657 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1182 10658 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1183 10659 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1184 10660 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1185 10661 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1186 10662 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1187 10663 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1188 10664 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1189 10665 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1190 10666 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1191 10667 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1192 10668 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1193 10669 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1194 10670 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1195 10671 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1196 10672 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1197 10673 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1198 10674 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1199 10675 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1200 10676 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1201 10677 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1202 10678 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1203 10679 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1204 10680 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1205 10681 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1206 10682 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1207 10683 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1208 10684 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1209 10685 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1210 10686 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1211 10687 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1212 10688 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1213 10689 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1214 10690 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1215 10691 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1216 10692 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1217 10693 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1218 10694 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1219 10695 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1220 10696 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1221 10697 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1222 10698 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1223 10699 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1224 10700 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1225 10701 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1226 10702 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1227 10703 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1228 10704 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1229 10705 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1230 10706 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1231 10707 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1232 10708 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1233 10709 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1234 10710 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1235 10711 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1236 10712 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1237 10713 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1238 10714 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1239 10715 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1240 10716 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1241 10717 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1242 10718 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1243 10719 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1244 10720 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1245 10721 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1246 10722 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1247 10723 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1248 10724 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1249 10725 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1250 10726 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1251 10727 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1252 10728 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1253 10729 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1254 10730 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1255 10731 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1256 10732 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1257 10733 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1258 10734 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1259 10735 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1260 10736 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1261 10737 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1262 10738 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1263 10739 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1264 10740 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1265 10741 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1266 10742 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1267 10743 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1268 10744 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1269 10745 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1270 10746 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1271 10747 CEFBS_InMips16Mode, // CmpRxRy16 = 1272 10748 CEFBS_InMips16Mode, // CmpiRxImm16 = 1273 10749 CEFBS_InMips16Mode, // CmpiRxImmX16 = 1274 10750 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1275 10751 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1276 10752 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1277 10753 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1278 10754 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1279 10755 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1280 10756 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1281 10757 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1282 10758 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1283 10759 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1284 10760 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1285 10761 CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1286 10762 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1287 10763 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1288 10764 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1289 10765 CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1290 10766 CEFBS_InMicroMips, // DERET_MM = 1291 10767 CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1292 10768 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1293 10769 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1294 10770 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1295 10771 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1296 10772 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1297 10773 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1298 10774 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1299 10775 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1300 10776 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1301 10777 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1302 10778 CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1303 10779 CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1304 10780 CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1305 10781 CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1306 10782 CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1307 10783 CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1308 10784 CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1309 10785 CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1310 10786 CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1311 10787 CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1312 10788 CEFBS_InMicroMips, // DI_MM = 1313 10789 CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1314 10790 CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1315 10791 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1316 10792 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1317 10793 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1318 10794 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1319 10795 CEFBS_HasCnMips, // DMFC2_OCTEON = 1320 10796 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1321 10797 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1322 10798 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1323 10799 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1324 10800 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1325 10801 CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1326 10802 CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1327 10803 CEFBS_HasCnMips, // DMTC2_OCTEON = 1328 10804 CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1329 10805 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1330 10806 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1331 10807 CEFBS_HasCnMips, // DMUL = 1332 10808 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1333 10809 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1334 10810 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1335 10811 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1336 10812 CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1337 10813 CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1338 10814 CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1339 10815 CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1340 10816 CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1341 10817 CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1342 10818 CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1343 10819 CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1344 10820 CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1345 10821 CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1346 10822 CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1347 10823 CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1348 10824 CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1349 10825 CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1350 10826 CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1351 10827 CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1352 10828 CEFBS_HasDSP, // DPAQ_SA_L_W = 1353 10829 CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1354 10830 CEFBS_HasDSP, // DPAQ_S_W_PH = 1355 10831 CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1356 10832 CEFBS_HasDSP, // DPAU_H_QBL = 1357 10833 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1358 10834 CEFBS_HasDSP, // DPAU_H_QBR = 1359 10835 CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1360 10836 CEFBS_HasDSPR2, // DPAX_W_PH = 1361 10837 CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1362 10838 CEFBS_HasDSPR2, // DPA_W_PH = 1363 10839 CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1364 10840 CEFBS_HasCnMips, // DPOP = 1365 10841 CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1366 10842 CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1367 10843 CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1368 10844 CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1369 10845 CEFBS_HasDSP, // DPSQ_SA_L_W = 1370 10846 CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1371 10847 CEFBS_HasDSP, // DPSQ_S_W_PH = 1372 10848 CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1373 10849 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1374 10850 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1375 10851 CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1376 10852 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1377 10853 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1378 10854 CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1379 10855 CEFBS_HasDSP, // DPSU_H_QBL = 1380 10856 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1381 10857 CEFBS_HasDSP, // DPSU_H_QBR = 1382 10858 CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1383 10859 CEFBS_HasDSPR2, // DPSX_W_PH = 1384 10860 CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1385 10861 CEFBS_HasDSPR2, // DPS_W_PH = 1386 10862 CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1387 10863 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1388 10864 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1389 10865 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1390 10866 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1391 10867 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1392 10868 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1393 10869 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1394 10870 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1395 10871 CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1396 10872 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1397 10873 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1398 10874 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1399 10875 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1400 10876 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1401 10877 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1402 10878 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1403 10879 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1404 10880 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1405 10881 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1406 10882 CEFBS_HasStdEnc_HasMips32r6, // DVP = 1407 10883 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1408 10884 CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1409 10885 CEFBS_InMips16Mode, // DivRxRy16 = 1410 10886 CEFBS_InMips16Mode, // DivuRxRy16 = 1411 10887 CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1412 10888 CEFBS_InMicroMips, // EHB_MM = 1413 10889 CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1414 10890 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1415 10891 CEFBS_InMicroMips, // EI_MM = 1416 10892 CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1417 10893 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1418 10894 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1419 10895 CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1420 10896 CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1421 10897 CEFBS_InMicroMips, // ERET_MM = 1422 10898 CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1423 10899 CEFBS_HasStdEnc_HasMips32r6, // EVP = 1424 10900 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1425 10901 CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1426 10902 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1427 10903 CEFBS_HasDSP, // EXTP = 1428 10904 CEFBS_HasDSP, // EXTPDP = 1429 10905 CEFBS_HasDSP, // EXTPDPV = 1430 10906 CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1431 10907 CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1432 10908 CEFBS_HasDSP, // EXTPV = 1433 10909 CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1434 10910 CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1435 10911 CEFBS_HasDSP, // EXTRV_RS_W = 1436 10912 CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1437 10913 CEFBS_HasDSP, // EXTRV_R_W = 1438 10914 CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1439 10915 CEFBS_HasDSP, // EXTRV_S_H = 1440 10916 CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1441 10917 CEFBS_HasDSP, // EXTRV_W = 1442 10918 CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1443 10919 CEFBS_HasDSP, // EXTR_RS_W = 1444 10920 CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1445 10921 CEFBS_HasDSP, // EXTR_R_W = 1446 10922 CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1447 10923 CEFBS_HasDSP, // EXTR_S_H = 1448 10924 CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1449 10925 CEFBS_HasDSP, // EXTR_W = 1450 10926 CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1451 10927 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1452 10928 CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1453 10929 CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1454 10930 CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1455 10931 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1456 10932 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1457 10933 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1458 10934 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1459 10935 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1460 10936 CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1461 10937 CEFBS_HasStdEnc_HasMSA, // FADD_D = 1462 10938 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1463 10939 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1464 10940 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1465 10941 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1466 10942 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1467 10943 CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1468 10944 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1469 10945 CEFBS_HasStdEnc_HasMSA, // FADD_W = 1470 10946 CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1471 10947 CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1472 10948 CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1473 10949 CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1474 10950 CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1475 10951 CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1476 10952 CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1477 10953 CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1478 10954 CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1479 10955 CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1480 10956 CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1481 10957 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1482 10958 CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1483 10959 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1484 10960 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1485 10961 CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1486 10962 CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1487 10963 CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1488 10964 CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1489 10965 CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1490 10966 CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1491 10967 CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1492 10968 CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1493 10969 CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1494 10970 CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1495 10971 CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1496 10972 CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1497 10973 CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1498 10974 CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1499 10975 CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1500 10976 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1501 10977 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1502 10978 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1503 10979 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1504 10980 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1505 10981 CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1506 10982 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1507 10983 CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1508 10984 CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1509 10985 CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1510 10986 CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1511 10987 CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1512 10988 CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1513 10989 CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1514 10990 CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1515 10991 CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1516 10992 CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1517 10993 CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1518 10994 CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1519 10995 CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1520 10996 CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1521 10997 CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1522 10998 CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1523 10999 CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1524 11000 CEFBS_HasStdEnc_HasMSA, // FILL_B = 1525 11001 CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1526 11002 CEFBS_HasStdEnc_HasMSA, // FILL_H = 1527 11003 CEFBS_HasStdEnc_HasMSA, // FILL_W = 1528 11004 CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1529 11005 CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1530 11006 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1531 11007 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1532 11008 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1533 11009 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1534 11010 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1535 11011 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1536 11012 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1537 11013 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1538 11014 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1539 11015 CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1540 11016 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1541 11017 CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1542 11018 CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1543 11019 CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1544 11020 CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1545 11021 CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1546 11022 CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1547 11023 CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1548 11024 CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1549 11025 CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1550 11026 CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1551 11027 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1552 11028 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1553 11029 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1554 11030 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1555 11031 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1556 11032 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1557 11033 CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1558 11034 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1559 11035 CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1560 11036 CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1561 11037 CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1562 11038 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1563 11039 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1564 11040 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1565 11041 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1566 11042 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1567 11043 CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1568 11044 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1569 11045 CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1570 11046 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1571 11047 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1572 11048 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1573 11049 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1574 11050 CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1575 11051 CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1576 11052 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1577 11053 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1578 11054 CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1579 11055 CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1580 11056 CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1581 11057 CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1582 11058 CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1583 11059 CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1584 11060 CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1585 11061 CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1586 11062 CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1587 11063 CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1588 11064 CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1589 11065 CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1590 11066 CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1591 11067 CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1592 11068 CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1593 11069 CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1594 11070 CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1595 11071 CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1596 11072 CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1597 11073 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1598 11074 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1599 11075 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1600 11076 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1601 11077 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1602 11078 CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1603 11079 CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1604 11080 CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1605 11081 CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1606 11082 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1607 11083 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1608 11084 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1609 11085 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1610 11086 CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1611 11087 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1612 11088 CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1613 11089 CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1614 11090 CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1615 11091 CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1616 11092 CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1617 11093 CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1618 11094 CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1619 11095 CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1620 11096 CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1621 11097 CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1622 11098 CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1623 11099 CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1624 11100 CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1625 11101 CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1626 11102 CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1627 11103 CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1628 11104 CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1629 11105 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1630 11106 CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1631 11107 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1632 11108 CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1633 11109 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1634 11110 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1635 11111 CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1636 11112 CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1637 11113 CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1638 11114 CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1639 11115 CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1640 11116 CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1641 11117 CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1642 11118 CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1643 11119 CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1644 11120 CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1645 11121 CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1646 11122 CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1647 11123 CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1648 11124 CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1649 11125 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1650 11126 CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1651 11127 CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1652 11128 CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1653 11129 CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1654 11130 CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1655 11131 CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1656 11132 CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1657 11133 CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1658 11134 CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1659 11135 CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1660 11136 CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1661 11137 CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1662 11138 CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1663 11139 CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1664 11140 CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1665 11141 CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1666 11142 CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1667 11143 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1668 11144 CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1669 11145 CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1670 11146 CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1671 11147 CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1672 11148 CEFBS_HasDSP, // INSV = 1673 11149 CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1674 11150 CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1675 11151 CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1676 11152 CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1677 11153 CEFBS_InMicroMips_HasDSP, // INSV_MM = 1678 11154 CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1679 11155 CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1680 11156 CEFBS_HasStdEnc_NotInMicroMips, // J = 1681 11157 CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1682 11158 CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1683 11159 CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1684 11160 CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1685 11161 CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1686 11162 CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1687 11163 CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1688 11164 CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1689 11165 CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1690 11166 CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1691 11167 CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1692 11168 CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1693 11169 CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1694 11170 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1695 11171 CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1696 11172 CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1697 11173 CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1698 11174 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1699 11175 CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1700 11176 CEFBS_HasStdEnc_HasMips32r6, // JIC = 1701 11177 CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1702 11178 CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1703 11179 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1704 11180 CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1705 11181 CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1706 11182 CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1707 11183 CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1708 11184 CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1709 11185 CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1710 11186 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1711 11187 CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1712 11188 CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1713 11189 CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1714 11190 CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1715 11191 CEFBS_InMicroMips_NotMips32r6, // J_MM = 1716 11192 CEFBS_InMips16Mode, // Jal16 = 1717 11193 CEFBS_InMips16Mode, // JalB16 = 1718 11194 CEFBS_InMips16Mode, // JrRa16 = 1719 11195 CEFBS_InMips16Mode, // JrcRa16 = 1720 11196 CEFBS_InMips16Mode, // JrcRx16 = 1721 11197 CEFBS_InMips16Mode, // JumpLinkReg16 = 1722 11198 CEFBS_HasStdEnc_NotInMicroMips, // LB = 1723 11199 CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1724 11200 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1725 11201 CEFBS_InMicroMips_HasEVA, // LBE_MM = 1726 11202 CEFBS_InMicroMips, // LBU16_MM = 1727 11203 CEFBS_HasDSP, // LBUX = 1728 11204 CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1729 11205 CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1730 11206 CEFBS_InMicroMips, // LB_MM = 1731 11207 CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1732 11208 CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1733 11209 CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1734 11210 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1735 11211 CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1736 11212 CEFBS_InMicroMips, // LBu_MM = 1737 11213 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1738 11214 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1739 11215 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1740 11216 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1741 11217 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM = 1742 11218 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1743 11219 CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1744 11220 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1745 11221 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1746 11222 CEFBS_HasStdEnc_HasMSA, // LDI_B = 1747 11223 CEFBS_HasStdEnc_HasMSA, // LDI_D = 1748 11224 CEFBS_HasStdEnc_HasMSA, // LDI_H = 1749 11225 CEFBS_HasStdEnc_HasMSA, // LDI_W = 1750 11226 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1751 11227 CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1752 11228 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1753 11229 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1754 11230 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1755 11231 CEFBS_HasStdEnc_HasMSA, // LD_B = 1756 11232 CEFBS_HasStdEnc_HasMSA, // LD_D = 1757 11233 CEFBS_HasStdEnc_HasMSA, // LD_H = 1758 11234 CEFBS_HasStdEnc_HasMSA, // LD_W = 1759 11235 CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1760 11236 CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1761 11237 CEFBS_InMicroMips, // LEA_ADDiu_MM = 1762 11238 CEFBS_HasStdEnc_NotInMicroMips, // LH = 1763 11239 CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1764 11240 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1765 11241 CEFBS_InMicroMips_HasEVA, // LHE_MM = 1766 11242 CEFBS_InMicroMips, // LHU16_MM = 1767 11243 CEFBS_HasDSP, // LHX = 1768 11244 CEFBS_InMicroMips_HasDSP, // LHX_MM = 1769 11245 CEFBS_InMicroMips, // LH_MM = 1770 11246 CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1771 11247 CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1772 11248 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1773 11249 CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1774 11250 CEFBS_InMicroMips, // LHu_MM = 1775 11251 CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1776 11252 CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1777 11253 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1778 11254 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1779 11255 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1780 11256 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1781 11257 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1782 11258 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1783 11259 CEFBS_InMicroMips_HasEVA, // LLE_MM = 1784 11260 CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1785 11261 CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1786 11262 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1787 11263 CEFBS_HasStdEnc_HasMSA, // LSA = 1788 11264 CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1789 11265 CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1790 11266 CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1791 11267 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1792 11268 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1793 11269 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1794 11270 CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1795 11271 CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1796 11272 CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1797 11273 CEFBS_HasStdEnc_NotInMicroMips, // LW = 1798 11274 CEFBS_InMicroMips, // LW16_MM = 1799 11275 CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1800 11276 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1801 11277 CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1802 11278 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1803 11279 CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1804 11280 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1805 11281 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1806 11282 CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1807 11283 CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1808 11284 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1809 11285 CEFBS_InMicroMips_HasEVA, // LWE_MM = 1810 11286 CEFBS_InMicroMips, // LWGP_MM = 1811 11287 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1812 11288 CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1813 11289 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1814 11290 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1815 11291 CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1816 11292 CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1817 11293 CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1818 11294 CEFBS_InMicroMips, // LWM32_MM = 1819 11295 CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1820 11296 CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1821 11297 CEFBS_InMicroMips, // LWP_MM = 1822 11298 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1823 11299 CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1824 11300 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1825 11301 CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1826 11302 CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1827 11303 CEFBS_InMicroMips, // LWSP_MM = 1828 11304 CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1829 11305 CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1830 11306 CEFBS_HasDSP, // LWX = 1831 11307 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1832 11308 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1833 11309 CEFBS_InMicroMips, // LWXS_MM = 1834 11310 CEFBS_InMicroMips_HasDSP, // LWX_MM = 1835 11311 CEFBS_InMicroMips, // LW_MM = 1836 11312 CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1837 11313 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1838 11314 CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1839 11315 CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1840 11316 CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1841 11317 CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1842 11318 CEFBS_InMips16Mode, // LiRxImm16 = 1843 11319 CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1844 11320 CEFBS_InMips16Mode, // LiRxImmX16 = 1845 11321 CEFBS_InMips16Mode, // LwRxPcTcp16 = 1846 11322 CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1847 11323 CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1848 11324 CEFBS_InMips16Mode, // LwRxSpImmX16 = 1849 11325 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1850 11326 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1851 11327 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1852 11328 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1853 11329 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1854 11330 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1855 11331 CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1856 11332 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1857 11333 CEFBS_HasDSP, // MADDU_DSP = 1858 11334 CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1859 11335 CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1860 11336 CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1861 11337 CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1862 11338 CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1863 11339 CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1864 11340 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1865 11341 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1866 11342 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1867 11343 CEFBS_HasDSP, // MADD_DSP = 1868 11344 CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1869 11345 CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1870 11346 CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1871 11347 CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1872 11348 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1873 11349 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1874 11350 CEFBS_HasDSP, // MAQ_SA_W_PHL = 1875 11351 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1876 11352 CEFBS_HasDSP, // MAQ_SA_W_PHR = 1877 11353 CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1878 11354 CEFBS_HasDSP, // MAQ_S_W_PHL = 1879 11355 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1880 11356 CEFBS_HasDSP, // MAQ_S_W_PHR = 1881 11357 CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1882 11358 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1883 11359 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1884 11360 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1885 11361 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1886 11362 CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1887 11363 CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1888 11364 CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1889 11365 CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1890 11366 CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1891 11367 CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1892 11368 CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1893 11369 CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1894 11370 CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1895 11371 CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1896 11372 CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1897 11373 CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1898 11374 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1899 11375 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1900 11376 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1901 11377 CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 1902 11378 CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 1903 11379 CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 1904 11380 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 1905 11381 CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 1906 11382 CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 1907 11383 CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 1908 11384 CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 1909 11385 CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 1910 11386 CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 1911 11387 CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 1912 11388 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 1913 11389 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 1914 11390 CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 1915 11391 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 1916 11392 CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 1917 11393 CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 1918 11394 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 1919 11395 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 1920 11396 CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 1921 11397 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 1922 11398 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 1923 11399 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 1924 11400 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 1925 11401 CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 1926 11402 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 1927 11403 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 1928 11404 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 1929 11405 CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 1930 11406 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 1931 11407 CEFBS_HasDSP, // MFHI_DSP = 1932 11408 CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 1933 11409 CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 1934 11410 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 1935 11411 CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 1936 11412 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 1937 11413 CEFBS_HasDSP, // MFLO_DSP = 1938 11414 CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 1939 11415 CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 1940 11416 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 1941 11417 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 1942 11418 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 1943 11419 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 1944 11420 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 1945 11421 CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 1946 11422 CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 1947 11423 CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 1948 11424 CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 1949 11425 CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 1950 11426 CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 1951 11427 CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 1952 11428 CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 1953 11429 CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 1954 11430 CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 1955 11431 CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 1956 11432 CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 1957 11433 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 1958 11434 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 1959 11435 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 1960 11436 CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 1961 11437 CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 1962 11438 CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 1963 11439 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 1964 11440 CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 1965 11441 CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 1966 11442 CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 1967 11443 CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 1968 11444 CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 1969 11445 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 1970 11446 CEFBS_HasDSP, // MODSUB = 1971 11447 CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 1972 11448 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 1973 11449 CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 1974 11450 CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 1975 11451 CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 1976 11452 CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 1977 11453 CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 1978 11454 CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 1979 11455 CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 1980 11456 CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 1981 11457 CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 1982 11458 CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 1983 11459 CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 1984 11460 CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 1985 11461 CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 1986 11462 CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 1987 11463 CEFBS_HasStdEnc_HasMSA, // MOVE_V = 1988 11464 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 1989 11465 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 1990 11466 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 1991 11467 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 1992 11468 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 1993 11469 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 1994 11470 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 1995 11471 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 1996 11472 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 1997 11473 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 1998 11474 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 1999 11475 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2000 11476 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2001 11477 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2002 11478 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2003 11479 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2004 11480 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2005 11481 CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2006 11482 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2007 11483 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2008 11484 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2009 11485 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2010 11486 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2011 11487 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2012 11488 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2013 11489 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2014 11490 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2015 11491 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2016 11492 CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2017 11493 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2018 11494 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2019 11495 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2020 11496 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2021 11497 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2022 11498 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2023 11499 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2024 11500 CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2025 11501 CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2026 11502 CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2027 11503 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2028 11504 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2029 11505 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2030 11506 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2031 11507 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2032 11508 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2033 11509 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2034 11510 CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2035 11511 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2036 11512 CEFBS_HasDSP, // MSUBU_DSP = 2037 11513 CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2038 11514 CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2039 11515 CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2040 11516 CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2041 11517 CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2042 11518 CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2043 11519 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2044 11520 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2045 11521 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2046 11522 CEFBS_HasDSP, // MSUB_DSP = 2047 11523 CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2048 11524 CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2049 11525 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2050 11526 CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2051 11527 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2052 11528 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2053 11529 CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2054 11530 CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2055 11531 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2056 11532 CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2057 11533 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2058 11534 CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2059 11535 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2060 11536 CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2061 11537 CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2062 11538 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2063 11539 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2064 11540 CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2065 11541 CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2066 11542 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2067 11543 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2068 11544 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2069 11545 CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2070 11546 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2071 11547 CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2072 11548 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2073 11549 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2074 11550 CEFBS_HasDSP, // MTHI_DSP = 2075 11551 CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2076 11552 CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2077 11553 CEFBS_HasDSP, // MTHLIP = 2078 11554 CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2079 11555 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2080 11556 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2081 11557 CEFBS_HasDSP, // MTLO_DSP = 2082 11558 CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2083 11559 CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2084 11560 CEFBS_HasCnMips, // MTM0 = 2085 11561 CEFBS_HasCnMips, // MTM1 = 2086 11562 CEFBS_HasCnMips, // MTM2 = 2087 11563 CEFBS_HasCnMips, // MTP0 = 2088 11564 CEFBS_HasCnMips, // MTP1 = 2089 11565 CEFBS_HasCnMips, // MTP2 = 2090 11566 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2091 11567 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2092 11568 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2093 11569 CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2094 11570 CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2095 11571 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2096 11572 CEFBS_HasDSP, // MULEQ_S_W_PHL = 2097 11573 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2098 11574 CEFBS_HasDSP, // MULEQ_S_W_PHR = 2099 11575 CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2100 11576 CEFBS_HasDSP, // MULEU_S_PH_QBL = 2101 11577 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2102 11578 CEFBS_HasDSP, // MULEU_S_PH_QBR = 2103 11579 CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2104 11580 CEFBS_HasDSP, // MULQ_RS_PH = 2105 11581 CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2106 11582 CEFBS_HasDSPR2, // MULQ_RS_W = 2107 11583 CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2108 11584 CEFBS_HasDSPR2, // MULQ_S_PH = 2109 11585 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2110 11586 CEFBS_HasDSPR2, // MULQ_S_W = 2111 11587 CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2112 11588 CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2113 11589 CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2114 11590 CEFBS_HasDSP, // MULSAQ_S_W_PH = 2115 11591 CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2116 11592 CEFBS_HasDSPR2, // MULSA_W_PH = 2117 11593 CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2118 11594 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2119 11595 CEFBS_HasDSP, // MULTU_DSP = 2120 11596 CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2121 11597 CEFBS_HasDSP, // MULT_DSP = 2122 11598 CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2123 11599 CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2124 11600 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2125 11601 CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2126 11602 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2127 11603 CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2128 11604 CEFBS_HasStdEnc_HasMSA, // MULV_B = 2129 11605 CEFBS_HasStdEnc_HasMSA, // MULV_D = 2130 11606 CEFBS_HasStdEnc_HasMSA, // MULV_H = 2131 11607 CEFBS_HasStdEnc_HasMSA, // MULV_W = 2132 11608 CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2133 11609 CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2134 11610 CEFBS_HasDSPR2, // MUL_PH = 2135 11611 CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2136 11612 CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2137 11613 CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2138 11614 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2139 11615 CEFBS_HasDSPR2, // MUL_S_PH = 2140 11616 CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2141 11617 CEFBS_InMips16Mode, // Mfhi16 = 2142 11618 CEFBS_InMips16Mode, // Mflo16 = 2143 11619 CEFBS_InMips16Mode, // Move32R16 = 2144 11620 CEFBS_InMips16Mode, // MoveR3216 = 2145 11621 CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2146 11622 CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2147 11623 CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2148 11624 CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2149 11625 CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2150 11626 CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2151 11627 CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2152 11628 CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2153 11629 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2154 11630 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2155 11631 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2156 11632 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2157 11633 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2158 11634 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2159 11635 CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2160 11636 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2161 11637 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2162 11638 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2163 11639 CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2164 11640 CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2165 11641 CEFBS_HasStdEnc_HasMSA, // NORI_B = 2166 11642 CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2167 11643 CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2168 11644 CEFBS_HasStdEnc_HasMSA, // NOR_V = 2169 11645 CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2170 11646 CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2171 11647 CEFBS_InMips16Mode, // NegRxRy16 = 2172 11648 CEFBS_InMips16Mode, // NotRxRy16 = 2173 11649 CEFBS_HasStdEnc_NotInMicroMips, // OR = 2174 11650 CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2175 11651 CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2176 11652 CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2177 11653 CEFBS_HasStdEnc_HasMSA, // ORI_B = 2178 11654 CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2179 11655 CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2180 11656 CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2181 11657 CEFBS_HasStdEnc_HasMSA, // OR_V = 2182 11658 CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2183 11659 CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2184 11660 CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2185 11661 CEFBS_InMips16Mode, // OrRxRxRy16 = 2186 11662 CEFBS_HasDSP, // PACKRL_PH = 2187 11663 CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2188 11664 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2189 11665 CEFBS_InMicroMips, // PAUSE_MM = 2190 11666 CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2191 11667 CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2192 11668 CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2193 11669 CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2194 11670 CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2195 11671 CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2196 11672 CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2197 11673 CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2198 11674 CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2199 11675 CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2200 11676 CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2201 11677 CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2202 11678 CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2203 11679 CEFBS_HasDSP, // PICK_PH = 2204 11680 CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2205 11681 CEFBS_HasDSP, // PICK_QB = 2206 11682 CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2207 11683 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2208 11684 CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2209 11685 CEFBS_HasCnMips, // POP = 2210 11686 CEFBS_HasDSP, // PRECEQU_PH_QBL = 2211 11687 CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2212 11688 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2213 11689 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2214 11690 CEFBS_HasDSP, // PRECEQU_PH_QBR = 2215 11691 CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2216 11692 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2217 11693 CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2218 11694 CEFBS_HasDSP, // PRECEQ_W_PHL = 2219 11695 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2220 11696 CEFBS_HasDSP, // PRECEQ_W_PHR = 2221 11697 CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2222 11698 CEFBS_HasDSP, // PRECEU_PH_QBL = 2223 11699 CEFBS_HasDSP, // PRECEU_PH_QBLA = 2224 11700 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2225 11701 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2226 11702 CEFBS_HasDSP, // PRECEU_PH_QBR = 2227 11703 CEFBS_HasDSP, // PRECEU_PH_QBRA = 2228 11704 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2229 11705 CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2230 11706 CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2231 11707 CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2232 11708 CEFBS_HasDSP, // PRECRQ_PH_W = 2233 11709 CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2234 11710 CEFBS_HasDSP, // PRECRQ_QB_PH = 2235 11711 CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2236 11712 CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2237 11713 CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2238 11714 CEFBS_HasDSPR2, // PRECR_QB_PH = 2239 11715 CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2240 11716 CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2241 11717 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2242 11718 CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2243 11719 CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2244 11720 CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2245 11721 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2246 11722 CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2247 11723 CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2248 11724 CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2249 11725 CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2250 11726 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2251 11727 CEFBS_HasDSPR2, // PREPEND = 2252 11728 CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2253 11729 CEFBS_HasDSP, // RADDU_W_QB = 2254 11730 CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2255 11731 CEFBS_HasDSP, // RDDSP = 2256 11732 CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2257 11733 CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2258 11734 CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2259 11735 CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2260 11736 CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2261 11737 CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2262 11738 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2263 11739 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2264 11740 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2265 11741 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2266 11742 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2267 11743 CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2268 11744 CEFBS_HasDSP, // REPLV_PH = 2269 11745 CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2270 11746 CEFBS_HasDSP, // REPLV_QB = 2271 11747 CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2272 11748 CEFBS_HasDSP, // REPL_PH = 2273 11749 CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2274 11750 CEFBS_HasDSP, // REPL_QB = 2275 11751 CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2276 11752 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2277 11753 CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2278 11754 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2279 11755 CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2280 11756 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2281 11757 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2282 11758 CEFBS_InMicroMips, // ROTRV_MM = 2283 11759 CEFBS_InMicroMips, // ROTR_MM = 2284 11760 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2285 11761 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2286 11762 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2287 11763 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2288 11764 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2289 11765 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2290 11766 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2291 11767 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2292 11768 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2293 11769 CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2294 11770 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2295 11771 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2296 11772 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2297 11773 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2298 11774 CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2299 11775 CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2300 11776 CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2301 11777 CEFBS_InMips16Mode, // Restore16 = 2302 11778 CEFBS_InMips16Mode, // RestoreX16 = 2303 11779 CEFBS_HasCnMipsP, // SAA = 2304 11780 CEFBS_HasCnMipsP, // SAAD = 2305 11781 CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2306 11782 CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2307 11783 CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2308 11784 CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2309 11785 CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2310 11786 CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2311 11787 CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2312 11788 CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2313 11789 CEFBS_HasStdEnc_NotInMicroMips, // SB = 2314 11790 CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2315 11791 CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2316 11792 CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2317 11793 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2318 11794 CEFBS_InMicroMips_HasEVA, // SBE_MM = 2319 11795 CEFBS_InMicroMips, // SB_MM = 2320 11796 CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2321 11797 CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2322 11798 CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2323 11799 CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2324 11800 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2325 11801 CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2326 11802 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2327 11803 CEFBS_InMicroMips_HasEVA, // SCE_MM = 2328 11804 CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2329 11805 CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2330 11806 CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2331 11807 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2332 11808 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2333 11809 CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2334 11810 CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2335 11811 CEFBS_InMicroMips, // SDBBP_MM = 2336 11812 CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2337 11813 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2338 11814 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2339 11815 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2340 11816 CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2341 11817 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM = 2342 11818 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2343 11819 CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2344 11820 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2345 11821 CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2346 11822 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2347 11823 CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2348 11824 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2349 11825 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2350 11826 CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2351 11827 CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2352 11828 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2353 11829 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2354 11830 CEFBS_InMicroMips, // SEB_MM = 2355 11831 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2356 11832 CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2357 11833 CEFBS_InMicroMips, // SEH_MM = 2358 11834 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2359 11835 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2360 11836 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2361 11837 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2362 11838 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2363 11839 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2364 11840 CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2365 11841 CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2366 11842 CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2367 11843 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2368 11844 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2369 11845 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2370 11846 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2371 11847 CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2372 11848 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2373 11849 CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2374 11850 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2375 11851 CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2376 11852 CEFBS_HasCnMips, // SEQ = 2377 11853 CEFBS_HasCnMips, // SEQi = 2378 11854 CEFBS_HasStdEnc_NotInMicroMips, // SH = 2379 11855 CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2380 11856 CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2381 11857 CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2382 11858 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2383 11859 CEFBS_InMicroMips_HasEVA, // SHE_MM = 2384 11860 CEFBS_HasStdEnc_HasMSA, // SHF_B = 2385 11861 CEFBS_HasStdEnc_HasMSA, // SHF_H = 2386 11862 CEFBS_HasStdEnc_HasMSA, // SHF_W = 2387 11863 CEFBS_HasDSP, // SHILO = 2388 11864 CEFBS_HasDSP, // SHILOV = 2389 11865 CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2390 11866 CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2391 11867 CEFBS_HasDSP, // SHLLV_PH = 2392 11868 CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2393 11869 CEFBS_HasDSP, // SHLLV_QB = 2394 11870 CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2395 11871 CEFBS_HasDSP, // SHLLV_S_PH = 2396 11872 CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2397 11873 CEFBS_HasDSP, // SHLLV_S_W = 2398 11874 CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2399 11875 CEFBS_HasDSP, // SHLL_PH = 2400 11876 CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2401 11877 CEFBS_HasDSP, // SHLL_QB = 2402 11878 CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2403 11879 CEFBS_HasDSP, // SHLL_S_PH = 2404 11880 CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2405 11881 CEFBS_HasDSP, // SHLL_S_W = 2406 11882 CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2407 11883 CEFBS_HasDSP, // SHRAV_PH = 2408 11884 CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2409 11885 CEFBS_HasDSPR2, // SHRAV_QB = 2410 11886 CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2411 11887 CEFBS_HasDSP, // SHRAV_R_PH = 2412 11888 CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2413 11889 CEFBS_HasDSPR2, // SHRAV_R_QB = 2414 11890 CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2415 11891 CEFBS_HasDSP, // SHRAV_R_W = 2416 11892 CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2417 11893 CEFBS_HasDSP, // SHRA_PH = 2418 11894 CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2419 11895 CEFBS_HasDSPR2, // SHRA_QB = 2420 11896 CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2421 11897 CEFBS_HasDSP, // SHRA_R_PH = 2422 11898 CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2423 11899 CEFBS_HasDSPR2, // SHRA_R_QB = 2424 11900 CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2425 11901 CEFBS_HasDSP, // SHRA_R_W = 2426 11902 CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2427 11903 CEFBS_HasDSPR2, // SHRLV_PH = 2428 11904 CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2429 11905 CEFBS_HasDSP, // SHRLV_QB = 2430 11906 CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2431 11907 CEFBS_HasDSPR2, // SHRL_PH = 2432 11908 CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2433 11909 CEFBS_HasDSP, // SHRL_QB = 2434 11910 CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2435 11911 CEFBS_InMicroMips, // SH_MM = 2436 11912 CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2437 11913 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2438 11914 CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2439 11915 CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2440 11916 CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2441 11917 CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2442 11918 CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2443 11919 CEFBS_HasStdEnc_HasMSA, // SLD_B = 2444 11920 CEFBS_HasStdEnc_HasMSA, // SLD_D = 2445 11921 CEFBS_HasStdEnc_HasMSA, // SLD_H = 2446 11922 CEFBS_HasStdEnc_HasMSA, // SLD_W = 2447 11923 CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2448 11924 CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2449 11925 CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2450 11926 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2451 11927 CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2452 11928 CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2453 11929 CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2454 11930 CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2455 11931 CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2456 11932 CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2457 11933 CEFBS_InMicroMips, // SLLV_MM = 2458 11934 CEFBS_HasStdEnc_HasMSA, // SLL_B = 2459 11935 CEFBS_HasStdEnc_HasMSA, // SLL_D = 2460 11936 CEFBS_HasStdEnc_HasMSA, // SLL_H = 2461 11937 CEFBS_InMicroMips, // SLL_MM = 2462 11938 CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2463 11939 CEFBS_HasStdEnc_HasMSA, // SLL_W = 2464 11940 CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2465 11941 CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2466 11942 CEFBS_InMicroMips, // SLT_MM = 2467 11943 CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2468 11944 CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2469 11945 CEFBS_InMicroMips, // SLTi_MM = 2470 11946 CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2471 11947 CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2472 11948 CEFBS_InMicroMips, // SLTiu_MM = 2473 11949 CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2474 11950 CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2475 11951 CEFBS_InMicroMips, // SLTu_MM = 2476 11952 CEFBS_HasCnMips, // SNE = 2477 11953 CEFBS_HasCnMips, // SNEi = 2478 11954 CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2479 11955 CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2480 11956 CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2481 11957 CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2482 11958 CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2483 11959 CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2484 11960 CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2485 11961 CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2486 11962 CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2487 11963 CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2488 11964 CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2489 11965 CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2490 11966 CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2491 11967 CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2492 11968 CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2493 11969 CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2494 11970 CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2495 11971 CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2496 11972 CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2497 11973 CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2498 11974 CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2499 11975 CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2500 11976 CEFBS_InMicroMips, // SRAV_MM = 2501 11977 CEFBS_HasStdEnc_HasMSA, // SRA_B = 2502 11978 CEFBS_HasStdEnc_HasMSA, // SRA_D = 2503 11979 CEFBS_HasStdEnc_HasMSA, // SRA_H = 2504 11980 CEFBS_InMicroMips, // SRA_MM = 2505 11981 CEFBS_HasStdEnc_HasMSA, // SRA_W = 2506 11982 CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2507 11983 CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2508 11984 CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2509 11985 CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2510 11986 CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2511 11987 CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2512 11988 CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2513 11989 CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2514 11990 CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2515 11991 CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2516 11992 CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2517 11993 CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2518 11994 CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2519 11995 CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2520 11996 CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2521 11997 CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2522 11998 CEFBS_InMicroMips, // SRLV_MM = 2523 11999 CEFBS_HasStdEnc_HasMSA, // SRL_B = 2524 12000 CEFBS_HasStdEnc_HasMSA, // SRL_D = 2525 12001 CEFBS_HasStdEnc_HasMSA, // SRL_H = 2526 12002 CEFBS_InMicroMips, // SRL_MM = 2527 12003 CEFBS_HasStdEnc_HasMSA, // SRL_W = 2528 12004 CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2529 12005 CEFBS_InMicroMips, // SSNOP_MM = 2530 12006 CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2531 12007 CEFBS_HasStdEnc_HasMSA, // ST_B = 2532 12008 CEFBS_HasStdEnc_HasMSA, // ST_D = 2533 12009 CEFBS_HasStdEnc_HasMSA, // ST_H = 2534 12010 CEFBS_HasStdEnc_HasMSA, // ST_W = 2535 12011 CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2536 12012 CEFBS_HasDSPR2, // SUBQH_PH = 2537 12013 CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2538 12014 CEFBS_HasDSPR2, // SUBQH_R_PH = 2539 12015 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2540 12016 CEFBS_HasDSPR2, // SUBQH_R_W = 2541 12017 CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2542 12018 CEFBS_HasDSPR2, // SUBQH_W = 2543 12019 CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2544 12020 CEFBS_HasDSP, // SUBQ_PH = 2545 12021 CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2546 12022 CEFBS_HasDSP, // SUBQ_S_PH = 2547 12023 CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2548 12024 CEFBS_HasDSP, // SUBQ_S_W = 2549 12025 CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2550 12026 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2551 12027 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2552 12028 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2553 12029 CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2554 12030 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2555 12031 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2556 12032 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2557 12033 CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2558 12034 CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2559 12035 CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2560 12036 CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2561 12037 CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2562 12038 CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2563 12039 CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2564 12040 CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2565 12041 CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2566 12042 CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2567 12043 CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2568 12044 CEFBS_HasDSPR2, // SUBUH_QB = 2569 12045 CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2570 12046 CEFBS_HasDSPR2, // SUBUH_R_QB = 2571 12047 CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2572 12048 CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2573 12049 CEFBS_HasDSPR2, // SUBU_PH = 2574 12050 CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2575 12051 CEFBS_HasDSP, // SUBU_QB = 2576 12052 CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2577 12053 CEFBS_HasDSPR2, // SUBU_S_PH = 2578 12054 CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2579 12055 CEFBS_HasDSP, // SUBU_S_QB = 2580 12056 CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2581 12057 CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2582 12058 CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2583 12059 CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2584 12060 CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2585 12061 CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2586 12062 CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2587 12063 CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2588 12064 CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2589 12065 CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2590 12066 CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2591 12067 CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2592 12068 CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2593 12069 CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2594 12070 CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2595 12071 CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2596 12072 CEFBS_HasStdEnc_NotInMicroMips, // SW = 2597 12073 CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2598 12074 CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2599 12075 CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2600 12076 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2601 12077 CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2602 12078 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2603 12079 CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2604 12080 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2605 12081 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2606 12082 CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2607 12083 CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2608 12084 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2609 12085 CEFBS_InMicroMips_HasEVA, // SWE_MM = 2610 12086 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2611 12087 CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2612 12088 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2613 12089 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2614 12090 CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2615 12091 CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2616 12092 CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2617 12093 CEFBS_InMicroMips, // SWM32_MM = 2618 12094 CEFBS_InMicroMips, // SWP_MM = 2619 12095 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2620 12096 CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2621 12097 CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2622 12098 CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2623 12099 CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2624 12100 CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2625 12101 CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2626 12102 CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2627 12103 CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2628 12104 CEFBS_InMicroMips, // SW_MM = 2629 12105 CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2630 12106 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2631 12107 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2632 12108 CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2633 12109 CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2634 12110 CEFBS_InMicroMips, // SYNC_MM = 2635 12111 CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2636 12112 CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2637 12113 CEFBS_InMicroMips, // SYSCALL_MM = 2638 12114 CEFBS_InMips16Mode, // Save16 = 2639 12115 CEFBS_InMips16Mode, // SaveX16 = 2640 12116 CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2641 12117 CEFBS_InMips16Mode, // SebRx16 = 2642 12118 CEFBS_InMips16Mode, // SehRx16 = 2643 12119 CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2644 12120 CEFBS_InMips16Mode, // SllX16 = 2645 12121 CEFBS_InMips16Mode, // SllvRxRy16 = 2646 12122 CEFBS_InMips16Mode, // SltRxRy16 = 2647 12123 CEFBS_InMips16Mode, // SltiRxImm16 = 2648 12124 CEFBS_InMips16Mode, // SltiRxImmX16 = 2649 12125 CEFBS_InMips16Mode, // SltiuRxImm16 = 2650 12126 CEFBS_InMips16Mode, // SltiuRxImmX16 = 2651 12127 CEFBS_InMips16Mode, // SltuRxRy16 = 2652 12128 CEFBS_InMips16Mode, // SraX16 = 2653 12129 CEFBS_InMips16Mode, // SravRxRy16 = 2654 12130 CEFBS_InMips16Mode, // SrlX16 = 2655 12131 CEFBS_InMips16Mode, // SrlvRxRy16 = 2656 12132 CEFBS_InMips16Mode, // SubuRxRyRz16 = 2657 12133 CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2658 12134 CEFBS_InMips16Mode, // SwRxSpImmX16 = 2659 12135 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2660 12136 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2661 12137 CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2662 12138 CEFBS_InMicroMips, // TEQ_MM = 2663 12139 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2664 12140 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2665 12141 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2666 12142 CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2667 12143 CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2668 12144 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2669 12145 CEFBS_InMicroMips, // TGEU_MM = 2670 12146 CEFBS_InMicroMips, // TGE_MM = 2671 12147 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2672 12148 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2673 12149 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2674 12150 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2675 12151 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2676 12152 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2677 12153 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2678 12154 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2679 12155 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2680 12156 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2681 12157 CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2682 12158 CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2683 12159 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2684 12160 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2685 12161 CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2686 12162 CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2687 12163 CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2688 12164 CEFBS_InMicroMips, // TLBP_MM = 2689 12165 CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2690 12166 CEFBS_InMicroMips, // TLBR_MM = 2691 12167 CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2692 12168 CEFBS_InMicroMips, // TLBWI_MM = 2693 12169 CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2694 12170 CEFBS_InMicroMips, // TLBWR_MM = 2695 12171 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2696 12172 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2697 12173 CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2698 12174 CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2699 12175 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2700 12176 CEFBS_InMicroMips, // TLTU_MM = 2701 12177 CEFBS_InMicroMips, // TLT_MM = 2702 12178 CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2703 12179 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2704 12180 CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2705 12181 CEFBS_InMicroMips, // TNE_MM = 2706 12182 CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2707 12183 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2708 12184 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2709 12185 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2710 12186 CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2711 12187 CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2712 12188 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2713 12189 CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2714 12190 CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2715 12191 CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2716 12192 CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2717 12193 CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2718 12194 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2719 12195 CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2720 12196 CEFBS_HasCnMips, // V3MULU = 2721 12197 CEFBS_HasCnMips, // VMM0 = 2722 12198 CEFBS_HasCnMips, // VMULU = 2723 12199 CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2724 12200 CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2725 12201 CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2726 12202 CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2727 12203 CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2728 12204 CEFBS_InMicroMips, // WAIT_MM = 2729 12205 CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2730 12206 CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2731 12207 CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2732 12208 CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2733 12209 CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2734 12210 CEFBS_InMicroMips, // WSBH_MM = 2735 12211 CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2736 12212 CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2737 12213 CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2738 12214 CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2739 12215 CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2740 12216 CEFBS_HasStdEnc_HasMSA, // XORI_B = 2741 12217 CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2742 12218 CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2743 12219 CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2744 12220 CEFBS_HasStdEnc_HasMSA, // XOR_V = 2745 12221 CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2746 12222 CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2747 12223 CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2748 12224 CEFBS_InMips16Mode, // XorRxRxRy16 = 2749 12225 CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2750 12226 }; 12227 12228 assert(Inst.getOpcode() < 2751); 12229 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; 12230 FeatureBitset MissingFeatures = 12231 (AvailableFeatures & RequiredFeatures) ^ 12232 RequiredFeatures; 12233 if (MissingFeatures.any()) { 12234 std::ostringstream Msg; 12235 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() 12236 << " instruction but the "; 12237 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 12238 if (MissingFeatures.test(i)) 12239 Msg << SubtargetFeatureNames[i] << " "; 12240 Msg << "predicate(s) are not met"; 12241 report_fatal_error(Msg.str()); 12242 } 12243#else 12244// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). 12245(void)MCII; 12246#endif // NDEBUG 12247} 12248#endif 12249