1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/X86TargetParser.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Triple.h"
16 
17 using namespace llvm;
18 using namespace llvm::X86;
19 
20 namespace {
21 
22 /// Container class for CPU features.
23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
24 /// nice to use std::bitset directly, but it doesn't support constant
25 /// initialization.
26 class FeatureBitset {
27   static constexpr unsigned NUM_FEATURE_WORDS =
28       (X86::CPU_FEATURE_MAX + 31) / 32;
29 
30   // This cannot be a std::array, operator[] is not constexpr until C++17.
31   uint32_t Bits[NUM_FEATURE_WORDS] = {};
32 
33 public:
34   constexpr FeatureBitset() = default;
FeatureBitset(std::initializer_list<unsigned> Init)35   constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36     for (auto I : Init)
37       set(I);
38   }
39 
any() const40   bool any() const {
41     return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42   }
43 
set(unsigned I)44   constexpr FeatureBitset &set(unsigned I) {
45     // GCC <6.2 crashes if this is written in a single statement.
46     uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47     Bits[I / 32] = NewBits;
48     return *this;
49   }
50 
operator [](unsigned I) const51   constexpr bool operator[](unsigned I) const {
52     uint32_t Mask = uint32_t(1) << (I % 32);
53     return (Bits[I / 32] & Mask) != 0;
54   }
55 
operator &=(const FeatureBitset & RHS)56   constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58       // GCC <6.2 crashes if this is written in a single statement.
59       uint32_t NewBits = Bits[I] & RHS.Bits[I];
60       Bits[I] = NewBits;
61     }
62     return *this;
63   }
64 
operator |=(const FeatureBitset & RHS)65   constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
67       // GCC <6.2 crashes if this is written in a single statement.
68       uint32_t NewBits = Bits[I] | RHS.Bits[I];
69       Bits[I] = NewBits;
70     }
71     return *this;
72   }
73 
74   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator &(const FeatureBitset & RHS) const75   constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
76     FeatureBitset Result;
77     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78       Result.Bits[I] = Bits[I] & RHS.Bits[I];
79     return Result;
80   }
81 
82   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator |(const FeatureBitset & RHS) const83   constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
84     FeatureBitset Result;
85     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86       Result.Bits[I] = Bits[I] | RHS.Bits[I];
87     return Result;
88   }
89 
operator ~() const90   constexpr FeatureBitset operator~() const {
91     FeatureBitset Result;
92     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93       Result.Bits[I] = ~Bits[I];
94     return Result;
95   }
96 
operator !=(const FeatureBitset & RHS) const97   constexpr bool operator!=(const FeatureBitset &RHS) const {
98     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99       if (Bits[I] != RHS.Bits[I])
100         return true;
101     return false;
102   }
103 };
104 
105 struct ProcInfo {
106   StringLiteral Name;
107   X86::CPUKind Kind;
108   unsigned KeyFeature;
109   FeatureBitset Features;
110 };
111 
112 struct FeatureInfo {
113   StringLiteral Name;
114   FeatureBitset ImpliedFeatures;
115 };
116 
117 } // end anonymous namespace
118 
119 #define X86_FEATURE(ENUM, STRING)                                              \
120   constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121 #include "llvm/Support/X86TargetParser.def"
122 
123 // Pentium with MMX.
124 constexpr FeatureBitset FeaturesPentiumMMX =
125     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126 
127 // Pentium 2 and 3.
128 constexpr FeatureBitset FeaturesPentium2 =
129     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
130 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
131 
132 // Pentium 4 CPUs
133 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
134 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
135 constexpr FeatureBitset FeaturesNocona =
136     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
137 
138 // Basic 64-bit capable CPU.
139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
140 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141                                             FeaturePOPCNT | FeatureSSE4_2 |
142                                             FeatureCMPXCHG16B;
143 constexpr FeatureBitset FeaturesX86_64_V3 =
144     FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145     FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
146 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 |
147                                             FeatureAVX512BW | FeatureAVX512CD |
148                                             FeatureAVX512DQ | FeatureAVX512VL;
149 
150 // Intel Core CPUs
151 constexpr FeatureBitset FeaturesCore2 =
152     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
153 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
154 constexpr FeatureBitset FeaturesNehalem =
155     FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
156 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
157 constexpr FeatureBitset FeaturesSandyBridge =
158     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
159 constexpr FeatureBitset FeaturesIvyBridge =
160     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
161 constexpr FeatureBitset FeaturesHaswell =
162     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
164 constexpr FeatureBitset FeaturesBroadwell =
165     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166 
167 // Intel Knights Landing and Knights Mill
168 // Knights Landing has feature parity with Broadwell.
169 constexpr FeatureBitset FeaturesKNL =
170     FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171     FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
172 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
173 
174 // Intel Skylake processors.
175 constexpr FeatureBitset FeaturesSkylakeClient =
176     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177     FeatureXSAVES | FeatureSGX;
178 // SkylakeServer inherits all SkylakeClient features except SGX.
179 // FIXME: That doesn't match gcc.
180 constexpr FeatureBitset FeaturesSkylakeServer =
181     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183     FeaturePKU;
184 constexpr FeatureBitset FeaturesCascadeLake =
185     FeaturesSkylakeServer | FeatureAVX512VNNI;
186 constexpr FeatureBitset FeaturesCooperLake =
187     FeaturesCascadeLake | FeatureAVX512BF16;
188 
189 // Intel 10nm processors.
190 constexpr FeatureBitset FeaturesCannonlake =
191     FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192     FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193     FeaturePKU | FeatureSHA;
194 constexpr FeatureBitset FeaturesICLClient =
195     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
197     FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
198 constexpr FeatureBitset FeaturesICLServer =
199     FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
200 constexpr FeatureBitset FeaturesTigerlake =
201     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
202     FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
203 constexpr FeatureBitset FeaturesSapphireRapids =
204     FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
205     FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
206     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
207     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
208     FeatureWAITPKG | FeatureAVXVNNI;
209 constexpr FeatureBitset FeaturesAlderlake =
210     FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE |
211     FeatureSERIALIZE | FeatureWAITPKG | FeatureAVXVNNI;
212 
213 // Intel Atom processors.
214 // Bonnell has feature parity with Core2 and adds MOVBE.
215 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
216 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
217 constexpr FeatureBitset FeaturesSilvermont =
218     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
219 constexpr FeatureBitset FeaturesGoldmont =
220     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
221     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
222     FeatureXSAVEOPT | FeatureXSAVES;
223 constexpr FeatureBitset FeaturesGoldmontPlus =
224     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
225 constexpr FeatureBitset FeaturesTremont =
226     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
227 
228 // Geode Processor.
229 constexpr FeatureBitset FeaturesGeode =
230     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
231 
232 // K6 processor.
233 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
234 
235 // K7 and K8 architecture processors.
236 constexpr FeatureBitset FeaturesAthlon =
237     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
238 constexpr FeatureBitset FeaturesAthlonXP =
239     FeaturesAthlon | FeatureFXSR | FeatureSSE;
240 constexpr FeatureBitset FeaturesK8 =
241     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
242 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
243 constexpr FeatureBitset FeaturesAMDFAM10 =
244     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
245     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
246 
247 // Bobcat architecture processors.
248 constexpr FeatureBitset FeaturesBTVER1 =
249     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
250     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
251     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
252     FeatureSAHF;
253 constexpr FeatureBitset FeaturesBTVER2 =
254     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
255     FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
256 
257 // AMD Bulldozer architecture processors.
258 constexpr FeatureBitset FeaturesBDVER1 =
259     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
260     FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
261     FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
262     FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
263     FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
264 constexpr FeatureBitset FeaturesBDVER2 =
265     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
266 constexpr FeatureBitset FeaturesBDVER3 =
267     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
268 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
269                                          FeatureBMI2 | FeatureMOVBE |
270                                          FeatureMWAITX | FeatureRDRND;
271 
272 // AMD Zen architecture processors.
273 constexpr FeatureBitset FeaturesZNVER1 =
274     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
275     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
276     FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
277     FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
278     FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
279     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
280     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
281     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
282     FeatureXSAVEOPT | FeatureXSAVES;
283 constexpr FeatureBitset FeaturesZNVER2 =
284     FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
285 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
286                                                 FeatureINVPCID | FeaturePKU |
287                                                 FeatureVAES | FeatureVPCLMULQDQ;
288 
289 constexpr ProcInfo Processors[] = {
290   // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
291   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
292   // i386-generation processors.
293   { {"i386"}, CK_i386, ~0U, FeatureX87 },
294   // i486-generation processors.
295   { {"i486"}, CK_i486, ~0U, FeatureX87 },
296   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
297   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
298   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
299   // i586-generation processors, P5 microarchitecture based.
300   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
301   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
302   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
303   // i686-generation processors, P6 / Pentium M microarchitecture based.
304   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305   { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
306   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
307   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
308   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
309   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
310   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
311   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
312   // Netburst microarchitecture based processors.
313   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
314   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
315   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
316   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
317   // Core microarchitecture based processors.
318   { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
319   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
320   // Atom processors
321   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
322   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
323   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
324   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
325   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
326   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
327   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
328   // Nehalem microarchitecture based processors.
329   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
330   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
331   // Westmere microarchitecture based processors.
332   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
333   // Sandy Bridge microarchitecture based processors.
334   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
335   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
336   // Ivy Bridge microarchitecture based processors.
337   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
338   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
339   // Haswell microarchitecture based processors.
340   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
341   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
342   // Broadwell microarchitecture based processors.
343   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
344   // Skylake client microarchitecture based processors.
345   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
346   // Skylake server microarchitecture based processors.
347   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
348   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
349   // Cascadelake Server microarchitecture based processors.
350   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
351   // Cooperlake Server microarchitecture based processors.
352   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
353   // Cannonlake client microarchitecture based processors.
354   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
355   // Icelake client microarchitecture based processors.
356   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
357   // Icelake server microarchitecture based processors.
358   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
359   // Tigerlake microarchitecture based processors.
360   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
361   // Sapphire Rapids microarchitecture based processors.
362   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
363   // Alderlake microarchitecture based processors.
364   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
365   // Knights Landing processor.
366   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
367   // Knights Mill processor.
368   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
369   // Lakemont microarchitecture based processors.
370   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
371   // K6 architecture processors.
372   { {"k6"}, CK_K6, ~0U, FeaturesK6 },
373   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
374   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
375   // K7 architecture processors.
376   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
377   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
378   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
379   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
380   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
381   // K8 architecture processors.
382   { {"k8"}, CK_K8, ~0U, FeaturesK8 },
383   { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
384   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
385   { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
386   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
387   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
388   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
389   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
390   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
391   // Bobcat architecture processors.
392   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
393   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
394   // Bulldozer architecture processors.
395   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
396   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
397   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
398   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
399   // Zen architecture processors.
400   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
401   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
402   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
403   // Generic 64-bit processor.
404   { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
405   { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
406   { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
407   { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
408   // Geode processors.
409   { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
410 };
411 
412 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
413 
parseArchX86(StringRef CPU,bool Only64Bit)414 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
415   for (const auto &P : Processors)
416     if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
417       return P.Kind;
418 
419   return CK_None;
420 }
421 
parseTuneCPU(StringRef CPU,bool Only64Bit)422 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
423   if (llvm::is_contained(NoTuneList, CPU))
424     return CK_None;
425   return parseArchX86(CPU, Only64Bit);
426 }
427 
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)428 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
429                                      bool Only64Bit) {
430   for (const auto &P : Processors)
431     if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
432       Values.emplace_back(P.Name);
433 }
434 
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)435 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
436                                      bool Only64Bit) {
437   for (const ProcInfo &P : Processors)
438     if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
439         !llvm::is_contained(NoTuneList, P.Name))
440       Values.emplace_back(P.Name);
441 }
442 
getKeyFeature(X86::CPUKind Kind)443 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
444   // FIXME: Can we avoid a linear search here? The table might be sorted by
445   // CPUKind so we could binary search?
446   for (const auto &P : Processors) {
447     if (P.Kind == Kind) {
448       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
449       return static_cast<ProcessorFeatures>(P.KeyFeature);
450     }
451   }
452 
453   llvm_unreachable("Unable to find CPU kind!");
454 }
455 
456 // Features with no dependencies.
457 constexpr FeatureBitset ImpliedFeatures64BIT = {};
458 constexpr FeatureBitset ImpliedFeaturesADX = {};
459 constexpr FeatureBitset ImpliedFeaturesBMI = {};
460 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
461 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
462 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
463 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
464 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
465 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
466 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
467 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
468 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
469 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
470 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
471 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
472 constexpr FeatureBitset ImpliedFeaturesLWP = {};
473 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
474 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
475 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
476 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
477 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
478 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
479 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
480 constexpr FeatureBitset ImpliedFeaturesPKU = {};
481 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
482 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
483 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
484 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
485 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
486 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
487 constexpr FeatureBitset ImpliedFeaturesRTM = {};
488 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
489 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
490 constexpr FeatureBitset ImpliedFeaturesSGX = {};
491 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
492 constexpr FeatureBitset ImpliedFeaturesTBM = {};
493 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
494 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
495 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
496 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
497 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
498 constexpr FeatureBitset ImpliedFeaturesX87 = {};
499 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
500 
501 // Not really CPU features, but need to be in the table because clang uses
502 // target features to communicate them to the backend.
503 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
504 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
505 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
506 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
507 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
508 
509 // XSAVE features are dependent on basic XSAVE.
510 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
511 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
512 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
513 
514 // MMX->3DNOW->3DNOWA chain.
515 constexpr FeatureBitset ImpliedFeaturesMMX = {};
516 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
517 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
518 
519 // SSE/AVX/AVX512F chain.
520 constexpr FeatureBitset ImpliedFeaturesSSE = {};
521 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
522 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
523 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
524 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
525 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
526 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
527 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
528 constexpr FeatureBitset ImpliedFeaturesAVX512F =
529     FeatureAVX2 | FeatureF16C | FeatureFMA;
530 
531 // Vector extensions that build on SSE or AVX.
532 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
533 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
534 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
535 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
536 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
537 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
538 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
539 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
540 
541 // AVX512 features.
542 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
543 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
544 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
545 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
546 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
547 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
548 
549 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
550 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
551 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
552 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
553 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
554 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
555 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
556 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
557 
558 // FIXME: These two aren't really implemented and just exist in the feature
559 // list for __builtin_cpu_supports. So omit their dependencies.
560 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
561 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
562 
563 // SSE4_A->FMA4->XOP chain.
564 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
565 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
566 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
567 
568 // AMX Features
569 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
570 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
571 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
572 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
573 
574 // Key Locker Features
575 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
576 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
577 
578 // AVXVNNI Features
579 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
580 
581 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
582 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
583 #include "llvm/Support/X86TargetParser.def"
584 };
585 
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures)586 void llvm::X86::getFeaturesForCPU(StringRef CPU,
587                                   SmallVectorImpl<StringRef> &EnabledFeatures) {
588   auto I = llvm::find_if(Processors,
589                          [&](const ProcInfo &P) { return P.Name == CPU; });
590   assert(I != std::end(Processors) && "Processor not found!");
591 
592   FeatureBitset Bits = I->Features;
593 
594   // Remove the 64-bit feature which we only use to validate if a CPU can
595   // be used with 64-bit mode.
596   Bits &= ~Feature64BIT;
597 
598   // Add the string version of all set bits.
599   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
600     if (Bits[i] && !FeatureInfos[i].Name.empty())
601       EnabledFeatures.push_back(FeatureInfos[i].Name);
602 }
603 
604 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)605 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
606                                       const FeatureBitset &Implies) {
607   // Fast path: Implies is often empty.
608   if (!Implies.any())
609     return;
610   FeatureBitset Prev;
611   Bits |= Implies;
612   do {
613     Prev = Bits;
614     for (unsigned i = CPU_FEATURE_MAX; i;)
615       if (Bits[--i])
616         Bits |= FeatureInfos[i].ImpliedFeatures;
617   } while (Prev != Bits);
618 }
619 
620 /// Create bit vector of features that are implied disabled if the feature
621 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)622 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
623   // Check all features looking for any dependent on this feature. If we find
624   // one, mark it and recursively find any feature that depend on it.
625   FeatureBitset Prev;
626   Bits.set(Value);
627   do {
628     Prev = Bits;
629     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
630       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
631         Bits.set(i);
632   } while (Prev != Bits);
633 }
634 
updateImpliedFeatures(StringRef Feature,bool Enabled,StringMap<bool> & Features)635 void llvm::X86::updateImpliedFeatures(
636     StringRef Feature, bool Enabled,
637     StringMap<bool> &Features) {
638   auto I = llvm::find_if(
639       FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
640   if (I == std::end(FeatureInfos)) {
641     // FIXME: This shouldn't happen, but may not have all features in the table
642     // yet.
643     return;
644   }
645 
646   FeatureBitset ImpliedBits;
647   if (Enabled)
648     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
649   else
650     getImpliedDisabledFeatures(ImpliedBits,
651                                std::distance(std::begin(FeatureInfos), I));
652 
653   // Update the map entry for all implied features.
654   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
655     if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
656       Features[FeatureInfos[i].Name] = Enabled;
657 }
658