1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <lib/fconf/fconf.h>
15 #include <lib/fconf/fconf_dyn_cfg_getter.h>
16 #include <lib/utils.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <plat/arm/common/plat_arm.h>
19 #include <plat/common/platform.h>
20
21 /* Weak definitions may be overridden in specific ARM standard platform */
22 #pragma weak bl1_early_platform_setup
23 #pragma weak bl1_plat_arch_setup
24 #pragma weak bl1_plat_sec_mem_layout
25 #pragma weak bl1_plat_prepare_exit
26 #pragma weak bl1_plat_get_next_image_id
27 #pragma weak plat_arm_bl1_fwu_needed
28
29 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \
30 bl1_tzram_layout.total_base, \
31 bl1_tzram_layout.total_size, \
32 MT_MEMORY | MT_RW | MT_SECURE)
33 /*
34 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
35 * otherwise one region is defined containing both
36 */
37 #if SEPARATE_CODE_AND_RODATA
38 #define MAP_BL1_RO MAP_REGION_FLAT( \
39 BL_CODE_BASE, \
40 BL1_CODE_END - BL_CODE_BASE, \
41 MT_CODE | MT_SECURE), \
42 MAP_REGION_FLAT( \
43 BL1_RO_DATA_BASE, \
44 BL1_RO_DATA_END \
45 - BL_RO_DATA_BASE, \
46 MT_RO_DATA | MT_SECURE)
47 #else
48 #define MAP_BL1_RO MAP_REGION_FLAT( \
49 BL_CODE_BASE, \
50 BL1_CODE_END - BL_CODE_BASE, \
51 MT_CODE | MT_SECURE)
52 #endif
53
54 /* Data structure which holds the extents of the trusted SRAM for BL1*/
55 static meminfo_t bl1_tzram_layout;
56
57 /* Boolean variable to hold condition whether firmware update needed or not */
58 static bool is_fwu_needed;
59
bl1_plat_sec_mem_layout(void)60 struct meminfo *bl1_plat_sec_mem_layout(void)
61 {
62 return &bl1_tzram_layout;
63 }
64
65 /*******************************************************************************
66 * BL1 specific platform actions shared between ARM standard platforms.
67 ******************************************************************************/
arm_bl1_early_platform_setup(void)68 void arm_bl1_early_platform_setup(void)
69 {
70
71 #if !ARM_DISABLE_TRUSTED_WDOG
72 /* Enable watchdog */
73 plat_arm_secure_wdt_start();
74 #endif
75
76 /* Initialize the console to provide early debug support */
77 arm_console_boot_init();
78
79 /* Allow BL1 to see the whole Trusted RAM */
80 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
81 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
82 }
83
bl1_early_platform_setup(void)84 void bl1_early_platform_setup(void)
85 {
86 arm_bl1_early_platform_setup();
87
88 /*
89 * Initialize Interconnect for this cluster during cold boot.
90 * No need for locks as no other CPU is active.
91 */
92 plat_arm_interconnect_init();
93 /*
94 * Enable Interconnect coherency for the primary CPU's cluster.
95 */
96 plat_arm_interconnect_enter_coherency();
97 }
98
99 /******************************************************************************
100 * Perform the very early platform specific architecture setup shared between
101 * ARM standard platforms. This only does basic initialization. Later
102 * architectural setup (bl1_arch_setup()) does not do anything platform
103 * specific.
104 *****************************************************************************/
arm_bl1_plat_arch_setup(void)105 void arm_bl1_plat_arch_setup(void)
106 {
107 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
108 /*
109 * Ensure ARM platforms don't use coherent memory in BL1 unless
110 * cryptocell integration is enabled.
111 */
112 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
113 #endif
114
115 const mmap_region_t bl_regions[] = {
116 MAP_BL1_TOTAL,
117 MAP_BL1_RO,
118 #if USE_ROMLIB
119 ARM_MAP_ROMLIB_CODE,
120 ARM_MAP_ROMLIB_DATA,
121 #endif
122 #if ARM_CRYPTOCELL_INTEG
123 ARM_MAP_BL_COHERENT_RAM,
124 #endif
125 {0}
126 };
127
128 setup_page_tables(bl_regions, plat_arm_get_mmap());
129 #ifdef __aarch64__
130 enable_mmu_el3(0);
131 #else
132 enable_mmu_svc_mon(0);
133 #endif /* __aarch64__ */
134
135 arm_setup_romlib();
136 }
137
bl1_plat_arch_setup(void)138 void bl1_plat_arch_setup(void)
139 {
140 arm_bl1_plat_arch_setup();
141 }
142
143 /*
144 * Perform the platform specific architecture setup shared between
145 * ARM standard platforms.
146 */
arm_bl1_platform_setup(void)147 void arm_bl1_platform_setup(void)
148 {
149 const struct dyn_cfg_dtb_info_t *fw_config_info;
150 image_desc_t *desc;
151 uint32_t fw_config_max_size;
152 int err = -1;
153
154 /* Initialise the IO layer and register platform IO devices */
155 plat_arm_io_setup();
156
157 /* Check if we need FWU before further processing */
158 is_fwu_needed = plat_arm_bl1_fwu_needed();
159 if (is_fwu_needed) {
160 ERROR("Skip platform setup as FWU detected\n");
161 return;
162 }
163
164 /* Set global DTB info for fixed fw_config information */
165 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
166 set_config_info(ARM_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
167
168 /* Fill the device tree information struct with the info from the config dtb */
169 err = fconf_load_config(FW_CONFIG_ID);
170 if (err < 0) {
171 ERROR("Loading of FW_CONFIG failed %d\n", err);
172 plat_error_handler(err);
173 }
174
175 /*
176 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
177 * is successful then load TB_FW_CONFIG device tree.
178 */
179 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
180 if (fw_config_info != NULL) {
181 err = fconf_populate_dtb_registry(fw_config_info->config_addr);
182 if (err < 0) {
183 ERROR("Parsing of FW_CONFIG failed %d\n", err);
184 plat_error_handler(err);
185 }
186 /* load TB_FW_CONFIG */
187 err = fconf_load_config(TB_FW_CONFIG_ID);
188 if (err < 0) {
189 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
190 plat_error_handler(err);
191 }
192 } else {
193 ERROR("Invalid FW_CONFIG address\n");
194 plat_error_handler(err);
195 }
196
197 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
198 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
199 assert(desc != NULL);
200 desc->ep_info.args.arg0 = fw_config_info->config_addr;
201
202 #if TRUSTED_BOARD_BOOT
203 /* Share the Mbed TLS heap info with other images */
204 arm_bl1_set_mbedtls_heap();
205 #endif /* TRUSTED_BOARD_BOOT */
206
207 /*
208 * Allow access to the System counter timer module and program
209 * counter frequency for non secure images during FWU
210 */
211 #ifdef ARM_SYS_TIMCTL_BASE
212 arm_configure_sys_timer();
213 #endif
214 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
215 write_cntfrq_el0(plat_get_syscnt_freq2());
216 #endif
217 }
218
bl1_plat_prepare_exit(entry_point_info_t * ep_info)219 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
220 {
221 #if !ARM_DISABLE_TRUSTED_WDOG
222 /* Disable watchdog before leaving BL1 */
223 plat_arm_secure_wdt_stop();
224 #endif
225
226 #ifdef EL3_PAYLOAD_BASE
227 /*
228 * Program the EL3 payload's entry point address into the CPUs mailbox
229 * in order to release secondary CPUs from their holding pen and make
230 * them jump there.
231 */
232 plat_arm_program_trusted_mailbox(ep_info->pc);
233 dsbsy();
234 sev();
235 #endif
236 }
237
238 /*
239 * On Arm platforms, the FWU process is triggered when the FIP image has
240 * been tampered with.
241 */
plat_arm_bl1_fwu_needed(void)242 bool plat_arm_bl1_fwu_needed(void)
243 {
244 return !arm_io_is_toc_valid();
245 }
246
247 /*******************************************************************************
248 * The following function checks if Firmware update is needed,
249 * by checking if TOC in FIP image is valid or not.
250 ******************************************************************************/
bl1_plat_get_next_image_id(void)251 unsigned int bl1_plat_get_next_image_id(void)
252 {
253 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
254 }
255