1 // DriConf options supported by all Gallium DRI drivers.
2 DRI_CONF_SECTION_PERFORMANCE
3    DRI_CONF_MESA_GLTHREAD(false)
4    DRI_CONF_MESA_NO_ERROR(false)
5    DRI_CONF_DISABLE_EXT_BUFFER_AGE(false)
6    DRI_CONF_DISABLE_OML_SYNC_CONTROL(false)
7    DRI_CONF_DISABLE_SGI_VIDEO_SYNC(false)
8 DRI_CONF_SECTION_END
9 
10 DRI_CONF_SECTION_QUALITY
11    DRI_CONF_PP_CELSHADE(0)
12    DRI_CONF_PP_NORED(0)
13    DRI_CONF_PP_NOGREEN(0)
14    DRI_CONF_PP_NOBLUE(0)
15    DRI_CONF_PP_JIMENEZMLAA(0, 0, 32)
16    DRI_CONF_PP_JIMENEZMLAA_COLOR(0, 0, 32)
17 DRI_CONF_SECTION_END
18 
19 DRI_CONF_SECTION_DEBUG
20    DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(false)
21    DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS(false)
22    DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED(false)
23    DRI_CONF_DISABLE_ARB_GPU_SHADER5(false)
24    DRI_CONF_FORCE_GLSL_VERSION(0)
25    DRI_CONF_ALLOW_EXTRA_PP_TOKENS(false)
26    DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER(false)
27    DRI_CONF_ALLOW_GLSL_120_SUBSET_IN_110(false)
28    DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION(false)
29    DRI_CONF_ALLOW_GLSL_RELAXED_ES(false)
30    DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION(false)
31    DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH(false)
32    DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(false)
33    DRI_CONF_FORCE_GLSL_ABS_SQRT(false)
34    DRI_CONF_GLSL_CORRECT_DERIVATIVES_AFTER_DISCARD(false)
35    DRI_CONF_ALLOW_DRAW_OUT_OF_ORDER(false)
36    DRI_CONF_FORCE_COMPAT_PROFILE(false)
37    DRI_CONF_FORCE_GL_NAMES_REUSE(false)
38    DRI_CONF_FORCE_GL_VENDOR()
39    DRI_CONF_OVERRIDE_VRAM_SIZE()
40    DRI_CONF_GLX_EXTENSION_OVERRIDE()
41    DRI_CONF_INDIRECT_GL_EXTENSION_OVERRIDE()
42    DRI_CONF_DISABLE_PROTECTED_CONTENT_CHECK(false)
43 DRI_CONF_SECTION_END
44 
45 DRI_CONF_SECTION_MISCELLANEOUS
46    DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER(false)
47    DRI_CONF_GLSL_ZERO_INIT(false)
48    DRI_CONF_VS_POSITION_ALWAYS_INVARIANT(false)
49    DRI_CONF_ALLOW_RGB10_CONFIGS(true)
50    DRI_CONF_ALLOW_FP16_CONFIGS(false)
51    DRI_CONF_FORCE_INTEGER_TEX_NEAREST(false)
52 DRI_CONF_SECTION_END
53