1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=armv8-eabi -mattr=+fullfp16 | FileCheck %s
3; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 | FileCheck %s
4
5define half @fp16_vminnm_o(half %a, half %b) {
6; CHECK-LABEL: fp16_vminnm_o:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    vmov.f16 s0, r1
9; CHECK-NEXT:    vmov.f16 s2, r0
10; CHECK-NEXT:    vcmp.f16 s0, s2
11; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
12; CHECK-NEXT:    vselgt.f16 s0, s2, s0
13; CHECK-NEXT:    vmov r0, s0
14; CHECK-NEXT:    bx lr
15entry:
16  %cmp = fcmp olt half %a, %b
17  %cond = select i1 %cmp, half %a, half %b
18  ret half %cond
19}
20
21define half @fp16_vminnm_o_rev(half %a, half %b) {
22; CHECK-LABEL: fp16_vminnm_o_rev:
23; CHECK:       @ %bb.0: @ %entry
24; CHECK-NEXT:    vmov.f16 s0, r1
25; CHECK-NEXT:    vmov.f16 s2, r0
26; CHECK-NEXT:    vcmp.f16 s2, s0
27; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
28; CHECK-NEXT:    vselgt.f16 s0, s2, s0
29; CHECK-NEXT:    vmov r0, s0
30; CHECK-NEXT:    bx lr
31entry:
32  %cmp = fcmp ogt half %a, %b
33  %cond = select i1 %cmp, half %a, half %b
34  ret half %cond
35}
36
37define half @fp16_vminnm_u(half %a, half %b) {
38; CHECK-LABEL: fp16_vminnm_u:
39; CHECK:       @ %bb.0: @ %entry
40; CHECK-NEXT:    vmov.f16 s0, r0
41; CHECK-NEXT:    vmov.f16 s2, r1
42; CHECK-NEXT:    vcmp.f16 s0, s2
43; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
44; CHECK-NEXT:    vselge.f16 s0, s2, s0
45; CHECK-NEXT:    vmov r0, s0
46; CHECK-NEXT:    bx lr
47entry:
48  %cmp = fcmp ult half %a, %b
49  %cond = select i1 %cmp, half %a, half %b
50  ret half %cond
51}
52
53define half @fp16_vminnm_ule(half %a, half %b) {
54; CHECK-LABEL: fp16_vminnm_ule:
55; CHECK:       @ %bb.0: @ %entry
56; CHECK-NEXT:    vmov.f16 s0, r0
57; CHECK-NEXT:    vmov.f16 s2, r1
58; CHECK-NEXT:    vcmp.f16 s0, s2
59; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
60; CHECK-NEXT:    vselgt.f16 s0, s2, s0
61; CHECK-NEXT:    vmov r0, s0
62; CHECK-NEXT:    bx lr
63entry:
64  %cmp = fcmp ule half %a, %b
65  %cond = select i1 %cmp, half %a, half %b
66  ret half %cond
67}
68
69define half @fp16_vminnm_u_rev(half %a, half %b) {
70; CHECK-LABEL: fp16_vminnm_u_rev:
71; CHECK:       @ %bb.0: @ %entry
72; CHECK-NEXT:    vmov.f16 s0, r1
73; CHECK-NEXT:    vmov.f16 s2, r0
74; CHECK-NEXT:    vcmp.f16 s0, s2
75; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
76; CHECK-NEXT:    vselge.f16 s0, s2, s0
77; CHECK-NEXT:    vmov r0, s0
78; CHECK-NEXT:    bx lr
79entry:
80  %cmp = fcmp ugt half %a, %b
81  %cond = select i1 %cmp, half %b, half %a
82  ret half %cond
83}
84
85define half @fp16_vmaxnm_o(half %a, half %b) {
86; CHECK-LABEL: fp16_vmaxnm_o:
87; CHECK:       @ %bb.0: @ %entry
88; CHECK-NEXT:    vmov.f16 s0, r1
89; CHECK-NEXT:    vmov.f16 s2, r0
90; CHECK-NEXT:    vcmp.f16 s2, s0
91; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
92; CHECK-NEXT:    vselgt.f16 s0, s2, s0
93; CHECK-NEXT:    vmov r0, s0
94; CHECK-NEXT:    bx lr
95entry:
96  %cmp = fcmp ogt half %a, %b
97  %cond = select i1 %cmp, half %a, half %b
98  ret half %cond
99}
100
101define half @fp16_vmaxnm_oge(half %a, half %b) {
102; CHECK-LABEL: fp16_vmaxnm_oge:
103; CHECK:       @ %bb.0: @ %entry
104; CHECK-NEXT:    vmov.f16 s0, r1
105; CHECK-NEXT:    vmov.f16 s2, r0
106; CHECK-NEXT:    vcmp.f16 s2, s0
107; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
108; CHECK-NEXT:    vselge.f16 s0, s2, s0
109; CHECK-NEXT:    vmov r0, s0
110; CHECK-NEXT:    bx lr
111entry:
112  %cmp = fcmp oge half %a, %b
113  %cond = select i1 %cmp, half %a, half %b
114  ret half %cond
115}
116
117define half @fp16_vmaxnm_o_rev(half %a, half %b) {
118; CHECK-LABEL: fp16_vmaxnm_o_rev:
119; CHECK:       @ %bb.0: @ %entry
120; CHECK-NEXT:    vmov.f16 s0, r0
121; CHECK-NEXT:    vmov.f16 s2, r1
122; CHECK-NEXT:    vcmp.f16 s2, s0
123; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
124; CHECK-NEXT:    vselgt.f16 s0, s2, s0
125; CHECK-NEXT:    vmov r0, s0
126; CHECK-NEXT:    bx lr
127entry:
128  %cmp = fcmp olt half %a, %b
129  %cond = select i1 %cmp, half %b, half %a
130  ret half %cond
131}
132
133define half @fp16_vmaxnm_ole_rev(half %a, half %b) {
134; CHECK-LABEL: fp16_vmaxnm_ole_rev:
135; CHECK:       @ %bb.0: @ %entry
136; CHECK-NEXT:    vmov.f16 s0, r0
137; CHECK-NEXT:    vmov.f16 s2, r1
138; CHECK-NEXT:    vcmp.f16 s2, s0
139; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
140; CHECK-NEXT:    vselge.f16 s0, s2, s0
141; CHECK-NEXT:    vmov r0, s0
142; CHECK-NEXT:    bx lr
143entry:
144  %cmp = fcmp ole half %a, %b
145  %cond = select i1 %cmp, half %b, half %a
146  ret half %cond
147}
148
149define half @fp16_vmaxnm_u(half %a, half %b) {
150; CHECK-LABEL: fp16_vmaxnm_u:
151; CHECK:       @ %bb.0: @ %entry
152; CHECK-NEXT:    vmov.f16 s0, r0
153; CHECK-NEXT:    vmov.f16 s2, r1
154; CHECK-NEXT:    vcmp.f16 s2, s0
155; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
156; CHECK-NEXT:    vselge.f16 s0, s2, s0
157; CHECK-NEXT:    vmov r0, s0
158; CHECK-NEXT:    bx lr
159entry:
160  %cmp = fcmp ugt half %a, %b
161  %cond = select i1 %cmp, half %a, half %b
162  ret half %cond
163}
164
165define half @fp16_vmaxnm_uge(half %a, half %b) {
166; CHECK-LABEL: fp16_vmaxnm_uge:
167; CHECK:       @ %bb.0: @ %entry
168; CHECK-NEXT:    vmov.f16 s0, r0
169; CHECK-NEXT:    vmov.f16 s2, r1
170; CHECK-NEXT:    vcmp.f16 s2, s0
171; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
172; CHECK-NEXT:    vselgt.f16 s0, s2, s0
173; CHECK-NEXT:    vmov r0, s0
174; CHECK-NEXT:    bx lr
175entry:
176  %cmp = fcmp uge half %a, %b
177  %cond = select i1 %cmp, half %a, half %b
178  ret half %cond
179}
180
181define half @fp16_vmaxnm_u_rev(half %a, half %b) {
182; CHECK-LABEL: fp16_vmaxnm_u_rev:
183; CHECK:       @ %bb.0: @ %entry
184; CHECK-NEXT:    vmov.f16 s0, r1
185; CHECK-NEXT:    vmov.f16 s2, r0
186; CHECK-NEXT:    vcmp.f16 s2, s0
187; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
188; CHECK-NEXT:    vselge.f16 s0, s2, s0
189; CHECK-NEXT:    vmov r0, s0
190; CHECK-NEXT:    bx lr
191entry:
192  %cmp = fcmp ult half %a, %b
193  %cond = select i1 %cmp, half %b, half %a
194  ret half %cond
195}
196
197; known non-NaNs
198
199define half @fp16_vminnm_NNNo(half %a) {
200; CHECK-LABEL: fp16_vminnm_NNNo:
201; CHECK:       @ %bb.0: @ %entry
202; CHECK-NEXT:    vmov.f16 s0, r0
203; CHECK-NEXT:    vmov.f16 s2, #1.200000e+01
204; CHECK-NEXT:    vminnm.f16 s0, s0, s2
205; CHECK-NEXT:    vldr.16 s2, .LCPI12_0
206; CHECK-NEXT:    vcmp.f16 s0, s2
207; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
208; CHECK-NEXT:    vselgt.f16 s0, s2, s0
209; CHECK-NEXT:    vmov r0, s0
210; CHECK-NEXT:    bx lr
211; CHECK-NEXT:    .p2align 1
212; CHECK-NEXT:  @ %bb.1:
213; CHECK-NEXT:  .LCPI12_0:
214; CHECK-NEXT:    .short 0x5040 @ half 34
215entry:
216  %cmp1 = fcmp olt half %a, 12.
217  %cond1 = select i1 %cmp1, half %a, half 12.
218  %cmp2 = fcmp olt half 34., %cond1
219  %cond2 = select i1 %cmp2, half 34., half %cond1
220  ret half %cond2
221}
222
223define half @fp16_vminnm_NNNo_rev(half %a) {
224; CHECK-LABEL: fp16_vminnm_NNNo_rev:
225; CHECK:       @ %bb.0: @ %entry
226; CHECK-NEXT:    vldr.16 s2, .LCPI13_0
227; CHECK-NEXT:    vmov.f16 s0, r0
228; CHECK-NEXT:    vcmp.f16 s0, s2
229; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
230; CHECK-NEXT:    vselgt.f16 s0, s2, s0
231; CHECK-NEXT:    vldr.16 s2, .LCPI13_1
232; CHECK-NEXT:    vminnm.f16 s0, s0, s2
233; CHECK-NEXT:    vmov r0, s0
234; CHECK-NEXT:    bx lr
235; CHECK-NEXT:    .p2align 1
236; CHECK-NEXT:  @ %bb.1:
237; CHECK-NEXT:  .LCPI13_0:
238; CHECK-NEXT:    .short 0x5300 @ half 56
239; CHECK-NEXT:  .LCPI13_1:
240; CHECK-NEXT:    .short 0x54e0 @ half 78
241entry:
242  %cmp1 = fcmp ogt half %a, 56.
243  %cond1 = select i1 %cmp1, half 56., half %a
244  %cmp2 = fcmp ogt half 78., %cond1
245  %cond2 = select i1 %cmp2, half %cond1, half 78.
246  ret half %cond2
247}
248
249define half @fp16_vminnm_NNNu(half %b) {
250; CHECK-LABEL: fp16_vminnm_NNNu:
251; CHECK:       @ %bb.0: @ %entry
252; CHECK-NEXT:    vmov.f16 s0, r0
253; CHECK-NEXT:    vmov.f16 s2, #1.200000e+01
254; CHECK-NEXT:    vminnm.f16 s0, s0, s2
255; CHECK-NEXT:    vldr.16 s2, .LCPI14_0
256; CHECK-NEXT:    vcmp.f16 s0, s2
257; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
258; CHECK-NEXT:    vselge.f16 s0, s2, s0
259; CHECK-NEXT:    vmov r0, s0
260; CHECK-NEXT:    bx lr
261; CHECK-NEXT:    .p2align 1
262; CHECK-NEXT:  @ %bb.1:
263; CHECK-NEXT:  .LCPI14_0:
264; CHECK-NEXT:    .short 0x5040 @ half 34
265entry:
266  %cmp1 = fcmp ult half 12., %b
267  %cond1 = select i1 %cmp1, half 12., half %b
268  %cmp2 = fcmp ult half %cond1, 34.
269  %cond2 = select i1 %cmp2, half %cond1, half 34.
270  ret half %cond2
271}
272
273define half @fp16_vminnm_NNNule(half %b) {
274; CHECK-LABEL: fp16_vminnm_NNNule:
275; CHECK:       @ %bb.0: @ %entry
276; CHECK-NEXT:    vldr.16 s2, .LCPI15_0
277; CHECK-NEXT:    vmov.f16 s0, r0
278; CHECK-NEXT:    vminnm.f16 s0, s0, s2
279; CHECK-NEXT:    vldr.16 s2, .LCPI15_1
280; CHECK-NEXT:    vcmp.f16 s0, s2
281; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
282; CHECK-NEXT:    vselgt.f16 s0, s2, s0
283; CHECK-NEXT:    vmov r0, s0
284; CHECK-NEXT:    bx lr
285; CHECK-NEXT:    .p2align 1
286; CHECK-NEXT:  @ %bb.1:
287; CHECK-NEXT:  .LCPI15_0:
288; CHECK-NEXT:    .short 0x5040 @ half 34
289; CHECK-NEXT:  .LCPI15_1:
290; CHECK-NEXT:    .short 0x5300 @ half 56
291
292entry:
293  %cmp1 = fcmp ule half 34., %b
294  %cond1 = select i1 %cmp1, half 34., half %b
295  %cmp2 = fcmp ule half %cond1, 56.
296  %cond2 = select i1 %cmp2, half %cond1, half 56.
297  ret half %cond2
298}
299
300define half @fp16_vminnm_NNNu_rev(half %b) {
301; CHECK-LABEL: fp16_vminnm_NNNu_rev:
302; CHECK:       @ %bb.0: @ %entry
303; CHECK-NEXT:    vldr.16 s2, .LCPI16_0
304; CHECK-NEXT:    vmov.f16 s0, r0
305; CHECK-NEXT:    vcmp.f16 s0, s2
306; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
307; CHECK-NEXT:    vselge.f16 s0, s2, s0
308; CHECK-NEXT:    vldr.16 s2, .LCPI16_1
309; CHECK-NEXT:    vminnm.f16 s0, s0, s2
310; CHECK-NEXT:    vmov r0, s0
311; CHECK-NEXT:    bx lr
312; CHECK-NEXT:    .p2align 1
313; CHECK-NEXT:  @ %bb.1:
314; CHECK-NEXT:  .LCPI16_0:
315; CHECK-NEXT:    .short 0x5300 @ half 56
316; CHECK-NEXT:  .LCPI16_1:
317; CHECK-NEXT:    .short 0x54e0 @ half 78
318
319
320entry:
321  %cmp1 = fcmp ugt half 56., %b
322  %cond1 = select i1 %cmp1, half %b, half 56.
323  %cmp2 = fcmp ugt half %cond1, 78.
324  %cond2 = select i1 %cmp2, half 78., half %cond1
325  ret half %cond2
326}
327
328define half @fp16_vmaxnm_NNNo(half %a) {
329; CHECK-LABEL: fp16_vmaxnm_NNNo:
330; CHECK:       @ %bb.0: @ %entry
331; CHECK-NEXT:    vmov.f16 s0, r0
332; CHECK-NEXT:    vmov.f16 s2, #1.200000e+01
333; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
334; CHECK-NEXT:    vldr.16 s2, .LCPI17_0
335; CHECK-NEXT:    vcmp.f16 s2, s0
336; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
337; CHECK-NEXT:    vselgt.f16 s0, s2, s0
338; CHECK-NEXT:    vmov r0, s0
339; CHECK-NEXT:    bx lr
340; CHECK-NEXT:    .p2align 1
341; CHECK-NEXT:  @ %bb.1:
342; CHECK-NEXT:  .LCPI17_0:
343; CHECK-NEXT:    .short 0x5040 @ half 34
344entry:
345  %cmp1 = fcmp ogt half %a, 12.
346  %cond1 = select i1 %cmp1, half %a, half 12.
347  %cmp2 = fcmp ogt half 34., %cond1
348  %cond2 = select i1 %cmp2, half 34., half %cond1
349  ret half %cond2
350}
351
352define half @fp16_vmaxnm_NNNoge(half %a) {
353; CHECK-LABEL: fp16_vmaxnm_NNNoge:
354; CHECK:       @ %bb.0: @ %entry
355; CHECK-NEXT:    vldr.16 s2, .LCPI18_0
356; CHECK-NEXT:    vmov.f16 s0, r0
357; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
358; CHECK-NEXT:    vldr.16 s2, .LCPI18_1
359; CHECK-NEXT:    vcmp.f16 s2, s0
360; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
361; CHECK-NEXT:    vselge.f16 s0, s2, s0
362; CHECK-NEXT:    vmov r0, s0
363; CHECK-NEXT:    bx lr
364; CHECK-NEXT:    .p2align 1
365; CHECK-NEXT:  @ %bb.1:
366; CHECK-NEXT:  .LCPI18_0:
367; CHECK-NEXT:    .short 0x5040 @ half 34
368; CHECK-NEXT:  .LCPI18_1:
369; CHECK-NEXT:    .short 0x5300 @ half 56
370entry:
371  %cmp1 = fcmp oge half %a, 34.
372  %cond1 = select i1 %cmp1, half %a, half 34.
373  %cmp2 = fcmp oge half 56., %cond1
374  %cond2 = select i1 %cmp2, half 56., half %cond1
375  ret half %cond2
376}
377
378define half @fp16_vmaxnm_NNNo_rev(half %a) {
379; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:
380; CHECK:       @ %bb.0: @ %entry
381; CHECK-NEXT:    vldr.16 s2, .LCPI19_0
382; CHECK-NEXT:    vmov.f16 s0, r0
383; CHECK-NEXT:    vcmp.f16 s2, s0
384; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
385; CHECK-NEXT:    vselgt.f16 s0, s2, s0
386; CHECK-NEXT:    vldr.16 s2, .LCPI19_1
387; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
388; CHECK-NEXT:    vmov r0, s0
389; CHECK-NEXT:    bx lr
390; CHECK-NEXT:    .p2align 1
391; CHECK-NEXT:  @ %bb.1:
392; CHECK-NEXT:  .LCPI19_0:
393; CHECK-NEXT:    .short 0x5300 @ half 56
394; CHECK-NEXT:  .LCPI19_1:
395; CHECK-NEXT:    .short 0x54e0 @ half 78
396entry:
397  %cmp1 = fcmp olt half %a, 56.
398  %cond1 = select i1 %cmp1, half 56., half %a
399  %cmp2 = fcmp olt half 78., %cond1
400  %cond2 = select i1 %cmp2, half %cond1, half 78.
401  ret half %cond2
402}
403
404define half @fp16_vmaxnm_NNNole_rev(half %a) {
405; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:
406; CHECK:       @ %bb.0: @ %entry
407; CHECK-NEXT:    vldr.16 s2, .LCPI20_0
408; CHECK-NEXT:    vmov.f16 s0, r0
409; CHECK-NEXT:    vcmp.f16 s2, s0
410; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
411; CHECK-NEXT:    vselge.f16 s0, s2, s0
412; CHECK-NEXT:    vldr.16 s2, .LCPI20_1
413; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
414; CHECK-NEXT:    vmov r0, s0
415; CHECK-NEXT:    bx lr
416; CHECK-NEXT:    .p2align 1
417; CHECK-NEXT:  @ %bb.1:
418; CHECK-NEXT:  .LCPI20_0:
419; CHECK-NEXT:    .short 0x54e0 @ half 78
420; CHECK-NEXT:  .LCPI20_1:
421; CHECK-NEXT:    .short 0x55a0 @ half 90
422entry:
423  %cmp1 = fcmp ole half %a, 78.
424  %cond1 = select i1 %cmp1, half 78., half %a
425  %cmp2 = fcmp ole half 90., %cond1
426  %cond2 = select i1 %cmp2, half %cond1, half 90.
427  ret half %cond2
428}
429
430define half @fp16_vmaxnm_NNNu(half %b) {
431; CHECK-LABEL: fp16_vmaxnm_NNNu:
432; CHECK:       @ %bb.0: @ %entry
433; CHECK-NEXT:    vmov.f16 s0, r0
434; CHECK-NEXT:    vmov.f16 s2, #1.200000e+01
435; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
436; CHECK-NEXT:    vldr.16 s2, .LCPI21_0
437; CHECK-NEXT:    vcmp.f16 s2, s0
438; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
439; CHECK-NEXT:    vselge.f16 s0, s2, s0
440; CHECK-NEXT:    vmov r0, s0
441; CHECK-NEXT:    bx lr
442; CHECK-NEXT:    .p2align 1
443; CHECK-NEXT:  @ %bb.1:
444; CHECK-NEXT:  .LCPI21_0:
445; CHECK-NEXT:    .short 0x5040 @ half 34
446entry:
447  %cmp1 = fcmp ugt half 12., %b
448  %cond1 = select i1 %cmp1, half 12., half %b
449  %cmp2 = fcmp ugt half %cond1, 34.
450  %cond2 = select i1 %cmp2, half %cond1, half 34.
451  ret half %cond2
452}
453
454define half @fp16_vmaxnm_NNNuge(half %b) {
455; CHECK-LABEL: fp16_vmaxnm_NNNuge:
456; CHECK:       @ %bb.0: @ %entry
457; CHECK-NEXT:    vldr.16 s2, .LCPI22_0
458; CHECK-NEXT:    vmov.f16 s0, r0
459; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
460; CHECK-NEXT:    vldr.16 s2, .LCPI22_1
461; CHECK-NEXT:    vcmp.f16 s2, s0
462; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
463; CHECK-NEXT:    vselgt.f16 s0, s2, s0
464; CHECK-NEXT:    vmov r0, s0
465; CHECK-NEXT:    bx lr
466; CHECK-NEXT:    .p2align 1
467; CHECK-NEXT:  @ %bb.1:
468; CHECK-NEXT:  .LCPI22_0:
469; CHECK-NEXT:    .short 0x5040 @ half 34
470; CHECK-NEXT:  .LCPI22_1:
471; CHECK-NEXT:    .short 0x5300 @ half 56
472entry:
473  %cmp1 = fcmp uge half 34., %b
474  %cond1 = select i1 %cmp1, half 34., half %b
475  %cmp2 = fcmp uge half %cond1, 56.
476  %cond2 = select i1 %cmp2, half %cond1, half 56.
477  ret half %cond2
478}
479
480define half @fp16_vminmaxnm_neg0(half %a) {
481; CHECK-LABEL: fp16_vminmaxnm_neg0:
482; CHECK:       @ %bb.0: @ %entry
483; CHECK-NEXT:    vldr.16 s0, .LCPI23_0
484; CHECK-NEXT:    vmov.f16 s2, r0
485; CHECK-NEXT:    vminnm.f16 s2, s2, s0
486; CHECK-NEXT:    vcmp.f16 s0, s2
487; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
488; CHECK-NEXT:    vselge.f16 s0, s0, s2
489; CHECK-NEXT:    vmov r0, s0
490; CHECK-NEXT:    bx lr
491; CHECK-NEXT:    .p2align 1
492; CHECK-NEXT:  @ %bb.1:
493; CHECK-NEXT:  .LCPI23_0:
494; CHECK-NEXT:    .short 0x8000 @ half -0
495entry:
496  %cmp1 = fcmp olt half %a, -0.
497  %cond1 = select i1 %cmp1, half %a, half -0.
498  %cmp2 = fcmp ugt half %cond1, -0.
499  %cond2 = select i1 %cmp2, half %cond1, half -0.
500  ret half %cond2
501}
502
503define half @fp16_vminmaxnm_e_0(half %a) {
504; CHECK-LABEL: fp16_vminmaxnm_e_0:
505; CHECK:       @ %bb.0: @ %entry
506; CHECK-NEXT:    vmov.f16 s0, r0
507; CHECK-NEXT:    vldr.16 s2, .LCPI24_0
508; CHECK-NEXT:    vcmp.f16 s0, #0
509; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
510; CHECK-NEXT:    vselge.f16 s0, s2, s0
511; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
512; CHECK-NEXT:    vmov r0, s0
513; CHECK-NEXT:    bx lr
514; CHECK-NEXT:    .p2align 1
515; CHECK-NEXT:  @ %bb.1:
516; CHECK-NEXT:  .LCPI24_0:
517; CHECK-NEXT:    .short 0x0000 @ half 0
518entry:
519  %cmp1 = fcmp nsz ole half 0., %a
520  %cond1 = select i1 %cmp1, half 0., half %a
521  %cmp2 = fcmp nsz uge half 0., %cond1
522  %cond2 = select i1 %cmp2, half 0., half %cond1
523  ret half %cond2
524}
525
526define half @fp16_vminmaxnm_e_neg0(half %a) {
527; CHECK-LABEL: fp16_vminmaxnm_e_neg0:
528; CHECK:       @ %bb.0: @ %entry
529; CHECK-NEXT:    vldr.16 s0, .LCPI25_0
530; CHECK-NEXT:    vmov.f16 s2, r0
531; CHECK-NEXT:    vminnm.f16 s2, s2, s0
532; CHECK-NEXT:    vcmp.f16 s0, s2
533; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
534; CHECK-NEXT:    vselge.f16 s0, s0, s2
535; CHECK-NEXT:    vmov r0, s0
536; CHECK-NEXT:    bx lr
537; CHECK-NEXT:    .p2align 1
538; CHECK-NEXT:  @ %bb.1:
539; CHECK-NEXT:  .LCPI25_0:
540; CHECK-NEXT:    .short 0x8000 @ half -0
541entry:
542  %cmp1 = fcmp nsz ule half -0., %a
543  %cond1 = select i1 %cmp1, half -0., half %a
544  %cmp2 = fcmp nsz oge half -0., %cond1
545  %cond2 = select i1 %cmp2, half -0., half %cond1
546  ret half %cond2
547}
548