1 #ifndef GEN9_RENDER_H
2 #define GEN9_RENDER_H
3 
4 #include "gen8_render.h"
5 
6 #define GEN9_3DSTATE_COMPONENT_PACKING		GEN4_3D(3, 0, 0x55)
7 
8 #define GEN9_SBE_ACTIVE_COMPONENT_NONE		0
9 #define GEN9_SBE_ACTIVE_COMPONENT_XY		1
10 #define GEN9_SBE_ACTIVE_COMPONENT_XYZ		2
11 #define GEN9_SBE_ACTIVE_COMPONENT_XYZW		3
12 
13 #define GEN9_PIPELINE_SELECTION_MASK		(3 << 8)
14 #define GEN9_PIPELINE_SELECT			(GEN4_3D(1, 1, 4) | (3 << 8))
15 
16 #define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16	(4 << 1)
17 
18 /* Shamelessly ripped from mesa */
19 struct gen9_surface_state {
20 	struct {
21 		uint32_t cube_pos_z:1;
22 		uint32_t cube_neg_z:1;
23 		uint32_t cube_pos_y:1;
24 		uint32_t cube_neg_y:1;
25 		uint32_t cube_pos_x:1;
26 		uint32_t cube_neg_x:1;
27 		uint32_t media_boundary_pixel_mode:2;
28 		uint32_t render_cache_read_write:1;
29 		uint32_t smapler_l2_bypass:1;
30 		uint32_t vert_line_stride_ofs:1;
31 		uint32_t vert_line_stride:1;
32 		uint32_t tiled_mode:2;
33 		uint32_t horizontal_alignment:2;
34 		uint32_t vertical_alignment:2;
35 		uint32_t surface_format:9;     /**< BRW_SURFACEFORMAT_x */
36 		uint32_t pad0:1;
37 		uint32_t is_array:1;
38 		uint32_t surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
39 	} ss0;
40 
41 	struct {
42 		uint32_t qpitch:15;
43 		uint32_t pad1:4;
44 		uint32_t base_mip_level:5;
45 		uint32_t memory_object_control:7;
46 		uint32_t pad0:1;
47 	} ss1;
48 
49 	struct {
50 		uint32_t width:14;
51 		uint32_t pad1:2;
52 		uint32_t height:14;
53 		uint32_t pad0:2;
54 	} ss2;
55 
56 	struct {
57 		uint32_t pitch:18;
58 		uint32_t pad:3;
59 		uint32_t depth:11;
60 	} ss3;
61 
62 	struct {
63 		uint32_t minimum_array_element:27;
64 		uint32_t pad0:5;
65 	} ss4;
66 
67 	struct {
68 		uint32_t mip_count:4;
69 		uint32_t min_lod:4;
70 		uint32_t mip_tail_start_lod:4;
71 		uint32_t pad3:2;
72 		uint32_t coherency_type:1;
73 		uint32_t pad2:3;
74 		uint32_t trmode:2;
75 		uint32_t ewa_disable_for_cube:1;
76 		uint32_t y_offset:3;
77 		uint32_t pad0:1;
78 		uint32_t x_offset:7;
79 	} ss5;
80 
81 	struct {
82 		uint32_t aux_mode:3;
83 		uint32_t aux_pitch:9;
84 		uint32_t pad0:4;
85 		uint32_t aux_qpitch:15;
86 		uint32_t pad1:1;
87 	} ss6;
88 
89 	struct {
90 		uint32_t resource_min_lod:12;
91 
92 		/* Only on Haswell */
93 		uint32_t pad0:4;
94 		uint32_t shader_chanel_select_a:3;
95 		uint32_t shader_chanel_select_b:3;
96 		uint32_t shader_chanel_select_g:3;
97 		uint32_t shader_chanel_select_r:3;
98 
99 		uint32_t alpha_clear_color:1;
100 		uint32_t blue_clear_color:1;
101 		uint32_t green_clear_color:1;
102 		uint32_t red_clear_color:1;
103 	} ss7;
104 
105 	struct {
106 		uint32_t base_addr;
107 	} ss8;
108 
109 	struct {
110 		uint32_t base_addr_hi;
111 	} ss9;
112 
113 	struct {
114 		uint32_t aux_base_addr;
115 	} ss10;
116 
117 	struct {
118 		uint32_t aux_base_addr_hi;
119 	} ss11;
120 
121 	struct {
122 		uint32_t hiz_depth_clear_value;
123 	} ss12;
124 
125 	struct {
126 		uint32_t reserved;
127 	} ss13;
128 
129 	struct {
130 		uint32_t reserved;
131 	} ss14;
132 
133 	struct {
134 		uint32_t reserved;
135 	} ss15;
136 };
137 
138 #endif
139